de0_cv_nes/mos6502.vhd

   1 library ieee;\r
   2 use ieee.std_logic_1164.all;\r
   3 use ieee.std_logic_unsigned.all;\r
   4 use ieee.std_logic_arith.conv_std_logic_vector;\r
   5 \r
   6 entity mos6502 is \r
   7     port (  \r
   8             pi_rst_n       : in std_logic;\r
   9             pi_base_clk         : in std_logic;\r
  10             pi_cpu_en       : in std_logic_vector (7 downto 0);\r
  11             pi_rdy         : in std_logic;\r
  12             pi_irq_n       : in std_logic;\r
  13             pi_nmi_n       : in std_logic;\r
  14             po_oe_n        : out std_logic;\r
  15             po_we_n        : out std_logic;\r
  16             po_addr        : out std_logic_vector ( 15 downto 0);\r
  17             pio_d_io       : inout std_logic_vector ( 7 downto 0);\r
  18             po_exc_cnt     : out std_logic_vector (63 downto 0)\r
  19     );\r
  20 end mos6502;\r
  21 \r
  22 architecture rtl of mos6502 is\r
  23 \r
  24 ---cpu main state:\r
  25 type cpu_main_state is (\r
  26     --common state. idle and inst fetch.\r
  27     ST_IDLE,\r
  28     ST_CM_T0,\r
  29 \r
  30     --single byte inst execute.\r
  31     ST_A1_T1,\r
  32 \r
  33     --mem data operation\r
  34     --imm\r
  35     ST_A21_T1,\r
  36     --zp\r
  37     ST_A22_T1, ST_A22_T2,\r
  38     --abs\r
  39     ST_A23_T1, ST_A23_T2, ST_A23_T3,\r
  40     --indir, x\r
  41     ST_A24_T1, ST_A24_T2, ST_A24_T3, ST_A24_T4, ST_A24_T5,\r
  42     --abs xy\r
  43     ST_A25_T1, ST_A25_T2, ST_A25_T3, ST_A25_T4,\r
  44     --zp xy\r
  45     ST_A26_T1, ST_A26_T2, ST_A26_T3,\r
  46     --indir, y\r
  47     ST_A27_T1, ST_A27_T2, ST_A27_T3, ST_A27_T4, ST_A27_T5,\r
  48 \r
  49     --store op.\r
  50     --zp\r
  51     ST_A31_T1, ST_A31_T2,\r
  52     --abs\r
  53     ST_A32_T1, ST_A32_T2, ST_A32_T3,\r
  54     --indir, x\r
  55     ST_A33_T1, ST_A33_T2, ST_A33_T3, ST_A33_T4, ST_A33_T5,\r
  56     --abs xy\r
  57     ST_A34_T1, ST_A34_T2, ST_A34_T3, ST_A34_T4,\r
  58     --zp xy\r
  59     ST_A35_T1, ST_A35_T2, ST_A35_T3,\r
  60     --indir, y\r
  61     ST_A36_T1, ST_A36_T2, ST_A36_T3, ST_A36_T4, ST_A36_T5,\r
  62 \r
  63     --memory to memory op.\r
  64     --zp\r
  65     ST_A41_T1, ST_A41_T2, ST_A41_T3, ST_A41_T4,\r
  66     --abs\r
  67     ST_A42_T1, ST_A42_T2, ST_A42_T3, ST_A42_T4, ST_A42_T5,\r
  68     --zp x\r
  69     ST_A43_T1, ST_A43_T2, ST_A43_T3, ST_A43_T4, ST_A43_T5,\r
  70     --abs x\r
  71     ST_A44_T1, ST_A44_T2, ST_A44_T3, ST_A44_T4, ST_A44_T5, ST_A44_T6, \r
  72 \r
  73     --misc operation.\r
  74     --push\r
  75     ST_A51_T1, ST_A51_T2,\r
  76     --pull\r
  77     ST_A52_T1, ST_A52_T2, ST_A52_T3,\r
  78     --jsr\r
  79     ST_A53_T1, ST_A53_T2, ST_A53_T3,ST_A53_T4, ST_A53_T5,\r
  80     --rti\r
  81     ST_A55_T1, ST_A55_T2, ST_A55_T3, ST_A55_T4, ST_A55_T5,\r
  82     --jmp abs\r
  83     ST_A561_T1, ST_A561_T2,\r
  84     --jmp indir\r
  85     ST_A562_T1, ST_A562_T2, ST_A562_T3, ST_A562_T4,\r
  86     --rts\r
  87     ST_A57_T1, ST_A57_T2, ST_A57_T3, ST_A57_T4, ST_A57_T5,\r
  88     --branch\r
  89     ST_A58_T1, ST_A58_T2, ST_A58_T3,\r
  90 \r
  91     --reset vector.\r
  92     ST_RS_T0, ST_RS_T1, ST_RS_T2, ST_RS_T3, ST_RS_T4, ST_RS_T5, ST_RS_T6, ST_RS_T7,\r
  93 \r
  94     --nmi interrupt.\r
  95               ST_NM_T1, ST_NM_T2, ST_NM_T3, ST_NM_T4, ST_NM_T5, ST_NM_T6, ST_NM_T7,\r
  96 \r
  97     --invalid state\r
  98     ST_INV\r
  99     );\r
 100 \r
 101 --cpu sub state.\r
 102 --1 cpu clock is split into 8 state.\r
 103 --1 cpu clock = 32 x base clock.\r
 104 type cpu_sub_state is (\r
 105     ST_SUB00, ST_SUB01, ST_SUB02, ST_SUB03,\r
 106     ST_SUB10, ST_SUB11, ST_SUB12, ST_SUB13,\r
 107     ST_SUB20, ST_SUB21, ST_SUB22, ST_SUB23,\r
 108     ST_SUB30, ST_SUB31, ST_SUB32, ST_SUB33,\r
 109     ST_SUB40, ST_SUB41, ST_SUB42, ST_SUB43,\r
 110     ST_SUB50, ST_SUB51, ST_SUB52, ST_SUB53,\r
 111     ST_SUB60, ST_SUB61, ST_SUB62, ST_SUB63,\r
 112     ST_SUB70, ST_SUB71, ST_SUB72, ST_SUB73\r
 113     );\r
 114 \r
 115 type cpu_state_array    is array (0 to 255) of cpu_main_state;\r
 116 constant inst_decode_rom : cpu_state_array := (\r
 117   --00          01          02          03          04          05          06          07\r
 118     ST_INV,     ST_A24_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A22_T1,  ST_A41_T1,  ST_INV,\r
 119   --08          09          0a          0b          0c          0d          0e          0f\r
 120     ST_A51_T1,  ST_A21_T1,  ST_A1_T1,   ST_INV,     ST_INV,     ST_A23_T1,  ST_A42_T1,  ST_INV,\r
 121   --10          11          12          13          14          15          16          17\r
 122     ST_A58_T1,  ST_A27_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A26_T1,  ST_A43_T1,  ST_INV,\r
 123   --18          19          1a          1b          1c          1d          1e          1f\r
 124     ST_A1_T1,   ST_A25_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A25_T1,  ST_A44_T1,  ST_INV,\r
 125   --20          21          22          23          24          25          26          27\r
 126     ST_A53_T1,  ST_A24_T1,  ST_INV,     ST_INV,     ST_A22_T1,  ST_A22_T1,  ST_A41_T1,  ST_INV,\r
 127   --28          29          2a          2b          2c          2d          2e          2f\r
 128     ST_A52_T1,  ST_A21_T1,  ST_A1_T1,   ST_INV,     ST_A23_T1,  ST_A23_T1,  ST_A42_T1,  ST_INV,\r
 129   --30          31          32          33          34          35          36          37\r
 130     ST_A58_T1,  ST_A27_T1,  ST_INV,     ST_INV,     ST_A26_T1,  ST_A26_T1,  ST_A43_T1,  ST_INV,\r
 131   --38          39          3a          3b          3c          3d          3e          3f\r
 132     ST_A1_T1,   ST_A25_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A25_T1,  ST_A44_T1,  ST_INV,\r
 133   --40          41          42          43          44          45          46          47\r
 134     ST_A55_T1,  ST_A24_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A22_T1,  ST_A41_T1,  ST_INV,\r
 135   --48          49          4a          4b          4c          4d          4e          4f\r
 136     ST_A51_T1,  ST_A21_T1,  ST_A1_T1,   ST_INV,     ST_A561_T1, ST_A23_T1,  ST_A42_T1,  ST_INV,\r
 137   --50          51          52          53          54          55          56          57\r
 138     ST_A58_T1,  ST_A27_T1,  ST_INV,     ST_INV,     ST_A26_T1,  ST_A26_T1,  ST_A43_T1,  ST_INV,\r
 139   --58          59          5a          5b          5c          5d          5e          5f\r
 140     ST_A1_T1,   ST_A25_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A25_T1,  ST_A44_T1,  ST_INV,\r
 141   --60          61          62          63          64          65          66          67\r
 142     ST_A57_T1,  ST_A24_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A22_T1,  ST_A41_T1,  ST_INV,\r
 143   --68          69          6a          6b          6c          6d          6e          6f\r
 144     ST_A52_T1,  ST_A21_T1,  ST_A1_T1,   ST_INV,     ST_A562_T1, ST_A23_T1,  ST_A42_T1,  ST_INV,\r
 145   --70          71          72          73          74          75          76          77\r
 146     ST_A58_T1,  ST_A27_T1,  ST_INV,     ST_INV,     ST_A26_T1,  ST_A26_T1,  ST_A43_T1,  ST_INV,\r
 147   --78          79          7a          7b          7c          7d          7e          7f\r
 148     ST_A1_T1,   ST_A25_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A25_T1,  ST_A44_T1,  ST_INV,\r
 149   --80          81          82          83          84          85          86          87\r
 150     ST_INV,     ST_A33_T1,  ST_INV,     ST_INV,     ST_A31_T1,  ST_A31_T1,  ST_A31_T1,  ST_INV,\r
 151   --88          89          8a          8b          8c          8d          8e          8f\r
 152     ST_A1_T1,   ST_INV,     ST_A1_T1,   ST_INV,     ST_A32_T1,  ST_A32_T1,  ST_A32_T1,  ST_INV,\r
 153   --90          91          92          93          94          95          96          97\r
 154     ST_A58_T1,  ST_A36_T1,  ST_INV,     ST_INV,     ST_A35_T1,  ST_A35_T1,  ST_A35_T1,  ST_INV,\r
 155   --98          99          9a          9b          9c          9d          9e          9f\r
 156     ST_A1_T1,   ST_A34_T1,  ST_A1_T1,   ST_INV,     ST_INV,     ST_A34_T1,  ST_INV,     ST_INV,\r
 157   --a0          a1          a2          a3          a4          a5          a6          a7\r
 158     ST_A21_T1,  ST_A24_T1,  ST_A21_T1,  ST_INV,     ST_A22_T1,  ST_A22_T1,  ST_A22_T1,  ST_INV,\r
 159   --a8          a9          aa          ab          ac          ad          ae          af\r
 160     ST_A1_T1,   ST_A21_T1,  ST_A1_T1,   ST_INV,     ST_A23_T1,  ST_A23_T1,  ST_A23_T1,  ST_INV,\r
 161   --b0          b1          b2          b3          b4          b5          b6          b7\r
 162     ST_A58_T1,  ST_A27_T1,  ST_INV,     ST_A26_T1,  ST_A26_T1,  ST_A26_T1,  ST_A26_T1,  ST_INV,\r
 163   --b8          b9          ba          bb          bc          bd          be          bf\r
 164     ST_A1_T1,   ST_A25_T1,  ST_A1_T1,   ST_INV,     ST_A25_T1,  ST_A25_T1,  ST_A25_T1,  ST_INV,\r
 165   --c0          c1          c2          c3          c4          c5          c6          c7\r
 166     ST_A21_T1,  ST_A24_T1,  ST_INV,     ST_INV,     ST_A22_T1,  ST_A22_T1,  ST_A41_T1,  ST_INV,\r
 167   --c8          c9          ca          cb          cc          cd          ce          cf\r
 168     ST_A1_T1,   ST_A21_T1,  ST_A1_T1,   ST_INV,     ST_A23_T1,  ST_A23_T1,  ST_A42_T1,  ST_INV,\r
 169   --d0          d1          d2          d3          d4          d5          d6          d7\r
 170     ST_A58_T1,  ST_A27_T1,  ST_INV,     ST_INV,     ST_A26_T1,  ST_A26_T1,  ST_A43_T1,  ST_INV,\r
 171   --d8          d9          da          db          dc          dd          de          df\r
 172     ST_A1_T1,   ST_A25_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A25_T1,  ST_A44_T1,  ST_INV,\r
 173   --e0          e1          e2          e3          e4          e5          e6          e7\r
 174     ST_A21_T1,  ST_A24_T1,  ST_INV,     ST_INV,     ST_A22_T1,  ST_A22_T1,  ST_A41_T1,  ST_INV,\r
 175   --e8          e9          ea          eb          ec          ed          ee          ef\r
 176     ST_A1_T1,   ST_A21_T1,  ST_A1_T1,   ST_INV,     ST_A23_T1,  ST_A23_T1,  ST_A42_T1,  ST_INV,\r
 177   --f0          f1          f2          f3          f4          f5          f6          f7\r
 178     ST_A58_T1,  ST_A27_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A26_T1,  ST_A43_T1,  ST_INV,\r
 179   --f8          f9          fa          fb          fc          fd          fe          ff\r
 180     ST_A1_T1,   ST_A25_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A25_T1,  ST_A44_T1,  ST_INV\r
 181 );\r
 182 \r
 183 --        Flags (bit 7 to bit 0):\r
 184 --        N   ....    Negative\r
 185 --        V   ....    Overflow\r
 186 --        -   ....    ignored   -- always 1 for NES 6502\r
 187 --        B   ....    Break\r
 188 --        D   ....    Decimal (use BCD for arithmetics)     -- not supported. always 0.\r
 189 --        I   ....    Interrupt (IRQ disable)\r
 190 --        Z   ....    Zero\r
 191 --        C   ....    Carry\r
 192 constant FL_N   : integer := 7;\r
 193 constant FL_V   : integer := 6;\r
 194 constant FL_I   : integer := 2;\r
 195 constant FL_Z   : integer := 1;\r
 196 constant FL_C   : integer := 0;\r
 197 \r
 198 signal reg_main_state           : cpu_main_state;\r
 199 signal reg_main_next_state      : cpu_main_state;\r
 200 signal reg_sub_state            : cpu_sub_state;\r
 201 signal reg_sub_next_state       : cpu_sub_state;\r
 202 \r
 203 --6502 register definition...\r
 204 signal reg_inst     : std_logic_vector (7 downto 0);\r
 205 signal reg_acc      : std_logic_vector (7 downto 0);\r
 206 signal reg_x        : std_logic_vector (7 downto 0);\r
 207 signal reg_y        : std_logic_vector (7 downto 0);\r
 208 signal reg_idl_l    : std_logic_vector (7 downto 0);\r
 209 signal reg_idl_h    : std_logic_vector (7 downto 0);\r
 210 signal reg_sp       : std_logic_vector (7 downto 0);\r
 211 signal reg_status   : std_logic_vector (7 downto 0);\r
 212 signal reg_pc_l     : std_logic_vector (7 downto 0);\r
 213 signal reg_pc_h     : std_logic_vector (7 downto 0);\r
 214 \r
 215 --tmp flag reg.\r
 216 signal reg_tmp_carry    : std_logic;\r
 217 signal reg_tmp_ovf      : std_logic;\r
 218 signal reg_tmp_condition    : std_logic;\r
 219 signal reg_tmp_pg_crossed   : std_logic;\r
 220 \r
 221 --tmp address reg.\r
 222 signal reg_tmp_l    : std_logic_vector (7 downto 0);\r
 223 signal reg_tmp_h    : std_logic_vector (7 downto 0);\r
 224 \r
 225 --tmp data reg.\r
 226 signal reg_tmp_data : std_logic_vector (7 downto 0);\r
 227 \r
 228 --bus i/o reg.\r
 229 signal reg_oe_n     : std_logic;\r
 230 signal reg_we_n     : std_logic;\r
 231 signal reg_addr     : std_logic_vector (15 downto 0);\r
 232 signal reg_d_in     : std_logic_vector (7 downto 0);\r
 233 signal reg_d_out    : std_logic_vector (7 downto 0);\r
 234 \r
 235 signal reg_nmi_handled  : integer range 0 to 1;\r
 236 signal reg_dma_set      : integer range 0 to 1;\r
 237 \r
 238 --debug purpose...\r
 239 signal reg_exc_cnt          : std_logic_vector (63 downto 0);\r
 240 \r
 241 begin\r
 242     --state transition process...\r
 243     set_stat_p : process (pi_rst_n, pi_base_clk)\r
 244     begin\r
 245         if (pi_rst_n = '0') then\r
 246             reg_main_state <= ST_RS_T0;\r
 247             reg_sub_state <= ST_SUB00;\r
 248         elsif (rising_edge(pi_base_clk)) then\r
 249             reg_main_state <= reg_main_next_state;\r
 250             reg_sub_state <= reg_sub_next_state;\r
 251         end if;--if (pi_rst_n = '0') then\r
 252     end process;\r
 253 \r
 254     --fixed length sub status change (0 - 31 because cpu clock is 1/32 of base clock).\r
 255     tx_next_sub_stat_p : process (reg_sub_state, pi_cpu_en)\r
 256     begin\r
 257         case reg_sub_state is\r
 258             when ST_SUB00 =>\r
 259                 if (pi_cpu_en(0) = '1') then\r
 260                     reg_sub_next_state <= ST_SUB01;\r
 261                 else\r
 262                     reg_sub_next_state <= reg_sub_state;\r
 263                 end if;\r
 264             when ST_SUB01 =>\r
 265                 reg_sub_next_state <= ST_SUB02;\r
 266             when ST_SUB02 =>\r
 267                 reg_sub_next_state <= ST_SUB03;\r
 268             when ST_SUB03 =>\r
 269                 reg_sub_next_state <= ST_SUB10;\r
 270             when ST_SUB10 =>\r
 271                 reg_sub_next_state <= ST_SUB11;\r
 272             when ST_SUB11 =>\r
 273                 reg_sub_next_state <= ST_SUB12;\r
 274             when ST_SUB12 =>\r
 275                 reg_sub_next_state <= ST_SUB13;\r
 276             when ST_SUB13 =>\r
 277                 reg_sub_next_state <= ST_SUB20;\r
 278             when ST_SUB20 =>\r
 279                 reg_sub_next_state <= ST_SUB21;\r
 280             when ST_SUB21 =>\r
 281                 reg_sub_next_state <= ST_SUB22;\r
 282             when ST_SUB22 =>\r
 283                 reg_sub_next_state <= ST_SUB23;\r
 284             when ST_SUB23 =>\r
 285                 reg_sub_next_state <= ST_SUB30;\r
 286             when ST_SUB30 =>\r
 287                 reg_sub_next_state <= ST_SUB31;\r
 288             when ST_SUB31 =>\r
 289                 reg_sub_next_state <= ST_SUB32;\r
 290             when ST_SUB32 =>\r
 291                 reg_sub_next_state <= ST_SUB33;\r
 292             when ST_SUB33 =>\r
 293                 reg_sub_next_state <= ST_SUB40;\r
 294             when ST_SUB40 =>\r
 295                 reg_sub_next_state <= ST_SUB41;\r
 296             when ST_SUB41 =>\r
 297                 reg_sub_next_state <= ST_SUB42;\r
 298             when ST_SUB42 =>\r
 299                 reg_sub_next_state <= ST_SUB43;\r
 300             when ST_SUB43 =>\r
 301                 reg_sub_next_state <= ST_SUB50;\r
 302             when ST_SUB50 =>\r
 303                 reg_sub_next_state <= ST_SUB51;\r
 304             when ST_SUB51 =>\r
 305                 reg_sub_next_state <= ST_SUB52;\r
 306             when ST_SUB52 =>\r
 307                 reg_sub_next_state <= ST_SUB53;\r
 308             when ST_SUB53 =>\r
 309                 reg_sub_next_state <= ST_SUB60;\r
 310             when ST_SUB60 =>\r
 311                 reg_sub_next_state <= ST_SUB61;\r
 312             when ST_SUB61 =>\r
 313                 reg_sub_next_state <= ST_SUB62;\r
 314             when ST_SUB62 =>\r
 315                 reg_sub_next_state <= ST_SUB63;\r
 316             when ST_SUB63 =>\r
 317                 reg_sub_next_state <= ST_SUB70;\r
 318             when ST_SUB70 =>\r
 319                 reg_sub_next_state <= ST_SUB71;\r
 320             when ST_SUB71 =>\r
 321                 reg_sub_next_state <= ST_SUB72;\r
 322             when ST_SUB72 =>\r
 323                 reg_sub_next_state <= ST_SUB73;\r
 324             when ST_SUB73 =>\r
 325                 reg_sub_next_state <= ST_SUB00;\r
 326         end case;\r
 327     end process;\r
 328 \r
 329     --state change to next.\r
 330     tx_next_main_stat_p : process (pi_rst_n, reg_main_state, reg_sub_state,\r
 331                                    reg_inst, reg_tmp_condition, reg_tmp_pg_crossed,\r
 332                                    pi_nmi_n, reg_nmi_handled, reg_dma_set, pi_rdy)\r
 333 \r
 334     begin\r
 335         case reg_main_state is\r
 336             -----idle...\r
 337             when ST_IDLE =>\r
 338                 if (pi_rst_n = '0') then\r
 339                     reg_main_next_state <= ST_RS_T0;\r
 340                 elsif (reg_sub_state = ST_SUB73 and reg_dma_set = 1 and pi_rdy = '1') then\r
 341                     --ST_CM_T0 is canceled when dma initiated.\r
 342                     --redo ST_CM_T0.\r
 343                     reg_main_next_state <= ST_CM_T0;\r
 344                 else\r
 345                     reg_main_next_state <= reg_main_state;\r
 346                 end if;\r
 347             -----reset...\r
 348             when ST_RS_T0 =>\r
 349                 if (reg_sub_state = ST_SUB73) then\r
 350                     if (pi_rst_n = '0') then\r
 351                         reg_main_next_state <= reg_main_state;\r
 352                     else\r
 353                         reg_main_next_state <= ST_RS_T1;\r
 354                     end if;\r
 355                 else\r
 356                     reg_main_next_state <= reg_main_state;\r
 357                 end if;\r
 358             when ST_RS_T1 =>\r
 359                 if (reg_sub_state = ST_SUB73) then\r
 360                     reg_main_next_state <= ST_RS_T2;\r
 361                 else\r
 362                     reg_main_next_state <= reg_main_state;\r
 363                 end if;\r
 364             when ST_RS_T2 =>\r
 365                 if (reg_sub_state = ST_SUB73) then\r
 366                     reg_main_next_state <= ST_RS_T3;\r
 367                 else\r
 368                     reg_main_next_state <= reg_main_state;\r
 369                 end if;\r
 370             when ST_RS_T3 =>\r
 371                 if (reg_sub_state = ST_SUB73) then\r
 372                     reg_main_next_state <= ST_RS_T4;\r
 373                 else\r
 374                     reg_main_next_state <= reg_main_state;\r
 375                 end if;\r
 376             when ST_RS_T4 =>\r
 377                 if (reg_sub_state = ST_SUB73) then\r
 378                     reg_main_next_state <= ST_RS_T5;\r
 379                 else\r
 380                     reg_main_next_state <= reg_main_state;\r
 381                 end if;\r
 382             when ST_RS_T5 =>\r
 383                 if (reg_sub_state = ST_SUB73) then\r
 384                     reg_main_next_state <= ST_RS_T6;\r
 385                 else\r
 386                     reg_main_next_state <= reg_main_state;\r
 387                 end if;\r
 388             when ST_RS_T6 =>\r
 389                 if (reg_sub_state = ST_SUB73) then\r
 390                     reg_main_next_state <= ST_RS_T7;\r
 391                 else\r
 392                     reg_main_next_state <= reg_main_state;\r
 393                 end if;\r
 394             when ST_RS_T7 =>\r
 395                 if (reg_sub_state = ST_SUB73) then\r
 396                     reg_main_next_state <= ST_CM_T0;\r
 397                 else\r
 398                     reg_main_next_state <= reg_main_state;\r
 399                 end if;\r
 400 \r
 401             --instruction fetch\r
 402             when ST_CM_T0 =>\r
 403                 if (reg_sub_state = ST_SUB73) then\r
 404                     if (pi_nmi_n = '0' and reg_nmi_handled = 0) then\r
 405                         --nmi raised. transit to nmi state.\r
 406                         reg_main_next_state <= ST_NM_T1;\r
 407                     elsif (pi_rdy = '0') then\r
 408                         --dma started.\r
 409                         reg_main_next_state <= ST_IDLE;\r
 410                     else\r
 411                         ---instruction decode next state.\r
 412                         ---pc inc is executed at the end of the cycle (ST_SUB73).\r
 413                         reg_main_next_state <= inst_decode_rom(conv_integer(reg_inst));\r
 414                     end if;\r
 415                 else\r
 416                     reg_main_next_state <= reg_main_state;\r
 417                 end if;\r
 418 \r
 419             --A1 inst.(single byte)\r
 420             when ST_A1_T1 =>\r
 421                 if (reg_sub_state = ST_SUB73) then\r
 422                     reg_main_next_state <= ST_CM_T0;\r
 423                 else\r
 424                     reg_main_next_state <= reg_main_state;\r
 425                 end if;\r
 426 \r
 427             --A2 inst.\r
 428             when ST_A21_T1 =>\r
 429                 if (reg_sub_state = ST_SUB73) then\r
 430                     reg_main_next_state <= ST_CM_T0;\r
 431                 else\r
 432                     reg_main_next_state <= reg_main_state;\r
 433                 end if;\r
 434             when ST_A22_T1 =>\r
 435                 if (reg_sub_state = ST_SUB73) then\r
 436                     reg_main_next_state <= ST_A22_T2;\r
 437                 else\r
 438                     reg_main_next_state <= reg_main_state;\r
 439                 end if;\r
 440             when ST_A22_T2 =>\r
 441                 if (reg_sub_state = ST_SUB73) then\r
 442                     reg_main_next_state <= ST_CM_T0;\r
 443                 else\r
 444                     reg_main_next_state <= reg_main_state;\r
 445                 end if;\r
 446             when ST_A23_T1 =>\r
 447                 if (reg_sub_state = ST_SUB73) then\r
 448                     reg_main_next_state <= ST_A23_T2;\r
 449                 else\r
 450                     reg_main_next_state <= reg_main_state;\r
 451                 end if;\r
 452             when ST_A23_T2 =>\r
 453                 if (reg_sub_state = ST_SUB73) then\r
 454                     reg_main_next_state <= ST_A23_T3;\r
 455                 else\r
 456                     reg_main_next_state <= reg_main_state;\r
 457                 end if;\r
 458             when ST_A23_T3 =>\r
 459                 if (reg_sub_state = ST_SUB73) then\r
 460                     reg_main_next_state <= ST_CM_T0;\r
 461                 else\r
 462                     reg_main_next_state <= reg_main_state;\r
 463                 end if;\r
 464             when ST_A24_T1 =>\r
 465                 if (reg_sub_state = ST_SUB73) then\r
 466                     reg_main_next_state <= ST_A24_T2;\r
 467                 else\r
 468                     reg_main_next_state <= reg_main_state;\r
 469                 end if;\r
 470             when ST_A24_T2 =>\r
 471                 if (reg_sub_state = ST_SUB73) then\r
 472                     reg_main_next_state <= ST_A24_T3;\r
 473                 else\r
 474                     reg_main_next_state <= reg_main_state;\r
 475                 end if;\r
 476             when ST_A24_T3 =>\r
 477                 if (reg_sub_state = ST_SUB73) then\r
 478                     reg_main_next_state <= ST_A24_T4;\r
 479                 else\r
 480                     reg_main_next_state <= reg_main_state;\r
 481                 end if;\r
 482             when ST_A24_T4 =>\r
 483                 if (reg_sub_state = ST_SUB73) then\r
 484                     reg_main_next_state <= ST_A24_T5;\r
 485                 else\r
 486                     reg_main_next_state <= reg_main_state;\r
 487                 end if;\r
 488             when ST_A24_T5 =>\r
 489                 if (reg_sub_state = ST_SUB73) then\r
 490                     reg_main_next_state <= ST_CM_T0;\r
 491                 else\r
 492                     reg_main_next_state <= reg_main_state;\r
 493                 end if;\r
 494             when ST_A25_T1 =>\r
 495                 if (reg_sub_state = ST_SUB73) then\r
 496                     reg_main_next_state <= ST_A25_T2;\r
 497                 else\r
 498                     reg_main_next_state <= reg_main_state;\r
 499                 end if;\r
 500             when ST_A25_T2 =>\r
 501                 if (reg_sub_state = ST_SUB73) then\r
 502                     reg_main_next_state <= ST_A25_T3;\r
 503                 else\r
 504                     reg_main_next_state <= reg_main_state;\r
 505                 end if;\r
 506             when ST_A25_T3 =>\r
 507                 if (reg_sub_state = ST_SUB73) then\r
 508                     --abs xy move to next only when page crossed.\r
 509                     if (reg_tmp_pg_crossed = '1') then\r
 510                         reg_main_next_state <= ST_A25_T4;\r
 511                     else\r
 512                         reg_main_next_state <= ST_CM_T0;\r
 513                     end if;\r
 514                 else\r
 515                     reg_main_next_state <= reg_main_state;\r
 516                 end if;\r
 517             when ST_A25_T4 =>\r
 518                 if (reg_sub_state = ST_SUB73) then\r
 519                     reg_main_next_state <= ST_CM_T0;\r
 520                 else\r
 521                     reg_main_next_state <= reg_main_state;\r
 522                 end if;\r
 523             when ST_A26_T1 =>\r
 524                 if (reg_sub_state = ST_SUB73) then\r
 525                     reg_main_next_state <= ST_A26_T2;\r
 526                 else\r
 527                     reg_main_next_state <= reg_main_state;\r
 528                 end if;\r
 529             when ST_A26_T2 =>\r
 530                 if (reg_sub_state = ST_SUB73) then\r
 531                     reg_main_next_state <= ST_A26_T3;\r
 532                 else\r
 533                     reg_main_next_state <= reg_main_state;\r
 534                 end if;\r
 535             when ST_A26_T3 =>\r
 536                 if (reg_sub_state = ST_SUB73) then\r
 537                     reg_main_next_state <= ST_CM_T0;\r
 538                 else\r
 539                     reg_main_next_state <= reg_main_state;\r
 540                 end if;\r
 541             when ST_A27_T1 =>\r
 542                 if (reg_sub_state = ST_SUB73) then\r
 543                     reg_main_next_state <= ST_A27_T2;\r
 544                 else\r
 545                     reg_main_next_state <= reg_main_state;\r
 546                 end if;\r
 547             when ST_A27_T2 =>\r
 548                 if (reg_sub_state = ST_SUB73) then\r
 549                     reg_main_next_state <= ST_A27_T3;\r
 550                 else\r
 551                     reg_main_next_state <= reg_main_state;\r
 552                 end if;\r
 553             when ST_A27_T3 =>\r
 554                 if (reg_sub_state = ST_SUB73) then\r
 555                     reg_main_next_state <= ST_A27_T4;\r
 556                 else\r
 557                     reg_main_next_state <= reg_main_state;\r
 558                 end if;\r
 559             when ST_A27_T4 =>\r
 560                 if (reg_sub_state = ST_SUB73) then\r
 561                     --indir, y move to next only when page crossed.\r
 562                     if (reg_tmp_pg_crossed = '1') then\r
 563                         reg_main_next_state <= ST_A27_T5;\r
 564                     else\r
 565                         reg_main_next_state <= ST_CM_T0;\r
 566                     end if;\r
 567                 else\r
 568                     reg_main_next_state <= reg_main_state;\r
 569                 end if;\r
 570             when ST_A27_T5 =>\r
 571                 if (reg_sub_state = ST_SUB73) then\r
 572                     reg_main_next_state <= ST_CM_T0;\r
 573                 else\r
 574                     reg_main_next_state <= reg_main_state;\r
 575                 end if;\r
 576 \r
 577             --A3 inst.\r
 578             when ST_A31_T1 =>\r
 579                 if (reg_sub_state = ST_SUB73) then\r
 580                     reg_main_next_state <= ST_A31_T2;\r
 581                 else\r
 582                     reg_main_next_state <= reg_main_state;\r
 583                 end if;\r
 584             when ST_A31_T2 =>\r
 585                 if (reg_sub_state = ST_SUB73) then\r
 586                     reg_main_next_state <= ST_CM_T0;\r
 587                 else\r
 588                     reg_main_next_state <= reg_main_state;\r
 589                 end if;\r
 590             when ST_A32_T1 =>\r
 591                 if (reg_sub_state = ST_SUB73) then\r
 592                     reg_main_next_state <= ST_A32_T2;\r
 593                 else\r
 594                     reg_main_next_state <= reg_main_state;\r
 595                 end if;\r
 596             when ST_A32_T2 =>\r
 597                 if (reg_sub_state = ST_SUB73) then\r
 598                     reg_main_next_state <= ST_A32_T3;\r
 599                 else\r
 600                     reg_main_next_state <= reg_main_state;\r
 601                 end if;\r
 602             when ST_A32_T3 =>\r
 603                 if (reg_sub_state = ST_SUB73) then\r
 604                     reg_main_next_state <= ST_CM_T0;\r
 605                 else\r
 606                     reg_main_next_state <= reg_main_state;\r
 607                 end if;\r
 608             when ST_A33_T1 =>\r
 609                 if (reg_sub_state = ST_SUB73) then\r
 610                     reg_main_next_state <= ST_A33_T2;\r
 611                 else\r
 612                     reg_main_next_state <= reg_main_state;\r
 613                 end if;\r
 614             when ST_A33_T2 =>\r
 615                 if (reg_sub_state = ST_SUB73) then\r
 616                     reg_main_next_state <= ST_A33_T3;\r
 617                 else\r
 618                     reg_main_next_state <= reg_main_state;\r
 619                 end if;\r
 620             when ST_A33_T3 =>\r
 621                 if (reg_sub_state = ST_SUB73) then\r
 622                     reg_main_next_state <= ST_A33_T4;\r
 623                 else\r
 624                     reg_main_next_state <= reg_main_state;\r
 625                 end if;\r
 626             when ST_A33_T4 =>\r
 627                 if (reg_sub_state = ST_SUB73) then\r
 628                     reg_main_next_state <= ST_A33_T5;\r
 629                 else\r
 630                     reg_main_next_state <= reg_main_state;\r
 631                 end if;\r
 632             when ST_A33_T5 =>\r
 633                 if (reg_sub_state = ST_SUB73) then\r
 634                     reg_main_next_state <= ST_CM_T0;\r
 635                 else\r
 636                     reg_main_next_state <= reg_main_state;\r
 637                 end if;\r
 638             when ST_A34_T1 =>\r
 639                 if (reg_sub_state = ST_SUB73) then\r
 640                     reg_main_next_state <= ST_A34_T2;\r
 641                 else\r
 642                     reg_main_next_state <= reg_main_state;\r
 643                 end if;\r
 644             when ST_A34_T2 =>\r
 645                 if (reg_sub_state = ST_SUB73) then\r
 646                     reg_main_next_state <= ST_A34_T3;\r
 647                 else\r
 648                     reg_main_next_state <= reg_main_state;\r
 649                 end if;\r
 650             when ST_A34_T3 =>\r
 651                 if (reg_sub_state = ST_SUB73) then\r
 652                     reg_main_next_state <= ST_A34_T4;\r
 653                 else\r
 654                     reg_main_next_state <= reg_main_state;\r
 655                 end if;\r
 656             when ST_A34_T4 =>\r
 657                 if (reg_sub_state = ST_SUB73) then\r
 658                     reg_main_next_state <= ST_CM_T0;\r
 659                 else\r
 660                     reg_main_next_state <= reg_main_state;\r
 661                 end if;\r
 662             when ST_A35_T1 =>\r
 663                 if (reg_sub_state = ST_SUB73) then\r
 664                     reg_main_next_state <= ST_A35_T2;\r
 665                 else\r
 666                     reg_main_next_state <= reg_main_state;\r
 667                 end if;\r
 668             when ST_A35_T2 =>\r
 669                 if (reg_sub_state = ST_SUB73) then\r
 670                     reg_main_next_state <= ST_A35_T3;\r
 671                 else\r
 672                     reg_main_next_state <= reg_main_state;\r
 673                 end if;\r
 674             when ST_A35_T3 =>\r
 675                 if (reg_sub_state = ST_SUB73) then\r
 676                     reg_main_next_state <= ST_CM_T0;\r
 677                 else\r
 678                     reg_main_next_state <= reg_main_state;\r
 679                 end if;\r
 680             when ST_A36_T1 =>\r
 681                 if (reg_sub_state = ST_SUB73) then\r
 682                     reg_main_next_state <= ST_A36_T2;\r
 683                 else\r
 684                     reg_main_next_state <= reg_main_state;\r
 685                 end if;\r
 686             when ST_A36_T2 =>\r
 687                 if (reg_sub_state = ST_SUB73) then\r
 688                     reg_main_next_state <= ST_A36_T3;\r
 689                 else\r
 690                     reg_main_next_state <= reg_main_state;\r
 691                 end if;\r
 692             when ST_A36_T3 =>\r
 693                 if (reg_sub_state = ST_SUB73) then\r
 694                     reg_main_next_state <= ST_A36_T4;\r
 695                 else\r
 696                     reg_main_next_state <= reg_main_state;\r
 697                 end if;\r
 698             when ST_A36_T4 =>\r
 699                 if (reg_sub_state = ST_SUB73) then\r
 700                     reg_main_next_state <= ST_A36_T5;\r
 701                 else\r
 702                     reg_main_next_state <= reg_main_state;\r
 703                 end if;\r
 704             when ST_A36_T5 =>\r
 705                 if (reg_sub_state = ST_SUB73) then\r
 706                     reg_main_next_state <= ST_CM_T0;\r
 707                 else\r
 708                     reg_main_next_state <= reg_main_state;\r
 709                 end if;\r
 710 \r
 711 \r
 712             --A4 inst.\r
 713             when ST_A41_T1 =>\r
 714                 if (reg_sub_state = ST_SUB73) then\r
 715                     reg_main_next_state <= ST_A41_T2;\r
 716                 else\r
 717                     reg_main_next_state <= reg_main_state;\r
 718                 end if;\r
 719             when ST_A41_T2 =>\r
 720                 if (reg_sub_state = ST_SUB73) then\r
 721                     reg_main_next_state <= ST_A41_T3;\r
 722                 else\r
 723                     reg_main_next_state <= reg_main_state;\r
 724                 end if;\r
 725             when ST_A41_T3 =>\r
 726                 if (reg_sub_state = ST_SUB73) then\r
 727                     reg_main_next_state <= ST_A41_T4;\r
 728                 else\r
 729                     reg_main_next_state <= reg_main_state;\r
 730                 end if;\r
 731             when ST_A41_T4 =>\r
 732                 if (reg_sub_state = ST_SUB73) then\r
 733                     reg_main_next_state <= ST_CM_T0;\r
 734                 else\r
 735                     reg_main_next_state <= reg_main_state;\r
 736                 end if;\r
 737             when ST_A42_T1 =>\r
 738                 if (reg_sub_state = ST_SUB73) then\r
 739                     reg_main_next_state <= ST_A42_T2;\r
 740                 else\r
 741                     reg_main_next_state <= reg_main_state;\r
 742                 end if;\r
 743             when ST_A42_T2 =>\r
 744                 if (reg_sub_state = ST_SUB73) then\r
 745                     reg_main_next_state <= ST_A42_T3;\r
 746                 else\r
 747                     reg_main_next_state <= reg_main_state;\r
 748                 end if;\r
 749             when ST_A42_T3 =>\r
 750                 if (reg_sub_state = ST_SUB73) then\r
 751                     reg_main_next_state <= ST_A42_T4;\r
 752                 else\r
 753                     reg_main_next_state <= reg_main_state;\r
 754                 end if;\r
 755             when ST_A42_T4 =>\r
 756                 if (reg_sub_state = ST_SUB73) then\r
 757                     reg_main_next_state <= ST_A42_T5;\r
 758                 else\r
 759                     reg_main_next_state <= reg_main_state;\r
 760                 end if;\r
 761             when ST_A42_T5 =>\r
 762                 if (reg_sub_state = ST_SUB73) then\r
 763                     reg_main_next_state <= ST_CM_T0;\r
 764                 else\r
 765                     reg_main_next_state <= reg_main_state;\r
 766                 end if;\r
 767             when ST_A43_T1 =>\r
 768                 if (reg_sub_state = ST_SUB73) then\r
 769                     reg_main_next_state <= ST_A43_T2;\r
 770                 else\r
 771                     reg_main_next_state <= reg_main_state;\r
 772                 end if;\r
 773             when ST_A43_T2 =>\r
 774                 if (reg_sub_state = ST_SUB73) then\r
 775                     reg_main_next_state <= ST_A43_T3;\r
 776                 else\r
 777                     reg_main_next_state <= reg_main_state;\r
 778                 end if;\r
 779             when ST_A43_T3 =>\r
 780                 if (reg_sub_state = ST_SUB73) then\r
 781                     reg_main_next_state <= ST_A43_T4;\r
 782                 else\r
 783                     reg_main_next_state <= reg_main_state;\r
 784                 end if;\r
 785             when ST_A43_T4 =>\r
 786                 if (reg_sub_state = ST_SUB73) then\r
 787                     reg_main_next_state <= ST_A43_T5;\r
 788                 else\r
 789                     reg_main_next_state <= reg_main_state;\r
 790                 end if;\r
 791             when ST_A43_T5 =>\r
 792                 if (reg_sub_state = ST_SUB73) then\r
 793                     reg_main_next_state <= ST_CM_T0;\r
 794                 else\r
 795                     reg_main_next_state <= reg_main_state;\r
 796                 end if;\r
 797             when ST_A44_T1 =>\r
 798                 if (reg_sub_state = ST_SUB73) then\r
 799                     reg_main_next_state <= ST_A44_T2;\r
 800                 else\r
 801                     reg_main_next_state <= reg_main_state;\r
 802                 end if;\r
 803             when ST_A44_T2 =>\r
 804                 if (reg_sub_state = ST_SUB73) then\r
 805                     reg_main_next_state <= ST_A44_T3;\r
 806                 else\r
 807                     reg_main_next_state <= reg_main_state;\r
 808                 end if;\r
 809             when ST_A44_T3 =>\r
 810                 if (reg_sub_state = ST_SUB73) then\r
 811                     reg_main_next_state <= ST_A44_T4;\r
 812                 else\r
 813                     reg_main_next_state <= reg_main_state;\r
 814                 end if;\r
 815             when ST_A44_T4 =>\r
 816                 if (reg_sub_state = ST_SUB73) then\r
 817                     reg_main_next_state <= ST_A44_T5;\r
 818                 else\r
 819                     reg_main_next_state <= reg_main_state;\r
 820                 end if;\r
 821             when ST_A44_T5 =>\r
 822                 if (reg_sub_state = ST_SUB73) then\r
 823                     reg_main_next_state <= ST_A44_T6;\r
 824                 else\r
 825                     reg_main_next_state <= reg_main_state;\r
 826                 end if;\r
 827             when ST_A44_T6 =>\r
 828                 if (reg_sub_state = ST_SUB73) then\r
 829                     reg_main_next_state <= ST_CM_T0;\r
 830                 else\r
 831                     reg_main_next_state <= reg_main_state;\r
 832                 end if;\r
 833 \r
 834 \r
 835             --A5 inst.\r
 836             when ST_A51_T1 =>\r
 837                 if (reg_sub_state = ST_SUB73) then\r
 838                     reg_main_next_state <= ST_A51_T2;\r
 839                 else\r
 840                     reg_main_next_state <= reg_main_state;\r
 841                 end if;\r
 842             when ST_A51_T2 =>\r
 843                 if (reg_sub_state = ST_SUB73) then\r
 844                     reg_main_next_state <= ST_CM_T0;\r
 845                 else\r
 846                     reg_main_next_state <= reg_main_state;\r
 847                 end if;\r
 848             when ST_A52_T1 =>\r
 849                 if (reg_sub_state = ST_SUB73) then\r
 850                     reg_main_next_state <= ST_A52_T2;\r
 851                 else\r
 852                     reg_main_next_state <= reg_main_state;\r
 853                 end if;\r
 854             when ST_A52_T2 =>\r
 855                 if (reg_sub_state = ST_SUB73) then\r
 856                     reg_main_next_state <= ST_A52_T3;\r
 857                 else\r
 858                     reg_main_next_state <= reg_main_state;\r
 859                 end if;\r
 860             when ST_A52_T3 =>\r
 861                 if (reg_sub_state = ST_SUB73) then\r
 862                     reg_main_next_state <= ST_CM_T0;\r
 863                 else\r
 864                     reg_main_next_state <= reg_main_state;\r
 865                 end if;\r
 866             when ST_A53_T1 =>\r
 867                 if (reg_sub_state = ST_SUB73) then\r
 868                     reg_main_next_state <= ST_A53_T2;\r
 869                 else\r
 870                     reg_main_next_state <= reg_main_state;\r
 871                 end if;\r
 872             when ST_A53_T2 =>\r
 873                 if (reg_sub_state = ST_SUB73) then\r
 874                     reg_main_next_state <= ST_A53_T3;\r
 875                 else\r
 876                     reg_main_next_state <= reg_main_state;\r
 877                 end if;\r
 878             when ST_A53_T3 =>\r
 879                 if (reg_sub_state = ST_SUB73) then\r
 880                     reg_main_next_state <= ST_A53_T4;\r
 881                 else\r
 882                     reg_main_next_state <= reg_main_state;\r
 883                 end if;\r
 884             when ST_A53_T4 =>\r
 885                 if (reg_sub_state = ST_SUB73) then\r
 886                     reg_main_next_state <= ST_A53_T5;\r
 887                 else\r
 888                     reg_main_next_state <= reg_main_state;\r
 889                 end if;\r
 890             when ST_A53_T5 =>\r
 891                 if (reg_sub_state = ST_SUB73) then\r
 892                     reg_main_next_state <= ST_CM_T0;\r
 893                 else\r
 894                     reg_main_next_state <= reg_main_state;\r
 895                 end if;\r
 896             when ST_A55_T1 =>\r
 897                 if (reg_sub_state = ST_SUB73) then\r
 898                     reg_main_next_state <= ST_A55_T2;\r
 899                 else\r
 900                     reg_main_next_state <= reg_main_state;\r
 901                 end if;\r
 902             when ST_A55_T2 =>\r
 903                 if (reg_sub_state = ST_SUB73) then\r
 904                     reg_main_next_state <= ST_A55_T3;\r
 905                 else\r
 906                     reg_main_next_state <= reg_main_state;\r
 907                 end if;\r
 908             when ST_A55_T3 =>\r
 909                 if (reg_sub_state = ST_SUB73) then\r
 910                     reg_main_next_state <= ST_A55_T4;\r
 911                 else\r
 912                     reg_main_next_state <= reg_main_state;\r
 913                 end if;\r
 914             when ST_A55_T4 =>\r
 915                 if (reg_sub_state = ST_SUB73) then\r
 916                     reg_main_next_state <= ST_A55_T5;\r
 917                 else\r
 918                     reg_main_next_state <= reg_main_state;\r
 919                 end if;\r
 920             when ST_A55_T5 =>\r
 921                 if (reg_sub_state = ST_SUB73) then\r
 922                     reg_main_next_state <= ST_CM_T0;\r
 923                 else\r
 924                     reg_main_next_state <= reg_main_state;\r
 925                 end if;\r
 926             when ST_A561_T1 =>\r
 927                 if (reg_sub_state = ST_SUB73) then\r
 928                     reg_main_next_state <= ST_A561_T2;\r
 929                 else\r
 930                     reg_main_next_state <= reg_main_state;\r
 931                 end if;\r
 932             when ST_A561_T2 =>\r
 933                 if (reg_sub_state = ST_SUB73) then\r
 934                     reg_main_next_state <= ST_CM_T0;\r
 935                 else\r
 936                     reg_main_next_state <= reg_main_state;\r
 937                 end if;\r
 938             when ST_A562_T1 =>\r
 939                 if (reg_sub_state = ST_SUB73) then\r
 940                     reg_main_next_state <= ST_A562_T2;\r
 941                 else\r
 942                     reg_main_next_state <= reg_main_state;\r
 943                 end if;\r
 944             when ST_A562_T2 =>\r
 945                 if (reg_sub_state = ST_SUB73) then\r
 946                     reg_main_next_state <= ST_A562_T3;\r
 947                 else\r
 948                     reg_main_next_state <= reg_main_state;\r
 949                 end if;\r
 950             when ST_A562_T3 =>\r
 951                 if (reg_sub_state = ST_SUB73) then\r
 952                     reg_main_next_state <= ST_A562_T4;\r
 953                 else\r
 954                     reg_main_next_state <= reg_main_state;\r
 955                 end if;\r
 956             when ST_A562_T4 =>\r
 957                 if (reg_sub_state = ST_SUB73) then\r
 958                     reg_main_next_state <= ST_CM_T0;\r
 959                 else\r
 960                     reg_main_next_state <= reg_main_state;\r
 961                 end if;\r
 962             when ST_A57_T1 =>\r
 963                 if (reg_sub_state = ST_SUB73) then\r
 964                     reg_main_next_state <= ST_A57_T2;\r
 965                 else\r
 966                     reg_main_next_state <= reg_main_state;\r
 967                 end if;\r
 968             when ST_A57_T2 =>\r
 969                 if (reg_sub_state = ST_SUB73) then\r
 970                     reg_main_next_state <= ST_A57_T3;\r
 971                 else\r
 972                     reg_main_next_state <= reg_main_state;\r
 973                 end if;\r
 974             when ST_A57_T3 =>\r
 975                 if (reg_sub_state = ST_SUB73) then\r
 976                     reg_main_next_state <= ST_A57_T4;\r
 977                 else\r
 978                     reg_main_next_state <= reg_main_state;\r
 979                 end if;\r
 980             when ST_A57_T4 =>\r
 981                 if (reg_sub_state = ST_SUB73) then\r
 982                     reg_main_next_state <= ST_A57_T5;\r
 983                 else\r
 984                     reg_main_next_state <= reg_main_state;\r
 985                 end if;\r
 986             when ST_A57_T5 =>\r
 987                 if (reg_sub_state = ST_SUB73) then\r
 988                     reg_main_next_state <= ST_CM_T0;\r
 989                 else\r
 990                     reg_main_next_state <= reg_main_state;\r
 991                 end if;\r
 992             when ST_A58_T1 =>\r
 993                 if (reg_sub_state = ST_SUB73) then\r
 994                     if (reg_tmp_condition = '1') then\r
 995                         --condition met. move to branch state.\r
 996                         reg_main_next_state <= ST_A58_T2;\r
 997                     else\r
 998                         --condition not met. goto next inst fetch.\r
 999                         reg_main_next_state <= ST_CM_T0;\r
1000                     end if;\r
1001                 else\r
1002                     reg_main_next_state <= reg_main_state;\r
1003                 end if;\r
1004             when ST_A58_T2 =>\r
1005                 if (reg_sub_state = ST_SUB73) then\r
1006                     if (reg_tmp_pg_crossed = '1') then\r
1007                         --page crossed. move to next.\r
1008                         reg_main_next_state <= ST_A58_T3;\r
1009                     else\r
1010                         --page not crossed. move to next inst fetch.\r
1011                         reg_main_next_state <= ST_CM_T0;\r
1012                     end if;\r
1013                 else\r
1014                     reg_main_next_state <= reg_main_state;\r
1015                 end if;\r
1016             when ST_A58_T3 =>\r
1017                 if (reg_sub_state = ST_SUB73) then\r
1018                     reg_main_next_state <= ST_CM_T0;\r
1019                 else\r
1020                     reg_main_next_state <= reg_main_state;\r
1021                 end if;\r
1022 \r
1023             -----nmi...\r
1024             when ST_NM_T1 =>\r
1025                 if (reg_sub_state = ST_SUB73) then\r
1026                     reg_main_next_state <= ST_NM_T2;\r
1027                 else\r
1028                     reg_main_next_state <= reg_main_state;\r
1029                 end if;\r
1030             when ST_NM_T2 =>\r
1031                 if (reg_sub_state = ST_SUB73) then\r
1032                     reg_main_next_state <= ST_NM_T3;\r
1033                 else\r
1034                     reg_main_next_state <= reg_main_state;\r
1035                 end if;\r
1036             when ST_NM_T3 =>\r
1037                 if (reg_sub_state = ST_SUB73) then\r
1038                     reg_main_next_state <= ST_NM_T4;\r
1039                 else\r
1040                     reg_main_next_state <= reg_main_state;\r
1041                 end if;\r
1042             when ST_NM_T4 =>\r
1043                 if (reg_sub_state = ST_SUB73) then\r
1044                     reg_main_next_state <= ST_NM_T5;\r
1045                 else\r
1046                     reg_main_next_state <= reg_main_state;\r
1047                 end if;\r
1048             when ST_NM_T5 =>\r
1049                 if (reg_sub_state = ST_SUB73) then\r
1050                     reg_main_next_state <= ST_NM_T6;\r
1051                 else\r
1052                     reg_main_next_state <= reg_main_state;\r
1053                 end if;\r
1054             when ST_NM_T6 =>\r
1055                 if (reg_sub_state = ST_SUB73) then\r
1056                     reg_main_next_state <= ST_NM_T7;\r
1057                 else\r
1058                     reg_main_next_state <= reg_main_state;\r
1059                 end if;\r
1060             when ST_NM_T7 =>\r
1061                 if (reg_sub_state = ST_SUB73) then\r
1062                     reg_main_next_state <= ST_CM_T0;\r
1063                 else\r
1064                     reg_main_next_state <= reg_main_state;\r
1065                 end if;\r
1066 \r
1067             --invalid state\r
1068             when ST_INV =>\r
1069                 ---failed to decode next...\r
1070                     reg_main_next_state <= reg_main_state;\r
1071 \r
1072 --            when others =>\r
1073 --                reg_main_next_state <= reg_main_state;\r
1074         end case;\r
1075     end process;\r
1076 \r
1077 \r
1078     po_oe_n     <= reg_oe_n;\r
1079     po_we_n     <= reg_we_n;\r
1080     po_addr     <= reg_addr;\r
1081     pio_d_io    <= reg_d_out;\r
1082 \r
1083     --addressing general process...\r
1084     --pc, io bus, r/w, instruction regs...\r
1085     ad_general_p : process (pi_rst_n, pi_base_clk)\r
1086 \r
1087     --address calcuratin w/ carry.\r
1088     variable calc_adl   : std_logic_vector(8 downto 0);\r
1089 \r
1090 procedure pc_inc is\r
1091 begin\r
1092     if (reg_pc_l = "11111111") then\r
1093         --pch page next.\r
1094         reg_pc_l    <= "00000000";\r
1095         reg_pc_h    <= reg_pc_h + 1;\r
1096     else\r
1097         reg_pc_l    <= reg_pc_l + 1;\r
1098     end if;\r
1099 end;\r
1100 \r
1101 procedure write_enable is\r
1102 begin\r
1103     reg_oe_n    <= '1';\r
1104     if (reg_sub_state = ST_SUB32 or\r
1105         reg_sub_state = ST_SUB33 or\r
1106         reg_sub_state = ST_SUB40 or\r
1107         reg_sub_state = ST_SUB41\r
1108         ) then\r
1109         reg_we_n    <= '0';\r
1110     else\r
1111         reg_we_n    <= '1';\r
1112     end if;\r
1113 end;\r
1114 \r
1115     begin\r
1116         if (pi_rst_n = '0') then\r
1117             reg_pc_l    <= (others => '0');\r
1118             reg_pc_h    <= (others => '0');\r
1119             reg_inst    <= (others => '0');\r
1120             reg_addr    <= (others => 'Z');\r
1121             reg_d_out   <= (others => 'Z');\r
1122             reg_d_in    <= (others => '0');\r
1123             reg_oe_n    <= 'Z';\r
1124             reg_we_n    <= 'Z';\r
1125             reg_tmp_pg_crossed  <= '0';\r
1126             calc_adl    := (others => '0');\r
1127         elsif (rising_edge(pi_base_clk)) then\r
1128 \r
1129             --general input data register.\r
1130             reg_d_in    <= pio_d_io;\r
1131             \r
1132             --reset vector\r
1133             if (reg_main_state = ST_RS_T0) then\r
1134                 reg_pc_l    <= (others => '0');\r
1135                 reg_pc_h    <= (others => '0');\r
1136                 reg_inst    <= (others => '0');\r
1137                 reg_addr    <= (others => '0');\r
1138                 reg_d_out   <= (others => 'Z');\r
1139                 reg_oe_n    <= '1';\r
1140                 reg_we_n    <= '1';\r
1141             elsif (reg_main_state = ST_RS_T3) then\r
1142                 --dummy sp out 1.\r
1143                 reg_addr    <= "00000001" & reg_sp;\r
1144                 reg_d_out   <= (others => '0');\r
1145                 write_enable;\r
1146             elsif (reg_main_state = ST_RS_T4) then\r
1147                 --dummy sp out 2.\r
1148                 reg_addr    <= "00000001" & (reg_sp - 1);\r
1149                 reg_d_out   <= (others => '0');\r
1150                 write_enable;\r
1151             elsif (reg_main_state = ST_RS_T5) then\r
1152                 --dummy sp out 3.\r
1153                 reg_addr    <= "00000001" & (reg_sp - 2);\r
1154                 reg_d_out   <= (others => '0');\r
1155                 write_enable;\r
1156             elsif (reg_main_state = ST_RS_T6) then\r
1157                 --reset vector low...\r
1158                 reg_addr    <= "1111111111111100";\r
1159                 reg_d_out   <= (others => 'Z');\r
1160                 reg_oe_n    <= '0';\r
1161                 reg_we_n    <= '1';\r
1162                 reg_pc_l    <= reg_d_in;\r
1163             elsif (reg_main_state = ST_RS_T7) then\r
1164                 --reset vector high...\r
1165                 reg_addr    <= "1111111111111101";\r
1166                 reg_pc_h    <= reg_d_in;\r
1167 \r
1168             --common entry cycle.\r
1169             elsif (reg_main_state = ST_CM_T0) then\r
1170                 --init flags.\r
1171                 reg_tmp_pg_crossed <= '0';\r
1172                 calc_adl    := (others => '0');\r
1173                 reg_d_out   <= (others => 'Z');\r
1174 \r
1175                 if (pi_nmi_n = '0' and reg_nmi_handled = 0) then\r
1176                     --nmi raised cycle.\r
1177                     reg_oe_n    <= '1';\r
1178                     reg_we_n    <= '1';\r
1179                     reg_addr    <= (others => 'Z');\r
1180                 elsif (pi_rdy = '0') then\r
1181                     --dma started cycle.\r
1182                     reg_oe_n    <= 'Z';\r
1183                     reg_we_n    <= 'Z';\r
1184                     reg_addr    <= (others => 'Z');\r
1185                 else\r
1186                     --normal cycle.\r
1187                     reg_oe_n    <= '0';\r
1188                     reg_we_n    <= '1';\r
1189                     if (reg_sub_state = ST_SUB00) then\r
1190                         --fetch next.\r
1191                         reg_addr    <= reg_pc_h & reg_pc_l;\r
1192                     elsif (reg_sub_state = ST_SUB30) then\r
1193                         --update instruction register.\r
1194                         reg_inst    <= reg_d_in;\r
1195                     elsif (reg_sub_state = ST_SUB73) then\r
1196                         --pc move next.\r
1197                         pc_inc;\r
1198                     end if;\r
1199                 end if;\r
1200 \r
1201             --fetch and move next case.\r
1202             elsif (reg_main_state = ST_A21_T1 or\r
1203                 reg_main_state = ST_A22_T1 or\r
1204                 reg_main_state = ST_A23_T1 or\r
1205                 reg_main_state = ST_A23_T2 or\r
1206                 reg_main_state = ST_A24_T1 or\r
1207                 reg_main_state = ST_A25_T1 or\r
1208                 reg_main_state = ST_A25_T2 or\r
1209                 reg_main_state = ST_A26_T1 or\r
1210                 reg_main_state = ST_A27_T1 or\r
1211                 reg_main_state = ST_A31_T1 or\r
1212                 reg_main_state = ST_A32_T1 or\r
1213                 reg_main_state = ST_A32_T2 or\r
1214                 reg_main_state = ST_A33_T1 or\r
1215                 reg_main_state = ST_A34_T1 or\r
1216                 reg_main_state = ST_A34_T2 or\r
1217                 reg_main_state = ST_A35_T1 or\r
1218                 reg_main_state = ST_A36_T1 or\r
1219                 reg_main_state = ST_A41_T1 or\r
1220                 reg_main_state = ST_A42_T1 or\r
1221                 reg_main_state = ST_A42_T2 or\r
1222                 reg_main_state = ST_A43_T1 or\r
1223                 reg_main_state = ST_A44_T1 or\r
1224                 reg_main_state = ST_A44_T2 or\r
1225                 reg_main_state = ST_A53_T1 or\r
1226                 reg_main_state = ST_A55_T1 or\r
1227                 reg_main_state = ST_A561_T1 or\r
1228                 reg_main_state = ST_A562_T1 or\r
1229                 reg_main_state = ST_A562_T2 or\r
1230                 reg_main_state = ST_A57_T1 or\r
1231                 reg_main_state = ST_A58_T1) then\r
1232                 if (reg_sub_state = ST_SUB00) then\r
1233                     --fetch next.\r
1234                     reg_addr    <= reg_pc_h & reg_pc_l;\r
1235                 elsif (reg_sub_state = ST_SUB70) then\r
1236                     --pc move next.\r
1237                     pc_inc;\r
1238                 end if;\r
1239 \r
1240             --intermediate cycles..\r
1241             elsif (reg_main_state = ST_A24_T2 or\r
1242                 reg_main_state = ST_A26_T2 or\r
1243                 reg_main_state = ST_A33_T2 or\r
1244                 reg_main_state = ST_A35_T2 or\r
1245                 reg_main_state = ST_A27_T2 or\r
1246                 reg_main_state = ST_A36_T2 or\r
1247                 reg_main_state = ST_A43_T2\r
1248                 ) then\r
1249                 --zp xy\r
1250                 --ind, x\r
1251                 -->>discarded cycle.\r
1252                 --ind, y\r
1253                 --ial cycle.\r
1254                 reg_addr    <= "00000000" & reg_idl_l;\r
1255             elsif (reg_main_state = ST_A24_T3 or\r
1256                 reg_main_state = ST_A33_T3\r
1257                 ) then\r
1258                 --ind, x\r
1259                 --bal + x cycle.\r
1260                 reg_addr    <= "00000000" & (reg_idl_l + reg_x);\r
1261             elsif (reg_main_state = ST_A24_T4 or\r
1262                 reg_main_state = ST_A33_T4) then\r
1263                 --ind, x\r
1264                 --bal + x + 1 cycle.\r
1265                 reg_addr    <= "00000000" & (reg_idl_l + reg_x + 1);\r
1266             elsif (reg_main_state = ST_A25_T3 or\r
1267                 reg_main_state = ST_A34_T3 or\r
1268                 reg_main_state = ST_A44_T3\r
1269                 ) then\r
1270                 --abs xy\r
1271                 --(discarded cycle for store inst..)\r
1272                 if (reg_inst = conv_std_logic_vector(16#be#, 8)) then\r
1273                     --abs y\r
1274                     --ldx\r
1275                     reg_addr    <= reg_idl_h & (reg_idl_l + reg_y);\r
1276                     calc_adl    := ("0" & reg_idl_l) + ("0" & reg_y);\r
1277                 elsif (reg_inst = conv_std_logic_vector(16#bc#, 8)) then\r
1278                     --abs x\r
1279                     --ldy\r
1280                     reg_addr    <= reg_idl_h & (reg_idl_l + reg_x);\r
1281                     calc_adl    := ("0" & reg_idl_l) + ("0" & reg_x);\r
1282                 elsif (reg_inst = conv_std_logic_vector(16#9d#, 8)) then\r
1283                     --sta, x\r
1284                     reg_addr    <= reg_idl_h & (reg_idl_l + reg_x);\r
1285                     calc_adl    := ("0" & reg_idl_l) + ("0" & reg_x);\r
1286                 elsif (reg_inst = conv_std_logic_vector(16#99#, 8)) then\r
1287                     --sta, y\r
1288                     reg_addr    <= reg_idl_h & (reg_idl_l + reg_y);\r
1289                     calc_adl    := ("0" & reg_idl_l) + ("0" & reg_y);\r
1290                 elsif (reg_inst(1 downto 0) = "10") then\r
1291                     --a4 inst.\r
1292                     if (reg_inst(4 downto 2) = "111") then\r
1293                         --abs x\r
1294                         reg_addr    <= reg_idl_h & (reg_idl_l + reg_x);\r
1295                         calc_adl    := ("0" & reg_idl_l) + ("0" & reg_x);\r
1296                     end if; \r
1297                 elsif (reg_inst(1 downto 0) = "01") then\r
1298                     --a2 inst\r
1299                     if (reg_inst(4 downto 2) = "110") then\r
1300                         --abs y\r
1301                         reg_addr    <= reg_idl_h & (reg_idl_l + reg_y);\r
1302                         calc_adl    := ("0" & reg_idl_l) + ("0" & reg_y);\r
1303                     elsif (reg_inst(4 downto 2) = "111") then\r
1304                         --abs x\r
1305                         reg_addr    <= reg_idl_h & (reg_idl_l + reg_x);\r
1306                         calc_adl    := ("0" & reg_idl_l) + ("0" & reg_x);\r
1307                     end if; \r
1308                 end if;\r
1309 \r
1310                 reg_tmp_pg_crossed <= calc_adl(8);\r
1311             elsif (reg_main_state = ST_A27_T3 or\r
1312                 reg_main_state = ST_A36_T3) then\r
1313                 --ind, y\r
1314                 --ial + 1 cycle.\r
1315                 reg_addr    <= "00000000" & (reg_idl_l + 1);\r
1316             elsif (reg_main_state = ST_A27_T4 or\r
1317                 reg_main_state = ST_A36_T4) then\r
1318                 --ind, y\r
1319                 --bal + y cycle.\r
1320                 reg_addr    <= reg_tmp_h & (reg_tmp_l + reg_y);\r
1321                 calc_adl    := ("0" & reg_tmp_l) + ("0" & reg_y);\r
1322                 reg_tmp_pg_crossed <= calc_adl(8);\r
1323             elsif (reg_main_state = ST_A51_T1 or\r
1324                 reg_main_state = ST_A52_T1) then\r
1325                 --push/pull\r
1326                 --discard pc cycle.\r
1327                 reg_addr    <= reg_pc_h & (reg_pc_l + 1);\r
1328             elsif (reg_main_state = ST_A52_T2 or\r
1329                 reg_main_state = ST_A53_T2\r
1330                 ) then\r
1331                 --pull, jsr\r
1332                 --discard sp cycle.\r
1333                 reg_addr    <= "00000001" & reg_sp;\r
1334 \r
1335 \r
1336            --a2 instructions.\r
1337             elsif (reg_main_state = ST_A22_T2 or\r
1338                 reg_main_state = ST_A23_T3 or\r
1339                 reg_main_state = ST_A24_T5 or\r
1340                 reg_main_state = ST_A25_T4 or\r
1341                 reg_main_state = ST_A26_T3 or\r
1342                 reg_main_state = ST_A27_T5\r
1343             ) then\r
1344                 --execute cycle.\r
1345 \r
1346                 --address bus out.\r
1347                 if (reg_main_state = ST_A22_T2) then\r
1348                     --zp\r
1349                     reg_addr    <= "00000000" & reg_idl_l;\r
1350 \r
1351                 elsif (reg_main_state = ST_A23_T3) then\r
1352                     --abs\r
1353                     reg_addr    <= reg_idl_h & reg_idl_l;\r
1354 \r
1355                 elsif (reg_main_state = ST_A24_T5) then\r
1356                     --ind, x\r
1357                     reg_addr    <= reg_tmp_h & reg_tmp_l;\r
1358 \r
1359                 elsif (reg_main_state = ST_A25_T4) then\r
1360                     --abs xy\r
1361                     if (reg_inst(1 downto 0) = "01") then\r
1362                         if (reg_inst(4 downto 2) = "110") then\r
1363                             --abs y\r
1364                             reg_addr    <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_y);\r
1365                         elsif (reg_inst(4 downto 2) = "111") then\r
1366                             --abs x\r
1367                             reg_addr    <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_x);\r
1368                         end if; \r
1369                     elsif (reg_inst = conv_std_logic_vector(16#be#, 8)) then\r
1370                         --abs y\r
1371                         --ldx\r
1372                         reg_addr    <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_y);\r
1373                     elsif (reg_inst = conv_std_logic_vector(16#bc#, 8)) then\r
1374                         --abs x\r
1375                         --ldy\r
1376                         reg_addr    <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_x);\r
1377                     end if; \r
1378 \r
1379                 elsif (reg_main_state = ST_A26_T3) then\r
1380                     --zp xy\r
1381                     if (reg_inst(1 downto 0) = "01") then\r
1382                         if (reg_inst(4 downto 2) = "101") then\r
1383                             --zp x\r
1384                             reg_addr    <= "00000000" & (reg_idl_l + reg_x);\r
1385                         end if; \r
1386                     elsif (reg_inst = conv_std_logic_vector(16#b6#, 8)) then\r
1387                         --zp y\r
1388                         --ldx\r
1389                         reg_addr    <= "00000000" & (reg_idl_l + reg_y);\r
1390                     elsif (reg_inst = conv_std_logic_vector(16#b4#, 8)) then\r
1391                         --zp y\r
1392                         --ldy\r
1393                         reg_addr    <= "00000000" & (reg_idl_l + reg_x);\r
1394                     end if; \r
1395 \r
1396                 elsif (reg_main_state = ST_A27_T5) then\r
1397                     --ind y\r
1398                     reg_addr    <= (reg_tmp_h + reg_tmp_pg_crossed) & (reg_tmp_l + reg_y);\r
1399                 end if;\r
1400 \r
1401            --a3 instructions.\r
1402            --sta, stx, sty\r
1403             elsif (reg_main_state = ST_A31_T2 or\r
1404                 reg_main_state = ST_A32_T3 or\r
1405                 reg_main_state = ST_A33_T5 or\r
1406                 reg_main_state = ST_A34_T4 or\r
1407                 reg_main_state = ST_A35_T3 or\r
1408                 reg_main_state = ST_A36_T5\r
1409             ) then\r
1410                 --store cycle.\r
1411                 --data out\r
1412                 if (reg_inst(1 downto 0) = "01" and reg_inst(7 downto 5) = "100") then\r
1413                     --sta\r
1414                     reg_d_out   <= reg_acc;\r
1415                 elsif (reg_inst(1 downto 0) = "10" and reg_inst(7 downto 5) = "100") then\r
1416                     --stx\r
1417                     reg_d_out   <= reg_x;\r
1418                 elsif (reg_inst(1 downto 0) = "00" and reg_inst(7 downto 5) = "100") then\r
1419                     --sty\r
1420                     reg_d_out   <= reg_y;\r
1421                 end if;\r
1422 \r
1423                 --rw ctrl\r
1424                 write_enable;\r
1425 \r
1426                 --address bus out.\r
1427                 if (reg_main_state = ST_A31_T2) then\r
1428                     --zp\r
1429                     reg_addr    <= "00000000" & reg_idl_l;\r
1430 \r
1431                 elsif (reg_main_state = ST_A32_T3) then\r
1432                     --abs\r
1433                     reg_addr    <= reg_idl_h & reg_idl_l;\r
1434 \r
1435                 elsif (reg_main_state = ST_A33_T5) then\r
1436                     --ind, x\r
1437                     reg_addr    <= reg_tmp_h & reg_tmp_l;\r
1438 \r
1439                 elsif (reg_main_state = ST_A34_T4) then\r
1440                     --abs xy\r
1441                     if (reg_inst = conv_std_logic_vector(16#9d#, 8)) then\r
1442                         --sta, x\r
1443                         reg_addr    <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_x);\r
1444                     elsif (reg_inst = conv_std_logic_vector(16#99#, 8)) then\r
1445                         --sta, y\r
1446                         reg_addr    <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_y);\r
1447                     end if;\r
1448 \r
1449                 elsif (reg_main_state = ST_A35_T3) then\r
1450                     --zp xy\r
1451                     --sta and sty has index x access,\r
1452                     --stx has index y access.\r
1453                     if (reg_inst = conv_std_logic_vector(16#95#, 8) or --sta\r
1454                         reg_inst = conv_std_logic_vector(16#94#, 8) --sty\r
1455                     ) then\r
1456                         reg_addr    <= "00000000" & (reg_idl_l + reg_x);\r
1457                     elsif (reg_inst = conv_std_logic_vector(16#96#, 8)) then\r
1458                         --stx\r
1459                         reg_addr    <= "00000000" & (reg_idl_l + reg_y);\r
1460                     end if;\r
1461 \r
1462                 elsif (reg_main_state = ST_A36_T5) then\r
1463                     --ind y\r
1464                     reg_addr    <= (reg_tmp_h + reg_tmp_pg_crossed) & (reg_tmp_l + reg_y);\r
1465                 end if;\r
1466 \r
1467            --a4 instructions.\r
1468            --asl    lsr\r
1469            --dec    rol\r
1470            --inc    ror\r
1471             elsif (reg_main_state = ST_A41_T2 or\r
1472                 reg_main_state = ST_A42_T3 or\r
1473                 reg_main_state = ST_A43_T3 or\r
1474                 reg_main_state = ST_A44_T4\r
1475             ) then\r
1476                 --data fetch cycle.\r
1477 \r
1478                 --address bus out.\r
1479                 if (reg_main_state = ST_A41_T2) then\r
1480                     --zp\r
1481                     reg_addr    <= "00000000" & reg_idl_l;\r
1482 \r
1483                 elsif (reg_main_state = ST_A42_T3) then\r
1484                     --abs\r
1485                     reg_addr    <= reg_idl_h & reg_idl_l;\r
1486 \r
1487                 elsif (reg_main_state = ST_A43_T3) then\r
1488                     --zp x\r
1489                     reg_addr    <= "00000000" & (reg_idl_l + reg_x);\r
1490 \r
1491                 elsif (reg_main_state = ST_A44_T4) then\r
1492                     --abs x\r
1493                     reg_addr    <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_x);\r
1494                 end if;\r
1495 \r
1496             elsif (reg_main_state = ST_A41_T3 or\r
1497                 reg_main_state = ST_A41_T4 or\r
1498                 reg_main_state = ST_A42_T4 or\r
1499                 reg_main_state = ST_A42_T5 or\r
1500                 reg_main_state = ST_A43_T4 or\r
1501                 reg_main_state = ST_A43_T5 or\r
1502                 reg_main_state = ST_A44_T5 or\r
1503                 reg_main_state = ST_A44_T6\r
1504             ) then\r
1505                 --data store cycle.\r
1506                 --data out\r
1507                 reg_d_out   <= reg_tmp_data;\r
1508                 write_enable;\r
1509 \r
1510                 --address bus out.\r
1511                 if (reg_main_state = ST_A41_T3 or\r
1512                     reg_main_state = ST_A41_T4\r
1513                     ) then\r
1514                     --zp\r
1515                     reg_addr    <= "00000000" & reg_idl_l;\r
1516 \r
1517                 elsif (reg_main_state = ST_A42_T4 or\r
1518                     reg_main_state = ST_A42_T5\r
1519                     ) then\r
1520                     --abs\r
1521                     reg_addr    <= reg_idl_h & reg_idl_l;\r
1522 \r
1523                 elsif (reg_main_state = ST_A43_T4 or\r
1524                     reg_main_state = ST_A43_T5\r
1525                     ) then\r
1526                     --zp x\r
1527                     reg_addr    <= "00000000" & (reg_idl_l + reg_x);\r
1528 \r
1529                 elsif (reg_main_state = ST_A44_T5 or\r
1530                     reg_main_state = ST_A44_T6\r
1531                     ) then\r
1532                     --abs x\r
1533                     reg_addr    <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_x);\r
1534                 end if;\r
1535 \r
1536             --a5 instruction...\r
1537             --push\r
1538             elsif (reg_main_state = ST_A51_T2) then\r
1539                 reg_addr    <= "00000001" & reg_sp;\r
1540                 if (reg_inst = conv_std_logic_vector(16#48#, 8)) then\r
1541                     --pha\r
1542                     reg_d_out   <= reg_acc;\r
1543                 elsif (reg_inst = conv_std_logic_vector(16#08#, 8)) then\r
1544                     --php\r
1545                     reg_d_out   <= reg_status;\r
1546                 end if;\r
1547                 write_enable;\r
1548 \r
1549             --pull\r
1550             elsif (reg_main_state = ST_A52_T3) then\r
1551                 reg_addr    <= "00000001" & reg_sp;\r
1552 \r
1553             --jsr.\r
1554             elsif (reg_main_state = ST_A53_T3) then\r
1555                 --push pch\r
1556                 reg_addr    <= "00000001" & reg_sp;\r
1557                 reg_d_out   <= reg_pc_h;\r
1558                 write_enable;\r
1559             elsif (reg_main_state = ST_A53_T4) then\r
1560                 --push pcl\r
1561                 reg_addr    <= "00000001" & reg_sp;\r
1562                 reg_d_out   <= reg_pc_l;\r
1563                 write_enable;\r
1564             elsif (reg_main_state = ST_A53_T5) then\r
1565                 if (reg_sub_state = ST_SUB00) then\r
1566                     --fetch next.\r
1567                     reg_addr    <= reg_pc_h & reg_pc_l;\r
1568                     reg_d_out   <= (others => 'Z');\r
1569                     reg_oe_n    <= '0';\r
1570                 elsif (reg_sub_state = ST_SUB70) then\r
1571                     --go to sub-routine addr.\r
1572                     reg_pc_l    <= reg_idl_l;\r
1573                     reg_pc_h    <= reg_idl_h;\r
1574                 end if;\r
1575 \r
1576            --jmp abs.\r
1577             elsif (reg_main_state = ST_A561_T2) then\r
1578                 if (reg_sub_state = ST_SUB00) then\r
1579                     --fetch next.\r
1580                     reg_addr    <= reg_pc_h & reg_pc_l;\r
1581                 elsif (reg_sub_state = ST_SUB70) then\r
1582                     reg_pc_l    <= reg_idl_l;\r
1583                     reg_pc_h    <= reg_idl_h;\r
1584                 end if;\r
1585 \r
1586            --jmp (indir).\r
1587             elsif (reg_main_state = ST_A562_T3) then\r
1588                 if (reg_sub_state = ST_SUB00) then\r
1589                     reg_addr    <= (reg_idl_h & reg_idl_l);\r
1590                 elsif (reg_sub_state = ST_SUB70) then\r
1591                     reg_pc_l    <= reg_d_in;\r
1592                 end if;\r
1593             elsif (reg_main_state = ST_A562_T4) then\r
1594                 if (reg_sub_state = ST_SUB00) then\r
1595                     reg_addr    <= (reg_idl_h & reg_idl_l) + 1;\r
1596                 elsif (reg_sub_state = ST_SUB70) then\r
1597                     reg_pc_h    <= reg_d_in;\r
1598                 end if;\r
1599 \r
1600            --rts.\r
1601             elsif (reg_main_state = ST_A57_T2) then\r
1602                 --sp out (discarded.)\r
1603                 reg_addr    <= "00000001" & reg_sp;\r
1604             elsif (reg_main_state = ST_A57_T3) then\r
1605                 --pull pcl\r
1606                 if (reg_sub_state = ST_SUB00) then\r
1607                     reg_addr    <= "00000001" & reg_sp;\r
1608                 elsif (reg_sub_state = ST_SUB70) then\r
1609                     reg_pc_l    <= reg_d_in;\r
1610                 end if;\r
1611             elsif (reg_main_state = ST_A57_T4) then\r
1612                 --pull pch\r
1613                 if (reg_sub_state = ST_SUB00) then\r
1614                     reg_addr    <= "00000001" & reg_sp;\r
1615                 elsif (reg_sub_state = ST_SUB70) then\r
1616                     reg_pc_h    <= reg_d_in;\r
1617                 end if;\r
1618             elsif (reg_main_state = ST_A57_T5) then\r
1619                 --pc out (discarded.)\r
1620                 if (reg_sub_state = ST_SUB00) then\r
1621                     reg_addr    <= reg_pc_h & reg_pc_l;\r
1622                 elsif (reg_sub_state = ST_SUB70) then\r
1623                     pc_inc;\r
1624                 end if;\r
1625 \r
1626             --conditional branch.\r
1627             elsif (reg_main_state = ST_A58_T2) then\r
1628                 if (reg_sub_state = ST_SUB10) then\r
1629                     calc_adl    := ("0" & reg_pc_l) + ("0" & reg_idl_l);\r
1630                     --conditional branch is signed add.\r
1631                     if ((reg_idl_l(7) xor calc_adl(8)) = '1') then\r
1632                         reg_tmp_pg_crossed <= '1';\r
1633                     else\r
1634                         reg_tmp_pg_crossed <= '0';\r
1635                     end if;\r
1636 \r
1637                     reg_pc_l    <= calc_adl(7 downto 0);\r
1638                     reg_addr    <= reg_pc_h & calc_adl(7 downto 0);\r
1639                 end if;\r
1640 \r
1641             --page crossed.\r
1642             elsif (reg_main_state = ST_A58_T3) then\r
1643                 if (reg_sub_state = ST_SUB10) then\r
1644                     if (reg_idl_l(7) = '0') then\r
1645                         --page crossig forward branch.\r
1646                         reg_pc_h    <= reg_pc_h + "1";\r
1647                         reg_addr    <= (reg_pc_h + "1") & reg_pc_l;\r
1648                     else\r
1649                         --page crossig backward branch.\r
1650                         reg_pc_h    <= reg_pc_h - "1";\r
1651                         reg_addr    <= (reg_pc_h - "1") & reg_pc_l;\r
1652                     end if;\r
1653                 end if;\r
1654 \r
1655             --nmi\r
1656             elsif (reg_main_state = ST_NM_T1) then\r
1657                 reg_inst    <= (others => '0');\r
1658                 reg_addr    <= (others => '0');\r
1659                 reg_d_out   <= (others => 'Z');\r
1660                 reg_oe_n    <= '1';\r
1661                 reg_we_n    <= '1';\r
1662             elsif (reg_main_state = ST_NM_T3) then\r
1663                 --push pch.\r
1664                 reg_addr    <= "00000001" & reg_sp;\r
1665                 reg_d_out   <= reg_pc_h;\r
1666                 write_enable;\r
1667             elsif (reg_main_state = ST_NM_T4) then\r
1668                 --push pcl.\r
1669                 reg_addr    <= "00000001" & reg_sp;\r
1670                 reg_d_out   <= reg_pc_l;\r
1671                 write_enable;\r
1672             elsif (reg_main_state = ST_NM_T5) then\r
1673                 --push status.\r
1674                 reg_addr    <= "00000001" & reg_sp;\r
1675                 reg_d_out   <= reg_status;\r
1676                 write_enable;\r
1677             elsif (reg_main_state = ST_NM_T6) then\r
1678                 --vector low...\r
1679                 reg_addr    <= "1111111111111010";\r
1680                 reg_d_out   <= (others => 'Z');\r
1681                 reg_oe_n    <= '0';\r
1682                 reg_we_n    <= '1';\r
1683                 reg_pc_l    <= reg_d_in;\r
1684             elsif (reg_main_state = ST_NM_T7) then\r
1685                 --vector high...\r
1686                 reg_addr    <= "1111111111111011";\r
1687                 reg_pc_h    <= reg_d_in;\r
1688 \r
1689            --rti.\r
1690             elsif (reg_main_state = ST_A55_T2) then\r
1691                 --sp out (discarded.)\r
1692                 reg_addr    <= "00000001" & reg_sp;\r
1693             elsif (reg_main_state = ST_A55_T3) then\r
1694                 --pull status\r
1695                 reg_addr    <= "00000001" & reg_sp;\r
1696             elsif (reg_main_state = ST_A55_T4) then\r
1697                 --pull pcl\r
1698                 if (reg_sub_state = ST_SUB00) then\r
1699                     reg_addr    <= "00000001" & reg_sp;\r
1700                 elsif (reg_sub_state = ST_SUB70) then\r
1701                     reg_pc_l    <= reg_d_in;\r
1702                 end if;\r
1703             elsif (reg_main_state = ST_A55_T5) then\r
1704                 --pull pch\r
1705                 if (reg_sub_state = ST_SUB00) then\r
1706                     reg_addr    <= "00000001" & reg_sp;\r
1707                 elsif (reg_sub_state = ST_SUB70) then\r
1708                     reg_pc_h    <= reg_d_in;\r
1709                 end if;\r
1710 \r
1711 \r
1712             end if;--if (reg_main_state = ST_RS_T0) then\r
1713         end if;--if (pi_rst_n = '0') then\r
1714     end process;\r
1715 \r
1716     --internal data latch...\r
1717     --fetch first and second operand.\r
1718     idl_p : process (pi_rst_n, pi_base_clk)\r
1719     begin\r
1720         if (pi_rst_n = '0') then\r
1721             reg_idl_l <= (others => '0');\r
1722             reg_idl_h <= (others => '0');\r
1723             reg_tmp_l <= (others => '0');\r
1724             reg_tmp_h <= (others => '0');\r
1725         elsif (rising_edge(pi_base_clk)) then\r
1726             if (reg_main_state = ST_A21_T1 or\r
1727                 reg_main_state = ST_A22_T1 or\r
1728                 reg_main_state = ST_A23_T1 or\r
1729                 reg_main_state = ST_A24_T1 or\r
1730                 reg_main_state = ST_A25_T1 or\r
1731                 reg_main_state = ST_A26_T1 or\r
1732                 reg_main_state = ST_A27_T1 or\r
1733                 reg_main_state = ST_A31_T1 or\r
1734                 reg_main_state = ST_A32_T1 or\r
1735                 reg_main_state = ST_A33_T1 or\r
1736                 reg_main_state = ST_A34_T1 or\r
1737                 reg_main_state = ST_A35_T1 or\r
1738                 reg_main_state = ST_A36_T1 or\r
1739                 reg_main_state = ST_A41_T1 or\r
1740                 reg_main_state = ST_A42_T1 or\r
1741                 reg_main_state = ST_A43_T1 or\r
1742                 reg_main_state = ST_A44_T1 or\r
1743                 reg_main_state = ST_A53_T1 or\r
1744                 reg_main_state = ST_A561_T1 or\r
1745                 reg_main_state = ST_A562_T1 or\r
1746                 reg_main_state = ST_A58_T1) then\r
1747                 if (reg_sub_state = ST_SUB30) then\r
1748                     --get low data from rom.\r
1749                     reg_idl_l <= reg_d_in;\r
1750                 end if;\r
1751             elsif (reg_main_state = ST_A23_T2 or\r
1752                 reg_main_state = ST_A25_T2 or\r
1753                 reg_main_state = ST_A32_T2 or\r
1754                 reg_main_state = ST_A34_T2 or\r
1755                 reg_main_state = ST_A42_T2 or\r
1756                 reg_main_state = ST_A44_T2 or\r
1757                 reg_main_state = ST_A53_T5 or\r
1758                 reg_main_state = ST_A561_T2 or\r
1759                 reg_main_state = ST_A562_T2) then\r
1760                 if (reg_sub_state = ST_SUB30) then\r
1761                     --get high data from rom.\r
1762                     reg_idl_h <= reg_d_in;\r
1763                 end if;\r
1764             elsif (reg_main_state = ST_A24_T3 or\r
1765                 reg_main_state = ST_A27_T2 or\r
1766                 reg_main_state = ST_A33_T3 or\r
1767                 reg_main_state = ST_A36_T2\r
1768                 ) then\r
1769                 --a24 indr, x\r
1770                 --a27 indr, y\r
1771                 --a33 indr, x\r
1772                 --a36 indr, y\r
1773                 if (reg_sub_state = ST_SUB30) then\r
1774                     reg_tmp_l <= reg_d_in;\r
1775                 end if;\r
1776             elsif (reg_main_state = ST_A24_T4 or\r
1777                 reg_main_state = ST_A27_T3 or\r
1778                 reg_main_state = ST_A33_T4 or\r
1779                 reg_main_state = ST_A36_T3\r
1780                 ) then\r
1781                 --a24 indr, x\r
1782                 --a27 indr, y\r
1783                 --a33 indr, x\r
1784                 --a36 indr, y\r
1785                 if (reg_sub_state = ST_SUB30) then\r
1786                     reg_tmp_h <= reg_d_in;\r
1787                 end if;\r
1788             end if;--if (reg_main_state = ST_RS_T0)\r
1789         end if;--if (pi_rst_n = '0') then\r
1790     end process;\r
1791 \r
1792     --stack pointer...\r
1793     sp_p : process (pi_rst_n, pi_base_clk)\r
1794     begin\r
1795         if (pi_rst_n = '0') then\r
1796             reg_sp <= (others => '0');\r
1797         elsif (rising_edge(pi_base_clk)) then\r
1798             if (reg_main_state = ST_A1_T1) then\r
1799                 --txs inst.\r
1800                 if (reg_inst = conv_std_logic_vector(16#9a#, 8)) then\r
1801                     reg_sp <= reg_x;\r
1802                 end if;\r
1803             elsif (reg_main_state = ST_A51_T2 or\r
1804                 reg_main_state = ST_A53_T3 or\r
1805                 reg_main_state = ST_A53_T4 or\r
1806                 reg_main_state = ST_NM_T3 or\r
1807                 reg_main_state = ST_NM_T4 or\r
1808                 reg_main_state = ST_NM_T5\r
1809                 ) then\r
1810                 --push, jsr, nmi.\r
1811                 if (reg_sub_state = ST_SUB70) then\r
1812                     reg_sp <= reg_sp - 1;\r
1813                 end if;\r
1814             elsif (reg_main_state = ST_A52_T2 or\r
1815                 reg_main_state = ST_A55_T2 or\r
1816                 reg_main_state = ST_A55_T3 or\r
1817                 reg_main_state = ST_A55_T4 or\r
1818                 reg_main_state = ST_A57_T2 or\r
1819                 reg_main_state = ST_A57_T3) then\r
1820                 --pull, rts, rti.\r
1821                 if (reg_sub_state = ST_SUB70) then\r
1822                     reg_sp <= reg_sp + 1;\r
1823                 end if;\r
1824             end if;--if (reg_main_state = ST_RS_T0)\r
1825         end if;--if (pi_rst_n = '0') then\r
1826     end process;\r
1827 \r
1828     --calcuration process...\r
1829     --update acc, x, y, status registers.\r
1830     calc_p : process (pi_rst_n, pi_base_clk)\r
1831 \r
1832     variable calc_res : std_logic_vector (8 downto 0);\r
1833 procedure update_status (\r
1834     d       : in std_logic_vector(7 downto 0);\r
1835     set_n   : in integer range 0 to 1;\r
1836     set_z   : in integer range 0 to 1;\r
1837     set_c   : in integer range 0 to 1\r
1838 ) is\r
1839 begin\r
1840     if (set_n = 1) then\r
1841         if (d(7) = '1') then\r
1842             reg_status(FL_N) <= '1';\r
1843         else\r
1844             reg_status(FL_N) <= '0';\r
1845         end if;\r
1846     end if;\r
1847     if (set_z = 1) then\r
1848         if (d = "00000000") then\r
1849             reg_status(FL_Z) <= '1';\r
1850         else\r
1851             reg_status(FL_Z) <= '0';\r
1852         end if;\r
1853     end if;\r
1854     if (set_c = 1) then\r
1855         reg_status(FL_C) <= reg_tmp_carry;\r
1856     end if;\r
1857 end;\r
1858 \r
1859 procedure set_condition_result (\r
1860     flg   : in integer range 0 to 7;\r
1861     chk_val : in std_logic\r
1862 ) is\r
1863 begin\r
1864     if (reg_status(flg) = chk_val) then\r
1865         reg_tmp_condition <= '1';\r
1866     else\r
1867         reg_tmp_condition <= '0';\r
1868     end if;\r
1869 end;\r
1870 \r
1871     begin\r
1872         --Most instructions that explicitly reference memory locations have bit patterns of the form aaabbbcc.\r
1873         if (pi_rst_n = '0') then\r
1874             reg_acc <= (others => '0');\r
1875             reg_x <= (others => '0');\r
1876             reg_y <= (others => '0');\r
1877             reg_status <= "00100000";\r
1878             reg_tmp_carry <= '0';\r
1879             reg_tmp_ovf <= '0';\r
1880             reg_tmp_condition <= '0';\r
1881         elsif (rising_edge(pi_base_clk)) then\r
1882             --not used status pin initialize (to avoid latches).\r
1883             reg_status(5 downto 3) <= "100";\r
1884 \r
1885             --a1 instructions...\r
1886             --asl   dex     nop     tax     tya\r
1887             --clc   dey     rol     tay\r
1888             --cld   inx     sec     tsx\r
1889             --cli   iny     sed     txa\r
1890             --clv   lsr     sei     txs\r
1891             if (reg_main_state = ST_CM_T0) then\r
1892                 --init flag regs..\r
1893                 reg_tmp_carry <= '0';\r
1894                 reg_tmp_ovf <= '0';\r
1895                 reg_tmp_condition <= '0';\r
1896             elsif (reg_main_state = ST_A1_T1) then\r
1897                 --update reg\r
1898                 if (reg_sub_state = ST_SUB30) then\r
1899                     if (reg_inst = conv_std_logic_vector(16#88#, 8)) then\r
1900                         --dey\r
1901                         reg_y <= reg_y - 1;\r
1902                     elsif (reg_inst = conv_std_logic_vector(16#a8#, 8)) then\r
1903                         --tay\r
1904                         reg_y <= reg_acc;\r
1905                     elsif (reg_inst = conv_std_logic_vector(16#c8#, 8)) then\r
1906                         --iny\r
1907                         reg_y <= reg_y + 1;\r
1908                     elsif (reg_inst = conv_std_logic_vector(16#e8#, 8)) then\r
1909                         --inx\r
1910                         reg_x <= reg_x + 1;\r
1911                     elsif (reg_inst = conv_std_logic_vector(16#18#, 8)) then\r
1912                         --clc\r
1913                         reg_status(FL_C) <= '0';\r
1914                     elsif (reg_inst = conv_std_logic_vector(16#38#, 8)) then\r
1915                         --sec\r
1916                         reg_status(FL_C) <= '1';\r
1917                     elsif (reg_inst = conv_std_logic_vector(16#58#, 8)) then\r
1918                         --cli\r
1919                         reg_status(FL_I) <= '0';\r
1920                     elsif (reg_inst = conv_std_logic_vector(16#78#, 8)) then\r
1921                         --sei\r
1922                         reg_status(FL_I) <= '1';\r
1923                     elsif (reg_inst = conv_std_logic_vector(16#98#, 8)) then\r
1924                         --tya\r
1925                         reg_acc <= reg_y;\r
1926                     elsif (reg_inst = conv_std_logic_vector(16#b8#, 8)) then\r
1927                         --clv\r
1928                         reg_status(FL_V) <= '0';\r
1929                     elsif (reg_inst = conv_std_logic_vector(16#8a#, 8)) then\r
1930                         --txa\r
1931                         reg_acc <= reg_x;\r
1932                     elsif (reg_inst = conv_std_logic_vector(16#aa#, 8)) then\r
1933                         --tax\r
1934                         reg_x <= reg_acc;\r
1935                     elsif (reg_inst = conv_std_logic_vector(16#ba#, 8)) then\r
1936                         --tsx\r
1937                         reg_x <= reg_sp;\r
1938                     elsif (reg_inst = conv_std_logic_vector(16#ca#, 8)) then\r
1939                         --dex\r
1940                         reg_x <= reg_x - 1;\r
1941                     elsif (reg_inst = conv_std_logic_vector(16#ea#, 8)) then\r
1942                         --nop\r
1943                         --do nothing...\r
1944                     --case cc=10\r
1945                     elsif (reg_inst(1 downto 0) = "10") then\r
1946                         if (reg_inst(7 downto 5) = "000") then\r
1947                             --asl\r
1948                             reg_acc <= reg_acc(6 downto 0) & "0";\r
1949                             reg_tmp_carry <= reg_acc(7);\r
1950                         elsif (reg_inst(7 downto 5) = "001") then\r
1951                             --rol\r
1952                             reg_acc <= reg_acc(6 downto 0) & reg_status(FL_C);\r
1953                             reg_tmp_carry <= reg_acc(7);\r
1954                         elsif (reg_inst(7 downto 5) = "010") then\r
1955                             --lsr\r
1956                             reg_acc <= "0" & reg_acc(7 downto 1);\r
1957                             reg_tmp_carry <= reg_acc(0);\r
1958                         elsif (reg_inst(7 downto 5) = "011") then\r
1959                             --ror\r
1960                             reg_acc <= reg_status(FL_C) & reg_acc(7 downto 1);\r
1961                             reg_tmp_carry <= reg_acc(0);\r
1962                         elsif (reg_inst(7 downto 5) = "110") then\r
1963                             --dec\r
1964                             reg_acc <= reg_acc - 1;\r
1965                         elsif (reg_inst(7 downto 5) = "111") then\r
1966                             --inc\r
1967                             reg_acc <= reg_acc + 1;\r
1968                         end if;\r
1969                     end if;\r
1970 \r
1971                 --update status reg\r
1972                 elsif (reg_sub_state = ST_SUB31) then\r
1973                     if (reg_inst = conv_std_logic_vector(16#88#, 8)) then\r
1974                         --dey\r
1975                         update_status(reg_y, 1, 1, 0);\r
1976                     elsif (reg_inst = conv_std_logic_vector(16#a8#, 8)) then\r
1977                         --tay\r
1978                         update_status(reg_y, 1, 1, 0);\r
1979                     elsif (reg_inst = conv_std_logic_vector(16#c8#, 8)) then\r
1980                         --iny\r
1981                         update_status(reg_y, 1, 1, 0);\r
1982                     elsif (reg_inst = conv_std_logic_vector(16#e8#, 8)) then\r
1983                         --inx\r
1984                         update_status(reg_x, 1, 1, 0);\r
1985                     elsif (reg_inst = conv_std_logic_vector(16#98#, 8)) then\r
1986                         --tya\r
1987                         update_status(reg_acc, 1, 1, 0);\r
1988                     elsif (reg_inst = conv_std_logic_vector(16#8a#, 8)) then\r
1989                         --txa\r
1990                         update_status(reg_acc, 1, 1, 0);\r
1991                     elsif (reg_inst = conv_std_logic_vector(16#9a#, 8)) then\r
1992                         --txs\r
1993                         update_status(reg_sp, 1, 1, 0);\r
1994                     elsif (reg_inst = conv_std_logic_vector(16#aa#, 8)) then\r
1995                         --tax\r
1996                         update_status(reg_x, 1, 1, 0);\r
1997                     elsif (reg_inst = conv_std_logic_vector(16#ba#, 8)) then\r
1998                         --tsx\r
1999                         update_status(reg_x, 1, 1, 0);\r
2000                     elsif (reg_inst = conv_std_logic_vector(16#ca#, 8)) then\r
2001                         --dex\r
2002                         update_status(reg_x, 1, 1, 0);\r
2003                     elsif (reg_inst = conv_std_logic_vector(16#ea#, 8)) then\r
2004                         --nop\r
2005                         --do nothing...\r
2006                     --case cc=10\r
2007                     elsif (reg_inst(1 downto 0) = "10") then\r
2008                         if (reg_inst(7 downto 5) = "000") then\r
2009                             --asl\r
2010                             update_status(reg_acc, 1, 1, 1);\r
2011                         elsif (reg_inst(7 downto 5) = "001") then\r
2012                             --rol\r
2013                             update_status(reg_acc, 1, 1, 1);\r
2014                         elsif (reg_inst(7 downto 5) = "010") then\r
2015                             --lsr\r
2016                             update_status(reg_acc, 0, 1, 1);\r
2017                         elsif (reg_inst(7 downto 5) = "011") then\r
2018                             --ror\r
2019                             update_status(reg_acc, 1, 1, 1);\r
2020                         elsif (reg_inst(7 downto 5) = "110") then\r
2021                             --dec\r
2022                             update_status(reg_acc, 1, 1, 0);\r
2023                         elsif (reg_inst(7 downto 5) = "111") then\r
2024                             --inc\r
2025                             update_status(reg_acc, 1, 1, 0);\r
2026                         end if;\r
2027                     end if;\r
2028                 end if;--if (reg_sub_state = ST_SUB30) then\r
2029 \r
2030             --a2 instructions...\r
2031             --adc   cmp     eor     ldy\r
2032             --and   cpx     lda     ora\r
2033             --bit   cpy     ldx     sbc\r
2034             elsif (reg_main_state = ST_A21_T1 or\r
2035                 reg_main_state = ST_A22_T2 or\r
2036                 reg_main_state = ST_A23_T3 or\r
2037                 reg_main_state = ST_A24_T5 or\r
2038                 reg_main_state = ST_A25_T3 or\r
2039                 reg_main_state = ST_A25_T4 or\r
2040                 reg_main_state = ST_A26_T3 or\r
2041                 reg_main_state = ST_A27_T4 or\r
2042                 reg_main_state = ST_A27_T5) then\r
2043                 \r
2044                 --update reg\r
2045                 if (reg_sub_state = ST_SUB30) then\r
2046                     --case cc=01\r
2047                     if (reg_inst(1 downto 0) = "01") then\r
2048                         if (reg_inst(7 downto 5) = "000") then\r
2049                             --ora\r
2050                             reg_acc <= (reg_acc or reg_d_in);\r
2051                         elsif (reg_inst(7 downto 5) = "001") then\r
2052                             --and\r
2053                             reg_acc <= (reg_acc and reg_d_in);\r
2054                         elsif (reg_inst(7 downto 5) = "010") then\r
2055                             --eor\r
2056                             reg_acc <= (reg_acc xor reg_d_in);\r
2057                         elsif (reg_inst(7 downto 5) = "011") then\r
2058                             --adc\r
2059                             calc_res := ("0" & reg_acc) + ("0" & reg_d_in) + reg_status(FL_C);\r
2060                             reg_tmp_carry <= calc_res(8);\r
2061                             if ((reg_acc(7) = reg_d_in(7)) and (reg_acc(7) /= calc_res(7))) then\r
2062                                 reg_tmp_ovf <= '1';\r
2063                             else\r
2064                                 reg_tmp_ovf <= '0';\r
2065                             end if;\r
2066                             reg_acc <= calc_res(7 downto 0);\r
2067                         elsif (reg_inst(7 downto 5) = "101") then\r
2068                             --lda\r
2069                             reg_acc <= reg_d_in;\r
2070                         elsif (reg_inst(7 downto 5) = "110") then\r
2071                             --cmp\r
2072                             --do nothing.\r
2073                         elsif (reg_inst(7 downto 5) = "111") then\r
2074                             --sbc\r
2075                             ---A - M - ~C -> A\r
2076                             calc_res := ("0" & reg_acc) - ("0" & reg_d_in) - not reg_status(FL_C);\r
2077 \r
2078                             --c Set if unsigned borrow not required; cleared if unsigned borrow.\r
2079                             reg_tmp_carry <= not calc_res(8);\r
2080                             --v Set if signed borrow required; cleared if no signed borrow.\r
2081                             if ((reg_acc(7) /= reg_d_in(7)) and (reg_acc(7) /= calc_res(7))) then\r
2082                                 reg_tmp_ovf <= '1';\r
2083                             else\r
2084                                 reg_tmp_ovf <= '0';\r
2085                             end if;\r
2086                             reg_acc <= calc_res(7 downto 0);\r
2087                         end if;\r
2088                     --case cc=10\r
2089                     elsif (reg_inst(1 downto 0) = "10") then\r
2090                         if (reg_inst(7 downto 5) = "101") then\r
2091                             --ldx\r
2092                             reg_x <= reg_d_in;\r
2093                         end if;\r
2094                     --case cc=00\r
2095                     elsif (reg_inst(1 downto 0) = "00") then\r
2096                         if (reg_inst(7 downto 5) = "001") then\r
2097                             --bit\r
2098                             --do nothing.\r
2099                         elsif (reg_inst(7 downto 5) = "101") then\r
2100                             --ldy\r
2101                             reg_y <= reg_d_in;\r
2102                         elsif (reg_inst(7 downto 5) = "110") then\r
2103                             --cpy\r
2104                             --do nothing.\r
2105                         elsif (reg_inst(7 downto 5) = "111") then\r
2106                             --cpx\r
2107                             --do nothing.\r
2108                         end if;\r
2109                     end if;\r
2110 \r
2111                 --update status reg\r
2112                 elsif (reg_sub_state = ST_SUB31) then\r
2113                     --case cc=01\r
2114                     if (reg_inst(1 downto 0) = "01") then\r
2115                         if (reg_inst(7 downto 5) = "000") then\r
2116                             --ora\r
2117                             update_status(reg_acc, 1, 1, 0);\r
2118                         elsif (reg_inst(7 downto 5) = "001") then\r
2119                             --and\r
2120                             update_status(reg_acc, 1, 1, 0);\r
2121                         elsif (reg_inst(7 downto 5) = "010") then\r
2122                             --eor\r
2123                             update_status(reg_acc, 1, 1, 0);\r
2124                         elsif (reg_inst(7 downto 5) = "011") then\r
2125                             --adc\r
2126                             update_status(reg_acc, 1, 1, 1);\r
2127                             reg_status(FL_V) <= reg_tmp_ovf;\r
2128                         elsif (reg_inst(7 downto 5) = "101") then\r
2129                             --lda\r
2130                             update_status(reg_acc, 1, 1, 0);\r
2131                         elsif (reg_inst(7 downto 5) = "110") then\r
2132                             --cmp\r
2133                             calc_res := (("0" & reg_acc) - ("0" & reg_d_in));\r
2134                             if (reg_acc >= reg_d_in) then\r
2135                                 reg_status(FL_C) <= '1';\r
2136                             else\r
2137                                 reg_status(FL_C) <= '0';\r
2138                             end if;\r
2139                             if (calc_res(7) = '1') then\r
2140                                 reg_status(FL_N) <= '1';\r
2141                             else\r
2142                                 reg_status(FL_N) <= '0';\r
2143                             end if;\r
2144                             if (calc_res = "000000000") then\r
2145                                 reg_status(FL_Z) <= '1';\r
2146                             else\r
2147                                 reg_status(FL_Z) <= '0';\r
2148                             end if;\r
2149                         elsif (reg_inst(7 downto 5) = "111") then\r
2150                             --sbc\r
2151                             update_status(reg_acc, 1, 1, 1);\r
2152                             reg_status(FL_V) <= reg_tmp_ovf;\r
2153                         end if;\r
2154                     --case cc=10\r
2155                     elsif (reg_inst(1 downto 0) = "10") then\r
2156                         if (reg_inst(7 downto 5) = "101") then\r
2157                             --ldx\r
2158                             update_status(reg_x, 1, 1, 0);\r
2159                         end if;\r
2160                     --case cc=00\r
2161                     elsif (reg_inst(1 downto 0) = "00") then\r
2162                         if (reg_inst(7 downto 5) = "001") then\r
2163                             --bit\r
2164                             calc_res(7 downto 0) := (reg_acc and reg_d_in);\r
2165                             reg_status(FL_N) <= reg_d_in(7);\r
2166                             reg_status(FL_V) <= reg_d_in(6);\r
2167                             if (calc_res(7 downto 0) = "00000000") then\r
2168                                 reg_status(FL_Z) <= '1';\r
2169                             else\r
2170                                 reg_status(FL_Z) <= '0';\r
2171                             end if;\r
2172                         elsif (reg_inst(7 downto 5) = "101") then\r
2173                             --ldy\r
2174                             update_status(reg_y, 1, 1, 0);\r
2175                         elsif (reg_inst(7 downto 5) = "110") then\r
2176                             --cpy\r
2177                             calc_res := (("0" & reg_y) - ("0" & reg_d_in));\r
2178                             if (reg_y >= reg_d_in) then\r
2179                                 reg_status(FL_C) <= '1';\r
2180                             else\r
2181                                 reg_status(FL_C) <= '0';\r
2182                             end if;\r
2183                             if (calc_res(7) = '1') then\r
2184                                 reg_status(FL_N) <= '1';\r
2185                             else\r
2186                                 reg_status(FL_N) <= '0';\r
2187                             end if;\r
2188                             if (calc_res = "000000000") then\r
2189                                 reg_status(FL_Z) <= '1';\r
2190                             else\r
2191                                 reg_status(FL_Z) <= '0';\r
2192                             end if;\r
2193                         elsif (reg_inst(7 downto 5) = "111") then\r
2194                             --cpx\r
2195                             calc_res := (("0" & reg_x) - ("0" & reg_d_in));\r
2196                             if (reg_x >= reg_d_in) then\r
2197                                 reg_status(FL_C) <= '1';\r
2198                             else\r
2199                                 reg_status(FL_C) <= '0';\r
2200                             end if;\r
2201                             if (calc_res(7) = '1') then\r
2202                                 reg_status(FL_N) <= '1';\r
2203                             else\r
2204                                 reg_status(FL_N) <= '0';\r
2205                             end if;\r
2206                             if (calc_res = "000000000") then\r
2207                                 reg_status(FL_Z) <= '1';\r
2208                             else\r
2209                                 reg_status(FL_Z) <= '0';\r
2210                             end if;\r
2211                         end if;\r
2212                     end if;\r
2213                 end if;--if (reg_sub_state = ST_SUB30) then\r
2214 \r
2215            --a4 instructions.\r
2216            --asl    lsr\r
2217            --dec    rol\r
2218            --inc    ror\r
2219             elsif (reg_main_state = ST_A41_T2 or\r
2220                 reg_main_state = ST_A42_T3 or\r
2221                 reg_main_state = ST_A43_T3 or\r
2222                 reg_main_state = ST_A44_T4\r
2223                 ) then\r
2224                 --data fetch cycle.\r
2225                 reg_tmp_data <= reg_d_in;\r
2226 \r
2227             elsif (reg_main_state = ST_A41_T4 or\r
2228                 reg_main_state = ST_A42_T5 or\r
2229                 reg_main_state = ST_A43_T5 or\r
2230                 reg_main_state = ST_A44_T6\r
2231                 ) then\r
2232                 --data modify cycle.\r
2233 \r
2234                 --update reg\r
2235                 if (reg_sub_state = ST_SUB10) then\r
2236                     --case cc=10\r
2237                     if (reg_inst(1 downto 0) = "10") then\r
2238                         if (reg_inst(7 downto 5) = "000") then\r
2239                             --asl\r
2240                             reg_tmp_data <= reg_tmp_data(6 downto 0) & "0";\r
2241                             reg_tmp_carry <= reg_tmp_data(7);\r
2242                         elsif (reg_inst(7 downto 5) = "001") then\r
2243                             --rol\r
2244                             reg_tmp_data <= reg_tmp_data(6 downto 0) & reg_status(FL_C);\r
2245                             reg_tmp_carry <= reg_tmp_data(7);\r
2246                         elsif (reg_inst(7 downto 5) = "010") then\r
2247                             --lsr\r
2248                             reg_tmp_data <= "0" & reg_tmp_data(7 downto 1);\r
2249                             reg_tmp_carry <= reg_tmp_data(0);\r
2250                         elsif (reg_inst(7 downto 5) = "011") then\r
2251                             --ror\r
2252                             reg_tmp_data <= reg_status(FL_C) & reg_tmp_data(7 downto 1);\r
2253                             reg_tmp_carry <= reg_tmp_data(0);\r
2254                         elsif (reg_inst(7 downto 5) = "110") then\r
2255                             --dec\r
2256                             reg_tmp_data <= reg_tmp_data - 1;\r
2257                         elsif (reg_inst(7 downto 5) = "111") then\r
2258                             --inc\r
2259                             reg_tmp_data <= reg_tmp_data + 1;\r
2260                         end if;\r
2261                     end if;\r
2262 \r
2263                 --update status reg\r
2264                 elsif (reg_sub_state = ST_SUB20) then\r
2265                     --case cc=10\r
2266                     if (reg_inst(1 downto 0) = "10") then\r
2267                         if (reg_inst(7 downto 5) = "000") then\r
2268                             --asl\r
2269                             update_status(reg_tmp_data, 1, 1, 1);\r
2270                         elsif (reg_inst(7 downto 5) = "001") then\r
2271                             --rol\r
2272                             update_status(reg_tmp_data, 1, 1, 1);\r
2273                         elsif (reg_inst(7 downto 5) = "010") then\r
2274                             --lsr\r
2275                             update_status(reg_tmp_data, 0, 1, 1);\r
2276                         elsif (reg_inst(7 downto 5) = "011") then\r
2277                             --ror\r
2278                             update_status(reg_tmp_data, 1, 1, 1);\r
2279                         elsif (reg_inst(7 downto 5) = "110") then\r
2280                             --dec\r
2281                             update_status(reg_tmp_data, 1, 1, 0);\r
2282                         elsif (reg_inst(7 downto 5) = "111") then\r
2283                             --inc\r
2284                             update_status(reg_tmp_data, 1, 1, 0);\r
2285                         end if;\r
2286                     end if;\r
2287                 end if;\r
2288 \r
2289             --a5 instructions...\r
2290             --plp, pla\r
2291             elsif (reg_main_state = ST_A52_T3) then\r
2292                 --update reg\r
2293                 if (reg_sub_state = ST_SUB30) then\r
2294                     if (reg_inst = conv_std_logic_vector(16#28#, 8)) then\r
2295                         --plp\r
2296                         reg_status <= reg_d_in;\r
2297                     elsif (reg_inst = conv_std_logic_vector(16#68#, 8)) then\r
2298                         --pla\r
2299                         reg_acc <= reg_d_in;\r
2300                     end if;\r
2301 \r
2302                 --update status reg\r
2303                 elsif (reg_sub_state = ST_SUB31) then\r
2304                     if (reg_inst = conv_std_logic_vector(16#68#, 8)) then\r
2305                         --pla\r
2306                         update_status(reg_acc, 1, 1, 0);\r
2307                     end if;\r
2308                 end if;--if (reg_sub_state = ST_SUB30) then\r
2309 \r
2310             --a58 branch inst.\r
2311             --bcc   bne\r
2312             --bcs   bpl\r
2313             --beq   bvc\r
2314             --bmi   bvs\r
2315             elsif (reg_main_state = ST_A58_T1) then\r
2316                 if (reg_sub_state = ST_SUB30) then\r
2317                     if (reg_inst = conv_std_logic_vector(16#90#, 8)) then\r
2318                         --bcc\r
2319                         set_condition_result(FL_C, '0');\r
2320 \r
2321                     elsif (reg_inst = conv_std_logic_vector(16#b0#, 8)) then\r
2322                         --bcs\r
2323                         set_condition_result(FL_C, '1');\r
2324 \r
2325                     elsif (reg_inst = conv_std_logic_vector(16#f0#, 8)) then\r
2326                         --beq\r
2327                         set_condition_result(FL_Z, '1');\r
2328 \r
2329                     elsif (reg_inst = conv_std_logic_vector(16#30#, 8)) then\r
2330                         --bmi\r
2331                         set_condition_result(FL_N, '1');\r
2332 \r
2333                     elsif (reg_inst = conv_std_logic_vector(16#d0#, 8)) then\r
2334                         --bne\r
2335                         set_condition_result(FL_Z, '0');\r
2336 \r
2337                     elsif (reg_inst = conv_std_logic_vector(16#10#, 8)) then\r
2338                         --bpl\r
2339                         set_condition_result(FL_N, '0');\r
2340 \r
2341                     elsif (reg_inst = conv_std_logic_vector(16#50#, 8)) then\r
2342                         --bvc\r
2343                         set_condition_result(FL_V, '0');\r
2344 \r
2345                     elsif (reg_inst = conv_std_logic_vector(16#70#, 8)) then\r
2346                         --bvs\r
2347                         set_condition_result(FL_V, '1');\r
2348                     end if;\r
2349                 end if;\r
2350 \r
2351             elsif (reg_main_state = ST_A55_T3) then\r
2352                 --rti, pull status reg.\r
2353                 if (reg_sub_state = ST_SUB30) then\r
2354                     reg_status <= reg_d_in;\r
2355                 end if;--if (reg_sub_state = ST_SUB30) then\r
2356 \r
2357 \r
2358             end if;--if (reg_main_state = ST_A21_T1 or...\r
2359         end if;--if (pi_rst_n = '0') then\r
2360     end process;\r
2361 \r
2362     --nmi handled flag process...\r
2363     nmi_handle_p : process (pi_rst_n, pi_base_clk)\r
2364     begin\r
2365         if (pi_rst_n = '0') then\r
2366             reg_nmi_handled <= 0;\r
2367         elsif (rising_edge(pi_base_clk)) then\r
2368             if (pi_nmi_n = '1') then\r
2369                 reg_nmi_handled <= 0;\r
2370             elsif (reg_main_state = ST_NM_T7 and reg_sub_state = ST_SUB73) then\r
2371                 reg_nmi_handled <= 1;\r
2372             end if;\r
2373         end if;--if (pi_rst_n = '0') then\r
2374     end process;\r
2375 \r
2376     --dma flag process...\r
2377     dma_set_p : process (pi_rst_n, pi_base_clk)\r
2378     begin\r
2379         if (pi_rst_n = '0') then\r
2380             reg_dma_set <= 0;\r
2381         elsif (rising_edge(pi_base_clk)) then\r
2382             if (pi_rdy = '0') then\r
2383                 reg_dma_set <= 1;\r
2384             elsif (reg_main_state = ST_CM_T0) then\r
2385                 reg_dma_set <= 0;\r
2386             end if;\r
2387         end if;--if (pi_rst_n = '0') then\r
2388     end process;\r
2389 \r
2390     --debug cnt...\r
2391     po_exc_cnt <= reg_exc_cnt;\r
2392     exc_cnt_p : process (pi_rst_n, pi_base_clk)\r
2393     begin\r
2394         if (pi_rst_n = '0') then\r
2395             reg_exc_cnt <= (others => '0');\r
2396         else\r
2397             if (rising_edge(pi_base_clk)) then\r
2398                 if (reg_main_state = ST_CM_T0 and reg_sub_state = ST_SUB73) then\r
2399                     reg_exc_cnt <= reg_exc_cnt + 1;\r
2400                 elsif (reg_main_state = ST_NM_T7 and reg_sub_state = ST_SUB73) then\r
2401                     --reg_exc_cnt upper 16 bit is nmi count.\r
2402                     --lower 48 bit is cpu exec count from nmi initiated.\r
2403                     reg_exc_cnt(47 downto 0) <= (others => '0');\r
2404                     reg_exc_cnt(63 downto 48) <= reg_exc_cnt(63 downto 48) + 1;\r
2405                 end if;\r
2406             end if;\r
2407         end if;\r
2408     end process;\r
2409 end rtl;\r
2410 \r