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[motonesfpga/motonesfpga.git] / de0_cv_nes / simulation / modelsim / de0_cv_nes_run_msim_rtl_vhdl.do
1 transcript on\r
2 if {[file exists rtl_work]} {\r
3         vdel -lib rtl_work -all\r
4 }\r
5 vlib rtl_work\r
6 vmap work rtl_work\r
7 \r
8 vcom -93 -work work {../../chip_selector.vhd}\r
9 vcom -93 -work work {../../mem/ram.vhd}\r
10 vcom -93 -work work {../../apu.vhd}\r
11 \r
12 vcom -93 -work work {../../mem/chr_rom.vhd}\r
13 vcom -93 -work work {../../ppu/ppu.vhd}\r
14 vcom -93 -work work {../../ppu/render.vhd}\r
15 #vcom -93 -work work {../../dummy-ppu.vhd}\r
16 \r
17 #vcom -93 -work work {../../dummy-mos6502.vhd}\r
18 #vcom -93 -work work {../../dummy-smb-rom.vhd}\r
19 vcom -93 -work work {../../mem/prg_rom.vhd}\r
20 vcom -93 -work work {../../mos6502.vhd}\r
21 \r
22 vcom -93 -work work {../../de0_cv_nes.vhd}\r
23 vcom -93 -work work {../../testbench_motones_sim.vhd}\r
24 \r
25 vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev -L rtl_work -L work -voptargs="+acc"  testbench_motones_sim\r
26 \r
27 \r
28 #################################### General.... ###########################################\r
29 \r
30 #add wave -label dbg_cnt -radix hex  sim:/testbench_motones_sim/sim_board/po_dbg_cnt;\r
31 add wave -label po_exc_cnt -radix hex  sim:/testbench_motones_sim/sim_board/po_exc_cnt;\r
32 add wave -label rst_n               sim:/testbench_motones_sim/sim_board/pi_rst_n;\r
33 add wave -label wr_nmi_n            sim:/testbench_motones_sim/sim_board/wr_nmi_n;\r
34 #add wave -label base_clk            sim:/testbench_motones_sim/sim_board/pi_base_clk;\r
35 #add wave -label wr_cpu_en           sim:/testbench_motones_sim/sim_board/wr_cpu_en;\r
36 add wave -label wr_cpu_en           sim:/testbench_motones_sim/sim_board/wr_cpu_en(0);\r
37 add wave -label wr_oe_n             sim:/testbench_motones_sim/sim_board/wr_oe_n;\r
38 add wave -label wr_we_n             sim:/testbench_motones_sim/sim_board/wr_we_n;\r
39 add wave -label addr -radix hex     sim:/testbench_motones_sim/sim_board/wr_addr;\r
40 add wave -label d_io -radix hex     sim:/testbench_motones_sim/sim_board/wr_d_io;\r
41 \r
42 #################################### CPU part.... ###########################################\r
43 \r
44 #add wave -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/reg*;\r
45 add wave -divider cpu\r
46 \r
47 add wave -label reg_inst -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/reg_inst;\r
48 add wave -label reg_acc -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/reg_acc;\r
49 add wave -label reg_x -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/reg_x;\r
50 add wave -label reg_y -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/reg_y;\r
51 add wave -label reg_sp -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/reg_sp;\r
52 add wave -label reg_status -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/reg_status;\r
53 \r
54 #add wave -divider internal_reg\r
55 #add wave -label reg_main_cur_state  sim:/testbench_motones_sim/sim_board/cpu_inst/reg_main_state;\r
56 ##add wave -label reg_sub_cur_state   sim:/testbench_motones_sim/sim_board/cpu_inst/reg_sub_state;\r
57 #add wave -label reg_pc_l -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/reg_pc_l;\r
58 #add wave -label reg_pc_h -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/reg_pc_h;\r
59 #add wave -label reg_idl_l -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/reg_idl_l;\r
60 #add wave -label reg_idl_h -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/reg_idl_h;\r
61 #add wave -label reg_tmp_pg_crossed  sim:/testbench_motones_sim/sim_board/cpu_inst/reg_tmp_pg_crossed;\r
62 \r
63 \r
64 ##################################### APU part.... ###########################################\r
65 #add wave -divider apu\r
66 #add wave -label wr_rdy  sim:/testbench_motones_sim/sim_board/wr_rdy;\r
67 #add wave -label reg_dma_cur_state   sim:/testbench_motones_sim/sim_board/apu_inst/reg_dma_cur_state;\r
68 #add wave -label reg_dma_addr -radix hex     sim:/testbench_motones_sim/sim_board/apu_inst/reg_dma_addr;\r
69 ##add wave -label pi_rnd_en  sim:/testbench_motones_sim/sim_board/apu_inst/pi_rnd_en;\r
70 ##add wave -label reg_dma_cnt sim:/testbench_motones_sim/sim_board/apu_inst/reg_dma_cnt;\r
71 #\r
72 #add wave -label reg_spr_ce_n  sim:/testbench_motones_sim/sim_board/apu_inst/reg_spr_ce_n;\r
73 #add wave -label reg_spr_rd_n  sim:/testbench_motones_sim/sim_board/apu_inst/reg_spr_rd_n;\r
74 #add wave -label reg_spr_wr_n  sim:/testbench_motones_sim/sim_board/apu_inst/reg_spr_wr_n;\r
75 #add wave -label reg_spr_addr -radix hex  sim:/testbench_motones_sim/sim_board/apu_inst/reg_spr_addr;\r
76 #add wave -label reg_spr_data -radix hex  sim:/testbench_motones_sim/sim_board/apu_inst/reg_spr_data;\r
77 #\r
78 #\r
79 #\r
80 #view structure\r
81 #view signals\r
82 #\r
83 #run 25 us\r
84 #wave zoom full\r
85 #\r
86 #run 900 us\r
87 \r
88 \r
89 #################################### PPU part.... ###########################################\r
90 add wave -divider ppu\r
91 add wave -label pi_ce_n         -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/pi_ce_n;\r
92 add wave -label ppu_ctrl        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_ctrl;\r
93 add wave -label ppu_mask        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_mask;\r
94 add wave -label ppu_status      -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/pi_ppu_status;\r
95 add wave -label oam_addr        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_oam_addr;\r
96 add wave -label oam_data        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_oam_data;\r
97 add wave -label ppu_scroll_x    -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_scroll_x;\r
98 add wave -label ppu_scroll_y    -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_scroll_y;\r
99 add wave -label ppu_addr        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_addr;\r
100 add wave -label ppu_data        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_data;\r
101 #add wave -label reg_v_cur_state            sim:/testbench_motones_sim/sim_board/ppu_inst/reg_v_cur_state;\r
102 \r
103 add wave -divider vram\r
104 add wave -label v_rd_n        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_rd_n;\r
105 add wave -label v_wr_n        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_wr_n;\r
106 add wave -label vram_addr        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_addr;\r
107 add wave -label vram_data        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_data;\r
108 \r
109 add wave -divider render\r
110 #add wave -label vga_x       sim:/testbench_motones_sim/sim_board/render_inst/reg_vga_x;\r
111 #add wave -label vga_y       sim:/testbench_motones_sim/sim_board/render_inst/reg_vga_y;\r
112 add wave -label nes_x       sim:/testbench_motones_sim/sim_board/render_inst/reg_nes_x;\r
113 add wave -label nes_y       sim:/testbench_motones_sim/sim_board/render_inst/reg_nes_y;\r
114 \r
115 #\r
116 #add wave -divider bg\r
117 ##add wave -label wr_rnd_en  sim:/testbench_motones_sim/sim_board/wr_rnd_en;\r
118 #add wave -label reg_v_cur_state sim:/testbench_motones_sim/sim_board/render_inst/reg_v_cur_state;\r
119 ##add wave -label prf_x       sim:/testbench_motones_sim/sim_board/render_inst/reg_prf_x;\r
120 ##add wave -label prf_y       sim:/testbench_motones_sim/sim_board/render_inst/reg_prf_y;\r
121 #\r
122 #add wave -label disp_nt -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_disp_nt;\r
123 #add wave -label disp_attr   -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_disp_attr;\r
124 #add wave -label sft_ptn_l -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_sft_ptn_l;\r
125 #add wave -label sft_ptn_h -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_sft_ptn_h;\r
126 #\r
127 #add wave -divider sprite\r
128 #add wave -label reg_s_oam_cur_state sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_cur_state;\r
129 #add wave -label reg_s_oam_ce_n  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_ce_n;\r
130 #add wave -label reg_s_oam_rd_n  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_rd_n;\r
131 #add wave -label reg_s_oam_wr_n  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_wr_n;\r
132 #add wave -label reg_s_oam_addr -radix hex  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_addr;\r
133 #add wave -label reg_s_oam_data -radix hex  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_data;\r
134 #\r
135 ##add wave -label reg_s_oam_cpy_cnt   sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_cpy_cnt;\r
136 ##add wave -label reg_p_oam_cpy_cnt   sim:/testbench_motones_sim/sim_board/render_inst/reg_p_oam_cpy_cnt;\r
137 ##add wave -label reg_spr_eval_cnt    sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_eval_cnt;\r
138 #\r
139 #add wave -label wr_spr_ce_n  sim:/testbench_motones_sim/sim_board/wr_spr_ce_n;\r
140 #add wave -label wr_spr_rd_n  sim:/testbench_motones_sim/sim_board/wr_spr_rd_n;\r
141 #add wave -label wr_spr_wr_n  sim:/testbench_motones_sim/sim_board/wr_spr_wr_n;\r
142 #add wave -label wr_spr_addr -radix hex  sim:/testbench_motones_sim/sim_board/wr_spr_addr;\r
143 #add wave -label wr_spr_data -radix hex  sim:/testbench_motones_sim/sim_board/wr_spr_data;\r
144 #\r
145 #add wave -label reg_spr_y_tmp -radix hex    sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_y_tmp;\r
146 #add wave -label reg_spr_tile_tmp -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_tile_tmp;\r
147 #add wave -label reg_spr_attr -radix hex     sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_attr;\r
148 #add wave -label reg_spr_x -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_x;\r
149 #add wave -label reg_spr_ptn_sft_start -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_ptn_sft_start;\r
150 #add wave -label reg_spr_ptn_l -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_ptn_l;\r
151 #add wave -label reg_spr_ptn_h -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_ptn_h;\r
152 #\r
153 #add wave -divider palette\r
154 #add wave -label plt_addr -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_plt_addr;\r
155 #add wave -label plt_data -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_plt_data;\r
156 \r
157 \r
158 add wave -divider vga\r
159 add wave -label h_sync_n       sim:/testbench_motones_sim/sim_board/po_h_sync_n;\r
160 add wave -label v_sync_n    sim:/testbench_motones_sim/sim_board/po_v_sync_n;\r
161 add wave -label r -radix hex sim:/testbench_motones_sim/sim_board/po_r;\r
162 add wave -label g -radix hex sim:/testbench_motones_sim/sim_board/po_g;\r
163 add wave -label b -radix hex sim:/testbench_motones_sim/sim_board/po_b;\r
164 \r
165 \r
166 \r
167 view structure\r
168 view signals\r
169 \r
170 run 15 us\r
171 wave zoom full\r
172 \r