added vram access register. currently bg displayed is broken.

diff --git a/de0_cv_nes/de0_cv_nes.qsf b/de0_cv_nes/de0_cv_nes.qsf
index 683211e..be9933b 100644 (file)
--- a/de0_cv_nes/de0_cv_nes.qsf
+++ b/de0_cv_nes/de0_cv_nes.qsf
@@ -620,5 +620,5 @@ set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -t
 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "counter_register:clock_counter_inst|\\clk_p:q_out[8]" -section_id auto_signaltap_0\r
 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "counter_register:clock_counter_inst|\\clk_p:q_out[9]" -section_id auto_signaltap_0\r
 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=65505" -section_id auto_signaltap_0\r
-set_global_assignment -name SLD_FILE "D:/daisuke/nes/repo/motonesfpga/de0_cv_nes/de0-cv-analyze-all_auto_stripped.stp"\r
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top\r
+set_global_assignment -name SLD_FILE "D:/daisuke/nes/repo/motonesfpga/de0_cv_nes/de0-cv-analyze-all_auto_stripped.stp"
\ No newline at end of file

diff --git a/de1_nes/mem/chr_rom.vhd b/de1_nes/mem/chr_rom.vhd
index e204125..87c8f85 100644 (file)
--- a/de1_nes/mem/chr_rom.vhd
+++ b/de1_nes/mem/chr_rom.vhd
@@ -50,12 +50,12 @@ function rom_fill return rom_array is
 
 --for GHDL environment
 --itinialize with the rom_fill function.
---signal p_rom : rom_array := rom_fill;
+signal p_rom : rom_array := rom_fill;
 
 --for Quartus II environment
-signal p_rom : rom_array;
-attribute ram_init_file : string;
-attribute ram_init_file of p_rom : signal is "sample1-chr.hex";
+--signal p_rom : rom_array;
+--attribute ram_init_file : string;
+--attribute ram_init_file of p_rom : signal is "sample1-chr.hex";
 
 begin
     

diff --git a/de1_nes/ppu/vga_ppu.vhd b/de1_nes/ppu/vga_ppu.vhd
index 7695f3a..3ca802e 100644 (file)
--- a/de1_nes/ppu/vga_ppu.vhd
+++ b/de1_nes/ppu/vga_ppu.vhd
@@ -214,7 +214,9 @@ signal io_cnt           : std_logic_vector(0 downto 0);
 --bg prefetch position (scroll + 16 cycle ahead of current pos)\r
 --511 x 239 (or 255 x 479)\r
 signal prf_x            : std_logic_vector(X_SIZE - 1 downto 0);\r
+signal prf_x_cnt        : std_logic_vector(X_SIZE - 1 downto 0);\r
 signal prf_y            : std_logic_vector(X_SIZE - 1 downto 0);\r
+signal vram_addr_in     : std_logic_vector (13 downto 0);\r
 \r
 signal nt_we_n          : std_logic;\r
 signal disp_nt          : std_logic_vector (dsize - 1 downto 0);\r
@@ -567,17 +569,36 @@ begin
     io_cnt_inst : counter_register generic map (1, 1)\r
             port map (emu_ppu_clk, io_cnt_rst_n, '0', '1', (others => '0'), io_cnt);\r
 \r
+    io_scr_cnt_inst : d_flip_flop generic map(X_SIZE)\r
+            port map (emu_ppu_clk, rst_n, '1', '0', prf_x, prf_x_cnt);\r
+\r
     ale_n <= \r
+            not prf_x_cnt(0) when (\r
+                ppu_mask(PPUSBG) = '1' and\r
+                (nes_x <= conv_std_logic_vector(HSCAN, X_SIZE) or\r
+                nes_x >= conv_std_logic_vector(HSCAN_NEXT_START, X_SIZE)) and\r
+                (nes_y < conv_std_logic_vector(VSCAN, X_SIZE) or \r
+                nes_y = conv_std_logic_vector(VSCAN_NEXT_START, X_SIZE))) else\r
             not io_cnt(0) when (\r
-                ((ppu_mask(PPUSBG) = '1' or ppu_mask(PPUSSP) = '1') and\r
+                ppu_mask(PPUSSP) = '1' and\r
+                (nes_x > conv_std_logic_vector(HSCAN, X_SIZE) and \r
+                nes_x <= conv_std_logic_vector(HSCAN_SPR_MAX, X_SIZE)) and\r
                 (nes_y < conv_std_logic_vector(VSCAN, X_SIZE) or \r
-                nes_y = conv_std_logic_vector(VSCAN_NEXT_START, X_SIZE)))) else\r
+                nes_y = conv_std_logic_vector(VSCAN_NEXT_START, X_SIZE))) else\r
             '1'; --else no latch, keep addr val.\r
     rd_n <= \r
+            prf_x_cnt(0) when (\r
+                ppu_mask(PPUSBG) = '1' and\r
+                (nes_x <= conv_std_logic_vector(HSCAN, X_SIZE) or\r
+                nes_x >= conv_std_logic_vector(HSCAN_NEXT_START, X_SIZE)) and\r
+                (nes_y < conv_std_logic_vector(VSCAN, X_SIZE) or \r
+                nes_y = conv_std_logic_vector(VSCAN_NEXT_START, X_SIZE))) else\r
             io_cnt(0) when (\r
-                ((ppu_mask(PPUSBG) = '1' or ppu_mask(PPUSSP) = '1') and\r
+                ppu_mask(PPUSSP) = '1' and\r
+                (nes_x > conv_std_logic_vector(HSCAN, X_SIZE) and \r
+                nes_x <= conv_std_logic_vector(HSCAN_SPR_MAX, X_SIZE)) and\r
                 (nes_y < conv_std_logic_vector(VSCAN, X_SIZE) or \r
-                nes_y = conv_std_logic_vector(VSCAN_NEXT_START, X_SIZE)))) else\r
+                nes_y = conv_std_logic_vector(VSCAN_NEXT_START, X_SIZE))) else\r
             '1';\r
     wr_n <= \r
             '1' when (\r
@@ -993,41 +1014,42 @@ begin
                     d_print("*");\r
                     d_print("nes_x: " & conv_hex16(conv_integer(nes_x)));\r
                     d_print("nes_y: " & conv_hex16(conv_integer(nes_y)));\r
+                    --all cycls is delayed by two clocks.\r
 \r
                     ----fetch next tile byte.\r
-                    if (nes_x (2 downto 0) = "010") then\r
+                    if (prf_x (2 downto 0) = "100") then\r
                         nt_we_n <= '0';\r
                     else\r
                         nt_we_n <= '1';\r
                     end if;\r
 \r
                     ----fetch attr table byte.\r
-                    if (nes_x (4 downto 0) = "00100") then\r
+                    if (prf_x (4 downto 0) = "00110") then\r
                         attr_we_n <= '0';\r
                     else\r
                         attr_we_n <= '1';\r
                     end if;\r
-                    if (nes_x (4 downto 0) = "10000") then\r
+                    if (prf_x (4 downto 0) = "10010") then\r
                         disp_attr_we_n <= '0';\r
                     else\r
                         disp_attr_we_n <= '1';\r
                     end if;\r
                     ---attribute is shifted every 16 bit.\r
-                    if (nes_x (3 downto 0) = "0000") then\r
+                    if (prf_x (3 downto 0) = "0010") then\r
                         attr_ce_n <= '0';\r
                     else\r
                         attr_ce_n <= '1';\r
                     end if;\r
 \r
                     ----fetch pattern table low byte.\r
-                    if (nes_x (2 downto 0) = "110") then\r
+                    if (prf_x (2 downto 0) = "000") then\r
                          ptn_l_we_n <= '0';\r
                     else\r
                          ptn_l_we_n <= '1';\r
                     end if;\r
 \r
                     ----fetch pattern table high byte.\r
-                    if (nes_x (2 downto 0) = "000") then\r
+                    if (prf_x (2 downto 0) = "010") then\r
                          ptn_h_we_n <= '0';\r
                     else\r
                          ptn_h_we_n <= '1';\r
@@ -1049,10 +1071,13 @@ begin
     -----------------------------------------\r
     ---vram addr access process\r
     -----------------------------------------\r
+    vaddr_inst : d_flip_flop generic map(asize)\r
+            port map (emu_ppu_clk, rst_n, '1', '0', vram_addr_in, vram_addr);\r
+\r
     vaddr_p : process (rst_n, emu_ppu_clk)\r
     begin\r
         if (rst_n = '0') then\r
-            vram_addr <= (others => 'Z');\r
+            vram_addr_in <= (others => 'Z');\r
         else\r
             if (rising_edge(emu_ppu_clk)) then\r
 \r
@@ -1063,39 +1088,37 @@ begin
                     --bg pattern fetch.\r
                     --------------------------\r
                     if (ppu_mask(PPUSBG) = '1' and (\r
-                        (nes_x > conv_std_logic_vector(0, X_SIZE) and \r
-                         nes_x <= conv_std_logic_vector(HSCAN, X_SIZE))\r
-                         or\r
-                        (nes_x >= conv_std_logic_vector(HSCAN_NEXT_START, X_SIZE))\r
+                        (nes_x <= conv_std_logic_vector(HSCAN, X_SIZE) or\r
+                        nes_x >= conv_std_logic_vector(HSCAN_NEXT_START, X_SIZE))\r
                         )) then\r
 \r
                         ----fetch next tile byte.\r
-                        if (nes_x (2 downto 0) = "001") then\r
+                        if (prf_x (2 downto 0) = "011") then\r
                             --vram addr is incremented every 8 cycle.\r
                             --name table at 0x2000\r
-                            vram_addr(9 downto 0) \r
+                            vram_addr_in(9 downto 0) \r
                                 <= prf_y(dsize - 1 downto 3) \r
                                     & prf_x(dsize - 1 downto 3);\r
-                            vram_addr(asize - 1 downto 10) <= "10" & ppu_ctrl(PPUBNA downto 0) \r
+                            vram_addr_in(asize - 1 downto 10) <= "10" & ppu_ctrl(PPUBNA downto 0) \r
                                                             + ("000" & prf_x(dsize));\r
                         ----fetch attr table byte.\r
-                        elsif (nes_x (2 downto 0) = "011") then\r
+                        elsif (prf_x (2 downto 0) = "101") then\r
                             --attr table at 0x23c0\r
-                            vram_addr(dsize - 1 downto 0) <= "11000000" +\r
+                            vram_addr_in(dsize - 1 downto 0) <= "11000000" +\r
                                     ("00" & prf_y(7 downto 5) & prf_x(7 downto 5));\r
-                            vram_addr(asize - 1 downto dsize) <= "10" &\r
+                            vram_addr_in(asize - 1 downto dsize) <= "10" &\r
                                     ppu_ctrl(PPUBNA downto 0) & "11"\r
                                         + ("000" & prf_x(dsize) & "00");\r
                         ----fetch pattern table low byte.\r
-                        elsif (nes_x (2 downto 0) = "101") then\r
+                        elsif (prf_x (2 downto 0) = "111") then\r
                              --vram addr is incremented every 8 cycle.\r
-                             vram_addr <= "0" & ppu_ctrl(PPUBPA) & \r
+                             vram_addr_in <= "0" & ppu_ctrl(PPUBPA) & \r
                                                   disp_nt(dsize - 1 downto 0) \r
                                                         & "0"  & prf_y(2  downto 0);\r
                         ----fetch pattern table high byte.\r
-                        elsif (nes_x (2 downto 0) = "111") then\r
+                        elsif (prf_x (2 downto 0) = "001") then\r
                              --vram addr is incremented every 8 cycle.\r
-                             vram_addr <= "0" & ppu_ctrl(PPUBPA) & \r
+                             vram_addr_in <= "0" & ppu_ctrl(PPUBPA) & \r
                                                   disp_nt(dsize - 1 downto 0) \r
                                                         & "0"  & prf_y(2 downto 0) + "00000000001000";\r
                         end if;\r
@@ -1103,43 +1126,45 @@ begin
                     --------------------------\r
                     --sprite pattern fetch.\r
                     --------------------------\r
-                    elsif (ppu_mask(PPUSSP) = '1' and (nes_x > conv_std_logic_vector(HSCAN, X_SIZE) and \r
-                        nes_x <= conv_std_logic_vector(HSCAN_SPR_MAX, X_SIZE))) then\r
+                    elsif (ppu_mask(PPUSSP) = '1' and (\r
+                        nes_x > conv_std_logic_vector(HSCAN, X_SIZE) and \r
+                        nes_x <= conv_std_logic_vector(HSCAN_SPR_MAX, X_SIZE))\r
+                        ) then\r
                         \r
                         ----fetch pattern table low byte.\r
-                        if (nes_x (2 downto 0) = "101" ) then\r
+                        if (nes_x (2 downto 0) = "111" ) then\r
                             if (spr_attr(conv_integer(s_oam_addr_cpy(4 downto 2)))(SPRVFL) = '0') then\r
-                                vram_addr <= "0" & ppu_ctrl(PPUSPA) & \r
+                                vram_addr_in <= "0" & ppu_ctrl(PPUSPA) & \r
                                             spr_tile_tmp(dsize - 1 downto 0) & "0" & \r
                                             (nes_y(2 downto 0) + "001" - spr_y_tmp(2 downto 0));\r
                             else\r
                                 --flip sprite vertically.\r
-                                vram_addr <= "0" & ppu_ctrl(PPUSPA) & \r
+                                vram_addr_in <= "0" & ppu_ctrl(PPUSPA) & \r
                                             spr_tile_tmp(dsize - 1 downto 0) & "0" & \r
                                             (spr_y_tmp(2 downto 0) - nes_y(2 downto 0) - "010");\r
                             end if;\r
                         \r
                         ----fetch pattern table high byte.\r
-                        elsif (nes_x (2 downto 0) = "111" ) then\r
+                        elsif (nes_x (2 downto 0) = "001" ) then\r
                             if (spr_attr(conv_integer(s_oam_addr_cpy(4 downto 2)))(SPRVFL) = '0') then\r
-                                vram_addr <= "0" & ppu_ctrl(PPUSPA) & \r
+                                vram_addr_in <= "0" & ppu_ctrl(PPUSPA) & \r
                                             spr_tile_tmp(dsize - 1 downto 0) & "0" & \r
                                             (nes_y(2 downto 0) + "001" - spr_y_tmp(2 downto 0))\r
                                                 + "00000000001000";\r
                             else\r
                                 --flip sprite vertically.\r
-                                vram_addr <= "0" & ppu_ctrl(PPUSPA) & \r
+                                vram_addr_in <= "0" & ppu_ctrl(PPUSPA) & \r
                                             spr_tile_tmp(dsize - 1 downto 0) & "0"  & \r
                                             (spr_y_tmp(2 downto 0) - nes_y(2 downto 0) - "010")\r
                                                 + "00000000001000";\r
                             end if;\r
                         end if;\r
                     else\r
-                        vram_addr <= (others => 'Z');\r
+                        vram_addr_in <= (others => 'Z');\r
                     end if; --if (nes_x > conv_std_logic_vector(HSCAN, X_SIZE) and \r
                                 --nes_x <= conv_std_logic_vector(HSCAN_SPR_MAX, X_SIZE)) then\r
                 else\r
-                    vram_addr <= (others => 'Z');\r
+                    vram_addr_in <= (others => 'Z');\r
                 end if; --(nes_y < conv_std_logic_vector(VSCAN, X_SIZE) or \r
                         --nes_y = conv_std_logic_vector(VSCAN_NEXT_START, X_SIZE))) then\r
             end if; --if (rising_edge(emu_ppu_clk)) then\r

diff --git a/de1_nes/simulation/modelsim/de1_nes_run_msim_rtl_vhdl.do b/de1_nes/simulation/modelsim/de1_nes_run_msim_rtl_vhdl.do
index 75f5496..ec02d7e 100644 (file)
--- a/de1_nes/simulation/modelsim/de1_nes_run_msim_rtl_vhdl.do
+++ b/de1_nes/simulation/modelsim/de1_nes_run_msim_rtl_vhdl.do
@@ -91,11 +91,13 @@ add wave -divider ppu
 \r
 #add wave  -radix hex  sim:/testbench_motones_sim/sim_board/ppu_inst/*\r
 #add wave  -radix hex  sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/*\r
-add wave  -label prf_x -radix decimal sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/prf_x\r
+\r
 \r
 #add wave -radix hex sim:/testbench_motones_sim/sim_board/vram_latch/*\r
 #add wave -label v_addr_ppu -radix hex sim:/testbench_motones_sim/sim_board/v_addr_ppu\r
 \r
+add wave -label vram_addr_in -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/vram_addr_in\r
+add wave -label vram_addr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/vram_addr\r
 \r
 \r
 view structure\r