dma data copy cpu side ok.

diff --git a/simulation/apu/apu.vhd b/simulation/apu/apu.vhd
index 8717f52..b2e4d04 100644 (file)
--- a/simulation/apu/apu.vhd
+++ b/simulation/apu/apu.vhd
@@ -6,7 +6,7 @@ entity apu is
             ce_n        : in std_logic;
             rst_n       : in std_logic;
             r_nw        : in std_logic;
-            cpu_addr    : in std_logic_vector (4 downto 0);
+            cpu_addr    : inout std_logic_vector (15 downto 0);
             cpu_d       : inout std_logic_vector (7 downto 0);
             vram_ad     : inout std_logic_vector (7 downto 0);
             vram_a      : out std_logic_vector (13 downto 8);
@@ -55,10 +55,8 @@ begin
 end  procedure;
 
 constant dsize     : integer := 8;
-
 constant OAM_DMA   : std_logic_vector(4 downto 0) := "10100";
 
-
 signal clk_n            : std_logic;
 
 signal oam_addr         : std_logic_vector (dsize - 1 downto 0);
@@ -68,7 +66,6 @@ signal oam_bus_ce_n     : std_logic;
 
 signal dma_addr         : std_logic_vector (dsize * 2 - 1 downto 0);
 signal dma_cnt_ce_n     : std_logic_vector(0 downto 0);
-signal dma_cnt_ce       : std_logic;
 signal dma_start_n      : std_logic;
 signal dma_end_n        : std_logic;
 signal dma_process_n    : std_logic;
@@ -84,16 +81,13 @@ begin
 
     clk_n <= not clk;
 
-    dma_cnt_ce <= not dma_cnt_ce_n(0);
-
-
     dma_rst_n <= not dma_process_n;
 
     dma_l_up_inst : counter_register generic map (1, 1)
             port map (clk_n, dma_rst_n, dma_process_n, '1', (others => '0'), dma_cnt_ce_n);
 
     dma_l_inst : counter_register generic map (dsize, 1)
-            port map (clk_n, dma_rst_n, dma_cnt_ce, '1', (others => '0'), 
+            port map (clk, dma_rst_n, dma_cnt_ce_n(0), '1', (others => '0'), 
                                                 dma_addr(dsize - 1 downto 0));
     dma_h_inst : d_flip_flop generic map(dsize)
             port map (clk_n, '1', '1', dma_start_n, cpu_d, 
@@ -102,11 +96,17 @@ begin
     dma_status_inst : d_flip_flop generic map(1)
             port map (clk_n, rst_n, '1', dma_status_we_n, dma_next_status, dma_status);
 
+    dma_val_inst : d_flip_flop generic map(dsize)
+            port map (clk_n, rst_n, '1', dma_process_n, cpu_d, oam_data);
+
+    cpu_addr <= dma_addr when dma_process_n = '0' else
+                (others => 'Z');
+
     --apu register access process
     reg_set_p : process (rst_n, ce_n, r_nw, cpu_addr, cpu_d)
     begin
         if (rst_n = '1' and ce_n = '0') then
-            if(cpu_addr = OAM_DMA) then
+            if(cpu_addr(4 downto 0) = OAM_DMA and r_nw = '0') then
                 dma_start_n <= '0';
             else
                 dma_start_n <= '1';
@@ -142,20 +142,20 @@ begin
                         dma_status_we_n <= '0';
                         dma_next_status <= DMA_ST_PROCESS;
                     end if;
+                    dma_process_n <= '1';
                     dma_end_n <= '1';
                 elsif (dma_status = DMA_ST_PROCESS) then
                     if (dma_addr(dsize - 1 downto 0) = "11111111" and dma_cnt_ce_n(0) = '1') then
                         dma_status_we_n <= '0';
                         dma_next_status <= DMA_ST_IDLE;
                         dma_end_n <= '0';
-                        dma_process_n <= '1';
                     else
                         dma_status_we_n <= '1';
                         dma_process_n <= '0';
                         dma_end_n <= '1';
                     end if;
-                end if;
-            end if;
+                end if;--if (dma_status = DMA_ST_IDLE) then
+            end if;--if (clk'event and clk = '1') then
         end if;
     end process;
 

diff --git a/simulation/cpu/decoder.vhd b/simulation/cpu/decoder.vhd
index dd54712..ccccacb 100644 (file)
--- a/simulation/cpu/decoder.vhd
+++ b/simulation/cpu/decoder.vhd
@@ -1037,7 +1037,7 @@ end  procedure;
             if rdy = '0' then
                 disable_pins;
                 inst_we_n <= '1';
-                ad_oe_n <= '1';
+                ad_oe_n <= '0';
                 dl_al_oe_n <= '1';
                 pcl_inc_n <= '1';
                 pcl_cmd <= "1111";

diff --git a/simulation/motones_sim.vhd b/simulation/motones_sim.vhd
index 5fc1584..3c1cfee 100644 (file)
--- a/simulation/motones_sim.vhd
+++ b/simulation/motones_sim.vhd
@@ -99,7 +99,7 @@ architecture rtl of motones_sim is
                 ce_n        : in std_logic;
                 rst_n       : in std_logic;
                 r_nw        : in std_logic;
-                cpu_addr    : in std_logic_vector (4 downto 0);
+                cpu_addr    : inout std_logic_vector (15 downto 0);
                 cpu_d       : inout std_logic_vector (7 downto 0);
                 vram_ad     : inout std_logic_vector (7 downto 0);
                 vram_a      : out std_logic_vector (13 downto 8);
@@ -185,7 +185,7 @@ begin
         port map (ppu_clk, rd_n, wr_n, ale, vram_ad, vram_a);
 
     apu_inst : apu
-        port map (cpu_clk, apu_ce_n, rst_n, r_nw, addr(4 downto 0), d_io, 
+        port map (cpu_clk, apu_ce_n, rst_n, r_nw, addr, d_io, 
                 vram_ad, vram_a, rdy);
 
     dummy_vga_disp : vga_device