module structure re-organized

diff --git a/simulation/Makefile b/simulation/Makefile
index 43d415e..c554620 100644 (file)
--- a/simulation/Makefile
+++ b/simulation/Makefile
@@ -1,4 +1,4 @@
-DIRS=mem ppu apu cpu clock
+DIRS=mem cpu ppu apu clock
 MODULES=motonesfpga_common.vhd address_decoder.vhd motones_sim.vhd 
 WORKDIR=work
 TEST_MODULE = testbench_motones_sim.vhd

diff --git a/simulation/address_decoder.vhd b/simulation/address_decoder.vhd
index 36eed8c..e3ca360 100644 (file)
--- a/simulation/address_decoder.vhd
+++ b/simulation/address_decoder.vhd
@@ -81,8 +81,12 @@ generic (abus_size : integer := 14; dbus_size : integer := 8);
             rd_n        : in std_logic;
             wr_n        : in std_logic;
             ale         : in std_logic;
-            vram_ad     : inout std_logic_vector (7 downto 0);
-            vram_a      : in std_logic_vector (13 downto 8)
+            v_addr      : in std_logic_vector (13 downto 0);
+            v_data      : in std_logic_vector (7 downto 0);
+            nt_v_mirror : in std_logic;
+            pt_ce_n     : out std_logic;
+            nt0_ce_n    : out std_logic;
+            nt1_ce_n    : out std_logic
         );
 end v_address_decoder;
 
@@ -98,73 +102,15 @@ end v_address_decoder;
 -- $3F20-$3FFF  $0080   Mirrors of $3F00-$3F1F
 
 architecture rtl of v_address_decoder is
-    component ram
-        generic (abus_size : integer := 16; dbus_size : integer := 8);
-        port (  ce_n, oe_n, we_n  : in std_logic;   --select pin active low.
-                addr              : in std_logic_vector (abus_size - 1 downto 0);
-                d_io              : inout std_logic_vector (dbus_size - 1 downto 0)
-        );
-    end component;
-
-    component chr_rom
-        generic (abus_size : integer := 13; dbus_size : integer := 8);
-        port (  ce_n            : in std_logic;     --active low.
-                addr            : in std_logic_vector (abus_size - 1 downto 0);
-                data            : out std_logic_vector (dbus_size - 1 downto 0);
-                nt_v_mirror     : out std_logic
-        );
-    end component;
-
-    component ls373
-        generic (
-            dsize : integer := 8
-        );
-        port (  c         : in std_logic;
-                oc_n      : in std_logic;
-                d         : in std_logic_vector(dsize - 1 downto 0);
-                q         : out std_logic_vector(dsize - 1 downto 0)
-        );
-    end component;
-
-    constant dsize : integer := 8;
-    constant vram_1k : integer := 10;      --2k = 11 bit width.
-    constant chr_rom_8k : integer := 13;     --32k = 15 bit width.
-
-    signal v_addr : std_logic_vector (13 downto 0);
-    --signal nt_v_mirror2  : std_logic;
-    signal nt_v_mirror  : std_logic;
-
-    signal pt_ce_n : std_logic;
-    signal nt0_ce_n : std_logic;
-    signal nt1_ce_n : std_logic;
 
 begin
 
-    --transparent d-latch
-    latch_inst : ls373 generic map (dsize)
-                port map(ale, '0', vram_ad, v_addr(7 downto 0));
-    v_addr (13 downto 8) <= vram_a;
-
     --pattern table
     pt_ce_n <= '0' when (v_addr(13) = '0' and rd_n = '0') else
              '1' ;
-    --nt_v_mirror <= '0';
-    pattern_tbl : chr_rom generic map (chr_rom_8k, dsize)
-            port map (pt_ce_n, v_addr(chr_rom_8k - 1 downto 0), vram_ad, nt_v_mirror);
-
-    --name table/attr table
-    name_tbl0 : ram generic map (vram_1k, dsize)
-            port map (nt0_ce_n, rd_n, wr_n, 
-                    v_addr(vram_1k - 1 downto 0), vram_ad);
-
-    name_tbl1 : ram generic map (vram_1k, dsize)
-            port map (nt1_ce_n, rd_n, wr_n, 
-                    v_addr(vram_1k - 1 downto 0), vram_ad);
-
-    --palette table data is stored in the inside ppu
 
     --ram io timing.
-    main_p : process (clk, v_addr, vram_ad, wr_n)
+    main_p : process (clk, v_addr, v_data, wr_n)
     begin
         if (v_addr(13) = '1') then
             ---name tbl

diff --git a/simulation/motones_sim.vhd b/simulation/motones_sim.vhd
index c9ba1d7..87445de 100644 (file)
--- a/simulation/motones_sim.vhd
+++ b/simulation/motones_sim.vhd
@@ -111,11 +111,35 @@ architecture rtl of motones_sim is
                 rd_n        : in std_logic;
                 wr_n        : in std_logic;
                 ale         : in std_logic;
-                vram_ad     : inout std_logic_vector (7 downto 0);
-                vram_a      : in std_logic_vector (13 downto 8)
+                v_addr      : in std_logic_vector (13 downto 0);
+                v_data      : in std_logic_vector (7 downto 0);
+                nt_v_mirror : in std_logic;
+                pt_ce_n     : out std_logic;
+                nt0_ce_n    : out std_logic;
+                nt1_ce_n    : out std_logic
             );
     end component;
 
+    component chr_rom
+        generic (abus_size : integer := 13; dbus_size : integer := 8);
+        port (  ce_n            : in std_logic;     --active low.
+                addr            : in std_logic_vector (abus_size - 1 downto 0);
+                data            : out std_logic_vector (dbus_size - 1 downto 0);
+                nt_v_mirror     : out std_logic
+        );
+    end component;
+
+    component ls373
+        generic (
+            dsize : integer := 8
+        );
+        port (  c         : in std_logic;
+                oc_n      : in std_logic;
+                d         : in std_logic_vector(dsize - 1 downto 0);
+                q         : out std_logic_vector(dsize - 1 downto 0)
+        );
+    end component;
+
     component apu
         port (  clk         : in std_logic;
                 ce_n        : in std_logic;
@@ -129,11 +153,12 @@ architecture rtl of motones_sim is
 
     constant data_size : integer := 8;
     constant addr_size : integer := 16;
-    constant size14    : integer := 14;
+    constant vram_size14    : integer := 14;
 
     constant ram_2k : integer := 11;      --2k = 11 bit width.
     constant rom_32k : integer := 15;     --32k = 15 bit width.
-    
+    constant vram_1k : integer := 10;      --1k = 10 bit width.
+    constant chr_rom_8k : integer := 13;     --32k = 15 bit width.
 
     signal cpu_clk  : std_logic;
     signal ppu_clk  : std_logic;
@@ -150,11 +175,18 @@ architecture rtl of motones_sim is
     signal ram_oe_n : std_logic;
     signal ppu_ce_n : std_logic;
     signal apu_ce_n : std_logic;
+
     signal rd_n     : std_logic;
     signal wr_n     : std_logic;
     signal ale      : std_logic;
     signal vram_ad  : std_logic_vector (7 downto 0);
     signal vram_a   : std_logic_vector (13 downto 8);
+    signal v_addr   : std_logic_vector (13 downto 0);
+    signal nt_v_mirror  : std_logic;
+    signal pt_ce_n  : std_logic;
+    signal nt0_ce_n : std_logic;
+    signal nt1_ce_n : std_logic;
+
 
 begin
 
@@ -187,9 +219,28 @@ begin
                 nmi_n, rd_n, wr_n, ale, vram_ad, vram_a,
                 vga_out_clk, h_sync_n, v_sync_n, r, g, b);
 
-    ppu_addr_decoder : v_address_decoder generic map (size14, data_size) 
-        port map (ppu_clk, rd_n, wr_n, ale, vram_ad, vram_a);
+    ppu_addr_decoder : v_address_decoder generic map (vram_size14, data_size) 
+        port map (ppu_clk, rd_n, wr_n, ale, v_addr, vram_ad, 
+                nt_v_mirror, pt_ce_n, nt0_ce_n, nt1_ce_n);
+
+    ---VRAM/CHR ROM instances
+    v_addr (13 downto 8) <= vram_a;
+
+    --transparent d-latch
+    latch_inst : ls373 generic map (data_size)
+                port map(ale, '0', vram_ad, v_addr(7 downto 0));
+
+    pattern_tbl : chr_rom generic map (chr_rom_8k, data_size)
+            port map (pt_ce_n, v_addr(chr_rom_8k - 1 downto 0), vram_ad, nt_v_mirror);
+
+    --name table/attr table
+    name_tbl0 : ram generic map (vram_1k, data_size)
+            port map (nt0_ce_n, rd_n, wr_n, v_addr(vram_1k - 1 downto 0), vram_ad);
+
+    name_tbl1 : ram generic map (vram_1k, data_size)
+            port map (nt1_ce_n, rd_n, wr_n, v_addr(vram_1k - 1 downto 0), vram_ad);
 
+    --APU/DMA instance
     apu_inst : apu
         port map (cpu_clk, apu_ce_n, rst_n, r_nw, addr, d_io, rdy);