-#\r
-#add wave -label disp_nt -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_disp_nt;\r
-#add wave -label disp_attr -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_disp_attr;\r
-#add wave -label sft_ptn_l -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_sft_ptn_l;\r
-#add wave -label sft_ptn_h -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_sft_ptn_h;\r
-#\r
-#add wave -divider sprite\r
-#add wave -label reg_s_oam_cur_state sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_cur_state;\r
-#add wave -label reg_s_oam_ce_n sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_ce_n;\r
-#add wave -label reg_s_oam_rd_n sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_rd_n;\r
-#add wave -label reg_s_oam_wr_n sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_wr_n;\r
-#add wave -label reg_s_oam_addr -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_addr;\r
-#add wave -label reg_s_oam_data -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_data;\r
-#\r
-##add wave -label reg_s_oam_cpy_cnt sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_cpy_cnt;\r
-##add wave -label reg_p_oam_cpy_cnt sim:/testbench_motones_sim/sim_board/render_inst/reg_p_oam_cpy_cnt;\r
-##add wave -label reg_spr_eval_cnt sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_eval_cnt;\r
-#\r
-#add wave -label wr_spr_ce_n sim:/testbench_motones_sim/sim_board/wr_spr_ce_n;\r
-#add wave -label wr_spr_rd_n sim:/testbench_motones_sim/sim_board/wr_spr_rd_n;\r
-#add wave -label wr_spr_wr_n sim:/testbench_motones_sim/sim_board/wr_spr_wr_n;\r
-#add wave -label wr_spr_addr -radix hex sim:/testbench_motones_sim/sim_board/wr_spr_addr;\r
-#add wave -label wr_spr_data -radix hex sim:/testbench_motones_sim/sim_board/wr_spr_data;\r
-#\r
-#add wave -label reg_spr_y_tmp -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_y_tmp;\r
-#add wave -label reg_spr_tile_tmp -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_tile_tmp;\r
-#add wave -label reg_spr_attr -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_attr;\r
-#add wave -label reg_spr_x -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_x;\r
-#add wave -label reg_spr_ptn_sft_start -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_ptn_sft_start;\r
-#add wave -label reg_spr_ptn_l -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_ptn_l;\r
-#add wave -label reg_spr_ptn_h -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_ptn_h;\r
+\r
+add wave -label disp_nt -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_disp_nt;\r
+add wave -label disp_attr -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_disp_attr;\r
+add wave -label sft_ptn_l -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_sft_ptn_l;\r
+add wave -label sft_ptn_h -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_sft_ptn_h;\r
+\r
+add wave -divider sprite\r
+add wave -label reg_s_oam_cur_state sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_cur_state;\r
+add wave -label reg_s_oam_ce_n sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_ce_n;\r
+add wave -label reg_s_oam_rd_n sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_rd_n;\r
+add wave -label reg_s_oam_wr_n sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_wr_n;\r
+add wave -label reg_s_oam_addr -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_addr;\r
+add wave -label reg_s_oam_data -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_data;\r
+\r
+#add wave -label reg_s_oam_cpy_cnt sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_cpy_cnt;\r
+#add wave -label reg_p_oam_cpy_cnt sim:/testbench_motones_sim/sim_board/render_inst/reg_p_oam_cpy_cnt;\r
+#add wave -label reg_spr_eval_cnt sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_eval_cnt;\r
+\r
+add wave -label wr_spr_ce_n sim:/testbench_motones_sim/sim_board/wr_spr_ce_n;\r
+add wave -label wr_spr_rd_n sim:/testbench_motones_sim/sim_board/wr_spr_rd_n;\r
+add wave -label wr_spr_wr_n sim:/testbench_motones_sim/sim_board/wr_spr_wr_n;\r
+add wave -label wr_spr_addr -radix hex sim:/testbench_motones_sim/sim_board/wr_spr_addr;\r
+add wave -label wr_spr_data -radix hex sim:/testbench_motones_sim/sim_board/wr_spr_data;\r
+\r
+add wave -label reg_spr_y_tmp -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_y_tmp;\r
+add wave -label reg_spr_tile_tmp -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_tile_tmp;\r
+add wave -label reg_spr_attr -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_attr;\r
+add wave -label reg_spr_x -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_x;\r
+add wave -label reg_spr_ptn_sft_start -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_ptn_sft_start;\r
+add wave -label reg_spr_ptn_l -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_ptn_l;\r
+add wave -label reg_spr_ptn_h -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_ptn_h;\r