sprite state machine added

diff --git a/de0_cv_nes/dummy-mos6502.vhd b/de0_cv_nes/dummy-mos6502.vhd
index 11e9951..175c83f 100644 (file)
--- a/de0_cv_nes/dummy-mos6502.vhd
+++ b/de0_cv_nes/dummy-mos6502.vhd
@@ -279,7 +279,7 @@ end;
 \r
                         else\r
                             io_brk;\r
-                            if (nt_step_cnt > 17 * cpu_io_multi) then\r
+                            if (nt_step_cnt > 4 * cpu_io_multi) then\r
                                 global_step_cnt := global_step_cnt + 1;\r
                             end if;\r
                         end if;\r

diff --git a/de0_cv_nes/ppu/render.vhd b/de0_cv_nes/ppu/render.vhd
index 764a962..fe54014 100644 (file)
--- a/de0_cv_nes/ppu/render.vhd
+++ b/de0_cv_nes/ppu/render.vhd
@@ -54,6 +54,18 @@ end render;
 \r
 architecture rtl of render is\r
 \r
+--secondary oam ram.\r
+component ram\r
+    generic (abus_size : integer := 16; dbus_size : integer := 8);\r
+    port (\r
+            pi_base_clk     : in std_logic;\r
+            pi_ce_n         : in std_logic;\r
+            pi_oe_n         : in std_logic;\r
+            pi_we_n         : in std_logic;\r
+            pi_addr         : in std_logic_vector (abus_size - 1 downto 0);\r
+            pio_d_io        : inout std_logic_vector (dbus_size - 1 downto 0)\r
+        );\r
+end component;\r
 \r
 --------- VGA screen constant -----------\r
 constant VGA_W          : integer := 640;\r
@@ -207,6 +219,7 @@ type vac_state is (
     REG_SET3\r
     );\r
 \r
+-------------bg registers.\r
 signal reg_v_cur_state      : vac_state;\r
 signal reg_v_next_state     : vac_state;\r
 \r
@@ -228,6 +241,50 @@ signal reg_plt_wr_n       : std_logic;
 signal reg_plt_addr       : std_logic_vector (4 downto 0);\r
 signal reg_plt_data       : std_logic_vector (7 downto 0);\r
 \r
+---------------oam registers.\r
+\r
+type s_oam_state is (\r
+    IDLE,\r
+    AD_SET0,\r
+    AD_SET1,\r
+    AD_SET2,\r
+    AD_SET3,\r
+    REG_CLR0,\r
+    REG_CLR1,\r
+    REG_CLR2,\r
+    REG_CLR3,\r
+    REG_CP0,\r
+    REG_CP1,\r
+    REG_CP2,\r
+    REG_CP3,\r
+    REG_NT0,\r
+    REG_NT1,\r
+    REG_NT2,\r
+    REG_NT3,\r
+    REG_AT0,\r
+    REG_AT1,\r
+    REG_AT2,\r
+    REG_AT3,\r
+    REG_PL0,\r
+    REG_PL1,\r
+    REG_PL2,\r
+    REG_PL3,\r
+    REG_PH0,\r
+    REG_PH1,\r
+    REG_PH2,\r
+    REG_PH3\r
+    );\r
+\r
+\r
+signal reg_s_oam_cur_state      : s_oam_state;\r
+signal reg_s_oam_next_state     : s_oam_state;\r
+\r
+signal reg_s_oam_ce_n       : std_logic;\r
+signal reg_s_oam_rd_n       : std_logic;\r
+signal reg_s_oam_wr_n       : std_logic;\r
+signal reg_s_oam_addr       : std_logic_vector (4 downto 0);\r
+signal reg_s_oam_data       : std_logic_vector (7 downto 0);\r
+\r
 begin\r
 \r
     --position and sync signal generate.\r
@@ -291,13 +348,15 @@ begin
         end if;--if (pi_rst_n = '0') then\r
     end process;\r
 \r
-    --vram access state machine (state transition)...\r
-    vac_set_stat_p : process (pi_rst_n, pi_base_clk)\r
+    --state transition process...\r
+    set_stat_p : process (pi_rst_n, pi_base_clk)\r
     begin\r
         if (pi_rst_n = '0') then\r
+            reg_s_oam_cur_state <= IDLE;\r
             reg_v_cur_state <= IDLE;\r
         elsif (rising_edge(pi_base_clk)) then\r
             reg_v_cur_state <= reg_v_next_state;\r
+            reg_s_oam_cur_state <= reg_s_oam_next_state;\r
         end if;--if (pi_rst_n = '0') then\r
     end process;\r
 \r
@@ -593,6 +652,7 @@ end;
         end if;--if (pi_rst_n = '0') then\r
     end process;\r
 \r
+    --vga output process...\r
     rgb_out_p : process (pi_rst_n, pi_base_clk)\r
     begin\r
         if (pi_rst_n = '0') then\r
@@ -616,6 +676,290 @@ end;
         end if;--if (rst_n = '0') then\r
     end process;--output_p\r
 \r
+    ---secondary oam ram inst.\r
+    secondary_oam_inst : ram generic map (5, 8) port map (\r
+                            pi_base_clk,\r
+                            reg_s_oam_ce_n,\r
+                            reg_s_oam_rd_n,\r
+                            reg_s_oam_wr_n,\r
+                            reg_s_oam_addr,\r
+                            reg_s_oam_data\r
+                            );\r
+\r
+\r
+    --state change to next.\r
+    s_oam_next_stat_p : process (reg_s_oam_cur_state, pi_rnd_en, pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y)\r
+function is_idle (\r
+    pm_ssp          : in std_logic;\r
+    pm_nes_x        : in integer range 0 to VGA_W_MAX - 1;\r
+    pm_nes_y        : in integer range 0 to VGA_H_MAX - 1\r
+    )return integer is\r
+begin\r
+    if (pm_ssp = '0' or\r
+        (pm_nes_x > HSCAN_SPR_MAX) or\r
+        (pm_nes_y >= VSCAN and pm_nes_y < VSCAN_NEXT_START)) then\r
+        return 1;\r
+    else\r
+        return 0;\r
+    end if;\r
+end;\r
+    begin\r
+        case reg_s_oam_cur_state is\r
+            when IDLE =>\r
+                if (pi_ppu_mask(PPUSSP) = '1' and reg_nes_x = 0 and\r
+                    (reg_nes_y < VSCAN or reg_nes_y = VSCAN_NEXT_START) and\r
+                    pi_rnd_en(2) = '1') then\r
+                    --start sprite clear.\r
+                    reg_s_oam_next_state <= AD_SET0;\r
+                else\r
+                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                end if;\r
+            when AD_SET0 =>\r
+                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
+                    reg_s_oam_next_state <= IDLE;\r
+                elsif (pi_rnd_en(3) = '1') then\r
+                    reg_s_oam_next_state <= AD_SET1;\r
+                else\r
+                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                end if;\r
+            when AD_SET1 =>\r
+                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
+                    reg_s_oam_next_state <= IDLE;\r
+                elsif (pi_rnd_en(0) = '1') then\r
+                    reg_s_oam_next_state <= AD_SET2;\r
+                else\r
+                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                end if;\r
+            when AD_SET2 =>\r
+                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
+                    reg_s_oam_next_state <= IDLE;\r
+                elsif (pi_rnd_en(1) = '1') then\r
+                    reg_s_oam_next_state <= AD_SET3;\r
+                else\r
+                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                end if;\r
+            when AD_SET3 =>\r
+                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
+                    reg_s_oam_next_state <= IDLE;\r
+                elsif (pi_rnd_en(2) = '1') then\r
+                    if (reg_nes_x < HSCAN_OAM_EVA_START) then\r
+                        --first 64 is oam clear.\r
+                        reg_s_oam_next_state <= REG_CLR0;\r
+                    elsif (reg_nes_x <= HSCAN) then\r
+                        --next until 256 is evaluate.\r
+                        --TODO: must add evaluation logic...\r
+                        reg_s_oam_next_state <= REG_CP0;\r
+                    else\r
+                        if (reg_nes_x mod 8 = 1) then\r
+                            reg_s_oam_next_state <= REG_NT0;\r
+                        elsif (reg_nes_x mod 8 = 3) then\r
+                            reg_s_oam_next_state <= REG_AT0;\r
+                        elsif (reg_nes_x mod 8 = 5) then\r
+                            reg_s_oam_next_state <= REG_PL0;\r
+                        elsif (reg_nes_x mod 8 = 7) then\r
+                            reg_s_oam_next_state <= REG_PH0;\r
+                        else\r
+                            reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                        end if;\r
+                    end if;\r
+                else\r
+                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                end if;\r
+            when REG_CLR0 =>\r
+                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
+                    reg_s_oam_next_state <= IDLE;\r
+                elsif (pi_rnd_en(3) = '1') then\r
+                    reg_s_oam_next_state <= REG_CLR1;\r
+                else\r
+                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                end if;\r
+            when REG_CLR1 =>\r
+                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
+                    reg_s_oam_next_state <= IDLE;\r
+                elsif (pi_rnd_en(0) = '1') then\r
+                    reg_s_oam_next_state <= REG_CLR2;\r
+                else\r
+                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                end if;\r
+            when REG_CLR2 =>\r
+                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
+                    reg_s_oam_next_state <= IDLE;\r
+                elsif (pi_rnd_en(1) = '1') then\r
+                    reg_s_oam_next_state <= REG_CLR3;\r
+                else\r
+                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                end if;\r
+            when REG_CLR3 =>\r
+                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
+                    reg_s_oam_next_state <= IDLE;\r
+                elsif (pi_rnd_en(2) = '1') then\r
+                    reg_s_oam_next_state <= AD_SET0;\r
+                else\r
+                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                end if;\r
+            when REG_CP0 =>\r
+                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
+                    reg_s_oam_next_state <= IDLE;\r
+                elsif (pi_rnd_en(3) = '1') then\r
+                    reg_s_oam_next_state <= REG_CP1;\r
+                else\r
+                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                end if;\r
+            when REG_CP1 =>\r
+                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
+                    reg_s_oam_next_state <= IDLE;\r
+                elsif (pi_rnd_en(0) = '1') then\r
+                    reg_s_oam_next_state <= REG_CP2;\r
+                else\r
+                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                end if;\r
+            when REG_CP2 =>\r
+                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
+                    reg_s_oam_next_state <= IDLE;\r
+                elsif (pi_rnd_en(1) = '1') then\r
+                    reg_s_oam_next_state <= REG_CP3;\r
+                else\r
+                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                end if;\r
+            when REG_CP3 =>\r
+                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
+                    reg_s_oam_next_state <= IDLE;\r
+                elsif (pi_rnd_en(2) = '1') then\r
+                    reg_s_oam_next_state <= AD_SET0;\r
+                else\r
+                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                end if;\r
+            when REG_NT0 =>\r
+                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
+                    reg_s_oam_next_state <= IDLE;\r
+                elsif (pi_rnd_en(3) = '1') then\r
+                    reg_s_oam_next_state <= REG_NT1;\r
+                else\r
+                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                end if;\r
+            when REG_NT1 =>\r
+                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
+                    reg_s_oam_next_state <= IDLE;\r
+                elsif (pi_rnd_en(0) = '1') then\r
+                    reg_s_oam_next_state <= REG_NT2;\r
+                else\r
+                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                end if;\r
+            when REG_NT2 =>\r
+                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
+                    reg_s_oam_next_state <= IDLE;\r
+                elsif (pi_rnd_en(1) = '1') then\r
+                    reg_s_oam_next_state <= REG_NT3;\r
+                else\r
+                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                end if;\r
+            when REG_NT3 =>\r
+                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
+                    reg_s_oam_next_state <= IDLE;\r
+                elsif (pi_rnd_en(2) = '1') then\r
+                    reg_s_oam_next_state <= AD_SET0;\r
+                else\r
+                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                end if;\r
+            when REG_AT0 =>\r
+                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
+                    reg_s_oam_next_state <= IDLE;\r
+                elsif (pi_rnd_en(3) = '1') then\r
+                    reg_s_oam_next_state <= REG_AT1;\r
+                else\r
+                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                end if;\r
+            when REG_AT1 =>\r
+                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
+                    reg_s_oam_next_state <= IDLE;\r
+                elsif (pi_rnd_en(0) = '1') then\r
+                    reg_s_oam_next_state <= REG_AT2;\r
+                else\r
+                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                end if;\r
+            when REG_AT2 =>\r
+                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
+                    reg_s_oam_next_state <= IDLE;\r
+                elsif (pi_rnd_en(1) = '1') then\r
+                    reg_s_oam_next_state <= REG_AT3;\r
+                else\r
+                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                end if;\r
+            when REG_AT3 =>\r
+                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
+                    reg_s_oam_next_state <= IDLE;\r
+                elsif (pi_rnd_en(2) = '1') then\r
+                    reg_s_oam_next_state <= AD_SET0;\r
+                else\r
+                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                end if;\r
+            when REG_PL0 =>\r
+                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
+                    reg_s_oam_next_state <= IDLE;\r
+                elsif (pi_rnd_en(3) = '1') then\r
+                    reg_s_oam_next_state <= REG_PL1;\r
+                else\r
+                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                end if;\r
+            when REG_PL1 =>\r
+                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
+                    reg_s_oam_next_state <= IDLE;\r
+                elsif (pi_rnd_en(0) = '1') then\r
+                    reg_s_oam_next_state <= REG_PL2;\r
+                else\r
+                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                end if;\r
+            when REG_PL2 =>\r
+                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
+                    reg_s_oam_next_state <= IDLE;\r
+                elsif (pi_rnd_en(1) = '1') then\r
+                    reg_s_oam_next_state <= REG_PL3;\r
+                else\r
+                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                end if;\r
+            when REG_PL3 =>\r
+                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
+                    reg_s_oam_next_state <= IDLE;\r
+                elsif (pi_rnd_en(2) = '1') then\r
+                    reg_s_oam_next_state <= AD_SET0;\r
+                else\r
+                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                end if;\r
+            when REG_PH0 =>\r
+                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
+                    reg_s_oam_next_state <= IDLE;\r
+                elsif (pi_rnd_en(3) = '1') then\r
+                    reg_s_oam_next_state <= REG_PH1;\r
+                else\r
+                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                end if;\r
+            when REG_PH1 =>\r
+                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
+                    reg_s_oam_next_state <= IDLE;\r
+                elsif (pi_rnd_en(0) = '1') then\r
+                    reg_s_oam_next_state <= REG_PH2;\r
+                else\r
+                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                end if;\r
+            when REG_PH2 =>\r
+                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
+                    reg_s_oam_next_state <= IDLE;\r
+                elsif (pi_rnd_en(1) = '1') then\r
+                    reg_s_oam_next_state <= REG_PH3;\r
+                else\r
+                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                end if;\r
+            when REG_PH3 =>\r
+                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
+                    reg_s_oam_next_state <= IDLE;\r
+                elsif (pi_rnd_en(2) = '1') then\r
+                    reg_s_oam_next_state <= AD_SET0;\r
+                else\r
+                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                end if;\r
+        end case;\r
+    end process;\r
+\r
     po_ppu_status   <= (others => '0');\r
 \r
     po_spr_ce_n     <= 'Z';\r

diff --git a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
index ff0ad3b..b8a36d4 100644 (file)
--- a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
+++ b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
@@ -28,23 +28,23 @@ add wave -label addr -radix hex     sim:/testbench_motones_sim/sim_board/wr_addr
 add wave -label d_io -radix hex     sim:/testbench_motones_sim/sim_board/wr_d_io;\r
 \r
 \r
-add wave -divider ppu\r
-add wave -label pi_ce_n         -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/pi_ce_n;\r
-add wave -label ppu_ctrl        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_ctrl;\r
-add wave -label ppu_mask        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_mask;\r
-add wave -label ppu_status      -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/pi_ppu_status;\r
-add wave -label oam_addr        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_oam_addr;\r
-add wave -label oam_data        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_oam_data;\r
-add wave -label ppu_scroll_x    -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_scroll_x;\r
-add wave -label ppu_scroll_y    -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_scroll_y;\r
-add wave -label ppu_addr        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_addr;\r
-add wave -label ppu_data        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_data;\r
-\r
-add wave -divider vram\r
-add wave -label v_rd_n        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_rd_n;\r
-add wave -label v_wr_n        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_wr_n;\r
-add wave -label vram_addr        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_addr;\r
-add wave -label vram_data        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_data;\r
+#add wave -divider ppu\r
+#add wave -label pi_ce_n         -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/pi_ce_n;\r
+#add wave -label ppu_ctrl        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_ctrl;\r
+#add wave -label ppu_mask        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_mask;\r
+#add wave -label ppu_status      -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/pi_ppu_status;\r
+#add wave -label oam_addr        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_oam_addr;\r
+#add wave -label oam_data        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_oam_data;\r
+#add wave -label ppu_scroll_x    -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_scroll_x;\r
+#add wave -label ppu_scroll_y    -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_scroll_y;\r
+#add wave -label ppu_addr        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_addr;\r
+#add wave -label ppu_data        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_data;\r
+#\r
+#add wave -divider vram\r
+#add wave -label v_rd_n        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_rd_n;\r
+#add wave -label v_wr_n        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_wr_n;\r
+#add wave -label vram_addr        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_addr;\r
+#add wave -label vram_data        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_data;\r
 \r
 add wave -divider render\r
 #add wave -label vga_x       sim:/testbench_motones_sim/sim_board/render_inst/reg_vga_x;\r
@@ -52,15 +52,19 @@ add wave -divider render
 add wave -label nes_x       sim:/testbench_motones_sim/sim_board/render_inst/reg_nes_x;\r
 add wave -label nes_y       sim:/testbench_motones_sim/sim_board/render_inst/reg_nes_y;\r
 #add wave -label wr_rnd_en  sim:/testbench_motones_sim/sim_board/wr_rnd_en;\r
-add wave -label reg_v_cur_state sim:/testbench_motones_sim/sim_board/render_inst/reg_v_cur_state;\r
+#add wave -label reg_v_cur_state sim:/testbench_motones_sim/sim_board/render_inst/reg_v_cur_state;\r
 #add wave -label prf_x       sim:/testbench_motones_sim/sim_board/render_inst/reg_prf_x;\r
 #add wave -label prf_y       sim:/testbench_motones_sim/sim_board/render_inst/reg_prf_y;\r
 \r
-add wave -label disp_nt -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_disp_nt;\r
-add wave -label disp_attr   -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_disp_attr;\r
-add wave -label sft_ptn_l -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_sft_ptn_l;\r
-add wave -label sft_ptn_h -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_sft_ptn_h;\r
+#add wave -label disp_nt -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_disp_nt;\r
+#add wave -label disp_attr   -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_disp_attr;\r
+#add wave -label sft_ptn_l -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_sft_ptn_l;\r
+#add wave -label sft_ptn_h -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_sft_ptn_h;\r
 \r
+add wave -divider sprite\r
+add wave -label reg_s_oam_cur_state sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_cur_state;\r
+\r
+add wave -divider palette\r
 add wave -label plt_addr -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_plt_addr;\r
 add wave -label plt_data -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_plt_data;\r
 \r
@@ -82,5 +86,5 @@ view signals
 run 4 us\r
 wave zoom full\r
 \r
-run 166 us\r
+run 190 us\r
 \r