constant PPUADDR : std_logic_vector(2 downto 0) := "110";
constant PPUDATA : std_logic_vector(2 downto 0) := "111";
+constant PPUVAI : integer := 2; --vram address increment
constant PPUNEN : integer := 7; --nmi enable
constant ST_VBL : integer := 7; --vblank
signal ppu_scroll_y : std_logic_vector (dsize - 1 downto 0);
signal ppu_scroll_cnt : std_logic_vector (0 downto 0);
signal ppu_addr : std_logic_vector (13 downto 0);
+signal ppu_addr_inc1 : std_logic_vector (13 downto 0);
+signal ppu_addr_inc32 : std_logic_vector (13 downto 0);
signal ppu_addr_in : std_logic_vector (13 downto 0);
signal ppu_addr_cnt : std_logic_vector (0 downto 0);
signal ppu_data : std_logic_vector (dsize - 1 downto 0);
port map (clk_n, ppu_latch_rst_n, ppu_scroll_cnt_ce_n,
'1', (others => '0'), ppu_scroll_cnt);
- ppu_addr_inst : counter_register generic map(14, 1)
- port map (clk_n, rst_n, ppu_data_we_n, ppu_addr_we_n, ppu_addr_in, ppu_addr);
+-- ppu_addr_inst : counter_register generic map(14, 1)
+-- port map (clk_n, rst_n, ppu_data_we_n, ppu_addr_we_n, ppu_addr_in, ppu_addr);
+
+ ppu_addr_inst_inc1 : counter_register generic map(14, 1)
+ port map (clk_n, rst_n, ppu_data_we_n, ppu_addr_we_n, ppu_addr_in, ppu_addr_inc1);
+ ppu_addr_inst_inc32 : counter_register generic map(14, 32)
+ port map (clk_n, rst_n, ppu_data_we_n, ppu_addr_we_n, ppu_addr_in, ppu_addr_inc32);
+
+ ppu_addr <= ppu_addr_inc32 when ppu_ctrl(PPUVAI) = '1' else
+ ppu_addr_inc1;
+
ppu_addr_cnt_inst : counter_register generic map (1, 1)
port map (clk_n, ppu_latch_rst_n, ppu_addr_cnt_ce_n,
'1', (others => '0'), ppu_addr_cnt);