bus pin restored... lol!

diff --git a/de1_nes/cpu/alu.vhd b/de1_nes/cpu/alu.vhd
index bb03b5d..69633ef 100644 (file)
--- a/de1_nes/cpu/alu.vhd
+++ b/de1_nes/cpu/alu.vhd
@@ -25,7 +25,6 @@ entity alu is
             indir_n         : in std_logic;
             indir_x_n       : in std_logic;
             indir_y_n       : in std_logic;
-            ba_out_n        : in std_logic;
             arith_en_n      : in std_logic;
             instruction     : in std_logic_vector (dsize - 1 downto 0);
             exec_cycle      : in std_logic_vector (5 downto 0);
@@ -220,7 +219,7 @@ begin
                     pcl_inc_n, sp_oe_n, sp_pop_n, sp_push_n,
                     zp_n, zp_xy_n, abs_xy_n, pg_next_n, rel_calc_n,
                     int_d_bus(7), indir_n, indir_x_n, exec_cycle,
-                    indir_y_n, ba_out_n
+                    indir_y_n
                     )
     begin
     
@@ -464,18 +463,18 @@ begin
             tmp_buf_we_n <= '1';
             ea_carry <= '0';
         end if; -- if (exec_cycle = T2) then
-    elsif (ba_out_n = '0') then
-        abh <= bah;
-        abl <= bal;
     else
         al_buf_we_n <= '1';
         ah_buf_we_n <= '1';
         tmp_buf_we_n <= '1';
         ea_carry <= '0';
 
-        abl <= (others => 'Z');
-        abh <= (others => 'Z');
-        addr_back <= (others => 'Z');
+        abl <= bal;
+        abh <= bah;
+
+        ----addr_back is always bal for jmp/jsr instruction....
+        -----TODO must check later if it's ok.
+        addr_back <= bal;
     end if; --if (pcl_inc_n = '0') then
 
     end process;

diff --git a/de1_nes/cpu/decoder.vhd b/de1_nes/cpu/decoder.vhd
index 4abd559..eef4d94 100644 (file)
--- a/de1_nes/cpu/decoder.vhd
+++ b/de1_nes/cpu/decoder.vhd
@@ -47,7 +47,6 @@ entity decoder is
             indir_n         : out std_logic;
             indir_x_n       : out std_logic;
             indir_y_n       : out std_logic;
-            ba_out_n        : out std_logic;
             arith_en_n      : out std_logic;
             stat_dec_oe_n   : out std_logic;
             stat_bus_oe_n   : out std_logic;
@@ -312,7 +311,6 @@ begin
         wk_next_cycle <= N1;
     else
         fetch_inst;
-        ba_out_n <= '1';
         wk_next_cycle <= T1;
     end if;
 end  procedure;
@@ -1115,7 +1113,6 @@ end  procedure;
                 pcl_cmd <= "1111";
                 pch_cmd <= "1111";
                 r_nw <= 'Z';
-                ba_out_n <= '1';
 
             elsif (exec_cycle = T0 and ea_carry = '0') then
                 --cycle #1
@@ -2752,7 +2749,6 @@ end  procedure;
                 indir_n <= '1';
                 indir_x_n <= '1';
                 indir_y_n <= '1';
-                ba_out_n <= '1';
                 arith_en_n <= '1';
 
                 stat_dec_oe_n <= '0';
@@ -2851,7 +2847,6 @@ end  procedure;
                     n_vec_oe_n <= '0';
                     wk_next_cycle <= N5;
                 end if;
-                ba_out_n <= '0';
                 
             elsif exec_cycle = R5 or exec_cycle = N5 then
                 front_we(pcl_cmd, '1');

diff --git a/de1_nes/cpu/mos6502.vhd b/de1_nes/cpu/mos6502.vhd
index 460717a..b4c02f1 100644 (file)
--- a/de1_nes/cpu/mos6502.vhd
+++ b/de1_nes/cpu/mos6502.vhd
@@ -79,7 +79,6 @@ component decoder
             indir_n         : out std_logic;
             indir_x_n       : out std_logic;
             indir_y_n       : out std_logic;
-            ba_out_n        : out std_logic;\r
             arith_en_n      : out std_logic;
             stat_dec_oe_n   : out std_logic;
             stat_bus_oe_n   : out std_logic;
@@ -115,7 +114,6 @@ component alu
             indir_n         : in std_logic;
             indir_x_n       : in std_logic;
             indir_y_n       : in std_logic;
-            ba_out_n        : in std_logic;\r
             arith_en_n      : in std_logic;
             instruction     : in std_logic_vector (dsize - 1 downto 0);
             exec_cycle      : in std_logic_vector (5 downto 0);
@@ -276,7 +274,6 @@ end component;
     signal indir_n         : std_logic;
     signal indir_x_n       : std_logic;
     signal indir_y_n       : std_logic;
-    signal ba_out_n        : std_logic;\r
     signal arith_en_n      : std_logic;
                     
     signal alu_n : std_logic;
@@ -418,7 +415,6 @@ begin
                     indir_n,
                     indir_x_n,
                     indir_y_n,
-                    ba_out_n,\r
                     arith_en_n,
                     stat_dec_oe_n, 
                     stat_bus_oe_n, 
@@ -450,7 +446,6 @@ begin
                     indir_n,
                     indir_x_n,
                     indir_y_n,\r
-                    ba_out_n,
                     arith_en_n,
                     instruction,
                     exec_cycle,

diff --git a/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do b/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do
index b9ef00f..107b753 100644 (file)
--- a/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do
+++ b/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do
@@ -38,6 +38,8 @@ add wave -label exec_cycle -radix hex sim:/testbench_motones_sim/sim_board/dbg_e
 add wave -label ea_carry   -radix decimal -unsigned  sim:/testbench_motones_sim/sim_board/dbg_ea_carry     \r
 #add wave -label wait_a58_branch_next -radix hex sim:/testbench_motones_sim/sim_board/dbg_wait_a58_branch_next     \r
 \r
+\r
+add wave -label acc -radix hex sim:/testbench_motones_sim/sim_board/dbg_acc\r
 add wave -label pcl -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_ctrl\r
 \r
 \r
@@ -118,7 +120,7 @@ wave zoom full
 \r
 #wave zoom range 3339700 ps 5138320 ps\r
 \r
-run 5 us\r
+run 20 us\r
 \r
 ##wave addcursor 907923400 ps\r
 \r

diff --git a/doc/mos6502-bus.xlsx b/doc/mos6502-bus.xlsx
index 02c843a..254c43d 100644 (file)
Binary files a/doc/mos6502-bus.xlsx and b/doc/mos6502-bus.xlsx differ