spr eval flag set bug

diff --git a/de0_cv_nes/ppu/render.vhd b/de0_cv_nes/ppu/render.vhd
index 4bce105..026ec19 100644 (file)
--- a/de0_cv_nes/ppu/render.vhd
+++ b/de0_cv_nes/ppu/render.vhd
@@ -977,7 +977,6 @@ end;
                     reg_s_oam_cpy_cnt <= 0;\r
                     reg_p_oam_cpy_cnt <= 0;\r
                     reg_spr_eval_cnt <= 0;\r
-                    reg_spr0_eval <= '0';\r
                 elsif (is_spr_eval(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
                     --copy data from primary oam ram.\r
                     reg_s_oam_addr <= conv_std_logic_vector(reg_s_oam_cpy_cnt mod 32, 5);\r
@@ -1058,6 +1057,9 @@ end;
                     reg_s_oam_wr_n <= '1';\r
                     reg_s_oam_rd_n <= '1';\r
                 else\r
+                    if (reg_nes_y > VSCAN) then\r
+                        reg_spr0_eval <= '0';\r
+                    end if;\r
                     reg_s_oam_ce_n <= '1';\r
                     reg_s_oam_rd_n <= '1';\r
                     reg_s_oam_wr_n <= '1';\r

diff --git a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
index 940b74a..d8ff635 100644 (file)
--- a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
+++ b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
@@ -25,7 +25,7 @@ vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev -
 \r
 ##script custom part...\r
 \r
-run 400ms\r
+run 450ms\r
 \r
 #################################### General.... ###########################################\r
 \r
@@ -170,5 +170,5 @@ view signals
 run 25 us\r
 wave zoom full\r
 \r
-run 400ms\r
+run 16ms\r
 \r