--- /dev/null
+# -------------------------------------------------------------------------- #\r
+#\r
+# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.\r
+# Your use of Altera Corporation's design tools, logic functions \r
+# and other software and tools, and its AMPP partner logic \r
+# functions, and any output files from any of the foregoing \r
+# (including device programming or simulation files), and any \r
+# associated documentation or information are expressly subject \r
+# to the terms and conditions of the Altera Program License \r
+# Subscription Agreement, the Altera Quartus II License Agreement,\r
+# the Altera MegaCore Function License Agreement, or other \r
+# applicable license agreement, including, without limitation, \r
+# that your use is for the sole purpose of programming logic \r
+# devices manufactured by Altera and sold by Altera or its \r
+# authorized distributors. Please refer to the applicable \r
+# agreement for further details.\r
+#\r
+# -------------------------------------------------------------------------- #\r
+#\r
+# Quartus II 64-Bit\r
+# Version 14.0.0 Build 200 06/17/2014 SJ Web Edition\r
+# Date created = 15:11:02 May 18, 2016\r
+#\r
+# -------------------------------------------------------------------------- #\r
+#\r
+# Notes:\r
+#\r
+# 1) The default values for assignments are stored in the file:\r
+# de0_cv_nes_assignment_defaults.qdf\r
+# If this file doesn't exist, see file:\r
+# assignment_defaults.qdf\r
+#\r
+# 2) Altera recommends that you do not modify this file. This\r
+# file is updated automatically by the Quartus II software\r
+# and any changes you make may be lost or overwritten.\r
+#\r
+# -------------------------------------------------------------------------- #\r
+\r
+\r
+set_global_assignment -name FAMILY "Cyclone V"\r
+set_global_assignment -name DEVICE 5CEBA4F23C7\r
+set_global_assignment -name TOP_LEVEL_ENTITY de0_cv_nes\r
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0\r
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:11:02 MAY 18, 2016"\r
+set_global_assignment -name LAST_QUARTUS_VERSION 14.0\r
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files\r
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0\r
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85\r
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA\r
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484\r
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7\r
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256\r
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"\r
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation\r
+set_global_assignment -name VHDL_FILE de0_cv_nes.vhd\r
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"\r
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"\r
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top\r
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top\r
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top\r
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"\r
+\r
+\r
+#clock pin\r
+set_location_assignment PIN_N8 -to base_clk\r
+\r
+\r
+#vga pin\r
+set_location_assignment PIN_B6 -to b[3]\r
+set_location_assignment PIN_B7 -to b[2]\r
+set_location_assignment PIN_A8 -to b[1]\r
+set_location_assignment PIN_A7 -to b[0]\r
+set_location_assignment PIN_L7 -to g[3]\r
+set_location_assignment PIN_K7 -to g[2]\r
+set_location_assignment PIN_J7 -to g[1]\r
+set_location_assignment PIN_J8 -to g[0]\r
+set_location_assignment PIN_A9 -to r[0]\r
+set_location_assignment PIN_B10 -to r[1]\r
+set_location_assignment PIN_C9 -to r[2]\r
+set_location_assignment PIN_A5 -to r[3]\r
+set_location_assignment PIN_H8 -to h_sync_n\r
+set_location_assignment PIN_G8 -to v_sync_n\r
+\r
+#button pin\r
+set_location_assignment PIN_P22 -to rst_n\r
+\r
+\r
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.conv_integer;
+
+--
+-- MOTO NES FPGA On GHDL Simulation Environment Virtual Cuicuit Board
+-- All of the components are assembled and instanciated on this board.
+--
+
+entity de0_cv_nes is
+ port (
+--debug signal
+ signal dbg_cpu_clk : out std_logic;
+ signal dbg_ppu_clk : out std_logic;
+ signal dbg_mem_clk : out std_logic;
+ signal dbg_r_nw : out std_logic;
+ signal dbg_addr : out std_logic_vector( 16 - 1 downto 0);
+ signal dbg_d_io : out std_logic_vector( 8 - 1 downto 0);
+ signal dbg_vram_ad : out std_logic_vector (7 downto 0);
+ signal dbg_vram_a : out std_logic_vector (13 downto 8);
+
+---monitor inside cpu
+ signal dbg_instruction : out std_logic_vector(7 downto 0);
+ signal dbg_int_d_bus : out std_logic_vector(7 downto 0);
+ signal dbg_exec_cycle : out std_logic_vector (5 downto 0);
+ signal dbg_ea_carry : out std_logic;
+ signal dbg_status : out std_logic_vector(7 downto 0);
+ signal dbg_sp, dbg_x, dbg_y, dbg_acc : out std_logic_vector(7 downto 0);
+ signal dbg_dec_oe_n : out std_logic;
+ signal dbg_dec_val : out std_logic_vector (7 downto 0);
+ signal dbg_int_dbus : out std_logic_vector (7 downto 0);
+
+----ppu debug pins
+-- signal dbg_ppu_ce_n : out std_logic;
+-- signal dbg_ppu_ctrl, dbg_ppu_mask, dbg_ppu_status : out std_logic_vector (7 downto 0);
+-- signal dbg_ppu_addr : out std_logic_vector (13 downto 0);
+-- signal dbg_ppu_data, dbg_ppu_scrl_x, dbg_ppu_scrl_y : out std_logic_vector (7 downto 0);
+-- signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0);
+-- signal dbg_disp_ptn_h, dbg_disp_ptn_l : out std_logic_vector (15 downto 0);
+-- signal dbg_nmi : out std_logic;
+
+
+--NES instance
+ base_clk : in std_logic;
+ rst_n : in std_logic;
+ joypad1 : in std_logic_vector(7 downto 0);
+ joypad2 : in std_logic_vector(7 downto 0);
+ h_sync_n : out std_logic;
+ v_sync_n : out std_logic;
+ r : out std_logic_vector(3 downto 0);
+ g : out std_logic_vector(3 downto 0);
+ b : out std_logic_vector(3 downto 0)
+ );
+end de0_cv_nes;
+
+architecture rtl of de0_cv_nes is
+ component mos6502
+ generic ( dsize : integer := 8;
+ asize : integer :=16
+ );
+ port (
+ signal dbg_instruction : out std_logic_vector(7 downto 0);
+ signal dbg_int_d_bus : out std_logic_vector(7 downto 0);
+ signal dbg_exec_cycle : out std_logic_vector (5 downto 0);
+ signal dbg_ea_carry : out std_logic;
+-- signal dbg_index_bus : out std_logic_vector(7 downto 0);
+-- signal dbg_acc_bus : out std_logic_vector(7 downto 0);
+ signal dbg_status : out std_logic_vector(7 downto 0);
+ signal dbg_pcl, dbg_pch, dbg_sp, dbg_x, dbg_y, dbg_acc : out std_logic_vector(7 downto 0);
+ signal dbg_dec_oe_n : out std_logic;
+ signal dbg_dec_val : out std_logic_vector (7 downto 0);
+ signal dbg_int_dbus : out std_logic_vector (7 downto 0);
+-- signal dbg_status_val : out std_logic_vector (7 downto 0);
+ signal dbg_stat_we_n : out std_logic;
+ signal dbg_idl_h, dbg_idl_l, dbg_dbb_r, dbg_dbb_w : out std_logic_vector (7 downto 0);
+
+ input_clk : in std_logic; --phi0 input pin.
+ rdy : in std_logic;
+ rst_n : in std_logic;
+ irq_n : in std_logic;
+ nmi_n : in std_logic;
+ dbe : in std_logic;
+ r_nw : out std_logic;
+ phi1 : out std_logic;
+ phi2 : out std_logic;
+ addr : out std_logic_vector ( asize - 1 downto 0);
+ d_io : inout std_logic_vector ( dsize - 1 downto 0)
+ );
+ end component;
+
+ component clock_divider
+ port ( base_clk : in std_logic;
+ reset_n : in std_logic;
+ cpu_clk : out std_logic;
+ ppu_clk : out std_logic;
+ mem_clk : out std_logic;
+ vga_clk : out std_logic
+ );
+ end component;
+
+ component address_decoder
+ generic (abus_size : integer := 16; dbus_size : integer := 8);
+ port ( phi2 : in std_logic;
+ mem_clk : in std_logic;
+ R_nW : in std_logic;
+ addr : in std_logic_vector (abus_size - 1 downto 0);
+ rom_ce_n : out std_logic;
+ ram_ce_n : out std_logic;
+ ppu_ce_n : out std_logic;
+ apu_ce_n : out std_logic
+ );
+ end component;
+
+ component ram
+ generic (abus_size : integer := 16; dbus_size : integer := 8);
+ port (
+ clk : in std_logic;
+ ce_n, oe_n, we_n : in std_logic; --select pin active low.
+ addr : in std_logic_vector (abus_size - 1 downto 0);
+ d_io : inout std_logic_vector (dbus_size - 1 downto 0)
+ );
+ end component;
+
+ component prg_rom
+ generic (abus_size : integer := 15; dbus_size : integer := 8);
+ port (
+ clk : in std_logic;
+ ce_n : in std_logic; --active low.
+ addr : in std_logic_vector (abus_size - 1 downto 0);
+ data : out std_logic_vector (dbus_size - 1 downto 0)
+ );
+ end component;
+
+ component ppu port (
+ signal dbg_ppu_ce_n : out std_logic;
+ signal dbg_ppu_ctrl, dbg_ppu_mask, dbg_ppu_status : out std_logic_vector (7 downto 0);
+ signal dbg_ppu_addr : out std_logic_vector (13 downto 0);
+ signal dbg_ppu_data, dbg_ppu_scrl_x, dbg_ppu_scrl_y : out std_logic_vector (7 downto 0);
+
+ signal dbg_ppu_clk : out std_logic;
+ signal dbg_vga_clk : out std_logic;
+ signal dbg_nes_x : out std_logic_vector (8 downto 0);
+ signal dbg_vga_x : out std_logic_vector (9 downto 0);
+ signal dbg_nes_y : out std_logic_vector (8 downto 0);
+ signal dbg_vga_y : out std_logic_vector (9 downto 0);
+ signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0);
+ signal dbg_disp_ptn_h, dbg_disp_ptn_l : out std_logic_vector (15 downto 0);
+ signal dbg_plt_ce_rn_wn : out std_logic_vector (2 downto 0);
+ signal dbg_plt_addr : out std_logic_vector (4 downto 0);
+ signal dbg_plt_data : out std_logic_vector (7 downto 0);
+ signal dbg_p_oam_ce_rn_wn : out std_logic_vector (2 downto 0);
+ signal dbg_p_oam_addr : out std_logic_vector (7 downto 0);
+ signal dbg_p_oam_data : out std_logic_vector (7 downto 0);
+ signal dbg_s_oam_ce_rn_wn : out std_logic_vector (2 downto 0);
+ signal dbg_s_oam_addr : out std_logic_vector (4 downto 0);
+ signal dbg_s_oam_data : out std_logic_vector (7 downto 0);
+ signal dbg_emu_ppu_clk : out std_logic;
+
+ signal dbg_ppu_addr_we_n : out std_logic;
+ signal dbg_ppu_clk_cnt : out std_logic_vector(1 downto 0);
+
+ ppu_clk : in std_logic;
+ mem_clk : in std_logic;
+ ce_n : in std_logic;
+ rst_n : in std_logic;
+ r_nw : in std_logic;
+ cpu_addr : in std_logic_vector (2 downto 0);
+ cpu_d : inout std_logic_vector (7 downto 0);
+
+ vblank_n : out std_logic;
+ rd_n : out std_logic;
+ wr_n : out std_logic;
+ ale : out std_logic;
+ vram_ad : inout std_logic_vector (7 downto 0);
+ vram_a : out std_logic_vector (13 downto 8);
+
+ vga_clk : in std_logic;
+ h_sync_n : out std_logic;
+ v_sync_n : out std_logic;
+ r : out std_logic_vector(3 downto 0);
+ g : out std_logic_vector(3 downto 0);
+ b : out std_logic_vector(3 downto 0)
+ );
+ end component;
+
+ component v_address_decoder
+ generic (abus_size : integer := 14; dbus_size : integer := 8);
+ port ( clk : in std_logic;
+ mem_clk : in std_logic;
+ rd_n : in std_logic;
+ wr_n : in std_logic;
+ ale : in std_logic;
+ v_addr : in std_logic_vector (13 downto 0);
+ v_data : in std_logic_vector (7 downto 0);
+ nt_v_mirror : in std_logic;
+ pt_ce_n : out std_logic;
+ nt0_ce_n : out std_logic;
+ nt1_ce_n : out std_logic
+ );
+ end component;
+
+ component chr_rom
+ generic (abus_size : integer := 13; dbus_size : integer := 8);
+ port (
+ clk : in std_logic;
+ ce_n : in std_logic; --active low.
+ addr : in std_logic_vector (abus_size - 1 downto 0);
+ data : out std_logic_vector (dbus_size - 1 downto 0);
+ nt_v_mirror : out std_logic
+ );
+ end component;
+
+ component ls373
+ generic (
+ dsize : integer := 8
+ );
+ port ( c : in std_logic;
+ we_n : in std_logic;
+ oc_n : in std_logic;
+ d : in std_logic_vector(dsize - 1 downto 0);
+ q : out std_logic_vector(dsize - 1 downto 0)
+ );
+ end component;
+
+ component apu
+ port ( clk : in std_logic;
+ ce_n : in std_logic;
+ rst_n : in std_logic;
+ r_nw : inout std_logic;
+ cpu_addr : inout std_logic_vector (15 downto 0);
+ cpu_d : inout std_logic_vector (7 downto 0);
+ rdy : out std_logic
+ );
+ end component;
+
+ constant data_size : integer := 8;
+ constant addr_size : integer := 16;
+ constant vram_size14 : integer := 14;
+
+ constant ram_2k : integer := 11; --2k = 11 bit width.
+ constant rom_32k : integer := 15; --32k = 15 bit width.
+ constant rom_8k : integer := 13; --8k = 13 bit width. (for test use)
+ constant vram_1k : integer := 10; --1k = 10 bit width.
+ constant chr_rom_8k : integer := 13; --32k = 15 bit width.
+
+ signal cpu_clk : std_logic;
+ signal ppu_clk : std_logic;
+ signal mem_clk : std_logic;
+ signal vga_clk : std_logic;
+
+ signal rdy, irq_n, nmi_n, dbe, r_nw : std_logic;
+ signal phi1, phi2 : std_logic;
+ signal addr : std_logic_vector( addr_size - 1 downto 0);
+ signal d_io : std_logic_vector( data_size - 1 downto 0);
+
+ signal rom_ce_n : std_logic;
+ signal ram_ce_n : std_logic;
+ signal ram_oe_n : std_logic;
+ signal ppu_ce_n : std_logic;
+ signal apu_ce_n : std_logic;
+
+ signal rd_n : std_logic;
+ signal wr_n : std_logic;
+ signal ale : std_logic;
+ signal vram_ad : std_logic_vector (7 downto 0);
+ signal vram_a : std_logic_vector (13 downto 8);
+ signal v_addr : std_logic_vector (13 downto 0);
+ signal nt_v_mirror : std_logic;
+ signal pt_ce_n : std_logic;
+ signal nt0_ce_n : std_logic;
+ signal nt1_ce_n : std_logic;
+
+ signal ale_n : std_logic;
+
+-- signal dbg_disp_nt, dbg_disp_attr : std_logic_vector (7 downto 0);
+-- signal dbg_disp_ptn_h, dbg_disp_ptn_l : std_logic_vector (15 downto 0);
+ signal dbg_pcl, dbg_pch : std_logic_vector(7 downto 0);
+ signal dbg_stat_we_n : std_logic;
+ signal dbg_idl_h, dbg_idl_l, dbg_dbb_r, dbg_dbb_w : std_logic_vector (7 downto 0);
+
+ signal dbg_vga_clk : std_logic;
+ signal dbg_ppu_addr_we_n : std_logic;
+ signal dbg_ppu_clk_cnt : std_logic_vector(1 downto 0);
+ signal dbg_ppu_addr_dummy : std_logic_vector (13 downto 0);
+ signal dbg_nes_x : std_logic_vector (8 downto 0);
+ signal dbg_vga_x : std_logic_vector (9 downto 0);
+ signal dbg_nes_y : std_logic_vector (8 downto 0);
+ signal dbg_vga_y : std_logic_vector (9 downto 0);
+ signal dbg_plt_ce_rn_wn : std_logic_vector (2 downto 0);
+ signal dbg_plt_addr : std_logic_vector (4 downto 0);
+ signal dbg_plt_data : std_logic_vector (7 downto 0);
+ signal dbg_p_oam_ce_rn_wn : std_logic_vector (2 downto 0);
+ signal dbg_p_oam_addr : std_logic_vector (7 downto 0);
+ signal dbg_p_oam_data : std_logic_vector (7 downto 0);
+ signal dbg_s_oam_ce_rn_wn : std_logic_vector (2 downto 0);
+ signal dbg_s_oam_addr : std_logic_vector (4 downto 0);
+ signal dbg_s_oam_data : std_logic_vector (7 downto 0);
+ signal dbg_emu_ppu_clk : std_logic;
+ signal dbg_ppu_data_dummy : std_logic_vector (7 downto 0);
+ signal dbg_ppu_status_dummy : std_logic_vector (7 downto 0);
+ signal dbg_ppu_scrl_x_dummy : std_logic_vector (7 downto 0);
+ signal dbg_ppu_scrl_y_dummy : std_logic_vector (7 downto 0);
+ signal dbg_disp_ptn_h_dummy, dbg_disp_ptn_l_dummy : std_logic_vector (15 downto 0);
+
+ signal dbg_instruction_dummy : std_logic_vector(7 downto 0);
+ signal dbg_int_d_bus_dummy : std_logic_vector(7 downto 0);
+ signal dbg_exec_cycle_dummy : std_logic_vector (5 downto 0);
+ signal dbg_ea_carry_dummy : std_logic;
+ signal dbg_status_dummy : std_logic_vector(7 downto 0);
+ signal dbg_sp_dummy, dbg_x_dummy, dbg_y_dummy, dbg_acc_dummy : std_logic_vector(7 downto 0);\r
+
+begin
+
+-- irq_n <= '0';
+--
+-- --ppu/cpu clock generator
+-- clock_inst : clock_divider port map
+-- (base_clk, rst_n, cpu_clk, ppu_clk, mem_clk, vga_clk);
+--
+-- addr_dec_inst : address_decoder generic map (addr_size, data_size) \r
+-- port map (phi2, mem_clk, r_nw, addr, rom_ce_n, ram_ce_n, ppu_ce_n, apu_ce_n);\r
+--\r
+-- --mos 6502 cpu instance
+-- cpu_inst : mos6502 generic map (data_size, addr_size)
+-- port map (
+-- dbg_instruction,
+-- dbg_int_d_bus,
+-- dbg_exec_cycle,
+-- dbg_ea_carry,
+-- -- dbg_index_bus,
+-- -- dbg_acc_bus,
+-- dbg_status_dummy,
+-- dbg_pcl, dbg_pch, dbg_sp_dummy, dbg_x_dummy, dbg_y, dbg_acc,
+-- dbg_dec_oe_n,
+-- dbg_dec_val,
+-- dbg_int_dbus,
+---- dbg_status_val ,
+-- dbg_stat_we_n ,
+-- dbg_idl_h, dbg_idl_l, dbg_dbb_r, dbg_dbb_w,
+--
+-- cpu_clk, rdy,
+-- rst_n, irq_n, nmi_n, dbe, r_nw,
+-- phi1, phi2, addr, d_io);
+--
+-- --main ROM/RAM instance
+---- prg_rom_inst : prg_rom generic map (rom_32k, data_size)
+---- port map (mem_clk, rom_ce_n, addr(rom_32k - 1 downto 0), d_io);
+--
+-- prg_rom_inst : prg_rom generic map (rom_8k, data_size)
+-- port map (mem_clk, rom_ce_n, addr(rom_8k - 1 downto 0), d_io);
+--
+-- ram_oe_n <= not R_nW;
+-- prg_ram_inst : ram generic map (ram_2k, data_size)
+-- port map (mem_clk, ram_ce_n, ram_oe_n, R_nW, addr(ram_2k - 1 downto 0), d_io);
+--
+---- dbg_exec_cycle(2 downto 1) <= dbg_vga_x(9 downto 8);
+---- dbg_int_d_bus <= dbg_vga_x(7 downto 0);
+---- dbg_exec_cycle(0) <= dbg_nes_x(8);
+---- dbg_instruction <= dbg_nes_x(7 downto 0);
+---- dbg_exec_cycle(3) <= dbg_emu_ppu_clk;
+----
+---- dbg_exec_cycle(4) <= dbg_nes_y(8);
+---- dbg_status <= dbg_nes_y(7 downto 0);
+--
+--
+---- dbg_ppu_scrl_x(0) <= ale;
+---- dbg_ppu_scrl_x(1) <= rd_n;
+---- dbg_ppu_scrl_x(2) <= wr_n;
+---- dbg_ppu_scrl_x(3) <= nt0_ce_n;
+---- dbg_ppu_scrl_x(4) <= vga_clk;
+---- dbg_ppu_scrl_x(5) <= rom_ce_n;
+---- dbg_ppu_scrl_x(6) <= ram_ce_n;
+---- dbg_ppu_scrl_x(7) <= addr(15);
+---- dbg_ppu_scrl_y(2 downto 0) <= dbg_p_oam_ce_rn_wn(2 downto 0);
+---- dbg_ppu_scrl_y(5 downto 3) <= dbg_plt_ce_rn_wn(2 downto 0);
+-- dbg_disp_ptn_l (7 downto 0) <= dbg_p_oam_addr;
+-- dbg_disp_ptn_l (15 downto 8) <= dbg_p_oam_data;
+--
+-- dbg_cpu_clk <= cpu_clk;
+-- dbg_mem_clk <= mem_clk;
+-- dbg_r_nw <= r_nw;
+-- dbg_addr <= addr;
+-- dbg_d_io <= d_io;
+-- dbg_vram_ad <= vram_ad ;\r
+-- dbg_vram_a <= vram_a ;\r
+--\r
+-- dbg_sp(7 downto 6) <= dbg_ppu_clk_cnt;\r
+-- dbg_sp(5 downto 0) <= v_addr (13 downto 8);\r
+-- dbg_x <= v_addr (7 downto 0);\r
+--\r
+-- dbg_nmi <= nmi_n;
+---- nmi_n <= dummy_nmi;
+---- dbg_ppu_ctrl <= dbg_pcl;
+---- dbg_ppu_mask <= dbg_pch;
+-- --nes ppu instance
+-- ppu_inst: ppu port map (
+-- dbg_ppu_ce_n ,
+-- dbg_ppu_ctrl, dbg_ppu_mask, dbg_ppu_status ,
+-- dbg_ppu_addr ,
+-- dbg_ppu_data, dbg_ppu_scrl_x, dbg_ppu_scrl_y ,
+--
+-- dbg_ppu_clk ,
+-- dbg_vga_clk ,
+-- dbg_nes_x ,
+-- dbg_vga_x ,
+-- dbg_nes_y ,
+-- dbg_vga_y ,
+-- dbg_disp_nt, dbg_disp_attr ,
+-- dbg_disp_ptn_h, dbg_disp_ptn_l_dummy ,
+-- dbg_plt_ce_rn_wn ,
+-- dbg_plt_addr ,
+-- dbg_plt_data ,
+-- dbg_p_oam_ce_rn_wn ,
+-- dbg_p_oam_addr ,
+-- dbg_p_oam_data ,
+-- dbg_s_oam_ce_rn_wn ,
+-- dbg_s_oam_addr ,
+-- dbg_s_oam_data ,
+-- dbg_emu_ppu_clk ,
+-- dbg_ppu_addr_we_n ,
+-- dbg_ppu_clk_cnt ,
+--
+-- ppu_clk ,
+-- mem_clk ,
+-- ppu_ce_n ,
+-- rst_n ,
+-- r_nw ,
+-- addr(2 downto 0) ,
+-- d_io ,
+--
+-- nmi_n ,
+-- rd_n ,
+-- wr_n ,
+-- ale ,
+-- vram_ad ,
+-- vram_a ,
+--
+-- vga_clk ,
+-- h_sync_n ,
+-- v_sync_n ,
+-- r ,
+-- g ,
+-- b
+--
+-- );
+--
+-- ppu_addr_decoder : v_address_decoder generic map (vram_size14, data_size)
+-- port map (ppu_clk, mem_clk, rd_n, wr_n, ale, v_addr, vram_ad,
+-- nt_v_mirror, pt_ce_n, nt0_ce_n, nt1_ce_n);
+--
+-- ---VRAM/CHR ROM instances
+-- v_addr (13 downto 8) <= vram_a;
+--
+-- --transparent d-latch
+-- --ale=1 >> addr latch\r
+-- --ale=0 >> addr output.\r
+-- ale_n <= not ale;
+-- vram_latch : ls373 generic map (data_size)
+-- port map(vga_clk, ale_n, ale, vram_ad, v_addr(7 downto 0));
+--
+-- vchr_rom : chr_rom generic map (chr_rom_8k, data_size)
+-- port map (mem_clk, pt_ce_n, v_addr(chr_rom_8k - 1 downto 0), vram_ad, nt_v_mirror);
+--
+-- --name table/attr table
+-- vram_nt0 : ram generic map (vram_1k, data_size)
+-- port map (mem_clk, nt0_ce_n, rd_n, wr_n, v_addr(vram_1k - 1 downto 0), vram_ad);
+--
+-- vram_nt1 : ram generic map (vram_1k, data_size)
+-- port map (mem_clk, nt1_ce_n, rd_n, wr_n, v_addr(vram_1k - 1 downto 0), vram_ad);
+--
+-- --APU/DMA instance
+-- apu_inst : apu
+-- port map (cpu_clk, apu_ce_n, rst_n, r_nw, addr, d_io, rdy);
+
+end rtl;
+
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