vga edge reset adjustment

diff --git a/tools/qt_proj_test5/qt_proj_test5.vhd b/tools/qt_proj_test5/qt_proj_test5.vhd
index 3dd2cec..52be8f1 100644 (file)
--- a/tools/qt_proj_test5/qt_proj_test5.vhd
+++ b/tools/qt_proj_test5/qt_proj_test5.vhd
@@ -196,8 +196,7 @@ begin
     dbg_cpu_clk <= vga_clk;\r
     dbg_ppu_addr <= "00000" & dbg_nes_x;\r
     dbg_d_io <= "000" & dbg_plt_addr;\r
-    --dbg_ppu_data <= dbg_plt_data;\r
-    dbg_ppu_data <= "00" & vram_a;\r
+    dbg_ppu_data <= dbg_plt_data;\r
     dbg_addr <= "00" & v_addr;\r
     dbg_ppu_status <= vram_ad;\r
     dbg_ppu_scrl_x(0) <= ale;\r
@@ -357,34 +356,34 @@ end;
                         ppu_set(16#2007#, 16#10#);\r
                     elsif (plt_step_cnt = 10) then\r
                         ppu_set(16#2007#, 16#20#);\r
---\r
---                    elsif (plt_step_cnt = 12) then\r
---                        ppu_set(16#2007#, 16#0f#);\r
---                    elsif (plt_step_cnt = 14) then\r
---                        ppu_set(16#2007#, 16#04#);\r
---                    elsif (plt_step_cnt = 16) then\r
---                        ppu_set(16#2007#, 16#14#);\r
---                    elsif (plt_step_cnt = 18) then\r
---                        ppu_set(16#2007#, 16#24#);\r
--- \r
---                    elsif (plt_step_cnt = 20) then\r
---                        ppu_set(16#2007#, 16#0f#);\r
---                    elsif (plt_step_cnt = 22) then\r
---                        ppu_set(16#2007#, 16#08#);\r
---                    elsif (plt_step_cnt = 24) then\r
---                        ppu_set(16#2007#, 16#18#);\r
---                    elsif (plt_step_cnt = 26) then\r
---                        ppu_set(16#2007#, 16#28#);\r
--- \r
---                    elsif (plt_step_cnt = 28) then\r
---                        ppu_set(16#2007#, 16#0f#);\r
---                    elsif (plt_step_cnt = 30) then\r
---                        ppu_set(16#2007#, 16#0c#);\r
---                    elsif (plt_step_cnt = 32) then\r
---                        ppu_set(16#2007#, 16#1c#);\r
---                    elsif (plt_step_cnt = 34) then\r
---                        ppu_set(16#2007#, 16#2c#);\r
--- \r
+\r
+                    elsif (plt_step_cnt = 12) then\r
+                        ppu_set(16#2007#, 16#0f#);\r
+                    elsif (plt_step_cnt = 14) then\r
+                        ppu_set(16#2007#, 16#04#);\r
+                    elsif (plt_step_cnt = 16) then\r
+                        ppu_set(16#2007#, 16#14#);\r
+                    elsif (plt_step_cnt = 18) then\r
+                        ppu_set(16#2007#, 16#24#);\r
+ \r
+                    elsif (plt_step_cnt = 20) then\r
+                        ppu_set(16#2007#, 16#0f#);\r
+                    elsif (plt_step_cnt = 22) then\r
+                        ppu_set(16#2007#, 16#08#);\r
+                    elsif (plt_step_cnt = 24) then\r
+                        ppu_set(16#2007#, 16#18#);\r
+                    elsif (plt_step_cnt = 26) then\r
+                        ppu_set(16#2007#, 16#28#);\r
+ \r
+                    elsif (plt_step_cnt = 28) then\r
+                        ppu_set(16#2007#, 16#0f#);\r
+                    elsif (plt_step_cnt = 30) then\r
+                        ppu_set(16#2007#, 16#0c#);\r
+                    elsif (plt_step_cnt = 32) then\r
+                        ppu_set(16#2007#, 16#1c#);\r
+                    elsif (plt_step_cnt = 34) then\r
+                        ppu_set(16#2007#, 16#2c#);\r
+ \r
                     else\r
                         ppu_clr;\r
                         if (plt_step_cnt > 10) then\r

diff --git a/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_gate_vhdl.do b/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_gate_vhdl.do
index 610ce62..d691161 100644 (file)
--- a/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_gate_vhdl.do
+++ b/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_gate_vhdl.do
@@ -38,12 +38,10 @@ add wave -label rd_n sim:/testbench_qt_proj_test5/sim_board/dbg_ppu_scrl_x(1)
 add wave -label wr_n sim:/testbench_qt_proj_test5/sim_board/dbg_ppu_scrl_x(2)\r
 add wave -label nt0_ce_n sim:/testbench_qt_proj_test5/sim_board/dbg_ppu_scrl_x(3)\r
 \r
-add wave  -radix hex -label vram_a sim:/testbench_qt_proj_test5/sim_board/dbg_ppu_data\r
-add wave  -radix hex -label vram_ad sim:/testbench_qt_proj_test5/sim_board/dbg_ppu_status\r
 add wave  -radix hex -label v_addr sim:/testbench_qt_proj_test5/sim_board/dbg_addr\r
-\r
-#add wave  -radix hex -label plt_addr sim:/testbench_qt_proj_test5/sim_board/dbg_d_io\r
-#add wave  -radix hex -label plt_data sim:/testbench_qt_proj_test5/sim_board/dbg_ppu_data\r
+add wave  -radix hex -label vram_ad sim:/testbench_qt_proj_test5/sim_board/dbg_ppu_status\r
+add wave  -radix hex -label plt_addr sim:/testbench_qt_proj_test5/sim_board/dbg_d_io\r
+add wave  -radix hex -label plt_data sim:/testbench_qt_proj_test5/sim_board/dbg_ppu_data\r
 \r
 \r
 \r
@@ -85,9 +83,7 @@ view signals
 ###run 10 us\r
 run 3 us\r
 \r
-run 20 us\r
+run 100 us\r
 \r
 wave zoom full\r
 \r
-#run 100 us\r
-\r

diff --git a/tools/qt_proj_test5/vga.vhd b/tools/qt_proj_test5/vga.vhd
index f5d99ca..b5f5593 100644 (file)
--- a/tools/qt_proj_test5/vga.vhd
+++ b/tools/qt_proj_test5/vga.vhd
@@ -430,7 +430,7 @@ constant asize        : integer := 14;
 --constant HSCAN_MAX    : integer := 341;\r
 constant HSCAN_MAX    : integer := 321;\r
 constant VSCAN_MAX    : integer := 262;\r
-constant HSCAN        : integer := 256;\r
+constant HSCAN        : integer := 257;\r
 constant VSCAN        : integer := 240;\r
 --constant HSCAN_NEXT_START    : integer := 320;\r
 --constant HSCAN_NEXT_EXTRA    : integer := 336;\r