DE1_control_panel
~$*
*.lnk
+<<<<<<< HEAD
bin2hex*
+=======
cc65/
+
+>>>>>>> bc7cef00d67db16adec9f9c03eeacb3e3a09bbdf
main_p : process (clk, v_addr, v_data, wr_n)
begin
if (v_addr(13) = '1') then
- ---name tbl
- if ((v_addr(12) and v_addr(11) and v_addr(10)
- and v_addr(9) and v_addr(8)) = '0') then
- if (nt_v_mirror = '1') then
- --bit 10 is the name table selector.
- if (v_addr(10) = '0') then
- --name table 0 enable.
- nt1_ce_n_in <= '1';
- if (wr_n = '0') then
- --write
- nt0_ce_n_in <= not clk;
- elsif (rd_n = '0') then
- --read
- nt0_ce_n_in <= '0';
- else
- nt0_ce_n_in <= '1';
- end if;
+ if (v_addr(13 downto 8) = "111111") then
+ --palette ram
+ nt0_ce_n_in <= '1';
+ nt1_ce_n_in <= '1';
+ else
+ ---name tbl
+ if (((v_addr(11) or v_addr(10)) = '0')
+ or (nt_v_mirror = '1' and v_addr(11) = '1' and v_addr(10) = '0')
+ or (nt_v_mirror = '0' and v_addr(11) = '0' and v_addr(10) = '1')
+ ) then
+ --name table 0 enable.
+ nt1_ce_n_in <= '1';
+ if (wr_n = '0') then
+ --write
+ nt0_ce_n_in <= not clk;
+ elsif (rd_n = '0') then
+ --read
+ nt0_ce_n_in <= '0';
else
- --name table 1 enable.
nt0_ce_n_in <= '1';
- if (wr_n = '0') then
- --write
- nt1_ce_n_in <= clk;
- elsif (rd_n = '0') then
- --read
- nt1_ce_n_in <= '0';
- else
- nt1_ce_n_in <= '1';
- end if;
end if;
- else
- --horizontal mirror.
- --bit 11 is the name table selector.
- if (v_addr(11) = '0') then
- --name table 0 enable.
- nt1_ce_n_in <= '1';
- if (wr_n = '0') then
- --write
- nt0_ce_n_in <= clk;
- elsif (rd_n = '0') then
- --read
- nt0_ce_n_in <= '0';
- else
- nt0_ce_n_in <= '1';
- end if;
+ elsif (((v_addr(11) and v_addr(10)) = '1')
+ or (nt_v_mirror = '1' and v_addr(11) = '0' and v_addr(10) = '1')
+ or (nt_v_mirror = '0' and v_addr(11) = '1' and v_addr(10) = '0')
+ ) then
+ --name table 1 enable.
+ nt0_ce_n_in <= '1';
+ if (wr_n = '0') then
+ --write
+ nt1_ce_n_in <= clk;
+ elsif (rd_n = '0') then
+ --read
+ nt1_ce_n_in <= '0';
else
- --name table 1 enable.
- nt0_ce_n_in <= '1';
- if (wr_n = '0') then
- --write
- nt1_ce_n_in <= clk;
- elsif (rd_n = '0') then
- --read
- nt1_ce_n_in <= '0';
- else
- nt1_ce_n_in <= '1';
- end if;
+ nt1_ce_n_in <= '1';
end if;
- end if; --if (nt_v_mirror = '1') then
- else
- nt0_ce_n_in <= '1';
- nt1_ce_n_in <= '1';
+ else
+ nt0_ce_n_in <= '1';
+ nt1_ce_n_in <= '1';
+ end if;
end if;
else
nt0_ce_n_in <= '1';
signal dma_cnt_ce_n : std_logic_vector(0 downto 0);
signal dma_cnt_ce : std_logic;
signal dma_start_n : std_logic;
+signal dma_write_we_n : std_logic;
signal dma_end_n : std_logic;
signal dma_process_n : std_logic;
signal dma_rst_n : std_logic;
-signal dma_status_we_n : std_logic;
signal dma_status : std_logic_vector(1 downto 0);
signal dma_next_status : std_logic_vector(1 downto 0);
constant DMA_ST_IDLE : std_logic_vector(1 downto 0) := "00";
constant DMA_ST_SETUP : std_logic_vector(1 downto 0) := "01";
constant DMA_ST_PROCESS : std_logic_vector(1 downto 0) := "10";
+constant DMA_ST_COMPLETE : std_logic_vector(1 downto 0) := "11";
begin
port map (clk, dma_rst_n, dma_cnt_ce, '1', (others => '0'),
dma_addr(dsize - 1 downto 0));
dma_h_inst : d_flip_flop generic map(dsize)
- port map (clk_n, '1', '1', dma_start_n, cpu_d,
+ port map (clk_n, '1', '1', dma_write_we_n, cpu_d,
dma_addr(dsize * 2 - 1 downto dsize));
dma_status_inst : d_flip_flop generic map(2)
- port map (clk_n, rst_n, '1', dma_status_we_n, dma_next_status, dma_status);
+ port map (clk_n, rst_n, '1', '0', dma_next_status, dma_status);
dma_val_inst : d_flip_flop generic map(dsize)
port map (clk_n, rst_n, '1', dma_process_n, cpu_d, oam_data);
- --apu register access process
- reg_set_p : process (rst_n, ce_n, r_nw, cpu_addr, cpu_d)
+ dma_write_we_n <= '0'
+ when (ce_n = '0' and r_nw = '0'and cpu_addr(4 downto 0) = OAM_DMA) else
+ '1';
+
+ --dma start process
+ reg_set_p : process (rst_n, clk_n)
begin
- if (rst_n = '1' and ce_n = '0') then
- if (r_nw = '0') then
- --apu write
- cpu_d <= (others => 'Z');
- if (cpu_addr(4 downto 0) = OAM_DMA) then
- dma_start_n <= '0';
- else
- dma_start_n <= '1';
- end if;
- elsif (r_nw = '1') then
- --apu read
- if (cpu_addr(4 downto 0) = OAM_JP1) then
- cpu_d <= (others => '0');
- elsif (cpu_addr(4 downto 0) = OAM_JP2) then
- cpu_d <= (others => '0');
- else
- --return dummy zero vale.
- cpu_d <= (others => '0');
- end if;
- end if;
- else
- cpu_d <= (others => 'Z');
+ if (rst_n = '0') then
dma_start_n <= '1';
- end if; --if (rst_n = '1' and ce_n = '0')
+ rdy <= '1';
+ elsif (rising_edge(clk_n)) then
+ if (ce_n = '0' and r_nw = '0' and cpu_addr(4 downto 0) = OAM_DMA) then
+ dma_start_n <= '0';
+ else
+ dma_start_n <= '1';
+ end if; --if (ce_n = '0')
+
+ if (ce_n = '0' and r_nw = '0' and cpu_addr(4 downto 0) = OAM_DMA) then
+ --pull rdy pin down to stop cpu bus accessing.
+ rdy <= '0';
+ elsif (dma_end_n = '0') then
+ --pull rdy pin up to re-enable cpu bus accessing.
+ rdy <= '1';
+ end if; --if (ce_n = '0')
+ end if; --if (rst_n = '0') then
end process;
--dma operation process
elsif (rising_edge(clk)) then
if (dma_status = DMA_ST_IDLE) then
if (dma_start_n = '0') then
- dma_status_we_n <= '0';
dma_next_status <= DMA_ST_SETUP;
+ else
+ dma_next_status <= DMA_ST_IDLE;
end if;
- dma_process_n <= '1';
dma_end_n <= '1';
+ dma_process_n <= '1';
cpu_addr <= (others => 'Z');
cpu_d <= (others => 'Z');
r_nw <= 'Z';
dma_next_status <= DMA_ST_PROCESS;
elsif (dma_status = DMA_ST_PROCESS) then
if (dma_addr(dsize - 1 downto 0) = "11111111" and dma_cnt_ce_n(0) = '1') then
- dma_status_we_n <= '0';
- dma_next_status <= DMA_ST_IDLE;
- dma_end_n <= '0';
+ dma_next_status <= DMA_ST_COMPLETE;
else
- dma_status_we_n <= '1';
+ dma_next_status <= DMA_ST_PROCESS;
dma_process_n <= '0';
- dma_end_n <= '1';
end if;
if (dma_cnt_ce_n(0) = '0') then
cpu_addr <= OAMDATA;
cpu_d <= oam_data;
end if;
+ elsif (dma_status = DMA_ST_COMPLETE) then
+ dma_next_status <= DMA_ST_IDLE;
+ dma_process_n <= '1';
+ dma_end_n <= '0';
+ r_nw <= 'Z';
+ cpu_addr <= (others => 'Z');
+ cpu_d <= (others => 'Z');
end if;--if (dma_status = DMA_ST_IDLE) then
end if;--if (rst_n = '0') then
end process;
- rdy_p : process (rst_n, clk_n)
- begin
- if (rst_n = '0') then
- rdy <= '1';
- elsif (rising_edge(clk_n)) then
- if (dma_start_n = '0') then
- --pull rdy pin down to stop cpu bus accessing.
- rdy <= '0';
- elsif (dma_end_n = '0') then
- --pull rdy pin up to re-enable cpu bus accessing.
- rdy <= '1';
- end if;
- end if;
- end process;
+-- --joy pad process..
+-- jp_p : process (rst_n, clk_n)
+-- begin
+-- if (rst_n = '0') then
+-- cpu_d <= (others => 'Z');
+-- elsif (rising_edge(clk)) then
+-- if (ce_n = '0' and r_nw = '1') then
+-- --joy pad read
+-- --return dummy zero vale.
+-- if (cpu_addr(4 downto 0) = OAM_JP1) then
+-- cpu_d <= (others => '0');
+-- elsif (cpu_addr(4 downto 0) = OAM_JP2) then
+-- cpu_d <= (others => '0');
+-- else
+-- cpu_d <= (others => 'Z');
+-- end if;
+-- else
+-- cpu_d <= (others => 'Z');
+-- end if; --if (ce_n = '0')
+-- end if; --if (rst_n = '0') then
+-- end process;
end rtl;
---save BAH.
ah_buf_we_n <= '0';
ah_reg_in <= int_d_bus;
- elsif (exec_cycle = T5) then
+ elsif (exec_cycle = T5 or exec_cycle = T0) then
ah_buf_we_n <= '1';
--output ah/al reg.
ea_carry <= addr_c;
elsif (exec_cycle = T4) then
+ ah_buf_we_n <= '1';
+
---add y reg.
a_sel <= ADDR_ADC;
al_reg_in <= addr_out;
tmp_buf_we_n <= '0';
tmp_reg_in <= ah_reg;
- elsif (exec_cycle = T5) then
+ elsif (exec_cycle = T5 or exec_cycle = T0) then
al_buf_we_n <= '1';
tmp_buf_we_n <= '1';
ea_carry <= '0';
- a_sel <= ADDR_INC;
- addr1 <= tmp_reg;
- ---next page.
- abh <= addr_out;
- abl <= al_reg;
+
+ if (pg_next_n = '0') then
+ a_sel <= ADDR_INC;
+ addr1 <= tmp_reg;
+ ---next page.
+ abh <= addr_out;
+ abl <= al_reg;
+ else
+ abh <= tmp_reg;
+ abl <= al_reg;
+ end if;
else
al_buf_we_n <= '1';
ah_buf_we_n <= '1';
signal wk_x_cmd : std_logic_vector(3 downto 0);
signal wk_y_cmd : std_logic_vector(3 downto 0);
signal wk_stat_alu_we_n : std_logic;
+signal ea_carry_reg : std_logic;
begin
pch_inc_reg : d_flip_flop_bit
port map(set_clk, '1', '1', '0', pch_inc_input, pch_inc_n);
+ ea_carry_inst: d_flip_flop_bit
+ port map(trig_clk, '1', '1', '0', ea_carry, ea_carry_reg);
+
--acc,x,y next cycle is changed when it goes page across.
--The conditional branch instructions all have the form xxy10000
next_cycle <= wk_next_cycle;
wk_next_cycle <= T0;
d_print("absx step 1");
- elsif (exec_cycle = T0 and ea_carry = '1') then
+ elsif (exec_cycle = T0 and ea_carry_reg = '1') then
--case page boundary crossed.
--redo inst.
d_print("absx 5 (page boudary crossed.)");
end if;
wk_next_cycle <= T4;
elsif exec_cycle = T4 then
- pg_next_n <= '0';
+ if (ea_carry_reg = '1') then
+ pg_next_n <= '0';
+ else
+ pg_next_n <= '1';
+ end if;
abs_latch_out;
if (is_x = true) then
ea_x_out;
--page handling.
back_oe(wk_y_cmd, '1');
indir_y_n <= '0';
- pg_next_n <= '0';
+
+ --ea_carry reg is suspicious. timing is not garanteed...
+ if (ea_carry_reg = '1') then
+ pg_next_n <= '0';
+ else
+ pg_next_n <= '1';
+ end if;
r_nw <= '0';
wk_next_cycle <= T0;
end if;
elsif exec_cycle = T4 then
abs_latch_out;
ea_x_out;
- pg_next_n <= '0';
+ if (ea_carry_reg = '1') then
+ pg_next_n <= '0';
+ else
+ pg_next_n <= '1';
+ end if;
--keep data in the alu reg.
arith_en_n <= '0';
--case dma is runnting.
disable_pins;
inst_we_n <= '1';
- ad_oe_n <= '0';
+ ad_oe_n <= '1';
dl_al_oe_n <= '1';
pcl_inc_n <= '1';
pcl_cmd <= "1111";
set_location_assignment PIN_L1 -to base_clk\r
set_location_assignment PIN_R22 -to rst_n\r
\r
-##DRAM\r
-set_location_assignment PIN_W4 -to dram_addr[0]\r
-set_location_assignment PIN_W5 -to dram_addr[1]\r
-set_location_assignment PIN_Y3 -to dram_addr[2]\r
-set_location_assignment PIN_Y4 -to dram_addr[3]\r
-set_location_assignment PIN_R6 -to dram_addr[4]\r
-set_location_assignment PIN_R5 -to dram_addr[5]\r
-set_location_assignment PIN_P6 -to dram_addr[6]\r
-set_location_assignment PIN_P5 -to dram_addr[7]\r
-set_location_assignment PIN_P3 -to dram_addr[8]\r
-set_location_assignment PIN_N4 -to dram_addr[9]\r
-set_location_assignment PIN_W3 -to dram_addr[10]\r
-set_location_assignment PIN_N6 -to dram_addr[11]\r
-set_location_assignment PIN_U3 -to dram_bank[0]\r
-set_location_assignment PIN_V4 -to dram_bank[1]\r
-set_location_assignment PIN_T3 -to dram_cas_n\r
-set_location_assignment PIN_N3 -to dram_cke\r
-set_location_assignment PIN_U4 -to dram_clk\r
-set_location_assignment PIN_T6 -to dram_cs_n\r
-set_location_assignment PIN_U1 -to dram_dq[0]\r
-set_location_assignment PIN_U2 -to dram_dq[1]\r
-set_location_assignment PIN_V1 -to dram_dq[2]\r
-set_location_assignment PIN_V2 -to dram_dq[3]\r
-set_location_assignment PIN_W1 -to dram_dq[4]\r
-set_location_assignment PIN_W2 -to dram_dq[5]\r
-set_location_assignment PIN_Y1 -to dram_dq[6]\r
-set_location_assignment PIN_Y2 -to dram_dq[7]\r
-set_location_assignment PIN_N1 -to dram_dq[8]\r
-set_location_assignment PIN_N2 -to dram_dq[9]\r
-set_location_assignment PIN_P1 -to dram_dq[10]\r
-set_location_assignment PIN_P2 -to dram_dq[11]\r
-set_location_assignment PIN_R1 -to dram_dq[12]\r
-set_location_assignment PIN_R2 -to dram_dq[13]\r
-set_location_assignment PIN_T1 -to dram_dq[14]\r
-set_location_assignment PIN_T2 -to dram_dq[15]\r
-set_location_assignment PIN_R7 -to dram_ldqm\r
-set_location_assignment PIN_T5 -to dram_ras_n\r
-set_location_assignment PIN_M5 -to dram_udqm\r
-set_location_assignment PIN_R8 -to dram_we_n\r
+#chr rom mirror setting\r
+set_location_assignment PIN_L2 -to nt_v_mirror\r
+\r
\r
#project files\r
set_global_assignment -name VHDL_FILE address_decoder.vhd\r
set_global_assignment -name VHDL_FILE motonesfpga_common.vhd\r
set_global_assignment -name VHDL_FILE clock/clock_divider.vhd\r
-#set_global_assignment -name VHDL_FILE mem/prg_rom.vhd\r
-set_global_assignment -name VHDL_FILE mem/chr_rom.vhd\r
set_global_assignment -name VHDL_FILE mem/ram.vhd\r
set_global_assignment -name VHDL_FILE apu/apu.vhd\r
+\r
+#ppu block...\r
+set_global_assignment -name VHDL_FILE mem/chr_rom.vhd\r
+set_global_assignment -name VHDL_FILE ppu/ppu.vhd\r
set_global_assignment -name VHDL_FILE ppu/ppu_registers.vhd\r
set_global_assignment -name VHDL_FILE ppu/vga_ppu.vhd\r
-set_global_assignment -name VHDL_FILE ppu/ppu.vhd\r
+\r
+#cpu block...\r
+#set_global_assignment -name VHDL_FILE mem/prg_rom.vhd\r
#set_global_assignment -name VHDL_FILE cpu/alu.vhd\r
#set_global_assignment -name VHDL_FILE cpu/cpu_registers.vhd\r
#set_global_assignment -name VHDL_FILE cpu/decoder.vhd\r
#set_global_assignment -name VHDL_FILE cpu/mos6502.vhd\r
+\r
set_global_assignment -name VHDL_FILE "dummy-mos6502.vhd"\r
set_global_assignment -name VHDL_FILE de1_nes.vhd\r
\r
signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0);
signal dbg_disp_ptn_h, dbg_disp_ptn_l : out std_logic_vector (15 downto 0);
signal dbg_nmi : out std_logic;
-
-
+
--NES instance
base_clk : in std_logic;
rst_n : in std_logic;
v_sync_n : out std_logic;
r : out std_logic_vector(3 downto 0);
g : out std_logic_vector(3 downto 0);
- b : out std_logic_vector(3 downto 0)
+ b : out std_logic_vector(3 downto 0);
+ nt_v_mirror : in std_logic\r
);
end de1_nes;
clk : in std_logic;
ce_n : in std_logic; --active low.
addr : in std_logic_vector (abus_size - 1 downto 0);
- data : out std_logic_vector (dbus_size - 1 downto 0);
- nt_v_mirror : out std_logic
+ data : out std_logic_vector (dbus_size - 1 downto 0)
);
end component;
signal vram_ad : std_logic_vector (7 downto 0);
signal vram_a : std_logic_vector (13 downto 8);
signal v_addr : std_logic_vector (13 downto 0);
- signal nt_v_mirror : std_logic;
signal pt_ce_n : std_logic;
signal nt0_ce_n : std_logic;
signal nt1_ce_n : std_logic;
clock_inst : clock_divider port map
(base_clk, rst_n, cpu_clk, ppu_clk, mem_clk, vga_clk);
+ addr_dec_inst : address_decoder generic map (addr_size, data_size) \r
+ port map (phi2, mem_clk, r_nw, addr, rom_ce_n, ram_ce_n, ppu_ce_n, apu_ce_n);\r
+\r
--mos 6502 cpu instance
cpu_inst : mos6502 generic map (data_size, addr_size)
port map (
dbg_instruction_dummy,
- dbg_int_d_bus_dummy,
+ dbg_int_d_bus,
dbg_exec_cycle_dummy,
- dbg_ea_carry_dummy,
+ dbg_ea_carry,
-- dbg_index_bus,
-- dbg_acc_bus,
dbg_status_dummy,
rst_n, irq_n, nmi_n, dbe, r_nw,
phi1, phi2, addr, d_io);
- addr_dec_inst : address_decoder generic map (addr_size, data_size)
- port map (phi2, mem_clk, r_nw, addr, rom_ce_n, ram_ce_n, ppu_ce_n, apu_ce_n);
-
--main ROM/RAM instance
-- prg_rom_inst : prg_rom generic map (rom_32k, data_size)
-- port map (mem_clk, rom_ce_n, addr(rom_32k - 1 downto 0), d_io);
prg_ram_inst : ram generic map (ram_2k, data_size)
port map (mem_clk, ram_ce_n, ram_oe_n, R_nW, addr(ram_2k - 1 downto 0), d_io);
- dbg_exec_cycle(2 downto 1) <= dbg_vga_x(9 downto 8);
- dbg_int_d_bus <= dbg_vga_x(7 downto 0);
- dbg_exec_cycle(0) <= dbg_nes_x(8);
- dbg_instruction <= dbg_nes_x(7 downto 0);
- dbg_exec_cycle(3) <= dbg_emu_ppu_clk;
-
- dbg_exec_cycle(4) <= dbg_nes_y(8);
- dbg_status <= dbg_nes_y(7 downto 0);
-
-
- dbg_ppu_scrl_x(0) <= ale;
- dbg_ppu_scrl_x(1) <= rd_n;
- dbg_ppu_scrl_x(2) <= wr_n;
- dbg_ppu_scrl_x(3) <= nt0_ce_n;
- dbg_ppu_scrl_x(4) <= vga_clk;
- dbg_ppu_scrl_x(5) <= rom_ce_n;
- dbg_ppu_scrl_x(6) <= ram_ce_n;
- dbg_ppu_scrl_x(7) <= addr(15);
- dbg_ppu_scrl_y(2 downto 0) <= dbg_p_oam_ce_rn_wn(2 downto 0);
- dbg_ppu_scrl_y(5 downto 3) <= dbg_plt_ce_rn_wn(2 downto 0);
--- dbg_disp_ptn_l (7 downto 0) <= dbg_p_oam_addr;
--- dbg_disp_ptn_l (15 downto 8) <= dbg_p_oam_data;
-
- dbg_cpu_clk <= cpu_clk;
- dbg_mem_clk <= mem_clk;
- dbg_r_nw <= r_nw;
- dbg_addr <= addr;
- dbg_d_io <= d_io;
- dbg_vram_ad <= vram_ad ;\r
- dbg_vram_a <= vram_a ;\r
-\r
- dbg_sp(7 downto 6) <= dbg_ppu_clk_cnt;\r
- dbg_sp(5 downto 0) <= v_addr (13 downto 8);\r
- dbg_x <= v_addr (7 downto 0);\r
-\r
- dbg_nmi <= nmi_n;
--- nmi_n <= dummy_nmi;
--- dbg_ppu_ctrl <= dbg_pcl;
--- dbg_ppu_mask <= dbg_pch;
--nes ppu instance
ppu_inst: ppu port map (
dbg_ppu_ce_n ,
dbg_ppu_ctrl, dbg_ppu_mask, dbg_ppu_status ,
dbg_ppu_addr ,
- dbg_ppu_data, dbg_ppu_scrl_x_dummy, dbg_ppu_scrl_y_dummy ,
+ dbg_ppu_data, dbg_ppu_scrl_x_dummy, dbg_ppu_scrl_y ,
dbg_ppu_clk ,
dbg_vga_clk ,
dbg_nes_y ,
dbg_vga_y ,
dbg_disp_nt, dbg_disp_attr ,
- dbg_disp_ptn_h, dbg_disp_ptn_l ,
+ dbg_disp_ptn_h, dbg_disp_ptn_l_dummy ,
dbg_plt_ce_rn_wn ,
dbg_plt_addr ,
dbg_plt_data ,
port map(vga_clk, ale_n, ale, vram_ad, v_addr(7 downto 0));
vchr_rom : chr_rom generic map (chr_rom_8k, data_size)
- port map (mem_clk, pt_ce_n, v_addr(chr_rom_8k - 1 downto 0), vram_ad, nt_v_mirror);
+ port map (mem_clk, pt_ce_n, v_addr(chr_rom_8k - 1 downto 0), vram_ad);
--name table/attr table
vram_nt0 : ram generic map (vram_1k, data_size)
--APU/DMA instance
apu_inst : apu
port map (cpu_clk, apu_ce_n, rst_n, r_nw, addr, d_io, rdy);
-
+\r
+\r
+\r
+-----------------------------------------------------------\r
+-----------------------------------------------------------\r
+------------------debug pin setting....--------------------
+-----------------------------------------------------------\r
+-----------------------------------------------------------\r
+\r
+-- dbg_exec_cycle(2 downto 1) <= dbg_vga_x(9 downto 8);\r
+-- dbg_int_d_bus <= dbg_vga_x(7 downto 0);\r
+ dbg_exec_cycle(0) <= dbg_nes_x(8);\r
+ dbg_instruction <= dbg_nes_x(7 downto 0);\r
+-- dbg_exec_cycle(3) <= dbg_emu_ppu_clk;\r
+\r
+ dbg_exec_cycle(4) <= dbg_nes_y(8);\r
+ dbg_status <= dbg_nes_y(7 downto 0);\r
+\r
+ dbg_ppu_scrl_x(0) <= ale;\r
+ dbg_ppu_scrl_x(1) <= rd_n;\r
+ dbg_ppu_scrl_x(2) <= wr_n;\r
+ dbg_ppu_scrl_x(3) <= nt0_ce_n;\r
+\r
+-- dbg_ppu_scrl_x(4) <= vga_clk;\r
+-- dbg_ppu_scrl_x(5) <= rom_ce_n;\r
+-- dbg_ppu_scrl_x(6) <= ram_ce_n;\r
+-- dbg_ppu_scrl_x(7) <= addr(15);\r
+-- dbg_ppu_scrl_y(2 downto 0) <= dbg_p_oam_ce_rn_wn(2 downto 0);\r
+-- dbg_ppu_scrl_y(5 downto 3) <= dbg_plt_ce_rn_wn(2 downto 0);\r
+ dbg_disp_ptn_l (7 downto 0) <= dbg_p_oam_addr;\r
+ dbg_disp_ptn_l (15 downto 8) <= dbg_p_oam_data;\r
+\r
+ dbg_cpu_clk <= cpu_clk;\r
+ dbg_mem_clk <= mem_clk;\r
+ dbg_r_nw <= r_nw;\r
+ dbg_addr <= addr;\r
+ dbg_d_io <= d_io;\r
+ dbg_vram_ad <= vram_ad ;\r
+ dbg_vram_a <= vram_a ;\r
+\r
+ dbg_sp(7 downto 6) <= dbg_ppu_clk_cnt;\r
+ dbg_sp(5 downto 0) <= v_addr (13 downto 8);\r
+ dbg_x <= v_addr (7 downto 0);\r
+\r
+ dbg_nmi <= nmi_n;\r
+-- nmi_n <= dummy_nmi;\r
+-- dbg_ppu_ctrl <= dbg_pcl;\r
+-- dbg_ppu_mask <= dbg_pch;\r
+\r
end rtl;
use ieee.std_logic_arith.conv_std_logic_vector;\r
\r
variable init_step_cnt, plt_step_cnt, \r
- nt_step_cnt, spr_step_cnt, dma_step_cnt, enable_ppu_step_cnt : integer;\r
+ nt_step_cnt, spr_step_cnt, dma_step_cnt, scl_step_cnt, \r
+ enable_ppu_step_cnt, nmi_step_cnt : integer;\r
variable init_done : std_logic;\r
variable global_step_cnt : integer;\r
constant cpu_io_multi : integer := 3; --io happens every 4 cpu cycle.\r
variable i, j : integer;\r
variable ch : integer := 16#41# ;\r
+ variable nmi_oam_x : integer range 0 to 255;\r
+ variable nmi_scl_y : integer range 0 to 255;\r
\r
procedure io_out (ad: in integer; dt : in integer) is\r
begin\r
nt_step_cnt := 0;\r
spr_step_cnt := 0;\r
dma_step_cnt := 0;\r
+ scl_step_cnt := 0;\r
enable_ppu_step_cnt := 0;\r
+ nmi_step_cnt := 0;\r
+ nmi_oam_x := 0;\r
+ nmi_scl_y := 200;\r
\r
elsif (rising_edge(input_clk)) then\r
\r
--set vram addr 2005 (first row, 6th col)\r
io_out(16#2006#, 16#20#);\r
elsif (nt_step_cnt = 1 * cpu_io_multi) then\r
- io_out(16#2006#, 16#06#);\r
+ io_out(16#2006#, 16#3b#);\r
elsif (nt_step_cnt = 2 * cpu_io_multi) then\r
--set name tbl data\r
--0x44, 45, 45 = DEE\r
\r
\r
elsif (nt_step_cnt = 5 * cpu_io_multi) then\r
- --set vram addr 23c1 (attribute)\r
- io_out(16#2006#, 16#23#);\r
+ io_out(16#2006#, 16#20#);\r
elsif (nt_step_cnt = 6 * cpu_io_multi) then\r
- io_out(16#2006#, 16#c1#);\r
+ io_out(16#2006#, 16#2a#);\r
elsif (nt_step_cnt = 7 * cpu_io_multi) then\r
- --attr=11011000\r
- io_out(16#2007#, 16#d8#);\r
-\r
+ io_out(16#2007#, 16#44#);\r
\r
elsif (nt_step_cnt = 8 * cpu_io_multi) then\r
- io_out(16#2006#, 16#20#);\r
+ io_out(16#2006#, 16#24#);\r
elsif (nt_step_cnt = 9 * cpu_io_multi) then\r
- io_out(16#2006#, 16#60#);\r
-\r
+ io_out(16#2006#, 16#43#);\r
elsif (nt_step_cnt = 10 * cpu_io_multi) then\r
- io_out(16#2007#, 48);\r
+ io_out(16#2007#, 16#6d#);\r
elsif (nt_step_cnt = 11 * cpu_io_multi) then\r
- io_out(16#2007#, 49);\r
+ io_out(16#2007#, 16#6f#);\r
elsif (nt_step_cnt = 12 * cpu_io_multi) then\r
- io_out(16#2007#, 50);\r
+ io_out(16#2007#, 16#74#);\r
elsif (nt_step_cnt = 13 * cpu_io_multi) then\r
- io_out(16#2007#, 51);\r
+ io_out(16#2007#, 16#6f#);\r
+ \r
elsif (nt_step_cnt = 14 * cpu_io_multi) then\r
- io_out(16#2007#, 52);\r
+ io_out(16#2006#, 16#2e#);\r
elsif (nt_step_cnt = 15 * cpu_io_multi) then\r
- io_out(16#2007#, 53);\r
+ io_out(16#2006#, 16#93#);\r
elsif (nt_step_cnt = 16 * cpu_io_multi) then\r
- io_out(16#2007#, 54);\r
- elsif (nt_step_cnt = 17 * cpu_io_multi) then\r
- io_out(16#2007#, 55);\r
- elsif (nt_step_cnt = 18 * cpu_io_multi) then\r
- io_out(16#2007#, 56);\r
-\r
- -- elsif (nt_step_cnt = 5 * cpu_io_multi) then\r
- -- --set vram addr 21d1\r
- -- io_out(16#2006#, 16#21#);\r
- -- elsif (nt_step_cnt = 6 * cpu_io_multi) then\r
- -- io_out(16#2006#, 16#E6#);\r
- -- elsif (nt_step_cnt = 7 * cpu_io_multi) then\r
- -- --msg=DEE TEST !!!\r
- -- io_out(16#2007#, 16#44#);\r
- -- elsif (nt_step_cnt = 8 * cpu_io_multi) then\r
- -- io_out(16#2007#, 16#45#);\r
- -- elsif (nt_step_cnt = 9 * cpu_io_multi) then\r
- -- io_out(16#2007#, 16#45#);\r
- -- elsif (nt_step_cnt = 10 * cpu_io_multi) then\r
- -- io_out(16#2007#, 16#00#);\r
- -- elsif (nt_step_cnt = 11 * cpu_io_multi) then\r
- -- io_out(16#2007#, 16#54#);\r
- -- elsif (nt_step_cnt = 12 * cpu_io_multi) then\r
- -- io_out(16#2007#, 16#45#);\r
- -- elsif (nt_step_cnt = 13 * cpu_io_multi) then\r
- -- io_out(16#2007#, 16#53#);\r
- -- elsif (nt_step_cnt = 14 * cpu_io_multi) then\r
- -- io_out(16#2007#, 16#54#);\r
- -- elsif (nt_step_cnt = 15 * cpu_io_multi) then\r
- -- io_out(16#2007#, 16#21#);\r
-\r
- --display test pattern\r
- elsif (nt_step_cnt = 19 * cpu_io_multi) then\r
- io_out(16#2006#, 16#20#);\r
- elsif (nt_step_cnt = 20 * cpu_io_multi) then\r
- io_out(16#2006#, 16#20#);\r
- \r
- elsif (nt_step_cnt = 21 * cpu_io_multi) then\r
- io_out(16#2007#, 16#01#);\r
- elsif (nt_step_cnt = 22 * cpu_io_multi) then\r
- io_out(16#2007#, 16#02#);\r
- elsif (nt_step_cnt = 23 * cpu_io_multi) then\r
- io_out(16#2007#, 16#03#);\r
- elsif (nt_step_cnt = 24 * cpu_io_multi) then\r
- io_out(16#2007#, 16#04#);\r
- elsif (nt_step_cnt = 25 * cpu_io_multi) then\r
- io_out(16#2007#, 16#05#);\r
- elsif (nt_step_cnt = 26 * cpu_io_multi) then\r
- io_out(16#2007#, 16#06#);\r
- elsif (nt_step_cnt = 27 * cpu_io_multi) then\r
- io_out(16#2007#, 16#07#);\r
- elsif (nt_step_cnt = 28 * cpu_io_multi) then\r
- io_out(16#2007#, 16#08#);\r
- elsif (nt_step_cnt = 29 * cpu_io_multi) then\r
- io_out(16#2007#, 16#09#);\r
- elsif (nt_step_cnt = 30 * cpu_io_multi) then\r
- io_out(16#2007#, 16#0a#);\r
- elsif (nt_step_cnt = 31 * cpu_io_multi) then\r
- io_out(16#2007#, 16#0b#);\r
- elsif (nt_step_cnt = 32 * cpu_io_multi) then\r
- io_out(16#2007#, 16#0c#);\r
- elsif (nt_step_cnt = 33 * cpu_io_multi) then\r
- io_out(16#2007#, 16#0d#);\r
- elsif (nt_step_cnt = 34 * cpu_io_multi) then\r
- io_out(16#2007#, 16#0e#);\r
- elsif (nt_step_cnt = 35 * cpu_io_multi) then\r
- io_out(16#2007#, 16#0f#);\r
+ io_out(16#2007#, 16#59#);\r
\r
- elsif (nt_step_cnt = 36 * cpu_io_multi) then\r
- io_out(16#2006#, 16#20#);\r
- elsif (nt_step_cnt = 37 * cpu_io_multi) then\r
- io_out(16#2006#, 16#40#);\r
- \r
- elsif (nt_step_cnt = 38 * cpu_io_multi) then\r
- io_out(16#2007#, 16#10#);\r
- elsif (nt_step_cnt = 39 * cpu_io_multi) then\r
- io_out(16#2007#, 16#11#);\r
- elsif (nt_step_cnt = 40 * cpu_io_multi) then\r
- io_out(16#2007#, 16#12#);\r
- elsif (nt_step_cnt = 41 * cpu_io_multi) then\r
- io_out(16#2007#, 16#13#);\r
- elsif (nt_step_cnt = 42 * cpu_io_multi) then\r
- io_out(16#2007#, 16#14#);\r
- elsif (nt_step_cnt = 43 * cpu_io_multi) then\r
- io_out(16#2007#, 16#15#);\r
- elsif (nt_step_cnt = 44 * cpu_io_multi) then\r
- io_out(16#2007#, 16#16#);\r
- elsif (nt_step_cnt = 45 * cpu_io_multi) then\r
- io_out(16#2007#, 16#17#);\r
- elsif (nt_step_cnt = 46 * cpu_io_multi) then\r
- io_out(16#2007#, 16#18#);\r
- elsif (nt_step_cnt = 47 * cpu_io_multi) then\r
- io_out(16#2007#, 16#19#);\r
- elsif (nt_step_cnt = 48 * cpu_io_multi) then\r
- io_out(16#2007#, 16#1a#);\r
- elsif (nt_step_cnt = 49 * cpu_io_multi) then\r
- io_out(16#2007#, 16#1b#);\r
- elsif (nt_step_cnt = 50 * cpu_io_multi) then\r
- io_out(16#2007#, 16#1c#);\r
- elsif (nt_step_cnt = 51 * cpu_io_multi) then\r
- io_out(16#2007#, 16#1d#);\r
- elsif (nt_step_cnt = 52 * cpu_io_multi) then\r
- io_out(16#2007#, 16#1e#);\r
- elsif (nt_step_cnt = 53 * cpu_io_multi) then\r
- io_out(16#2007#, 16#1f#);\r
+ elsif (nt_step_cnt = 17 * cpu_io_multi) then\r
+ io_out(16#2007#, 16#00#);\r
\r
else\r
io_brk;\r
- if (nt_step_cnt > 4 * cpu_io_multi) then\r
+ if (nt_step_cnt > 17 * cpu_io_multi) then\r
global_step_cnt := global_step_cnt + 1;\r
end if;\r
end if;\r
else\r
io_brk;\r
if (spr_step_cnt > 4 * cpu_io_multi) then\r
- global_step_cnt := global_step_cnt + 1;\r
+ global_step_cnt := global_step_cnt + 2;\r
end if;\r
end if;\r
spr_step_cnt := spr_step_cnt + 1;\r
dma_step_cnt := dma_step_cnt + 1;\r
\r
elsif (global_step_cnt = 5) then\r
+ --step4 = scroll test.\r
+ if (scl_step_cnt = 0) then\r
+ --x scroll pos=123\r
+ io_out(16#2005#, 123);\r
+ elsif (scl_step_cnt = 1 * cpu_io_multi) then\r
+ --y scroll pos=100\r
+ io_out(16#2005#, 100);\r
+\r
+ else\r
+ io_brk;\r
+ if (scl_step_cnt > 1 * cpu_io_multi) then\r
+ global_step_cnt := global_step_cnt + 1;\r
+ end if;\r
+ end if;\r
+ scl_step_cnt := scl_step_cnt + 1;\r
+\r
+ elsif (global_step_cnt = 6) then\r
--final step = enable ppu.\r
if (enable_ppu_step_cnt = 0 * cpu_io_multi) then\r
- --scroll reg set x.\r
- io_out(16#2005#, 0);\r
- elsif (enable_ppu_step_cnt = 1 * cpu_io_multi) then\r
- --scroll reg set y.\r
- io_out(16#2005#, 0);\r
- elsif (enable_ppu_step_cnt = 2 * cpu_io_multi) then\r
--show bg\r
--PPUMASK=1e (show bg and sprite)\r
--PPUMASK=0e (show bg only)\r
io_out(16#2001#, 16#1e#);\r
- elsif (enable_ppu_step_cnt = 3 * cpu_io_multi) then\r
+ elsif (enable_ppu_step_cnt = 1 * cpu_io_multi) then\r
--enable nmi\r
--PPUCTRL=80\r
io_out(16#2000#, 16#80#);\r
else\r
io_brk;\r
- if (enable_ppu_step_cnt > 4 * cpu_io_multi) then\r
+ if (enable_ppu_step_cnt > 1 * cpu_io_multi) then\r
global_step_cnt := global_step_cnt + 1;\r
end if;\r
end if;\r
enable_ppu_step_cnt := enable_ppu_step_cnt + 1;\r
\r
+ elsif (global_step_cnt = 7) then\r
+ ----nmi tests.....\r
+ if (nmi_n = '0') then\r
+\r
+ if (nmi_step_cnt = 0 * cpu_io_multi) then\r
+ --set sprite addr=00 (first sprite)\r
+ io_out(16#2003#, 16#03#);\r
+ elsif (nmi_step_cnt = 1 * cpu_io_multi) then\r
+ --set sprite data: x=100\r
+ io_out(16#2004#, nmi_oam_x);\r
+ elsif (nmi_step_cnt = 2 * cpu_io_multi) then\r
+ --scroll x=0\r
+-- io_out(16#2005#, nmi_scl_y);\r
+ elsif (nmi_step_cnt = 3 * cpu_io_multi) then\r
+ --scroll y++\r
+-- io_out(16#2005#, nmi_scl_y);\r
+ else\r
+ nmi_oam_x := nmi_oam_x + 1;\r
+ if (nmi_step_cnt mod 10 = 0) then\r
+ nmi_scl_y := nmi_scl_y + 1;\r
+ end if;\r
+ io_brk;\r
+ if (nmi_step_cnt > 3 * cpu_io_multi) then\r
+ global_step_cnt := global_step_cnt + 1;\r
+ end if;\r
+ end if;\r
+ nmi_step_cnt := nmi_step_cnt + 1;\r
+ end if;\r
+ elsif (global_step_cnt = 8) then\r
+ ----back to nmi tests.....\r
+ if (nmi_n = '1') then\r
+ nmi_step_cnt := 0;\r
+ global_step_cnt := global_step_cnt - 1;\r
+ end if;\r
else\r
io_brk;\r
init_done := '1';\r
clk : in std_logic;
ce_n : in std_logic; --active low.
addr : in std_logic_vector (abus_size - 1 downto 0);
- data : out std_logic_vector (dbus_size - 1 downto 0);
- nt_v_mirror : out std_logic
+ data : out std_logic_vector (dbus_size - 1 downto 0)
);
end chr_rom;
return ret;
end rom_fill;
-function vmirror return std_logic is
- type binary_file is file of character;
- FILE nes_file : binary_file OPEN read_mode IS "rom-file.nes" ;
- variable read_data : character;
- variable i : integer;
- variable ret : std_logic_vector(7 downto 0);
- begin
- --read NES cardridge header part
- for i in 0 to 15 loop
- read(nes_file, read_data);
- if (i = 6) then
- ret :=
- conv_std_logic_vector(character'pos(read_data), 8);
- end if;
- end loop;
- d_print("nes header read ok.");
- return ret(0);
- end vmirror;
-
--for GHDL environment
--itinialize with the rom_fill function.
--signal p_rom : rom_array := rom_fill;
begin
- --nt_v_mirror <= vmirror;
- nt_v_mirror <= '1';
-
p : process (clk)
begin
if (rising_edge(clk)) then
);
end component;
+component d_flip_flop_bit
+ port (
+ clk : in std_logic;
+ res_n : in std_logic;
+ set_n : in std_logic;
+ we_n : in std_logic;
+ d : in std_logic;
+ q : out std_logic
+ );
+end component;
+
constant dsize : integer := 8;
constant PPUCTRL : std_logic_vector(2 downto 0) := "000";
signal oam_plt_addr : std_logic_vector (dsize - 1 downto 0);
signal oam_plt_data : std_logic_vector (dsize - 1 downto 0);
signal plt_data_out : std_logic_vector (dsize - 1 downto 0);
+signal ST_VBL_old : std_logic;
begin
plt_data_out_inst : d_flip_flop generic map(dsize)
port map (ppu_clk_n, rst_n, '1', ppu_data_we_n, oam_plt_data, plt_data_out);
+ ST_VBL_old_inst : d_flip_flop_bit
+ port map (ppu_clk_n, rst_n, '1', '0', ppu_status(ST_VBL), ST_VBL_old);
+
+
reg_set_p : process (rst_n, ce_n, r_nw, cpu_addr)
begin
ppu_mask_we_n <= '1';
oam_addr_we_n <= '1';
oam_data_we_n <= '1';
- ppu_scroll_x_we_n <= '1';
- ppu_scroll_y_we_n <= '1';
ppu_scroll_cnt_ce_n <= '1';
read_status <= '0';
read_data_n <= '1';
elsif (rst_n = '1' and ce_n = '0') then
--register set.
- if(cpu_addr = PPUCTRL) then
+ if(cpu_addr = PPUCTRL and r_nw = '0') then
ppu_ctrl_we_n <= '0';
else
ppu_ctrl_we_n <= '1';
end if;
- if(cpu_addr = PPUMASK) then
+ if(cpu_addr = PPUMASK and r_nw = '0') then
ppu_mask_we_n <= '0';
else
ppu_mask_we_n <= '1';
read_status <= '0';
end if;
- if(cpu_addr = OAMADDR) then
+ if(cpu_addr = OAMADDR and r_nw = '0') then
oam_addr_we_n <= '0';
else
oam_addr_we_n <= '1';
end if;
- if(cpu_addr = OAMDATA) then
+ if(cpu_addr = OAMDATA and r_nw = '0') then
oam_data_we_n <= '0';
else
oam_data_we_n <= '1';
end if;
- if(cpu_addr = PPUSCROLL) then
+ if(cpu_addr = PPUSCROLL and r_nw = '0') then
ppu_scroll_cnt_ce_n <= '0';
- if (ppu_scroll_cnt(0) = '0') then
- ppu_scroll_x_we_n <= '0';
- ppu_scroll_y_we_n <= '1';
- else
- ppu_scroll_y_we_n <= '0';
- ppu_scroll_x_we_n <= '1';
- end if;
else
- ppu_scroll_x_we_n <= '1';
- ppu_scroll_y_we_n <= '1';
ppu_scroll_cnt_ce_n <= '1';
end if;
ppu_mask_we_n <= '1';
oam_addr_we_n <= '1';
oam_data_we_n <= '1';
- ppu_scroll_x_we_n <= '1';
- ppu_scroll_y_we_n <= '1';
ppu_scroll_cnt_ce_n <= '1';
read_status <= '0';
read_data_n <= '1';
ppu_clk_cnt_res_n <= not ce_n;
+ --scroll reg...
+ scl_reg_p : process (rst_n, ppu_clk)
+ begin
+ if (rst_n = '0') then
+ ppu_scroll_x_we_n <= '1';
+ ppu_scroll_y_we_n <= '1';
+ elsif (rising_edge(ppu_clk)) then
+ if (ppu_scroll_cnt_ce_n = '0' and ppu_clk_cnt = "01" and r_nw = '0') then
+ if (ppu_scroll_cnt(0) = '1') then
+ ppu_scroll_x_we_n <= '0';
+ ppu_scroll_y_we_n <= '1';
+ else
+ ppu_scroll_y_we_n <= '0';
+ ppu_scroll_x_we_n <= '1';
+ end if;
+ else
+ ppu_scroll_x_we_n <= '1';
+ ppu_scroll_y_we_n <= '1';
+ end if;
+ end if;
+ end process;
+
--cpu nmi generation...
clk_nmi_p : process (rst_n, ppu_clk)
begin
vblank_n <= '1';
elsif (rising_edge(ppu_clk)) then
if (ppu_status(ST_VBL) = '1' and ppu_ctrl(PPUNEN) = '1') then
- --start vblank.
- vblank_n <= '0';
+ --nmi takes place only when ST_VBL arises...
+ --doesn't work....
+-- if (ST_VBL_old = '0') then
+ --start vblank.
+ vblank_n <= '0';
+-- end if;
else
--clear flag.
vblank_n <= '1';
end process;
--cpu and ppu clock timing adjustment...
- clk_cnt_set_p : process (rst_n, ce_n, r_nw, cpu_addr, ppu_clk)
+ clk_cnt_set_p : process (rst_n, ce_n, r_nw, cpu_addr, ppu_clk, cpu_d, ppu_clk_cnt, ppu_addr_cnt)
begin
if (rst_n = '0') then
ppu_latch_rst_n <= '0';
signal spr_tile_tmp : std_logic_vector (dsize - 1 downto 0);\r
signal spr_ptn_in : std_logic_vector (dsize - 1 downto 0);\r
\r
+signal sprite0_evaluated : std_logic;\r
+signal sprite0_displayed : std_logic;\r
\r
begin\r
dbg_ppu_clk <= ppu_clk;\r
\r
prf_y <= cur_y + ppu_scroll_y\r
when cur_x < conv_std_logic_vector(HSCAN, X_SIZE) and\r
- cur_y + ppu_scroll_y <\r
- conv_std_logic_vector(VSCAN_MAX - 1, X_SIZE) else\r
+ cur_y < conv_std_logic_vector(VSCAN, X_SIZE) else\r
cur_y + ppu_scroll_y + "000000001" \r
- when cur_y + ppu_scroll_y <\r
- conv_std_logic_vector(VSCAN_MAX - 1, X_SIZE) else\r
+ when cur_y < conv_std_logic_vector(VSCAN_MAX - 1, X_SIZE) else\r
"000000000"; \r
\r
nt_inst : d_flip_flop generic map(dsize)\r
end if; --if (rst_n = '0') then\r
end process;\r
\r
- clk_p : process (rst_n, ppu_clk, read_status)\r
+ clk_p : process (rst_n, ppu_clk)\r
\r
procedure output_rgb is\r
variable pl_addr : integer;\r
variable pl_index : integer;\r
-variable dot_output : boolean;\r
begin\r
- dot_output := false;\r
-\r
- --first show sprite.\r
- if (ppu_mask(PPUSSP) = '1') then\r
- for i in 0 to 7 loop\r
- if (spr_x_cnt(i) = "00000000") then\r
- if ((spr_ptn_h(i)(0) or spr_ptn_l(i)(0)) = '1') then\r
- dot_output := true;\r
- exit;\r
- end if;\r
- end if;\r
- end loop;\r
- end if;\r
-\r
- if (dot_output = true and ppu_mask(PPUSBG) = '1' and \r
- (disp_ptn_h(0) or disp_ptn_l(0)) = '1') then\r
- --raise sprite 0 hit.\r
- ppu_status(ST_SP0) <= '1';\r
- end if;\r
-\r
- --first color in the palette is transparent color.\r
- if (ppu_mask(PPUSBG) = '1' and dot_output = false and \r
- (disp_ptn_h(0) or disp_ptn_l(0)) = '1') then\r
- dot_output := true;\r
+ if (rst_n = '0') then\r
+ b <= (others => '0');\r
+ g <= (others => '0');\r
+ r <= (others => '0');\r
+ else\r
+ if ((cur_x < conv_std_logic_vector(HSCAN, X_SIZE)) and\r
+ (cur_y < conv_std_logic_vector(VSCAN, X_SIZE))) then\r
+ --if or if not bg/sprite is shown, output color anyway \r
+ --sinse universal bg color is included..\r
+ pl_index := conv_integer(plt_data(5 downto 0));\r
+ b <= nes_color_palette(pl_index) (11 downto 8);\r
+ g <= nes_color_palette(pl_index) (7 downto 4);\r
+ r <= nes_color_palette(pl_index) (3 downto 0);\r
+ else\r
+ b <= (others => '0');\r
+ g <= (others => '0');\r
+ r <= (others => '0');\r
+ end if;\r
end if;\r
-\r
- --if or if not bg/sprite is shown, output color anyway \r
- --sinse universal bg color is included..\r
- pl_index := conv_integer(plt_data(5 downto 0));\r
- b <= nes_color_palette(pl_index) (11 downto 8);\r
- g <= nes_color_palette(pl_index) (7 downto 4);\r
- r <= nes_color_palette(pl_index) (3 downto 0);\r
end;\r
-procedure stop_rgb is\r
+\r
+procedure set_sp0_hit is\r
begin\r
- b <= (others => '0');\r
- g <= (others => '0');\r
- r <= (others => '0');\r
+ if (rst_n = '0') then\r
+ ppu_status(ST_SP0) <= '0';\r
+ else\r
+ if ((cur_x < conv_std_logic_vector(HSCAN, X_SIZE)) and\r
+ (cur_y < conv_std_logic_vector(VSCAN, X_SIZE))) then\r
+ if (sprite0_displayed = '1' \r
+ and (ppu_mask(PPUSSP) = '1' and (spr_x_cnt(0) & (spr_ptn_h(0)(0) or spr_ptn_l(0)(0)) = "000000001"))\r
+ and (ppu_mask(PPUSBG) = '1' and ((disp_ptn_h(0) or disp_ptn_l(0)) = '1'))\r
+ ) then\r
+ --raise sprite 0 hit.\r
+ ppu_status(ST_SP0) <= '1';\r
+ end if;\r
+ else\r
+ ppu_status(ST_SP0) <= '0';\r
+ end if;\r
+ end if;\r
end;\r
\r
begin\r
nt_we_n <= '1';\r
ppu_status <= (others => '0');\r
s_oam_data <= (others => 'Z');\r
- stop_rgb;\r
else\r
\r
if (ppu_clk'event and ppu_clk = '1') then\r
s_oam_cnt_ce_n <= '0';\r
--copy remaining oam entry.\r
p_oam_cnt_ce_n <= '1';\r
+ \r
+ --check sprite 0 is used.\r
+ if (p_oam_cnt = "00000000") then\r
+ sprite0_evaluated <= '1';\r
+ end if;\r
else\r
--goto next entry\r
p_oam_cnt_ce_n <= '0';\r
else\r
spr_ptn_h_we_n(conv_integer(s_oam_addr_cpy(4 downto 2) - "001")) <= '1';\r
end if;\r
+ \r
+ --check sprite 0 is used in the next line.\r
+ if (sprite0_evaluated = '1') then\r
+ sprite0_displayed <= '1';\r
+ end if;\r
\r
elsif (cur_x > conv_std_logic_vector(320, X_SIZE)) then\r
--clear last write enable.\r
spr_x_ce_n <= "11111111";\r
spr_ptn_ce_n <= "11111111";\r
end if; --if ((cur_x < conv_std_logic_vector(HSCAN, X_SIZE)) \r
- end if; --if (ppu_mask(PPUSSP) = '1') then\r
+ else\r
+ --sprite evaluation are cleared during the blank line.\r
+ sprite0_evaluated <= '0';\r
+ sprite0_displayed <= '0';\r
+ end if; --if (ppu_mask(PPUSSP) = '1') \r
+ --(cur_y < conv_std_logic_vector(VSCAN, X_SIZE) or \r
+ --cur_y = conv_std_logic_vector(VSCAN_MAX - 1, X_SIZE))) then\r
+ \r
\r
--output visible area only.\r
- if ((cur_x < conv_std_logic_vector(HSCAN, X_SIZE)) and\r
- (cur_y < conv_std_logic_vector(VSCAN, X_SIZE))) then\r
- --output image.\r
- output_rgb;\r
- else\r
- stop_rgb;\r
- end if;\r
+ output_rgb;\r
\r
--flag operation\r
- if ((cur_x = conv_std_logic_vector(1, X_SIZE)) and\r
- (cur_y = conv_std_logic_vector(VSCAN + 1, X_SIZE))) then\r
+ --TODO: sprite overflow is not inplemented!\r
+ ppu_status(ST_SOF) <= '0';\r
+ set_sp0_hit;\r
+\r
+ if ((cur_y > conv_std_logic_vector(VSCAN, X_SIZE))) then\r
--vblank start\r
ppu_status(ST_VBL) <= '1';\r
- elsif ((cur_x = conv_std_logic_vector(1, X_SIZE)) and\r
- (cur_y = conv_std_logic_vector(VSCAN_MAX - 1, X_SIZE))) then\r
- ppu_status(ST_SP0) <= '0';\r
+ else\r
--vblank end\r
ppu_status(ST_VBL) <= '0';\r
- --TODO: sprite overflow is not inplemented!\r
- ppu_status(ST_SOF) <= '0';\r
end if;\r
end if; --if (clk'event and clk = '1') then\r
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+:201AE0002A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A38A977EA092D\r
+:201B0000F0C9F7F0032054804C1A9F2A2A2A2A2A372A2A2A2A2A2A2A2A2A2A2A2A2A2A2AAA\r
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+:201BC0002A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2AC5\r
+:201BE0002A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A38A9C18D2006A991EAED200611\r
+:201C0000C9D0F0032054804C1D9F2A2A2A2A2A2A382A2A2A2A2A2A2A2A2A2A2A2A2A2A2A92\r
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+:201DC0002A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2AC3\r
+:201DE0002A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A269FEA6CFB5F\r
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+:201E20002A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A62\r
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+:201E80002A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A02\r
+:201EA0002A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2AE2\r
+:201EC0002A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2AC2\r
+:201EE0002A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2C9FEA6C29\r
+:201F0000FC9E4C2F9F4CFE944CFD954CFC964CFC974CFF984CFC994CFB9A4CF49B4CFC9C30\r
+:201F20004C009D4CFD9D4C019E4CFE9E4C029FADD08E8500ADD18E850120B88D6001010029\r
:201F4000000000000000000000000000000000000000000000000000000000000000000081\r
:201F6000000000000000000000000000000000000000000000000000000000000000000061\r
:201F8000000000000000000000000000000000000000000000000000000000000000000041\r
:201FA000000000000000000000000000000000000000000000000000000000000000000021\r
:201FC000000000000000000000000000000000000000000000000000000000000000000001\r
-:201FE0000000000000000000000000000000000000000000000000000000000000000000E1\r
+:201FE00000000000000000000000000000000000000000000000000000007F83008000005F\r
:00000001FF\r
\r
add wave -divider cpu\r
add wave -label rst_n sim:/testbench_motones_sim/sim_board/rst_n\r
-add wave -label nmi sim:/testbench_motones_sim/sim_board/dbg_nmi\r
+add wave -label nmi sim:/testbench_motones_sim/sim_board/dbg_nmi\r
add wave -label cpu_clk sim:/testbench_motones_sim/sim_board/dbg_cpu_clk\r
#add wave -label vga_clk sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(4)\r
#add wave -label mem_clk sim:/testbench_motones_sim/sim_board/dbg_mem_clk\r
add wave -label r_nw sim:/testbench_motones_sim/sim_board/dbg_r_nw\r
add wave -label addr -radix hex sim:/testbench_motones_sim/sim_board/dbg_addr\r
add wave -label d_io -radix hex sim:/testbench_motones_sim/sim_board/dbg_d_io\r
-#add wave -label instruction -radix hex sim:/testbench_motones_sim/sim_board/dbg_instruction\r
+add wave -label instruction -radix hex sim:/testbench_motones_sim/sim_board/dbg_instruction\r
\r
\r
add wave -divider ce-pins\r
-#add wave -label rom_ce_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(5)\r
-#add wave -label ram_ce_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(6)\r
+add wave -label rom_ce_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(5)\r
+add wave -label ram_ce_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(6)\r
\r
#add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_int_d_bus\r
-#add wave -label exec_cycle -radix hex sim:/testbench_motones_sim/sim_board/dbg_exec_cycle\r
-#add wave -label ea_carry -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/dbg_ea_carry \r
+add wave -label exec_cycle -radix hex sim:/testbench_motones_sim/sim_board/dbg_exec_cycle\r
+add wave -label ea_carry -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/dbg_ea_carry \r
#add wave -label wait_a58_branch_next -radix hex sim:/testbench_motones_sim/sim_board/dbg_wait_a58_branch_next \r
\r
\r
\r
-add wave -divider regs\r
-\r
+#add wave -divider regs\r
+#\r
#add wave -label pcl -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_ctrl\r
#add wave -label pch -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_mask\r
-\r
+#\r
#add wave -label acc -radix hex sim:/testbench_motones_sim/sim_board/dbg_acc\r
#add wave -label sp -radix hex sim:/testbench_motones_sim/sim_board/dbg_sp\r
#add wave -label x -radix hex sim:/testbench_motones_sim/sim_board/dbg_x\r
#add wave -label status -radix hex sim:/testbench_motones_sim/sim_board/dbg_status\r
\r
\r
-#add wave -divider ppu\r
+add wave -divider ppu\r
add wave -label ppu_clk sim:/testbench_motones_sim/sim_board/dbg_ppu_clk\r
add wave -label ppu_ce_n sim:/testbench_motones_sim/sim_board/dbg_ppu_ce_n\r
add wave -label ppu_ctrl -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_ctrl\r
add wave -label ppu_mask -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_mask\r
-#add wave -label ppu_status -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_status\r
+add wave -label ppu_status -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_status\r
add wave -label ppu_addr -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_addr\r
add wave -label ppu_data -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_data\r
+add wave -label ppu_scrl_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x\r
+add wave -label ppu_scrl_y -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y\r
\r
\r
add wave -divider vga_pos\r
-add wave -label vga_x -radix decimal -unsigned {sim:/testbench_motones_sim/sim_board/dbg_exec_cycle(2 downto 1) & sim:/testbench_motones_sim/sim_board/dbg_int_d_bus (7 downto 0)}\r
-add wave -label nes_y -radix decimal -unsigned {sim:/testbench_motones_sim/sim_board/dbg_exec_cycle(4) & sim:/testbench_motones_sim/sim_board/dbg_status (7 downto 0)}\r
-\r
-add wave -label emu_ppu_clk sim:/testbench_motones_sim/sim_board/dbg_exec_cycle(3)\r
-add wave -label nes_x -radix decimal -unsigned {sim:/testbench_motones_sim/sim_board/dbg_exec_cycle(0) & sim:/testbench_motones_sim/sim_board/dbg_instruction (7 downto 0)}\r
+add wave -label nes_x -radix decimal -unsigned {sim:/testbench_motones_sim/sim_board/dbg_exec_cycle(0) & \r
+ sim:/testbench_motones_sim/sim_board/dbg_instruction(7 downto 0)}\r
+add wave -label nes_y -radix decimal -unsigned {sim:/testbench_motones_sim/sim_board/dbg_exec_cycle(4) & \r
+ sim:/testbench_motones_sim/sim_board/dbg_status(7 downto 0)}\r
add wave -label dbg_disp_nt -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_nt\r
add wave -label dbg_disp_attr -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_attr\r
-add wave -label dbg_disp_ptn_h -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_h\r
-add wave -label dbg_disp_ptn_l -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_l\r
+#add wave -label dbg_disp_ptn_h -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_h\r
+#add wave -label dbg_disp_ptn_l -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_l\r
\r
add wave -divider vram\r
-\r
-\r
-add wave -label ppu_clk_cnt -radix decimal -unsigned {sim:/testbench_motones_sim/sim_board/dbg_sp(7 downto 6)}\r
-\r
add wave -label ale sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(0)\r
add wave -label rd_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(1)\r
add wave -label wr_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(2)\r
add wave -label nt0_ce_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(3)\r
-###add wave -radix hex -label vram_addr {sim:/testbench_motones_sim/sim_board/dbg_vram_a(13 downto 8) & sim:/testbench_motones_sim/sim_board/dbg_vram_ad(7 downto 0)}\r
-add wave -radix hex -label v_addr {sim:/testbench_motones_sim/sim_board/dbg_sp(5 downto 0) & sim:/testbench_motones_sim/sim_board/dbg_x(7 downto 0)}\r
+\r
+add wave -radix hex -label v_addr {sim:/testbench_motones_sim/sim_board/dbg_sp(5 downto 0)}\r
add wave -radix hex -label vram_ad sim:/testbench_motones_sim/sim_board/dbg_vram_ad\r
\r
-###\r
-###\r
-###add wave -label plt_ce_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(5)\r
-###add wave -label plt_r_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(4)\r
-###add wave -label plt_w_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(3)\r
-###add wave -radix hex -label plt_addr {sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_h(12 downto 8)}\r
-###add wave -radix hex -label plt_data {sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_h(7 downto 0)}\r
-###\r
-###\r
-###\r
-###add wave -divider vga_out\r
-###add wave -label h_sync_n sim:/testbench_motones_sim/sim_board/v_sync_n\r
-###add wave -label v_sync_n sim:/testbench_motones_sim/sim_board/h_sync_n\r
-###add wave -label r -radix hex sim:/testbench_motones_sim/sim_board/r\r
-###add wave -label g -radix hex sim:/testbench_motones_sim/sim_board/g\r
-###add wave -label b -radix hex sim:/testbench_motones_sim/sim_board/b\r
+#add wave -label plt_ce_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(5)\r
+#add wave -label plt_r_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(4)\r
+#add wave -label plt_w_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(3)\r
+#add wave -label oam_ce_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(2)\r
+#add wave -label oam_r_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(1)\r
+#add wave -label oam_w_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(0)\r
+#add wave -radix hex -label plt_addr {sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_h(12 downto 8)}\r
+#add wave -radix hex -label plt_data {sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_h(7 downto 0)}\r
+\r
+\r
+add wave -divider oam\r
+add wave -radix hex -label p_oam_addr {sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_l (7 downto 0)}\r
+add wave -radix hex -label p_oam_data {sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_l (15 downto 8)}\r
+\r
+#add wave -divider vga_out\r
+#add wave -label h_sync_n sim:/testbench_motones_sim/sim_board/v_sync_n\r
+#add wave -label v_sync_n sim:/testbench_motones_sim/sim_board/h_sync_n\r
+#add wave -label r -radix hex sim:/testbench_motones_sim/sim_board/r\r
+#add wave -label g -radix hex sim:/testbench_motones_sim/sim_board/g\r
+#add wave -label b -radix hex sim:/testbench_motones_sim/sim_board/b\r
\r
\r
view structure\r
view signals\r
#run -all\r
-run 1 us\r
+run 8 us\r
wave zoom full\r
\r
#wave zoom range 3339700 ps 5138320 ps\r
\r
-run 54 us\r
-\r
-run 77 us\r
-\r
-run 10 us\r
+run 100 us\r
\r
##wave addcursor 907923400 ps\r
\r
vlib rtl_work\r
vmap work rtl_work\r
\r
-vcom -93 -work work {../../motonesfpga_common.vhd}\r
-vcom -93 -work work {../../mem/ram.vhd}\r
-vcom -93 -work work {../../ppu/ppu_registers.vhd}\r
-vcom -93 -work work {../../clock/clock_divider.vhd}\r
-vcom -93 -work work {../../address_decoder.vhd}\r
-vcom -93 -work work {../../de1_nes.vhd}\r
-vcom -93 -work work {../../mem/chr_rom.vhd}\r
-vcom -93 -work work {../../ppu/vga_ppu.vhd}\r
-vcom -93 -work work {../../ppu/ppu.vhd}\r
-vcom -93 -work work {../../dummy-mos6502.vhd}\r
-\r
-vcom -93 -work work {../../apu/apu.vhd}\r
-#vcom -93 -work work {../../mem/prg_rom.vhd}\r
-#vcom -93 -work work {../../cpu/cpu_registers.vhd}\r
-#vcom -93 -work work {../../cpu/mos6502.vhd}\r
-#vcom -93 -work work {../../cpu/decoder.vhd}\r
-#vcom -93 -work work {../../cpu/alu.vhd}\r
-\r
-vcom -93 -work work {../../testbench_motones_sim.vhd}\r
+vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/address_decoder.vhd}\r
+vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/motonesfpga_common.vhd}\r
+vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/clock/clock_divider.vhd}\r
+vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/mem/ram.vhd}\r
+vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/apu/apu.vhd}\r
+\r
+#ppu block...\r
+vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/mem/chr_rom.vhd}\r
+vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/ppu/ppu.vhd}\r
+vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/ppu/ppu_registers.vhd}\r
+vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/ppu/vga_ppu.vhd}\r
+\r
+#cpu block...\r
+#vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/mem/prg_rom.vhd}\r
+#vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/cpu/alu.vhd}\r
+#vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/cpu/cpu_registers.vhd}\r
+#vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/cpu/decoder.vhd}\r
+#vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/cpu/mos6502.vhd}\r
+\r
+vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/dummy-mos6502.vhd}\r
+vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/de1_nes.vhd}\r
+\r
+vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/testbench_motones_sim.vhd}\r
\r
vsim -t 1ps -L lpm -L altera -L altera_mf -L sgate -L cycloneii -L rtl_work -L work testbench_motones_sim\r
\r
-##add wave sim:/testbench_motones_sim/sim_board/ppu_clk\r
\r
add wave -label rst_n sim:/testbench_motones_sim/sim_board/rst_n;\r
-add wave -label rdy sim:/testbench_motones_sim/sim_board/rdy\r
+add wave -label nmi_n sim:/testbench_motones_sim/sim_board/cpu_inst/nmi_n;\r
add wave -label r_nw sim:/testbench_motones_sim/sim_board/r_nw;\r
add wave -label cpu_clk sim:/testbench_motones_sim/sim_board/cpu_clk\r
-add wave -label nmi_n sim:/testbench_motones_sim/sim_board/nmi_n\r
add wave -label addr -radix hex sim:/testbench_motones_sim/sim_board/addr\r
add wave -label d_io -radix hex sim:/testbench_motones_sim/sim_board/d_io\r
\r
#add wave -label instruction -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/instruction\r
#add wave -label int_d_bus -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/int_d_bus\r
#add wave -label exec_cycle -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/exec_cycle\r
-\r
+#\r
#add wave -divider regs\r
#add wave -label acc -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/acc/q\r
#add wave -label status_val -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/status_register/status_val\r
\r
##add wave -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/status_reg\r
\r
-add wave -divider apu\r
-\r
-\r
-\r
add wave -divider ppu\r
-\r
+add wave -label cpu_addr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/cpu_addr\r
+add wave -label cpu_d -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/cpu_d\r
add wave -label ppu_ce_n sim:/testbench_motones_sim/sim_board/ppu_inst/ce_n\r
-add wave -label ppu_clk sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk\r
-\r
-add wave -label ppu_clk_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk_cnt\r
-\r
+#add wave -label ppu_clk sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk\r
+#add wave -label ppu_clk_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk_cnt\r
add wave -label ppu_ctl -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_ctrl\r
add wave -label ppu_mask -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_mask\r
add wave -label ppu_status -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_status\r
-\r
-\r
-add wave -label ppu_addr_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_cnt\r
+#add wave -label ppu_addr_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_cnt\r
#add wave -label ppu_addr_we_n -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_we_n\r
#add wave -label ppu_addr_in -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_in\r
#add wave -label ppu_addr_inc1 -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_inc1\r
#add wave -label ppu_addr_inc32 -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_inc32\r
-\r
add wave -label ppu_addr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr\r
add wave -label ppu_data -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_data\r
-#add wave -label ppu_scr_x -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scrl_x\r
-#add wave -label ppu_scr_y -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scrl_y\r
\r
\r
+add wave -divider ppu_scrl\r
+#add wave -label ppu_ce_n sim:/testbench_motones_sim/sim_board/ppu_inst/ce_n\r
+#add wave -label ppu_clk sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk\r
+#add wave -label ppu_scroll_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_cnt\r
+#add wave -label ppu_clk_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk_cnt\r
+#\r
+#add wave -label ppu_scroll_cnt_ce_n sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_cnt_ce_n\r
+#add wave -label ppu_scroll_x_we_n sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_x_we_n\r
+#add wave -label ppu_scroll_y_we_n sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_y_we_n\r
+add wave -label ppu_scr_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_x\r
+add wave -label ppu_scr_y -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_y\r
+\r
\r
-add wave -divider vram\r
-add wave -radix hex -label nt0_ce_n sim:/testbench_motones_sim/sim_board/nt0_ce_n\r
-add wave -radix hex -label v_addr sim:/testbench_motones_sim/sim_board/v_addr\r
-add wave -radix hex -label vram_ad sim:/testbench_motones_sim/sim_board/vram_ad\r
+add wave -divider render\r
+#add wave -label vba_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/vga_x\r
+add wave -label nes_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/nes_x\r
+#add wave -label vga_y -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/vga_y\r
+add wave -label nes_y -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/nes_y\r
\r
-add wave -label ale sim:/testbench_motones_sim/sim_board/ale\r
-add wave -label rd_n sim:/testbench_motones_sim/sim_board/rd_n\r
-add wave -label wr_n sim:/testbench_motones_sim/sim_board/wr_n\r
\r
+add wave -label cur_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/cur_x\r
+add wave -label prf_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/prf_x\r
+add wave -label cur_y -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/cur_y\r
+add wave -label prf_y -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/prf_y\r
+\r
+add wave -label disp_nt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/disp_nt\r
+add wave -label disp_attr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/disp_attr\r
+add wave -label attr_val -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/attr_val\r
\r
-add wave -divider render\r
\r
#add wave -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/nes_r \\r
#sim:/testbench_motones_sim/sim_board/ppu_inst/nes_g \\r
#sim:/testbench_motones_sim/sim_board/ppu_inst/nes_b\r
\r
-add wave -label vga_clk sim:/testbench_motones_sim/sim_board/ppu_inst/vga_clk\r
-add wave -label emu_ppu_clk sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/ppu_clk\r
-\r
add wave -label h_sync_n sim:/testbench_motones_sim/sim_board/ppu_inst/h_sync_n\r
add wave -label v_sync_n sim:/testbench_motones_sim/sim_board/ppu_inst/v_sync_n\r
\r
-add wave -label vga_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/x_inst/q\r
-add wave -label vga_y -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/y_inst/q\r
\r
-add wave -label nes_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/cur_x\r
-add wave -label nes_y -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/cur_y\r
+\r
+#add wave -divider apu\r
+#add wave -label cpu_addr sim:/testbench_motones_sim/sim_board/apu_inst/dma_start_n\r
+#add wave -label dma_next_status -radix hex sim:/testbench_motones_sim/sim_board/apu_inst/dma_next_status\r
+#add wave -label dma_status -radix hex sim:/testbench_motones_sim/sim_board/apu_inst/dma_status\r
+#add wave -label dma_cnt_ce sim:/testbench_motones_sim/sim_board/apu_inst/dma_cnt_ce\r
+#add wave -label rdy sim:/testbench_motones_sim/sim_board/apu_inst/rdy\r
+#add wave -label dma_write_we_n sim:/testbench_motones_sim/sim_board/apu_inst/dma_write_we_n\r
+#add wave -label dma_addr -radix hex sim:/testbench_motones_sim/sim_board/apu_inst/dma_addr\r
+#add wave -label dma_start_n sim:/testbench_motones_sim/sim_board/apu_inst/dma_start_n\r
+#add wave -label dma_end_n sim:/testbench_motones_sim/sim_board/apu_inst/dma_end_n\r
+\r
\r
\r
view structure\r
view signals\r
\r
-run 10 us\r
+run 8 us\r
+run 6000 us\r
wave zoom full\r
+#run 10000 us\r
\r
-run 440 us\r
-#run 65 us\r
\r
; Specify whether or not a WLF file should be deleted when the\r
; simulation ends. A value of 1 will cause the WLF file to be deleted.\r
; The default is 0 (do not delete WLF file when simulation ends).\r
-; WLFDeleteOnQuit = 1\r
+WLFDeleteOnQuit = 1\r
\r
; Automatic SDF compilation\r
; Disables automatic compilation of SDF files in flows that support it.\r
v_sync_n : out std_logic;
r : out std_logic_vector(3 downto 0);
g : out std_logic_vector(3 downto 0);
- b : out std_logic_vector(3 downto 0)
+ b : out std_logic_vector(3 downto 0);
+ nt_v_mirror : in std_logic
);
end component;
signal b : std_logic_vector(3 downto 0);
signal joypad1 : std_logic_vector(7 downto 0);
signal joypad2 : std_logic_vector(7 downto 0);
+ signal nt_v_mirror : std_logic;
constant powerup_time : time := 2 us;
constant reset_time : time := 890 ns;
dbg_nmi,
base_clk, reset_input, joypad1, joypad2,
- h_sync_n, v_sync_n, r, g, b);
+ h_sync_n, v_sync_n, r, g, b, nt_v_mirror);
--- input reset.
reset_p: process
end if;
end process;
+ --set chr rom mirror setting.
+ nt_v_mirror <= '1';
end stimulus;
LIBRARIES =\r
#-------------------------------------------------------------------------------\r
all : $(OBJECTS) $(LIBRARIES)\r
- ld65 -o regression.nes --config sample1.cfg --obj $(OBJECTS)\r
- ./dd-img.sh regression\r
- cp sample1-chr.hex ../../de1_nes/\r
-# cp sample1-prg.hex ../../de1_nes/\r
-# cp regression.nes ../../de1_nes/simulation/modelsim/rom-file.nes\r
-\r
- \r
-run : all\r
- VirtuaNES.exe regression.nes\r
-\r
+ ld65 -o sample1.nes --config sample1.cfg --obj $(OBJECTS)\r
\r
.SUFFIXES : .asm .o\r
\r
ca65 -t none $*.asm\r
\r
clean :\r
- -rm *.nes\r
+ -rm sample1.nes\r
-rm *.o\r
- -rm *.bin *.hex\r
+ -rm *.hex\r
+ -rm *.bin\r
\r
dd if=$in_file of=$out_file1 bs=16 skip=1 count=2048 2> /dev/null
dd if=$in_file of=$out_file2 bs=16 skip=2049 2> /dev/null
#4k img creation
-dd if=$in_name-prg.bin of=$in_name-prg-8k.bin bs=512 count=16
+dd if=sample1-prg.bin of=sample1-prg-4k.bin bs=512 count=8
-bin2hex $in_name-prg-8k.bin sample1-prg.hex
-bin2hex $in_name-chr.bin sample1-chr.hex
+bin2hex sample1-prg-4k.bin sample1-prg.hex
+bin2hex sample1-chr.bin sample1-chr.hex
echo "done."
.segment "STARTUP"\r
.proc Reset\r
\r
+;;; de1 env decoder bug test\r
+;;;LDA $8182, y\r
+;;;STA $2007\r
+;;;INY \r
+;;;DEX \r
+;;;;;BPL #-10\r
+;;;LDA $8182, y\r
+;;;STA $2007\r
+;;;INY \r
+;;;DEX \r
+;;;;;BPL #-10\r
+;;;LDA #$3d\r
+;;;STA $0302 ;;;>>>invalid store address!!!! @ 907,921,200 ps\r
+\r
+\r
+\r
\r
; interrupt off, initialize sp.\r
sei\r
sta $2001\r
\r
\r
- ;;bg palette\r
lda #$3f\r
sta $2006\r
lda #$00\r
sta $2006\r
\r
- lda #$11\r
- sta $2007\r
- lda #$01\r
- sta $2007\r
- lda #$03\r
- sta $2007\r
- lda #$13\r
- sta $2007\r
-\r
- lda #$0f\r
- sta $2007\r
- lda #$04\r
- sta $2007\r
- lda #$14\r
- sta $2007\r
- lda #$24\r
- sta $2007\r
-\r
- lda #$0f\r
- sta $2007\r
- lda #$08\r
- sta $2007\r
- lda #$18\r
- sta $2007\r
- lda #$28\r
- sta $2007\r
-\r
- lda #$05\r
- sta $2007\r
- lda #$0c\r
- sta $2007\r
- lda #$1c\r
- sta $2007\r
- lda #$2c\r
- sta $2007\r
-\r
- ;;sprite..\r
- lda #$00\r
- sta $2007\r
- lda #$24\r
- sta $2007\r
- lda #$1b\r
- sta $2007\r
- lda #$11\r
- sta $2007\r
-\r
- lda #$00\r
- sta $2007\r
- lda #$32\r
- sta $2007\r
- lda #$16\r
+ ;;load palette.\r
+ ldx #$00\r
+ ldy #$20\r
+copypal:\r
+ lda palettes, x\r
sta $2007\r
- lda #$20\r
- sta $2007\r
-\r
- lda #$00\r
- sta $2007\r
- lda #$26\r
- sta $2007\r
- lda #$01\r
- sta $2007\r
- lda #$31\r
- sta $2007\r
-\r
-\r
+ inx\r
+ dey\r
+ bne copypal\r
\r
- ;;name table set.\r
lda #$20\r
sta $2006\r
- lda #$06\r
+ lda #$ab\r
sta $2006\r
+ ldx #$00\r
+ ldy #$0d\r
\r
-;;0x44, 45, 45 = DEE\r
- lda #$44\r
+ ;;load name table.\r
+copymap:\r
+ lda string, x\r
sta $2007\r
- lda #$45\r
- sta $2007\r
- lda #$45\r
- sta $2007\r
-\r
+ inx\r
+ dey\r
+ bne copymap\r
\r
- lda #$20\r
- sta $2006\r
- lda #$60\r
- sta $2006\r
-\r
- lda #48\r
- sta $2007\r
- lda #49\r
- sta $2007\r
- lda #50\r
- sta $2007\r
- lda #51\r
- sta $2007\r
- lda #52\r
- sta $2007\r
- lda #53\r
- sta $2007\r
- lda #54\r
- sta $2007\r
- lda #55\r
- sta $2007\r
- lda #56\r
+ ;;scroll reg set.\r
+ lda #$00\r
+ sta $2005\r
+ sta $2005\r
\r
+;;;;----------------------\r
+ ;;load name tbl.\r
+ ldy #$00\r
+ ldx #$40 ;;name table entry cnt.\r
\r
+ lda #$20\r
+ sta $2006\r
+ lda #$c0\r
+ sta $2006\r
\r
- lda #$21\r
- sta $2006\r
- lda #$e6\r
- sta $2006\r
+nt_st:\r
+ lda nt1, y\r
+ sta $2007\r
+ iny\r
+ dex\r
+ bpl nt_st\r
\r
-;;test pattern\r
- lda #$20\r
- sta $2006\r
- lda #$20\r
- sta $2006\r
+ ;;load attr tbl.\r
+ ldy #$00\r
+ ldx #$08 ;;attribute entry cnt\r
\r
- lda #$01\r
- sta $2007\r
- lda #$02\r
- sta $2007\r
- lda #$03\r
- sta $2007\r
- lda #$04\r
- sta $2007\r
- lda #$05\r
- sta $2007\r
- lda #$06\r
- sta $2007\r
- lda #$07\r
- sta $2007\r
- lda #$08\r
- sta $2007\r
- lda #$09\r
- sta $2007\r
- lda #$0a\r
- sta $2007\r
- lda #$0b\r
- sta $2007\r
- lda #$0c\r
- sta $2007\r
- lda #$0d\r
- sta $2007\r
- lda #$0e\r
- sta $2007\r
- lda #$0f\r
- sta $2007\r
+ lda #$23\r
+ sta $2006\r
+ lda #$c8\r
+ sta $2006\r
\r
- lda #$20\r
- sta $2006\r
- lda #$40\r
- sta $2006\r
+at_st:\r
+ lda at1, y\r
+ sta $2007\r
+ iny\r
+ dex\r
+ bpl at_st\r
\r
- lda #$10\r
- sta $2007\r
- lda #$11\r
- sta $2007\r
- lda #$12\r
- sta $2007\r
- lda #$13\r
- sta $2007\r
- lda #$14\r
- sta $2007\r
- lda #$15\r
- sta $2007\r
- lda #$16\r
- sta $2007\r
- lda #$17\r
- sta $2007\r
- lda #$18\r
- sta $2007\r
- lda #$19\r
- sta $2007\r
- lda #$1a\r
- sta $2007\r
- lda #$1b\r
- sta $2007\r
- lda #$1c\r
- sta $2007\r
- lda #$1d\r
- sta $2007\r
- lda #$1e\r
- sta $2007\r
- lda #$1f\r
- sta $2007\r
+ ;;set universal bg color.\r
+ lda #$3d\r
+ sta $0302\r
+ jsr set_bg_col\r
+\r
+ ;;set scroll reg.\r
+ ;;lda #$a6\r
+ lda #$05\r
+ sta $0300\r
+ lda #00\r
+ sta $0301\r
+ jsr set_scroll\r
+\r
+ ;;set next page name table\r
+ ldy #$00\r
+ ldx #$0b\r
\r
+ lda #$24\r
+ sta $2006\r
+ lda #$c0\r
+ sta $2006\r
\r
-;;attr\r
- lda #$23\r
- sta $2006\r
- lda #$c1\r
- sta $2006\r
+nt2_st:\r
+ lda nt2, y\r
+ sta $2007\r
+ iny\r
+ dex\r
+ bpl nt2_st\r
\r
-;;--attr=11011000\r
- lda #$d8\r
- sta $2007\r
+ ;;next page attr.\r
+ lda #$27\r
+ sta $2006\r
+ lda #$d0\r
+ sta $2006\r
\r
+ lda #$e4\r
+ sta $2007\r
\r
+;;---------------------\r
;;;set sprite\r
;;sprite addr=00\r
lda #$00\r
sta $2003\r
-\r
- ;;sprite data: y=02\r
- lda #3\r
+ ;;sprite data: y=60\r
+ lda #$3c\r
sta $2004\r
;;tile=0x4d (ascii 'M')\r
lda #$4d\r
sta $2004\r
- lda #$01\r
- sta $2004\r
- ;x=100\r
- lda #$64\r
- sta $2004\r
-\r
- lda #$32\r
- sta $2004\r
- lda #$4f\r
- sta $2004\r
- lda #$01\r
- sta $2004\r
- lda #$1e\r
- sta $2004\r
-\r
- lda #60\r
- sta $2004\r
- lda #$50\r
- sta $2004\r
- lda #$01\r
- sta $2004\r
- lda #$21\r
- sta $2004\r
-\r
-\r
- lda #$3d\r
- sta $2004\r
- lda #$51\r
- sta $2004\r
- lda #$02\r
+ lda #$00\r
sta $2004\r
- lda #45\r
+ ;x=39\r
+ lda #$27\r
sta $2004\r
\r
- ;;dma test data.\r
- ldy #$00\r
- ldx #$41\r
- stx $00\r
- ldx #$00\r
-dma_set:\r
- ;;y pos\r
- txa\r
- sta $0200, y\r
- iny\r
- ;;tile index\r
- lda $00\r
- cmp #$5b\r
- bne inc_tile\r
- lda #$41\r
- sta $00\r
-inc_tile:\r
- inc $00\r
- sta $0200, y\r
- iny\r
- ;;attribute\r
- lda #$01\r
- sta $0200, y\r
- iny\r
- ;;x pos\r
- txa\r
- adc #$03\r
- tax\r
- rol\r
- sta $0200, y\r
- iny\r
- bne dma_set\r
-\r
- ;;dma start.\r
- lda #$02\r
- sta $4014\r
-\r
-\r
-\r
- ;;init scroll point.\r
- lda #$00\r
- sta $2005\r
- lda #248\r
- sta $2005\r
+;;; ;;dma test data.\r
+;;; ldy #$00\r
+;;; ldx #$41\r
+;;; stx $00\r
+;;; ldx #$00\r
+;;;dma_set:\r
+;;; ;;y pos\r
+;;; txa\r
+;;; sta $0200, y\r
+;;; iny\r
+;;; ;;tile index\r
+;;; lda $00\r
+;;; cmp #$5b\r
+;;; bne inc_tile\r
+;;; lda #$41\r
+;;; sta $00\r
+;;;inc_tile:\r
+;;; inc $00\r
+;;; sta $0200, y\r
+;;; iny\r
+;;; ;;attribute\r
+;;; lda #$01\r
+;;; sta $0200, y\r
+;;; iny\r
+;;; ;;x pos\r
+;;; txa\r
+;;; adc #$03\r
+;;; tax\r
+;;; rol\r
+;;; sta $0200, y\r
+;;; iny\r
+;;; bne dma_set\r
+;;;\r
+;;; ;;dma start.\r
+;;; lda #$02\r
+;;; sta $4014\r
\r
;;show bg...\r
lda #$1e\r
;;done...\r
;;infinite loop.\r
mainloop:\r
+\r
+ ;;read ppu status reg while displaying\r
+ ;;vram read test\r
+ ldx #$0a\r
+l1:\r
+ nop\r
+ dex\r
+ bne l1\r
+\r
+ ldx #$0a\r
+read_status:\r
+ lda $2002\r
+ dex\r
+ bne read_status\r
+\r
jmp mainloop\r
.endproc\r
\r
\r
nmi_test:\r
-; jsr set_scroll\r
-; jsr set_bg_col\r
- jsr set_dma\r
+ jsr set_scroll\r
+ jsr set_bg_col\r
\r
rti\r
\r
-set_dma:\r
- ldy #0\r
+add_nl:\r
+ clc\r
+ txa\r
+ pha\r
\r
-y_loop:\r
- lda $0200, y\r
+ lda $01\r
+ sta $2006\r
\r
- clc\r
- adc #$1\r
- sta $0200, y\r
+ lda $00\r
+ adc #$20\r
+ sta $00\r
+ sta $2006\r
\r
- iny\r
- iny\r
- iny\r
- iny\r
+ bcc no_carry\r
+ lda $01\r
+ adc #$00\r
+ sta $01\r
+ sta $2006\r
+ lda $00\r
+ sta $2006\r
+no_carry:\r
\r
- bne y_loop\r
+ pla\r
+ tax\r
+ rts\r
\r
- ;;dma start.\r
- lda #$02\r
- sta $4014\r
+set_scroll:\r
+ lda $0300\r
+ sta $2005\r
+ clc\r
+ adc #$05\r
+ sta $0300\r
+ lda $0301\r
+ sta $2005\r
+ clc\r
+ adc #04\r
+;; sta $0301\r
+ rts\r
\r
+set_bg_col:\r
+ lda #$3f\r
+ sta $2006\r
+ lda #$10\r
+ sta $2006\r
+ lda $0302\r
+ sta $2007\r
+ cmp #$30\r
+ bne bg_dec\r
+ lda #$3d\r
+ sta $0302\r
+ jmp bg_done\r
+bg_dec:\r
+ dec $0302\r
+bg_done:\r
rts\r
\r
+nt1:\r
+ .byte $41, $42, $43, $44, $45, $46, $47, $48, $49, $4a, $4b, $4c, $4d, $4e, $4f, $50\r
+ .byte $61, $62, $63, $64, $65, $66, $67, $68, $69, $6a, $6b, $6c, $6d, $6e, $6f, $70\r
+ .byte $80, $81, $82, $83, $84, $85, $86, $87, $88, $89, $8a, $8b, $8c, $8d, $8e, $8f\r
+ .byte $90, $91, $92, $93, $94, $95, $96, $97, $98, $99, $9a, $9b, $9c, $9d, $9e, $9f\r
+nt2:\r
+ .byte $6b, $6a, $69, $68, $67, $66, $65, $64, $63, $62, $61\r
+ .byte $30, $31, $32, $33, $34, $35, $36, $37, $38, $39, $3a\r
+\r
+at1:\r
+ .byte $1b, $e4, $a5, $5a\r
+ .byte $e4, $1b, $5a, $a5\r
+\r
+palettes:\r
+;;;bg palette\r
+ .byte $0f, $00, $10, $20\r
+ .byte $0f, $04, $14, $24\r
+ .byte $0f, $08, $18, $28\r
+ .byte $0f, $0c, $1c, $2c\r
+;;;spr palette\r
+ .byte $0f, $00, $10, $20\r
+ .byte $0f, $06, $16, $26\r
+ .byte $0f, $08, $18, $28\r
+ .byte $0f, $0a, $1a, $2a\r
+\r
+string:\r
+ .byte "test2!"\r
\r
;;;for DE1 internal memory constraints.\r
.segment "VECINFO_4k"\r
+memo.txt\r
+ascii-code-memo.xlsx\r
disas*\r
*.log\r
-*-32k
\ No newline at end of file
+*.*-*k\r
all : $(OBJECTS) $(LIBRARIES)\r
ld65 -o regression.nes --config linker.cfg --obj $(OBJECTS)\r
./dd-img.sh regression\r
+ cp regression.nes ../../de1_nes/simulation/modelsim/rom-file.nes\r
cp sample1-chr.hex ../../de1_nes/\r
-# cp sample1-prg.hex ../../de1_nes/\r
-# cp regression.nes ../../de1_nes/simulation/modelsim/rom-file.nes\r
+ cp sample1-prg.hex ../../de1_nes/\r
\r
\r
run : all\r
jsr print_ln\r
jsr print_ln\r
\r
-\r
-;;;;;following tests all ok\r
-; jsr single_inst_test\r
-; a2_inst_test\r
-; a3_inst_test\r
-; a4_inst_test\r
-; a5_inst_test\r
-\r
;;test start...\r
jsr addr_test\r
jsr single_inst_test\r
jsr status_test\r
jsr ppu_test\r
\r
+ jsr pg_border_test\r
+ jsr dma_test\r
+\r
.endproc\r
\r
\r
jmp mainloop\r
\r
\r
+.proc sprite_test\r
+ jsr check_ppu\r
+ lda ad_sprite_test\r
+ sta $00\r
+ lda ad_sprite_test+1\r
+ sta $01\r
+ jsr print_ln\r
+\r
+\r
+;;set sprite addr=08 (third sprite)\r
+ lda #$08\r
+ sta $2003\r
+;;set sprite data: y=20\r
+ lda #20\r
+ sta $2004\r
+;;tile=0x4d (ascii 'M')\r
+ lda #$4d\r
+ sta $2004\r
+;;set sprite attr=03 (palette 03)\r
+ lda #$03\r
+ sta $2004\r
+;;set sprite data: x=100\r
+ lda #$64\r
+ sta $2004\r
+\r
+ rts\r
+.endproc\r
+\r
+.proc simple_dma_test\r
+ jsr check_ppu\r
+ lda ad_simple_dma_test\r
+ sta $00\r
+ lda ad_simple_dma_test+1\r
+ sta $01\r
+ jsr print_ln\r
+\r
+;;set sprite addr=0C (forth sprite)\r
+;;set sprite data: y=80\r
+ lda #80\r
+ sta $020C\r
+;;tile=0x4d (ascii 'd')\r
+ lda #$64\r
+ sta $020D\r
+;;set sprite attr=03 (palette 03)\r
+ lda #$03\r
+ sta $020E\r
+;;set sprite data: x=100\r
+ lda #$64\r
+ sta $020F\r
+\r
+ ;;more sprite...\r
+ lda #90\r
+ sta $0210\r
+ lda #$64\r
+ sta $0211\r
+ lda #$03\r
+ sta $0212\r
+ lda #50\r
+ sta $0213\r
+\r
+ lda #100\r
+ sta $0220\r
+ lda #$65\r
+ sta $0221\r
+ lda #$03\r
+ sta $0222\r
+ lda #200\r
+ sta $0223\r
+\r
+ lda #30\r
+ sta $0230\r
+ lda #$44\r
+ sta $0231\r
+ lda #$03\r
+ sta $0232\r
+ lda #200\r
+ sta $0233\r
+\r
+ ;;dma start.\r
+ lda #$02\r
+ sta $4014\r
+\r
+ rts\r
+.endproc\r
+\r
+\r
+.proc ppu_test\r
+ jsr check_ppu\r
+ lda ad_ppu_test\r
+ sta $00\r
+ lda ad_ppu_test+1\r
+ sta $01\r
+ jsr print_ln\r
+\r
+ jsr sprite_test\r
+ jsr simple_dma_test\r
+ rts\r
+.endproc\r
+\r
+\r
+.proc pg_border_test\r
+ ldx #$12\r
+ ldy #$e5\r
+ \r
+ ;;a2 abs, x\r
+ ;;a2 (ind, x)\r
+ ;;a2 (ind), y\r
+ ;;a3 abs, x\r
+ ;;a3 (ind, x)\r
+ ;;a3 (ind), y\r
+ ;;a4 abs, y\r
+ ;;branch\r
+\r
+\r
+ ;;;a2 inst...\r
+ \r
+ ;;no page crossing\r
+ lda #$55\r
+ ;;0466+12=478\r
+ sta $0478\r
+\r
+ lda #$c3\r
+ clc\r
+ adc $0466, x\r
+ ;;c3+55=118\r
+ cmp #$18\r
+ beq :+\r
+ jsr test_failure\r
+:\r
+\r
+ ;;page crossing\r
+ lda #$55\r
+ ;;0466+e5=54b\r
+ sta $054b\r
+\r
+ lda #$f1\r
+ clc\r
+ adc $0466, y\r
+ ;;f1+55=146\r
+ cmp #$46\r
+ beq :+\r
+ jsr test_failure\r
+:\r
+\r
+ ;;no page crossing\r
+ lda #$55\r
+ sta $051c\r
+ ;@051c=55\r
+\r
+ lda #$1c\r
+ sta $66\r
+ lda #$05\r
+ sta $67\r
+ ;;(66)=051c\r
+ \r
+ lda #$c3\r
+ sec\r
+ ;;54+12=66\r
+ sbc ($54, x)\r
+ ;;c3-55=6e\r
+ cmp #$6e\r
+ beq :+\r
+ jsr test_failure\r
+:\r
+\r
+ ;;page crossing\r
+ lda #$55\r
+ sta $0422\r
+ ;@0422=55\r
+\r
+ lda #$22\r
+ sta $0a\r
+ lda #$04\r
+ sta $0b\r
+ ;;(0a)=0422\r
+ \r
+ lda #$c3\r
+ ;;f8+12=10a\r
+ ora ($f8, x)\r
+ ;;c3 | 55=d7\r
+ cmp #$d7\r
+ beq :+\r
+ jsr test_failure\r
+:\r
+\r
+\r
+ ;;no page crossing\r
+ lda #$55\r
+ sta $059e\r
+ ;@059e=55\r
+\r
+ lda #$8c\r
+ sta $54\r
+ lda #$05\r
+ sta $55\r
+ ;;(54)=058c\r
+ \r
+ ldy #$12\r
+ lda #$c3\r
+ ;;058c+12=59e\r
+ and ($54), y\r
+ ;;c3 & 55=41\r
+ cmp #$41\r
+ beq :+\r
+ jsr test_failure\r
+:\r
+\r
+ ;;page crossing\r
+ lda #$66\r
+ sta $0671\r
+ ;@0671=55\r
+\r
+ lda #$8c\r
+ sta $54\r
+ lda #$05\r
+ sta $55\r
+ ;;(54)=058c\r
+ \r
+ ldy #$e5\r
+ lda #$c3\r
+ ;;058c+e5=0671\r
+ eor ($54), y\r
+ ;;c3 ^ 66 = a5\r
+ cmp #$a5\r
+ beq :+\r
+ jsr test_failure\r
+:\r
+\r
+\r
+ ;;;;a3 inst...\r
+ ;;no page crossing\r
+ lda #$15\r
+ sta $0355, x\r
+ ;;0355+12=0367\r
+ ;;@0367=15\r
+\r
+ ;;c3+55=118\r
+ cmp $0367\r
+ beq :+\r
+ jsr test_failure\r
+:\r
+\r
+ ;;page crossing\r
+ lda #$67\r
+ sta $0355, y\r
+ ;;0355+e5=043a\r
+ ;;@043a=67\r
+\r
+ ;;c3+55=118\r
+ cpx $043a\r
+ bne :+\r
+ jsr test_failure\r
+:\r
+ cmp $043a\r
+ beq :+\r
+ jsr test_failure\r
+:\r
+\r
+\r
+ ;;no page crossing\r
+ lda #$ff\r
+ sta $a2\r
+ lda #$04\r
+ sta $a3\r
+ ;;(a2)=04ff\r
+\r
+ ;;90+12=a2\r
+ lda #$88\r
+ sta ($90, x)\r
+\r
+ lda $04ff\r
+ cmp #$e5\r
+ bne :+\r
+ jsr test_failure\r
+:\r
+ cmp #$88\r
+ beq :+\r
+ jsr test_failure\r
+:\r
+\r
+ ;;page crossing\r
+ lda #$ff\r
+ sta $ff\r
+ lda #$05\r
+ sta $00\r
+ ;;(ff)=05ff\r
+\r
+ ;;ed+12=ff\r
+ lda #$d1\r
+ sta ($ed, x)\r
+\r
+ lda $05ff\r
+ cmp #$e5\r
+ bne :+\r
+ jsr test_failure\r
+:\r
+ cmp #$d1\r
+ beq :+\r
+ jsr test_failure\r
+:\r
+\r
+\r
+ ;;no page crossing\r
+ lda #$f1\r
+ sta $ff\r
+ lda #$05\r
+ sta $00\r
+ ;;(ff)=05f1\r
+ \r
+ ldy #$03\r
+ lda #$a5\r
+ ;;05f1+3=05f4\r
+ sta ($ff), y\r
+\r
+\r
+ lda $05f4\r
+\r
+ cmp #$a5\r
+ beq :+\r
+ jsr test_failure\r
+:\r
+\r
+ ;;page crossing\r
+ lda #$ff\r
+ sta $ff\r
+ lda #$06\r
+ sta $00\r
+ ;;(ff)=06ff\r
+ \r
+ ldy #$12\r
+ lda #$dd\r
+ ;;06ff+12=711\r
+ sta ($ff), y\r
+\r
+\r
+ lda $0711\r
+\r
+ cmp #$dd\r
+ beq :+\r
+ jsr test_failure\r
+:\r
+\r
+\r
+ ;;a4 inst....\r
+ ;;no page crossing\r
+ lda #$55\r
+ sta $0478\r
+\r
+ ;;0466+12=478\r
+ sec\r
+ ror $0466, x\r
+\r
+ lda $0478\r
+\r
+ cmp #$aa\r
+ beq :+\r
+ jsr test_failure\r
+:\r
+\r
+ ;;page crossing\r
+ ldx #$e5\r
+ lda #$a5\r
+ sta $0476\r
+\r
+ ;;0391+e5=476\r
+ sec\r
+ rol $0391, x\r
+\r
+ lda $0476\r
+\r
+ cmp #$4b\r
+ beq :+\r
+ jsr test_failure\r
+:\r
+\r
+\r
+ ;;branch test...\r
+ jmp @br_start\r
+\r
+@br_back:\r
+ lda #$02\r
+ cmp #$03\r
+ bne @br_fwd\r
+\r
+ ;;branch across the page border.\r
+.repeat 116\r
+ .byte $00\r
+.endrepeat\r
+\r
+@br_start:\r
+ lda #$01\r
+ cmp #$01\r
+ beq @br_back\r
+\r
+@br_fwd:\r
+\r
+\r
+ jsr check_ppu\r
+ lda ad_pg_border_test\r
+ sta $00\r
+ lda ad_pg_border_test+1\r
+ sta $01\r
+ jsr print_ln\r
+\r
+ rts\r
+.endproc\r
+\r
+.proc dma_test\r
+ lda full_dma_test\r
+ bne :+\r
+ rts\r
+:\r
+\r
+ ;;dma test data.\r
+ ldy #$00\r
+ ldx #$41\r
+ stx $00\r
+ ldx #$00\r
+dma_set:\r
+ ;;y pos\r
+ txa\r
+ sta $0200, y\r
+ iny\r
+ ;;tile index\r
+ lda $00\r
+ cmp #$5b\r
+ bne inc_tile\r
+ lda #$41\r
+ sta $00\r
+inc_tile:\r
+ inc $00\r
+ sta $0200, y\r
+ iny\r
+ ;;attribute\r
+ lda #$03\r
+ sta $0200, y\r
+ iny\r
+ ;;x pos\r
+ txa\r
+ adc #$03\r
+ tax\r
+ rol\r
+ sta $0200, y\r
+ iny\r
+ bne dma_set\r
+\r
+ ;;dma start.\r
+ lda #$02\r
+ sta $4014\r
+\r
+ jsr check_ppu\r
+ lda ad_dma_test\r
+ sta $00\r
+ lda ad_dma_test+1\r
+ sta $01\r
+ jsr print_ln\r
+\r
+ rts\r
+.endproc\r
+\r
+\r
+.proc update_dma\r
+ lda full_dma_test\r
+ bne :+\r
+ rts\r
+:\r
+\r
+ ldy #0\r
+\r
+y_loop:\r
+ iny\r
+ iny\r
+ iny\r
+\r
+ lda $0200, y\r
+ clc\r
+ adc #$1\r
+ sta $0200, y\r
+\r
+ iny\r
+\r
+ bne y_loop\r
+\r
+ ;;dma start.\r
+ lda #$02\r
+ sta $4014\r
+\r
+ rts\r
+.endproc\r
+\r
nmi_test:\r
jsr update_counter\r
jsr update_scroll\r
+ jsr update_dma\r
\r
rti\r
\r
\r
@cnt_done:\r
\r
+ lda #50\r
+ sta $2005\r
+ lda #200\r
+ sta $2005\r
rts\r
.endproc\r
\r
bne :+\r
ldx #0\r
:\r
- ldx #$00\r
+ ldx #80\r
stx $2005\r
stx scroll_y\r
\r
rts\r
.endproc\r
\r
-.proc ppu_test\r
- jsr check_ppu\r
- lda ad_ppu_test\r
- sta $00\r
- lda ad_ppu_test+1\r
- sta $01\r
- jsr print_ln\r
-\r
- rts\r
-.endproc\r
-\r
-\r
;;a5 instructions:\r
;;bcc brk php\r
;;bcs bvc pla\r
.endproc\r
\r
\r
+;;;read only global datas\r
\r
;;;;string datas\r
ad_start_msg:\r
.byte "status test..."\r
.byte $00\r
\r
+\r
+ad_pg_border_test:\r
+ .addr :+\r
+:\r
+ .byte "page border crossing test..."\r
+ .byte $00\r
+\r
+ad_dma_test:\r
+ .addr :+\r
+:\r
+ .byte "dma test..."\r
+ .byte $00\r
+\r
+ad_sprite_test:\r
+ .addr :+\r
+:\r
+ .byte "sprite test..."\r
+ .byte $00\r
+\r
+ad_simple_dma_test:\r
+ .addr :+\r
+:\r
+ .byte "simple sprite test (dma)..."\r
+ .byte $00\r
+\r
ad_ppu_test:\r
.addr :+\r
:\r
.byte "single byte inst test..."\r
.byte $00\r
\r
-;;;read only global datas\r
-use_ppu:\r
- .byte $01\r
-\r
\r
;;;;address fixed test code..\r
.segment "SEG_5K"\r
rts\r
.endproc\r
\r
+;;ppu test flag.\r
+use_ppu:\r
+ .byte $01\r
+\r
+full_dma_test:\r
+ .byte $01\r
\r
;;;;r/w global variables.\r
.segment "BSS"\r
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