sim work started.

diff --git a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
index 53ffa05..4aa1b1a 100644 (file)
--- a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
+++ b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
@@ -24,9 +24,6 @@ vcom -93 -work work {../../testbench_motones_sim.vhd}
 \r
 vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev -L rtl_work -L work -voptargs="+acc"  testbench_motones_sim\r
 \r
-##script custom part...\r
-\r
-#run 450ms\r
 \r
 #################################### General.... ###########################################\r
 \r
@@ -115,47 +112,47 @@ add wave -divider render
 add wave -label nes_x       sim:/testbench_motones_sim/sim_board/render_inst/reg_nes_x;\r
 add wave -label nes_y       sim:/testbench_motones_sim/sim_board/render_inst/reg_nes_y;\r
 \r
-\r
-add wave -divider bg\r
-#add wave -label wr_rnd_en  sim:/testbench_motones_sim/sim_board/wr_rnd_en;\r
-add wave -label reg_v_cur_state sim:/testbench_motones_sim/sim_board/render_inst/reg_v_cur_state;\r
-#add wave -label prf_x       sim:/testbench_motones_sim/sim_board/render_inst/reg_prf_x;\r
-#add wave -label prf_y       sim:/testbench_motones_sim/sim_board/render_inst/reg_prf_y;\r
-\r
-add wave -label disp_nt -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_disp_nt;\r
-add wave -label disp_attr   -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_disp_attr;\r
-add wave -label sft_ptn_l -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_sft_ptn_l;\r
-add wave -label sft_ptn_h -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_sft_ptn_h;\r
-\r
-add wave -divider sprite\r
-add wave -label reg_s_oam_cur_state sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_cur_state;\r
-add wave -label reg_s_oam_ce_n  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_ce_n;\r
-add wave -label reg_s_oam_rd_n  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_rd_n;\r
-add wave -label reg_s_oam_wr_n  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_wr_n;\r
-add wave -label reg_s_oam_addr -radix hex  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_addr;\r
-add wave -label reg_s_oam_data -radix hex  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_data;\r
-\r
-#add wave -label reg_s_oam_cpy_cnt   sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_cpy_cnt;\r
-#add wave -label reg_p_oam_cpy_cnt   sim:/testbench_motones_sim/sim_board/render_inst/reg_p_oam_cpy_cnt;\r
-#add wave -label reg_spr_eval_cnt    sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_eval_cnt;\r
-\r
-add wave -label wr_spr_ce_n  sim:/testbench_motones_sim/sim_board/wr_spr_ce_n;\r
-add wave -label wr_spr_rd_n  sim:/testbench_motones_sim/sim_board/wr_spr_rd_n;\r
-add wave -label wr_spr_wr_n  sim:/testbench_motones_sim/sim_board/wr_spr_wr_n;\r
-add wave -label wr_spr_addr -radix hex  sim:/testbench_motones_sim/sim_board/wr_spr_addr;\r
-add wave -label wr_spr_data -radix hex  sim:/testbench_motones_sim/sim_board/wr_spr_data;\r
-\r
-add wave -label reg_spr_y_tmp -radix hex    sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_y_tmp;\r
-add wave -label reg_spr_tile_tmp -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_tile_tmp;\r
-add wave -label reg_spr_attr -radix hex     sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_attr;\r
-add wave -label reg_spr_x -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_x;\r
-add wave -label reg_spr_ptn_sft_start -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_ptn_sft_start;\r
-add wave -label reg_spr_ptn_l -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_ptn_l;\r
-add wave -label reg_spr_ptn_h -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_ptn_h;\r
-\r
-add wave -divider palette\r
-add wave -label plt_addr -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_plt_addr;\r
-add wave -label plt_data -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_plt_data;\r
+#\r
+#add wave -divider bg\r
+##add wave -label wr_rnd_en  sim:/testbench_motones_sim/sim_board/wr_rnd_en;\r
+#add wave -label reg_v_cur_state sim:/testbench_motones_sim/sim_board/render_inst/reg_v_cur_state;\r
+##add wave -label prf_x       sim:/testbench_motones_sim/sim_board/render_inst/reg_prf_x;\r
+##add wave -label prf_y       sim:/testbench_motones_sim/sim_board/render_inst/reg_prf_y;\r
+#\r
+#add wave -label disp_nt -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_disp_nt;\r
+#add wave -label disp_attr   -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_disp_attr;\r
+#add wave -label sft_ptn_l -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_sft_ptn_l;\r
+#add wave -label sft_ptn_h -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_sft_ptn_h;\r
+#\r
+#add wave -divider sprite\r
+#add wave -label reg_s_oam_cur_state sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_cur_state;\r
+#add wave -label reg_s_oam_ce_n  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_ce_n;\r
+#add wave -label reg_s_oam_rd_n  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_rd_n;\r
+#add wave -label reg_s_oam_wr_n  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_wr_n;\r
+#add wave -label reg_s_oam_addr -radix hex  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_addr;\r
+#add wave -label reg_s_oam_data -radix hex  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_data;\r
+#\r
+##add wave -label reg_s_oam_cpy_cnt   sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_cpy_cnt;\r
+##add wave -label reg_p_oam_cpy_cnt   sim:/testbench_motones_sim/sim_board/render_inst/reg_p_oam_cpy_cnt;\r
+##add wave -label reg_spr_eval_cnt    sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_eval_cnt;\r
+#\r
+#add wave -label wr_spr_ce_n  sim:/testbench_motones_sim/sim_board/wr_spr_ce_n;\r
+#add wave -label wr_spr_rd_n  sim:/testbench_motones_sim/sim_board/wr_spr_rd_n;\r
+#add wave -label wr_spr_wr_n  sim:/testbench_motones_sim/sim_board/wr_spr_wr_n;\r
+#add wave -label wr_spr_addr -radix hex  sim:/testbench_motones_sim/sim_board/wr_spr_addr;\r
+#add wave -label wr_spr_data -radix hex  sim:/testbench_motones_sim/sim_board/wr_spr_data;\r
+#\r
+#add wave -label reg_spr_y_tmp -radix hex    sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_y_tmp;\r
+#add wave -label reg_spr_tile_tmp -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_tile_tmp;\r
+#add wave -label reg_spr_attr -radix hex     sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_attr;\r
+#add wave -label reg_spr_x -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_x;\r
+#add wave -label reg_spr_ptn_sft_start -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_ptn_sft_start;\r
+#add wave -label reg_spr_ptn_l -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_ptn_l;\r
+#add wave -label reg_spr_ptn_h -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_ptn_h;\r
+#\r
+#add wave -divider palette\r
+#add wave -label plt_addr -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_plt_addr;\r
+#add wave -label plt_data -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_plt_data;\r
 \r
 \r
 add wave -divider vga\r
@@ -170,41 +167,6 @@ add wave -label b -radix hex sim:/testbench_motones_sim/sim_board/po_b;
 view structure\r
 view signals\r
 \r
-run 25 us\r
+run 15 us\r
 wave zoom full\r
 \r
-#palette\r
-#run 70 us\r
-#\r
-##vram\r
-#run 2000 us\r
-#\r
-##sprite\r
-#run 550 us\r
-\r
-#until nmi 0x08 end.\r
-run 230ms\r
-\r
-mem save -o D:/daisuke/nes/repo/motonesfpga/doc/dbg/sim-dump/after-08-sim-ram.mem -f mti -data hex -addr hex -wordsperline 16 /testbench_motones_sim/sim_board/cpu_ram_inst/work_ram\r
-mem save -o D:/daisuke/nes/repo/motonesfpga/doc/dbg/sim-dump/after-08-sim-vram.mem -f mti -data hex -addr hex -wordsperline 16 /testbench_motones_sim/sim_board/vram_nt0_inst/work_ram\r
-\r
-run 16.8ms\r
-mem save -o D:/daisuke/nes/repo/motonesfpga/doc/dbg/sim-dump/after-09-sim-ram.mem -f mti -data hex -addr hex -wordsperline 16 /testbench_motones_sim/sim_board/cpu_ram_inst/work_ram\r
-mem save -o D:/daisuke/nes/repo/motonesfpga/doc/dbg/sim-dump/after-09-sim-vram.mem -f mti -data hex -addr hex -wordsperline 16 /testbench_motones_sim/sim_board/vram_nt0_inst/work_ram\r
-\r
-run 253ms\r
-##currently @500ms. nmi 18 is done.\r
-mem save -o D:/daisuke/nes/repo/motonesfpga/doc/dbg/sim-dump/after-18-sim-ram.mem -f mti -data hex -addr hex -wordsperline 16 /testbench_motones_sim/sim_board/cpu_ram_inst/work_ram\r
-mem save -o D:/daisuke/nes/repo/motonesfpga/doc/dbg/sim-dump/after-18-sim-vram.mem -f mti -data hex -addr hex -wordsperline 16 /testbench_motones_sim/sim_board/vram_nt0_inst/work_ram\r
-\r
-run 16.8ms\r
-mem save -o D:/daisuke/nes/repo/motonesfpga/doc/dbg/sim-dump/after-19-sim-ram.mem -f mti -data hex -addr hex -wordsperline 16 /testbench_motones_sim/sim_board/cpu_ram_inst/work_ram\r
-mem save -o D:/daisuke/nes/repo/motonesfpga/doc/dbg/sim-dump/after-19-sim-vram.mem -f mti -data hex -addr hex -wordsperline 16 /testbench_motones_sim/sim_board/vram_nt0_inst/work_ram\r
-\r
-run 16.8ms\r
-mem save -o D:/daisuke/nes/repo/motonesfpga/doc/dbg/sim-dump/after-1a-sim-ram.mem -f mti -data hex -addr hex -wordsperline 16 /testbench_motones_sim/sim_board/cpu_ram_inst/work_ram\r
-mem save -o D:/daisuke/nes/repo/motonesfpga/doc/dbg/sim-dump/after-1a-sim-vram.mem -f mti -data hex -addr hex -wordsperline 16 /testbench_motones_sim/sim_board/vram_nt0_inst/work_ram\r
-\r
-run 16.8ms\r
-mem save -o D:/daisuke/nes/repo/motonesfpga/doc/dbg/sim-dump/after-1b-sim-ram.mem -f mti -data hex -addr hex -wordsperline 16 /testbench_motones_sim/sim_board/cpu_ram_inst/work_ram\r
-mem save -o D:/daisuke/nes/repo/motonesfpga/doc/dbg/sim-dump/after-1b-sim-vram.mem -f mti -data hex -addr hex -wordsperline 16 /testbench_motones_sim/sim_board/vram_nt0_inst/work_ram\r