vram latch bug fixed...

diff --git a/de1_nes/ppu/ppu.vhd b/de1_nes/ppu/ppu.vhd
index ff94107..684d82f 100644 (file)
--- a/de1_nes/ppu/ppu.vhd
+++ b/de1_nes/ppu/ppu.vhd
@@ -337,14 +337,14 @@ begin
     ale <= '1' when ce_n = '0' and cpu_addr = PPUADDR and r_nw = '0' else
            '1' when ppu_addr_upd_n = '0' else
            '0' when ce_n = '0' and cpu_addr = PPUDATA and r_nw = '0' else
-           'Z';
+           '0';
     wr_n <= '0' when ce_n = '0' and cpu_addr = PPUDATA and r_nw = '0' else
             '1' when ppu_addr_upd_n = '0' else
             '1' when ce_n = '0' and cpu_addr = PPUADDR and r_nw = '0' else
-            'Z';
+            '1';
     rd_n <= '1' when ce_n = '0' and cpu_addr = PPUADDR and r_nw = '0' else
             '1' when ppu_addr_upd_n = '0' else
-            'Z';
+            '1';
     vram_a <= ppu_addr(13 downto 8) when ce_n = '0' and cpu_addr = PPUADDR and r_nw = '0' else
               ppu_addr(13 downto 8) when ppu_addr_upd_n = '0' else
               (others => 'Z');

diff --git a/de1_nes/ppu/ppu_registers.vhd b/de1_nes/ppu/ppu_registers.vhd
index 661435d..6764f16 100644 (file)
--- a/de1_nes/ppu/ppu_registers.vhd
+++ b/de1_nes/ppu/ppu_registers.vhd
@@ -112,9 +112,8 @@ begin
     d_in <= vram_a & vram_ad;\r
     we_n <= '0' when ale = '1' else\r
             '1';
---    oe_n <= '0' when ale = '0' else\r
---            '1';\r
-    oe_n <= '0';\r
+    oe_n <= '0' when ale = '0' else\r
+            '1';\r
     out_reg_inst : d_flip_flop generic map (14)\r
             port map (clk, rst_n, '1', we_n, d_in, q_out);\r
     out_tss_inst : tri_state_buffer generic map (14)\r

diff --git a/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do b/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do
index 2eca828..7d43e6d 100644 (file)
--- a/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do
+++ b/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do
@@ -57,16 +57,16 @@ add wave -label wr_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(2)
 \r
 add wave  -radix hex -label vram_a sim:/testbench_motones_sim/sim_board/dbg_vram_a\r
 add wave  -radix hex -label vram_ad sim:/testbench_motones_sim/sim_board/dbg_vram_ad\r
-#add wave  -radix hex -label v_addr_h  sim:/testbench_motones_sim/sim_board/dbg_sp\r
+#add wave  -radix hex -label v_addr_h  {sim:/testbench_motones_sim/sim_board/dbg_sp (5 downto 0)}\r
 #add wave  -radix hex -label v_addr_l  sim:/testbench_motones_sim/sim_board/dbg_x\r
 add wave -label emu_ppu_clk     sim:/testbench_motones_sim/sim_board/dbg_emu_ppu_clk\r
-add wave -label dbg_vl_we_n     sim:/testbench_motones_sim/sim_board/dbg_sp(6)\r
+#add wave -label dbg_vl_we_n     sim:/testbench_motones_sim/sim_board/dbg_sp(6)\r
 add wave  -radix hex -label v_addr  {sim:/testbench_motones_sim/sim_board/dbg_sp (5 downto 0) & \r
                                      sim:/testbench_motones_sim/sim_board/dbg_x (7 downto 0)}\r
 \r
-add wave -label ppu_data_we_n   sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(2)\r
-add wave -label ppu_addr_inc_n  sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(1)\r
-add wave -label ppu_addr_upd_n  sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(0)\r
+#add wave -label ppu_data_we_n   sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(2)\r
+#add wave -label ppu_addr_inc_n  sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(1)\r
+#add wave -label ppu_addr_upd_n  sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(0)\r
 \r
 #add wave -divider vga_pos\r
 #add wave -label emu_ppu_clk     sim:/testbench_motones_sim/sim_board/dbg_emu_ppu_clk\r