inx/dey supported.

diff --git a/simulation/cpu/cpu_registers.vhd b/simulation/cpu/cpu_registers.vhd
index 8f1a57b..3141735 100644 (file)
--- a/simulation/cpu/cpu_registers.vhd
+++ b/simulation/cpu/cpu_registers.vhd
@@ -450,10 +450,6 @@ begin
                 val <= int_dbus;
             elsif (load_bus_nz_n = '0') then
                 ---other case: n/z data must be interpreted.
-                tmp := val;
-                val (6 downto 2) <= tmp (6 downto 2);
-                val (0) <= tmp (0);
-
                 --n bit.
                 val (7) <= int_dbus(7);
                 --z bit.
@@ -596,8 +592,12 @@ entity index_reg is
             d_we_n      : in std_logic;
             d_oe_n      : in std_logic;
             ea_oe_n     : in std_logic;
+            inc_n       : in std_logic;
+            dec_n       : in std_logic;
             int_dbus    : inout std_logic_vector (dsize - 1 downto 0);
-            ea_bus      : out std_logic_vector (dsize - 1 downto 0)
+            ea_bus      : out std_logic_vector (dsize - 1 downto 0);
+            n           : out std_logic;
+            z           : out std_logic
         );
 end index_reg;
 
@@ -615,7 +615,12 @@ component dff
         );
 end component;
 
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+signal we_n : std_logic;
 signal q : std_logic_vector (dsize - 1 downto 0);
+signal d : std_logic_vector (dsize - 1 downto 0);
 
 begin
     int_dbus <= q when d_oe_n = '0' else
@@ -623,9 +628,38 @@ begin
     ea_bus <= q when ea_oe_n = '0' else
         (others => 'Z');
 
+    --for inx/iny/dex/dey instructions...
+    inc_dec_p : process (clk, int_dbus, inc_n, dec_n)
+    variable inc_work : std_logic_vector (dsize downto 0);
+    variable dec_work : std_logic_vector (dsize downto 0);
+    begin
+        inc_work := ('0' & q) + 1;
+        dec_work := ('0' & q) - 1;
+        if inc_n = '0' then
+            d <= inc_work(dsize - 1 downto 0);
+            z <= not (inc_work(7) or inc_work(6) or 
+                    inc_work(5) or inc_work(4) or inc_work(3) or 
+                    inc_work(2) or inc_work(1) or inc_work(0));
+            n <= inc_work(dsize);
+        elsif dec_n = '0' then
+            d <= dec_work(dsize - 1 downto 0);
+            z <= not (dec_work(7) or dec_work(6) or 
+                dec_work(5) or dec_work(4) or dec_work(3) or 
+                dec_work(2) or dec_work(1) or dec_work(0)); 
+            n <= dec_work(dsize); 
+        else
+            d <= int_dbus;
+            z <= 'Z';
+            n <= 'Z';
+        end if;
+
+    end process;
+
     --read from i/o to cpu
+    we_n <= d_we_n and inc_n and dec_n;
     dff_inst : dff generic map (dsize) 
-                    port map(clk, d_we_n, '0', int_dbus, q);
+                    port map(clk, we_n, '0', d, q);
+
 end rtl;
 
 

diff --git a/simulation/cpu/decoder.vhd b/simulation/cpu/decoder.vhd
index 88b36dd..5858e07 100644 (file)
--- a/simulation/cpu/decoder.vhd
+++ b/simulation/cpu/decoder.vhd
@@ -43,9 +43,13 @@ entity decoder is
             x_we_n          : out std_logic;
             x_oe_n          : out std_logic;
             x_ea_oe_n       : out std_logic;
+            x_inc_n         : out std_logic;
+            x_dec_n         : out std_logic;
             y_we_n          : out std_logic;
             y_oe_n          : out std_logic;
             y_ea_oe_n       : out std_logic;
+            y_inc_n         : out std_logic;
+            y_dec_n         : out std_logic;
             ea_calc_n       : out std_logic;
             ea_zp_n         : out std_logic;
             ea_pg_next_n    : out std_logic;
@@ -205,9 +209,14 @@ begin
     acc_d_oe_n  <= '1';
     stat_bus_nz_n <= '1';
     stat_set_flg_n <= '1';
+    stat_alu_we_n <= '1';
     x_ea_oe_n <= '1';
     ea_calc_n <= '1';
     ea_pg_next_n <= '1';
+    x_inc_n <= '1';
+    x_dec_n <= '1';
+    y_inc_n <= '1';
+    y_dec_n <= '1';
 end;
 
 ---common routine for single byte instruction.
@@ -427,9 +436,21 @@ end  procedure;
 
                 elsif instruction = conv_std_logic_vector(16#88#, dsize) then
                     d_print("dey");
+                    y_dec_n <= '0';
+                    --set nz bit.
+                    stat_alu_we_n <= '0';
+                    stat_dec_oe_n <= '1';
+                    status_reg <= "10000010";
+                    single_inst;
 
                 elsif instruction = conv_std_logic_vector(16#e8#, dsize) then
                     d_print("inx");
+                    x_inc_n <= '0';
+                    --set nz bit.
+                    stat_alu_we_n <= '0';
+                    stat_dec_oe_n <= '1';
+                    status_reg <= "10000010";
+                    single_inst;
 
                 elsif instruction = conv_std_logic_vector(16#c8#, dsize) then
                     d_print("iny");
@@ -1232,6 +1253,10 @@ end  procedure;
                 x_oe_n <= '1';
                 y_we_n <= '1';
                 y_oe_n <= '1';
+                x_inc_n <= '1';
+                x_dec_n <= '1';
+                y_inc_n <= '1';
+                y_dec_n <= '1';
 
                 stat_dec_oe_n <= '1';
                 stat_bus_oe_n <= '1';

diff --git a/simulation/cpu/mos6502.vhd b/simulation/cpu/mos6502.vhd
index d82a57e..442faa3 100644 (file)
--- a/simulation/cpu/mos6502.vhd
+++ b/simulation/cpu/mos6502.vhd
@@ -81,9 +81,13 @@ architecture rtl of mos6502 is
                 x_we_n          : out std_logic;
                 x_oe_n          : out std_logic;
                 x_ea_oe_n       : out std_logic;
+                x_inc_n         : out std_logic;
+                x_dec_n         : out std_logic;
                 y_we_n          : out std_logic;
                 y_oe_n          : out std_logic;
                 y_ea_oe_n       : out std_logic;
+                y_inc_n         : out std_logic;
+                y_dec_n         : out std_logic;
                 ea_calc_n       : out std_logic;
                 ea_zp_n         : out std_logic;
                 ea_pg_next_n    : out std_logic;
@@ -218,8 +222,12 @@ architecture rtl of mos6502 is
             d_we_n      : in std_logic;
             d_oe_n      : in std_logic;
             ea_oe_n     : in std_logic;
+            inc_n       : in std_logic;
+            dec_n       : in std_logic;
             int_dbus    : inout std_logic_vector (dsize - 1 downto 0);
-            ea_bus      : out std_logic_vector (dsize - 1 downto 0)
+            ea_bus      : out std_logic_vector (dsize - 1 downto 0);
+            n           : out std_logic;
+            z           : out std_logic
         );
     end component;
 
@@ -277,9 +285,13 @@ architecture rtl of mos6502 is
 
     signal x_we_n : std_logic;
     signal x_oe_n : std_logic;
+    signal x_inc_n : std_logic;
+    signal x_dec_n : std_logic;
 
     signal y_we_n : std_logic;
     signal y_oe_n : std_logic;
+    signal y_inc_n : std_logic;
+    signal y_dec_n : std_logic;
 
     signal ea_base_l : std_logic_vector(dsize - 1 downto 0);
     signal ea_base_h : std_logic_vector(dsize - 1 downto 0);
@@ -359,9 +371,13 @@ begin
                     x_we_n, 
                     x_oe_n, 
                     x_ea_oe_n,
+                    x_inc_n,
+                    x_dec_n,
                     y_we_n, 
                     y_oe_n, 
                     y_ea_oe_n,
+                    y_inc_n,
+                    y_dec_n,
                     ea_calc_n,
                     ea_zp_n,
                     ea_pg_next_n,
@@ -423,10 +439,14 @@ begin
 
     --x/y output pin is connected to effective address calcurator
     x_reg : index_reg generic map (dsize) 
-            port map(trigger_clk, x_we_n, x_oe_n, x_ea_oe_n, internal_dbus, ea_index);
+            port map(trigger_clk, x_we_n, x_oe_n, x_ea_oe_n, 
+                    x_inc_n, x_dec_n, internal_dbus, ea_index, 
+                    alu_n, alu_z);
 
     y_reg : index_reg generic map (dsize) 
-            port map(trigger_clk, y_we_n, y_oe_n, y_ea_oe_n, internal_dbus, ea_index);
+            port map(trigger_clk, y_we_n, y_oe_n, y_ea_oe_n, 
+                    y_inc_n, y_dec_n, internal_dbus, ea_index,
+                    alu_n, alu_z);
 
     acc_reg : accumulator generic map (dsize) 
             port map(trigger_clk,