plt ram access added

diff --git a/de1_nes/ppu/ppu.vhd b/de1_nes/ppu/ppu.vhd
index d404822..f789309 100644 (file)
--- a/de1_nes/ppu/ppu.vhd
+++ b/de1_nes/ppu/ppu.vhd
@@ -101,6 +101,8 @@ component vga_ppu_render
             plt_bus_ce_n    : in std_logic;
             plt_addr_in     : in std_logic_vector (4 downto 0);
             plt_data_in     : in std_logic_vector (7 downto 0);
+            plt_data_out    : out std_logic_vector (7 downto 0);
+
             oam_bus_ce_n    : in std_logic;
             oam_addr_in     : in std_logic_vector (7 downto 0);
             oam_data_in     : in std_logic_vector (7 downto 0);
@@ -205,6 +207,8 @@ signal rnd_rd_n, rnd_wr_n, rnd_ale : std_logic;
 signal rnd_vram_ad  : std_logic_vector (7 downto 0);
 signal rnd_vram_a   : std_logic_vector (13 downto 8);
 
+signal rnd_plt_data_out    : std_logic_vector (7 downto 0);
+
 signal v_bus_busy_n     : std_logic;
 
 begin
@@ -331,21 +335,28 @@ begin
     ale <= '1' when ce_n = '0' and cpu_addr = PPUADDR and r_nw = '0' else
            '1' when ppu_addr_upd_n = '0' else
            '0' when ce_n = '0' and cpu_addr = PPUDATA and r_nw = '0' else
-           '0';
+           rnd_ale;
     wr_n <= '0' when ce_n = '0' and cpu_addr = PPUDATA and r_nw = '0' else
             '1' when ppu_addr_upd_n = '0' else
             '1' when ce_n = '0' and cpu_addr = PPUADDR and r_nw = '0' else
-            '1';
+            rnd_wr_n;
     rd_n <= '1' when ce_n = '0' and cpu_addr = PPUADDR and r_nw = '0' else
             '1' when ppu_addr_upd_n = '0' else
-            '1';
+            rnd_rd_n;
     vram_a <= ppu_addr(13 downto 8) when ce_n = '0' and cpu_addr = PPUADDR and r_nw = '0' else
               ppu_addr(13 downto 8) when ppu_addr_upd_n = '0' else
-              (others => 'Z');
+              rnd_vram_a;
     vram_ad <= cpu_d when ce_n = '0' and cpu_addr = PPUADDR and r_nw = '0' else
                ppu_addr(7 downto 0) when ppu_addr_upd_n = '0' else
                cpu_d when ce_n = '0' and cpu_addr = PPUDATA and r_nw = '0' else
-               (others => 'Z');
+               rnd_vram_ad;
+
+
+    -----------------------------
+    --palette ram access..
+    -----------------------------
+    plt_bus_ce_n <= '0' when ce_n = '0' and cpu_addr = PPUDATA and ppu_addr(13 downto 8) = "111111" else
+                    '1';
 
     -----------------------------
     --cpu nmi generation...
@@ -391,7 +402,7 @@ begin
             rnd_rd_n, rnd_wr_n, rnd_ale, rnd_vram_ad, rnd_vram_a,
             h_sync_n, v_sync_n, r, g, b, 
             ppu_ctrl, ppu_mask, rdr_ppu_stat, ppu_scroll_x, ppu_scroll_y,
-            r_nw, plt_bus_ce_n, ppu_addr(4 downto 0), cpu_d, 
+            r_nw, plt_bus_ce_n, ppu_addr(4 downto 0), cpu_d, rnd_plt_data_out,
             oam_bus_ce_n, oam_addr, cpu_d, v_bus_busy_n);
 
 end rtl;

diff --git a/de1_nes/ppu/vga_ppu.vhd b/de1_nes/ppu/vga_ppu.vhd
index 713d850..dd5b8ae 100644 (file)
--- a/de1_nes/ppu/vga_ppu.vhd
+++ b/de1_nes/ppu/vga_ppu.vhd
@@ -60,6 +60,8 @@ entity vga_ppu_render is
             plt_bus_ce_n    : in std_logic;\r
             plt_addr_in     : in std_logic_vector (4 downto 0);\r
             plt_data_in     : in std_logic_vector (7 downto 0);\r
+            plt_data_out    : out std_logic_vector (7 downto 0);\r
+\r
             oam_bus_ce_n    : in std_logic;\r
             oam_addr_in     : in std_logic_vector (7 downto 0);\r
             oam_data_in     : in std_logic_vector (7 downto 0);\r
@@ -142,15 +144,6 @@ component palette_ram
     );\r
 end component;\r
 \r
-component ram_ctrl\r
-    generic (wr_en_timing : integer);\r
-    port (  \r
-            clk              : in std_logic;\r
-            ce_n, oe_n, we_n : in std_logic;\r
-            sync_ce_n        : out std_logic\r
-        );\r
-end component;\r
-\r
 --------- VGA screen constant -----------\r
 constant VGA_W          : integer := 640;\r
 constant VGA_H          : integer := 480;\r
@@ -467,81 +460,19 @@ begin
     --nes_y <= vga_y(8 downto 0);\r
 \r
 \r
---    -----------------------------------------\r
---    ---vram access signals\r
---    -----------------------------------------\r
---    reset_p : process (rst_n, emu_ppu_clk)\r
---    begin\r
---        if (rst_n = '0') then\r
---            io_cnt_rst_n <= '0';\r
---        else\r
---            if (falling_edge(emu_ppu_clk)) then\r
---                if (nes_x >= conv_std_logic_vector(VGA_W_MAX / 2 - 1, X_SIZE)) then io_cnt_rst_n <= '0';\r
---                else io_cnt_rst_n <= '1';\r
---                end if; \r
---            end if;\r
---        end if;\r
---    end process;\r
---\r
---    io_cnt_inst : counter_register generic map (1, 1)\r
---            port map (emu_ppu_clk, io_cnt_rst_n, '0', '1', (others => '0'), io_cnt);\r
---\r
---    ale <= \r
---            not io_cnt(0) when (\r
---                ((ppu_mask(PPUSBG) = '1' or ppu_mask(PPUSSP) = '1') and\r
---                (nes_y < conv_std_logic_vector(VSCAN, X_SIZE) or \r
---                nes_y = conv_std_logic_vector(VSCAN_NEXT_START, X_SIZE)))) else\r
---            'Z';\r
---    rd_n <= \r
---            not io_cnt(0) when (\r
---                ((ppu_mask(PPUSBG) = '1' or ppu_mask(PPUSSP) = '1') and\r
---                (nes_y < conv_std_logic_vector(VSCAN, X_SIZE) or \r
---                nes_y = conv_std_logic_vector(VSCAN_NEXT_START, X_SIZE)))) else\r
---            'Z';\r
---    wr_n <= \r
---            '1' when (\r
---                ((ppu_mask(PPUSBG) = '1' or ppu_mask(PPUSSP) = '1') and\r
---                (nes_y < conv_std_logic_vector(VSCAN, X_SIZE) or \r
---                nes_y = conv_std_logic_vector(VSCAN_NEXT_START, X_SIZE)))) else\r
---            'Z';\r
---    al_oe_n <= \r
---            io_cnt(0) when (\r
---                ((ppu_mask(PPUSBG) = '1' or ppu_mask(PPUSSP) = '1') and\r
---                (nes_y < conv_std_logic_vector(VSCAN, X_SIZE) or \r
---                nes_y = conv_std_logic_vector(VSCAN_NEXT_START, X_SIZE)))) else\r
---               '1';\r
---    ah_oe_n <= \r
---            '0' when (\r
---                ((ppu_mask(PPUSBG) = '1' or ppu_mask(PPUSSP) = '1') and\r
---                (nes_y < conv_std_logic_vector(VSCAN, X_SIZE) or \r
---                nes_y = conv_std_logic_vector(VSCAN_NEXT_START, X_SIZE)))) else\r
---            '1';\r
---    v_bus_busy_n <= ah_oe_n;\r
---\r
---\r
---    -----------------------------------------\r
---    --vram i/o\r
---    -----------------------------------------\r
---    vram_io_buf : tri_state_buffer generic map (dsize)\r
---            port map (al_oe_n, vram_addr(dsize - 1 downto 0), vram_ad);\r
---\r
---    vram_a_buf : tri_state_buffer generic map (6)\r
---            port map (ah_oe_n, vram_addr(asize - 1 downto dsize), vram_a);\r
---\r
---\r
---    -----------------------------------------\r
---    ---palette ram\r
---    -----------------------------------------\r
---    r_n <= not r_nw;\r
---\r
---    plt_ram_ce_n <= '0' when plt_bus_ce_n = '0' and r_nw = '0' else \r
---                    '0' when plt_bus_ce_n = '0' and r_nw = '1' else\r
---                    '0' when ppu_mask(PPUSBG) = '1' and \r
---                            (nes_x < conv_std_logic_vector(HSCAN, X_SIZE)) and \r
---                            (nes_y < conv_std_logic_vector(VSCAN, X_SIZE)) else\r
---                    '1';\r
---\r
---    plt_addr <= oam_plt_addr(4 downto 0) when plt_bus_ce_n = '0' else\r
+    -----------------------------------------\r
+    ---palette ram\r
+    -----------------------------------------\r
+    r_n <= not r_nw;\r
+\r
+    plt_ram_ce_n <= '0' when plt_bus_ce_n = '0' and r_nw = '0' else \r
+                    '0' when plt_bus_ce_n = '0' and r_nw = '1' else\r
+                    '0' when ppu_mask(PPUSBG) = '1' and \r
+                            (nes_x < conv_std_logic_vector(HSCAN, X_SIZE)) and \r
+                            (nes_y < conv_std_logic_vector(VSCAN, X_SIZE)) else\r
+                    '1';\r
+\r
+    plt_addr <= plt_addr_in when plt_bus_ce_n = '0' else\r
 --                "1" & spr_attr(0)(1 downto 0) & spr_ptn_h(0)(0) & spr_ptn_l(0)(0)\r
 --                    when ppu_mask(PPUSSP) = '1' and\r
 --                        (nes_x < conv_std_logic_vector(HSCAN, X_SIZE)) and\r
@@ -600,21 +531,84 @@ begin
 --                        ((disp_ptn_h(0) or disp_ptn_l(0)) = '1') and\r
 --                        (nes_x < conv_std_logic_vector(HSCAN, X_SIZE)) and\r
 --                        (nes_y < conv_std_logic_vector(VSCAN, X_SIZE)) else\r
---                ---else: no output color >> universal bg color output.\r
---                --0x3f00 is the universal bg palette.\r
---                (others => '0');    \r
+                ---else: no output color >> universal bg color output.\r
+                --0x3f00 is the universal bg palette.\r
+                (others => '0');    \r
+\r
+    plt_r_n <= not r_nw when plt_bus_ce_n = '0' else\r
+                '0' when ppu_mask(PPUSBG) = '1' else\r
+                '1';\r
+    plt_w_n <= r_nw when plt_bus_ce_n = '0' else\r
+                '1';\r
+    plt_d_buf_w : tri_state_buffer generic map (dsize)\r
+            port map (plt_w_n, plt_data_in, plt_data);\r
+    plt_d_buf_r : tri_state_buffer generic map (dsize)\r
+            port map (plt_r_n, plt_data, plt_data_out);\r
+    palette_inst : palette_ram generic map (5, dsize)\r
+            port map (emu_ppu_clk, plt_ram_ce_n, plt_r_n, plt_w_n, plt_addr, plt_data);\r
+\r
+\r
+\r
+    -----------------------------------------\r
+    ---vram access signals\r
+    -----------------------------------------\r
+    reset_p : process (rst_n, emu_ppu_clk)\r
+    begin\r
+        if (rst_n = '0') then\r
+            io_cnt_rst_n <= '0';\r
+        else\r
+            if (rising_edge(emu_ppu_clk)) then\r
+                if (nes_x >= conv_std_logic_vector(VGA_W_MAX / 2 - 1, X_SIZE)) then io_cnt_rst_n <= '0';\r
+                else io_cnt_rst_n <= '1';\r
+                end if; \r
+            end if;\r
+        end if;\r
+    end process;\r
+\r
+    io_cnt_inst : counter_register generic map (1, 1)\r
+            port map (emu_ppu_clk, io_cnt_rst_n, '0', '1', (others => '0'), io_cnt);\r
+\r
+    ale <= \r
+            not io_cnt(0) when (\r
+                ((ppu_mask(PPUSBG) = '1' or ppu_mask(PPUSSP) = '1') and\r
+                (nes_y < conv_std_logic_vector(VSCAN, X_SIZE) or \r
+                nes_y = conv_std_logic_vector(VSCAN_NEXT_START, X_SIZE)))) else\r
+            'Z';\r
+    rd_n <= \r
+            not io_cnt(0) when (\r
+                ((ppu_mask(PPUSBG) = '1' or ppu_mask(PPUSSP) = '1') and\r
+                (nes_y < conv_std_logic_vector(VSCAN, X_SIZE) or \r
+                nes_y = conv_std_logic_vector(VSCAN_NEXT_START, X_SIZE)))) else\r
+            'Z';\r
+    wr_n <= \r
+            '1' when (\r
+                ((ppu_mask(PPUSBG) = '1' or ppu_mask(PPUSSP) = '1') and\r
+                (nes_y < conv_std_logic_vector(VSCAN, X_SIZE) or \r
+                nes_y = conv_std_logic_vector(VSCAN_NEXT_START, X_SIZE)))) else\r
+            'Z';\r
+    al_oe_n <= \r
+            io_cnt(0) when (\r
+                ((ppu_mask(PPUSBG) = '1' or ppu_mask(PPUSSP) = '1') and\r
+                (nes_y < conv_std_logic_vector(VSCAN, X_SIZE) or \r
+                nes_y = conv_std_logic_vector(VSCAN_NEXT_START, X_SIZE)))) else\r
+               '1';\r
+    ah_oe_n <= \r
+            '0' when (\r
+                ((ppu_mask(PPUSBG) = '1' or ppu_mask(PPUSSP) = '1') and\r
+                (nes_y < conv_std_logic_vector(VSCAN, X_SIZE) or \r
+                nes_y = conv_std_logic_vector(VSCAN_NEXT_START, X_SIZE)))) else\r
+            '1';\r
+    v_bus_busy_n <= ah_oe_n;\r
+\r
+\r
+--    -----------------------------------------\r
+--    --vram i/o\r
+--    -----------------------------------------\r
+--    vram_io_buf : tri_state_buffer generic map (dsize)\r
+--            port map (al_oe_n, vram_addr(dsize - 1 downto 0), vram_ad);\r
 --\r
---    plt_r_n <= not r_nw when plt_bus_ce_n = '0' else\r
---                '0' when ppu_mask(PPUSBG) = '1' else\r
---                '1';\r
---    plt_w_n <= r_nw when plt_bus_ce_n = '0' else\r
---                '1';\r
---    plt_d_buf_w : tri_state_buffer generic map (dsize)\r
---            port map (plt_w_n, oam_plt_data, plt_data);\r
---    plt_d_buf_r : tri_state_buffer generic map (dsize)\r
---            port map (plt_r_n, plt_data, oam_plt_data);\r
---    palette_inst : palette_ram generic map (5, dsize)\r
---            port map (emu_ppu_clk, plt_ram_ce_n, plt_r_n, plt_w_n, plt_addr, plt_data);\r
+--    vram_a_buf : tri_state_buffer generic map (6)\r
+--            port map (ah_oe_n, vram_addr(asize - 1 downto dsize), vram_a);\r
 --\r
 --\r
 --    -----------------------------------------\r