bg pattern ok on rtl.

diff --git a/de0_cv_nes/ppu/render.vhd b/de0_cv_nes/ppu/render.vhd
index 18d3e92..ce79111 100644 (file)
--- a/de0_cv_nes/ppu/render.vhd
+++ b/de0_cv_nes/ppu/render.vhd
@@ -424,6 +424,8 @@ end;
         if (pi_rst_n = '0') then\r
             reg_v_addr  <= (others => 'Z');\r
             reg_v_data    <= (others => 'Z');\r
+            reg_disp_nt     <= (others => 'Z');\r
+            reg_disp_attr   <= (others => 'Z');\r
         elsif (rising_edge(pi_base_clk)) then\r
             reg_v_data    <= pi_v_data;\r
             \r
@@ -437,6 +439,10 @@ end;
                             & conv_std_logic_vector(reg_prf_x, 9)(7 downto 3);\r
                     reg_v_addr(13 downto 10) <= "10" & pi_ppu_ctrl(PPUBNA downto 0)\r
                                                     + ("000" & conv_std_logic_vector(reg_prf_x, 9)(8));\r
+                \r
+                elsif (reg_prf_x mod 8 = 2 and reg_v_cur_state = REG_SET0) then\r
+                    reg_disp_nt     <= reg_v_data;\r
+                \r
                 ----fetch attr table byte.\r
                 elsif (reg_prf_x mod 8 = 3) then\r
                     --attr table at 0x23c0\r
@@ -446,12 +452,17 @@ end;
                     reg_v_addr(13 downto 8) <= "10" &\r
                             pi_ppu_ctrl(PPUBNA downto 0) & "11"\r
                                 + ("000" & conv_std_logic_vector(reg_prf_x, 9)(8) & "00");\r
+                \r
+                elsif (reg_prf_x mod 8 = 4 and reg_v_cur_state = REG_SET0) then\r
+                    reg_disp_attr   <= reg_v_data;\r
+\r
                 ----fetch pattern table low byte.\r
                 elsif (reg_prf_x mod 8 = 5) then\r
                      --vram addr is incremented every 8 cycle.\r
                      reg_v_addr <= "0" & pi_ppu_ctrl(PPUBPA) &\r
                                           reg_disp_nt(7 downto 0)\r
                                         & "0" & conv_std_logic_vector(reg_prf_y, 9)(2 downto 0);\r
+\r
                 ----fetch pattern table high byte.\r
                 elsif (reg_prf_x mod 8 = 7) then\r
                      --vram addr is incremented every 8 cycle.\r
@@ -464,28 +475,50 @@ end;
         end if;--if (pi_rst_n = '0') then\r
     end process;\r
 \r
-    --vram r/w selector state machine...\r
-    bg_main_stat_p : process (reg_v_cur_state, reg_v_data)\r
+    --vram address state machine...\r
+    bg_ptn_p : process (pi_rst_n, pi_base_clk)\r
+function is_bg (\r
+    pm_sbg          : in std_logic;\r
+    pm_nes_x        : in integer range 0 to VGA_W_MAX - 1;\r
+    pm_nes_y        : in integer range 0 to VGA_H_MAX - 1\r
+    )return integer is\r
+begin\r
+    if (pm_sbg = '1'and\r
+        (pm_nes_x <= HSCAN or pm_nes_x >= HSCAN_NEXT_START) and\r
+        (pm_nes_y < VSCAN or pm_nes_y = VSCAN_NEXT_START)) then\r
+        return 1;\r
+    else\r
+        return 0;\r
+    end if;\r
+end;\r
     begin\r
-        case reg_v_cur_state is\r
-            when IDLE =>\r
-                reg_disp_nt     <= (others => 'Z');\r
-                reg_disp_attr   <= (others => 'Z');\r
-                reg_disp_ptn_l  <= (others => 'Z');\r
-                reg_disp_ptn_h  <= (others => 'Z');\r
-            when AD_SET0 | AD_SET1 | REG_SET2 | AD_SET2 | AD_SET3 | REG_SET0 | REG_SET1 =>\r
---                reg_disp_nt     <= (others => 'Z');\r
---                reg_disp_attr   <= (others => 'Z');\r
---                reg_disp_ptn_l  <= (others => 'Z');\r
---                reg_disp_ptn_h  <= (others => 'Z');\r
-            when REG_SET3 =>\r
-                reg_disp_nt     <= reg_v_data;\r
-                reg_disp_attr   <= reg_v_data;\r
-                reg_disp_ptn_l  <= reg_v_data & "00000000";\r
-                reg_disp_ptn_h  <= reg_v_data & "00000000";\r
-        end case;\r
-    end process;\r
+        if (pi_rst_n = '0') then\r
+            reg_disp_ptn_l  <= (others => '0');\r
+            reg_disp_ptn_h  <= (others => '0');\r
+        elsif (rising_edge(pi_base_clk)) then\r
+\r
+            if (is_bg(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1) then\r
+                if (reg_v_cur_state = REG_SET0) then\r
+                    if (reg_prf_x mod 8 = 6) then\r
+                        reg_disp_ptn_l   <= reg_v_data & reg_disp_ptn_l(7 downto 0);\r
+                    else\r
+                        reg_disp_ptn_l   <= "0" & reg_disp_ptn_l(15 downto 1);\r
+                    end if;\r
+\r
+                    if (reg_prf_x mod 8 = 0) then\r
+                        reg_disp_ptn_h   <= reg_v_data & reg_disp_ptn_h(7 downto 0);\r
+                    else\r
+                        reg_disp_ptn_h   <= "0" & reg_disp_ptn_h(15 downto 1);\r
+                    end if;\r
+\r
+                elsif (reg_v_cur_state = AD_SET0) then\r
+                    reg_disp_ptn_l   <= "0" & reg_disp_ptn_l(15 downto 1);\r
+                    reg_disp_ptn_h   <= "0" & reg_disp_ptn_h(15 downto 1);\r
 \r
+                end if;\r
+            end if;\r
+        end if;--if (pi_rst_n = '0') then\r
+    end process;\r
 \r
     po_ppu_status   <= (others => '0');\r
 \r

diff --git a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
index d0c965e..da8999f 100644 (file)
--- a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
+++ b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
@@ -51,7 +51,7 @@ add wave -divider render
 add wave -label nes_x       sim:/testbench_motones_sim/sim_board/render_inst/reg_nes_x;\r
 add wave -label nes_y       sim:/testbench_motones_sim/sim_board/render_inst/reg_nes_y;\r
 #add wave -label wr_rnd_en  sim:/testbench_motones_sim/sim_board/wr_rnd_en;\r
-#add wave -label reg_v_cur_state sim:/testbench_motones_sim/sim_board/render_inst/reg_v_cur_state;\r
+add wave -label reg_v_cur_state sim:/testbench_motones_sim/sim_board/render_inst/reg_v_cur_state;\r
 add wave -label prf_x       sim:/testbench_motones_sim/sim_board/render_inst/reg_prf_x;\r
 #add wave -label prf_y       sim:/testbench_motones_sim/sim_board/render_inst/reg_prf_y;\r
 \r

diff --git a/doc/mos6502-clock.xlsx b/doc/mos6502-clock.xlsx
index 1ed951b..56f040a 100644 (file)
Binary files a/doc/mos6502-clock.xlsx and b/doc/mos6502-clock.xlsx differ