cleaned up meaningless timing

diff --git a/de0_cv_nes/ppu/render.vhd b/de0_cv_nes/ppu/render.vhd
index a2cc895..2a07eeb 100644 (file)
--- a/de0_cv_nes/ppu/render.vhd
+++ b/de0_cv_nes/ppu/render.vhd
@@ -406,81 +406,49 @@ end;
                 end if;\r
             when AD_SET0 =>\r
                 if (is_v_access(pi_ppu_mask(PPUSBG), pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
-                    if (pi_rnd_en(3) = '1') then\r
-                        reg_v_next_state <= AD_SET1;\r
-                    else\r
-                        reg_v_next_state <= reg_v_cur_state;\r
-                    end if;\r
+                    reg_v_next_state <= AD_SET1;\r
                 else\r
                     reg_v_next_state <= IDLE;\r
                 end if;\r
             when AD_SET1 =>\r
                 if (is_v_access(pi_ppu_mask(PPUSBG), pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
-                    if (pi_rnd_en(0) = '1') then\r
-                        reg_v_next_state <= AD_SET2;\r
-                    else\r
-                        reg_v_next_state <= reg_v_cur_state;\r
-                    end if;\r
+                    reg_v_next_state <= AD_SET2;\r
                 else\r
                     reg_v_next_state <= IDLE;\r
                 end if;\r
             when AD_SET2 =>\r
                 if (is_v_access(pi_ppu_mask(PPUSBG), pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
-                    if (pi_rnd_en(1) = '1') then\r
-                        reg_v_next_state <= AD_SET3;\r
-                    else\r
-                        reg_v_next_state <= reg_v_cur_state;\r
-                    end if;\r
+                    reg_v_next_state <= AD_SET3;\r
                 else\r
                     reg_v_next_state <= IDLE;\r
                 end if;\r
             when AD_SET3 =>\r
                 if (is_v_access(pi_ppu_mask(PPUSBG), pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
-                    if (pi_rnd_en(2) = '1') then\r
-                        reg_v_next_state <= REG_SET0;\r
-                    else\r
-                        reg_v_next_state <= reg_v_cur_state;\r
-                    end if;\r
+                    reg_v_next_state <= REG_SET0;\r
                 else\r
                     reg_v_next_state <= IDLE;\r
                 end if;\r
             when REG_SET0 =>\r
                 if (is_v_access(pi_ppu_mask(PPUSBG), pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
-                    if (pi_rnd_en(3) = '1') then\r
-                        reg_v_next_state <= REG_SET1;\r
-                    else\r
-                        reg_v_next_state <= reg_v_cur_state;\r
-                    end if;\r
+                    reg_v_next_state <= REG_SET1;\r
                 else\r
                     reg_v_next_state <= IDLE;\r
                 end if;\r
             when REG_SET1 =>\r
                 if (is_v_access(pi_ppu_mask(PPUSBG), pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
-                    if (pi_rnd_en(0) = '1') then\r
-                        reg_v_next_state <= REG_SET2;\r
-                    else\r
-                        reg_v_next_state <= reg_v_cur_state;\r
-                    end if;\r
+                    reg_v_next_state <= REG_SET2;\r
                 else\r
                     reg_v_next_state <= IDLE;\r
                 end if;\r
             when REG_SET2 =>\r
                 if (is_v_access(pi_ppu_mask(PPUSBG), pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
-                    if (pi_rnd_en(1) = '1') then\r
-                        reg_v_next_state <= REG_SET3;\r
-                    else\r
-                        reg_v_next_state <= reg_v_cur_state;\r
-                    end if;\r
+                    reg_v_next_state <= REG_SET3;\r
                 else\r
                     reg_v_next_state <= IDLE;\r
                 end if;\r
             when REG_SET3 =>\r
                 if (is_v_access(pi_ppu_mask(PPUSBG), pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
-                    if (pi_rnd_en(2) = '1') then\r
-                        reg_v_next_state <= AD_SET0;\r
-                    else\r
-                        reg_v_next_state <= reg_v_cur_state;\r
-                    end if;\r
+                    reg_v_next_state <= AD_SET0;\r
                 else\r
                     reg_v_next_state <= IDLE;\r
                 end if;\r
@@ -719,20 +687,27 @@ end;
 \r
     --state change to next.\r
     s_oam_next_stat_p : process (reg_s_oam_cur_state, pi_rnd_en, pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y)\r
-function is_idle (\r
+function is_s_oam_access (\r
     pm_ssp          : in std_logic;\r
     pm_nes_x        : in integer range 0 to VGA_W_MAX - 1;\r
     pm_nes_y        : in integer range 0 to VGA_H_MAX - 1\r
     )return integer is\r
 begin\r
-    if (pm_ssp = '0' or\r
-        (pm_nes_x > HSCAN_SPR_MAX) or\r
-        (pm_nes_y >= VSCAN and pm_nes_y < VSCAN_NEXT_START)) then\r
-        return 1;\r
+    if ((pm_nes_y < VSCAN or pm_nes_y = VSCAN_NEXT_START)) then\r
+        if (pm_nes_x < HSCAN_SPR_MAX) then\r
+            if (pm_ssp = '1') then\r
+                return 1;\r
+            else\r
+                return 0;\r
+            end if;\r
+        else\r
+            return 0;\r
+        end if;\r
     else\r
         return 0;\r
     end if;\r
 end;\r
+\r
     begin\r
         case reg_s_oam_cur_state is\r
             when IDLE =>\r
@@ -745,68 +720,52 @@ end;
                     reg_s_oam_next_state <= reg_s_oam_cur_state;\r
                 end if;\r
             when AD_SET0 =>\r
-                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
-                    reg_s_oam_next_state <= IDLE;\r
-                elsif (pi_rnd_en(3) = '1') then\r
+                if (is_s_oam_access(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
                     reg_s_oam_next_state <= AD_SET1;\r
                 else\r
-                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                    reg_s_oam_next_state <= IDLE;\r
                 end if;\r
             when AD_SET1 =>\r
-                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
-                    reg_s_oam_next_state <= IDLE;\r
-                elsif (pi_rnd_en(0) = '1') then\r
+                if (is_s_oam_access(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
                     reg_s_oam_next_state <= AD_SET2;\r
                 else\r
-                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                    reg_s_oam_next_state <= IDLE;\r
                 end if;\r
             when AD_SET2 =>\r
-                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
-                    reg_s_oam_next_state <= IDLE;\r
-                elsif (pi_rnd_en(1) = '1') then\r
+                if (is_s_oam_access(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
                     reg_s_oam_next_state <= AD_SET3;\r
                 else\r
-                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                    reg_s_oam_next_state <= IDLE;\r
                 end if;\r
             when AD_SET3 =>\r
-                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
-                    reg_s_oam_next_state <= IDLE;\r
-                elsif (pi_rnd_en(2) = '1') then\r
+                if (is_s_oam_access(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
                     reg_s_oam_next_state <= REG_SET0;\r
                 else\r
-                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                    reg_s_oam_next_state <= IDLE;\r
                 end if;\r
             when REG_SET0 =>\r
-                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
-                    reg_s_oam_next_state <= IDLE;\r
-                elsif (pi_rnd_en(3) = '1') then\r
+                if (is_s_oam_access(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
                     reg_s_oam_next_state <= REG_SET1;\r
                 else\r
-                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                    reg_s_oam_next_state <= IDLE;\r
                 end if;\r
             when REG_SET1 =>\r
-                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
-                    reg_s_oam_next_state <= IDLE;\r
-                elsif (pi_rnd_en(0) = '1') then\r
+                if (is_s_oam_access(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
                     reg_s_oam_next_state <= REG_SET2;\r
                 else\r
-                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                    reg_s_oam_next_state <= IDLE;\r
                 end if;\r
             when REG_SET2 =>\r
-                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
-                    reg_s_oam_next_state <= IDLE;\r
-                elsif (pi_rnd_en(1) = '1') then\r
+                if (is_s_oam_access(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
                     reg_s_oam_next_state <= REG_SET3;\r
                 else\r
-                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                    reg_s_oam_next_state <= IDLE;\r
                 end if;\r
             when REG_SET3 =>\r
-                if (is_idle(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
-                    reg_s_oam_next_state <= IDLE;\r
-                elsif (pi_rnd_en(2) = '1') then\r
+                if (is_s_oam_access(pi_ppu_mask(PPUSSP), reg_nes_x, reg_nes_y) = 1) then\r
                     reg_s_oam_next_state <= AD_SET0;\r
                 else\r
-                    reg_s_oam_next_state <= reg_s_oam_cur_state;\r
+                    reg_s_oam_next_state <= IDLE;\r
                 end if;\r
         end case;\r
     end process;\r