timing analysis started... (so late!)

diff --git a/de1_nes/de1_nes.qsf b/de1_nes/de1_nes.qsf
index ce9d102..e4ed9cc 100644 (file)
--- a/de1_nes/de1_nes.qsf
+++ b/de1_nes/de1_nes.qsf
@@ -89,13 +89,15 @@ set_global_assignment -name VHDL_FILE ppu/ppu.vhd
 #set_global_assignment -name VHDL_FILE "dummy-ppu.vhd"\r
 \r
 #cpu block...\r
-#set_global_assignment -name VHDL_FILE mem/prg_rom.vhd\r
-#set_global_assignment -name VHDL_FILE cpu/cpu_registers.vhd\r
-#set_global_assignment -name VHDL_FILE cpu/alu.vhd\r
-#set_global_assignment -name VHDL_FILE cpu/decoder.vhd\r
-#set_global_assignment -name VHDL_FILE cpu/mos6502.vhd\r
+set_global_assignment -name VHDL_FILE mem/prg_rom.vhd\r
+set_global_assignment -name VHDL_FILE cpu/cpu_registers.vhd\r
+set_global_assignment -name VHDL_FILE cpu/alu.vhd\r
+set_global_assignment -name VHDL_FILE cpu/decoder.vhd\r
+set_global_assignment -name VHDL_FILE cpu/mos6502.vhd\r
 \r
-set_global_assignment -name VHDL_FILE "dummy-mos6502.vhd"\r
+#set_global_assignment -name VHDL_FILE "dummy-mos6502.vhd"\r
+\r
+#entire motones element...\r
 set_global_assignment -name VHDL_FILE de1_nes.vhd\r
 \r
 #need this config to program active serial mode...\r

diff --git a/de1_nes/ppu/vga_ppu.vhd b/de1_nes/ppu/vga_ppu.vhd
index 132caf8..b850b12 100644 (file)
--- a/de1_nes/ppu/vga_ppu.vhd
+++ b/de1_nes/ppu/vga_ppu.vhd
@@ -1100,7 +1100,6 @@ begin
             vram_addr <= (others => 'Z');\r
         else\r
             if (rising_edge(emu_ppu_clk)) then\r
-                --fetch sprite and display.\r
 \r
                 if (nes_y < conv_std_logic_vector(VSCAN, X_SIZE) or \r
                      nes_y = conv_std_logic_vector(VSCAN_NEXT_START, X_SIZE)) then\r
@@ -1181,6 +1180,8 @@ begin
                                                 + "00000000001000";\r
                             end if;\r
                         end if;\r
+                    else\r
+                        vram_addr <= (others => 'Z');\r
                     end if; --if (nes_x > conv_std_logic_vector(HSCAN, X_SIZE) and \r
                                 --nes_x <= conv_std_logic_vector(HSCAN_SPR_MAX, X_SIZE)) then\r
                 else\r

diff --git a/tools/regression-test/regression.asm b/tools/regression-test/regression.asm
index 379e268..8812156 100644 (file)
--- a/tools/regression-test/regression.asm
+++ b/tools/regression-test/regression.asm
@@ -33,31 +33,31 @@
     jsr init_global\r
     jsr init_ppu\r
 \r
-;    lda ad_start_msg\r
-;    sta $00\r
-;    lda ad_start_msg+1\r
-;    sta $01\r
-;    jsr print_ln\r
-;    jsr print_ln\r
-;    jsr print_ln\r
-;    jsr print_ln\r
-;    jsr print_ln\r
-;    jsr print_ln\r
-;\r
-;    ;;test start...\r
-;    jsr addr_test\r
-;    jsr single_inst_test\r
-;    jsr a2_inst_test\r
-;    jsr a3_inst_test\r
-;    jsr a4_inst_test\r
-;    jsr a5_inst_test\r
-;    jsr status_test\r
-;    jsr ppu_test\r
-;\r
-;    jsr pg_border_test\r
-;    jsr dma_test\r
-\r
-;    jsr simple_dma_test\r
+    lda ad_start_msg\r
+    sta $00\r
+    lda ad_start_msg+1\r
+    sta $01\r
+    jsr print_ln\r
+    jsr print_ln\r
+    jsr print_ln\r
+    jsr print_ln\r
+    jsr print_ln\r
+    jsr print_ln\r
+\r
+    ;;test start...\r
+    jsr addr_test\r
+    jsr single_inst_test\r
+    jsr a2_inst_test\r
+    jsr a3_inst_test\r
+    jsr a4_inst_test\r
+    jsr a5_inst_test\r
+    jsr status_test\r
+    jsr ppu_test\r
+\r
+    jsr pg_border_test\r
+    jsr dma_test\r
+\r
+    jsr simple_dma_test\r
 \r
 .endproc\r
 \r
@@ -3397,7 +3397,7 @@ ad_single_test:
 \r
 ;;ppu test flag.\r
 use_ppu:\r
-    .byte   $00\r
+    .byte   $01\r
 \r
 full_dma_test:\r
     .byte   $01\r