pc update timing fixed.

added ldx, txs, jmp (not completed).

diff --git a/simulation/cpu/cpu_registers.vhd b/simulation/cpu/cpu_registers.vhd
index 4a6b552..45f9598 100644 (file)
--- a/simulation/cpu/cpu_registers.vhd
+++ b/simulation/cpu/cpu_registers.vhd
@@ -67,7 +67,7 @@ entity instruction_reg is
             dsize : integer := 8
             );
     port (  
-            set_clk         : in std_logic;
+            trig_clk        : in std_logic;
             cpu_d_bus       : in std_logic_vector (dsize - 1 downto 0);
             to_decoder      : out std_logic_vector (dsize - 1 downto 0)
         );
@@ -75,9 +75,9 @@ end instruction_reg;
 
 architecture rtl of instruction_reg is
 begin
-    process (set_clk)
+    process (trig_clk)
     begin
-        if ( set_clk'event and set_clk = '1') then
+        if ( trig_clk'event and trig_clk = '1') then
             to_decoder <= cpu_d_bus;
         end if;
     end process;

diff --git a/simulation/cpu/decoder.vhd b/simulation/cpu/decoder.vhd
index e6b1b6e..ae029f2 100644 (file)
--- a/simulation/cpu/decoder.vhd
+++ b/simulation/cpu/decoder.vhd
@@ -3,6 +3,8 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.conv_std_logic_vector;
 --use ieee.std_logic_arith.all;
 use std.textio.all;
+use ieee.std_logic_textio.all;
+use ieee.std_logic_unsigned.conv_integer;
 
 entity decoder is 
     generic (dsize : integer := 8);
@@ -34,62 +36,123 @@ begin
     writeline(output, out_l);
 end  procedure;
 
+procedure d_print(msg : string; sig : std_logic_vector) is
+variable out_l : line;
+begin
+    write(out_l, msg);
+    write(out_l, sig);
+    writeline(output, out_l);
+end  procedure;
+
+procedure d_print(msg : string; ival : integer) is
+variable out_l : line;
+begin
+    write(out_l, msg);
+    write(out_l, ival);
+    writeline(output, out_l);
+end  procedure;
+
 type dec_status is (reset0, reset1, reset2, reset3, reset4, reset5, 
                     fetch, exec, 
                     sei,
+                    ldx1, ldx2, ldx3,
+                    jmp1, jmp2, jmp3, jmp4,
                     nop,
                     unknown_stat
                     );
 
-signal cur_stat : dec_status;
+signal cur_status : dec_status;
 
 begin
 
     main_p : process (set_clk, trig_clk, res_n)
     begin
         if (res_n'event and res_n = '0') then
-            cur_stat <= reset0;
+            d_print(string'("reset"));
+            cur_status <= reset0;
         end if;
 
         if (set_clk'event and set_clk = '1') then
-            d_print(string'("set_clk"));
+            d_print(string'("*"));
 
-            case cur_stat is
+            case cur_status is
                 when reset0 => 
-                    cur_stat <= reset1;
+                    cur_status <= reset1;
                 when reset1 => 
-                    cur_stat <= reset2;
+                    cur_status <= reset2;
                 when reset2 => 
-                    cur_stat <= reset3;
+                    cur_status <= reset3;
                 when reset3 => 
-                    cur_stat <= reset4;
+                    cur_status <= reset4;
                 when reset4 => 
-                    cur_stat <= reset5;
+                    cur_status <= reset5;
                 when reset5 => 
-                    cur_stat <= fetch;
+                    cur_status <= fetch;
                 when fetch => 
                     d_print(string'("fetch"));
                     pcl_a_o_n <= '0';
                     pch_a_o_n <= '0';
                     r_nw <= '1';
-                    cur_stat <= exec;
+                    pc_inc_n <= '0';
+                    cur_status <= exec;
                 when exec => 
-                    d_print(string'("exec and decode"));
+                    d_print(string'(" exec and decode "), conv_integer(instruction));
                     ---one byte instruction decoding.
                     if instruction = conv_std_logic_vector(16#78#, dsize) then
-                        d_print(string'("sei"));
+                        --0x78 = 120
+                        d_print(string'("   sei"));
+                        pcl_a_o_n <= '1';
+                        pch_a_o_n <= '1';
+                        pc_inc_n <= '1';
+                        ---set flag operation here.
+                        cur_status <= fetch;
+                    elsif instruction = conv_std_logic_vector(16#a2#, dsize) then
+                        --0xa2 = 162 
+                        d_print(string'("   ldx 0"));
+                        pcl_a_o_n <= '0';
+                        pch_a_o_n <= '0';
+                        pc_inc_n <= '0';
+                        ---load X operation here.
+                        cur_status <= fetch;
+                    elsif instruction = conv_std_logic_vector(16#9a#, dsize) then
+                        --0x9a = 154
+                        d_print(string'("   txs"));
                         pcl_a_o_n <= '1';
                         pch_a_o_n <= '1';
+                        pc_inc_n <= '1';
+                        cur_status <= fetch;
+                    elsif instruction = conv_std_logic_vector(16#4c#, dsize) then
+                        --0x4c = 76
+                        cur_status <= jmp1;
+                        d_print(string'("   jmp 0"));
                         pc_inc_n <= '0';
-                        cur_stat <= fetch;
+                        pcl_a_o_n <= '0';
+                        pch_a_o_n <= '0';
+                        cur_status <= jmp1;
+
                     else
-                        cur_stat <= unknown_stat;
+                        cur_status <= unknown_stat;
                         d_print(string'("unknown inst."));
+                        pc_inc_n <= '1';
+                        pcl_a_o_n <= '1';
+                        pch_a_o_n <= '1';
                     end if;
 
+                when ldx1 => 
+                    d_print(string'("   ldx 1"));
+                    cur_status <= unknown_stat;
+                when jmp1 => 
+                    d_print(string'("   jmp 1"));
+                    pc_inc_n <= '0';
+                    pcl_a_o_n <= '1';
+                    pch_a_o_n <= '1';
+                    cur_status <= fetch;
+                when jmp2 => 
+                    d_print(string'("   jmp 2"));
+
                 when others => null;
                     d_print(string'("unknown status."));
-                    cur_stat <= unknown_stat;
+                    cur_status <= unknown_stat;
             end case;
         end if;
 

diff --git a/simulation/cpu/mos6502.vhd b/simulation/cpu/mos6502.vhd
index a0c7d45..bea8a23 100644 (file)
--- a/simulation/cpu/mos6502.vhd
+++ b/simulation/cpu/mos6502.vhd
@@ -65,7 +65,7 @@ architecture rtl of mos6502 is
                 dsize : integer := 8
                 );
         port (  
-                set_clk         : in std_logic;
+                trig_clk         : in std_logic;
                 cpu_d_bus       : in std_logic_vector (dsize - 1 downto 0);
                 to_decoder      : out std_logic_vector (dsize - 1 downto 0)
             );
@@ -110,7 +110,7 @@ begin
                     );
 
     instruction_register : instruction_reg generic map (dsize) 
-            port map(set_clk, d_io, instruction);
+            port map(trigger_clk, d_io, instruction);
 
     -- clock generate.
     phi1 <= input_clk;