sprite & dma ok.

diff --git a/de0_cv_nes/dummy-smb-rom.vhd b/de0_cv_nes/dummy-smb-rom.vhd
index 3310b79..2dabacb 100644 (file)
--- a/de0_cv_nes/dummy-smb-rom.vhd
+++ b/de0_cv_nes/dummy-smb-rom.vhd
@@ -22,6 +22,10 @@ end mos6502;
 \r
 architecture rtl of mos6502 is\r
 \r
+constant cpu_io_multi   : integer := 3; --io happens every 4 cpu cycle.\r
+constant bg_tile_cnt    : integer := 1023;\r
+constant spr_tile_cnt    : integer := 255;\r
+    \r
 signal reg_oe_n     : std_logic;\r
 signal reg_we_n     : std_logic;\r
 signal reg_addr     : std_logic_vector ( 15 downto 0);\r
@@ -137,11 +141,6 @@ begin
     set_ppu_p : process (pi_base_clk, pi_rst_n)\r
     use ieee.std_logic_arith.conv_std_logic_vector;\r
 \r
-    constant cpu_io_multi   : integer := 3; --io happens every 4 cpu cycle.\r
-    constant bg_tile_cnt    : integer := 1023;\r
-    constant spr_tile_cnt    : integer := 255;\r
-    --constant bg_tile_cnt    : integer := 127;\r
-    \r
     variable init_plt_cnt : integer;\r
     variable init_vram_cnt : integer;\r
     variable init_spr_cnt : integer;\r
@@ -162,6 +161,7 @@ use ieee.std_logic_unsigned.all;
 begin\r
     --fake ram read/write to emulate dummy i/o.\r
     reg_d_out <= (others => 'Z');\r
+    reg_addr <= (others => 'Z');\r
     reg_oe_n <= 'Z';\r
     reg_we_n <= 'Z';\r
 end;\r
@@ -215,7 +215,7 @@ end;
                         else\r
                             io_read(16#00#);\r
                             if (init_plt_cnt > (32 + 3) * cpu_io_multi) then\r
-                                global_step_cnt := global_step_cnt + 2;\r
+                                global_step_cnt := global_step_cnt + 1;\r
                             end if;\r
                         end if;\r
                         init_plt_cnt := init_plt_cnt + 1;\r
@@ -242,10 +242,10 @@ end;
                     elsif (global_step_cnt = 2) then\r
                         --set dma data.\r
                         --dma addr = 0x0300.\r
-                        if (init_spr_cnt mod cpu_io_multi = 0 and init_spr_cnt <= (spr_tile_cnt + 2) * cpu_io_multi) then\r
+                        if (init_spr_cnt mod cpu_io_multi = 0 and init_spr_cnt <= (spr_tile_cnt + 0) * cpu_io_multi) then\r
                             io_out(16#0300# + init_spr_cnt / cpu_io_multi, nes_spr_data(init_spr_cnt / cpu_io_multi));\r
 \r
-                        elsif (init_spr_cnt = (spr_tile_cnt + 0) * cpu_io_multi) then\r
+                        elsif (init_spr_cnt = (spr_tile_cnt + 1) * cpu_io_multi) then\r
                             --dma start.\r
                             io_out(16#4014#, 3);\r
 \r
@@ -324,46 +324,46 @@ end rtl;
 \r
 \r
 \r
------------dummy apu\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.std_logic_arith.conv_std_logic_vector;\r
-\r
-entity apu is \r
-    port (\r
-        pi_rst_n       : in std_logic;\r
-        pi_base_clk    : in std_logic;\r
-        pi_cpu_en      : in std_logic_vector (7 downto 0);\r
-        pi_rnd_en      : in std_logic_vector (3 downto 0);\r
-        pi_ce_n        : in std_logic;\r
-\r
-        --cpu i/f\r
-        pio_oe_n       : inout std_logic;\r
-        pio_we_n       : inout std_logic;\r
-        pio_cpu_addr   : inout std_logic_vector (15 downto 0);\r
-        pio_cpu_d      : inout std_logic_vector (7 downto 0);\r
-        po_rdy         : out std_logic;\r
-\r
-        --sprite i/f\r
-        po_spr_ce_n    : out std_logic;\r
-        po_spr_rd_n    : out std_logic;\r
-        po_spr_wr_n    : out std_logic;\r
-        po_spr_addr    : out std_logic_vector (7 downto 0);\r
-        po_spr_data    : out std_logic_vector (7 downto 0)\r
-    );\r
-end apu;\r
-\r
-architecture rtl of apu is\r
-begin\r
-    pio_oe_n       <= 'Z';\r
-    pio_we_n       <= 'Z';\r
-    pio_cpu_addr   <= (others => 'Z');\r
-    pio_cpu_d      <= (others => 'Z');\r
-    po_rdy         <= '1';\r
-    po_spr_ce_n    <= 'Z';\r
-    po_spr_rd_n    <= 'Z';\r
-    po_spr_wr_n    <= 'Z';\r
-    po_spr_addr    <= (others => 'Z');\r
-    po_spr_data    <= (others => 'Z');\r
-end rtl;\r
-\r
+-------------dummy apu\r
+--library ieee;\r
+--use ieee.std_logic_1164.all;\r
+--use ieee.std_logic_arith.conv_std_logic_vector;\r
+--\r
+--entity apu is \r
+--    port (\r
+--        pi_rst_n       : in std_logic;\r
+--        pi_base_clk    : in std_logic;\r
+--        pi_cpu_en      : in std_logic_vector (7 downto 0);\r
+--        pi_rnd_en      : in std_logic_vector (3 downto 0);\r
+--        pi_ce_n        : in std_logic;\r
+--\r
+--        --cpu i/f\r
+--        pio_oe_n       : inout std_logic;\r
+--        pio_we_n       : inout std_logic;\r
+--        pio_cpu_addr   : inout std_logic_vector (15 downto 0);\r
+--        pio_cpu_d      : inout std_logic_vector (7 downto 0);\r
+--        po_rdy         : out std_logic;\r
+--\r
+--        --sprite i/f\r
+--        po_spr_ce_n    : out std_logic;\r
+--        po_spr_rd_n    : out std_logic;\r
+--        po_spr_wr_n    : out std_logic;\r
+--        po_spr_addr    : out std_logic_vector (7 downto 0);\r
+--        po_spr_data    : out std_logic_vector (7 downto 0)\r
+--    );\r
+--end apu;\r
+--\r
+--architecture rtl of apu is\r
+--begin\r
+--    pio_oe_n       <= 'Z';\r
+--    pio_we_n       <= 'Z';\r
+--    pio_cpu_addr   <= (others => 'Z');\r
+--    pio_cpu_d      <= (others => 'Z');\r
+--    po_rdy         <= '1';\r
+--    po_spr_ce_n    <= 'Z';\r
+--    po_spr_rd_n    <= 'Z';\r
+--    po_spr_wr_n    <= 'Z';\r
+--    po_spr_addr    <= (others => 'Z');\r
+--    po_spr_data    <= (others => 'Z');\r
+--end rtl;\r
+--\r

diff --git a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
index 22dcffd..5767387 100644 (file)
--- a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
+++ b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
@@ -171,9 +171,13 @@ view signals
 run 25 us\r
 wave zoom full\r
 \r
+#palette\r
 #run 16ms\r
 run 70 us\r
 \r
+#vram\r
+run 2000 us\r
+\r
+#sprite\r
 run 550 us\r
-#run 2000 us\r
 \r