- rol supported

- flag set bug fixed.

diff --git a/simulation/cpu/alu.vhd b/simulation/cpu/alu.vhd
index a3a335f..9a36d16 100644 (file)
--- a/simulation/cpu/alu.vhd
+++ b/simulation/cpu/alu.vhd
@@ -526,6 +526,14 @@ end procedure;
             set_nz;
             output_d_bus;
 
+        elsif instruction = conv_std_logic_vector(16#2a#, dsize) then
+            --rol acc.
+            sel <= ALU_ROL;
+            d1 <= acc_out;
+            set_nz;
+            carry_out <= c;
+            output_d_bus;
+
         elsif instruction = conv_std_logic_vector(16#4a#, dsize) then
             --lsr acc.
             sel <= ALU_LSR;
@@ -626,10 +634,16 @@ end procedure;
 
             if instruction (7 downto 5) = "000" then
                 d_print("asl");
+
             elsif instruction (7 downto 5) = "001" then
                 d_print("rol");
+                sel <= ALU_ROL;
+                set_nz;
+                carry_out <= c;
+
             elsif instruction (7 downto 5) = "010" then
                 d_print("lsr");
+
             elsif instruction (7 downto 5) = "011" then
                 --d_print("ror");
                 sel <= ALU_ROR;
@@ -892,7 +906,14 @@ end procedure;
         carry_out <= res(dsize);
 
     elsif sel = ALU_ROL then
-        ----
+        res(dsize - 1 downto 1) := d1(dsize - 2 downto 0);
+        res(0) := carry_in;
+
+        d_out <= res(dsize - 1 downto 0);
+        set_n(res(dsize - 1 downto 0));
+        set_z(res(dsize - 1 downto 0));
+        carry_out <= d1(7);
+
     elsif sel = ALU_ROR then
         res(dsize - 1) := carry_in;
         res(dsize - 2 downto 0) := d1(dsize - 1 downto 1);

diff --git a/simulation/cpu/decoder.vhd b/simulation/cpu/decoder.vhd
index 3f1317c..63ec7f2 100644 (file)
--- a/simulation/cpu/decoder.vhd
+++ b/simulation/cpu/decoder.vhd
@@ -322,17 +322,15 @@ end  procedure;
 procedure set_nz_from_bus is
 begin
     --status register n/z bit update.
-    stat_dec_oe_n <= '1';
-    status_reg <= "10000010";
     stat_bus_nz_n <= '0';
 end  procedure;
 
-procedure set_nzc_from_bus is
+procedure set_zc_from_alu is
 begin
-    --status register n,z,c bit update.
+    --status register n/z bit update.
+    stat_alu_we_n <= '0';
     stat_dec_oe_n <= '1';
-    status_reg <= "10000011";
-    stat_bus_nz_n <= '0';
+    status_reg <= "00000011";
 end  procedure;
 
 procedure set_nz_from_alu is
@@ -951,7 +949,7 @@ end  procedure;
                     arith_en_n <= '0';
                     back_oe(acc_cmd, '0');
                     front_we(acc_cmd, '0');
-                    set_nzc_from_bus;
+                    set_zc_from_alu;
                     single_inst;
 
                 elsif instruction = conv_std_logic_vector(16#ea#, dsize) then
@@ -961,6 +959,11 @@ end  procedure;
                 elsif instruction = conv_std_logic_vector(16#2a#, dsize) then
                     --rol acc
                     d_print("rol");
+                    arith_en_n <= '0';
+                    back_oe(acc_cmd, '0');
+                    front_we(acc_cmd, '0');
+                    set_nzc_from_alu;
+                    single_inst;
 
                 elsif instruction = conv_std_logic_vector(16#38#, dsize) then
                     d_print("sec");
@@ -1672,10 +1675,10 @@ end  procedure;
                 elsif instruction  = conv_std_logic_vector(16#66#, dsize) then
                     --zp
                     d_print("ror");
-                    a4_zp;
-                    if exec_cycle = T4 then
-                        set_nzc_from_bus;
-                    end if;
+--                    a4_zp;
+--                    if exec_cycle = T4 then
+--                        set_nzc_from_alu;
+--                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#76#, dsize) then
                     --zp, x

diff --git a/simulation/motones_sim.vhd b/simulation/motones_sim.vhd
index 2c6f46f..0ec8e9c 100644 (file)
--- a/simulation/motones_sim.vhd
+++ b/simulation/motones_sim.vhd
@@ -164,7 +164,7 @@ begin
     --nes ppu instance
     ppu_inst : ppu 
         port map (ppu_clk, ppu_ce_n, rst_n, r_nw, addr(2 downto 0), d_io, 
-                nmi_n2, rd_n, wr_n, ale, vram_ad, vram_a,
+                nmi_n, rd_n, wr_n, ale, vram_ad, vram_a,
                 vga_clk, h_sync_n, v_sync_n, r, g, b);
 
     ppu_addr_decoder : v_address_decoder generic map (size14, data_size) 
@@ -173,18 +173,18 @@ begin
     dummy_vga_disp : vga_device 
         port map (vga_clk, rst_n, h_sync_n, v_sync_n, r, g, b);
 
-    nmi_p: process
-    constant powerup_time : time := 5000 ns;
-    constant reset_time : time := 10 us;
-    begin
-        wait for powerup_time;
-        nmi_n  <= '1';
-        wait for reset_time;
-        wait for 46 us;
-        nmi_n  <= '0';
-
-        wait;
-    end process;
+--    nmi_p: process
+--    constant powerup_time : time := 5000 ns;
+--    constant reset_time : time := 10 us;
+--    begin
+--        wait for powerup_time;
+--        nmi_n  <= '1';
+--        wait for reset_time;
+--        wait for 46 us;
+--        nmi_n  <= '0';
+--
+--        wait;
+--    end process;
 
 end rtl;