simulation result broken by the unknown reason..., restored some of the codes.

diff --git a/tools/qt_proj_test5/vga.vhd b/tools/qt_proj_test5/vga.vhd
index e13451b..c08beb6 100644 (file)
--- a/tools/qt_proj_test5/vga.vhd
+++ b/tools/qt_proj_test5/vga.vhd
@@ -283,7 +283,6 @@ begin
         end if;\r
     end process;\r
 \r
-    --sw_write is mealy machine. (the state is decided by both the input and current state)\r
     sw_state_p : process (rst_n, sdram_clk)\r
     begin\r
         if (rst_n = '0') then\r
@@ -345,6 +344,7 @@ begin
 --            wbs_cyc_i        <= '0';\r
 --            wbs_stb_i        <= '0';\r
 --\r
+--               <= sw_idle;\r
 --            sr_state <= sr_idle;\r
 --            wait_cnt := SDRAM_READ_WAIT_CNT;\r
 --            \r
@@ -399,7 +399,7 @@ begin
 --            else\r
 --\r
 --                --write to sdram\r
---                case sw_state is\r
+--                case   is\r
 --                when sw_idle =>\r
 --                    --pop data from fifo first.\r
 ----                    sdram_addr_inc_n <= '1';\r
@@ -408,13 +408,20 @@ begin
 --                    \r
 --                    if (f_cnt = "00000000") then\r
 --                        --if fifo is empty, do nothing.\r
+--                        f_rd <= '0';\r
 --                        f_val_we_n <= '1';\r
 --                    else\r
+--                        f_rd <= '1';\r
+--                           <= sw_pop_fifo;\r
 --                        f_val_we_n <= '0';\r
 --                    end if;\r
 --                \r
 --                when sw_pop_fifo =>\r
+--                    f_rd <= '0';\r
 --                    f_val_we_n <= '1';\r
+--                       <= sw_write;\r
+--                    --     <= sw_idle;\r
+--                    \r
 --                \r
 ----                    --set fifo data to sdram.\r
 ----                    wbs_adr_i <= sdram_write_addr;\r
@@ -422,32 +429,38 @@ begin
 ----                    wbs_dat_i <= "0000" & f_val;\r
 --\r
 --                when sw_write =>\r
+--                    f_rd <= '0';\r
+--                       <= sw_write_ack;\r
 --\r
 ----                    wbs_cyc_i <= '1';\r
 ----                    wbs_stb_i <= '1';\r
 ----                    wbs_tga_i <= f_cnt;\r
 --                    \r
 --                when sw_write_ack =>\r
+--                    f_rd <= '0';\r
 --                    sdram_addr_inc_n <= '0';\r
 --                    if (f_emp = '0') then\r
---                        sw_state <= sw_write_burst;\r
+--                           <= sw_write_burst;\r
 --                    else\r
 --                        ---write finished.\r
---                        sw_state <= sw_idle;\r
+--                           <= sw_idle;\r
 --                    end if;\r
 --\r
 --                when sw_write_burst =>\r
+--                    f_rd <= '0';\r
 --                    wbs_adr_i <= sdram_write_addr;\r
 --                    --wbs_adr_i <= (others => '1');\r
 --                    wbs_dat_i <= "0000" & f_val;\r
 --                    if (f_emp = '0') then\r
---                        sw_state <= sw_write_burst;\r
+--                           <= sw_write_burst;\r
 --                    else\r
 --                        ---write finished.\r
---                        sw_state <= sw_idle;\r
+--                           <= sw_idle;\r
 --                    end if;\r
 --                \r
 --                when others =>\r
+--                    f_rd <= '0';\r
+--                       <= sw_idle;\r
 --                end case;\r
 --\r
 --                --for sdram read...\r