simulation minimum interval changed due to pll simulation

diff --git a/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do b/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do
index c4ea81c..64f2dc2 100644 (file)
--- a/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do
+++ b/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do
@@ -9,7 +9,7 @@ vcom -93 -work work {de1_nes.vho}
 \r
 vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/testbench_motones_sim.vhd}\r
 \r
-vsim -t 10ps +transport_int_delays +transport_path_delays -sdftyp /sim_board=de1_nes_vhd.sdo -L cycloneii -L gate_work -L work testbench_motones_sim\r
+vsim -t 1ps +transport_int_delays +transport_path_delays -sdftyp /sim_board=de1_nes_vhd.sdo -L cycloneii -L gate_work -L work testbench_motones_sim\r
 \r
 #add wave *\r
 \r

diff --git a/de1_nes/simulation/modelsim/motones_modelsim.mpf b/de1_nes/simulation/modelsim/motones_modelsim.mpf
index a1bdd0e..d5b1180 100644 (file)
--- a/de1_nes/simulation/modelsim/motones_modelsim.mpf
+++ b/de1_nes/simulation/modelsim/motones_modelsim.mpf
@@ -127,7 +127,7 @@ cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
 hardcopyiv_hssi_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_hssi\r
 hardcopyiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_pcie_hip\r
 \r
-work = rtl_work\r
+work = gate_work\r
 [vcom]\r
 ; VHDL93 variable selects language version as the default. \r
 ; Default is VHDL-2002.\r