oam_bus_ce_n : in std_logic;
plt_bus_ce_n : in std_logic;
oam_plt_addr : in std_logic_vector (7 downto 0);
- oam_plt_data : inout std_logic_vector (7 downto 0)
+ oam_plt_data : inout std_logic_vector (7 downto 0);
+ v_bus_busy_n : out std_logic
);
end component;
signal ppu_addr_in : std_logic_vector (13 downto 0);
signal ppu_addr_cnt : std_logic_vector (0 downto 0);
signal ppu_data : std_logic_vector (dsize - 1 downto 0);
-signal read_data : std_logic;
+signal ppu_data_out : std_logic_vector (dsize - 1 downto 0);
+signal read_data_n : std_logic;
signal ppu_latch_rst_n : std_logic;
+signal v_bus_busy_n : std_logic;
signal oam_bus_ce_n : std_logic;
signal plt_bus_ce_n : std_logic;
pos_x, pos_y, nes_r, nes_g, nes_b,
ppu_ctrl, ppu_mask, read_status, ppu_status, ppu_scroll_x, ppu_scroll_y,
r_nw, oam_bus_ce_n, plt_bus_ce_n,
- oam_plt_addr, oam_plt_data);
+ oam_plt_addr, oam_plt_data, v_bus_busy_n);
vga_inst : vga_ctl port map (clk, vga_clk, rst_n,
pos_x, pos_y, nes_r, nes_g, nes_b,
ppu_data_inst : d_flip_flop generic map(dsize)
port map (clk_n, rst_n, '1', ppu_data_we_n, cpu_d, ppu_data);
+ ppu_data_out_inst : d_flip_flop generic map(dsize)
+ port map (clk_n, rst_n, '1', read_data_n, ppu_data, ppu_data_out);
+
reg_set_p : process (rst_n, ce_n, r_nw, cpu_addr, cpu_d,
ppu_status(ST_VBL), ppu_ctrl(PPUNEN))
ppu_addr_cnt_ce_n <= '1';
ppu_addr_we_n <= '1';
end if;
+
+ if (cpu_addr = PPUDATA and r_nw = '0') then
+ read_data_n <= '0';
+ else
+ read_data_n <= '1';
+ end if;
else
ppu_ctrl_we_n <= '1';
ppu_mask_we_n <= '1';
ppu_scroll_cnt_ce_n <= '1';
ppu_addr_we_n <= '1';
ppu_addr_cnt_ce_n <= '1';
-
read_status <= '0';
- read_data <= '0';
+ read_data_n <= '1';
end if; --if (rst_n = '1' and ce_n = '0')
end process;
if (cpu_addr = PPUDATA and ppu_clk_cnt = "00") then
ppu_data_we_n <= '0';
+ vram_a <= ppu_addr(13 downto 8);
if (ppu_addr(13 downto 8) = "111111") then
--case palette tbl.
plt_bus_ce_n <= '0';
oam_bus_ce_n : in std_logic;
plt_bus_ce_n : in std_logic;
oam_plt_addr : in std_logic_vector (7 downto 0);
- oam_plt_data : inout std_logic_vector (7 downto 0)
+ oam_plt_data : inout std_logic_vector (7 downto 0);
+ v_bus_busy_n : out std_logic
);
end ppu_render;
(cur_y < conv_std_logic_vector(VSCAN, X_SIZE) or
cur_y = conv_std_logic_vector(VSCAN_MAX - 1, X_SIZE)) else
'1';
+ v_bus_busy_n <= d_oe_n;
io_cnt_inst : counter_register generic map (1, 1)
port map (clk, cnt_x_res_n, '0', '1', (others => '0'), io_cnt);