pc increment and carry next page with alu ok.

diff --git a/simulation/cpu/alu.vhd b/simulation/cpu/alu.vhd
index b2044ce..c9ce3d5 100644 (file)
--- a/simulation/cpu/alu.vhd
+++ b/simulation/cpu/alu.vhd
@@ -99,6 +99,7 @@ end procedure;
     elsif sel = ALU_INC then
         res := ('0' & d1) + "000000001";
         d_out <= res(dsize - 1 downto 0);
+        carry_out <= res(dsize);
     elsif sel = ALU_DEC then
         res := ('0' & d1) - "000000001";
     end if;
@@ -121,7 +122,8 @@ entity alu is
     generic (   dsize : integer := 8
             );
     port (  clk             : in std_logic;
-            pc_inc_n        : in std_logic;
+            pcl_inc_n       : in std_logic;
+            pch_inc_n       : in std_logic;
             abs_ea_n        : in std_logic;
             zp_ea_n         : in std_logic;
             arith_en_n      : in std_logic;
@@ -136,6 +138,7 @@ entity alu is
             abh             : out std_logic_vector (dsize - 1 downto 0);
             pcl             : out std_logic_vector (dsize - 1 downto 0);
             pch             : out std_logic_vector (dsize - 1 downto 0);
+            pcl_inc_carry   : out std_logic;
             carry_in        : in std_logic;
             negative        : out std_logic;
             zero            : out std_logic;
@@ -207,6 +210,10 @@ signal d_out : std_logic_vector (dsize - 1 downto 0);
 signal bal_reg : std_logic_vector (dsize - 1 downto 0);
 signal bah_reg : std_logic_vector (dsize - 1 downto 0);
 
+signal n : std_logic;
+signal z : std_logic;
+signal c : std_logic;
+signal v : std_logic;
 begin
 
     bal_inst : d_flip_flop generic map (dsize) 
@@ -215,16 +222,27 @@ begin
             port map(clk, '1', '1', '1', bah, bah_reg);
 
     alu_inst : alu_core generic map (dsize)
-            port map (sel, d1, d2, d_out, 
-                    carry_in, negative, zero, carry_out, overflow);
+            port map (sel, d1, d2, d_out, carry_in, n, z, c, v);
 
-    alu_p : process (clk, pc_inc_n, abs_ea_n, zp_ea_n, arith_en_n, instruction, 
-                    int_d_bus, acc_out, index_bus, bal, bal, carry_in, d_out)
+    alu_p : process (clk, pcl_inc_n, pch_inc_n, abs_ea_n, zp_ea_n, arith_en_n, 
+                    instruction, 
+                    int_d_bus, acc_out, index_bus, bal, bal, carry_in, d_out, 
+                    n, z, c, v)
     begin
-    if (pc_inc_n = '0') then
+    if (pcl_inc_n = '0') then
         sel <= ALU_INC;
         d1 <= bal;
         pcl <= d_out;
+        pcl_inc_carry <= c;
+
+        abl <= bal;
+        abh <= bah;
+
+    elsif (pch_inc_n = '0') then
+        sel <= ALU_INC;
+        d1 <= bah;
+        pch <= d_out;
+        pcl_inc_carry <= '0';
 
         abl <= bal;
         abh <= bah;
@@ -296,7 +314,8 @@ begin
 
         abl <= bal;
         abh <= bah;
-    end if; --if (arith_en_n = '') then
+        pcl_inc_carry <= '0';
+    end if; --if (pcl_inc_n = '0') then
     end process;
 
 end rtl;

diff --git a/simulation/cpu/decoder.vhd b/simulation/cpu/decoder.vhd
index 00afdd5..46a3807 100644 (file)
--- a/simulation/cpu/decoder.vhd
+++ b/simulation/cpu/decoder.vhd
@@ -18,7 +18,8 @@ entity decoder is
             inst_we_n       : out std_logic;
             ad_oe_n         : out std_logic;
             dbuf_int_oe_n   : out std_logic;
-            pc_inc_n        : out std_logic;
+            pcl_inc_n       : out std_logic;
+            pch_inc_n       : out std_logic;
             pcl_cmd         : out std_logic_vector(3 downto 0);
             pch_cmd         : out std_logic_vector(3 downto 0);
             sp_cmd          : out std_logic_vector(3 downto 0);
@@ -54,38 +55,38 @@ end;
 
 --cycle bit format
 --00xxx : exec cycle : T0 > T1 > T2 > T3 > T4 > T5 > T6 > T7 > T0
-constant T0 : std_logic_vector (5 downto 0) := "-00000";
-constant T1 : std_logic_vector (5 downto 0) := "-00001";
-constant T2 : std_logic_vector (5 downto 0) := "-00010";
-constant T3 : std_logic_vector (5 downto 0) := "-00011";
-constant T4 : std_logic_vector (5 downto 0) := "-00100";
-constant T5 : std_logic_vector (5 downto 0) := "-00101";
-constant T6 : std_logic_vector (5 downto 0) := "-00110";
-constant T7 : std_logic_vector (5 downto 0) := "-00111";
+constant T0 : std_logic_vector (5 downto 0) := "000000";
+constant T1 : std_logic_vector (5 downto 0) := "000001";
+constant T2 : std_logic_vector (5 downto 0) := "000010";
+constant T3 : std_logic_vector (5 downto 0) := "000011";
+constant T4 : std_logic_vector (5 downto 0) := "000100";
+constant T5 : std_logic_vector (5 downto 0) := "000101";
+constant T6 : std_logic_vector (5 downto 0) := "000110";
+constant T7 : std_logic_vector (5 downto 0) := "000111";
 
 --01xxx : reset cycle : R0 > R1 > R2 > R3 > R4 > R5 > T0
-constant R0 : std_logic_vector (5 downto 0) := "-01000";
-constant R1 : std_logic_vector (5 downto 0) := "-01001";
-constant R2 : std_logic_vector (5 downto 0) := "-01010";
-constant R3 : std_logic_vector (5 downto 0) := "-01011";
-constant R4 : std_logic_vector (5 downto 0) := "-01100";
-constant R5 : std_logic_vector (5 downto 0) := "-01101";
+constant R0 : std_logic_vector (5 downto 0) := "001000";
+constant R1 : std_logic_vector (5 downto 0) := "001001";
+constant R2 : std_logic_vector (5 downto 0) := "001010";
+constant R3 : std_logic_vector (5 downto 0) := "001011";
+constant R4 : std_logic_vector (5 downto 0) := "001100";
+constant R5 : std_logic_vector (5 downto 0) := "001101";
 
 --10xxx : nmi cycle : N0 > N1 > N2 > N3 > N4 > N5 > T0
-constant N0 : std_logic_vector (5 downto 0) := "-10000";
-constant N1 : std_logic_vector (5 downto 0) := "-10001";
-constant N2 : std_logic_vector (5 downto 0) := "-10010";
-constant N3 : std_logic_vector (5 downto 0) := "-10011";
-constant N4 : std_logic_vector (5 downto 0) := "-10100";
-constant N5 : std_logic_vector (5 downto 0) := "-10101";
+constant N0 : std_logic_vector (5 downto 0) := "010000";
+constant N1 : std_logic_vector (5 downto 0) := "010001";
+constant N2 : std_logic_vector (5 downto 0) := "010010";
+constant N3 : std_logic_vector (5 downto 0) := "010011";
+constant N4 : std_logic_vector (5 downto 0) := "010100";
+constant N5 : std_logic_vector (5 downto 0) := "010101";
 
 --11xxx : irq cycle : I0 > I1 > I2 > I3 > I4 > I5 > T0
-constant I0 : std_logic_vector (5 downto 0) := "-11000";
-constant I1 : std_logic_vector (5 downto 0) := "-11001";
-constant I2 : std_logic_vector (5 downto 0) := "-11010";
-constant I3 : std_logic_vector (5 downto 0) := "-11011";
-constant I4 : std_logic_vector (5 downto 0) := "-11100";
-constant I5 : std_logic_vector (5 downto 0) := "-11101";
+constant I0 : std_logic_vector (5 downto 0) := "011000";
+constant I1 : std_logic_vector (5 downto 0) := "011001";
+constant I2 : std_logic_vector (5 downto 0) := "011010";
+constant I3 : std_logic_vector (5 downto 0) := "011011";
+constant I4 : std_logic_vector (5 downto 0) := "011100";
+constant I5 : std_logic_vector (5 downto 0) := "011101";
 
 constant ERROR_CYCLE : std_logic_vector (5 downto 0) := "111111";
 
@@ -144,17 +145,20 @@ end;
 
 procedure fetch_inst is
 begin
+    --fetch opcode and phc increment.
     ad_oe_n <= '0';
     back_oe(pcl_cmd, '0');
     back_oe(pch_cmd, '0');
     back_we(pcl_cmd, '0');
+    back_we(pch_cmd, '1');
+
     inst_we_n <= '0';
-    pc_inc_n <= '0';
+    pcl_inc_n <= '0';
     r_nw <= '1';
-    --pcl_inc_n <= '0';
 
     --disable the last opration pins.
     dbuf_int_oe_n <= '1';
+    pch_inc_n <= '1';
     sp_cmd <= "1111";
     acc_cmd <= "1111";
     x_cmd <= "1111";
@@ -167,7 +171,7 @@ procedure single_inst is
 begin
     back_oe(pcl_cmd, '1');
     back_oe(pch_cmd, '1');
-    pc_inc_n <= '1';
+    pcl_inc_n <= '1';
     next_cycle <= T0;
 end  procedure;
 
@@ -266,7 +270,7 @@ end  procedure;
             if exec_cycle = T0 then
                 --cycle #1
                 fetch_inst;
-                next_cycle <= T1;
+                --next_cycle <= T1;
 
             elsif exec_cycle = T1 or exec_cycle = T2 or exec_cycle = T3 or 
                 exec_cycle = T4 or exec_cycle = T5 or exec_cycle = T6 or 
@@ -955,7 +959,8 @@ end  procedure;
                 inst_we_n <= '1';
                 ad_oe_n <= '1';
                 dbuf_int_oe_n <= '1';
-                pc_inc_n <= '1';
+                pcl_inc_n <= '1';
+                pch_inc_n <= '1';
                 pcl_cmd <= "1111";
                 pch_cmd <= "1111";
                 sp_cmd <= "1111";
@@ -980,6 +985,16 @@ end  procedure;
             elsif exec_cycle = R5 then
                 next_cycle <= T0;
 
+            elsif exec_cycle(5) = '1' then
+                ---pc increment and next page.
+                d_print(string'("pch next page..."));
+                --pcl stop increment
+                pcl_inc_n <= '1';
+                back_we(pcl_cmd, '1');
+                --pch increment
+                pch_inc_n <= '0';
+                back_we(pch_cmd, '0');
+
             end if; --if exec_cycle = T0 then
 
         end if; --if (set_clk'event and set_clk = '1') 

diff --git a/simulation/cpu/mos6502.vhd b/simulation/cpu/mos6502.vhd
index 4de5f6e..61c4f41 100644 (file)
--- a/simulation/cpu/mos6502.vhd
+++ b/simulation/cpu/mos6502.vhd
@@ -39,7 +39,8 @@ component decoder
             inst_we_n       : out std_logic;
             ad_oe_n         : out std_logic;
             dbuf_int_oe_n   : out std_logic;
-            pc_inc_n        : out std_logic;
+            pcl_inc_n       : out std_logic;
+            pch_inc_n       : out std_logic;
             pcl_cmd         : out std_logic_vector(3 downto 0);
             pch_cmd         : out std_logic_vector(3 downto 0);
             sp_cmd          : out std_logic_vector(3 downto 0);
@@ -56,7 +57,8 @@ component alu
     generic (   dsize : integer := 8
             );
     port (  clk             : in std_logic;
-            pc_inc_n        : in std_logic;
+            pcl_inc_n       : in std_logic;
+            pch_inc_n       : in std_logic;
             abs_ea_n        : in std_logic;
             zp_ea_n         : in std_logic;
             arith_en_n      : in std_logic;
@@ -71,6 +73,7 @@ component alu
             abh             : out std_logic_vector (dsize - 1 downto 0);
             pcl             : out std_logic_vector (dsize - 1 downto 0);
             pch             : out std_logic_vector (dsize - 1 downto 0);
+            pcl_inc_carry   : out std_logic;
             carry_in        : in std_logic;
             negative        : out std_logic;
             zero            : out std_logic;
@@ -172,7 +175,9 @@ end component;
     signal dl_al_oe_n : std_logic;
     signal dl_ah_oe_n : std_logic;
 
-    signal pc_inc_n : std_logic;
+    signal pcl_inc_n : std_logic;
+    signal pch_inc_n : std_logic;
+    signal pcl_inc_carry : std_logic_vector(0 downto 0);
     signal abs_ea_n : std_logic;
     signal zp_ea_n : std_logic;
     signal arith_en_n : std_logic;
@@ -260,7 +265,8 @@ begin
                     inst_we_n, 
                     ad_oe_n, 
                     dbuf_int_oe_n,
-                    pc_inc_n,
+                    pcl_inc_n,
+                    pch_inc_n,
                     pcl_cmd,
                     pch_cmd,
                     sp_cmd,
@@ -273,7 +279,8 @@ begin
 
     alu_inst : alu generic map (dsize) 
             port map (trigger_clk, 
-                    pc_inc_n,
+                    pcl_inc_n,
+                    pch_inc_n,
                     abs_ea_n,
                     zp_ea_n,
                     arith_en_n,
@@ -288,6 +295,7 @@ begin
                     abh,
                     pcl_back,
                     pch_back,
+                    pcl_inc_carry(0),
                     alu_c_in,
                     alu_n,
                     alu_z,
@@ -296,8 +304,13 @@ begin
                     );
 
     --cpu execution cycle number
-    exec_cycle_inst : d_flip_flop generic map (6) 
-            port map(trigger_clk, '1', '1', '0', next_cycle, exec_cycle);
+    exec_cycle_inst : d_flip_flop generic map (5) 
+            port map(trigger_clk, '1', '1', '0', 
+                    next_cycle(4 downto 0), exec_cycle(4 downto 0));
+
+    exec_cycle_carry_inst : d_flip_flop generic map (1) 
+            port map(trigger_clk, '1', '1', '0', 
+                    pcl_inc_carry, exec_cycle(5 downto 5));
 
     --io data buffer
     dbus_buf : data_bus_buffer generic map (dsize)