VGADisplay/src/vga_generate.nsl

   1 /**
   2 *       VGA\81@Signal Generate Circuit
   3 *       Module name is "vga_generate"
   4 *       @auther Yujiro Kaneko
   5 *       @version 1.2
   6 */
   7
   8 #include "vga_ram.nsh"
   9
  10 %d CNT_H_00                     10'd0           /* for Initialize */
  11 %d CNT_H1                       10'd96          /* 96clock */
  12 %d CNT_H_REP32          10'd110         /* 110 clock */
  13 %d CNT_H_DATA_IN        10'd142         /* 142 for 144clock */
  14 %d CNT_H_DATA_OUT       10'd782         /* 782 for 784clock */
  15 %d CNT_H2                       10'd800         /* 800clock */
  16
  17 %d CNT_32                       5'b11111        /* 32dot */
  18
  19 %d H_MINUS_32           10'd1111100001          /* -31 */
  20 %d H_MINUS_1            10'b1111111111          /* -1 */
  21
  22 %d V_MINUS_32           19'b1111111111111100001 /* -32 */
  23 %d V_MINUS_1            19'b1111111111111111111 /* -1 */
  24
  25 %d CNT_V1                       19'd1599        /* 1600clock */
  26 %d CNT_V_DATA_IN        19'd24799       /* 24800clock */
  27 %d CNT_V_DATA_OUT       19'd408799      /* 408800clock */
  28 %d CNT_V2                       19'd416799      /* 416800clock */
  29
  30
  31 declare vga_generate  interface {
  32         // FIFO\81@interface
  33         input  i_50clk ;
  34         input  i_wdata1[32] ;
  35         input  i_wdata2[32] ;
  36
  37         func_in fi_vgaram_write1( i_wdata1 ) ;
  38         func_in fi_vgaram_write2( i_wdata2 ) ;
  39         func_in fi_fifo1_rst ;
  40         func_in fi_fifo2_rst ;
  41
  42         input  p_reset ;
  43         input  m_clock ;
  44         output o_v_sync ;
  45         output o_h_sync ;
  46         output o_vga_red[4] ;
  47         output o_vga_green[4] ;
  48         output o_vga_blue[4] ;
  49         output o_h_cnt[10] ;
  50
  51         output o_scanline[10] ;
  52
  53 //      func_in  fi_ack_req_32dot(i_pix32_data) ;
  54 //      func_out fo_req_32dot ;
  55
  56 }
  57 module vga_generate {
  58         func_self fs_disp_data ;
  59
  60         reg r_v_sync = 0 ;
  61         reg r_h_sync = 0 ;
  62
  63         reg r_vdata_flg = 0 ;
  64         reg r_hdata_flg = 0 ;
  65
  66         reg r_h_cnt[10] = 0 ;
  67         reg r_v_cnt[19] = 0 ;
  68
  69         reg r_bit32_cnt[5] = 0 ;
  70         reg r_flg = 0 ;
  71         reg r1[32] = 0 ;
  72         reg r2[32] = 0 ;
  73         reg r_data_select_flag = 0 ;
  74
  75         reg r_scanline_cnt[10] = 0 ;
  76
  77         wire w_red[4] ;
  78         wire w_green[4] ;
  79         wire w_blue[4] ;
  80         wire w_disp_data;
  81
  82         reg r_cnt_flg = 0 ;
  83         reg r_hld_h_sync = 0 ;
  84
  85         func_self vgaram_read1() ;
  86         func_self vgaram_read2() ;
  87
  88         vga_ram u_VGARAM ;
  89
  90         {
  91                 /* vga_top - vga_ram assign */
  92                 u_VGARAM.i_clock  = i_50clk ;
  93                 u_VGARAM.i_wdata1 = i_wdata1 ;
  94                 u_VGARAM.i_wdata2 = i_wdata2 ;
  95                 u_VGARAM.m_clock = m_clock ;
  96                 u_VGARAM.p_reset = p_reset ;
  97
  98
  99                 /* vga_top - vga_gen */
 100                 o_v_sync        = r_v_sync ;
 101                 o_h_sync        = r_h_sync ;
 102                 o_vga_red       = w_red ;
 103                 o_vga_green     = w_green ;
 104                 o_vga_blue  = w_blue ;
 105                 o_h_cnt         = r_h_cnt ;
 106
 107
 108                 /* y point counter */
 109                 o_scanline        = r_scanline_cnt ;
 110                 r_hld_h_sync := r_h_sync ;
 111
 112
 113                 if( r_v_sync ) {
 114                         if(r_h_sync & ~r_hld_h_sync) {
 115                                 if(~r_cnt_flg) {
 116                                         r_cnt_flg := 1 ;
 117                                 } else {
 118                                         r_scanline_cnt++ ;
 119                                 }
 120                         }
 121                 } else {
 122                         r_cnt_flg := 0 ;
 123                         r_scanline_cnt := 0 ;
 124                 }
 125
 126
 127                 //horizonal synchronous signal generate
 128                 any{
 129                         r_h_cnt == 10'd96 : {
 130                                 r_h_sync := ~r_h_sync;
 131                                 r_h_cnt++ ;
 132                         }
 133                         r_h_cnt == 10'd142 : {
 134                                 r_hdata_flg := 0b1;
 135                                 r_h_cnt++ ;
 136                         }
 137                         r_h_cnt == 10'd782 : {
 138                                 r_hdata_flg := 0b0;
 139                                 r_h_cnt++ ;
 140                         }
 141                         r_h_cnt == 10'd800 : {
 142                                 r_h_sync := ~r_h_sync;
 143                                 r_h_cnt  := 0 ;
 144                         }
 145                         else : {
 146                                 r_h_cnt++ ;
 147                         }
 148                 }
 149
 150                 //vartical synchronous signal generate
 151                 any{
 152                         r_v_cnt == CNT_V1 : {
 153                                 r_v_sync := ~r_v_sync;
 154                                 r_v_cnt++ ;
 155                         }
 156                         r_v_cnt == CNT_V_DATA_IN : {
 157                                 r_vdata_flg := 0b1;
 158                                 r_v_cnt++ ;
 159                         }
 160                         r_v_cnt == CNT_V_DATA_OUT : {
 161                                 r_vdata_flg := 0b0;
 162                                 r_v_cnt++ ;
 163                         }
 164                         r_v_cnt == CNT_V2 : {
 165                                 r_v_sync := ~r_v_sync;
 166                                 r_v_cnt  := 0 ;
 167                         }
 168                         else : {
 169                                 r_v_cnt++ ;
 170                         }
 171                 }
 172
 173                 //address counter
 174                 if( r_hdata_flg & r_vdata_flg ) fs_disp_data();
 175
 176                 //32dot request signal
 177                 any {
 178                         ((r_h_cnt >= (CNT_H_DATA_IN + H_MINUS_32)) &
 179                         (r_h_cnt <= (CNT_H_DATA_OUT + H_MINUS_32 + H_MINUS_1))) &
 180                         ((r_v_cnt >= (CNT_V_DATA_IN + V_MINUS_32)) &
 181                         (r_v_cnt <= (CNT_V_DATA_OUT + V_MINUS_32 + V_MINUS_1))) : {
 182                                 if(r_bit32_cnt == 0b00000) {
 183                                         any {
 184                                                 r_scanline_cnt[0] == 0 : vgaram_read1() ;
 185                                                 else                               : vgaram_read2() ;
 186                                         }
 187                                 }
 188                                 any {
 189                                         r_bit32_cnt == 0b11111 : r_bit32_cnt := 0b00000 ;
 190                                         else                     : r_bit32_cnt := r_bit32_cnt + 0b00001 ;
 191                                 }
 192                         }
 193                         else : r_bit32_cnt := 0b00000 ;
 194                 }
 195
 196                 if( vgaram_read1 ) {
 197                         u_VGARAM.i_re1 = 1 ;
 198                 } else {
 199                         u_VGARAM.i_re1 = 0 ;
 200                 }
 201
 202                 if( vgaram_read2 ) {
 203                         u_VGARAM.i_re2 = 1 ;
 204                 } else {
 205                         u_VGARAM.i_re2 = 0 ;
 206                 }
 207
 208                 if (r_hdata_flg & r_vdata_flg) {
 209 //                      w_red = 4'h0;
 210 //                      w_blue = 4'hF;
 211 //                      w_green = 4'h0;
 212
 213                         any {
 214                                 w_disp_data : {
 215                                         w_red   = 4'hF ;
 216                                         w_blue  = 4'hF ;
 217                                         w_green = 4'hF ;
 218                                 }
 219                                 ~w_disp_data : {
 220                                         w_red   = 4'hF ;
 221                                         w_blue  = 4'h0 ;
 222                                         w_green = 4'h0 ;
 223                                 }
 224                         }
 225
 226                 } else {
 227                         w_red   = 4'h0 ;
 228                         w_blue  = 4'h0 ;
 229                         w_green = 4'h0 ;
 230                 }
 231
 232         }//par end
 233
 234 /*
 235         func fi_ack_req_32dot {
 236                 r_data_select_flag := ~r_data_select_flag ;
 237                 any{
 238                         r_data_select_flag : r1 := i_pix32_data ;
 239                         else                       : r2 := i_pix32_data ;
 240                 }
 241         }
 242 */
 243
 244
 245
 246         if ( u_VGARAM.o_rdack1 & u_VGARAM.o_rdack2 ) {
 247                 r_data_select_flag := ~r_data_select_flag ;
 248                 any{
 249                         r_data_select_flag : r1 := u_VGARAM.o_rddata1 ;
 250                         else                       : r2 := u_VGARAM.o_rddata2 ;
 251                 }
 252         }
 253
 254         func fi_vgaram_write1 {
 255                 u_VGARAM.i_we1 = 1 ;
 256         }
 257
 258         func fi_vgaram_write2 {
 259                 u_VGARAM.i_we2 = 1 ;
 260         }
 261
 262         func fi_fifo1_rst {
 263                 u_VGARAM.i_fifo1_rst = 1 ;
 264         }
 265
 266         func fi_fifo2_rst {
 267                 u_VGARAM.i_fifo2_rst = 1 ;
 268         }
 269
 270         func fs_disp_data {
 271                 any{
 272                         ~r_flg : any{
 273                                 r_bit32_cnt == 0b00000 : w_disp_data = r1[31] ;
 274                                 r_bit32_cnt == 0b00001 : w_disp_data = r1[30] ;
 275                                 r_bit32_cnt == 0b00010 : w_disp_data = r1[29] ;
 276                                 r_bit32_cnt == 0b00011 : w_disp_data = r1[28] ;
 277                                 r_bit32_cnt == 0b00100 : w_disp_data = r1[27] ;
 278                                 r_bit32_cnt == 0b00101 : w_disp_data = r1[26] ;
 279                                 r_bit32_cnt == 0b00110 : w_disp_data = r1[25] ;
 280                                 r_bit32_cnt == 0b00111 : w_disp_data = r1[24] ;
 281                                 r_bit32_cnt == 0b01000 : w_disp_data = r1[23] ;
 282                                 r_bit32_cnt == 0b01001 : w_disp_data = r1[22] ;
 283                                 r_bit32_cnt == 0b01010 : w_disp_data = r1[21] ;
 284                                 r_bit32_cnt == 0b01011 : w_disp_data = r1[20] ;
 285                                 r_bit32_cnt == 0b01100 : w_disp_data = r1[19] ;
 286                                 r_bit32_cnt == 0b01101 : w_disp_data = r1[18] ;
 287                                 r_bit32_cnt == 0b01110 : w_disp_data = r1[17] ;
 288                                 r_bit32_cnt == 0b01111 : w_disp_data = r1[16] ;
 289                                 r_bit32_cnt == 0b10000 : w_disp_data = r1[15] ;
 290                                 r_bit32_cnt == 0b10001 : w_disp_data = r1[14] ;
 291                                 r_bit32_cnt == 0b10010 : w_disp_data = r1[13] ;
 292                                 r_bit32_cnt == 0b10011 : w_disp_data = r1[12] ;
 293                                 r_bit32_cnt == 0b10100 : w_disp_data = r1[11] ;
 294                                 r_bit32_cnt == 0b10101 : w_disp_data = r1[10] ;
 295                                 r_bit32_cnt == 0b10110 : w_disp_data = r1[9] ;
 296                                 r_bit32_cnt == 0b10111 : w_disp_data = r1[8] ;
 297                                 r_bit32_cnt == 0b11000 : w_disp_data = r1[7] ;
 298                                 r_bit32_cnt == 0b11001 : w_disp_data = r1[6] ;
 299                                 r_bit32_cnt == 0b11010 : w_disp_data = r1[5] ;
 300                                 r_bit32_cnt == 0b11011 : w_disp_data = r1[4] ;
 301                                 r_bit32_cnt == 0b11100 : w_disp_data = r1[3] ;
 302                                 r_bit32_cnt == 0b11101 : w_disp_data = r1[2] ;
 303                                 r_bit32_cnt == 0b11110 : w_disp_data = r1[1] ;
 304                                 r_bit32_cnt == 0b11111 : {
 305                                                                            w_disp_data = r1[0] ;
 306                                                                            r_flg := ~r_flg ;
 307                                 }
 308                         }
 309                         else : any{
 310                                 r_bit32_cnt == 0b00000 : w_disp_data = r2[31] ;
 311                                 r_bit32_cnt == 0b00001 : w_disp_data = r2[30] ;
 312                                 r_bit32_cnt == 0b00010 : w_disp_data = r2[29] ;
 313                                 r_bit32_cnt == 0b00011 : w_disp_data = r2[28] ;
 314                                 r_bit32_cnt == 0b00100 : w_disp_data = r2[27] ;
 315                                 r_bit32_cnt == 0b00101 : w_disp_data = r2[26] ;
 316                                 r_bit32_cnt == 0b00110 : w_disp_data = r2[25] ;
 317                                 r_bit32_cnt == 0b00111 : w_disp_data = r2[24] ;
 318                                 r_bit32_cnt == 0b01000 : w_disp_data = r2[23] ;
 319                                 r_bit32_cnt == 0b01001 : w_disp_data = r2[22] ;
 320                                 r_bit32_cnt == 0b01010 : w_disp_data = r2[21] ;
 321                                 r_bit32_cnt == 0b01011 : w_disp_data = r2[20] ;
 322                                 r_bit32_cnt == 0b01100 : w_disp_data = r2[19] ;
 323                                 r_bit32_cnt == 0b01101 : w_disp_data = r2[18] ;
 324                                 r_bit32_cnt == 0b01110 : w_disp_data = r2[17] ;
 325                                 r_bit32_cnt == 0b01111 : w_disp_data = r2[16] ;
 326                                 r_bit32_cnt == 0b10000 : w_disp_data = r2[15] ;
 327                                 r_bit32_cnt == 0b10001 : w_disp_data = r2[14] ;
 328                                 r_bit32_cnt == 0b10010 : w_disp_data = r2[13] ;
 329                                 r_bit32_cnt == 0b10011 : w_disp_data = r2[12] ;
 330                                 r_bit32_cnt == 0b10100 : w_disp_data = r2[11] ;
 331                                 r_bit32_cnt == 0b10101 : w_disp_data = r2[10] ;
 332                                 r_bit32_cnt == 0b10110 : w_disp_data = r2[9] ;
 333                                 r_bit32_cnt == 0b10111 : w_disp_data = r2[8] ;
 334                                 r_bit32_cnt == 0b11000 : w_disp_data = r2[7] ;
 335                                 r_bit32_cnt == 0b11001 : w_disp_data = r2[6] ;
 336                                 r_bit32_cnt == 0b11010 : w_disp_data = r2[5] ;
 337                                 r_bit32_cnt == 0b11011 : w_disp_data = r2[4] ;
 338                                 r_bit32_cnt == 0b11100 : w_disp_data = r2[3] ;
 339                                 r_bit32_cnt == 0b11101 : w_disp_data = r2[2] ;
 340                                 r_bit32_cnt == 0b11110 : w_disp_data = r2[1] ;
 341                                 r_bit32_cnt == 0b11111 : {
 342                                                                            w_disp_data = r2[0] ;
 343                                                                            r_flg := ~r_flg ;
 344                                 }
 345                         }
 346                 }
 347                 r_bit32_cnt++ ;
 348         } //disp_data
 349 } //module end