SDRAM設計開始

[oca1/test.git] / VGADisplay / Verilog / vram.v

diff --git a/VGADisplay/Verilog/vram.v b/VGADisplay/Verilog/vram.v
index 0df1f25..ff13b0a 100644 (file)
--- a/VGADisplay/Verilog/vram.v
+++ b/VGADisplay/Verilog/vram.v
@@ -1,6 +1,6 @@
 /*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Jul 20 21:25:22 2011\r
- Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Sep 21 22:08:08 2011\r
+ Licensed to Yujiro_Kaneko::zyangalianhamster01@gmail.com :NON PROFIT USER:\r
 */\r
 \r
 module vram ( p_reset , m_clock , clock , data , rdaddress , wraddress , wren , q );\r
@@ -15,18 +15,19 @@ module vram ( p_reset , m_clock , clock , data , rdaddress , wraddress , wren ,
   reg [7:0] r_ram_data;\r
 \r
    assign  q = r_ram_data;\r
-always @(posedge clock)\r
+always @(posedge m_clock)\r
   begin\r
    if (wren )\r
      m_vram[wraddress] <= data;\r
 end\r
-always @(posedge clock)\r
-       begin\r
-               r_ram_data <= m_vram[rdaddress];\r
-       end\r
+always @(posedge m_clock or posedge p_reset)\r
+  begin\r
+if (p_reset)\r
+     r_ram_data <= 8'b00000000;\r
+else   r_ram_data <= m_vram[rdaddress];\r
+end\r
 endmodule\r
-\r
 /*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Jul 20 21:25:23 2011\r
- Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Sep 21 22:08:09 2011\r
+ Licensed to Yujiro_Kaneko::zyangalianhamster01@gmail.com \r
 */\r