Merge remote branch 'origin/master'

diff --git a/VGADisplay/src/memo b/VGADisplay/src/memo
index e16ba19..642d458 100644 (file)
--- a/VGADisplay/src/memo
+++ b/VGADisplay/src/memo
@@ -21,5 +21,5 @@ output q[8];
 \r
 VHDL VerilogHDL\82Ì\83v\83\89\83O\83C\83\93\82ð\82¢\82ê\82Ä\82¨\82­\81B\r
 \r
-1. \89¼\91z\83\81\83\82\83\8a\82Æexp_ctrl\82ð\83e\83X\83g\r
+1.\89¼\91z\83\81\83\82\83\8a\82Æexp_ctrl\82ð\83e\83X\83g\r
 \82Q\81D\83\81\83\82\83\8a\8eÀ\8b@\83e\83X\83g
\ No newline at end of file

diff --git a/VGADisplay/src/top.nsl b/VGADisplay/src/top.nsl
deleted file mode 100644 (file)
index 714bc47..0000000
--- a/VGADisplay/src/top.nsl
+++ /dev/null
@@ -1,64 +0,0 @@
-#define SIM\r
-\r
-#include "vga_generate.nsl"\r
-#include "exp_ctrl.nsl"\r
-\r
-#define ONE_SEC 25'd50000000\r
-\r
-declare vga_top {\r
-       output v_sync_o ;\r
-       output h_sync_o ;\r
-       output vga_red_o[4] ;\r
-       output vga_green_o[4] ;\r
-       output vga_blue_o[4] ;\r
-}\r
-module vga_top {\r
-       integer i ;\r
-\r
-       reg cnt = 0 ;\r
-       reg reset[3] = 0b111 ;\r
-       reg line_cnt[7] = 0 ;\r
-       reg vram_adrs_cnt[14] = 0 ;\r
-       reg rSec_cnt[25] = 0 ;\r
-       \r
-       mem line_buff1[80][8] ;\r
-       mem line_buff2[80][8] ;\r
-\r
-       func_self vga_sys_init ;\r
-\r
-       vga_generate U_VGA ;\r
-       exp_ctrl U_EXP ;\r
-       \r
-       U_VGA.pix32_data_i = 32'd0 ;\r
-       \r
-       v_sync_o        = U_VGA.v_sync_o ;\r
-       h_sync_o        = U_VGA.h_sync_o ;\r
-       vga_red_o       = U_VGA.vga_red_o ;\r
-       vga_green_o = U_VGA.vga_green_o ;\r
-       vga_blue_o      = U_VGA.vga_blue_o ;\r
-\r
-       {\r
-               cnt := ~cnt ;\r
-\r
-               reset := { reset[1:0], 0b0 } ;\r
-\r
-               U_VGA.p_reset = reset[2] ;\r
-               U_VGA.m_clock = cnt ;\r
-       \r
-               any {\r
-                       rSec_cnt == ONE_SEC : {\r
-                               \r
-                               rSec_cnt := 0 ;\r
-                       }\r
-                       else : {\r
-                               rSec_cnt++ ;\r
-                       }\r
-               }\r
-       }\r
-       \r
-       func vga_sys_init seq {\r
-//             for(line_cnt:=0;line_cnt<80;line_cnt++) {\r
-//                     line_buff1[line_cnt] := \r
-//             }\r
-       }\r
-}
\ No newline at end of file

diff --git a/VGADisplay/src/vga_generate.nsl b/VGADisplay/src/vga_generate.nsl
index 9d5d0fc..5af645d 100644 (file)
--- a/VGADisplay/src/vga_generate.nsl
+++ b/VGADisplay/src/vga_generate.nsl
@@ -160,8 +160,8 @@ module vga_generate {
 
                if (hdata_flg & vdata_flg) {
                        red = 4'h0;
-                       blue = 4'h0;
-                       green = 4'hF;
+                       blue = 4'hF;
+                       green = 4'h0;
 
 /*
                        any {
@@ -175,8 +175,8 @@ module vga_generate {
                                        blue    = 4'h0 ;
                                        green   = 4'h0 ;
                                }
-*/
                        }
+*/
                } else {
                        red             = 4'h0 ;
                        blue    = 4'h0 ;

diff --git a/VGADisplay/src/vga_top.nsl b/VGADisplay/src/vga_top.nsl
new file mode 100644 (file)
index 0000000..f2622be
--- /dev/null
+++ b/VGADisplay/src/vga_top.nsl
@@ -0,0 +1,105 @@
+#define SIM\r
+\r
+#include "vga_generate.nsl"\r
+#include "exp_ctrl.nsh"\r
+\r
+// #define ONE_SEC 25'd50000000\r
+#define ONE_SEC 25'd100\r
+\r
+\r
+declare vga_top {\r
+       output v_sync_o ;\r
+       output h_sync_o ;\r
+       output vga_red_o[4] ;\r
+       output vga_green_o[4] ;\r
+       output vga_blue_o[4] ;\r
+       \r
+       output oLED[8] ;\r
+}\r
+module vga_top {\r
+       integer i ;\r
+\r
+       reg cnt = 0 ;\r
+       reg reset[3] = 0b111 ;\r
+       reg line_cnt[15] = 0 ;\r
+       reg line_cnt2[14] = 0 ;\r
+       reg vram_adrs_cnt[14] = 0 ;\r
+       reg rSec_cnt[25] = 0 ;\r
+       reg rInit_flag = 0 ;\r
+       reg rLED[8] = 0 ;\r
+       reg test_LED = 0 ;\r
+       \r
+       mem line_buff1[80][8] ;\r
+       mem line_buff2[80][8] ;\r
+\r
+       func_self vga_sys_init ;\r
+\r
+       vga_generate U_VGA ;\r
+       exp_ctrl U_EXP ;\r
+       \r
+       v_sync_o        = U_VGA.v_sync_o ;\r
+       h_sync_o        = U_VGA.h_sync_o ;\r
+       vga_red_o       = U_VGA.vga_red_o ;\r
+       vga_green_o = U_VGA.vga_green_o ;\r
+       vga_blue_o      = U_VGA.vga_blue_o ;\r
+\r
+       if( U_VGA.req_32dot ) {\r
+               U_VGA.ack_req_32dot( 32'hFFFFFFFF ) ;\r
+       }\r
+\r
+       {\r
+               cnt := ~cnt ;\r
+               oLED = rLED ;\r
+\r
+               reset := { reset[1:0], 0b0 } ;\r
+               if( reset == 0b100 ) vga_sys_init() ;\r
+\r
+               U_VGA.p_reset = reset[2] ;\r
+               U_VGA.m_clock = cnt ;\r
+               \r
+               if( U_EXP.foRd_ack ) {\r
+                       rLED := {\r
+//                             U_EXP.oRdata[14],\r
+                               U_EXP.oRdata[12],\r
+                               U_EXP.oRdata[10],\r
+                               U_EXP.oRdata[8],\r
+                               U_EXP.oRdata[6],\r
+                               U_EXP.oRdata[4],\r
+                               U_EXP.oRdata[2],\r
+                               U_EXP.oRdata[0],\r
+                               test_LED\r
+                       } ;\r
+               }\r
+       \r
+               if( rInit_flag ) {\r
+                       any {\r
+                               rSec_cnt == ONE_SEC : {\r
+                                       U_EXP.fiRd_req( line_cnt2 ) ;\r
+                                       rSec_cnt := 0 ;\r
+                                       test_LED := ~test_LED ;\r
+                                       any {\r
+                                               line_cnt2 == 14'd1000 : line_cnt2 := 0 ;\r
+                                               else : line_cnt2++ ;\r
+                                       }\r
+                               }\r
+                               else : {\r
+                                       rSec_cnt++ ;\r
+                               }\r
+                       }\r
+               } else {\r
+                       rSec_cnt := 0 ;\r
+               }\r
+       }\r
+       \r
+       func vga_sys_init seq {\r
+//             for(line_cnt=0;line_cnt<80;line_cnt++) {\r
+//                     line_buff1[line_cnt] := \r
+//             }\r
+\r
+               for( line_cnt:=0; line_cnt<16384; line_cnt++ ) {\r
+                       U_EXP.fiWr_req( line_cnt, line_cnt[7:0] ) ;\r
+               }\r
+               \r
+               rInit_flag := 1 ;\r
+       }\r
+}
\ No newline at end of file