PIE1bits.TX1IE = 0;
PIE1bits.RC1IE = 1;
uart_rx_wakeup = 0;
+ UART_CTSOUT = 0;
SPBRGH = UART_BAUD_FACTOR / 256;
SPBRG = UART_BAUD_FACTOR % 256;
}
TXSTA = 0b00100100; //8bit, ASYNC, TXEN, Break, BRGH=1
PIE1bits.TX1IE = 0;
PIE1bits.RC1IE = 1;
-// uart_rx_wakeup = 0xff;
+ UART_CTSOUT = 0;
+ // uart_rx_wakeup = 0xff;
SPBRGH = UART_BAUD_FACTOR / 256;
SPBRG = UART_BAUD_FACTOR % 256;
}
if(RCSTAbits.OERR == 0) {
if(RCSTAbits.FERR == 0) {
uart_rx_sts = 0; // Clear error
-// c = RCREG;
- if(c == UART_CH_XOFF) {
- uart_tx_xon = 0; // XOFF Sequence for TX
- } else if(c == UART_CH_XON) { // XON Sequence for TX
- uart_tx_xon = 0xff;
- } else if(uart_rx_bytes < UART_BUF_SIZE) { //
- uart_rfifo[uart_rx_wptr++] = c;
- if(uart_rx_wptr >= UART_BUF_SIZE) uart_rx_wptr = 0;
- uart_rx_bytes++;
- if(uart_rx_bytes >= UART_BUF_SIZE) uart_rx_bytes = UART_BUF_SIZE;
- if((uart_rx_xon != 0) && (uart_rx_bytes >= ((UART_BUF_SIZE * 7) / 10))) {
- uart_pushxoff(100);
- uart_rx_xon = 0;
- }
-
-// uart_pushchar(c, 0x0000);
- }// else {
- // If overflow, discard.
- //}
-
+ uart_rfifo[uart_rx_wptr] = c;
+ uart_rx_wptr++;
+ if(uart_rx_wptr >= UART_BUF_SIZE) uart_rx_wptr = 0;
+ uart_rx_bytes++;
+ if(uart_rx_bytes >= UART_BUF_SIZE) uart_rx_bytes = UART_BUF_SIZE;
+ if((uart_rx_xon != 0) && (uart_rx_bytes >= ((UART_BUF_SIZE * 8) / 10))) { // Buffer will be full
+ UART_CTSOUT = 1; // OFF
+ uart_rx_xon = 0;
+ }
} else { // Frame Error
uart_rx_sts != UART_FRAMEERROR;
}
if(uart_rx_rptr > UART_BUF_SIZE) uart_rx_rptr = 0;
uart_rx_bytes--;
if(uart_rx_bytes <= 0) uart_rx_bytes = 0;
- if((uart_rx_xon == 0) && (uart_rx_bytes < ((UART_BUF_SIZE * 7) / 10))) {
- uart_pushxon(100);
+ if((uart_rx_xon == 0) && (uart_rx_bytes < ((UART_BUF_SIZE * 3) / 10))) { // Buffer will be empty
+ UART_CTSOUT = 0; // ON
uart_rx_xon = 0xff;
}
return c;
unsigned int i;
if(timeout != 0){
for(i = timeout; i > 0; i--){
- if((uart_tx_xon != 0) && (TXSTAbits.TRMT1 == 1)) break;
+ if((UART_RTSIN == 0) && (TXSTAbits.TRMT1 == 1)) break;
idle(100);
}
if(i != 0) goto _l1; // Send and return;
return UART_TIMEOUT; // Timeout
}
- if((TXSTAbits.TRMT1 == 0) || (uart_tx_xon == 0)) return UART_TIMEOUT; // If timeout=0 return immidiately.
+ if((TXSTAbits.TRMT1 == 0) || (UART_RTSIN != 0)) return UART_TIMEOUT; // If timeout=0 return immidiately.
_l1:
TXREG = c;
return 0;
void uart_pushxon(unsigned int timeout)
{
unsigned int i;
- if(uart_rx_wakeup == 0) return;
+#if 0
+ if(uart_rx_wakeup == 0) return;
if(timeout != 0) {
for(i = timeout; i > 0; i--){
if(TXSTAbits.TRMT1 == 1) break;
} else {
while(TXSTAbits.TRMT1 == 0) idle(100);
}
- TXREG = UART_CH_XON;
+#endif
+ // TXREG = UART_CH_XON;
+ UART_CTSOUT = 0;
}
void uart_pushxoff(unsigned int timeout)
{
unsigned int i;
- if(uart_rx_wakeup == 0) return;
+#if 0
+ if(uart_rx_wakeup == 0) return;
if(timeout != 0) {
for(i = timeout; i > 0; i--){
if(TXSTAbits.TRMT1 == 1) break;
} else {
while(TXSTAbits.TRMT1 == 0) idle(100);
}
- TXREG = UART_CH_XOFF;
+#endif
+ // TXREG = UART_CH_XOFF;
+ UART_CTSOUT = 1;
}
void uart_break(void)
value=470
}
C 47700 49100 1 0 0 gnd-2.sym
-N 50600 48000 53200 48000 4
-N 53200 48000 53200 49500 4
-N 53200 49500 55100 49500 4
+N 50600 48000 52200 48000 4
+N 52200 48000 52200 49500 4
+N 52200 49500 55100 49500 4
N 50600 45000 55500 45000 4
N 55500 45000 55500 45600 4
N 55500 45600 56200 45600 4
N 56200 44800 50600 44800 4
N 50600 44800 50600 44700 4
N 50600 45600 53200 45600 4
-N 52600 50400 55100 50400 4
-C 53700 48400 1 0 0 gnd-2.sym
+N 52000 50400 55100 50400 4
+C 53700 48600 1 0 0 gnd-2.sym
N 55100 49800 53800 49800 4
-N 53800 49800 53800 48700 4
+N 53800 49800 53800 48900 4
T 56400 48500 9 10 1 0 0 0 1
ICSP
T 56500 46900 9 10 1 0 0 0 1
T 52700 42900 5 10 1 1 0 1 1
value=SDA
}
-C 43300 42300 1 180 0 io-1.sym
+C 43200 42300 1 180 0 io-1.sym
{
-T 42500 42200 5 10 1 1 180 0 1
+T 42800 42000 5 10 1 1 180 0 1
net=SCL
-T 43100 41700 5 10 0 0 180 0 1
+T 43000 41700 5 10 0 0 180 0 1
device=none
-T 42400 42200 5 10 0 1 180 1 1
+T 42300 42200 5 10 0 1 180 1 1
value=SCL
}
N 50600 42900 51900 42900 4
{
T 52700 44000 5 10 0 0 0 6 1
device=INPUT
-T 52700 43800 5 10 1 1 0 0 1
+T 52700 43700 5 10 1 1 0 0 1
net=UART_RX
}
C 51900 43400 1 0 0 output-1.sym
{
T 52000 43700 5 10 0 0 0 0 1
device=OUTPUT
-T 52700 43500 5 10 1 1 0 0 1
+T 52700 43400 5 10 1 1 0 0 1
net=UART_TX
}
N 50600 43800 51900 43800 4
T 51500 40100 9 10 1 0 0 0 1
9
T 53900 40400 9 10 1 0 0 0 1
-2.03
+2.04
T 53900 40000 9 10 1 0 0 0 2
K.Ohta
<whatisthis.sowhat@gmail.com>
T 55900 40400 9 10 1 0 0 0 1
-Nov 09,2013
+Nov 14,2013
G 55500 40772 1500 528 0 0 0
/home/whatisthis/Bunsho/001_回路図/OpenI2CRadio/by-sa.png
U 53400 48600 43600 48600 10 0
T 42200 49800 5 10 1 1 0 0 1
model-name=1SS196
}
-N 45200 49000 52600 49000 4
+N 45200 49000 52000 49000 4
N 44200 49500 42000 49500 4
N 43100 49400 43100 49500 4
C 41300 44100 1 270 0 busripper-1.sym
T 44600 41100 5 10 1 1 0 0 1
net=AKC_TUNLED
}
-N 52600 49000 52600 50400 4
+N 52000 49000 52000 50400 4
C 45300 49500 1 90 0 resistor-1.sym
{
T 44900 49800 5 10 0 0 90 0 1
{
T 54300 47700 5 10 0 0 180 0 1
device=RESISTOR
-T 54000 48300 5 10 1 1 0 0 1
+T 53900 48400 5 10 1 1 0 0 1
refdes=R10
T 54300 48300 5 10 1 1 180 0 1
value=22K
T 48900 48800 5 10 0 1 0 0 1
net=Vdd:1
}
-C 52400 48800 1 180 0 busripper-1.sym
+C 53000 48800 1 180 0 busripper-1.sym
{
-T 52400 48400 5 8 0 0 180 0 1
+T 53000 48400 5 8 0 0 180 0 1
device=none
-T 52200 48400 5 10 1 1 0 0 1
+T 53100 48800 5 10 1 1 0 0 1
net=VDD
-T 52400 48800 5 10 0 1 0 0 1
+T 53000 48800 5 10 0 1 0 0 1
net=Vdd:1
}
C 53200 45600 1 0 0 busripper-1.sym
}
N 53200 45300 50600 45300 4
N 50900 50100 55100 50100 4
-N 52400 50100 52400 48800 4
N 48900 48800 48900 50300 4
N 46200 50300 49100 50300 4
C 47000 49400 1 90 0 capacitor-1.sym
N 44800 42300 45200 42300 4
N 45200 43200 43200 43200 4
N 43200 43200 43200 42800 4
-N 45200 42900 43300 42900 4
-N 43300 42900 43300 42200 4
+N 45200 42900 43400 42900 4
+N 43400 42900 43400 42200 4
N 45200 43800 43200 43800 4
N 43200 43800 43200 43400 4
C 45200 42000 1 0 0 PIC18F46K20_DIP40.sym
N 43400 47600 43200 47600 4
N 43200 47600 43200 47300 4
N 43200 46400 43200 45600 4
-T 50900 43100 9 10 1 0 0 0 1
-※9
+T 53700 43000 9 10 1 0 0 0 1
+※11
T 51000 47800 9 10 1 0 0 0 1
※9
T 42800 47300 9 10 1 0 0 0 1
N 54600 48000 55700 48000 4
N 54700 48000 54700 50100 4
N 53700 48000 53700 47100 4
-N 50900 48800 53500 48800 4
-N 55100 49200 53500 49200 4
-N 53500 49200 53500 48800 4
+N 50900 48800 52500 48800 4
+N 55100 49200 52500 49200 4
+N 52500 49200 52500 48800 4
N 51600 49200 51600 43800 4
T 51500 50600 9 10 1 0 0 0 1
※10
T 51600 43600 9 10 1 0 0 0 1
※10
+T 47700 40300 9 10 1 0 0 0 1
+※11 2013-11-14
+N 53000 48800 53000 50100 4
+N 43400 42200 43200 42200 4
+T 50600 43300 9 10 1 0 0 0 1
+CTS OUT
+T 50600 42700 9 10 1 0 0 0 1
+RTS IN
+C 52700 42700 1 180 0 input-1.sym
+{
+T 52700 42400 5 10 0 0 180 0 1
+device=INPUT
+T 52700 42500 5 10 1 1 0 0 1
+net=UART_RTS
+}
+N 51900 42600 50600 42600 4
+C 51900 43100 1 0 0 output-1.sym
+{
+T 52000 43400 5 10 0 0 0 0 1
+device=OUTPUT
+T 52700 43100 5 10 1 1 0 0 1
+net=UART_CTS
+}
+T 53800 42600 9 10 1 0 0 0 1
+※11
+N 51900 43200 50600 43200 4
T 47700 40500 9 10 1 0 0 0 1
※10 2013-11-09