1 /* CPU class elements for arm.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 2000-2009 Red Hat, Inc.
7 This file is part of the Red Hat simulators.
12 // This file is included in the middle of the cpu class struct.
16 // CPU state information.
20 /* ARM program counter (h-gr reg 15) */
22 /* General purpose registers */
24 /* user/system mode r8-r14 holding buffer */
26 /* fiq mode r8-r14 regs */
28 /* supervisor mode r13-r14 regs */
30 /* abort mode r13-r14 regs */
32 /* irq mode r13-r14 regs */
34 /* undefined mode r13-r14 regs */
52 /* Saved Process Status Register during FIQ */
54 /* Saved Process Status Register during SVC */
56 /* Saved Process Status Register during Abort */
58 /* Saved Process Status Register during IRQ */
60 /* Saved Process Status Register during Undefined */
64 void stream_cgen_hardware (std::ostream &ost) const
66 ost << hardware.h_pc << ' ';
67 for (int i = 0; i < 16; i++)
68 ost << hardware.h_gr[i] << ' ';
69 for (int i = 0; i < 7; i++)
70 ost << hardware.h_gr_usr[i] << ' ';
71 for (int i = 0; i < 7; i++)
72 ost << hardware.h_gr_fiq[i] << ' ';
73 for (int i = 0; i < 2; i++)
74 ost << hardware.h_gr_svc[i] << ' ';
75 for (int i = 0; i < 2; i++)
76 ost << hardware.h_gr_abt[i] << ' ';
77 for (int i = 0; i < 2; i++)
78 ost << hardware.h_gr_irq[i] << ' ';
79 for (int i = 0; i < 2; i++)
80 ost << hardware.h_gr_und[i] << ' ';
81 ost << hardware.h_cbit << ' ';
82 ost << hardware.h_nbit << ' ';
83 ost << hardware.h_vbit << ' ';
84 ost << hardware.h_zbit << ' ';
85 ost << hardware.h_ibit << ' ';
86 ost << hardware.h_fbit << ' ';
87 ost << hardware.h_tbit << ' ';
88 ost << hardware.h_mbits << ' ';
89 ost << hardware.h_spsr_fiq << ' ';
90 ost << hardware.h_spsr_svc << ' ';
91 ost << hardware.h_spsr_abt << ' ';
92 ost << hardware.h_spsr_irq << ' ';
93 ost << hardware.h_spsr_und << ' ';
95 void destream_cgen_hardware (std::istream &ist)
98 for (int i = 0; i < 16; i++)
99 ist >> hardware.h_gr[i];
100 for (int i = 0; i < 7; i++)
101 ist >> hardware.h_gr_usr[i];
102 for (int i = 0; i < 7; i++)
103 ist >> hardware.h_gr_fiq[i];
104 for (int i = 0; i < 2; i++)
105 ist >> hardware.h_gr_svc[i];
106 for (int i = 0; i < 2; i++)
107 ist >> hardware.h_gr_abt[i];
108 for (int i = 0; i < 2; i++)
109 ist >> hardware.h_gr_irq[i];
110 for (int i = 0; i < 2; i++)
111 ist >> hardware.h_gr_und[i];
112 ist >> hardware.h_cbit;
113 ist >> hardware.h_nbit;
114 ist >> hardware.h_vbit;
115 ist >> hardware.h_zbit;
116 ist >> hardware.h_ibit;
117 ist >> hardware.h_fbit;
118 ist >> hardware.h_tbit;
119 ist >> hardware.h_mbits;
120 ist >> hardware.h_spsr_fiq;
121 ist >> hardware.h_spsr_svc;
122 ist >> hardware.h_spsr_abt;
123 ist >> hardware.h_spsr_irq;
124 ist >> hardware.h_spsr_und;
126 // C++ register access function templates
127 #define current_cpu this
129 inline USI h_pc_get () const { return this->hardware.h_pc; }
130 inline void h_pc_set (USI newval) { if (current_cpu->hardware.h_tbit) {
131 current_cpu->hardware.h_pc = ANDSI (newval, -2);
133 current_cpu->hardware.h_pc = ANDSI (newval, -4);
137 inline SI h_gr_get (UINT regno) const { return this->hardware.h_gr[regno]; }
138 inline void h_gr_set (UINT regno, SI newval) { this->hardware.h_gr[regno] = newval; }
140 inline SI h_gr_usr_get (UINT regno) const { return this->hardware.h_gr_usr[regno]; }
141 inline void h_gr_usr_set (UINT regno, SI newval) { this->hardware.h_gr_usr[regno] = newval; }
143 inline SI h_gr_fiq_get (UINT regno) const { return this->hardware.h_gr_fiq[regno]; }
144 inline void h_gr_fiq_set (UINT regno, SI newval) { this->hardware.h_gr_fiq[regno] = newval; }
146 inline SI h_gr_svc_get (UINT regno) const { return this->hardware.h_gr_svc[regno]; }
147 inline void h_gr_svc_set (UINT regno, SI newval) { this->hardware.h_gr_svc[regno] = newval; }
149 inline SI h_gr_abt_get (UINT regno) const { return this->hardware.h_gr_abt[regno]; }
150 inline void h_gr_abt_set (UINT regno, SI newval) { this->hardware.h_gr_abt[regno] = newval; }
152 inline SI h_gr_irq_get (UINT regno) const { return this->hardware.h_gr_irq[regno]; }
153 inline void h_gr_irq_set (UINT regno, SI newval) { this->hardware.h_gr_irq[regno] = newval; }
155 inline SI h_gr_und_get (UINT regno) const { return this->hardware.h_gr_und[regno]; }
156 inline void h_gr_und_set (UINT regno, SI newval) { this->hardware.h_gr_und[regno] = newval; }
158 inline BI h_cbit_get () const { return this->hardware.h_cbit; }
159 inline void h_cbit_set (BI newval) { this->hardware.h_cbit = newval; }
161 inline BI h_nbit_get () const { return this->hardware.h_nbit; }
162 inline void h_nbit_set (BI newval) { this->hardware.h_nbit = newval; }
164 inline BI h_vbit_get () const { return this->hardware.h_vbit; }
165 inline void h_vbit_set (BI newval) { this->hardware.h_vbit = newval; }
167 inline BI h_zbit_get () const { return this->hardware.h_zbit; }
168 inline void h_zbit_set (BI newval) { this->hardware.h_zbit = newval; }
170 inline BI h_ibit_get () const { return this->hardware.h_ibit; }
171 inline void h_ibit_set (BI newval) { this->hardware.h_ibit = newval; }
173 inline BI h_fbit_get () const { return this->hardware.h_fbit; }
174 inline void h_fbit_set (BI newval) { this->hardware.h_fbit = newval; }
176 inline BI h_tbit_get () const { return this->hardware.h_tbit; }
177 inline void h_tbit_set (BI newval) { {
178 current_cpu->arm_tbit_set (newval);
182 inline UINT h_mbits_get () const { return this->hardware.h_mbits; }
183 inline void h_mbits_set (UINT newval) { {
186 case ARM_MODE_USER : case ARM_MODE_FIQ : case ARM_MODE_IRQ : case ARM_MODE_SUPERVISOR : case ARM_MODE_ABORT : case ARM_MODE_UNDEFINED : case ARM_MODE_SYSTEM : {
191 current_cpu->cgen_rtx_error ("bad value for M4-M0");
195 current_cpu->arm_mbits_set (newval);
199 inline SI h_cpsr_get () const { return ORSI (SLLSI (ZEXTBISI (current_cpu->hardware.h_nbit), 31), ORSI (SLLSI (ZEXTBISI (current_cpu->hardware.h_zbit), 30), ORSI (SLLSI (ZEXTBISI (current_cpu->hardware.h_cbit), 29), ORSI (SLLSI (ZEXTBISI (current_cpu->hardware.h_vbit), 28), ORSI (SLLSI (ZEXTBISI (current_cpu->hardware.h_ibit), 7), ORSI (SLLSI (ZEXTBISI (current_cpu->hardware.h_fbit), 6), ORSI (SLLSI (ZEXTBISI (current_cpu->hardware.h_tbit), 5), current_cpu->hardware.h_mbits))))))); }
200 inline void h_cpsr_set (SI newval) { {
201 current_cpu->hardware.h_nbit = NESI (ANDSI (newval, 0x80000000), 0);
202 current_cpu->hardware.h_zbit = NESI (ANDSI (newval, 1073741824), 0);
203 current_cpu->hardware.h_cbit = NESI (ANDSI (newval, 536870912), 0);
204 current_cpu->hardware.h_vbit = NESI (ANDSI (newval, 268435456), 0);
205 current_cpu->hardware.h_ibit = NESI (ANDSI (newval, 128), 0);
206 current_cpu->hardware.h_fbit = NESI (ANDSI (newval, 64), 0);
207 current_cpu->h_tbit_set (NESI (ANDSI (newval, 32), 0));
208 current_cpu->h_mbits_set (ANDSI (newval, 31));
212 inline SI h_spsr_fiq_get () const { return this->hardware.h_spsr_fiq; }
213 inline void h_spsr_fiq_set (SI newval) { this->hardware.h_spsr_fiq = newval; }
215 inline SI h_spsr_svc_get () const { return this->hardware.h_spsr_svc; }
216 inline void h_spsr_svc_set (SI newval) { this->hardware.h_spsr_svc = newval; }
218 inline SI h_spsr_abt_get () const { return this->hardware.h_spsr_abt; }
219 inline void h_spsr_abt_set (SI newval) { this->hardware.h_spsr_abt = newval; }
221 inline SI h_spsr_irq_get () const { return this->hardware.h_spsr_irq; }
222 inline void h_spsr_irq_set (SI newval) { this->hardware.h_spsr_irq = newval; }
224 inline SI h_spsr_und_get () const { return this->hardware.h_spsr_und; }
225 inline void h_spsr_und_set (SI newval) { this->hardware.h_spsr_und = newval; }
227 inline SI h_spsr_get () const { return (current_cpu->hardware.h_mbits == ARM_MODE_USER) ? ((current_cpu->cgen_rtx_error ("can't read spsr in user mode"), 0)) : (current_cpu->hardware.h_mbits == ARM_MODE_FIQ) ? (current_cpu->hardware.h_spsr_fiq) : (current_cpu->hardware.h_mbits == ARM_MODE_IRQ) ? (current_cpu->hardware.h_spsr_irq) : (current_cpu->hardware.h_mbits == ARM_MODE_SUPERVISOR) ? (current_cpu->hardware.h_spsr_svc) : (current_cpu->hardware.h_mbits == ARM_MODE_ABORT) ? (current_cpu->hardware.h_spsr_abt) : (current_cpu->hardware.h_mbits == ARM_MODE_UNDEFINED) ? (current_cpu->hardware.h_spsr_und) : (current_cpu->hardware.h_mbits == ARM_MODE_SYSTEM) ? ((current_cpu->cgen_rtx_error ("can't read spsr in system mode"), 0)) : ((current_cpu->cgen_rtx_error ("can't read spsr, invalid mode"), 0)); }
228 inline void h_spsr_set (SI newval) { switch (current_cpu->hardware.h_mbits)
230 case ARM_MODE_USER : {
231 current_cpu->cgen_rtx_error ("can't set spsr in user mode");
234 case ARM_MODE_FIQ : {
235 current_cpu->hardware.h_spsr_fiq = newval;
238 case ARM_MODE_IRQ : {
239 current_cpu->hardware.h_spsr_irq = newval;
242 case ARM_MODE_SUPERVISOR : {
243 current_cpu->hardware.h_spsr_svc = newval;
246 case ARM_MODE_ABORT : {
247 current_cpu->hardware.h_spsr_abt = newval;
250 case ARM_MODE_UNDEFINED : {
251 current_cpu->hardware.h_spsr_und = newval;
254 case ARM_MODE_SYSTEM : {
255 current_cpu->cgen_rtx_error ("can't set spsr in system mode");
259 current_cpu->cgen_rtx_error ("can't set spsr, invalid mode");
265 inline SI thumb_h_gr_t_get (UINT regno) const { return current_cpu->hardware.h_gr[regno]; }
266 inline void thumb_h_gr_t_set (UINT regno, SI newval) { current_cpu->hardware.h_gr[regno] = newval;
269 inline SI thumb_h_lr_t_get () const { return current_cpu->hardware.h_gr[((UINT) 14)]; }
270 inline void thumb_h_lr_t_set (SI newval) { current_cpu->hardware.h_gr[((UINT) 14)] = newval;
273 inline SI thumb_h_sp_t_get () const { return current_cpu->hardware.h_gr[((UINT) 13)]; }
274 inline void thumb_h_sp_t_set (SI newval) { current_cpu->hardware.h_gr[((UINT) 13)] = newval;
277 inline SI thumb_h_hiregs_get (UINT regno) const { return current_cpu->hardware.h_gr[((regno) + (8))]; }
278 inline void thumb_h_hiregs_set (UINT regno, SI newval) { current_cpu->hardware.h_gr[((regno) + (8))] = newval;