1 /* Simulator instruction decoder for arm.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 2000-2010 Red Hat, Inc.
7 This file is part of the Red Hat simulators.
18 using namespace arm7f; // FIXME: namespace organization still wip
21 // The instruction descriptor array.
23 // Have label pointers been initialized?
24 // XXX: Note that this is also needed by when semantics are implemented as
25 // functions to handle machine variants.
26 bool arm_idesc::idesc_table_initialized_p = false;
28 arm_idesc arm_idesc::idesc_table[ARM_INSN_MSR_S + 1] =
30 { 0, 0, "X_COND", ARM_INSN_X_COND, { 0|(1<<CGEN_INSN_PBB)|(1<<CGEN_INSN_VIRTUAL), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
31 { 0, 0, "X_AFTER", ARM_INSN_X_AFTER, { 0|(1<<CGEN_INSN_PBB)|(1<<CGEN_INSN_VIRTUAL), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
32 { 0, 0, "X_BEFORE", ARM_INSN_X_BEFORE, { 0|(1<<CGEN_INSN_PBB)|(1<<CGEN_INSN_VIRTUAL), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
33 { 0, 0, "X_CTI_CHAIN", ARM_INSN_X_CTI_CHAIN, { 0|(1<<CGEN_INSN_PBB)|(1<<CGEN_INSN_VIRTUAL), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
34 { 0, 0, "X_CHAIN", ARM_INSN_X_CHAIN, { 0|(1<<CGEN_INSN_PBB)|(1<<CGEN_INSN_VIRTUAL), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
35 { 0, 0, "X_BEGIN", ARM_INSN_X_BEGIN, { 0|(1<<CGEN_INSN_PBB)|(1<<CGEN_INSN_VIRTUAL), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
36 { 0, arm_sem_x_invalid, "X_INVALID", ARM_INSN_X_INVALID, { 0|(1<<CGEN_INSN_VIRTUAL), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
37 { 0, arm_sem_b, "B", ARM_INSN_B, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
38 { 0, arm_sem_bl, "BL", ARM_INSN_BL, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
39 { 0, arm_sem_bx, "BX", ARM_INSN_BX, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
40 { 0, arm_sem_ldr_post_dec_imm_offset, "LDR_POST_DEC_IMM_OFFSET", ARM_INSN_LDR_POST_DEC_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
41 { 0, arm_sem_ldr_post_dec_reg_offset, "LDR_POST_DEC_REG_OFFSET", ARM_INSN_LDR_POST_DEC_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
42 { 0, arm_sem_ldr_post_inc_imm_offset, "LDR_POST_INC_IMM_OFFSET", ARM_INSN_LDR_POST_INC_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
43 { 0, arm_sem_ldr_post_inc_reg_offset, "LDR_POST_INC_REG_OFFSET", ARM_INSN_LDR_POST_INC_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
44 { 0, arm_sem_ldr_post_dec_nonpriv_imm_offset, "LDR_POST_DEC_NONPRIV_IMM_OFFSET", ARM_INSN_LDR_POST_DEC_NONPRIV_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
45 { 0, arm_sem_ldr_post_dec_nonpriv_reg_offset, "LDR_POST_DEC_NONPRIV_REG_OFFSET", ARM_INSN_LDR_POST_DEC_NONPRIV_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
46 { 0, arm_sem_ldr_post_inc_nonpriv_imm_offset, "LDR_POST_INC_NONPRIV_IMM_OFFSET", ARM_INSN_LDR_POST_INC_NONPRIV_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
47 { 0, arm_sem_ldr_post_inc_nonpriv_reg_offset, "LDR_POST_INC_NONPRIV_REG_OFFSET", ARM_INSN_LDR_POST_INC_NONPRIV_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
48 { 0, arm_sem_ldr_pre_dec_imm_offset, "LDR_PRE_DEC_IMM_OFFSET", ARM_INSN_LDR_PRE_DEC_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
49 { 0, arm_sem_ldr_pre_dec_reg_offset, "LDR_PRE_DEC_REG_OFFSET", ARM_INSN_LDR_PRE_DEC_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
50 { 0, arm_sem_ldr_pre_inc_imm_offset, "LDR_PRE_INC_IMM_OFFSET", ARM_INSN_LDR_PRE_INC_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
51 { 0, arm_sem_ldr_pre_inc_reg_offset, "LDR_PRE_INC_REG_OFFSET", ARM_INSN_LDR_PRE_INC_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
52 { 0, arm_sem_ldr_pre_dec_wb_imm_offset, "LDR_PRE_DEC_WB_IMM_OFFSET", ARM_INSN_LDR_PRE_DEC_WB_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
53 { 0, arm_sem_ldr_pre_dec_wb_reg_offset, "LDR_PRE_DEC_WB_REG_OFFSET", ARM_INSN_LDR_PRE_DEC_WB_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
54 { 0, arm_sem_ldr_pre_inc_wb_imm_offset, "LDR_PRE_INC_WB_IMM_OFFSET", ARM_INSN_LDR_PRE_INC_WB_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
55 { 0, arm_sem_ldr_pre_inc_wb_reg_offset, "LDR_PRE_INC_WB_REG_OFFSET", ARM_INSN_LDR_PRE_INC_WB_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
56 { 0, arm_sem_ldrb_post_dec_imm_offset, "LDRB_POST_DEC_IMM_OFFSET", ARM_INSN_LDRB_POST_DEC_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
57 { 0, arm_sem_ldrb_post_dec_reg_offset, "LDRB_POST_DEC_REG_OFFSET", ARM_INSN_LDRB_POST_DEC_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
58 { 0, arm_sem_ldrb_post_inc_imm_offset, "LDRB_POST_INC_IMM_OFFSET", ARM_INSN_LDRB_POST_INC_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
59 { 0, arm_sem_ldrb_post_inc_reg_offset, "LDRB_POST_INC_REG_OFFSET", ARM_INSN_LDRB_POST_INC_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
60 { 0, arm_sem_ldrb_post_dec_nonpriv_imm_offset, "LDRB_POST_DEC_NONPRIV_IMM_OFFSET", ARM_INSN_LDRB_POST_DEC_NONPRIV_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
61 { 0, arm_sem_ldrb_post_dec_nonpriv_reg_offset, "LDRB_POST_DEC_NONPRIV_REG_OFFSET", ARM_INSN_LDRB_POST_DEC_NONPRIV_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
62 { 0, arm_sem_ldrb_post_inc_nonpriv_imm_offset, "LDRB_POST_INC_NONPRIV_IMM_OFFSET", ARM_INSN_LDRB_POST_INC_NONPRIV_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
63 { 0, arm_sem_ldrb_post_inc_nonpriv_reg_offset, "LDRB_POST_INC_NONPRIV_REG_OFFSET", ARM_INSN_LDRB_POST_INC_NONPRIV_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
64 { 0, arm_sem_ldrb_pre_dec_imm_offset, "LDRB_PRE_DEC_IMM_OFFSET", ARM_INSN_LDRB_PRE_DEC_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
65 { 0, arm_sem_ldrb_pre_dec_reg_offset, "LDRB_PRE_DEC_REG_OFFSET", ARM_INSN_LDRB_PRE_DEC_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
66 { 0, arm_sem_ldrb_pre_inc_imm_offset, "LDRB_PRE_INC_IMM_OFFSET", ARM_INSN_LDRB_PRE_INC_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
67 { 0, arm_sem_ldrb_pre_inc_reg_offset, "LDRB_PRE_INC_REG_OFFSET", ARM_INSN_LDRB_PRE_INC_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
68 { 0, arm_sem_ldrb_pre_dec_wb_imm_offset, "LDRB_PRE_DEC_WB_IMM_OFFSET", ARM_INSN_LDRB_PRE_DEC_WB_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
69 { 0, arm_sem_ldrb_pre_dec_wb_reg_offset, "LDRB_PRE_DEC_WB_REG_OFFSET", ARM_INSN_LDRB_PRE_DEC_WB_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
70 { 0, arm_sem_ldrb_pre_inc_wb_imm_offset, "LDRB_PRE_INC_WB_IMM_OFFSET", ARM_INSN_LDRB_PRE_INC_WB_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
71 { 0, arm_sem_ldrb_pre_inc_wb_reg_offset, "LDRB_PRE_INC_WB_REG_OFFSET", ARM_INSN_LDRB_PRE_INC_WB_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
72 { 0, arm_sem_str_post_dec_imm_offset, "STR_POST_DEC_IMM_OFFSET", ARM_INSN_STR_POST_DEC_IMM_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
73 { 0, arm_sem_str_post_dec_reg_offset, "STR_POST_DEC_REG_OFFSET", ARM_INSN_STR_POST_DEC_REG_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
74 { 0, arm_sem_str_post_inc_imm_offset, "STR_POST_INC_IMM_OFFSET", ARM_INSN_STR_POST_INC_IMM_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
75 { 0, arm_sem_str_post_inc_reg_offset, "STR_POST_INC_REG_OFFSET", ARM_INSN_STR_POST_INC_REG_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
76 { 0, arm_sem_str_post_dec_nonpriv_imm_offset, "STR_POST_DEC_NONPRIV_IMM_OFFSET", ARM_INSN_STR_POST_DEC_NONPRIV_IMM_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
77 { 0, arm_sem_str_post_dec_nonpriv_reg_offset, "STR_POST_DEC_NONPRIV_REG_OFFSET", ARM_INSN_STR_POST_DEC_NONPRIV_REG_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
78 { 0, arm_sem_str_post_inc_nonpriv_imm_offset, "STR_POST_INC_NONPRIV_IMM_OFFSET", ARM_INSN_STR_POST_INC_NONPRIV_IMM_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
79 { 0, arm_sem_str_post_inc_nonpriv_reg_offset, "STR_POST_INC_NONPRIV_REG_OFFSET", ARM_INSN_STR_POST_INC_NONPRIV_REG_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
80 { 0, arm_sem_str_pre_dec_imm_offset, "STR_PRE_DEC_IMM_OFFSET", ARM_INSN_STR_PRE_DEC_IMM_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
81 { 0, arm_sem_str_pre_dec_reg_offset, "STR_PRE_DEC_REG_OFFSET", ARM_INSN_STR_PRE_DEC_REG_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
82 { 0, arm_sem_str_pre_inc_imm_offset, "STR_PRE_INC_IMM_OFFSET", ARM_INSN_STR_PRE_INC_IMM_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
83 { 0, arm_sem_str_pre_inc_reg_offset, "STR_PRE_INC_REG_OFFSET", ARM_INSN_STR_PRE_INC_REG_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
84 { 0, arm_sem_str_pre_dec_wb_imm_offset, "STR_PRE_DEC_WB_IMM_OFFSET", ARM_INSN_STR_PRE_DEC_WB_IMM_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
85 { 0, arm_sem_str_pre_dec_wb_reg_offset, "STR_PRE_DEC_WB_REG_OFFSET", ARM_INSN_STR_PRE_DEC_WB_REG_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
86 { 0, arm_sem_str_pre_inc_wb_imm_offset, "STR_PRE_INC_WB_IMM_OFFSET", ARM_INSN_STR_PRE_INC_WB_IMM_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
87 { 0, arm_sem_str_pre_inc_wb_reg_offset, "STR_PRE_INC_WB_REG_OFFSET", ARM_INSN_STR_PRE_INC_WB_REG_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
88 { 0, arm_sem_strb_post_dec_imm_offset, "STRB_POST_DEC_IMM_OFFSET", ARM_INSN_STRB_POST_DEC_IMM_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
89 { 0, arm_sem_strb_post_dec_reg_offset, "STRB_POST_DEC_REG_OFFSET", ARM_INSN_STRB_POST_DEC_REG_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
90 { 0, arm_sem_strb_post_inc_imm_offset, "STRB_POST_INC_IMM_OFFSET", ARM_INSN_STRB_POST_INC_IMM_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
91 { 0, arm_sem_strb_post_inc_reg_offset, "STRB_POST_INC_REG_OFFSET", ARM_INSN_STRB_POST_INC_REG_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
92 { 0, arm_sem_strb_post_dec_nonpriv_imm_offset, "STRB_POST_DEC_NONPRIV_IMM_OFFSET", ARM_INSN_STRB_POST_DEC_NONPRIV_IMM_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
93 { 0, arm_sem_strb_post_dec_nonpriv_reg_offset, "STRB_POST_DEC_NONPRIV_REG_OFFSET", ARM_INSN_STRB_POST_DEC_NONPRIV_REG_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
94 { 0, arm_sem_strb_post_inc_nonpriv_imm_offset, "STRB_POST_INC_NONPRIV_IMM_OFFSET", ARM_INSN_STRB_POST_INC_NONPRIV_IMM_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
95 { 0, arm_sem_strb_post_inc_nonpriv_reg_offset, "STRB_POST_INC_NONPRIV_REG_OFFSET", ARM_INSN_STRB_POST_INC_NONPRIV_REG_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
96 { 0, arm_sem_strb_pre_dec_imm_offset, "STRB_PRE_DEC_IMM_OFFSET", ARM_INSN_STRB_PRE_DEC_IMM_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
97 { 0, arm_sem_strb_pre_dec_reg_offset, "STRB_PRE_DEC_REG_OFFSET", ARM_INSN_STRB_PRE_DEC_REG_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
98 { 0, arm_sem_strb_pre_inc_imm_offset, "STRB_PRE_INC_IMM_OFFSET", ARM_INSN_STRB_PRE_INC_IMM_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
99 { 0, arm_sem_strb_pre_inc_reg_offset, "STRB_PRE_INC_REG_OFFSET", ARM_INSN_STRB_PRE_INC_REG_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
100 { 0, arm_sem_strb_pre_dec_wb_imm_offset, "STRB_PRE_DEC_WB_IMM_OFFSET", ARM_INSN_STRB_PRE_DEC_WB_IMM_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
101 { 0, arm_sem_strb_pre_dec_wb_reg_offset, "STRB_PRE_DEC_WB_REG_OFFSET", ARM_INSN_STRB_PRE_DEC_WB_REG_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
102 { 0, arm_sem_strb_pre_inc_wb_imm_offset, "STRB_PRE_INC_WB_IMM_OFFSET", ARM_INSN_STRB_PRE_INC_WB_IMM_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
103 { 0, arm_sem_strb_pre_inc_wb_reg_offset, "STRB_PRE_INC_WB_REG_OFFSET", ARM_INSN_STRB_PRE_INC_WB_REG_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
104 { 0, arm_sem_strh_pre_dec_imm_offset, "STRH_PRE_DEC_IMM_OFFSET", ARM_INSN_STRH_PRE_DEC_IMM_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
105 { 0, arm_sem_strh_pre_dec_reg_offset, "STRH_PRE_DEC_REG_OFFSET", ARM_INSN_STRH_PRE_DEC_REG_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
106 { 0, arm_sem_strh_pre_inc_imm_offset, "STRH_PRE_INC_IMM_OFFSET", ARM_INSN_STRH_PRE_INC_IMM_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
107 { 0, arm_sem_strh_pre_inc_reg_offset, "STRH_PRE_INC_REG_OFFSET", ARM_INSN_STRH_PRE_INC_REG_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
108 { 0, arm_sem_strh_pre_dec_wb_imm_offset, "STRH_PRE_DEC_WB_IMM_OFFSET", ARM_INSN_STRH_PRE_DEC_WB_IMM_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
109 { 0, arm_sem_strh_pre_dec_wb_reg_offset, "STRH_PRE_DEC_WB_REG_OFFSET", ARM_INSN_STRH_PRE_DEC_WB_REG_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
110 { 0, arm_sem_strh_pre_inc_wb_imm_offset, "STRH_PRE_INC_WB_IMM_OFFSET", ARM_INSN_STRH_PRE_INC_WB_IMM_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
111 { 0, arm_sem_strh_pre_inc_wb_reg_offset, "STRH_PRE_INC_WB_REG_OFFSET", ARM_INSN_STRH_PRE_INC_WB_REG_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
112 { 0, arm_sem_strh_post_dec_imm_offset, "STRH_POST_DEC_IMM_OFFSET", ARM_INSN_STRH_POST_DEC_IMM_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
113 { 0, arm_sem_strh_post_dec_reg_offset, "STRH_POST_DEC_REG_OFFSET", ARM_INSN_STRH_POST_DEC_REG_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
114 { 0, arm_sem_strh_post_inc_imm_offset, "STRH_POST_INC_IMM_OFFSET", ARM_INSN_STRH_POST_INC_IMM_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
115 { 0, arm_sem_strh_post_inc_reg_offset, "STRH_POST_INC_REG_OFFSET", ARM_INSN_STRH_POST_INC_REG_OFFSET, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
116 { 0, arm_sem_ldrsb_pre_dec_imm_offset, "LDRSB_PRE_DEC_IMM_OFFSET", ARM_INSN_LDRSB_PRE_DEC_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
117 { 0, arm_sem_ldrsb_pre_dec_reg_offset, "LDRSB_PRE_DEC_REG_OFFSET", ARM_INSN_LDRSB_PRE_DEC_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
118 { 0, arm_sem_ldrsb_pre_inc_imm_offset, "LDRSB_PRE_INC_IMM_OFFSET", ARM_INSN_LDRSB_PRE_INC_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
119 { 0, arm_sem_ldrsb_pre_inc_reg_offset, "LDRSB_PRE_INC_REG_OFFSET", ARM_INSN_LDRSB_PRE_INC_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
120 { 0, arm_sem_ldrsb_pre_dec_wb_imm_offset, "LDRSB_PRE_DEC_WB_IMM_OFFSET", ARM_INSN_LDRSB_PRE_DEC_WB_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
121 { 0, arm_sem_ldrsb_pre_dec_wb_reg_offset, "LDRSB_PRE_DEC_WB_REG_OFFSET", ARM_INSN_LDRSB_PRE_DEC_WB_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
122 { 0, arm_sem_ldrsb_pre_inc_wb_imm_offset, "LDRSB_PRE_INC_WB_IMM_OFFSET", ARM_INSN_LDRSB_PRE_INC_WB_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
123 { 0, arm_sem_ldrsb_pre_inc_wb_reg_offset, "LDRSB_PRE_INC_WB_REG_OFFSET", ARM_INSN_LDRSB_PRE_INC_WB_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
124 { 0, arm_sem_ldrsb_post_dec_imm_offset, "LDRSB_POST_DEC_IMM_OFFSET", ARM_INSN_LDRSB_POST_DEC_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
125 { 0, arm_sem_ldrsb_post_dec_reg_offset, "LDRSB_POST_DEC_REG_OFFSET", ARM_INSN_LDRSB_POST_DEC_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
126 { 0, arm_sem_ldrsb_post_inc_imm_offset, "LDRSB_POST_INC_IMM_OFFSET", ARM_INSN_LDRSB_POST_INC_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
127 { 0, arm_sem_ldrsb_post_inc_reg_offset, "LDRSB_POST_INC_REG_OFFSET", ARM_INSN_LDRSB_POST_INC_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
128 { 0, arm_sem_ldrh_pre_dec_imm_offset, "LDRH_PRE_DEC_IMM_OFFSET", ARM_INSN_LDRH_PRE_DEC_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
129 { 0, arm_sem_ldrh_pre_dec_reg_offset, "LDRH_PRE_DEC_REG_OFFSET", ARM_INSN_LDRH_PRE_DEC_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
130 { 0, arm_sem_ldrh_pre_inc_imm_offset, "LDRH_PRE_INC_IMM_OFFSET", ARM_INSN_LDRH_PRE_INC_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
131 { 0, arm_sem_ldrh_pre_inc_reg_offset, "LDRH_PRE_INC_REG_OFFSET", ARM_INSN_LDRH_PRE_INC_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
132 { 0, arm_sem_ldrh_pre_dec_wb_imm_offset, "LDRH_PRE_DEC_WB_IMM_OFFSET", ARM_INSN_LDRH_PRE_DEC_WB_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
133 { 0, arm_sem_ldrh_pre_dec_wb_reg_offset, "LDRH_PRE_DEC_WB_REG_OFFSET", ARM_INSN_LDRH_PRE_DEC_WB_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
134 { 0, arm_sem_ldrh_pre_inc_wb_imm_offset, "LDRH_PRE_INC_WB_IMM_OFFSET", ARM_INSN_LDRH_PRE_INC_WB_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
135 { 0, arm_sem_ldrh_pre_inc_wb_reg_offset, "LDRH_PRE_INC_WB_REG_OFFSET", ARM_INSN_LDRH_PRE_INC_WB_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
136 { 0, arm_sem_ldrh_post_dec_imm_offset, "LDRH_POST_DEC_IMM_OFFSET", ARM_INSN_LDRH_POST_DEC_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
137 { 0, arm_sem_ldrh_post_dec_reg_offset, "LDRH_POST_DEC_REG_OFFSET", ARM_INSN_LDRH_POST_DEC_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
138 { 0, arm_sem_ldrh_post_inc_imm_offset, "LDRH_POST_INC_IMM_OFFSET", ARM_INSN_LDRH_POST_INC_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
139 { 0, arm_sem_ldrh_post_inc_reg_offset, "LDRH_POST_INC_REG_OFFSET", ARM_INSN_LDRH_POST_INC_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
140 { 0, arm_sem_ldrsh_pre_dec_imm_offset, "LDRSH_PRE_DEC_IMM_OFFSET", ARM_INSN_LDRSH_PRE_DEC_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
141 { 0, arm_sem_ldrsh_pre_dec_reg_offset, "LDRSH_PRE_DEC_REG_OFFSET", ARM_INSN_LDRSH_PRE_DEC_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
142 { 0, arm_sem_ldrsh_pre_inc_imm_offset, "LDRSH_PRE_INC_IMM_OFFSET", ARM_INSN_LDRSH_PRE_INC_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
143 { 0, arm_sem_ldrsh_pre_inc_reg_offset, "LDRSH_PRE_INC_REG_OFFSET", ARM_INSN_LDRSH_PRE_INC_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
144 { 0, arm_sem_ldrsh_pre_dec_wb_imm_offset, "LDRSH_PRE_DEC_WB_IMM_OFFSET", ARM_INSN_LDRSH_PRE_DEC_WB_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
145 { 0, arm_sem_ldrsh_pre_dec_wb_reg_offset, "LDRSH_PRE_DEC_WB_REG_OFFSET", ARM_INSN_LDRSH_PRE_DEC_WB_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
146 { 0, arm_sem_ldrsh_pre_inc_wb_imm_offset, "LDRSH_PRE_INC_WB_IMM_OFFSET", ARM_INSN_LDRSH_PRE_INC_WB_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
147 { 0, arm_sem_ldrsh_pre_inc_wb_reg_offset, "LDRSH_PRE_INC_WB_REG_OFFSET", ARM_INSN_LDRSH_PRE_INC_WB_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
148 { 0, arm_sem_ldrsh_post_dec_imm_offset, "LDRSH_POST_DEC_IMM_OFFSET", ARM_INSN_LDRSH_POST_DEC_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
149 { 0, arm_sem_ldrsh_post_dec_reg_offset, "LDRSH_POST_DEC_REG_OFFSET", ARM_INSN_LDRSH_POST_DEC_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
150 { 0, arm_sem_ldrsh_post_inc_imm_offset, "LDRSH_POST_INC_IMM_OFFSET", ARM_INSN_LDRSH_POST_INC_IMM_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
151 { 0, arm_sem_ldrsh_post_inc_reg_offset, "LDRSH_POST_INC_REG_OFFSET", ARM_INSN_LDRSH_POST_INC_REG_OFFSET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
152 { 0, arm_sem_mul, "MUL", ARM_INSN_MUL, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
153 { 0, arm_sem_mla, "MLA", ARM_INSN_MLA, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
154 { 0, arm_sem_umull, "UMULL", ARM_INSN_UMULL, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
155 { 0, arm_sem_umlal, "UMLAL", ARM_INSN_UMLAL, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
156 { 0, arm_sem_smull, "SMULL", ARM_INSN_SMULL, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
157 { 0, arm_sem_smlal, "SMLAL", ARM_INSN_SMLAL, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
158 { 0, arm_sem_swp, "SWP", ARM_INSN_SWP, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
159 { 0, arm_sem_swpb, "SWPB", ARM_INSN_SWPB, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
160 { 0, arm_sem_swi, "SWI", ARM_INSN_SWI, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
161 { 0, arm_sem_and_reg_imm_shift, "AND_REG_IMM_SHIFT", ARM_INSN_AND_REG_IMM_SHIFT, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
162 { 0, arm_sem_and_reg_reg_shift, "AND_REG_REG_SHIFT", ARM_INSN_AND_REG_REG_SHIFT, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 12 } },
163 { 0, arm_sem_and_imm, "AND_IMM", ARM_INSN_AND_IMM, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
164 { 0, arm_sem_orr_reg_imm_shift, "ORR_REG_IMM_SHIFT", ARM_INSN_ORR_REG_IMM_SHIFT, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
165 { 0, arm_sem_orr_reg_reg_shift, "ORR_REG_REG_SHIFT", ARM_INSN_ORR_REG_REG_SHIFT, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 12 } },
166 { 0, arm_sem_orr_imm, "ORR_IMM", ARM_INSN_ORR_IMM, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
167 { 0, arm_sem_eor_reg_imm_shift, "EOR_REG_IMM_SHIFT", ARM_INSN_EOR_REG_IMM_SHIFT, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
168 { 0, arm_sem_eor_reg_reg_shift, "EOR_REG_REG_SHIFT", ARM_INSN_EOR_REG_REG_SHIFT, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 12 } },
169 { 0, arm_sem_eor_imm, "EOR_IMM", ARM_INSN_EOR_IMM, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
170 { 0, arm_sem_mov_reg_imm_shift, "MOV_REG_IMM_SHIFT", ARM_INSN_MOV_REG_IMM_SHIFT, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
171 { 0, arm_sem_mov_reg_reg_shift, "MOV_REG_REG_SHIFT", ARM_INSN_MOV_REG_REG_SHIFT, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 12 } },
172 { 0, arm_sem_mov_imm, "MOV_IMM", ARM_INSN_MOV_IMM, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
173 { 0, arm_sem_bic_reg_imm_shift, "BIC_REG_IMM_SHIFT", ARM_INSN_BIC_REG_IMM_SHIFT, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
174 { 0, arm_sem_bic_reg_reg_shift, "BIC_REG_REG_SHIFT", ARM_INSN_BIC_REG_REG_SHIFT, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 12 } },
175 { 0, arm_sem_bic_imm, "BIC_IMM", ARM_INSN_BIC_IMM, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
176 { 0, arm_sem_mvn_reg_imm_shift, "MVN_REG_IMM_SHIFT", ARM_INSN_MVN_REG_IMM_SHIFT, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
177 { 0, arm_sem_mvn_reg_reg_shift, "MVN_REG_REG_SHIFT", ARM_INSN_MVN_REG_REG_SHIFT, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 12 } },
178 { 0, arm_sem_mvn_imm, "MVN_IMM", ARM_INSN_MVN_IMM, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
179 { 0, arm_sem_add_reg_imm_shift, "ADD_REG_IMM_SHIFT", ARM_INSN_ADD_REG_IMM_SHIFT, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
180 { 0, arm_sem_add_reg_reg_shift, "ADD_REG_REG_SHIFT", ARM_INSN_ADD_REG_REG_SHIFT, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 12 } },
181 { 0, arm_sem_add_imm, "ADD_IMM", ARM_INSN_ADD_IMM, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
182 { 0, arm_sem_adc_reg_imm_shift, "ADC_REG_IMM_SHIFT", ARM_INSN_ADC_REG_IMM_SHIFT, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
183 { 0, arm_sem_adc_reg_reg_shift, "ADC_REG_REG_SHIFT", ARM_INSN_ADC_REG_REG_SHIFT, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 12 } },
184 { 0, arm_sem_adc_imm, "ADC_IMM", ARM_INSN_ADC_IMM, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
185 { 0, arm_sem_sub_reg_imm_shift, "SUB_REG_IMM_SHIFT", ARM_INSN_SUB_REG_IMM_SHIFT, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
186 { 0, arm_sem_sub_reg_reg_shift, "SUB_REG_REG_SHIFT", ARM_INSN_SUB_REG_REG_SHIFT, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 12 } },
187 { 0, arm_sem_sub_imm, "SUB_IMM", ARM_INSN_SUB_IMM, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
188 { 0, arm_sem_sbc_reg_imm_shift, "SBC_REG_IMM_SHIFT", ARM_INSN_SBC_REG_IMM_SHIFT, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
189 { 0, arm_sem_sbc_reg_reg_shift, "SBC_REG_REG_SHIFT", ARM_INSN_SBC_REG_REG_SHIFT, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 12 } },
190 { 0, arm_sem_sbc_imm, "SBC_IMM", ARM_INSN_SBC_IMM, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
191 { 0, arm_sem_rsb_reg_imm_shift, "RSB_REG_IMM_SHIFT", ARM_INSN_RSB_REG_IMM_SHIFT, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
192 { 0, arm_sem_rsb_reg_reg_shift, "RSB_REG_REG_SHIFT", ARM_INSN_RSB_REG_REG_SHIFT, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 12 } },
193 { 0, arm_sem_rsb_imm, "RSB_IMM", ARM_INSN_RSB_IMM, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
194 { 0, arm_sem_rsc_reg_imm_shift, "RSC_REG_IMM_SHIFT", ARM_INSN_RSC_REG_IMM_SHIFT, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
195 { 0, arm_sem_rsc_reg_reg_shift, "RSC_REG_REG_SHIFT", ARM_INSN_RSC_REG_REG_SHIFT, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 12 } },
196 { 0, arm_sem_rsc_imm, "RSC_IMM", ARM_INSN_RSC_IMM, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
197 { 0, arm_sem_tst_reg_imm_shift, "TST_REG_IMM_SHIFT", ARM_INSN_TST_REG_IMM_SHIFT, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
198 { 0, arm_sem_tst_reg_reg_shift, "TST_REG_REG_SHIFT", ARM_INSN_TST_REG_REG_SHIFT, { 0, (1<<MACH_BASE), { 1, "\x80" }, 12 } },
199 { 0, arm_sem_tst_imm, "TST_IMM", ARM_INSN_TST_IMM, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
200 { 0, arm_sem_teq_reg_imm_shift, "TEQ_REG_IMM_SHIFT", ARM_INSN_TEQ_REG_IMM_SHIFT, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
201 { 0, arm_sem_teq_reg_reg_shift, "TEQ_REG_REG_SHIFT", ARM_INSN_TEQ_REG_REG_SHIFT, { 0, (1<<MACH_BASE), { 1, "\x80" }, 12 } },
202 { 0, arm_sem_teq_imm, "TEQ_IMM", ARM_INSN_TEQ_IMM, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
203 { 0, arm_sem_cmp_reg_imm_shift, "CMP_REG_IMM_SHIFT", ARM_INSN_CMP_REG_IMM_SHIFT, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
204 { 0, arm_sem_cmp_reg_reg_shift, "CMP_REG_REG_SHIFT", ARM_INSN_CMP_REG_REG_SHIFT, { 0, (1<<MACH_BASE), { 1, "\x80" }, 12 } },
205 { 0, arm_sem_cmp_imm, "CMP_IMM", ARM_INSN_CMP_IMM, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
206 { 0, arm_sem_cmn_reg_imm_shift, "CMN_REG_IMM_SHIFT", ARM_INSN_CMN_REG_IMM_SHIFT, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
207 { 0, arm_sem_cmn_reg_reg_shift, "CMN_REG_REG_SHIFT", ARM_INSN_CMN_REG_REG_SHIFT, { 0, (1<<MACH_BASE), { 1, "\x80" }, 12 } },
208 { 0, arm_sem_cmn_imm, "CMN_IMM", ARM_INSN_CMN_IMM, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
209 { 0, arm_sem_ldmda, "LDMDA", ARM_INSN_LDMDA, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
210 { 0, arm_sem_ldmda_sw, "LDMDA_SW", ARM_INSN_LDMDA_SW, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
211 { 0, arm_sem_ldmda_wb, "LDMDA_WB", ARM_INSN_LDMDA_WB, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
212 { 0, arm_sem_ldmda_sw_wb, "LDMDA_SW_WB", ARM_INSN_LDMDA_SW_WB, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
213 { 0, arm_sem_ldmib, "LDMIB", ARM_INSN_LDMIB, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
214 { 0, arm_sem_ldmib_sw, "LDMIB_SW", ARM_INSN_LDMIB_SW, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
215 { 0, arm_sem_ldmib_wb, "LDMIB_WB", ARM_INSN_LDMIB_WB, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
216 { 0, arm_sem_ldmib_sw_wb, "LDMIB_SW_WB", ARM_INSN_LDMIB_SW_WB, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
217 { 0, arm_sem_ldmia, "LDMIA", ARM_INSN_LDMIA, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
218 { 0, arm_sem_ldmia_sw, "LDMIA_SW", ARM_INSN_LDMIA_SW, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
219 { 0, arm_sem_ldmia_wb, "LDMIA_WB", ARM_INSN_LDMIA_WB, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
220 { 0, arm_sem_ldmia_sw_wb, "LDMIA_SW_WB", ARM_INSN_LDMIA_SW_WB, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
221 { 0, arm_sem_ldmdb, "LDMDB", ARM_INSN_LDMDB, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
222 { 0, arm_sem_ldmdb_sw, "LDMDB_SW", ARM_INSN_LDMDB_SW, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
223 { 0, arm_sem_ldmdb_wb, "LDMDB_WB", ARM_INSN_LDMDB_WB, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
224 { 0, arm_sem_ldmdb_sw_wb, "LDMDB_SW_WB", ARM_INSN_LDMDB_SW_WB, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\x80" }, 8 } },
225 { 0, arm_sem_stmdb, "STMDB", ARM_INSN_STMDB, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
226 { 0, arm_sem_stmdb_sw, "STMDB_SW", ARM_INSN_STMDB_SW, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
227 { 0, arm_sem_stmdb_wb, "STMDB_WB", ARM_INSN_STMDB_WB, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
228 { 0, arm_sem_stmdb_sw_wb, "STMDB_SW_WB", ARM_INSN_STMDB_SW_WB, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
229 { 0, arm_sem_stmib, "STMIB", ARM_INSN_STMIB, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
230 { 0, arm_sem_stmib_sw, "STMIB_SW", ARM_INSN_STMIB_SW, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
231 { 0, arm_sem_stmib_wb, "STMIB_WB", ARM_INSN_STMIB_WB, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
232 { 0, arm_sem_stmib_sw_wb, "STMIB_SW_WB", ARM_INSN_STMIB_SW_WB, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
233 { 0, arm_sem_stmia, "STMIA", ARM_INSN_STMIA, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
234 { 0, arm_sem_stmia_sw, "STMIA_SW", ARM_INSN_STMIA_SW, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
235 { 0, arm_sem_stmia_wb, "STMIA_WB", ARM_INSN_STMIA_WB, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
236 { 0, arm_sem_stmia_sw_wb, "STMIA_SW_WB", ARM_INSN_STMIA_SW_WB, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
237 { 0, arm_sem_stmda, "STMDA", ARM_INSN_STMDA, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
238 { 0, arm_sem_stmda_sw, "STMDA_SW", ARM_INSN_STMDA_SW, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
239 { 0, arm_sem_stmda_wb, "STMDA_WB", ARM_INSN_STMDA_WB, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
240 { 0, arm_sem_stmda_sw_wb, "STMDA_SW_WB", ARM_INSN_STMDA_SW_WB, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
241 { 0, arm_sem_mrs_c, "MRS_C", ARM_INSN_MRS_C, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
242 { 0, arm_sem_mrs_s, "MRS_S", ARM_INSN_MRS_S, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
243 { 0, arm_sem_msr_c, "MSR_C", ARM_INSN_MSR_C, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
244 { 0, arm_sem_msr_s, "MSR_S", ARM_INSN_MSR_S, { 0, (1<<MACH_BASE), { 1, "\x80" }, 8 } },
248 // Given a canonical virtual insn id, return the target specific one.
251 arm_idesc::lookup_virtual (virtual_insn_type vit)
255 case VIRTUAL_INSN_INVALID: return ARM_INSN_X_INVALID;
256 case VIRTUAL_INSN_BEGIN: return ARM_INSN_X_BEGIN;
257 case VIRTUAL_INSN_CHAIN: return ARM_INSN_X_CHAIN;
258 case VIRTUAL_INSN_CTI_CHAIN: return ARM_INSN_X_CTI_CHAIN;
259 case VIRTUAL_INSN_BEFORE: return ARM_INSN_X_BEFORE;
260 case VIRTUAL_INSN_AFTER: return ARM_INSN_X_AFTER;
261 case VIRTUAL_INSN_COND: return ARM_INSN_X_COND;
267 // Declare extractor functions
270 arm_extract_sfmt_empty (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
272 arm_extract_sfmt_b (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
274 arm_extract_sfmt_bl (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
276 arm_extract_sfmt_bx (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
278 arm_extract_sfmt_ldr_post_dec_imm_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
280 arm_extract_sfmt_ldr_post_dec_reg_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
282 arm_extract_sfmt_ldr_pre_dec_imm_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
284 arm_extract_sfmt_ldr_pre_dec_reg_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
286 arm_extract_sfmt_ldrb_post_dec_imm_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
288 arm_extract_sfmt_ldrb_post_dec_reg_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
290 arm_extract_sfmt_ldrb_pre_dec_imm_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
292 arm_extract_sfmt_ldrb_pre_dec_reg_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
294 arm_extract_sfmt_str_post_dec_imm_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
296 arm_extract_sfmt_str_post_dec_reg_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
298 arm_extract_sfmt_str_pre_dec_imm_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
300 arm_extract_sfmt_str_pre_dec_reg_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
302 arm_extract_sfmt_strb_post_dec_imm_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
304 arm_extract_sfmt_strb_post_dec_reg_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
306 arm_extract_sfmt_strb_pre_dec_imm_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
308 arm_extract_sfmt_strb_pre_dec_reg_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
310 arm_extract_sfmt_strh_pre_dec_imm_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
312 arm_extract_sfmt_strh_pre_dec_reg_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
314 arm_extract_sfmt_strh_pre_dec_wb_imm_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
316 arm_extract_sfmt_strh_pre_dec_wb_reg_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
318 arm_extract_sfmt_ldrsb_pre_dec_imm_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
320 arm_extract_sfmt_ldrsb_pre_dec_reg_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
322 arm_extract_sfmt_ldrsb_pre_dec_wb_imm_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
324 arm_extract_sfmt_ldrsb_pre_dec_wb_reg_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
326 arm_extract_sfmt_ldrh_pre_dec_imm_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
328 arm_extract_sfmt_ldrh_pre_dec_reg_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
330 arm_extract_sfmt_ldrh_pre_dec_wb_imm_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
332 arm_extract_sfmt_ldrh_pre_dec_wb_reg_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
334 arm_extract_sfmt_mul (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
336 arm_extract_sfmt_mla (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
338 arm_extract_sfmt_umull (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
340 arm_extract_sfmt_umlal (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
342 arm_extract_sfmt_swp (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
344 arm_extract_sfmt_swpb (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
346 arm_extract_sfmt_swi (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
348 arm_extract_sfmt_and_reg_imm_shift (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
350 arm_extract_sfmt_and_reg_reg_shift (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
352 arm_extract_sfmt_and_imm (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
354 arm_extract_sfmt_mov_reg_imm_shift (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
356 arm_extract_sfmt_mov_reg_reg_shift (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
358 arm_extract_sfmt_mov_imm (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
360 arm_extract_sfmt_add_reg_imm_shift (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
362 arm_extract_sfmt_add_reg_reg_shift (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
364 arm_extract_sfmt_add_imm (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
366 arm_extract_sfmt_adc_reg_imm_shift (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
368 arm_extract_sfmt_adc_reg_reg_shift (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
370 arm_extract_sfmt_adc_imm (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
372 arm_extract_sfmt_tst_reg_imm_shift (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
374 arm_extract_sfmt_tst_reg_reg_shift (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
376 arm_extract_sfmt_tst_imm (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
378 arm_extract_sfmt_cmp_reg_imm_shift (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
380 arm_extract_sfmt_cmp_reg_reg_shift (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
382 arm_extract_sfmt_cmp_imm (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
384 arm_extract_sfmt_ldmda (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
386 arm_extract_sfmt_ldmda_sw (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
388 arm_extract_sfmt_ldmda_wb (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
390 arm_extract_sfmt_ldmda_sw_wb (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
392 arm_extract_sfmt_stmdb (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
394 arm_extract_sfmt_stmdb_sw (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
396 arm_extract_sfmt_stmdb_wb (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
398 arm_extract_sfmt_stmdb_sw_wb (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
400 arm_extract_sfmt_mrs_c (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
402 arm_extract_sfmt_mrs_s (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
404 arm_extract_sfmt_msr_c (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
406 arm_extract_sfmt_msr_s (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
408 // Fetch & decode instruction
410 arm_scache::decode (arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn)
412 /* Result of decoder. */
416 arm_insn_word insn = base_insn;
419 unsigned int val = (((insn >> 21) & (127 << 0)));
424 unsigned int val = (((insn >> 16) & (1 << 4)) | ((insn >> 4) & (15 << 0)));
427 case 0 : /* fall through */
428 case 2 : /* fall through */
429 case 4 : /* fall through */
430 case 6 : /* fall through */
431 case 8 : /* fall through */
432 case 10 : /* fall through */
433 case 12 : /* fall through */
434 case 14 : /* fall through */
435 case 16 : /* fall through */
436 case 18 : /* fall through */
437 case 20 : /* fall through */
438 case 22 : /* fall through */
439 case 24 : /* fall through */
440 case 26 : /* fall through */
441 case 28 : /* fall through */
442 case 30 : itype = ARM_INSN_AND_REG_IMM_SHIFT; arm_extract_sfmt_and_reg_imm_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
443 case 1 : /* fall through */
444 case 3 : /* fall through */
445 case 5 : /* fall through */
446 case 7 : /* fall through */
447 case 17 : /* fall through */
448 case 19 : /* fall through */
449 case 21 : /* fall through */
450 case 23 : itype = ARM_INSN_AND_REG_REG_SHIFT; arm_extract_sfmt_and_reg_reg_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
451 case 9 : /* fall through */
452 case 25 : itype = ARM_INSN_MUL; arm_extract_sfmt_mul (this, current_cpu, pc, base_insn, entire_insn); goto done;
454 if ((entire_insn & 0xff00ff0) == 0xb0)
455 { itype = ARM_INSN_STRH_POST_DEC_REG_OFFSET; arm_extract_sfmt_strh_pre_dec_wb_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
456 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
458 if ((entire_insn & 0xff00ff0) == 0x1000b0)
459 { itype = ARM_INSN_LDRH_POST_DEC_REG_OFFSET; arm_extract_sfmt_ldrh_pre_dec_wb_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
460 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
462 if ((entire_insn & 0xff00ff0) == 0x1000d0)
463 { itype = ARM_INSN_LDRSB_POST_DEC_REG_OFFSET; arm_extract_sfmt_ldrsb_pre_dec_wb_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
464 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
466 if ((entire_insn & 0xff00ff0) == 0x1000f0)
467 { itype = ARM_INSN_LDRSH_POST_DEC_REG_OFFSET; arm_extract_sfmt_ldrh_pre_dec_wb_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
468 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
469 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
474 unsigned int val = (((insn >> 6) & (1 << 1)) | ((insn >> 4) & (1 << 0)));
477 case 0 : /* fall through */
478 case 2 : itype = ARM_INSN_EOR_REG_IMM_SHIFT; arm_extract_sfmt_and_reg_imm_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
479 case 1 : itype = ARM_INSN_EOR_REG_REG_SHIFT; arm_extract_sfmt_and_reg_reg_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
481 if ((entire_insn & 0xfe000f0) == 0x200090)
482 { itype = ARM_INSN_MLA; arm_extract_sfmt_mla (this, current_cpu, pc, base_insn, entire_insn); goto done; }
483 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
484 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
489 unsigned int val = (((insn >> 16) & (1 << 4)) | ((insn >> 4) & (15 << 0)));
492 case 0 : /* fall through */
493 case 2 : /* fall through */
494 case 4 : /* fall through */
495 case 6 : /* fall through */
496 case 8 : /* fall through */
497 case 10 : /* fall through */
498 case 12 : /* fall through */
499 case 14 : /* fall through */
500 case 16 : /* fall through */
501 case 18 : /* fall through */
502 case 20 : /* fall through */
503 case 22 : /* fall through */
504 case 24 : /* fall through */
505 case 26 : /* fall through */
506 case 28 : /* fall through */
507 case 30 : itype = ARM_INSN_SUB_REG_IMM_SHIFT; arm_extract_sfmt_add_reg_imm_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
508 case 1 : /* fall through */
509 case 3 : /* fall through */
510 case 5 : /* fall through */
511 case 7 : /* fall through */
512 case 17 : /* fall through */
513 case 19 : /* fall through */
514 case 21 : /* fall through */
515 case 23 : itype = ARM_INSN_SUB_REG_REG_SHIFT; arm_extract_sfmt_add_reg_reg_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
516 case 11 : itype = ARM_INSN_STRH_POST_DEC_IMM_OFFSET; arm_extract_sfmt_strh_pre_dec_wb_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
517 case 27 : itype = ARM_INSN_LDRH_POST_DEC_IMM_OFFSET; arm_extract_sfmt_ldrh_pre_dec_wb_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
518 case 29 : itype = ARM_INSN_LDRSB_POST_DEC_IMM_OFFSET; arm_extract_sfmt_ldrsb_pre_dec_wb_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
519 case 31 : itype = ARM_INSN_LDRSH_POST_DEC_IMM_OFFSET; arm_extract_sfmt_ldrh_pre_dec_wb_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
520 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
525 unsigned int val = (((insn >> 4) & (1 << 0)));
528 case 0 : itype = ARM_INSN_RSB_REG_IMM_SHIFT; arm_extract_sfmt_add_reg_imm_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
530 if ((entire_insn & 0xfe00090) == 0x600010)
531 { itype = ARM_INSN_RSB_REG_REG_SHIFT; arm_extract_sfmt_add_reg_reg_shift (this, current_cpu, pc, base_insn, entire_insn); goto done; }
532 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
533 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
538 unsigned int val = (((insn >> 16) & (1 << 4)) | ((insn >> 4) & (15 << 0)));
541 case 0 : /* fall through */
542 case 2 : /* fall through */
543 case 4 : /* fall through */
544 case 6 : /* fall through */
545 case 8 : /* fall through */
546 case 10 : /* fall through */
547 case 12 : /* fall through */
548 case 14 : /* fall through */
549 case 16 : /* fall through */
550 case 18 : /* fall through */
551 case 20 : /* fall through */
552 case 22 : /* fall through */
553 case 24 : /* fall through */
554 case 26 : /* fall through */
555 case 28 : /* fall through */
556 case 30 : itype = ARM_INSN_ADD_REG_IMM_SHIFT; arm_extract_sfmt_add_reg_imm_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
557 case 1 : /* fall through */
558 case 3 : /* fall through */
559 case 5 : /* fall through */
560 case 7 : /* fall through */
561 case 17 : /* fall through */
562 case 19 : /* fall through */
563 case 21 : /* fall through */
564 case 23 : itype = ARM_INSN_ADD_REG_REG_SHIFT; arm_extract_sfmt_add_reg_reg_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
565 case 9 : /* fall through */
566 case 25 : itype = ARM_INSN_UMULL; arm_extract_sfmt_umull (this, current_cpu, pc, base_insn, entire_insn); goto done;
568 if ((entire_insn & 0xff00ff0) == 0x8000b0)
569 { itype = ARM_INSN_STRH_POST_INC_REG_OFFSET; arm_extract_sfmt_strh_pre_dec_wb_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
570 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
572 if ((entire_insn & 0xff00ff0) == 0x9000b0)
573 { itype = ARM_INSN_LDRH_POST_INC_REG_OFFSET; arm_extract_sfmt_ldrh_pre_dec_wb_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
574 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
576 if ((entire_insn & 0xff00ff0) == 0x9000d0)
577 { itype = ARM_INSN_LDRSB_POST_INC_REG_OFFSET; arm_extract_sfmt_ldrsb_pre_dec_wb_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
578 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
580 if ((entire_insn & 0xff00ff0) == 0x9000f0)
581 { itype = ARM_INSN_LDRSH_POST_INC_REG_OFFSET; arm_extract_sfmt_ldrh_pre_dec_wb_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
582 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
583 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
588 unsigned int val = (((insn >> 6) & (1 << 1)) | ((insn >> 4) & (1 << 0)));
591 case 0 : /* fall through */
592 case 2 : itype = ARM_INSN_ADC_REG_IMM_SHIFT; arm_extract_sfmt_adc_reg_imm_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
593 case 1 : itype = ARM_INSN_ADC_REG_REG_SHIFT; arm_extract_sfmt_adc_reg_reg_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
595 if ((entire_insn & 0xfe000f0) == 0xa00090)
596 { itype = ARM_INSN_UMLAL; arm_extract_sfmt_umlal (this, current_cpu, pc, base_insn, entire_insn); goto done; }
597 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
598 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
603 unsigned int val = (((insn >> 16) & (1 << 4)) | ((insn >> 4) & (15 << 0)));
606 case 0 : /* fall through */
607 case 2 : /* fall through */
608 case 4 : /* fall through */
609 case 6 : /* fall through */
610 case 8 : /* fall through */
611 case 10 : /* fall through */
612 case 12 : /* fall through */
613 case 14 : /* fall through */
614 case 16 : /* fall through */
615 case 18 : /* fall through */
616 case 20 : /* fall through */
617 case 22 : /* fall through */
618 case 24 : /* fall through */
619 case 26 : /* fall through */
620 case 28 : /* fall through */
621 case 30 : itype = ARM_INSN_SBC_REG_IMM_SHIFT; arm_extract_sfmt_adc_reg_imm_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
622 case 1 : /* fall through */
623 case 3 : /* fall through */
624 case 5 : /* fall through */
625 case 7 : /* fall through */
626 case 17 : /* fall through */
627 case 19 : /* fall through */
628 case 21 : /* fall through */
629 case 23 : itype = ARM_INSN_SBC_REG_REG_SHIFT; arm_extract_sfmt_adc_reg_reg_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
630 case 9 : /* fall through */
631 case 25 : itype = ARM_INSN_SMULL; arm_extract_sfmt_umull (this, current_cpu, pc, base_insn, entire_insn); goto done;
632 case 11 : itype = ARM_INSN_STRH_POST_INC_IMM_OFFSET; arm_extract_sfmt_strh_pre_dec_wb_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
633 case 27 : itype = ARM_INSN_LDRH_POST_INC_IMM_OFFSET; arm_extract_sfmt_ldrh_pre_dec_wb_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
634 case 29 : itype = ARM_INSN_LDRSB_POST_INC_IMM_OFFSET; arm_extract_sfmt_ldrsb_pre_dec_wb_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
635 case 31 : itype = ARM_INSN_LDRSH_POST_INC_IMM_OFFSET; arm_extract_sfmt_ldrh_pre_dec_wb_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
636 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
641 unsigned int val = (((insn >> 6) & (1 << 1)) | ((insn >> 4) & (1 << 0)));
644 case 0 : /* fall through */
645 case 2 : itype = ARM_INSN_RSC_REG_IMM_SHIFT; arm_extract_sfmt_adc_reg_imm_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
646 case 1 : itype = ARM_INSN_RSC_REG_REG_SHIFT; arm_extract_sfmt_adc_reg_reg_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
648 if ((entire_insn & 0xfe000f0) == 0xe00090)
649 { itype = ARM_INSN_SMLAL; arm_extract_sfmt_umlal (this, current_cpu, pc, base_insn, entire_insn); goto done; }
650 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
651 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
656 unsigned int val = (((insn >> 16) & (1 << 4)) | ((insn >> 4) & (15 << 0)));
660 if ((entire_insn & 0xfff0fff) == 0x10f0000)
661 { itype = ARM_INSN_MRS_C; arm_extract_sfmt_mrs_c (this, current_cpu, pc, base_insn, entire_insn); goto done; }
662 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
664 if ((entire_insn & 0xff00ff0) == 0x1000090)
665 { itype = ARM_INSN_SWP; arm_extract_sfmt_swp (this, current_cpu, pc, base_insn, entire_insn); goto done; }
666 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
668 if ((entire_insn & 0xff00ff0) == 0x10000b0)
669 { itype = ARM_INSN_STRH_PRE_DEC_REG_OFFSET; arm_extract_sfmt_strh_pre_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
670 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
671 case 16 : /* fall through */
672 case 18 : /* fall through */
673 case 20 : /* fall through */
674 case 22 : /* fall through */
675 case 24 : /* fall through */
676 case 26 : /* fall through */
677 case 28 : /* fall through */
678 case 30 : itype = ARM_INSN_TST_REG_IMM_SHIFT; arm_extract_sfmt_tst_reg_imm_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
679 case 17 : /* fall through */
680 case 19 : /* fall through */
681 case 21 : /* fall through */
682 case 23 : itype = ARM_INSN_TST_REG_REG_SHIFT; arm_extract_sfmt_tst_reg_reg_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
684 if ((entire_insn & 0xff00ff0) == 0x11000b0)
685 { itype = ARM_INSN_LDRH_PRE_DEC_REG_OFFSET; arm_extract_sfmt_ldrh_pre_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
686 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
688 if ((entire_insn & 0xff00ff0) == 0x11000d0)
689 { itype = ARM_INSN_LDRSB_PRE_DEC_REG_OFFSET; arm_extract_sfmt_ldrsb_pre_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
690 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
692 if ((entire_insn & 0xff00ff0) == 0x11000f0)
693 { itype = ARM_INSN_LDRSH_PRE_DEC_REG_OFFSET; arm_extract_sfmt_ldrh_pre_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
694 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
695 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
700 unsigned int val = (((insn >> 14) & (1 << 6)) | ((insn >> 4) & (63 << 0)));
704 if ((entire_insn & 0xffffff0) == 0x129f000)
705 { itype = ARM_INSN_MSR_C; arm_extract_sfmt_msr_c (this, current_cpu, pc, base_insn, entire_insn); goto done; }
706 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
708 if ((entire_insn & 0xff00ff0) == 0x12000b0)
709 { itype = ARM_INSN_STRH_PRE_DEC_WB_REG_OFFSET; arm_extract_sfmt_strh_pre_dec_wb_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
710 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
712 if ((entire_insn & 0xffffff0) == 0x12fff10)
713 { itype = ARM_INSN_BX; arm_extract_sfmt_bx (this, current_cpu, pc, base_insn, entire_insn); goto done; }
714 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
715 case 64 : /* fall through */
716 case 66 : /* fall through */
717 case 68 : /* fall through */
718 case 70 : /* fall through */
719 case 72 : /* fall through */
720 case 74 : /* fall through */
721 case 76 : /* fall through */
722 case 78 : /* fall through */
723 case 80 : /* fall through */
724 case 82 : /* fall through */
725 case 84 : /* fall through */
726 case 86 : /* fall through */
727 case 88 : /* fall through */
728 case 90 : /* fall through */
729 case 92 : /* fall through */
730 case 94 : /* fall through */
731 case 96 : /* fall through */
732 case 98 : /* fall through */
733 case 100 : /* fall through */
734 case 102 : /* fall through */
735 case 104 : /* fall through */
736 case 106 : /* fall through */
737 case 108 : /* fall through */
738 case 110 : /* fall through */
739 case 112 : /* fall through */
740 case 114 : /* fall through */
741 case 116 : /* fall through */
742 case 118 : /* fall through */
743 case 120 : /* fall through */
744 case 122 : /* fall through */
745 case 124 : /* fall through */
746 case 126 : itype = ARM_INSN_TEQ_REG_IMM_SHIFT; arm_extract_sfmt_tst_reg_imm_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
747 case 65 : /* fall through */
748 case 67 : /* fall through */
749 case 69 : /* fall through */
750 case 71 : /* fall through */
751 case 81 : /* fall through */
752 case 83 : /* fall through */
753 case 85 : /* fall through */
754 case 87 : /* fall through */
755 case 97 : /* fall through */
756 case 99 : /* fall through */
757 case 101 : /* fall through */
758 case 103 : /* fall through */
759 case 113 : /* fall through */
760 case 115 : /* fall through */
761 case 117 : /* fall through */
762 case 119 : itype = ARM_INSN_TEQ_REG_REG_SHIFT; arm_extract_sfmt_tst_reg_reg_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
764 if ((entire_insn & 0xff00ff0) == 0x13000b0)
765 { itype = ARM_INSN_LDRH_PRE_DEC_WB_REG_OFFSET; arm_extract_sfmt_ldrh_pre_dec_wb_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
766 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
768 if ((entire_insn & 0xff00ff0) == 0x13000d0)
769 { itype = ARM_INSN_LDRSB_PRE_DEC_WB_REG_OFFSET; arm_extract_sfmt_ldrsb_pre_dec_wb_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
770 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
772 if ((entire_insn & 0xff00ff0) == 0x13000f0)
773 { itype = ARM_INSN_LDRSH_PRE_DEC_WB_REG_OFFSET; arm_extract_sfmt_ldrh_pre_dec_wb_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
774 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
775 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
780 unsigned int val = (((insn >> 16) & (1 << 4)) | ((insn >> 4) & (15 << 0)));
784 if ((entire_insn & 0xfff0fff) == 0x14f0000)
785 { itype = ARM_INSN_MRS_S; arm_extract_sfmt_mrs_s (this, current_cpu, pc, base_insn, entire_insn); goto done; }
786 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
788 if ((entire_insn & 0xff00ff0) == 0x1400090)
789 { itype = ARM_INSN_SWPB; arm_extract_sfmt_swpb (this, current_cpu, pc, base_insn, entire_insn); goto done; }
790 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
791 case 11 : itype = ARM_INSN_STRH_PRE_DEC_IMM_OFFSET; arm_extract_sfmt_strh_pre_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
792 case 16 : /* fall through */
793 case 18 : /* fall through */
794 case 20 : /* fall through */
795 case 22 : /* fall through */
796 case 24 : /* fall through */
797 case 26 : /* fall through */
798 case 28 : /* fall through */
799 case 30 : itype = ARM_INSN_CMP_REG_IMM_SHIFT; arm_extract_sfmt_cmp_reg_imm_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
800 case 17 : /* fall through */
801 case 19 : /* fall through */
802 case 21 : /* fall through */
803 case 23 : itype = ARM_INSN_CMP_REG_REG_SHIFT; arm_extract_sfmt_cmp_reg_reg_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
804 case 27 : itype = ARM_INSN_LDRH_PRE_DEC_IMM_OFFSET; arm_extract_sfmt_ldrh_pre_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
805 case 29 : itype = ARM_INSN_LDRSB_PRE_DEC_IMM_OFFSET; arm_extract_sfmt_ldrsb_pre_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
806 case 31 : itype = ARM_INSN_LDRSH_PRE_DEC_IMM_OFFSET; arm_extract_sfmt_ldrh_pre_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
807 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
812 unsigned int val = (((insn >> 16) & (1 << 4)) | ((insn >> 4) & (15 << 0)));
816 if ((entire_insn & 0xffffff0) == 0x169f000)
817 { itype = ARM_INSN_MSR_S; arm_extract_sfmt_msr_s (this, current_cpu, pc, base_insn, entire_insn); goto done; }
818 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
819 case 11 : itype = ARM_INSN_STRH_PRE_DEC_WB_IMM_OFFSET; arm_extract_sfmt_strh_pre_dec_wb_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
820 case 16 : /* fall through */
821 case 18 : /* fall through */
822 case 20 : /* fall through */
823 case 22 : /* fall through */
824 case 24 : /* fall through */
825 case 26 : /* fall through */
826 case 28 : /* fall through */
827 case 30 : itype = ARM_INSN_CMN_REG_IMM_SHIFT; arm_extract_sfmt_cmp_reg_imm_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
828 case 17 : /* fall through */
829 case 19 : /* fall through */
830 case 21 : /* fall through */
831 case 23 : itype = ARM_INSN_CMN_REG_REG_SHIFT; arm_extract_sfmt_cmp_reg_reg_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
832 case 27 : itype = ARM_INSN_LDRH_PRE_DEC_WB_IMM_OFFSET; arm_extract_sfmt_ldrh_pre_dec_wb_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
833 case 29 : itype = ARM_INSN_LDRSB_PRE_DEC_WB_IMM_OFFSET; arm_extract_sfmt_ldrsb_pre_dec_wb_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
834 case 31 : itype = ARM_INSN_LDRSH_PRE_DEC_WB_IMM_OFFSET; arm_extract_sfmt_ldrh_pre_dec_wb_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
835 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
840 unsigned int val = (((insn >> 16) & (1 << 4)) | ((insn >> 4) & (15 << 0)));
843 case 0 : /* fall through */
844 case 2 : /* fall through */
845 case 4 : /* fall through */
846 case 6 : /* fall through */
847 case 8 : /* fall through */
848 case 10 : /* fall through */
849 case 12 : /* fall through */
850 case 14 : /* fall through */
851 case 16 : /* fall through */
852 case 18 : /* fall through */
853 case 20 : /* fall through */
854 case 22 : /* fall through */
855 case 24 : /* fall through */
856 case 26 : /* fall through */
857 case 28 : /* fall through */
858 case 30 : itype = ARM_INSN_ORR_REG_IMM_SHIFT; arm_extract_sfmt_and_reg_imm_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
859 case 1 : /* fall through */
860 case 3 : /* fall through */
861 case 5 : /* fall through */
862 case 7 : /* fall through */
863 case 17 : /* fall through */
864 case 19 : /* fall through */
865 case 21 : /* fall through */
866 case 23 : itype = ARM_INSN_ORR_REG_REG_SHIFT; arm_extract_sfmt_and_reg_reg_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
868 if ((entire_insn & 0xff00ff0) == 0x18000b0)
869 { itype = ARM_INSN_STRH_PRE_INC_REG_OFFSET; arm_extract_sfmt_strh_pre_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
870 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
872 if ((entire_insn & 0xff00ff0) == 0x19000b0)
873 { itype = ARM_INSN_LDRH_PRE_INC_REG_OFFSET; arm_extract_sfmt_ldrh_pre_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
874 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
876 if ((entire_insn & 0xff00ff0) == 0x19000d0)
877 { itype = ARM_INSN_LDRSB_PRE_INC_REG_OFFSET; arm_extract_sfmt_ldrsb_pre_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
878 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
880 if ((entire_insn & 0xff00ff0) == 0x19000f0)
881 { itype = ARM_INSN_LDRSH_PRE_INC_REG_OFFSET; arm_extract_sfmt_ldrh_pre_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
882 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
883 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
888 unsigned int val = (((insn >> 16) & (1 << 4)) | ((insn >> 4) & (15 << 0)));
891 case 0 : /* fall through */
892 case 2 : /* fall through */
893 case 4 : /* fall through */
894 case 6 : /* fall through */
895 case 8 : /* fall through */
896 case 10 : /* fall through */
897 case 12 : /* fall through */
898 case 14 : /* fall through */
899 case 16 : /* fall through */
900 case 18 : /* fall through */
901 case 20 : /* fall through */
902 case 22 : /* fall through */
903 case 24 : /* fall through */
904 case 26 : /* fall through */
905 case 28 : /* fall through */
906 case 30 : itype = ARM_INSN_MOV_REG_IMM_SHIFT; arm_extract_sfmt_mov_reg_imm_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
907 case 1 : /* fall through */
908 case 3 : /* fall through */
909 case 5 : /* fall through */
910 case 7 : /* fall through */
911 case 17 : /* fall through */
912 case 19 : /* fall through */
913 case 21 : /* fall through */
914 case 23 : itype = ARM_INSN_MOV_REG_REG_SHIFT; arm_extract_sfmt_mov_reg_reg_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
916 if ((entire_insn & 0xff00ff0) == 0x1a000b0)
917 { itype = ARM_INSN_STRH_PRE_INC_WB_REG_OFFSET; arm_extract_sfmt_strh_pre_dec_wb_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
918 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
920 if ((entire_insn & 0xff00ff0) == 0x1b000b0)
921 { itype = ARM_INSN_LDRH_PRE_INC_WB_REG_OFFSET; arm_extract_sfmt_ldrh_pre_dec_wb_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
922 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
924 if ((entire_insn & 0xff00ff0) == 0x1b000d0)
925 { itype = ARM_INSN_LDRSB_PRE_INC_WB_REG_OFFSET; arm_extract_sfmt_ldrsb_pre_dec_wb_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
926 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
928 if ((entire_insn & 0xff00ff0) == 0x1b000f0)
929 { itype = ARM_INSN_LDRSH_PRE_INC_WB_REG_OFFSET; arm_extract_sfmt_ldrh_pre_dec_wb_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
930 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
931 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
936 unsigned int val = (((insn >> 16) & (1 << 4)) | ((insn >> 4) & (15 << 0)));
939 case 0 : /* fall through */
940 case 2 : /* fall through */
941 case 4 : /* fall through */
942 case 6 : /* fall through */
943 case 8 : /* fall through */
944 case 10 : /* fall through */
945 case 12 : /* fall through */
946 case 14 : /* fall through */
947 case 16 : /* fall through */
948 case 18 : /* fall through */
949 case 20 : /* fall through */
950 case 22 : /* fall through */
951 case 24 : /* fall through */
952 case 26 : /* fall through */
953 case 28 : /* fall through */
954 case 30 : itype = ARM_INSN_BIC_REG_IMM_SHIFT; arm_extract_sfmt_and_reg_imm_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
955 case 1 : /* fall through */
956 case 3 : /* fall through */
957 case 5 : /* fall through */
958 case 7 : /* fall through */
959 case 17 : /* fall through */
960 case 19 : /* fall through */
961 case 21 : /* fall through */
962 case 23 : itype = ARM_INSN_BIC_REG_REG_SHIFT; arm_extract_sfmt_and_reg_reg_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
963 case 11 : itype = ARM_INSN_STRH_PRE_INC_IMM_OFFSET; arm_extract_sfmt_strh_pre_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
964 case 27 : itype = ARM_INSN_LDRH_PRE_INC_IMM_OFFSET; arm_extract_sfmt_ldrh_pre_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
965 case 29 : itype = ARM_INSN_LDRSB_PRE_INC_IMM_OFFSET; arm_extract_sfmt_ldrsb_pre_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
966 case 31 : itype = ARM_INSN_LDRSH_PRE_INC_IMM_OFFSET; arm_extract_sfmt_ldrh_pre_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
967 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
972 unsigned int val = (((insn >> 16) & (1 << 4)) | ((insn >> 4) & (15 << 0)));
975 case 0 : /* fall through */
976 case 2 : /* fall through */
977 case 4 : /* fall through */
978 case 6 : /* fall through */
979 case 8 : /* fall through */
980 case 10 : /* fall through */
981 case 12 : /* fall through */
982 case 14 : /* fall through */
983 case 16 : /* fall through */
984 case 18 : /* fall through */
985 case 20 : /* fall through */
986 case 22 : /* fall through */
987 case 24 : /* fall through */
988 case 26 : /* fall through */
989 case 28 : /* fall through */
990 case 30 : itype = ARM_INSN_MVN_REG_IMM_SHIFT; arm_extract_sfmt_mov_reg_imm_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
991 case 1 : /* fall through */
992 case 3 : /* fall through */
993 case 5 : /* fall through */
994 case 7 : /* fall through */
995 case 17 : /* fall through */
996 case 19 : /* fall through */
997 case 21 : /* fall through */
998 case 23 : itype = ARM_INSN_MVN_REG_REG_SHIFT; arm_extract_sfmt_mov_reg_reg_shift (this, current_cpu, pc, base_insn, entire_insn); goto done;
999 case 11 : itype = ARM_INSN_STRH_PRE_INC_WB_IMM_OFFSET; arm_extract_sfmt_strh_pre_dec_wb_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1000 case 27 : itype = ARM_INSN_LDRH_PRE_INC_WB_IMM_OFFSET; arm_extract_sfmt_ldrh_pre_dec_wb_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1001 case 29 : itype = ARM_INSN_LDRSB_PRE_INC_WB_IMM_OFFSET; arm_extract_sfmt_ldrsb_pre_dec_wb_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1002 case 31 : itype = ARM_INSN_LDRSH_PRE_INC_WB_IMM_OFFSET; arm_extract_sfmt_ldrh_pre_dec_wb_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1003 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1006 case 16 : itype = ARM_INSN_AND_IMM; arm_extract_sfmt_and_imm (this, current_cpu, pc, base_insn, entire_insn); goto done;
1007 case 17 : itype = ARM_INSN_EOR_IMM; arm_extract_sfmt_and_imm (this, current_cpu, pc, base_insn, entire_insn); goto done;
1008 case 18 : itype = ARM_INSN_SUB_IMM; arm_extract_sfmt_add_imm (this, current_cpu, pc, base_insn, entire_insn); goto done;
1009 case 19 : itype = ARM_INSN_RSB_IMM; arm_extract_sfmt_add_imm (this, current_cpu, pc, base_insn, entire_insn); goto done;
1010 case 20 : itype = ARM_INSN_ADD_IMM; arm_extract_sfmt_add_imm (this, current_cpu, pc, base_insn, entire_insn); goto done;
1011 case 21 : itype = ARM_INSN_ADC_IMM; arm_extract_sfmt_adc_imm (this, current_cpu, pc, base_insn, entire_insn); goto done;
1012 case 22 : itype = ARM_INSN_SBC_IMM; arm_extract_sfmt_adc_imm (this, current_cpu, pc, base_insn, entire_insn); goto done;
1013 case 23 : itype = ARM_INSN_RSC_IMM; arm_extract_sfmt_adc_imm (this, current_cpu, pc, base_insn, entire_insn); goto done;
1015 if ((entire_insn & 0xff00000) == 0x3100000)
1016 { itype = ARM_INSN_TST_IMM; arm_extract_sfmt_tst_imm (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1017 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1019 if ((entire_insn & 0xff00000) == 0x3300000)
1020 { itype = ARM_INSN_TEQ_IMM; arm_extract_sfmt_tst_imm (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1021 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1023 if ((entire_insn & 0xff00000) == 0x3500000)
1024 { itype = ARM_INSN_CMP_IMM; arm_extract_sfmt_cmp_imm (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1025 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1027 if ((entire_insn & 0xff00000) == 0x3700000)
1028 { itype = ARM_INSN_CMN_IMM; arm_extract_sfmt_cmp_imm (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1029 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1030 case 28 : itype = ARM_INSN_ORR_IMM; arm_extract_sfmt_and_imm (this, current_cpu, pc, base_insn, entire_insn); goto done;
1031 case 29 : itype = ARM_INSN_MOV_IMM; arm_extract_sfmt_mov_imm (this, current_cpu, pc, base_insn, entire_insn); goto done;
1032 case 30 : itype = ARM_INSN_BIC_IMM; arm_extract_sfmt_and_imm (this, current_cpu, pc, base_insn, entire_insn); goto done;
1033 case 31 : itype = ARM_INSN_MVN_IMM; arm_extract_sfmt_mov_imm (this, current_cpu, pc, base_insn, entire_insn); goto done;
1036 unsigned int val = (((insn >> 20) & (1 << 0)));
1039 case 0 : itype = ARM_INSN_STR_POST_DEC_IMM_OFFSET; arm_extract_sfmt_str_post_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1040 case 1 : itype = ARM_INSN_LDR_POST_DEC_IMM_OFFSET; arm_extract_sfmt_ldr_post_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1041 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1046 unsigned int val = (((insn >> 20) & (1 << 0)));
1049 case 0 : itype = ARM_INSN_STR_POST_DEC_NONPRIV_IMM_OFFSET; arm_extract_sfmt_str_post_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1050 case 1 : itype = ARM_INSN_LDR_POST_DEC_NONPRIV_IMM_OFFSET; arm_extract_sfmt_ldr_post_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1051 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1056 unsigned int val = (((insn >> 20) & (1 << 0)));
1059 case 0 : itype = ARM_INSN_STRB_POST_DEC_IMM_OFFSET; arm_extract_sfmt_strb_post_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1060 case 1 : itype = ARM_INSN_LDRB_POST_DEC_IMM_OFFSET; arm_extract_sfmt_ldrb_post_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1061 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1066 unsigned int val = (((insn >> 20) & (1 << 0)));
1069 case 0 : itype = ARM_INSN_STRB_POST_DEC_NONPRIV_IMM_OFFSET; arm_extract_sfmt_strb_post_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1070 case 1 : itype = ARM_INSN_LDRB_POST_DEC_NONPRIV_IMM_OFFSET; arm_extract_sfmt_ldrb_post_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1071 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1076 unsigned int val = (((insn >> 20) & (1 << 0)));
1079 case 0 : itype = ARM_INSN_STR_POST_INC_IMM_OFFSET; arm_extract_sfmt_str_post_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1080 case 1 : itype = ARM_INSN_LDR_POST_INC_IMM_OFFSET; arm_extract_sfmt_ldr_post_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1081 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1086 unsigned int val = (((insn >> 20) & (1 << 0)));
1089 case 0 : itype = ARM_INSN_STR_POST_INC_NONPRIV_IMM_OFFSET; arm_extract_sfmt_str_post_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1090 case 1 : itype = ARM_INSN_LDR_POST_INC_NONPRIV_IMM_OFFSET; arm_extract_sfmt_ldr_post_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1091 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1096 unsigned int val = (((insn >> 20) & (1 << 0)));
1099 case 0 : itype = ARM_INSN_STRB_POST_INC_IMM_OFFSET; arm_extract_sfmt_strb_post_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1100 case 1 : itype = ARM_INSN_LDRB_POST_INC_IMM_OFFSET; arm_extract_sfmt_ldrb_post_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1101 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1106 unsigned int val = (((insn >> 20) & (1 << 0)));
1109 case 0 : itype = ARM_INSN_STRB_POST_INC_NONPRIV_IMM_OFFSET; arm_extract_sfmt_strb_post_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1110 case 1 : itype = ARM_INSN_LDRB_POST_INC_NONPRIV_IMM_OFFSET; arm_extract_sfmt_ldrb_post_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1111 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1116 unsigned int val = (((insn >> 20) & (1 << 0)));
1119 case 0 : itype = ARM_INSN_STR_PRE_DEC_IMM_OFFSET; arm_extract_sfmt_str_pre_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1120 case 1 : itype = ARM_INSN_LDR_PRE_DEC_IMM_OFFSET; arm_extract_sfmt_ldr_pre_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1121 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1126 unsigned int val = (((insn >> 20) & (1 << 0)));
1129 case 0 : itype = ARM_INSN_STR_PRE_DEC_WB_IMM_OFFSET; arm_extract_sfmt_str_post_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1130 case 1 : itype = ARM_INSN_LDR_PRE_DEC_WB_IMM_OFFSET; arm_extract_sfmt_ldr_post_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1131 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1136 unsigned int val = (((insn >> 20) & (1 << 0)));
1139 case 0 : itype = ARM_INSN_STRB_PRE_DEC_IMM_OFFSET; arm_extract_sfmt_strb_pre_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1140 case 1 : itype = ARM_INSN_LDRB_PRE_DEC_IMM_OFFSET; arm_extract_sfmt_ldrb_pre_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1141 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1146 unsigned int val = (((insn >> 20) & (1 << 0)));
1149 case 0 : itype = ARM_INSN_STRB_PRE_DEC_WB_IMM_OFFSET; arm_extract_sfmt_strb_post_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1150 case 1 : itype = ARM_INSN_LDRB_PRE_DEC_WB_IMM_OFFSET; arm_extract_sfmt_ldrb_post_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1151 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1156 unsigned int val = (((insn >> 20) & (1 << 0)));
1159 case 0 : itype = ARM_INSN_STR_PRE_INC_IMM_OFFSET; arm_extract_sfmt_str_pre_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1160 case 1 : itype = ARM_INSN_LDR_PRE_INC_IMM_OFFSET; arm_extract_sfmt_ldr_pre_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1161 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1166 unsigned int val = (((insn >> 20) & (1 << 0)));
1169 case 0 : itype = ARM_INSN_STR_PRE_INC_WB_IMM_OFFSET; arm_extract_sfmt_str_post_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1170 case 1 : itype = ARM_INSN_LDR_PRE_INC_WB_IMM_OFFSET; arm_extract_sfmt_ldr_post_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1171 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1176 unsigned int val = (((insn >> 20) & (1 << 0)));
1179 case 0 : itype = ARM_INSN_STRB_PRE_INC_IMM_OFFSET; arm_extract_sfmt_strb_pre_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1180 case 1 : itype = ARM_INSN_LDRB_PRE_INC_IMM_OFFSET; arm_extract_sfmt_ldrb_pre_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1181 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1186 unsigned int val = (((insn >> 20) & (1 << 0)));
1189 case 0 : itype = ARM_INSN_STRB_PRE_INC_WB_IMM_OFFSET; arm_extract_sfmt_strb_post_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1190 case 1 : itype = ARM_INSN_LDRB_PRE_INC_WB_IMM_OFFSET; arm_extract_sfmt_ldrb_post_dec_imm_offset (this, current_cpu, pc, base_insn, entire_insn); goto done;
1191 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1196 unsigned int val = (((insn >> 20) & (1 << 0)));
1200 if ((entire_insn & 0xff00010) == 0x6000000)
1201 { itype = ARM_INSN_STR_POST_DEC_REG_OFFSET; arm_extract_sfmt_str_post_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1202 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1204 if ((entire_insn & 0xff00010) == 0x6100000)
1205 { itype = ARM_INSN_LDR_POST_DEC_REG_OFFSET; arm_extract_sfmt_ldr_post_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1206 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1207 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1212 unsigned int val = (((insn >> 20) & (1 << 0)));
1216 if ((entire_insn & 0xff00010) == 0x6200000)
1217 { itype = ARM_INSN_STR_POST_DEC_NONPRIV_REG_OFFSET; arm_extract_sfmt_str_post_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1218 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1220 if ((entire_insn & 0xff00010) == 0x6300000)
1221 { itype = ARM_INSN_LDR_POST_DEC_NONPRIV_REG_OFFSET; arm_extract_sfmt_ldr_post_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1222 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1223 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1228 unsigned int val = (((insn >> 20) & (1 << 0)));
1232 if ((entire_insn & 0xff00010) == 0x6400000)
1233 { itype = ARM_INSN_STRB_POST_DEC_REG_OFFSET; arm_extract_sfmt_strb_post_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1234 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1236 if ((entire_insn & 0xff00010) == 0x6500000)
1237 { itype = ARM_INSN_LDRB_POST_DEC_REG_OFFSET; arm_extract_sfmt_ldrb_post_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1238 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1239 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1244 unsigned int val = (((insn >> 20) & (1 << 0)));
1248 if ((entire_insn & 0xff00010) == 0x6600000)
1249 { itype = ARM_INSN_STRB_POST_DEC_NONPRIV_REG_OFFSET; arm_extract_sfmt_strb_post_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1250 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1252 if ((entire_insn & 0xff00010) == 0x6700000)
1253 { itype = ARM_INSN_LDRB_POST_DEC_NONPRIV_REG_OFFSET; arm_extract_sfmt_ldrb_post_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1254 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1255 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1260 unsigned int val = (((insn >> 20) & (1 << 0)));
1264 if ((entire_insn & 0xff00010) == 0x6800000)
1265 { itype = ARM_INSN_STR_POST_INC_REG_OFFSET; arm_extract_sfmt_str_post_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1266 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1268 if ((entire_insn & 0xff00010) == 0x6900000)
1269 { itype = ARM_INSN_LDR_POST_INC_REG_OFFSET; arm_extract_sfmt_ldr_post_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1270 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1271 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1276 unsigned int val = (((insn >> 20) & (1 << 0)));
1280 if ((entire_insn & 0xff00010) == 0x6a00000)
1281 { itype = ARM_INSN_STR_POST_INC_NONPRIV_REG_OFFSET; arm_extract_sfmt_str_post_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1282 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1284 if ((entire_insn & 0xff00010) == 0x6b00000)
1285 { itype = ARM_INSN_LDR_POST_INC_NONPRIV_REG_OFFSET; arm_extract_sfmt_ldr_post_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1286 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1287 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1292 unsigned int val = (((insn >> 20) & (1 << 0)));
1296 if ((entire_insn & 0xff00010) == 0x6c00000)
1297 { itype = ARM_INSN_STRB_POST_INC_REG_OFFSET; arm_extract_sfmt_strb_post_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1298 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1300 if ((entire_insn & 0xff00010) == 0x6d00000)
1301 { itype = ARM_INSN_LDRB_POST_INC_REG_OFFSET; arm_extract_sfmt_ldrb_post_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1302 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1303 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1308 unsigned int val = (((insn >> 20) & (1 << 0)));
1312 if ((entire_insn & 0xff00010) == 0x6e00000)
1313 { itype = ARM_INSN_STRB_POST_INC_NONPRIV_REG_OFFSET; arm_extract_sfmt_strb_post_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1314 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1316 if ((entire_insn & 0xff00010) == 0x6f00000)
1317 { itype = ARM_INSN_LDRB_POST_INC_NONPRIV_REG_OFFSET; arm_extract_sfmt_ldrb_post_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1318 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1319 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1324 unsigned int val = (((insn >> 20) & (1 << 0)));
1328 if ((entire_insn & 0xff00010) == 0x7000000)
1329 { itype = ARM_INSN_STR_PRE_DEC_REG_OFFSET; arm_extract_sfmt_str_pre_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1330 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1332 if ((entire_insn & 0xff00010) == 0x7100000)
1333 { itype = ARM_INSN_LDR_PRE_DEC_REG_OFFSET; arm_extract_sfmt_ldr_pre_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1334 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1335 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1340 unsigned int val = (((insn >> 20) & (1 << 0)));
1344 if ((entire_insn & 0xff00010) == 0x7200000)
1345 { itype = ARM_INSN_STR_PRE_DEC_WB_REG_OFFSET; arm_extract_sfmt_str_post_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1346 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1348 if ((entire_insn & 0xff00010) == 0x7300000)
1349 { itype = ARM_INSN_LDR_PRE_DEC_WB_REG_OFFSET; arm_extract_sfmt_ldr_post_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1350 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1351 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1356 unsigned int val = (((insn >> 20) & (1 << 0)));
1360 if ((entire_insn & 0xff00010) == 0x7400000)
1361 { itype = ARM_INSN_STRB_PRE_DEC_REG_OFFSET; arm_extract_sfmt_strb_pre_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1362 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1364 if ((entire_insn & 0xff00010) == 0x7500000)
1365 { itype = ARM_INSN_LDRB_PRE_DEC_REG_OFFSET; arm_extract_sfmt_ldrb_pre_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1366 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1367 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1372 unsigned int val = (((insn >> 20) & (1 << 0)));
1376 if ((entire_insn & 0xff00010) == 0x7600000)
1377 { itype = ARM_INSN_STRB_PRE_DEC_WB_REG_OFFSET; arm_extract_sfmt_strb_post_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1378 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1380 if ((entire_insn & 0xff00010) == 0x7700000)
1381 { itype = ARM_INSN_LDRB_PRE_DEC_WB_REG_OFFSET; arm_extract_sfmt_ldrb_post_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1382 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1383 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1388 unsigned int val = (((insn >> 20) & (1 << 0)));
1392 if ((entire_insn & 0xff00010) == 0x7800000)
1393 { itype = ARM_INSN_STR_PRE_INC_REG_OFFSET; arm_extract_sfmt_str_pre_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1394 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1396 if ((entire_insn & 0xff00010) == 0x7900000)
1397 { itype = ARM_INSN_LDR_PRE_INC_REG_OFFSET; arm_extract_sfmt_ldr_pre_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1398 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1399 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1404 unsigned int val = (((insn >> 20) & (1 << 0)));
1408 if ((entire_insn & 0xff00010) == 0x7a00000)
1409 { itype = ARM_INSN_STR_PRE_INC_WB_REG_OFFSET; arm_extract_sfmt_str_post_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1410 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1412 if ((entire_insn & 0xff00010) == 0x7b00000)
1413 { itype = ARM_INSN_LDR_PRE_INC_WB_REG_OFFSET; arm_extract_sfmt_ldr_post_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1414 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1415 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1420 unsigned int val = (((insn >> 20) & (1 << 0)));
1424 if ((entire_insn & 0xff00010) == 0x7c00000)
1425 { itype = ARM_INSN_STRB_PRE_INC_REG_OFFSET; arm_extract_sfmt_strb_pre_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1426 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1428 if ((entire_insn & 0xff00010) == 0x7d00000)
1429 { itype = ARM_INSN_LDRB_PRE_INC_REG_OFFSET; arm_extract_sfmt_ldrb_pre_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1430 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1431 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1436 unsigned int val = (((insn >> 20) & (1 << 0)));
1440 if ((entire_insn & 0xff00010) == 0x7e00000)
1441 { itype = ARM_INSN_STRB_PRE_INC_WB_REG_OFFSET; arm_extract_sfmt_strb_post_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1442 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1444 if ((entire_insn & 0xff00010) == 0x7f00000)
1445 { itype = ARM_INSN_LDRB_PRE_INC_WB_REG_OFFSET; arm_extract_sfmt_ldrb_post_dec_reg_offset (this, current_cpu, pc, base_insn, entire_insn); goto done; }
1446 itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1447 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1452 unsigned int val = (((insn >> 20) & (1 << 0)));
1455 case 0 : itype = ARM_INSN_STMDA; arm_extract_sfmt_stmdb (this, current_cpu, pc, base_insn, entire_insn); goto done;
1456 case 1 : itype = ARM_INSN_LDMDA; arm_extract_sfmt_ldmda (this, current_cpu, pc, base_insn, entire_insn); goto done;
1457 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1462 unsigned int val = (((insn >> 20) & (1 << 0)));
1465 case 0 : itype = ARM_INSN_STMDA_WB; arm_extract_sfmt_stmdb_wb (this, current_cpu, pc, base_insn, entire_insn); goto done;
1466 case 1 : itype = ARM_INSN_LDMDA_WB; arm_extract_sfmt_ldmda_wb (this, current_cpu, pc, base_insn, entire_insn); goto done;
1467 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1472 unsigned int val = (((insn >> 20) & (1 << 0)));
1475 case 0 : itype = ARM_INSN_STMDA_SW; arm_extract_sfmt_stmdb_sw (this, current_cpu, pc, base_insn, entire_insn); goto done;
1476 case 1 : itype = ARM_INSN_LDMDA_SW; arm_extract_sfmt_ldmda_sw (this, current_cpu, pc, base_insn, entire_insn); goto done;
1477 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1482 unsigned int val = (((insn >> 20) & (1 << 0)));
1485 case 0 : itype = ARM_INSN_STMDA_SW_WB; arm_extract_sfmt_stmdb_sw_wb (this, current_cpu, pc, base_insn, entire_insn); goto done;
1486 case 1 : itype = ARM_INSN_LDMDA_SW_WB; arm_extract_sfmt_ldmda_sw_wb (this, current_cpu, pc, base_insn, entire_insn); goto done;
1487 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1492 unsigned int val = (((insn >> 20) & (1 << 0)));
1495 case 0 : itype = ARM_INSN_STMIA; arm_extract_sfmt_stmdb (this, current_cpu, pc, base_insn, entire_insn); goto done;
1496 case 1 : itype = ARM_INSN_LDMIA; arm_extract_sfmt_ldmda (this, current_cpu, pc, base_insn, entire_insn); goto done;
1497 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1502 unsigned int val = (((insn >> 20) & (1 << 0)));
1505 case 0 : itype = ARM_INSN_STMIA_WB; arm_extract_sfmt_stmdb_wb (this, current_cpu, pc, base_insn, entire_insn); goto done;
1506 case 1 : itype = ARM_INSN_LDMIA_WB; arm_extract_sfmt_ldmda_wb (this, current_cpu, pc, base_insn, entire_insn); goto done;
1507 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1512 unsigned int val = (((insn >> 20) & (1 << 0)));
1515 case 0 : itype = ARM_INSN_STMIA_SW; arm_extract_sfmt_stmdb_sw (this, current_cpu, pc, base_insn, entire_insn); goto done;
1516 case 1 : itype = ARM_INSN_LDMIA_SW; arm_extract_sfmt_ldmda_sw (this, current_cpu, pc, base_insn, entire_insn); goto done;
1517 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1522 unsigned int val = (((insn >> 20) & (1 << 0)));
1525 case 0 : itype = ARM_INSN_STMIA_SW_WB; arm_extract_sfmt_stmdb_sw_wb (this, current_cpu, pc, base_insn, entire_insn); goto done;
1526 case 1 : itype = ARM_INSN_LDMIA_SW_WB; arm_extract_sfmt_ldmda_sw_wb (this, current_cpu, pc, base_insn, entire_insn); goto done;
1527 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1532 unsigned int val = (((insn >> 20) & (1 << 0)));
1535 case 0 : itype = ARM_INSN_STMDB; arm_extract_sfmt_stmdb (this, current_cpu, pc, base_insn, entire_insn); goto done;
1536 case 1 : itype = ARM_INSN_LDMDB; arm_extract_sfmt_ldmda (this, current_cpu, pc, base_insn, entire_insn); goto done;
1537 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1542 unsigned int val = (((insn >> 20) & (1 << 0)));
1545 case 0 : itype = ARM_INSN_STMDB_WB; arm_extract_sfmt_stmdb_wb (this, current_cpu, pc, base_insn, entire_insn); goto done;
1546 case 1 : itype = ARM_INSN_LDMDB_WB; arm_extract_sfmt_ldmda_wb (this, current_cpu, pc, base_insn, entire_insn); goto done;
1547 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1552 unsigned int val = (((insn >> 20) & (1 << 0)));
1555 case 0 : itype = ARM_INSN_STMDB_SW; arm_extract_sfmt_stmdb_sw (this, current_cpu, pc, base_insn, entire_insn); goto done;
1556 case 1 : itype = ARM_INSN_LDMDB_SW; arm_extract_sfmt_ldmda_sw (this, current_cpu, pc, base_insn, entire_insn); goto done;
1557 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1562 unsigned int val = (((insn >> 20) & (1 << 0)));
1565 case 0 : itype = ARM_INSN_STMDB_SW_WB; arm_extract_sfmt_stmdb_sw_wb (this, current_cpu, pc, base_insn, entire_insn); goto done;
1566 case 1 : itype = ARM_INSN_LDMDB_SW_WB; arm_extract_sfmt_ldmda_sw_wb (this, current_cpu, pc, base_insn, entire_insn); goto done;
1567 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1572 unsigned int val = (((insn >> 20) & (1 << 0)));
1575 case 0 : itype = ARM_INSN_STMIB; arm_extract_sfmt_stmdb (this, current_cpu, pc, base_insn, entire_insn); goto done;
1576 case 1 : itype = ARM_INSN_LDMIB; arm_extract_sfmt_ldmda (this, current_cpu, pc, base_insn, entire_insn); goto done;
1577 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1582 unsigned int val = (((insn >> 20) & (1 << 0)));
1585 case 0 : itype = ARM_INSN_STMIB_WB; arm_extract_sfmt_stmdb_wb (this, current_cpu, pc, base_insn, entire_insn); goto done;
1586 case 1 : itype = ARM_INSN_LDMIB_WB; arm_extract_sfmt_ldmda_wb (this, current_cpu, pc, base_insn, entire_insn); goto done;
1587 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1592 unsigned int val = (((insn >> 20) & (1 << 0)));
1595 case 0 : itype = ARM_INSN_STMIB_SW; arm_extract_sfmt_stmdb_sw (this, current_cpu, pc, base_insn, entire_insn); goto done;
1596 case 1 : itype = ARM_INSN_LDMIB_SW; arm_extract_sfmt_ldmda_sw (this, current_cpu, pc, base_insn, entire_insn); goto done;
1597 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1602 unsigned int val = (((insn >> 20) & (1 << 0)));
1605 case 0 : itype = ARM_INSN_STMIB_SW_WB; arm_extract_sfmt_stmdb_sw_wb (this, current_cpu, pc, base_insn, entire_insn); goto done;
1606 case 1 : itype = ARM_INSN_LDMIB_SW_WB; arm_extract_sfmt_ldmda_sw_wb (this, current_cpu, pc, base_insn, entire_insn); goto done;
1607 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1610 case 80 : /* fall through */
1611 case 81 : /* fall through */
1612 case 82 : /* fall through */
1613 case 83 : /* fall through */
1614 case 84 : /* fall through */
1615 case 85 : /* fall through */
1616 case 86 : /* fall through */
1617 case 87 : itype = ARM_INSN_B; arm_extract_sfmt_b (this, current_cpu, pc, base_insn, entire_insn); goto done;
1618 case 88 : /* fall through */
1619 case 89 : /* fall through */
1620 case 90 : /* fall through */
1621 case 91 : /* fall through */
1622 case 92 : /* fall through */
1623 case 93 : /* fall through */
1624 case 94 : /* fall through */
1625 case 95 : itype = ARM_INSN_BL; arm_extract_sfmt_bl (this, current_cpu, pc, base_insn, entire_insn); goto done;
1626 case 120 : /* fall through */
1627 case 121 : /* fall through */
1628 case 122 : /* fall through */
1629 case 123 : /* fall through */
1630 case 124 : /* fall through */
1631 case 125 : /* fall through */
1632 case 126 : /* fall through */
1633 case 127 : itype = ARM_INSN_SWI; arm_extract_sfmt_swi (this, current_cpu, pc, base_insn, entire_insn); goto done;
1634 default : itype = ARM_INSN_X_INVALID; arm_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
1640 /* The instruction has been decoded and fields extracted. */
1644 f_cond = EXTRACT_LSB0_UINT (base_insn, 32, 31, 4);
1645 this->cond = f_cond;
1649 // FIXME: To be redone (to handle ISA variants).
1650 this->idesc = & arm_idesc::idesc_table[itype];
1651 // ??? record semantic handler?
1652 assert(this->idesc->sem_index == itype);
1656 arm_extract_sfmt_empty (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
1657 arm_insn_word insn = entire_insn;
1658 #define FLD(f) abuf->fields.fmt_empty.f
1661 /* Record the fields for the semantic handler. */
1662 if (UNLIKELY(current_cpu->trace_extract_p))
1664 current_cpu->trace_stream
1665 << "0x" << hex << pc << dec << " (sfmt_empty)\t"
1673 arm_extract_sfmt_b (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
1674 arm_insn_word insn = entire_insn;
1675 #define FLD(f) abuf->fields.sfmt_b.f
1678 f_offset24 = ((((EXTRACT_LSB0_SINT (insn, 32, 23, 24)) << (2))) + (((pc) + (8))));
1680 /* Record the fields for the semantic handler. */
1681 FLD (i_offset24) = f_offset24;
1682 if (UNLIKELY(current_cpu->trace_extract_p))
1684 current_cpu->trace_stream
1685 << "0x" << hex << pc << dec << " (sfmt_b)\t"
1693 arm_extract_sfmt_bl (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
1694 arm_insn_word insn = entire_insn;
1695 #define FLD(f) abuf->fields.sfmt_b.f
1698 f_offset24 = ((((EXTRACT_LSB0_SINT (insn, 32, 23, 24)) << (2))) + (((pc) + (8))));
1700 /* Record the fields for the semantic handler. */
1701 FLD (i_offset24) = f_offset24;
1702 if (UNLIKELY(current_cpu->trace_extract_p))
1704 current_cpu->trace_stream
1705 << "0x" << hex << pc << dec << " (sfmt_bl)\t"
1713 arm_extract_sfmt_bx (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
1714 arm_insn_word insn = entire_insn;
1715 #define FLD(f) abuf->fields.sfmt_bx.f
1718 f_bx_rn = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
1720 /* Record the fields for the semantic handler. */
1721 FLD (f_bx_rn) = f_bx_rn;
1722 FLD (i_bx_rn) = & current_cpu->hardware.h_gr[f_bx_rn];
1723 if (UNLIKELY(current_cpu->trace_extract_p))
1725 current_cpu->trace_stream
1726 << "0x" << hex << pc << dec << " (sfmt_bx)\t"
1727 << " f_bx_rn:0x" << hex << f_bx_rn << dec
1735 arm_extract_sfmt_ldr_post_dec_imm_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
1736 arm_insn_word insn = entire_insn;
1737 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
1742 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
1743 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
1744 f_uimm12 = EXTRACT_LSB0_UINT (insn, 32, 11, 12);
1746 /* Record the fields for the semantic handler. */
1749 FLD (f_uimm12) = f_uimm12;
1750 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
1751 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
1752 if (UNLIKELY(current_cpu->trace_extract_p))
1754 current_cpu->trace_stream
1755 << "0x" << hex << pc << dec << " (sfmt_ldr_post_dec_imm_offset)\t"
1756 << " f_rd:0x" << hex << f_rd << dec
1757 << " f_rn:0x" << hex << f_rn << dec
1758 << " f_uimm12:0x" << hex << f_uimm12 << dec
1766 arm_extract_sfmt_ldr_post_dec_reg_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
1767 arm_insn_word insn = entire_insn;
1768 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
1771 UINT f_operand2_shiftimm;
1772 UINT f_operand2_shifttype;
1775 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
1776 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
1777 f_operand2_shiftimm = EXTRACT_LSB0_UINT (insn, 32, 11, 5);
1778 f_operand2_shifttype = EXTRACT_LSB0_UINT (insn, 32, 6, 2);
1779 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
1781 /* Record the fields for the semantic handler. */
1783 FLD (f_operand2_shiftimm) = f_operand2_shiftimm;
1784 FLD (f_operand2_shifttype) = f_operand2_shifttype;
1787 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
1788 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
1789 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
1790 if (UNLIKELY(current_cpu->trace_extract_p))
1792 current_cpu->trace_stream
1793 << "0x" << hex << pc << dec << " (sfmt_ldr_post_dec_reg_offset)\t"
1794 << " f_rd:0x" << hex << f_rd << dec
1795 << " f_operand2_shiftimm:0x" << hex << f_operand2_shiftimm << dec
1796 << " f_operand2_shifttype:0x" << hex << f_operand2_shifttype << dec
1797 << " f_rm:0x" << hex << f_rm << dec
1798 << " f_rn:0x" << hex << f_rn << dec
1806 arm_extract_sfmt_ldr_pre_dec_imm_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
1807 arm_insn_word insn = entire_insn;
1808 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
1813 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
1814 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
1815 f_uimm12 = EXTRACT_LSB0_UINT (insn, 32, 11, 12);
1817 /* Record the fields for the semantic handler. */
1820 FLD (f_uimm12) = f_uimm12;
1821 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
1822 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
1823 if (UNLIKELY(current_cpu->trace_extract_p))
1825 current_cpu->trace_stream
1826 << "0x" << hex << pc << dec << " (sfmt_ldr_pre_dec_imm_offset)\t"
1827 << " f_rd:0x" << hex << f_rd << dec
1828 << " f_rn:0x" << hex << f_rn << dec
1829 << " f_uimm12:0x" << hex << f_uimm12 << dec
1837 arm_extract_sfmt_ldr_pre_dec_reg_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
1838 arm_insn_word insn = entire_insn;
1839 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
1842 UINT f_operand2_shiftimm;
1843 UINT f_operand2_shifttype;
1846 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
1847 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
1848 f_operand2_shiftimm = EXTRACT_LSB0_UINT (insn, 32, 11, 5);
1849 f_operand2_shifttype = EXTRACT_LSB0_UINT (insn, 32, 6, 2);
1850 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
1852 /* Record the fields for the semantic handler. */
1854 FLD (f_operand2_shiftimm) = f_operand2_shiftimm;
1855 FLD (f_operand2_shifttype) = f_operand2_shifttype;
1858 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
1859 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
1860 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
1861 if (UNLIKELY(current_cpu->trace_extract_p))
1863 current_cpu->trace_stream
1864 << "0x" << hex << pc << dec << " (sfmt_ldr_pre_dec_reg_offset)\t"
1865 << " f_rd:0x" << hex << f_rd << dec
1866 << " f_operand2_shiftimm:0x" << hex << f_operand2_shiftimm << dec
1867 << " f_operand2_shifttype:0x" << hex << f_operand2_shifttype << dec
1868 << " f_rm:0x" << hex << f_rm << dec
1869 << " f_rn:0x" << hex << f_rn << dec
1877 arm_extract_sfmt_ldrb_post_dec_imm_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
1878 arm_insn_word insn = entire_insn;
1879 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
1884 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
1885 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
1886 f_uimm12 = EXTRACT_LSB0_UINT (insn, 32, 11, 12);
1888 /* Record the fields for the semantic handler. */
1891 FLD (f_uimm12) = f_uimm12;
1892 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
1893 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
1894 if (UNLIKELY(current_cpu->trace_extract_p))
1896 current_cpu->trace_stream
1897 << "0x" << hex << pc << dec << " (sfmt_ldrb_post_dec_imm_offset)\t"
1898 << " f_rd:0x" << hex << f_rd << dec
1899 << " f_rn:0x" << hex << f_rn << dec
1900 << " f_uimm12:0x" << hex << f_uimm12 << dec
1908 arm_extract_sfmt_ldrb_post_dec_reg_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
1909 arm_insn_word insn = entire_insn;
1910 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
1913 UINT f_operand2_shiftimm;
1914 UINT f_operand2_shifttype;
1917 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
1918 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
1919 f_operand2_shiftimm = EXTRACT_LSB0_UINT (insn, 32, 11, 5);
1920 f_operand2_shifttype = EXTRACT_LSB0_UINT (insn, 32, 6, 2);
1921 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
1923 /* Record the fields for the semantic handler. */
1925 FLD (f_operand2_shiftimm) = f_operand2_shiftimm;
1926 FLD (f_operand2_shifttype) = f_operand2_shifttype;
1929 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
1930 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
1931 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
1932 if (UNLIKELY(current_cpu->trace_extract_p))
1934 current_cpu->trace_stream
1935 << "0x" << hex << pc << dec << " (sfmt_ldrb_post_dec_reg_offset)\t"
1936 << " f_rd:0x" << hex << f_rd << dec
1937 << " f_operand2_shiftimm:0x" << hex << f_operand2_shiftimm << dec
1938 << " f_operand2_shifttype:0x" << hex << f_operand2_shifttype << dec
1939 << " f_rm:0x" << hex << f_rm << dec
1940 << " f_rn:0x" << hex << f_rn << dec
1948 arm_extract_sfmt_ldrb_pre_dec_imm_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
1949 arm_insn_word insn = entire_insn;
1950 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
1955 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
1956 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
1957 f_uimm12 = EXTRACT_LSB0_UINT (insn, 32, 11, 12);
1959 /* Record the fields for the semantic handler. */
1962 FLD (f_uimm12) = f_uimm12;
1963 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
1964 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
1965 if (UNLIKELY(current_cpu->trace_extract_p))
1967 current_cpu->trace_stream
1968 << "0x" << hex << pc << dec << " (sfmt_ldrb_pre_dec_imm_offset)\t"
1969 << " f_rd:0x" << hex << f_rd << dec
1970 << " f_rn:0x" << hex << f_rn << dec
1971 << " f_uimm12:0x" << hex << f_uimm12 << dec
1979 arm_extract_sfmt_ldrb_pre_dec_reg_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
1980 arm_insn_word insn = entire_insn;
1981 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
1984 UINT f_operand2_shiftimm;
1985 UINT f_operand2_shifttype;
1988 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
1989 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
1990 f_operand2_shiftimm = EXTRACT_LSB0_UINT (insn, 32, 11, 5);
1991 f_operand2_shifttype = EXTRACT_LSB0_UINT (insn, 32, 6, 2);
1992 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
1994 /* Record the fields for the semantic handler. */
1996 FLD (f_operand2_shiftimm) = f_operand2_shiftimm;
1997 FLD (f_operand2_shifttype) = f_operand2_shifttype;
2000 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
2001 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
2002 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
2003 if (UNLIKELY(current_cpu->trace_extract_p))
2005 current_cpu->trace_stream
2006 << "0x" << hex << pc << dec << " (sfmt_ldrb_pre_dec_reg_offset)\t"
2007 << " f_rd:0x" << hex << f_rd << dec
2008 << " f_operand2_shiftimm:0x" << hex << f_operand2_shiftimm << dec
2009 << " f_operand2_shifttype:0x" << hex << f_operand2_shifttype << dec
2010 << " f_rm:0x" << hex << f_rm << dec
2011 << " f_rn:0x" << hex << f_rn << dec
2019 arm_extract_sfmt_str_post_dec_imm_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
2020 arm_insn_word insn = entire_insn;
2021 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
2026 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
2027 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
2028 f_uimm12 = EXTRACT_LSB0_UINT (insn, 32, 11, 12);
2030 /* Record the fields for the semantic handler. */
2033 FLD (f_uimm12) = f_uimm12;
2034 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
2035 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
2036 if (UNLIKELY(current_cpu->trace_extract_p))
2038 current_cpu->trace_stream
2039 << "0x" << hex << pc << dec << " (sfmt_str_post_dec_imm_offset)\t"
2040 << " f_rd:0x" << hex << f_rd << dec
2041 << " f_rn:0x" << hex << f_rn << dec
2042 << " f_uimm12:0x" << hex << f_uimm12 << dec
2050 arm_extract_sfmt_str_post_dec_reg_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
2051 arm_insn_word insn = entire_insn;
2052 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
2055 UINT f_operand2_shiftimm;
2056 UINT f_operand2_shifttype;
2059 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
2060 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
2061 f_operand2_shiftimm = EXTRACT_LSB0_UINT (insn, 32, 11, 5);
2062 f_operand2_shifttype = EXTRACT_LSB0_UINT (insn, 32, 6, 2);
2063 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
2065 /* Record the fields for the semantic handler. */
2066 FLD (f_operand2_shiftimm) = f_operand2_shiftimm;
2067 FLD (f_operand2_shifttype) = f_operand2_shifttype;
2071 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
2072 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
2073 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
2074 if (UNLIKELY(current_cpu->trace_extract_p))
2076 current_cpu->trace_stream
2077 << "0x" << hex << pc << dec << " (sfmt_str_post_dec_reg_offset)\t"
2078 << " f_operand2_shiftimm:0x" << hex << f_operand2_shiftimm << dec
2079 << " f_operand2_shifttype:0x" << hex << f_operand2_shifttype << dec
2080 << " f_rd:0x" << hex << f_rd << dec
2081 << " f_rm:0x" << hex << f_rm << dec
2082 << " f_rn:0x" << hex << f_rn << dec
2090 arm_extract_sfmt_str_pre_dec_imm_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
2091 arm_insn_word insn = entire_insn;
2092 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
2097 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
2098 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
2099 f_uimm12 = EXTRACT_LSB0_UINT (insn, 32, 11, 12);
2101 /* Record the fields for the semantic handler. */
2104 FLD (f_uimm12) = f_uimm12;
2105 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
2106 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
2107 if (UNLIKELY(current_cpu->trace_extract_p))
2109 current_cpu->trace_stream
2110 << "0x" << hex << pc << dec << " (sfmt_str_pre_dec_imm_offset)\t"
2111 << " f_rd:0x" << hex << f_rd << dec
2112 << " f_rn:0x" << hex << f_rn << dec
2113 << " f_uimm12:0x" << hex << f_uimm12 << dec
2121 arm_extract_sfmt_str_pre_dec_reg_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
2122 arm_insn_word insn = entire_insn;
2123 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
2126 UINT f_operand2_shiftimm;
2127 UINT f_operand2_shifttype;
2130 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
2131 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
2132 f_operand2_shiftimm = EXTRACT_LSB0_UINT (insn, 32, 11, 5);
2133 f_operand2_shifttype = EXTRACT_LSB0_UINT (insn, 32, 6, 2);
2134 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
2136 /* Record the fields for the semantic handler. */
2137 FLD (f_operand2_shiftimm) = f_operand2_shiftimm;
2138 FLD (f_operand2_shifttype) = f_operand2_shifttype;
2142 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
2143 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
2144 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
2145 if (UNLIKELY(current_cpu->trace_extract_p))
2147 current_cpu->trace_stream
2148 << "0x" << hex << pc << dec << " (sfmt_str_pre_dec_reg_offset)\t"
2149 << " f_operand2_shiftimm:0x" << hex << f_operand2_shiftimm << dec
2150 << " f_operand2_shifttype:0x" << hex << f_operand2_shifttype << dec
2151 << " f_rd:0x" << hex << f_rd << dec
2152 << " f_rm:0x" << hex << f_rm << dec
2153 << " f_rn:0x" << hex << f_rn << dec
2161 arm_extract_sfmt_strb_post_dec_imm_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
2162 arm_insn_word insn = entire_insn;
2163 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
2168 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
2169 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
2170 f_uimm12 = EXTRACT_LSB0_UINT (insn, 32, 11, 12);
2172 /* Record the fields for the semantic handler. */
2175 FLD (f_uimm12) = f_uimm12;
2176 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
2177 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
2178 if (UNLIKELY(current_cpu->trace_extract_p))
2180 current_cpu->trace_stream
2181 << "0x" << hex << pc << dec << " (sfmt_strb_post_dec_imm_offset)\t"
2182 << " f_rd:0x" << hex << f_rd << dec
2183 << " f_rn:0x" << hex << f_rn << dec
2184 << " f_uimm12:0x" << hex << f_uimm12 << dec
2192 arm_extract_sfmt_strb_post_dec_reg_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
2193 arm_insn_word insn = entire_insn;
2194 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
2197 UINT f_operand2_shiftimm;
2198 UINT f_operand2_shifttype;
2201 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
2202 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
2203 f_operand2_shiftimm = EXTRACT_LSB0_UINT (insn, 32, 11, 5);
2204 f_operand2_shifttype = EXTRACT_LSB0_UINT (insn, 32, 6, 2);
2205 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
2207 /* Record the fields for the semantic handler. */
2208 FLD (f_operand2_shiftimm) = f_operand2_shiftimm;
2209 FLD (f_operand2_shifttype) = f_operand2_shifttype;
2213 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
2214 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
2215 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
2216 if (UNLIKELY(current_cpu->trace_extract_p))
2218 current_cpu->trace_stream
2219 << "0x" << hex << pc << dec << " (sfmt_strb_post_dec_reg_offset)\t"
2220 << " f_operand2_shiftimm:0x" << hex << f_operand2_shiftimm << dec
2221 << " f_operand2_shifttype:0x" << hex << f_operand2_shifttype << dec
2222 << " f_rd:0x" << hex << f_rd << dec
2223 << " f_rm:0x" << hex << f_rm << dec
2224 << " f_rn:0x" << hex << f_rn << dec
2232 arm_extract_sfmt_strb_pre_dec_imm_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
2233 arm_insn_word insn = entire_insn;
2234 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
2239 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
2240 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
2241 f_uimm12 = EXTRACT_LSB0_UINT (insn, 32, 11, 12);
2243 /* Record the fields for the semantic handler. */
2246 FLD (f_uimm12) = f_uimm12;
2247 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
2248 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
2249 if (UNLIKELY(current_cpu->trace_extract_p))
2251 current_cpu->trace_stream
2252 << "0x" << hex << pc << dec << " (sfmt_strb_pre_dec_imm_offset)\t"
2253 << " f_rd:0x" << hex << f_rd << dec
2254 << " f_rn:0x" << hex << f_rn << dec
2255 << " f_uimm12:0x" << hex << f_uimm12 << dec
2263 arm_extract_sfmt_strb_pre_dec_reg_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
2264 arm_insn_word insn = entire_insn;
2265 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
2268 UINT f_operand2_shiftimm;
2269 UINT f_operand2_shifttype;
2272 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
2273 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
2274 f_operand2_shiftimm = EXTRACT_LSB0_UINT (insn, 32, 11, 5);
2275 f_operand2_shifttype = EXTRACT_LSB0_UINT (insn, 32, 6, 2);
2276 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
2278 /* Record the fields for the semantic handler. */
2279 FLD (f_operand2_shiftimm) = f_operand2_shiftimm;
2280 FLD (f_operand2_shifttype) = f_operand2_shifttype;
2284 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
2285 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
2286 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
2287 if (UNLIKELY(current_cpu->trace_extract_p))
2289 current_cpu->trace_stream
2290 << "0x" << hex << pc << dec << " (sfmt_strb_pre_dec_reg_offset)\t"
2291 << " f_operand2_shiftimm:0x" << hex << f_operand2_shiftimm << dec
2292 << " f_operand2_shifttype:0x" << hex << f_operand2_shifttype << dec
2293 << " f_rd:0x" << hex << f_rd << dec
2294 << " f_rm:0x" << hex << f_rm << dec
2295 << " f_rn:0x" << hex << f_rn << dec
2303 arm_extract_sfmt_strh_pre_dec_imm_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
2304 arm_insn_word insn = entire_insn;
2305 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
2312 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
2313 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
2314 f_offset4_hi = EXTRACT_LSB0_UINT (insn, 32, 11, 4);
2315 f_offset4_lo = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
2316 f_hdt_offset8 = ((((f_offset4_hi) << (4))) | (f_offset4_lo));
2318 /* Record the fields for the semantic handler. */
2321 FLD (i_hdt_offset8) = f_hdt_offset8;
2322 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
2323 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
2324 if (UNLIKELY(current_cpu->trace_extract_p))
2326 current_cpu->trace_stream
2327 << "0x" << hex << pc << dec << " (sfmt_strh_pre_dec_imm_offset)\t"
2328 << " f_rd:0x" << hex << f_rd << dec
2329 << " f_rn:0x" << hex << f_rn << dec
2337 arm_extract_sfmt_strh_pre_dec_reg_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
2338 arm_insn_word insn = entire_insn;
2339 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
2344 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
2345 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
2346 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
2348 /* Record the fields for the semantic handler. */
2352 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
2353 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
2354 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
2355 if (UNLIKELY(current_cpu->trace_extract_p))
2357 current_cpu->trace_stream
2358 << "0x" << hex << pc << dec << " (sfmt_strh_pre_dec_reg_offset)\t"
2359 << " f_rd:0x" << hex << f_rd << dec
2360 << " f_rm:0x" << hex << f_rm << dec
2361 << " f_rn:0x" << hex << f_rn << dec
2369 arm_extract_sfmt_strh_pre_dec_wb_imm_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
2370 arm_insn_word insn = entire_insn;
2371 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
2378 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
2379 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
2380 f_offset4_hi = EXTRACT_LSB0_UINT (insn, 32, 11, 4);
2381 f_offset4_lo = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
2382 f_hdt_offset8 = ((((f_offset4_hi) << (4))) | (f_offset4_lo));
2384 /* Record the fields for the semantic handler. */
2387 FLD (i_hdt_offset8) = f_hdt_offset8;
2388 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
2389 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
2390 if (UNLIKELY(current_cpu->trace_extract_p))
2392 current_cpu->trace_stream
2393 << "0x" << hex << pc << dec << " (sfmt_strh_pre_dec_wb_imm_offset)\t"
2394 << " f_rd:0x" << hex << f_rd << dec
2395 << " f_rn:0x" << hex << f_rn << dec
2403 arm_extract_sfmt_strh_pre_dec_wb_reg_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
2404 arm_insn_word insn = entire_insn;
2405 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
2410 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
2411 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
2412 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
2414 /* Record the fields for the semantic handler. */
2418 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
2419 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
2420 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
2421 if (UNLIKELY(current_cpu->trace_extract_p))
2423 current_cpu->trace_stream
2424 << "0x" << hex << pc << dec << " (sfmt_strh_pre_dec_wb_reg_offset)\t"
2425 << " f_rd:0x" << hex << f_rd << dec
2426 << " f_rm:0x" << hex << f_rm << dec
2427 << " f_rn:0x" << hex << f_rn << dec
2435 arm_extract_sfmt_ldrsb_pre_dec_imm_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
2436 arm_insn_word insn = entire_insn;
2437 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
2444 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
2445 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
2446 f_offset4_hi = EXTRACT_LSB0_UINT (insn, 32, 11, 4);
2447 f_offset4_lo = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
2448 f_hdt_offset8 = ((((f_offset4_hi) << (4))) | (f_offset4_lo));
2450 /* Record the fields for the semantic handler. */
2453 FLD (i_hdt_offset8) = f_hdt_offset8;
2454 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
2455 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
2456 if (UNLIKELY(current_cpu->trace_extract_p))
2458 current_cpu->trace_stream
2459 << "0x" << hex << pc << dec << " (sfmt_ldrsb_pre_dec_imm_offset)\t"
2460 << " f_rd:0x" << hex << f_rd << dec
2461 << " f_rn:0x" << hex << f_rn << dec
2469 arm_extract_sfmt_ldrsb_pre_dec_reg_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
2470 arm_insn_word insn = entire_insn;
2471 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
2476 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
2477 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
2478 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
2480 /* Record the fields for the semantic handler. */
2484 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
2485 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
2486 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
2487 if (UNLIKELY(current_cpu->trace_extract_p))
2489 current_cpu->trace_stream
2490 << "0x" << hex << pc << dec << " (sfmt_ldrsb_pre_dec_reg_offset)\t"
2491 << " f_rd:0x" << hex << f_rd << dec
2492 << " f_rm:0x" << hex << f_rm << dec
2493 << " f_rn:0x" << hex << f_rn << dec
2501 arm_extract_sfmt_ldrsb_pre_dec_wb_imm_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
2502 arm_insn_word insn = entire_insn;
2503 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
2510 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
2511 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
2512 f_offset4_hi = EXTRACT_LSB0_UINT (insn, 32, 11, 4);
2513 f_offset4_lo = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
2514 f_hdt_offset8 = ((((f_offset4_hi) << (4))) | (f_offset4_lo));
2516 /* Record the fields for the semantic handler. */
2519 FLD (i_hdt_offset8) = f_hdt_offset8;
2520 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
2521 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
2522 if (UNLIKELY(current_cpu->trace_extract_p))
2524 current_cpu->trace_stream
2525 << "0x" << hex << pc << dec << " (sfmt_ldrsb_pre_dec_wb_imm_offset)\t"
2526 << " f_rd:0x" << hex << f_rd << dec
2527 << " f_rn:0x" << hex << f_rn << dec
2535 arm_extract_sfmt_ldrsb_pre_dec_wb_reg_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
2536 arm_insn_word insn = entire_insn;
2537 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
2542 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
2543 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
2544 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
2546 /* Record the fields for the semantic handler. */
2550 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
2551 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
2552 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
2553 if (UNLIKELY(current_cpu->trace_extract_p))
2555 current_cpu->trace_stream
2556 << "0x" << hex << pc << dec << " (sfmt_ldrsb_pre_dec_wb_reg_offset)\t"
2557 << " f_rd:0x" << hex << f_rd << dec
2558 << " f_rm:0x" << hex << f_rm << dec
2559 << " f_rn:0x" << hex << f_rn << dec
2567 arm_extract_sfmt_ldrh_pre_dec_imm_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
2568 arm_insn_word insn = entire_insn;
2569 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
2576 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
2577 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
2578 f_offset4_hi = EXTRACT_LSB0_UINT (insn, 32, 11, 4);
2579 f_offset4_lo = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
2580 f_hdt_offset8 = ((((f_offset4_hi) << (4))) | (f_offset4_lo));
2582 /* Record the fields for the semantic handler. */
2585 FLD (i_hdt_offset8) = f_hdt_offset8;
2586 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
2587 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
2588 if (UNLIKELY(current_cpu->trace_extract_p))
2590 current_cpu->trace_stream
2591 << "0x" << hex << pc << dec << " (sfmt_ldrh_pre_dec_imm_offset)\t"
2592 << " f_rd:0x" << hex << f_rd << dec
2593 << " f_rn:0x" << hex << f_rn << dec
2601 arm_extract_sfmt_ldrh_pre_dec_reg_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
2602 arm_insn_word insn = entire_insn;
2603 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
2608 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
2609 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
2610 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
2612 /* Record the fields for the semantic handler. */
2616 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
2617 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
2618 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
2619 if (UNLIKELY(current_cpu->trace_extract_p))
2621 current_cpu->trace_stream
2622 << "0x" << hex << pc << dec << " (sfmt_ldrh_pre_dec_reg_offset)\t"
2623 << " f_rd:0x" << hex << f_rd << dec
2624 << " f_rm:0x" << hex << f_rm << dec
2625 << " f_rn:0x" << hex << f_rn << dec
2633 arm_extract_sfmt_ldrh_pre_dec_wb_imm_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
2634 arm_insn_word insn = entire_insn;
2635 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
2642 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
2643 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
2644 f_offset4_hi = EXTRACT_LSB0_UINT (insn, 32, 11, 4);
2645 f_offset4_lo = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
2646 f_hdt_offset8 = ((((f_offset4_hi) << (4))) | (f_offset4_lo));
2648 /* Record the fields for the semantic handler. */
2651 FLD (i_hdt_offset8) = f_hdt_offset8;
2652 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
2653 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
2654 if (UNLIKELY(current_cpu->trace_extract_p))
2656 current_cpu->trace_stream
2657 << "0x" << hex << pc << dec << " (sfmt_ldrh_pre_dec_wb_imm_offset)\t"
2658 << " f_rd:0x" << hex << f_rd << dec
2659 << " f_rn:0x" << hex << f_rn << dec
2667 arm_extract_sfmt_ldrh_pre_dec_wb_reg_offset (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
2668 arm_insn_word insn = entire_insn;
2669 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
2674 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
2675 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
2676 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
2678 /* Record the fields for the semantic handler. */
2682 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
2683 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
2684 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
2685 if (UNLIKELY(current_cpu->trace_extract_p))
2687 current_cpu->trace_stream
2688 << "0x" << hex << pc << dec << " (sfmt_ldrh_pre_dec_wb_reg_offset)\t"
2689 << " f_rd:0x" << hex << f_rd << dec
2690 << " f_rm:0x" << hex << f_rm << dec
2691 << " f_rn:0x" << hex << f_rn << dec
2699 arm_extract_sfmt_mul (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
2700 arm_insn_word insn = entire_insn;
2701 #define FLD(f) abuf->fields.sfmt_mla.f
2707 f_set_cc_ = EXTRACT_LSB0_UINT (insn, 32, 20, 1);
2708 f_mul_rd = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
2709 f_rs = EXTRACT_LSB0_UINT (insn, 32, 11, 4);
2710 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
2712 /* Record the fields for the semantic handler. */
2715 FLD (f_set_cc_) = f_set_cc_;
2716 FLD (f_mul_rd) = f_mul_rd;
2717 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
2718 FLD (i_rs) = & current_cpu->hardware.h_gr[f_rs];
2719 FLD (i_mul_rd) = & current_cpu->hardware.h_gr[f_mul_rd];
2720 if (UNLIKELY(current_cpu->trace_extract_p))
2722 current_cpu->trace_stream
2723 << "0x" << hex << pc << dec << " (sfmt_mul)\t"
2724 << " f_rm:0x" << hex << f_rm << dec
2725 << " f_rs:0x" << hex << f_rs << dec
2726 << " f_set_cc_:0x" << hex << f_set_cc_ << dec
2727 << " f_mul_rd:0x" << hex << f_mul_rd << dec
2735 arm_extract_sfmt_mla (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
2736 arm_insn_word insn = entire_insn;
2737 #define FLD(f) abuf->fields.sfmt_mla.f
2744 f_set_cc_ = EXTRACT_LSB0_UINT (insn, 32, 20, 1);
2745 f_mul_rd = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
2746 f_mul_rn = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
2747 f_rs = EXTRACT_LSB0_UINT (insn, 32, 11, 4);
2748 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
2750 /* Record the fields for the semantic handler. */
2751 FLD (f_mul_rn) = f_mul_rn;
2754 FLD (f_set_cc_) = f_set_cc_;
2755 FLD (f_mul_rd) = f_mul_rd;
2756 FLD (i_mul_rn) = & current_cpu->hardware.h_gr[f_mul_rn];
2757 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
2758 FLD (i_rs) = & current_cpu->hardware.h_gr[f_rs];
2759 FLD (i_mul_rd) = & current_cpu->hardware.h_gr[f_mul_rd];
2760 if (UNLIKELY(current_cpu->trace_extract_p))
2762 current_cpu->trace_stream
2763 << "0x" << hex << pc << dec << " (sfmt_mla)\t"
2764 << " f_mul_rn:0x" << hex << f_mul_rn << dec
2765 << " f_rm:0x" << hex << f_rm << dec
2766 << " f_rs:0x" << hex << f_rs << dec
2767 << " f_set_cc_:0x" << hex << f_set_cc_ << dec
2768 << " f_mul_rd:0x" << hex << f_mul_rd << dec
2776 arm_extract_sfmt_umull (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
2777 arm_insn_word insn = entire_insn;
2778 #define FLD(f) abuf->fields.sfmt_umull.f
2785 f_set_cc_ = EXTRACT_LSB0_UINT (insn, 32, 20, 1);
2786 f_rdhi = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
2787 f_rdlo = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
2788 f_rs = EXTRACT_LSB0_UINT (insn, 32, 11, 4);
2789 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
2791 /* Record the fields for the semantic handler. */
2794 FLD (f_set_cc_) = f_set_cc_;
2795 FLD (f_rdhi) = f_rdhi;
2796 FLD (f_rdlo) = f_rdlo;
2797 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
2798 FLD (i_rs) = & current_cpu->hardware.h_gr[f_rs];
2799 FLD (i_rdhi) = & current_cpu->hardware.h_gr[f_rdhi];
2800 FLD (i_rdlo) = & current_cpu->hardware.h_gr[f_rdlo];
2801 if (UNLIKELY(current_cpu->trace_extract_p))
2803 current_cpu->trace_stream
2804 << "0x" << hex << pc << dec << " (sfmt_umull)\t"
2805 << " f_rm:0x" << hex << f_rm << dec
2806 << " f_rs:0x" << hex << f_rs << dec
2807 << " f_set_cc_:0x" << hex << f_set_cc_ << dec
2808 << " f_rdhi:0x" << hex << f_rdhi << dec
2809 << " f_rdlo:0x" << hex << f_rdlo << dec
2817 arm_extract_sfmt_umlal (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
2818 arm_insn_word insn = entire_insn;
2819 #define FLD(f) abuf->fields.sfmt_umull.f
2826 f_set_cc_ = EXTRACT_LSB0_UINT (insn, 32, 20, 1);
2827 f_rdhi = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
2828 f_rdlo = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
2829 f_rs = EXTRACT_LSB0_UINT (insn, 32, 11, 4);
2830 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
2832 /* Record the fields for the semantic handler. */
2833 FLD (f_rdhi) = f_rdhi;
2834 FLD (f_rdlo) = f_rdlo;
2837 FLD (f_set_cc_) = f_set_cc_;
2838 FLD (i_rdhi) = & current_cpu->hardware.h_gr[f_rdhi];
2839 FLD (i_rdlo) = & current_cpu->hardware.h_gr[f_rdlo];
2840 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
2841 FLD (i_rs) = & current_cpu->hardware.h_gr[f_rs];
2842 if (UNLIKELY(current_cpu->trace_extract_p))
2844 current_cpu->trace_stream
2845 << "0x" << hex << pc << dec << " (sfmt_umlal)\t"
2846 << " f_rdhi:0x" << hex << f_rdhi << dec
2847 << " f_rdlo:0x" << hex << f_rdlo << dec
2848 << " f_rm:0x" << hex << f_rm << dec
2849 << " f_rs:0x" << hex << f_rs << dec
2850 << " f_set_cc_:0x" << hex << f_set_cc_ << dec
2858 arm_extract_sfmt_swp (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
2859 arm_insn_word insn = entire_insn;
2860 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
2865 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
2866 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
2867 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
2869 /* Record the fields for the semantic handler. */
2873 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
2874 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
2875 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
2876 if (UNLIKELY(current_cpu->trace_extract_p))
2878 current_cpu->trace_stream
2879 << "0x" << hex << pc << dec << " (sfmt_swp)\t"
2880 << " f_rm:0x" << hex << f_rm << dec
2881 << " f_rn:0x" << hex << f_rn << dec
2882 << " f_rd:0x" << hex << f_rd << dec
2890 arm_extract_sfmt_swpb (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
2891 arm_insn_word insn = entire_insn;
2892 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
2897 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
2898 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
2899 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
2901 /* Record the fields for the semantic handler. */
2905 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
2906 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
2907 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
2908 if (UNLIKELY(current_cpu->trace_extract_p))
2910 current_cpu->trace_stream
2911 << "0x" << hex << pc << dec << " (sfmt_swpb)\t"
2912 << " f_rm:0x" << hex << f_rm << dec
2913 << " f_rn:0x" << hex << f_rn << dec
2914 << " f_rd:0x" << hex << f_rd << dec
2922 arm_extract_sfmt_swi (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
2923 arm_insn_word insn = entire_insn;
2924 #define FLD(f) abuf->fields.sfmt_swi.f
2927 f_swi_comment = EXTRACT_LSB0_UINT (insn, 32, 23, 24);
2929 /* Record the fields for the semantic handler. */
2930 FLD (f_swi_comment) = f_swi_comment;
2931 if (UNLIKELY(current_cpu->trace_extract_p))
2933 current_cpu->trace_stream
2934 << "0x" << hex << pc << dec << " (sfmt_swi)\t"
2935 << " f_swi_comment:0x" << hex << f_swi_comment << dec
2943 arm_extract_sfmt_and_reg_imm_shift (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
2944 arm_insn_word insn = entire_insn;
2945 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
2949 UINT f_operand2_shiftimm;
2950 UINT f_operand2_shifttype;
2953 f_set_cc_ = EXTRACT_LSB0_UINT (insn, 32, 20, 1);
2954 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
2955 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
2956 f_operand2_shiftimm = EXTRACT_LSB0_UINT (insn, 32, 11, 5);
2957 f_operand2_shifttype = EXTRACT_LSB0_UINT (insn, 32, 6, 2);
2958 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
2960 /* Record the fields for the semantic handler. */
2962 FLD (f_operand2_shiftimm) = f_operand2_shiftimm;
2963 FLD (f_operand2_shifttype) = f_operand2_shifttype;
2966 FLD (f_set_cc_) = f_set_cc_;
2967 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
2968 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
2969 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
2970 if (UNLIKELY(current_cpu->trace_extract_p))
2972 current_cpu->trace_stream
2973 << "0x" << hex << pc << dec << " (sfmt_and_reg_imm_shift)\t"
2974 << " f_rd:0x" << hex << f_rd << dec
2975 << " f_operand2_shiftimm:0x" << hex << f_operand2_shiftimm << dec
2976 << " f_operand2_shifttype:0x" << hex << f_operand2_shifttype << dec
2977 << " f_rm:0x" << hex << f_rm << dec
2978 << " f_rn:0x" << hex << f_rn << dec
2979 << " f_set_cc_:0x" << hex << f_set_cc_ << dec
2987 arm_extract_sfmt_and_reg_reg_shift (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
2988 arm_insn_word insn = entire_insn;
2989 #define FLD(f) abuf->fields.sfmt_and_reg_reg_shift.f
2993 UINT f_operand2_shiftreg;
2994 UINT f_operand2_shifttype;
2997 f_set_cc_ = EXTRACT_LSB0_UINT (insn, 32, 20, 1);
2998 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
2999 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
3000 f_operand2_shiftreg = EXTRACT_LSB0_UINT (insn, 32, 11, 4);
3001 f_operand2_shifttype = EXTRACT_LSB0_UINT (insn, 32, 6, 2);
3002 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
3004 /* Record the fields for the semantic handler. */
3006 FLD (f_operand2_shiftreg) = f_operand2_shiftreg;
3007 FLD (f_operand2_shifttype) = f_operand2_shifttype;
3010 FLD (f_set_cc_) = f_set_cc_;
3011 FLD (i_operand2_shiftreg) = & current_cpu->hardware.h_gr[f_operand2_shiftreg];
3012 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
3013 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
3014 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
3015 if (UNLIKELY(current_cpu->trace_extract_p))
3017 current_cpu->trace_stream
3018 << "0x" << hex << pc << dec << " (sfmt_and_reg_reg_shift)\t"
3019 << " f_rd:0x" << hex << f_rd << dec
3020 << " f_operand2_shiftreg:0x" << hex << f_operand2_shiftreg << dec
3021 << " f_operand2_shifttype:0x" << hex << f_operand2_shifttype << dec
3022 << " f_rm:0x" << hex << f_rm << dec
3023 << " f_rn:0x" << hex << f_rn << dec
3024 << " f_set_cc_:0x" << hex << f_set_cc_ << dec
3032 arm_extract_sfmt_and_imm (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
3033 arm_insn_word insn = entire_insn;
3034 #define FLD(f) abuf->fields.sfmt_and_imm.f
3040 f_set_cc_ = EXTRACT_LSB0_UINT (insn, 32, 20, 1);
3041 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
3042 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
3043 f_imm12 = RORSI (((EXTRACT_LSB0_UINT (insn, 32, 11, 12)) & (255)), ((2) * (((unsigned int) (((EXTRACT_LSB0_UINT (insn, 32, 11, 12)) & (3840))) >> (8)))));
3045 /* Record the fields for the semantic handler. */
3047 FLD (f_imm12) = f_imm12;
3049 FLD (f_set_cc_) = f_set_cc_;
3050 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
3051 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
3052 if (UNLIKELY(current_cpu->trace_extract_p))
3054 current_cpu->trace_stream
3055 << "0x" << hex << pc << dec << " (sfmt_and_imm)\t"
3056 << " f_rd:0x" << hex << f_rd << dec
3057 << " f_imm12:0x" << hex << f_imm12 << dec
3058 << " f_rn:0x" << hex << f_rn << dec
3059 << " f_set_cc_:0x" << hex << f_set_cc_ << dec
3067 arm_extract_sfmt_mov_reg_imm_shift (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
3068 arm_insn_word insn = entire_insn;
3069 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
3072 UINT f_operand2_shiftimm;
3073 UINT f_operand2_shifttype;
3076 f_set_cc_ = EXTRACT_LSB0_UINT (insn, 32, 20, 1);
3077 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
3078 f_operand2_shiftimm = EXTRACT_LSB0_UINT (insn, 32, 11, 5);
3079 f_operand2_shifttype = EXTRACT_LSB0_UINT (insn, 32, 6, 2);
3080 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
3082 /* Record the fields for the semantic handler. */
3084 FLD (f_operand2_shiftimm) = f_operand2_shiftimm;
3085 FLD (f_operand2_shifttype) = f_operand2_shifttype;
3087 FLD (f_set_cc_) = f_set_cc_;
3088 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
3089 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
3090 if (UNLIKELY(current_cpu->trace_extract_p))
3092 current_cpu->trace_stream
3093 << "0x" << hex << pc << dec << " (sfmt_mov_reg_imm_shift)\t"
3094 << " f_rd:0x" << hex << f_rd << dec
3095 << " f_operand2_shiftimm:0x" << hex << f_operand2_shiftimm << dec
3096 << " f_operand2_shifttype:0x" << hex << f_operand2_shifttype << dec
3097 << " f_rm:0x" << hex << f_rm << dec
3098 << " f_set_cc_:0x" << hex << f_set_cc_ << dec
3106 arm_extract_sfmt_mov_reg_reg_shift (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
3107 arm_insn_word insn = entire_insn;
3108 #define FLD(f) abuf->fields.sfmt_and_reg_reg_shift.f
3111 UINT f_operand2_shiftreg;
3112 UINT f_operand2_shifttype;
3115 f_set_cc_ = EXTRACT_LSB0_UINT (insn, 32, 20, 1);
3116 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
3117 f_operand2_shiftreg = EXTRACT_LSB0_UINT (insn, 32, 11, 4);
3118 f_operand2_shifttype = EXTRACT_LSB0_UINT (insn, 32, 6, 2);
3119 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
3121 /* Record the fields for the semantic handler. */
3123 FLD (f_operand2_shiftreg) = f_operand2_shiftreg;
3124 FLD (f_operand2_shifttype) = f_operand2_shifttype;
3126 FLD (f_set_cc_) = f_set_cc_;
3127 FLD (i_operand2_shiftreg) = & current_cpu->hardware.h_gr[f_operand2_shiftreg];
3128 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
3129 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
3130 if (UNLIKELY(current_cpu->trace_extract_p))
3132 current_cpu->trace_stream
3133 << "0x" << hex << pc << dec << " (sfmt_mov_reg_reg_shift)\t"
3134 << " f_rd:0x" << hex << f_rd << dec
3135 << " f_operand2_shiftreg:0x" << hex << f_operand2_shiftreg << dec
3136 << " f_operand2_shifttype:0x" << hex << f_operand2_shifttype << dec
3137 << " f_rm:0x" << hex << f_rm << dec
3138 << " f_set_cc_:0x" << hex << f_set_cc_ << dec
3146 arm_extract_sfmt_mov_imm (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
3147 arm_insn_word insn = entire_insn;
3148 #define FLD(f) abuf->fields.sfmt_and_imm.f
3153 f_set_cc_ = EXTRACT_LSB0_UINT (insn, 32, 20, 1);
3154 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
3155 f_imm12 = RORSI (((EXTRACT_LSB0_UINT (insn, 32, 11, 12)) & (255)), ((2) * (((unsigned int) (((EXTRACT_LSB0_UINT (insn, 32, 11, 12)) & (3840))) >> (8)))));
3157 /* Record the fields for the semantic handler. */
3159 FLD (f_imm12) = f_imm12;
3160 FLD (f_set_cc_) = f_set_cc_;
3161 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
3162 if (UNLIKELY(current_cpu->trace_extract_p))
3164 current_cpu->trace_stream
3165 << "0x" << hex << pc << dec << " (sfmt_mov_imm)\t"
3166 << " f_rd:0x" << hex << f_rd << dec
3167 << " f_imm12:0x" << hex << f_imm12 << dec
3168 << " f_set_cc_:0x" << hex << f_set_cc_ << dec
3176 arm_extract_sfmt_add_reg_imm_shift (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
3177 arm_insn_word insn = entire_insn;
3178 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
3182 UINT f_operand2_shiftimm;
3183 UINT f_operand2_shifttype;
3186 f_set_cc_ = EXTRACT_LSB0_UINT (insn, 32, 20, 1);
3187 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
3188 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
3189 f_operand2_shiftimm = EXTRACT_LSB0_UINT (insn, 32, 11, 5);
3190 f_operand2_shifttype = EXTRACT_LSB0_UINT (insn, 32, 6, 2);
3191 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
3193 /* Record the fields for the semantic handler. */
3195 FLD (f_operand2_shiftimm) = f_operand2_shiftimm;
3196 FLD (f_operand2_shifttype) = f_operand2_shifttype;
3199 FLD (f_set_cc_) = f_set_cc_;
3200 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
3201 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
3202 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
3203 if (UNLIKELY(current_cpu->trace_extract_p))
3205 current_cpu->trace_stream
3206 << "0x" << hex << pc << dec << " (sfmt_add_reg_imm_shift)\t"
3207 << " f_rd:0x" << hex << f_rd << dec
3208 << " f_operand2_shiftimm:0x" << hex << f_operand2_shiftimm << dec
3209 << " f_operand2_shifttype:0x" << hex << f_operand2_shifttype << dec
3210 << " f_rm:0x" << hex << f_rm << dec
3211 << " f_rn:0x" << hex << f_rn << dec
3212 << " f_set_cc_:0x" << hex << f_set_cc_ << dec
3220 arm_extract_sfmt_add_reg_reg_shift (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
3221 arm_insn_word insn = entire_insn;
3222 #define FLD(f) abuf->fields.sfmt_and_reg_reg_shift.f
3226 UINT f_operand2_shiftreg;
3227 UINT f_operand2_shifttype;
3230 f_set_cc_ = EXTRACT_LSB0_UINT (insn, 32, 20, 1);
3231 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
3232 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
3233 f_operand2_shiftreg = EXTRACT_LSB0_UINT (insn, 32, 11, 4);
3234 f_operand2_shifttype = EXTRACT_LSB0_UINT (insn, 32, 6, 2);
3235 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
3237 /* Record the fields for the semantic handler. */
3239 FLD (f_operand2_shiftreg) = f_operand2_shiftreg;
3240 FLD (f_operand2_shifttype) = f_operand2_shifttype;
3243 FLD (f_set_cc_) = f_set_cc_;
3244 FLD (i_operand2_shiftreg) = & current_cpu->hardware.h_gr[f_operand2_shiftreg];
3245 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
3246 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
3247 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
3248 if (UNLIKELY(current_cpu->trace_extract_p))
3250 current_cpu->trace_stream
3251 << "0x" << hex << pc << dec << " (sfmt_add_reg_reg_shift)\t"
3252 << " f_rd:0x" << hex << f_rd << dec
3253 << " f_operand2_shiftreg:0x" << hex << f_operand2_shiftreg << dec
3254 << " f_operand2_shifttype:0x" << hex << f_operand2_shifttype << dec
3255 << " f_rm:0x" << hex << f_rm << dec
3256 << " f_rn:0x" << hex << f_rn << dec
3257 << " f_set_cc_:0x" << hex << f_set_cc_ << dec
3265 arm_extract_sfmt_add_imm (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
3266 arm_insn_word insn = entire_insn;
3267 #define FLD(f) abuf->fields.sfmt_and_imm.f
3273 f_set_cc_ = EXTRACT_LSB0_UINT (insn, 32, 20, 1);
3274 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
3275 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
3276 f_imm12 = RORSI (((EXTRACT_LSB0_UINT (insn, 32, 11, 12)) & (255)), ((2) * (((unsigned int) (((EXTRACT_LSB0_UINT (insn, 32, 11, 12)) & (3840))) >> (8)))));
3278 /* Record the fields for the semantic handler. */
3280 FLD (f_imm12) = f_imm12;
3282 FLD (f_set_cc_) = f_set_cc_;
3283 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
3284 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
3285 if (UNLIKELY(current_cpu->trace_extract_p))
3287 current_cpu->trace_stream
3288 << "0x" << hex << pc << dec << " (sfmt_add_imm)\t"
3289 << " f_rd:0x" << hex << f_rd << dec
3290 << " f_imm12:0x" << hex << f_imm12 << dec
3291 << " f_rn:0x" << hex << f_rn << dec
3292 << " f_set_cc_:0x" << hex << f_set_cc_ << dec
3300 arm_extract_sfmt_adc_reg_imm_shift (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
3301 arm_insn_word insn = entire_insn;
3302 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
3306 UINT f_operand2_shiftimm;
3307 UINT f_operand2_shifttype;
3310 f_set_cc_ = EXTRACT_LSB0_UINT (insn, 32, 20, 1);
3311 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
3312 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
3313 f_operand2_shiftimm = EXTRACT_LSB0_UINT (insn, 32, 11, 5);
3314 f_operand2_shifttype = EXTRACT_LSB0_UINT (insn, 32, 6, 2);
3315 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
3317 /* Record the fields for the semantic handler. */
3319 FLD (f_operand2_shiftimm) = f_operand2_shiftimm;
3320 FLD (f_operand2_shifttype) = f_operand2_shifttype;
3323 FLD (f_set_cc_) = f_set_cc_;
3324 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
3325 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
3326 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
3327 if (UNLIKELY(current_cpu->trace_extract_p))
3329 current_cpu->trace_stream
3330 << "0x" << hex << pc << dec << " (sfmt_adc_reg_imm_shift)\t"
3331 << " f_rd:0x" << hex << f_rd << dec
3332 << " f_operand2_shiftimm:0x" << hex << f_operand2_shiftimm << dec
3333 << " f_operand2_shifttype:0x" << hex << f_operand2_shifttype << dec
3334 << " f_rm:0x" << hex << f_rm << dec
3335 << " f_rn:0x" << hex << f_rn << dec
3336 << " f_set_cc_:0x" << hex << f_set_cc_ << dec
3344 arm_extract_sfmt_adc_reg_reg_shift (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
3345 arm_insn_word insn = entire_insn;
3346 #define FLD(f) abuf->fields.sfmt_and_reg_reg_shift.f
3350 UINT f_operand2_shiftreg;
3351 UINT f_operand2_shifttype;
3354 f_set_cc_ = EXTRACT_LSB0_UINT (insn, 32, 20, 1);
3355 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
3356 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
3357 f_operand2_shiftreg = EXTRACT_LSB0_UINT (insn, 32, 11, 4);
3358 f_operand2_shifttype = EXTRACT_LSB0_UINT (insn, 32, 6, 2);
3359 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
3361 /* Record the fields for the semantic handler. */
3363 FLD (f_operand2_shiftreg) = f_operand2_shiftreg;
3364 FLD (f_operand2_shifttype) = f_operand2_shifttype;
3367 FLD (f_set_cc_) = f_set_cc_;
3368 FLD (i_operand2_shiftreg) = & current_cpu->hardware.h_gr[f_operand2_shiftreg];
3369 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
3370 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
3371 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
3372 if (UNLIKELY(current_cpu->trace_extract_p))
3374 current_cpu->trace_stream
3375 << "0x" << hex << pc << dec << " (sfmt_adc_reg_reg_shift)\t"
3376 << " f_rd:0x" << hex << f_rd << dec
3377 << " f_operand2_shiftreg:0x" << hex << f_operand2_shiftreg << dec
3378 << " f_operand2_shifttype:0x" << hex << f_operand2_shifttype << dec
3379 << " f_rm:0x" << hex << f_rm << dec
3380 << " f_rn:0x" << hex << f_rn << dec
3381 << " f_set_cc_:0x" << hex << f_set_cc_ << dec
3389 arm_extract_sfmt_adc_imm (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
3390 arm_insn_word insn = entire_insn;
3391 #define FLD(f) abuf->fields.sfmt_and_imm.f
3397 f_set_cc_ = EXTRACT_LSB0_UINT (insn, 32, 20, 1);
3398 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
3399 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
3400 f_imm12 = RORSI (((EXTRACT_LSB0_UINT (insn, 32, 11, 12)) & (255)), ((2) * (((unsigned int) (((EXTRACT_LSB0_UINT (insn, 32, 11, 12)) & (3840))) >> (8)))));
3402 /* Record the fields for the semantic handler. */
3404 FLD (f_imm12) = f_imm12;
3406 FLD (f_set_cc_) = f_set_cc_;
3407 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
3408 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
3409 if (UNLIKELY(current_cpu->trace_extract_p))
3411 current_cpu->trace_stream
3412 << "0x" << hex << pc << dec << " (sfmt_adc_imm)\t"
3413 << " f_rd:0x" << hex << f_rd << dec
3414 << " f_imm12:0x" << hex << f_imm12 << dec
3415 << " f_rn:0x" << hex << f_rn << dec
3416 << " f_set_cc_:0x" << hex << f_set_cc_ << dec
3424 arm_extract_sfmt_tst_reg_imm_shift (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
3425 arm_insn_word insn = entire_insn;
3426 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
3429 UINT f_operand2_shiftimm;
3430 UINT f_operand2_shifttype;
3433 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
3434 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
3435 f_operand2_shiftimm = EXTRACT_LSB0_UINT (insn, 32, 11, 5);
3436 f_operand2_shifttype = EXTRACT_LSB0_UINT (insn, 32, 6, 2);
3437 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
3439 /* Record the fields for the semantic handler. */
3441 FLD (f_operand2_shiftimm) = f_operand2_shiftimm;
3442 FLD (f_operand2_shifttype) = f_operand2_shifttype;
3445 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
3446 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
3447 if (UNLIKELY(current_cpu->trace_extract_p))
3449 current_cpu->trace_stream
3450 << "0x" << hex << pc << dec << " (sfmt_tst_reg_imm_shift)\t"
3451 << " f_rd:0x" << hex << f_rd << dec
3452 << " f_operand2_shiftimm:0x" << hex << f_operand2_shiftimm << dec
3453 << " f_operand2_shifttype:0x" << hex << f_operand2_shifttype << dec
3454 << " f_rm:0x" << hex << f_rm << dec
3455 << " f_rn:0x" << hex << f_rn << dec
3463 arm_extract_sfmt_tst_reg_reg_shift (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
3464 arm_insn_word insn = entire_insn;
3465 #define FLD(f) abuf->fields.sfmt_and_reg_reg_shift.f
3468 UINT f_operand2_shiftreg;
3469 UINT f_operand2_shifttype;
3472 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
3473 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
3474 f_operand2_shiftreg = EXTRACT_LSB0_UINT (insn, 32, 11, 4);
3475 f_operand2_shifttype = EXTRACT_LSB0_UINT (insn, 32, 6, 2);
3476 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
3478 /* Record the fields for the semantic handler. */
3480 FLD (f_operand2_shiftreg) = f_operand2_shiftreg;
3481 FLD (f_operand2_shifttype) = f_operand2_shifttype;
3484 FLD (i_operand2_shiftreg) = & current_cpu->hardware.h_gr[f_operand2_shiftreg];
3485 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
3486 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
3487 if (UNLIKELY(current_cpu->trace_extract_p))
3489 current_cpu->trace_stream
3490 << "0x" << hex << pc << dec << " (sfmt_tst_reg_reg_shift)\t"
3491 << " f_rd:0x" << hex << f_rd << dec
3492 << " f_operand2_shiftreg:0x" << hex << f_operand2_shiftreg << dec
3493 << " f_operand2_shifttype:0x" << hex << f_operand2_shifttype << dec
3494 << " f_rm:0x" << hex << f_rm << dec
3495 << " f_rn:0x" << hex << f_rn << dec
3503 arm_extract_sfmt_tst_imm (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
3504 arm_insn_word insn = entire_insn;
3505 #define FLD(f) abuf->fields.sfmt_tst_imm.f
3507 UINT f_ror_imm8_rotate;
3508 UINT f_ror_imm8_value;
3511 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
3512 f_ror_imm8_rotate = EXTRACT_LSB0_UINT (insn, 32, 11, 4);
3513 f_ror_imm8_value = EXTRACT_LSB0_UINT (insn, 32, 7, 8);
3515 f_ror_imm8 = RORSI (f_ror_imm8_value, ((2) * (f_ror_imm8_rotate)));
3518 /* Record the fields for the semantic handler. */
3519 FLD (f_ror_imm8_rotate) = f_ror_imm8_rotate;
3521 FLD (f_ror_imm8) = f_ror_imm8;
3522 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
3523 if (UNLIKELY(current_cpu->trace_extract_p))
3525 current_cpu->trace_stream
3526 << "0x" << hex << pc << dec << " (sfmt_tst_imm)\t"
3527 << " f_ror_imm8_rotate:0x" << hex << f_ror_imm8_rotate << dec
3528 << " f_rn:0x" << hex << f_rn << dec
3529 << " f_ror_imm8:0x" << hex << f_ror_imm8 << dec
3537 arm_extract_sfmt_cmp_reg_imm_shift (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
3538 arm_insn_word insn = entire_insn;
3539 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
3542 UINT f_operand2_shiftimm;
3543 UINT f_operand2_shifttype;
3546 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
3547 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
3548 f_operand2_shiftimm = EXTRACT_LSB0_UINT (insn, 32, 11, 5);
3549 f_operand2_shifttype = EXTRACT_LSB0_UINT (insn, 32, 6, 2);
3550 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
3552 /* Record the fields for the semantic handler. */
3554 FLD (f_operand2_shiftimm) = f_operand2_shiftimm;
3555 FLD (f_operand2_shifttype) = f_operand2_shifttype;
3558 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
3559 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
3560 if (UNLIKELY(current_cpu->trace_extract_p))
3562 current_cpu->trace_stream
3563 << "0x" << hex << pc << dec << " (sfmt_cmp_reg_imm_shift)\t"
3564 << " f_rd:0x" << hex << f_rd << dec
3565 << " f_operand2_shiftimm:0x" << hex << f_operand2_shiftimm << dec
3566 << " f_operand2_shifttype:0x" << hex << f_operand2_shifttype << dec
3567 << " f_rm:0x" << hex << f_rm << dec
3568 << " f_rn:0x" << hex << f_rn << dec
3576 arm_extract_sfmt_cmp_reg_reg_shift (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
3577 arm_insn_word insn = entire_insn;
3578 #define FLD(f) abuf->fields.sfmt_and_reg_reg_shift.f
3581 UINT f_operand2_shiftreg;
3582 UINT f_operand2_shifttype;
3585 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
3586 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
3587 f_operand2_shiftreg = EXTRACT_LSB0_UINT (insn, 32, 11, 4);
3588 f_operand2_shifttype = EXTRACT_LSB0_UINT (insn, 32, 6, 2);
3589 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
3591 /* Record the fields for the semantic handler. */
3593 FLD (f_operand2_shiftreg) = f_operand2_shiftreg;
3594 FLD (f_operand2_shifttype) = f_operand2_shifttype;
3597 FLD (i_operand2_shiftreg) = & current_cpu->hardware.h_gr[f_operand2_shiftreg];
3598 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
3599 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
3600 if (UNLIKELY(current_cpu->trace_extract_p))
3602 current_cpu->trace_stream
3603 << "0x" << hex << pc << dec << " (sfmt_cmp_reg_reg_shift)\t"
3604 << " f_rd:0x" << hex << f_rd << dec
3605 << " f_operand2_shiftreg:0x" << hex << f_operand2_shiftreg << dec
3606 << " f_operand2_shifttype:0x" << hex << f_operand2_shifttype << dec
3607 << " f_rm:0x" << hex << f_rm << dec
3608 << " f_rn:0x" << hex << f_rn << dec
3616 arm_extract_sfmt_cmp_imm (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
3617 arm_insn_word insn = entire_insn;
3618 #define FLD(f) abuf->fields.sfmt_and_imm.f
3622 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
3623 f_imm12 = RORSI (((EXTRACT_LSB0_UINT (insn, 32, 11, 12)) & (255)), ((2) * (((unsigned int) (((EXTRACT_LSB0_UINT (insn, 32, 11, 12)) & (3840))) >> (8)))));
3625 /* Record the fields for the semantic handler. */
3626 FLD (f_imm12) = f_imm12;
3628 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
3629 if (UNLIKELY(current_cpu->trace_extract_p))
3631 current_cpu->trace_stream
3632 << "0x" << hex << pc << dec << " (sfmt_cmp_imm)\t"
3633 << " f_imm12:0x" << hex << f_imm12 << dec
3634 << " f_rn:0x" << hex << f_rn << dec
3642 arm_extract_sfmt_ldmda (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
3643 arm_insn_word insn = entire_insn;
3644 #define FLD(f) abuf->fields.sfmt_ldmda.f
3648 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
3649 f_reg_list = EXTRACT_LSB0_UINT (insn, 32, 15, 16);
3651 /* Record the fields for the semantic handler. */
3652 FLD (f_reg_list) = f_reg_list;
3654 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
3655 if (UNLIKELY(current_cpu->trace_extract_p))
3657 current_cpu->trace_stream
3658 << "0x" << hex << pc << dec << " (sfmt_ldmda)\t"
3659 << " f_reg_list:0x" << hex << f_reg_list << dec
3660 << " f_rn:0x" << hex << f_rn << dec
3668 arm_extract_sfmt_ldmda_sw (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
3669 arm_insn_word insn = entire_insn;
3670 #define FLD(f) abuf->fields.sfmt_ldmda.f
3674 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
3675 f_reg_list = EXTRACT_LSB0_UINT (insn, 32, 15, 16);
3677 /* Record the fields for the semantic handler. */
3678 FLD (f_reg_list) = f_reg_list;
3680 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
3681 if (UNLIKELY(current_cpu->trace_extract_p))
3683 current_cpu->trace_stream
3684 << "0x" << hex << pc << dec << " (sfmt_ldmda_sw)\t"
3685 << " f_reg_list:0x" << hex << f_reg_list << dec
3686 << " f_rn:0x" << hex << f_rn << dec
3694 arm_extract_sfmt_ldmda_wb (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
3695 arm_insn_word insn = entire_insn;
3696 #define FLD(f) abuf->fields.sfmt_ldmda.f
3700 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
3701 f_reg_list = EXTRACT_LSB0_UINT (insn, 32, 15, 16);
3703 /* Record the fields for the semantic handler. */
3704 FLD (f_reg_list) = f_reg_list;
3706 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
3707 if (UNLIKELY(current_cpu->trace_extract_p))
3709 current_cpu->trace_stream
3710 << "0x" << hex << pc << dec << " (sfmt_ldmda_wb)\t"
3711 << " f_reg_list:0x" << hex << f_reg_list << dec
3712 << " f_rn:0x" << hex << f_rn << dec
3720 arm_extract_sfmt_ldmda_sw_wb (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
3721 arm_insn_word insn = entire_insn;
3722 #define FLD(f) abuf->fields.sfmt_ldmda.f
3726 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
3727 f_reg_list = EXTRACT_LSB0_UINT (insn, 32, 15, 16);
3729 /* Record the fields for the semantic handler. */
3730 FLD (f_reg_list) = f_reg_list;
3732 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
3733 if (UNLIKELY(current_cpu->trace_extract_p))
3735 current_cpu->trace_stream
3736 << "0x" << hex << pc << dec << " (sfmt_ldmda_sw_wb)\t"
3737 << " f_reg_list:0x" << hex << f_reg_list << dec
3738 << " f_rn:0x" << hex << f_rn << dec
3746 arm_extract_sfmt_stmdb (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
3747 arm_insn_word insn = entire_insn;
3748 #define FLD(f) abuf->fields.sfmt_ldmda.f
3752 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
3753 f_reg_list = EXTRACT_LSB0_UINT (insn, 32, 15, 16);
3755 /* Record the fields for the semantic handler. */
3756 FLD (f_reg_list) = f_reg_list;
3758 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
3759 if (UNLIKELY(current_cpu->trace_extract_p))
3761 current_cpu->trace_stream
3762 << "0x" << hex << pc << dec << " (sfmt_stmdb)\t"
3763 << " f_reg_list:0x" << hex << f_reg_list << dec
3764 << " f_rn:0x" << hex << f_rn << dec
3772 arm_extract_sfmt_stmdb_sw (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
3773 arm_insn_word insn = entire_insn;
3774 #define FLD(f) abuf->fields.sfmt_ldmda.f
3778 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
3779 f_reg_list = EXTRACT_LSB0_UINT (insn, 32, 15, 16);
3781 /* Record the fields for the semantic handler. */
3782 FLD (f_reg_list) = f_reg_list;
3784 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
3785 if (UNLIKELY(current_cpu->trace_extract_p))
3787 current_cpu->trace_stream
3788 << "0x" << hex << pc << dec << " (sfmt_stmdb_sw)\t"
3789 << " f_reg_list:0x" << hex << f_reg_list << dec
3790 << " f_rn:0x" << hex << f_rn << dec
3798 arm_extract_sfmt_stmdb_wb (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
3799 arm_insn_word insn = entire_insn;
3800 #define FLD(f) abuf->fields.sfmt_ldmda.f
3804 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
3805 f_reg_list = EXTRACT_LSB0_UINT (insn, 32, 15, 16);
3807 /* Record the fields for the semantic handler. */
3808 FLD (f_reg_list) = f_reg_list;
3810 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
3811 if (UNLIKELY(current_cpu->trace_extract_p))
3813 current_cpu->trace_stream
3814 << "0x" << hex << pc << dec << " (sfmt_stmdb_wb)\t"
3815 << " f_reg_list:0x" << hex << f_reg_list << dec
3816 << " f_rn:0x" << hex << f_rn << dec
3824 arm_extract_sfmt_stmdb_sw_wb (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
3825 arm_insn_word insn = entire_insn;
3826 #define FLD(f) abuf->fields.sfmt_ldmda.f
3830 f_rn = EXTRACT_LSB0_UINT (insn, 32, 19, 4);
3831 f_reg_list = EXTRACT_LSB0_UINT (insn, 32, 15, 16);
3833 /* Record the fields for the semantic handler. */
3834 FLD (f_reg_list) = f_reg_list;
3836 FLD (i_rn) = & current_cpu->hardware.h_gr[f_rn];
3837 if (UNLIKELY(current_cpu->trace_extract_p))
3839 current_cpu->trace_stream
3840 << "0x" << hex << pc << dec << " (sfmt_stmdb_sw_wb)\t"
3841 << " f_reg_list:0x" << hex << f_reg_list << dec
3842 << " f_rn:0x" << hex << f_rn << dec
3850 arm_extract_sfmt_mrs_c (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
3851 arm_insn_word insn = entire_insn;
3852 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
3855 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
3857 /* Record the fields for the semantic handler. */
3859 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
3860 if (UNLIKELY(current_cpu->trace_extract_p))
3862 current_cpu->trace_stream
3863 << "0x" << hex << pc << dec << " (sfmt_mrs_c)\t"
3864 << " f_rd:0x" << hex << f_rd << dec
3872 arm_extract_sfmt_mrs_s (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
3873 arm_insn_word insn = entire_insn;
3874 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
3877 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 4);
3879 /* Record the fields for the semantic handler. */
3881 FLD (i_rd) = & current_cpu->hardware.h_gr[f_rd];
3882 if (UNLIKELY(current_cpu->trace_extract_p))
3884 current_cpu->trace_stream
3885 << "0x" << hex << pc << dec << " (sfmt_mrs_s)\t"
3886 << " f_rd:0x" << hex << f_rd << dec
3894 arm_extract_sfmt_msr_c (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
3895 arm_insn_word insn = entire_insn;
3896 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
3899 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
3901 /* Record the fields for the semantic handler. */
3903 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
3904 if (UNLIKELY(current_cpu->trace_extract_p))
3906 current_cpu->trace_stream
3907 << "0x" << hex << pc << dec << " (sfmt_msr_c)\t"
3908 << " f_rm:0x" << hex << f_rm << dec
3916 arm_extract_sfmt_msr_s (arm_scache* abuf, arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn){
3917 arm_insn_word insn = entire_insn;
3918 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
3921 f_rm = EXTRACT_LSB0_UINT (insn, 32, 3, 4);
3923 /* Record the fields for the semantic handler. */
3925 FLD (i_rm) = & current_cpu->hardware.h_gr[f_rm];
3926 if (UNLIKELY(current_cpu->trace_extract_p))
3928 current_cpu->trace_stream
3929 << "0x" << hex << pc << dec << " (sfmt_msr_s)\t"
3930 << " f_rm:0x" << hex << f_rm << dec