1 /* Decode header for arm.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 2000-2009 Red Hat, Inc.
7 This file is part of the Red Hat simulators.
20 typedef UINT arm_insn_word;
22 /* Enum declaration for instructions in cpu family arm. */
23 typedef enum arm_insn_type {
24 ARM_INSN_X_COND, ARM_INSN_X_AFTER, ARM_INSN_X_BEFORE, ARM_INSN_X_CTI_CHAIN
25 , ARM_INSN_X_CHAIN, ARM_INSN_X_BEGIN, ARM_INSN_X_INVALID, ARM_INSN_B
26 , ARM_INSN_BL, ARM_INSN_BX, ARM_INSN_LDR_POST_DEC_IMM_OFFSET, ARM_INSN_LDR_POST_DEC_REG_OFFSET
27 , ARM_INSN_LDR_POST_INC_IMM_OFFSET, ARM_INSN_LDR_POST_INC_REG_OFFSET, ARM_INSN_LDR_POST_DEC_NONPRIV_IMM_OFFSET, ARM_INSN_LDR_POST_DEC_NONPRIV_REG_OFFSET
28 , ARM_INSN_LDR_POST_INC_NONPRIV_IMM_OFFSET, ARM_INSN_LDR_POST_INC_NONPRIV_REG_OFFSET, ARM_INSN_LDR_PRE_DEC_IMM_OFFSET, ARM_INSN_LDR_PRE_DEC_REG_OFFSET
29 , ARM_INSN_LDR_PRE_INC_IMM_OFFSET, ARM_INSN_LDR_PRE_INC_REG_OFFSET, ARM_INSN_LDR_PRE_DEC_WB_IMM_OFFSET, ARM_INSN_LDR_PRE_DEC_WB_REG_OFFSET
30 , ARM_INSN_LDR_PRE_INC_WB_IMM_OFFSET, ARM_INSN_LDR_PRE_INC_WB_REG_OFFSET, ARM_INSN_LDRB_POST_DEC_IMM_OFFSET, ARM_INSN_LDRB_POST_DEC_REG_OFFSET
31 , ARM_INSN_LDRB_POST_INC_IMM_OFFSET, ARM_INSN_LDRB_POST_INC_REG_OFFSET, ARM_INSN_LDRB_POST_DEC_NONPRIV_IMM_OFFSET, ARM_INSN_LDRB_POST_DEC_NONPRIV_REG_OFFSET
32 , ARM_INSN_LDRB_POST_INC_NONPRIV_IMM_OFFSET, ARM_INSN_LDRB_POST_INC_NONPRIV_REG_OFFSET, ARM_INSN_LDRB_PRE_DEC_IMM_OFFSET, ARM_INSN_LDRB_PRE_DEC_REG_OFFSET
33 , ARM_INSN_LDRB_PRE_INC_IMM_OFFSET, ARM_INSN_LDRB_PRE_INC_REG_OFFSET, ARM_INSN_LDRB_PRE_DEC_WB_IMM_OFFSET, ARM_INSN_LDRB_PRE_DEC_WB_REG_OFFSET
34 , ARM_INSN_LDRB_PRE_INC_WB_IMM_OFFSET, ARM_INSN_LDRB_PRE_INC_WB_REG_OFFSET, ARM_INSN_STR_POST_DEC_IMM_OFFSET, ARM_INSN_STR_POST_DEC_REG_OFFSET
35 , ARM_INSN_STR_POST_INC_IMM_OFFSET, ARM_INSN_STR_POST_INC_REG_OFFSET, ARM_INSN_STR_POST_DEC_NONPRIV_IMM_OFFSET, ARM_INSN_STR_POST_DEC_NONPRIV_REG_OFFSET
36 , ARM_INSN_STR_POST_INC_NONPRIV_IMM_OFFSET, ARM_INSN_STR_POST_INC_NONPRIV_REG_OFFSET, ARM_INSN_STR_PRE_DEC_IMM_OFFSET, ARM_INSN_STR_PRE_DEC_REG_OFFSET
37 , ARM_INSN_STR_PRE_INC_IMM_OFFSET, ARM_INSN_STR_PRE_INC_REG_OFFSET, ARM_INSN_STR_PRE_DEC_WB_IMM_OFFSET, ARM_INSN_STR_PRE_DEC_WB_REG_OFFSET
38 , ARM_INSN_STR_PRE_INC_WB_IMM_OFFSET, ARM_INSN_STR_PRE_INC_WB_REG_OFFSET, ARM_INSN_STRB_POST_DEC_IMM_OFFSET, ARM_INSN_STRB_POST_DEC_REG_OFFSET
39 , ARM_INSN_STRB_POST_INC_IMM_OFFSET, ARM_INSN_STRB_POST_INC_REG_OFFSET, ARM_INSN_STRB_POST_DEC_NONPRIV_IMM_OFFSET, ARM_INSN_STRB_POST_DEC_NONPRIV_REG_OFFSET
40 , ARM_INSN_STRB_POST_INC_NONPRIV_IMM_OFFSET, ARM_INSN_STRB_POST_INC_NONPRIV_REG_OFFSET, ARM_INSN_STRB_PRE_DEC_IMM_OFFSET, ARM_INSN_STRB_PRE_DEC_REG_OFFSET
41 , ARM_INSN_STRB_PRE_INC_IMM_OFFSET, ARM_INSN_STRB_PRE_INC_REG_OFFSET, ARM_INSN_STRB_PRE_DEC_WB_IMM_OFFSET, ARM_INSN_STRB_PRE_DEC_WB_REG_OFFSET
42 , ARM_INSN_STRB_PRE_INC_WB_IMM_OFFSET, ARM_INSN_STRB_PRE_INC_WB_REG_OFFSET, ARM_INSN_STRH_PRE_DEC_IMM_OFFSET, ARM_INSN_STRH_PRE_DEC_REG_OFFSET
43 , ARM_INSN_STRH_PRE_INC_IMM_OFFSET, ARM_INSN_STRH_PRE_INC_REG_OFFSET, ARM_INSN_STRH_PRE_DEC_WB_IMM_OFFSET, ARM_INSN_STRH_PRE_DEC_WB_REG_OFFSET
44 , ARM_INSN_STRH_PRE_INC_WB_IMM_OFFSET, ARM_INSN_STRH_PRE_INC_WB_REG_OFFSET, ARM_INSN_STRH_POST_DEC_IMM_OFFSET, ARM_INSN_STRH_POST_DEC_REG_OFFSET
45 , ARM_INSN_STRH_POST_INC_IMM_OFFSET, ARM_INSN_STRH_POST_INC_REG_OFFSET, ARM_INSN_LDRSB_PRE_DEC_IMM_OFFSET, ARM_INSN_LDRSB_PRE_DEC_REG_OFFSET
46 , ARM_INSN_LDRSB_PRE_INC_IMM_OFFSET, ARM_INSN_LDRSB_PRE_INC_REG_OFFSET, ARM_INSN_LDRSB_PRE_DEC_WB_IMM_OFFSET, ARM_INSN_LDRSB_PRE_DEC_WB_REG_OFFSET
47 , ARM_INSN_LDRSB_PRE_INC_WB_IMM_OFFSET, ARM_INSN_LDRSB_PRE_INC_WB_REG_OFFSET, ARM_INSN_LDRSB_POST_DEC_IMM_OFFSET, ARM_INSN_LDRSB_POST_DEC_REG_OFFSET
48 , ARM_INSN_LDRSB_POST_INC_IMM_OFFSET, ARM_INSN_LDRSB_POST_INC_REG_OFFSET, ARM_INSN_LDRH_PRE_DEC_IMM_OFFSET, ARM_INSN_LDRH_PRE_DEC_REG_OFFSET
49 , ARM_INSN_LDRH_PRE_INC_IMM_OFFSET, ARM_INSN_LDRH_PRE_INC_REG_OFFSET, ARM_INSN_LDRH_PRE_DEC_WB_IMM_OFFSET, ARM_INSN_LDRH_PRE_DEC_WB_REG_OFFSET
50 , ARM_INSN_LDRH_PRE_INC_WB_IMM_OFFSET, ARM_INSN_LDRH_PRE_INC_WB_REG_OFFSET, ARM_INSN_LDRH_POST_DEC_IMM_OFFSET, ARM_INSN_LDRH_POST_DEC_REG_OFFSET
51 , ARM_INSN_LDRH_POST_INC_IMM_OFFSET, ARM_INSN_LDRH_POST_INC_REG_OFFSET, ARM_INSN_LDRSH_PRE_DEC_IMM_OFFSET, ARM_INSN_LDRSH_PRE_DEC_REG_OFFSET
52 , ARM_INSN_LDRSH_PRE_INC_IMM_OFFSET, ARM_INSN_LDRSH_PRE_INC_REG_OFFSET, ARM_INSN_LDRSH_PRE_DEC_WB_IMM_OFFSET, ARM_INSN_LDRSH_PRE_DEC_WB_REG_OFFSET
53 , ARM_INSN_LDRSH_PRE_INC_WB_IMM_OFFSET, ARM_INSN_LDRSH_PRE_INC_WB_REG_OFFSET, ARM_INSN_LDRSH_POST_DEC_IMM_OFFSET, ARM_INSN_LDRSH_POST_DEC_REG_OFFSET
54 , ARM_INSN_LDRSH_POST_INC_IMM_OFFSET, ARM_INSN_LDRSH_POST_INC_REG_OFFSET, ARM_INSN_MUL, ARM_INSN_MLA
55 , ARM_INSN_UMULL, ARM_INSN_UMLAL, ARM_INSN_SMULL, ARM_INSN_SMLAL
56 , ARM_INSN_SWP, ARM_INSN_SWPB, ARM_INSN_SWI, ARM_INSN_AND_REG_IMM_SHIFT
57 , ARM_INSN_AND_REG_REG_SHIFT, ARM_INSN_AND_IMM, ARM_INSN_ORR_REG_IMM_SHIFT, ARM_INSN_ORR_REG_REG_SHIFT
58 , ARM_INSN_ORR_IMM, ARM_INSN_EOR_REG_IMM_SHIFT, ARM_INSN_EOR_REG_REG_SHIFT, ARM_INSN_EOR_IMM
59 , ARM_INSN_MOV_REG_IMM_SHIFT, ARM_INSN_MOV_REG_REG_SHIFT, ARM_INSN_MOV_IMM, ARM_INSN_BIC_REG_IMM_SHIFT
60 , ARM_INSN_BIC_REG_REG_SHIFT, ARM_INSN_BIC_IMM, ARM_INSN_MVN_REG_IMM_SHIFT, ARM_INSN_MVN_REG_REG_SHIFT
61 , ARM_INSN_MVN_IMM, ARM_INSN_ADD_REG_IMM_SHIFT, ARM_INSN_ADD_REG_REG_SHIFT, ARM_INSN_ADD_IMM
62 , ARM_INSN_ADC_REG_IMM_SHIFT, ARM_INSN_ADC_REG_REG_SHIFT, ARM_INSN_ADC_IMM, ARM_INSN_SUB_REG_IMM_SHIFT
63 , ARM_INSN_SUB_REG_REG_SHIFT, ARM_INSN_SUB_IMM, ARM_INSN_SBC_REG_IMM_SHIFT, ARM_INSN_SBC_REG_REG_SHIFT
64 , ARM_INSN_SBC_IMM, ARM_INSN_RSB_REG_IMM_SHIFT, ARM_INSN_RSB_REG_REG_SHIFT, ARM_INSN_RSB_IMM
65 , ARM_INSN_RSC_REG_IMM_SHIFT, ARM_INSN_RSC_REG_REG_SHIFT, ARM_INSN_RSC_IMM, ARM_INSN_TST_REG_IMM_SHIFT
66 , ARM_INSN_TST_REG_REG_SHIFT, ARM_INSN_TST_IMM, ARM_INSN_TEQ_REG_IMM_SHIFT, ARM_INSN_TEQ_REG_REG_SHIFT
67 , ARM_INSN_TEQ_IMM, ARM_INSN_CMP_REG_IMM_SHIFT, ARM_INSN_CMP_REG_REG_SHIFT, ARM_INSN_CMP_IMM
68 , ARM_INSN_CMN_REG_IMM_SHIFT, ARM_INSN_CMN_REG_REG_SHIFT, ARM_INSN_CMN_IMM, ARM_INSN_LDMDA
69 , ARM_INSN_LDMDA_SW, ARM_INSN_LDMDA_WB, ARM_INSN_LDMDA_SW_WB, ARM_INSN_LDMIB
70 , ARM_INSN_LDMIB_SW, ARM_INSN_LDMIB_WB, ARM_INSN_LDMIB_SW_WB, ARM_INSN_LDMIA
71 , ARM_INSN_LDMIA_SW, ARM_INSN_LDMIA_WB, ARM_INSN_LDMIA_SW_WB, ARM_INSN_LDMDB
72 , ARM_INSN_LDMDB_SW, ARM_INSN_LDMDB_WB, ARM_INSN_LDMDB_SW_WB, ARM_INSN_STMDB
73 , ARM_INSN_STMDB_SW, ARM_INSN_STMDB_WB, ARM_INSN_STMDB_SW_WB, ARM_INSN_STMIB
74 , ARM_INSN_STMIB_SW, ARM_INSN_STMIB_WB, ARM_INSN_STMIB_SW_WB, ARM_INSN_STMIA
75 , ARM_INSN_STMIA_SW, ARM_INSN_STMIA_WB, ARM_INSN_STMIA_SW_WB, ARM_INSN_STMDA
76 , ARM_INSN_STMDA_SW, ARM_INSN_STMDA_WB, ARM_INSN_STMDA_SW_WB, ARM_INSN_MRS_C
77 , ARM_INSN_MRS_S, ARM_INSN_MSR_C, ARM_INSN_MSR_S
84 typedef sem_status (arm_sem_fn) (arm7f_cpu* cpu, arm_scache* sem);
87 // Instruction descriptor.
91 // computed-goto label pointer (pbb engine)
92 // FIXME: frag case to be redone (should instead point to usage table).
95 // scache engine executor for this insn
98 const char* insn_name;
99 enum arm_insn_type sem_index;
102 // idesc table: indexed by sem_index
103 static arm_idesc idesc_table[];
105 // semantic label pointers filled_in?
106 static bool idesc_table_initialized_p;
108 static arm_insn_type lookup_virtual (virtual_insn_type vit);
111 // Instruction argument buffer.
113 union arm_sem_fields {
114 struct { /* no operands */
136 UINT f_ror_imm8_rotate;
144 } sfmt_strh_pre_dec_imm_offset;
151 } sfmt_ldr_post_dec_imm_offset;
164 UINT f_operand2_shiftimm;
165 UINT f_operand2_shifttype;
170 } sfmt_and_reg_imm_shift;
194 SI* i_operand2_shiftreg;
198 UINT f_operand2_shiftreg;
199 UINT f_operand2_shifttype;
204 } sfmt_and_reg_reg_shift;
205 // This one is for chain/cti-chain virtual insns.
207 // Number of insns in pbb.
209 // This is used by chain insns and by untaken conditional branches.
211 arm_scache* branch_target;
213 // This one is for `before' virtual insns.
215 // The cache entry of the real insn.
220 // Simulator instruction cache.
232 // PC of this instruction.
239 arm_sem_fields fields;
243 // decode given instruction
244 void decode (arm7f_cpu* current_cpu, PCADDR pc, arm_insn_word base_insn, arm_insn_word entire_insn);
247 } // end arm7f namespace
249 // Decls of each semantic fn.
251 using arm7f::arm_sem_fn;
252 extern arm_sem_fn arm_sem_x_invalid;
253 extern arm_sem_fn arm_sem_b;
254 extern arm_sem_fn arm_sem_bl;
255 extern arm_sem_fn arm_sem_bx;
256 extern arm_sem_fn arm_sem_ldr_post_dec_imm_offset;
257 extern arm_sem_fn arm_sem_ldr_post_dec_reg_offset;
258 extern arm_sem_fn arm_sem_ldr_post_inc_imm_offset;
259 extern arm_sem_fn arm_sem_ldr_post_inc_reg_offset;
260 extern arm_sem_fn arm_sem_ldr_post_dec_nonpriv_imm_offset;
261 extern arm_sem_fn arm_sem_ldr_post_dec_nonpriv_reg_offset;
262 extern arm_sem_fn arm_sem_ldr_post_inc_nonpriv_imm_offset;
263 extern arm_sem_fn arm_sem_ldr_post_inc_nonpriv_reg_offset;
264 extern arm_sem_fn arm_sem_ldr_pre_dec_imm_offset;
265 extern arm_sem_fn arm_sem_ldr_pre_dec_reg_offset;
266 extern arm_sem_fn arm_sem_ldr_pre_inc_imm_offset;
267 extern arm_sem_fn arm_sem_ldr_pre_inc_reg_offset;
268 extern arm_sem_fn arm_sem_ldr_pre_dec_wb_imm_offset;
269 extern arm_sem_fn arm_sem_ldr_pre_dec_wb_reg_offset;
270 extern arm_sem_fn arm_sem_ldr_pre_inc_wb_imm_offset;
271 extern arm_sem_fn arm_sem_ldr_pre_inc_wb_reg_offset;
272 extern arm_sem_fn arm_sem_ldrb_post_dec_imm_offset;
273 extern arm_sem_fn arm_sem_ldrb_post_dec_reg_offset;
274 extern arm_sem_fn arm_sem_ldrb_post_inc_imm_offset;
275 extern arm_sem_fn arm_sem_ldrb_post_inc_reg_offset;
276 extern arm_sem_fn arm_sem_ldrb_post_dec_nonpriv_imm_offset;
277 extern arm_sem_fn arm_sem_ldrb_post_dec_nonpriv_reg_offset;
278 extern arm_sem_fn arm_sem_ldrb_post_inc_nonpriv_imm_offset;
279 extern arm_sem_fn arm_sem_ldrb_post_inc_nonpriv_reg_offset;
280 extern arm_sem_fn arm_sem_ldrb_pre_dec_imm_offset;
281 extern arm_sem_fn arm_sem_ldrb_pre_dec_reg_offset;
282 extern arm_sem_fn arm_sem_ldrb_pre_inc_imm_offset;
283 extern arm_sem_fn arm_sem_ldrb_pre_inc_reg_offset;
284 extern arm_sem_fn arm_sem_ldrb_pre_dec_wb_imm_offset;
285 extern arm_sem_fn arm_sem_ldrb_pre_dec_wb_reg_offset;
286 extern arm_sem_fn arm_sem_ldrb_pre_inc_wb_imm_offset;
287 extern arm_sem_fn arm_sem_ldrb_pre_inc_wb_reg_offset;
288 extern arm_sem_fn arm_sem_str_post_dec_imm_offset;
289 extern arm_sem_fn arm_sem_str_post_dec_reg_offset;
290 extern arm_sem_fn arm_sem_str_post_inc_imm_offset;
291 extern arm_sem_fn arm_sem_str_post_inc_reg_offset;
292 extern arm_sem_fn arm_sem_str_post_dec_nonpriv_imm_offset;
293 extern arm_sem_fn arm_sem_str_post_dec_nonpriv_reg_offset;
294 extern arm_sem_fn arm_sem_str_post_inc_nonpriv_imm_offset;
295 extern arm_sem_fn arm_sem_str_post_inc_nonpriv_reg_offset;
296 extern arm_sem_fn arm_sem_str_pre_dec_imm_offset;
297 extern arm_sem_fn arm_sem_str_pre_dec_reg_offset;
298 extern arm_sem_fn arm_sem_str_pre_inc_imm_offset;
299 extern arm_sem_fn arm_sem_str_pre_inc_reg_offset;
300 extern arm_sem_fn arm_sem_str_pre_dec_wb_imm_offset;
301 extern arm_sem_fn arm_sem_str_pre_dec_wb_reg_offset;
302 extern arm_sem_fn arm_sem_str_pre_inc_wb_imm_offset;
303 extern arm_sem_fn arm_sem_str_pre_inc_wb_reg_offset;
304 extern arm_sem_fn arm_sem_strb_post_dec_imm_offset;
305 extern arm_sem_fn arm_sem_strb_post_dec_reg_offset;
306 extern arm_sem_fn arm_sem_strb_post_inc_imm_offset;
307 extern arm_sem_fn arm_sem_strb_post_inc_reg_offset;
308 extern arm_sem_fn arm_sem_strb_post_dec_nonpriv_imm_offset;
309 extern arm_sem_fn arm_sem_strb_post_dec_nonpriv_reg_offset;
310 extern arm_sem_fn arm_sem_strb_post_inc_nonpriv_imm_offset;
311 extern arm_sem_fn arm_sem_strb_post_inc_nonpriv_reg_offset;
312 extern arm_sem_fn arm_sem_strb_pre_dec_imm_offset;
313 extern arm_sem_fn arm_sem_strb_pre_dec_reg_offset;
314 extern arm_sem_fn arm_sem_strb_pre_inc_imm_offset;
315 extern arm_sem_fn arm_sem_strb_pre_inc_reg_offset;
316 extern arm_sem_fn arm_sem_strb_pre_dec_wb_imm_offset;
317 extern arm_sem_fn arm_sem_strb_pre_dec_wb_reg_offset;
318 extern arm_sem_fn arm_sem_strb_pre_inc_wb_imm_offset;
319 extern arm_sem_fn arm_sem_strb_pre_inc_wb_reg_offset;
320 extern arm_sem_fn arm_sem_strh_pre_dec_imm_offset;
321 extern arm_sem_fn arm_sem_strh_pre_dec_reg_offset;
322 extern arm_sem_fn arm_sem_strh_pre_inc_imm_offset;
323 extern arm_sem_fn arm_sem_strh_pre_inc_reg_offset;
324 extern arm_sem_fn arm_sem_strh_pre_dec_wb_imm_offset;
325 extern arm_sem_fn arm_sem_strh_pre_dec_wb_reg_offset;
326 extern arm_sem_fn arm_sem_strh_pre_inc_wb_imm_offset;
327 extern arm_sem_fn arm_sem_strh_pre_inc_wb_reg_offset;
328 extern arm_sem_fn arm_sem_strh_post_dec_imm_offset;
329 extern arm_sem_fn arm_sem_strh_post_dec_reg_offset;
330 extern arm_sem_fn arm_sem_strh_post_inc_imm_offset;
331 extern arm_sem_fn arm_sem_strh_post_inc_reg_offset;
332 extern arm_sem_fn arm_sem_ldrsb_pre_dec_imm_offset;
333 extern arm_sem_fn arm_sem_ldrsb_pre_dec_reg_offset;
334 extern arm_sem_fn arm_sem_ldrsb_pre_inc_imm_offset;
335 extern arm_sem_fn arm_sem_ldrsb_pre_inc_reg_offset;
336 extern arm_sem_fn arm_sem_ldrsb_pre_dec_wb_imm_offset;
337 extern arm_sem_fn arm_sem_ldrsb_pre_dec_wb_reg_offset;
338 extern arm_sem_fn arm_sem_ldrsb_pre_inc_wb_imm_offset;
339 extern arm_sem_fn arm_sem_ldrsb_pre_inc_wb_reg_offset;
340 extern arm_sem_fn arm_sem_ldrsb_post_dec_imm_offset;
341 extern arm_sem_fn arm_sem_ldrsb_post_dec_reg_offset;
342 extern arm_sem_fn arm_sem_ldrsb_post_inc_imm_offset;
343 extern arm_sem_fn arm_sem_ldrsb_post_inc_reg_offset;
344 extern arm_sem_fn arm_sem_ldrh_pre_dec_imm_offset;
345 extern arm_sem_fn arm_sem_ldrh_pre_dec_reg_offset;
346 extern arm_sem_fn arm_sem_ldrh_pre_inc_imm_offset;
347 extern arm_sem_fn arm_sem_ldrh_pre_inc_reg_offset;
348 extern arm_sem_fn arm_sem_ldrh_pre_dec_wb_imm_offset;
349 extern arm_sem_fn arm_sem_ldrh_pre_dec_wb_reg_offset;
350 extern arm_sem_fn arm_sem_ldrh_pre_inc_wb_imm_offset;
351 extern arm_sem_fn arm_sem_ldrh_pre_inc_wb_reg_offset;
352 extern arm_sem_fn arm_sem_ldrh_post_dec_imm_offset;
353 extern arm_sem_fn arm_sem_ldrh_post_dec_reg_offset;
354 extern arm_sem_fn arm_sem_ldrh_post_inc_imm_offset;
355 extern arm_sem_fn arm_sem_ldrh_post_inc_reg_offset;
356 extern arm_sem_fn arm_sem_ldrsh_pre_dec_imm_offset;
357 extern arm_sem_fn arm_sem_ldrsh_pre_dec_reg_offset;
358 extern arm_sem_fn arm_sem_ldrsh_pre_inc_imm_offset;
359 extern arm_sem_fn arm_sem_ldrsh_pre_inc_reg_offset;
360 extern arm_sem_fn arm_sem_ldrsh_pre_dec_wb_imm_offset;
361 extern arm_sem_fn arm_sem_ldrsh_pre_dec_wb_reg_offset;
362 extern arm_sem_fn arm_sem_ldrsh_pre_inc_wb_imm_offset;
363 extern arm_sem_fn arm_sem_ldrsh_pre_inc_wb_reg_offset;
364 extern arm_sem_fn arm_sem_ldrsh_post_dec_imm_offset;
365 extern arm_sem_fn arm_sem_ldrsh_post_dec_reg_offset;
366 extern arm_sem_fn arm_sem_ldrsh_post_inc_imm_offset;
367 extern arm_sem_fn arm_sem_ldrsh_post_inc_reg_offset;
368 extern arm_sem_fn arm_sem_mul;
369 extern arm_sem_fn arm_sem_mla;
370 extern arm_sem_fn arm_sem_umull;
371 extern arm_sem_fn arm_sem_umlal;
372 extern arm_sem_fn arm_sem_smull;
373 extern arm_sem_fn arm_sem_smlal;
374 extern arm_sem_fn arm_sem_swp;
375 extern arm_sem_fn arm_sem_swpb;
376 extern arm_sem_fn arm_sem_swi;
377 extern arm_sem_fn arm_sem_and_reg_imm_shift;
378 extern arm_sem_fn arm_sem_and_reg_reg_shift;
379 extern arm_sem_fn arm_sem_and_imm;
380 extern arm_sem_fn arm_sem_orr_reg_imm_shift;
381 extern arm_sem_fn arm_sem_orr_reg_reg_shift;
382 extern arm_sem_fn arm_sem_orr_imm;
383 extern arm_sem_fn arm_sem_eor_reg_imm_shift;
384 extern arm_sem_fn arm_sem_eor_reg_reg_shift;
385 extern arm_sem_fn arm_sem_eor_imm;
386 extern arm_sem_fn arm_sem_mov_reg_imm_shift;
387 extern arm_sem_fn arm_sem_mov_reg_reg_shift;
388 extern arm_sem_fn arm_sem_mov_imm;
389 extern arm_sem_fn arm_sem_bic_reg_imm_shift;
390 extern arm_sem_fn arm_sem_bic_reg_reg_shift;
391 extern arm_sem_fn arm_sem_bic_imm;
392 extern arm_sem_fn arm_sem_mvn_reg_imm_shift;
393 extern arm_sem_fn arm_sem_mvn_reg_reg_shift;
394 extern arm_sem_fn arm_sem_mvn_imm;
395 extern arm_sem_fn arm_sem_add_reg_imm_shift;
396 extern arm_sem_fn arm_sem_add_reg_reg_shift;
397 extern arm_sem_fn arm_sem_add_imm;
398 extern arm_sem_fn arm_sem_adc_reg_imm_shift;
399 extern arm_sem_fn arm_sem_adc_reg_reg_shift;
400 extern arm_sem_fn arm_sem_adc_imm;
401 extern arm_sem_fn arm_sem_sub_reg_imm_shift;
402 extern arm_sem_fn arm_sem_sub_reg_reg_shift;
403 extern arm_sem_fn arm_sem_sub_imm;
404 extern arm_sem_fn arm_sem_sbc_reg_imm_shift;
405 extern arm_sem_fn arm_sem_sbc_reg_reg_shift;
406 extern arm_sem_fn arm_sem_sbc_imm;
407 extern arm_sem_fn arm_sem_rsb_reg_imm_shift;
408 extern arm_sem_fn arm_sem_rsb_reg_reg_shift;
409 extern arm_sem_fn arm_sem_rsb_imm;
410 extern arm_sem_fn arm_sem_rsc_reg_imm_shift;
411 extern arm_sem_fn arm_sem_rsc_reg_reg_shift;
412 extern arm_sem_fn arm_sem_rsc_imm;
413 extern arm_sem_fn arm_sem_tst_reg_imm_shift;
414 extern arm_sem_fn arm_sem_tst_reg_reg_shift;
415 extern arm_sem_fn arm_sem_tst_imm;
416 extern arm_sem_fn arm_sem_teq_reg_imm_shift;
417 extern arm_sem_fn arm_sem_teq_reg_reg_shift;
418 extern arm_sem_fn arm_sem_teq_imm;
419 extern arm_sem_fn arm_sem_cmp_reg_imm_shift;
420 extern arm_sem_fn arm_sem_cmp_reg_reg_shift;
421 extern arm_sem_fn arm_sem_cmp_imm;
422 extern arm_sem_fn arm_sem_cmn_reg_imm_shift;
423 extern arm_sem_fn arm_sem_cmn_reg_reg_shift;
424 extern arm_sem_fn arm_sem_cmn_imm;
425 extern arm_sem_fn arm_sem_ldmda;
426 extern arm_sem_fn arm_sem_ldmda_sw;
427 extern arm_sem_fn arm_sem_ldmda_wb;
428 extern arm_sem_fn arm_sem_ldmda_sw_wb;
429 extern arm_sem_fn arm_sem_ldmib;
430 extern arm_sem_fn arm_sem_ldmib_sw;
431 extern arm_sem_fn arm_sem_ldmib_wb;
432 extern arm_sem_fn arm_sem_ldmib_sw_wb;
433 extern arm_sem_fn arm_sem_ldmia;
434 extern arm_sem_fn arm_sem_ldmia_sw;
435 extern arm_sem_fn arm_sem_ldmia_wb;
436 extern arm_sem_fn arm_sem_ldmia_sw_wb;
437 extern arm_sem_fn arm_sem_ldmdb;
438 extern arm_sem_fn arm_sem_ldmdb_sw;
439 extern arm_sem_fn arm_sem_ldmdb_wb;
440 extern arm_sem_fn arm_sem_ldmdb_sw_wb;
441 extern arm_sem_fn arm_sem_stmdb;
442 extern arm_sem_fn arm_sem_stmdb_sw;
443 extern arm_sem_fn arm_sem_stmdb_wb;
444 extern arm_sem_fn arm_sem_stmdb_sw_wb;
445 extern arm_sem_fn arm_sem_stmib;
446 extern arm_sem_fn arm_sem_stmib_sw;
447 extern arm_sem_fn arm_sem_stmib_wb;
448 extern arm_sem_fn arm_sem_stmib_sw_wb;
449 extern arm_sem_fn arm_sem_stmia;
450 extern arm_sem_fn arm_sem_stmia_sw;
451 extern arm_sem_fn arm_sem_stmia_wb;
452 extern arm_sem_fn arm_sem_stmia_sw_wb;
453 extern arm_sem_fn arm_sem_stmda;
454 extern arm_sem_fn arm_sem_stmda_sw;
455 extern arm_sem_fn arm_sem_stmda_wb;
456 extern arm_sem_fn arm_sem_stmda_sw_wb;
457 extern arm_sem_fn arm_sem_mrs_c;
458 extern arm_sem_fn arm_sem_mrs_s;
459 extern arm_sem_fn arm_sem_msr_c;
460 extern arm_sem_fn arm_sem_msr_s;
462 #endif /* ARM_DECODE_H */