1 /* Simulator instruction semantics for arm.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 2000-2009 Red Hat, Inc.
7 This file is part of the Red Hat simulators.
15 using namespace arm7f; // FIXME: namespace organization still wip
17 #define GET_ATTR(name) GET_ATTR_##name ()
22 /* Enum declaration for semantic fragments in cpu family arm. */
23 typedef enum arm_frag_type {
24 ARM_FRAG_LIST_END, ARM_FRAG_MVN_REG_REG_SHIFT_HDR, ARM_FRAG_CMP_REG_REG_SHIFT_HDR, ARM_FRAG_TST_REG_REG_SHIFT_HDR
25 , ARM_FRAG_ORR_REG_REG_SHIFT_HDR, ARM_FRAG_MVN_REG_IMM_SHIFT_HDR, ARM_FRAG_CMP_REG_IMM_SHIFT_HDR, ARM_FRAG_TST_REG_IMM_SHIFT_HDR
26 , ARM_FRAG_ORR_REG_IMM_SHIFT_HDR, ARM_FRAG_STRB_POST_INC_NONPRIV_REG_OFFSET_HDR, ARM_FRAG_LDR_PRE_DEC_WB_REG_OFFSET_HDR, ARM_FRAG_LDR_POST_INC_NONPRIV_REG_OFFSET_HDR
27 , ARM_FRAG_STR_POST_DEC_REG_OFFSET_HDR, ARM_FRAG_LDR_POST_DEC_NONPRIV_REG_OFFSET_HDR, ARM_FRAG_STMDA_WB_HDR, ARM_FRAG_STMIA_WB_HDR
28 , ARM_FRAG_STMIB_WB_HDR, ARM_FRAG_STMDB_WB_HDR, ARM_FRAG_LDMIA_WB_HDR, ARM_FRAG_LDMIB_WB_HDR
29 , ARM_FRAG_STRB_POST_DEC_NONPRIV_IMM_OFFSET_HDR, ARM_FRAG_LDRB_POST_DEC_NONPRIV_IMM_OFFSET_HDR, ARM_FRAG_LDR_POST_DEC_NONPRIV_IMM_OFFSET_HDR, ARM_FRAG_X_HEADER
30 , ARM_FRAG_TST_REG_REG_SHIFT_TRLR, ARM_FRAG_TEQ_REG_IMM_SHIFT_TRLR, ARM_FRAG_AND_IMM_TRLR, ARM_FRAG_AND_REG_REG_SHIFT_TRLR
31 , ARM_FRAG_ORR_REG_IMM_SHIFT_TRLR, ARM_FRAG_UMULL_TRLR, ARM_FRAG_LDR_PRE_INC_IMM_OFFSET_TRLR, ARM_FRAG_LDRB_PRE_DEC_REG_OFFSET_TRLR
32 , ARM_FRAG_STR_PRE_DEC_REG_OFFSET_TRLR, ARM_FRAG_STR_PRE_DEC_IMM_OFFSET_TRLR, ARM_FRAG_STRH_PRE_DEC_IMM_OFFSET_TRLR, ARM_FRAG_LDRSB_PRE_DEC_IMM_OFFSET_TRLR
33 , ARM_FRAG_LDR_PRE_DEC_IMM_OFFSET_TRLR, ARM_FRAG_LDR_PRE_INC_REG_OFFSET_TRLR, ARM_FRAG_LDR_PRE_INC_WB_IMM_OFFSET_TRLR, ARM_FRAG_LDRB_PRE_DEC_WB_REG_OFFSET_TRLR
34 , ARM_FRAG_STR_PRE_DEC_WB_REG_OFFSET_TRLR, ARM_FRAG_STR_PRE_DEC_WB_IMM_OFFSET_TRLR, ARM_FRAG_STRH_PRE_DEC_WB_IMM_OFFSET_TRLR, ARM_FRAG_LDRSB_PRE_DEC_WB_IMM_OFFSET_TRLR
35 , ARM_FRAG_LDR_PRE_DEC_WB_IMM_OFFSET_TRLR, ARM_FRAG_LDR_PRE_INC_WB_REG_OFFSET_TRLR, ARM_FRAG_STRB_POST_INC_REG_OFFSET_TRLR, ARM_FRAG_STR_POST_INC_REG_OFFSET_TRLR
36 , ARM_FRAG_STR_POST_INC_IMM_OFFSET_TRLR, ARM_FRAG_LDRB_POST_INC_REG_OFFSET_TRLR, ARM_FRAG_STRB_POST_DEC_REG_OFFSET_TRLR, ARM_FRAG_STR_POST_DEC_REG_OFFSET_TRLR
37 , ARM_FRAG_STR_POST_DEC_IMM_OFFSET_TRLR, ARM_FRAG_LDRB_POST_DEC_REG_OFFSET_TRLR, ARM_FRAG_X_TRAILER, ARM_FRAG_X_COND_MID
38 , ARM_FRAG_X_AFTER_MID, ARM_FRAG_X_BEFORE_MID, ARM_FRAG_X_CTI_CHAIN_MID, ARM_FRAG_X_CHAIN_MID
39 , ARM_FRAG_X_BEGIN_MID, ARM_FRAG_X_INVALID_MID, ARM_FRAG_B_MID, ARM_FRAG_BL_MID
40 , ARM_FRAG_BX_MID, ARM_FRAG_LDR_POST_DEC_IMM_OFFSET_MID, ARM_FRAG_LDR_POST_DEC_REG_OFFSET_MID, ARM_FRAG_LDR_POST_INC_IMM_OFFSET_MID
41 , ARM_FRAG_LDR_POST_INC_REG_OFFSET_MID, ARM_FRAG_LDR_POST_DEC_NONPRIV_IMM_OFFSET_MID, ARM_FRAG_LDR_POST_DEC_NONPRIV_REG_OFFSET_MID, ARM_FRAG_LDR_POST_INC_NONPRIV_IMM_OFFSET_MID
42 , ARM_FRAG_LDR_POST_INC_NONPRIV_REG_OFFSET_MID, ARM_FRAG_LDR_PRE_DEC_IMM_OFFSET_MID, ARM_FRAG_LDR_PRE_DEC_REG_OFFSET_MID, ARM_FRAG_LDR_PRE_INC_IMM_OFFSET_MID
43 , ARM_FRAG_LDR_PRE_INC_REG_OFFSET_MID, ARM_FRAG_LDR_PRE_DEC_WB_IMM_OFFSET_MID, ARM_FRAG_LDR_PRE_DEC_WB_REG_OFFSET_MID, ARM_FRAG_LDR_PRE_INC_WB_IMM_OFFSET_MID
44 , ARM_FRAG_LDR_PRE_INC_WB_REG_OFFSET_MID, ARM_FRAG_LDRB_POST_DEC_IMM_OFFSET_MID, ARM_FRAG_LDRB_POST_INC_IMM_OFFSET_MID, ARM_FRAG_LDRB_POST_DEC_NONPRIV_IMM_OFFSET_MID
45 , ARM_FRAG_LDRB_POST_INC_NONPRIV_IMM_OFFSET_MID, ARM_FRAG_LDRB_PRE_DEC_IMM_OFFSET_MID, ARM_FRAG_LDRB_PRE_DEC_REG_OFFSET_MID, ARM_FRAG_LDRB_PRE_INC_IMM_OFFSET_MID
46 , ARM_FRAG_LDRB_PRE_INC_REG_OFFSET_MID, ARM_FRAG_LDRB_PRE_DEC_WB_IMM_OFFSET_MID, ARM_FRAG_LDRB_PRE_DEC_WB_REG_OFFSET_MID, ARM_FRAG_LDRB_PRE_INC_WB_IMM_OFFSET_MID
47 , ARM_FRAG_LDRB_PRE_INC_WB_REG_OFFSET_MID, ARM_FRAG_STR_POST_DEC_IMM_OFFSET_MID, ARM_FRAG_STR_POST_INC_IMM_OFFSET_MID, ARM_FRAG_STR_POST_DEC_NONPRIV_IMM_OFFSET_MID
48 , ARM_FRAG_STR_POST_INC_NONPRIV_IMM_OFFSET_MID, ARM_FRAG_STR_PRE_DEC_IMM_OFFSET_MID, ARM_FRAG_STR_PRE_DEC_REG_OFFSET_MID, ARM_FRAG_STR_PRE_INC_IMM_OFFSET_MID
49 , ARM_FRAG_STR_PRE_INC_REG_OFFSET_MID, ARM_FRAG_STR_PRE_DEC_WB_IMM_OFFSET_MID, ARM_FRAG_STR_PRE_DEC_WB_REG_OFFSET_MID, ARM_FRAG_STR_PRE_INC_WB_IMM_OFFSET_MID
50 , ARM_FRAG_STR_PRE_INC_WB_REG_OFFSET_MID, ARM_FRAG_STRB_POST_DEC_IMM_OFFSET_MID, ARM_FRAG_STRB_POST_INC_IMM_OFFSET_MID, ARM_FRAG_STRB_POST_DEC_NONPRIV_IMM_OFFSET_MID
51 , ARM_FRAG_STRB_POST_INC_NONPRIV_IMM_OFFSET_MID, ARM_FRAG_STRB_POST_INC_NONPRIV_REG_OFFSET_MID, ARM_FRAG_STRB_PRE_DEC_IMM_OFFSET_MID, ARM_FRAG_STRB_PRE_DEC_REG_OFFSET_MID
52 , ARM_FRAG_STRB_PRE_INC_IMM_OFFSET_MID, ARM_FRAG_STRB_PRE_INC_REG_OFFSET_MID, ARM_FRAG_STRB_PRE_DEC_WB_IMM_OFFSET_MID, ARM_FRAG_STRB_PRE_DEC_WB_REG_OFFSET_MID
53 , ARM_FRAG_STRB_PRE_INC_WB_IMM_OFFSET_MID, ARM_FRAG_STRB_PRE_INC_WB_REG_OFFSET_MID, ARM_FRAG_STRH_PRE_DEC_IMM_OFFSET_MID, ARM_FRAG_STRH_PRE_DEC_REG_OFFSET_MID
54 , ARM_FRAG_STRH_PRE_INC_IMM_OFFSET_MID, ARM_FRAG_STRH_PRE_INC_REG_OFFSET_MID, ARM_FRAG_STRH_PRE_DEC_WB_IMM_OFFSET_MID, ARM_FRAG_STRH_PRE_DEC_WB_REG_OFFSET_MID
55 , ARM_FRAG_STRH_PRE_INC_WB_IMM_OFFSET_MID, ARM_FRAG_STRH_PRE_INC_WB_REG_OFFSET_MID, ARM_FRAG_STRH_POST_DEC_IMM_OFFSET_MID, ARM_FRAG_STRH_POST_DEC_REG_OFFSET_MID
56 , ARM_FRAG_STRH_POST_INC_IMM_OFFSET_MID, ARM_FRAG_STRH_POST_INC_REG_OFFSET_MID, ARM_FRAG_LDRSB_PRE_DEC_IMM_OFFSET_MID, ARM_FRAG_LDRSB_PRE_DEC_REG_OFFSET_MID
57 , ARM_FRAG_LDRSB_PRE_INC_IMM_OFFSET_MID, ARM_FRAG_LDRSB_PRE_INC_REG_OFFSET_MID, ARM_FRAG_LDRSB_PRE_DEC_WB_IMM_OFFSET_MID, ARM_FRAG_LDRSB_PRE_DEC_WB_REG_OFFSET_MID
58 , ARM_FRAG_LDRSB_PRE_INC_WB_IMM_OFFSET_MID, ARM_FRAG_LDRSB_PRE_INC_WB_REG_OFFSET_MID, ARM_FRAG_LDRSB_POST_DEC_IMM_OFFSET_MID, ARM_FRAG_LDRSB_POST_DEC_REG_OFFSET_MID
59 , ARM_FRAG_LDRSB_POST_INC_IMM_OFFSET_MID, ARM_FRAG_LDRSB_POST_INC_REG_OFFSET_MID, ARM_FRAG_LDRH_PRE_DEC_IMM_OFFSET_MID, ARM_FRAG_LDRH_PRE_DEC_REG_OFFSET_MID
60 , ARM_FRAG_LDRH_PRE_INC_IMM_OFFSET_MID, ARM_FRAG_LDRH_PRE_INC_REG_OFFSET_MID, ARM_FRAG_LDRH_PRE_DEC_WB_IMM_OFFSET_MID, ARM_FRAG_LDRH_PRE_DEC_WB_REG_OFFSET_MID
61 , ARM_FRAG_LDRH_PRE_INC_WB_IMM_OFFSET_MID, ARM_FRAG_LDRH_PRE_INC_WB_REG_OFFSET_MID, ARM_FRAG_LDRH_POST_DEC_IMM_OFFSET_MID, ARM_FRAG_LDRH_POST_DEC_REG_OFFSET_MID
62 , ARM_FRAG_LDRH_POST_INC_IMM_OFFSET_MID, ARM_FRAG_LDRH_POST_INC_REG_OFFSET_MID, ARM_FRAG_LDRSH_PRE_DEC_IMM_OFFSET_MID, ARM_FRAG_LDRSH_PRE_DEC_REG_OFFSET_MID
63 , ARM_FRAG_LDRSH_PRE_INC_IMM_OFFSET_MID, ARM_FRAG_LDRSH_PRE_INC_REG_OFFSET_MID, ARM_FRAG_LDRSH_PRE_DEC_WB_IMM_OFFSET_MID, ARM_FRAG_LDRSH_PRE_DEC_WB_REG_OFFSET_MID
64 , ARM_FRAG_LDRSH_PRE_INC_WB_IMM_OFFSET_MID, ARM_FRAG_LDRSH_PRE_INC_WB_REG_OFFSET_MID, ARM_FRAG_LDRSH_POST_DEC_IMM_OFFSET_MID, ARM_FRAG_LDRSH_POST_DEC_REG_OFFSET_MID
65 , ARM_FRAG_LDRSH_POST_INC_IMM_OFFSET_MID, ARM_FRAG_LDRSH_POST_INC_REG_OFFSET_MID, ARM_FRAG_MUL_MID, ARM_FRAG_MLA_MID
66 , ARM_FRAG_UMULL_MID, ARM_FRAG_UMLAL_MID, ARM_FRAG_SMULL_MID, ARM_FRAG_SMLAL_MID
67 , ARM_FRAG_SWP_MID, ARM_FRAG_SWPB_MID, ARM_FRAG_SWI_MID, ARM_FRAG_AND_REG_IMM_SHIFT_MID
68 , ARM_FRAG_AND_REG_REG_SHIFT_MID, ARM_FRAG_AND_IMM_MID, ARM_FRAG_ORR_REG_IMM_SHIFT_MID, ARM_FRAG_ORR_REG_REG_SHIFT_MID
69 , ARM_FRAG_ORR_IMM_MID, ARM_FRAG_EOR_REG_IMM_SHIFT_MID, ARM_FRAG_EOR_REG_REG_SHIFT_MID, ARM_FRAG_EOR_IMM_MID
70 , ARM_FRAG_MOV_REG_IMM_SHIFT_MID, ARM_FRAG_MOV_REG_REG_SHIFT_MID, ARM_FRAG_MOV_IMM_MID, ARM_FRAG_BIC_REG_IMM_SHIFT_MID
71 , ARM_FRAG_BIC_REG_REG_SHIFT_MID, ARM_FRAG_BIC_IMM_MID, ARM_FRAG_MVN_REG_IMM_SHIFT_MID, ARM_FRAG_MVN_REG_REG_SHIFT_MID
72 , ARM_FRAG_MVN_IMM_MID, ARM_FRAG_ADD_REG_IMM_SHIFT_MID, ARM_FRAG_ADD_REG_REG_SHIFT_MID, ARM_FRAG_ADD_IMM_MID
73 , ARM_FRAG_ADC_REG_IMM_SHIFT_MID, ARM_FRAG_ADC_REG_REG_SHIFT_MID, ARM_FRAG_ADC_IMM_MID, ARM_FRAG_SUB_REG_IMM_SHIFT_MID
74 , ARM_FRAG_SUB_REG_REG_SHIFT_MID, ARM_FRAG_SUB_IMM_MID, ARM_FRAG_SBC_REG_IMM_SHIFT_MID, ARM_FRAG_SBC_REG_REG_SHIFT_MID
75 , ARM_FRAG_SBC_IMM_MID, ARM_FRAG_RSB_REG_IMM_SHIFT_MID, ARM_FRAG_RSB_REG_REG_SHIFT_MID, ARM_FRAG_RSB_IMM_MID
76 , ARM_FRAG_RSC_REG_IMM_SHIFT_MID, ARM_FRAG_RSC_REG_REG_SHIFT_MID, ARM_FRAG_RSC_IMM_MID, ARM_FRAG_TST_REG_IMM_SHIFT_MID
77 , ARM_FRAG_TST_REG_REG_SHIFT_MID, ARM_FRAG_TST_IMM_MID, ARM_FRAG_TEQ_REG_IMM_SHIFT_MID, ARM_FRAG_TEQ_REG_REG_SHIFT_MID
78 , ARM_FRAG_TEQ_IMM_MID, ARM_FRAG_CMP_REG_IMM_SHIFT_MID, ARM_FRAG_CMP_REG_REG_SHIFT_MID, ARM_FRAG_CMP_IMM_MID
79 , ARM_FRAG_CMN_REG_IMM_SHIFT_MID, ARM_FRAG_CMN_REG_REG_SHIFT_MID, ARM_FRAG_CMN_IMM_MID, ARM_FRAG_LDMDA_MID
80 , ARM_FRAG_LDMDA_SW_MID, ARM_FRAG_LDMDA_WB_MID, ARM_FRAG_LDMDA_SW_WB_MID, ARM_FRAG_LDMIB_MID
81 , ARM_FRAG_LDMIB_SW_MID, ARM_FRAG_LDMIB_WB_MID, ARM_FRAG_LDMIB_SW_WB_MID, ARM_FRAG_LDMIA_MID
82 , ARM_FRAG_LDMIA_SW_MID, ARM_FRAG_LDMIA_WB_MID, ARM_FRAG_LDMIA_SW_WB_MID, ARM_FRAG_LDMDB_MID
83 , ARM_FRAG_LDMDB_SW_MID, ARM_FRAG_LDMDB_WB_MID, ARM_FRAG_LDMDB_SW_WB_MID, ARM_FRAG_STMDB_MID
84 , ARM_FRAG_STMDB_SW_MID, ARM_FRAG_STMDB_WB_MID, ARM_FRAG_STMDB_SW_WB_MID, ARM_FRAG_STMIB_MID
85 , ARM_FRAG_STMIB_SW_MID, ARM_FRAG_STMIB_WB_MID, ARM_FRAG_STMIB_SW_WB_MID, ARM_FRAG_STMIA_MID
86 , ARM_FRAG_STMIA_SW_MID, ARM_FRAG_STMIA_WB_MID, ARM_FRAG_STMIA_SW_WB_MID, ARM_FRAG_STMDA_MID
87 , ARM_FRAG_STMDA_SW_MID, ARM_FRAG_STMDA_WB_MID, ARM_FRAG_STMDA_SW_WB_MID, ARM_FRAG_MRS_C_MID
88 , ARM_FRAG_MRS_S_MID, ARM_FRAG_MSR_C_MID, ARM_FRAG_MSR_S_MID, ARM_FRAG_MAX
91 struct arm_insn_frag {
93 // 4: header+middle+trailer+delimiter
94 ARM_FRAG_TYPE ftype[4];
97 struct arm_pbb_label {
102 } // end arm7f namespace
104 // Table of frags used by each insn.
106 const arm_insn_frag arm_frag_usage[] = {
107 { ARM_INSN_X_COND, ARM_FRAG_X_COND_MID, ARM_FRAG_LIST_END },
108 { ARM_INSN_X_AFTER, ARM_FRAG_X_AFTER_MID, ARM_FRAG_LIST_END },
109 { ARM_INSN_X_BEFORE, ARM_FRAG_X_BEFORE_MID, ARM_FRAG_LIST_END },
110 { ARM_INSN_X_CTI_CHAIN, ARM_FRAG_X_CTI_CHAIN_MID, ARM_FRAG_LIST_END },
111 { ARM_INSN_X_CHAIN, ARM_FRAG_X_CHAIN_MID, ARM_FRAG_LIST_END },
112 { ARM_INSN_X_BEGIN, ARM_FRAG_X_BEGIN_MID, ARM_FRAG_LIST_END },
113 { ARM_INSN_X_INVALID, ARM_FRAG_X_INVALID_MID, ARM_FRAG_LIST_END },
114 { ARM_INSN_B, ARM_FRAG_B_MID, ARM_FRAG_LIST_END },
115 { ARM_INSN_BL, ARM_FRAG_BL_MID, ARM_FRAG_LIST_END },
116 { ARM_INSN_BX, ARM_FRAG_BX_MID, ARM_FRAG_LIST_END },
117 { ARM_INSN_LDR_POST_DEC_IMM_OFFSET, ARM_FRAG_LDR_POST_DEC_IMM_OFFSET_MID, ARM_FRAG_LIST_END },
118 { ARM_INSN_LDR_POST_DEC_REG_OFFSET, ARM_FRAG_LDR_POST_DEC_REG_OFFSET_MID, ARM_FRAG_LIST_END },
119 { ARM_INSN_LDR_POST_INC_IMM_OFFSET, ARM_FRAG_LDR_POST_DEC_NONPRIV_IMM_OFFSET_HDR, ARM_FRAG_LDR_POST_INC_IMM_OFFSET_MID, ARM_FRAG_LIST_END },
120 { ARM_INSN_LDR_POST_INC_REG_OFFSET, ARM_FRAG_LDR_POST_DEC_NONPRIV_REG_OFFSET_HDR, ARM_FRAG_LDR_POST_INC_REG_OFFSET_MID, ARM_FRAG_LIST_END },
121 { ARM_INSN_LDR_POST_DEC_NONPRIV_IMM_OFFSET, ARM_FRAG_LDR_POST_DEC_NONPRIV_IMM_OFFSET_HDR, ARM_FRAG_LDR_POST_DEC_NONPRIV_IMM_OFFSET_MID, ARM_FRAG_LIST_END },
122 { ARM_INSN_LDR_POST_DEC_NONPRIV_REG_OFFSET, ARM_FRAG_LDR_POST_DEC_NONPRIV_REG_OFFSET_HDR, ARM_FRAG_LDR_POST_DEC_NONPRIV_REG_OFFSET_MID, ARM_FRAG_LIST_END },
123 { ARM_INSN_LDR_POST_INC_NONPRIV_IMM_OFFSET, ARM_FRAG_LDR_POST_INC_NONPRIV_IMM_OFFSET_MID, ARM_FRAG_LIST_END },
124 { ARM_INSN_LDR_POST_INC_NONPRIV_REG_OFFSET, ARM_FRAG_LDR_POST_INC_NONPRIV_REG_OFFSET_HDR, ARM_FRAG_LDR_POST_INC_NONPRIV_REG_OFFSET_MID, ARM_FRAG_LIST_END },
125 { ARM_INSN_LDR_PRE_DEC_IMM_OFFSET, ARM_FRAG_LDR_PRE_DEC_IMM_OFFSET_MID, ARM_FRAG_LDR_PRE_DEC_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
126 { ARM_INSN_LDR_PRE_DEC_REG_OFFSET, ARM_FRAG_LDR_PRE_DEC_WB_REG_OFFSET_HDR, ARM_FRAG_LDR_PRE_DEC_REG_OFFSET_MID, ARM_FRAG_LIST_END },
127 { ARM_INSN_LDR_PRE_INC_IMM_OFFSET, ARM_FRAG_LDR_PRE_INC_IMM_OFFSET_MID, ARM_FRAG_LDR_PRE_INC_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
128 { ARM_INSN_LDR_PRE_INC_REG_OFFSET, ARM_FRAG_LDR_PRE_DEC_WB_REG_OFFSET_HDR, ARM_FRAG_LDR_PRE_INC_REG_OFFSET_MID, ARM_FRAG_LDR_PRE_INC_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
129 { ARM_INSN_LDR_PRE_DEC_WB_IMM_OFFSET, ARM_FRAG_LDR_PRE_DEC_WB_IMM_OFFSET_MID, ARM_FRAG_LDR_PRE_DEC_WB_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
130 { ARM_INSN_LDR_PRE_DEC_WB_REG_OFFSET, ARM_FRAG_LDR_PRE_DEC_WB_REG_OFFSET_HDR, ARM_FRAG_LDR_PRE_DEC_WB_REG_OFFSET_MID, ARM_FRAG_LIST_END },
131 { ARM_INSN_LDR_PRE_INC_WB_IMM_OFFSET, ARM_FRAG_LDR_PRE_INC_WB_IMM_OFFSET_MID, ARM_FRAG_LDR_PRE_INC_WB_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
132 { ARM_INSN_LDR_PRE_INC_WB_REG_OFFSET, ARM_FRAG_LDR_PRE_DEC_WB_REG_OFFSET_HDR, ARM_FRAG_LDR_PRE_INC_WB_REG_OFFSET_MID, ARM_FRAG_LDR_PRE_INC_WB_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
133 { ARM_INSN_LDRB_POST_DEC_IMM_OFFSET, ARM_FRAG_LDRB_POST_DEC_IMM_OFFSET_MID, ARM_FRAG_LIST_END },
134 { ARM_INSN_LDRB_POST_DEC_REG_OFFSET, ARM_FRAG_LDR_POST_INC_NONPRIV_REG_OFFSET_HDR, ARM_FRAG_LDRB_POST_DEC_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
135 { ARM_INSN_LDRB_POST_INC_IMM_OFFSET, ARM_FRAG_LDRB_POST_DEC_NONPRIV_IMM_OFFSET_HDR, ARM_FRAG_LDRB_POST_INC_IMM_OFFSET_MID, ARM_FRAG_LIST_END },
136 { ARM_INSN_LDRB_POST_INC_REG_OFFSET, ARM_FRAG_LDR_POST_INC_NONPRIV_REG_OFFSET_HDR, ARM_FRAG_LDRB_POST_INC_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
137 { ARM_INSN_LDRB_POST_DEC_NONPRIV_IMM_OFFSET, ARM_FRAG_LDRB_POST_DEC_NONPRIV_IMM_OFFSET_HDR, ARM_FRAG_LDRB_POST_DEC_NONPRIV_IMM_OFFSET_MID, ARM_FRAG_LIST_END },
138 { ARM_INSN_LDRB_POST_DEC_NONPRIV_REG_OFFSET, ARM_FRAG_LDR_POST_INC_NONPRIV_REG_OFFSET_HDR, ARM_FRAG_LDRB_POST_DEC_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
139 { ARM_INSN_LDRB_POST_INC_NONPRIV_IMM_OFFSET, ARM_FRAG_LDRB_POST_INC_NONPRIV_IMM_OFFSET_MID, ARM_FRAG_LIST_END },
140 { ARM_INSN_LDRB_POST_INC_NONPRIV_REG_OFFSET, ARM_FRAG_LDR_POST_INC_NONPRIV_REG_OFFSET_HDR, ARM_FRAG_LDRB_POST_INC_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
141 { ARM_INSN_LDRB_PRE_DEC_IMM_OFFSET, ARM_FRAG_LDRB_PRE_DEC_IMM_OFFSET_MID, ARM_FRAG_LDR_PRE_INC_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
142 { ARM_INSN_LDRB_PRE_DEC_REG_OFFSET, ARM_FRAG_LDR_PRE_DEC_WB_REG_OFFSET_HDR, ARM_FRAG_LDRB_PRE_DEC_REG_OFFSET_MID, ARM_FRAG_LDRB_PRE_DEC_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
143 { ARM_INSN_LDRB_PRE_INC_IMM_OFFSET, ARM_FRAG_LDRB_PRE_INC_IMM_OFFSET_MID, ARM_FRAG_LDR_PRE_INC_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
144 { ARM_INSN_LDRB_PRE_INC_REG_OFFSET, ARM_FRAG_LDR_PRE_DEC_WB_REG_OFFSET_HDR, ARM_FRAG_LDRB_PRE_INC_REG_OFFSET_MID, ARM_FRAG_LDRB_PRE_DEC_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
145 { ARM_INSN_LDRB_PRE_DEC_WB_IMM_OFFSET, ARM_FRAG_LDRB_PRE_DEC_WB_IMM_OFFSET_MID, ARM_FRAG_LDR_PRE_INC_WB_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
146 { ARM_INSN_LDRB_PRE_DEC_WB_REG_OFFSET, ARM_FRAG_LDR_PRE_DEC_WB_REG_OFFSET_HDR, ARM_FRAG_LDRB_PRE_DEC_WB_REG_OFFSET_MID, ARM_FRAG_LDRB_PRE_DEC_WB_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
147 { ARM_INSN_LDRB_PRE_INC_WB_IMM_OFFSET, ARM_FRAG_LDRB_PRE_INC_WB_IMM_OFFSET_MID, ARM_FRAG_LDR_PRE_INC_WB_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
148 { ARM_INSN_LDRB_PRE_INC_WB_REG_OFFSET, ARM_FRAG_LDR_PRE_DEC_WB_REG_OFFSET_HDR, ARM_FRAG_LDRB_PRE_INC_WB_REG_OFFSET_MID, ARM_FRAG_LDRB_PRE_DEC_WB_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
149 { ARM_INSN_STR_POST_DEC_IMM_OFFSET, ARM_FRAG_STR_POST_DEC_IMM_OFFSET_MID, ARM_FRAG_STR_POST_DEC_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
150 { ARM_INSN_STR_POST_DEC_REG_OFFSET, ARM_FRAG_STR_POST_DEC_REG_OFFSET_HDR, ARM_FRAG_STR_POST_DEC_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
151 { ARM_INSN_STR_POST_INC_IMM_OFFSET, ARM_FRAG_STR_POST_INC_IMM_OFFSET_MID, ARM_FRAG_STR_POST_INC_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
152 { ARM_INSN_STR_POST_INC_REG_OFFSET, ARM_FRAG_STR_POST_DEC_REG_OFFSET_HDR, ARM_FRAG_STR_POST_INC_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
153 { ARM_INSN_STR_POST_DEC_NONPRIV_IMM_OFFSET, ARM_FRAG_STR_POST_DEC_NONPRIV_IMM_OFFSET_MID, ARM_FRAG_LIST_END },
154 { ARM_INSN_STR_POST_DEC_NONPRIV_REG_OFFSET, ARM_FRAG_STR_POST_DEC_REG_OFFSET_HDR, ARM_FRAG_STR_POST_DEC_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
155 { ARM_INSN_STR_POST_INC_NONPRIV_IMM_OFFSET, ARM_FRAG_STR_POST_INC_NONPRIV_IMM_OFFSET_MID, ARM_FRAG_LIST_END },
156 { ARM_INSN_STR_POST_INC_NONPRIV_REG_OFFSET, ARM_FRAG_STR_POST_DEC_REG_OFFSET_HDR, ARM_FRAG_STR_POST_INC_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
157 { ARM_INSN_STR_PRE_DEC_IMM_OFFSET, ARM_FRAG_STR_PRE_DEC_IMM_OFFSET_MID, ARM_FRAG_STR_PRE_DEC_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
158 { ARM_INSN_STR_PRE_DEC_REG_OFFSET, ARM_FRAG_STRB_POST_INC_NONPRIV_REG_OFFSET_HDR, ARM_FRAG_STR_PRE_DEC_REG_OFFSET_MID, ARM_FRAG_STR_PRE_DEC_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
159 { ARM_INSN_STR_PRE_INC_IMM_OFFSET, ARM_FRAG_STR_PRE_INC_IMM_OFFSET_MID, ARM_FRAG_STR_PRE_DEC_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
160 { ARM_INSN_STR_PRE_INC_REG_OFFSET, ARM_FRAG_STRB_POST_INC_NONPRIV_REG_OFFSET_HDR, ARM_FRAG_STR_PRE_INC_REG_OFFSET_MID, ARM_FRAG_STR_PRE_DEC_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
161 { ARM_INSN_STR_PRE_DEC_WB_IMM_OFFSET, ARM_FRAG_STR_PRE_DEC_WB_IMM_OFFSET_MID, ARM_FRAG_STR_PRE_DEC_WB_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
162 { ARM_INSN_STR_PRE_DEC_WB_REG_OFFSET, ARM_FRAG_STRB_POST_INC_NONPRIV_REG_OFFSET_HDR, ARM_FRAG_STR_PRE_DEC_WB_REG_OFFSET_MID, ARM_FRAG_STR_PRE_DEC_WB_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
163 { ARM_INSN_STR_PRE_INC_WB_IMM_OFFSET, ARM_FRAG_STR_PRE_INC_WB_IMM_OFFSET_MID, ARM_FRAG_STR_PRE_DEC_WB_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
164 { ARM_INSN_STR_PRE_INC_WB_REG_OFFSET, ARM_FRAG_STRB_POST_INC_NONPRIV_REG_OFFSET_HDR, ARM_FRAG_STR_PRE_INC_WB_REG_OFFSET_MID, ARM_FRAG_STR_PRE_DEC_WB_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
165 { ARM_INSN_STRB_POST_DEC_IMM_OFFSET, ARM_FRAG_STRB_POST_DEC_IMM_OFFSET_MID, ARM_FRAG_LIST_END },
166 { ARM_INSN_STRB_POST_DEC_REG_OFFSET, ARM_FRAG_STR_POST_DEC_REG_OFFSET_HDR, ARM_FRAG_STRB_POST_DEC_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
167 { ARM_INSN_STRB_POST_INC_IMM_OFFSET, ARM_FRAG_STRB_POST_DEC_NONPRIV_IMM_OFFSET_HDR, ARM_FRAG_STRB_POST_INC_IMM_OFFSET_MID, ARM_FRAG_LIST_END },
168 { ARM_INSN_STRB_POST_INC_REG_OFFSET, ARM_FRAG_STR_POST_DEC_REG_OFFSET_HDR, ARM_FRAG_STRB_POST_INC_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
169 { ARM_INSN_STRB_POST_DEC_NONPRIV_IMM_OFFSET, ARM_FRAG_STRB_POST_DEC_NONPRIV_IMM_OFFSET_HDR, ARM_FRAG_STRB_POST_DEC_NONPRIV_IMM_OFFSET_MID, ARM_FRAG_LIST_END },
170 { ARM_INSN_STRB_POST_DEC_NONPRIV_REG_OFFSET, ARM_FRAG_STR_POST_DEC_REG_OFFSET_HDR, ARM_FRAG_STRB_POST_DEC_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
171 { ARM_INSN_STRB_POST_INC_NONPRIV_IMM_OFFSET, ARM_FRAG_STRB_POST_INC_NONPRIV_IMM_OFFSET_MID, ARM_FRAG_LIST_END },
172 { ARM_INSN_STRB_POST_INC_NONPRIV_REG_OFFSET, ARM_FRAG_STRB_POST_INC_NONPRIV_REG_OFFSET_HDR, ARM_FRAG_STRB_POST_INC_NONPRIV_REG_OFFSET_MID, ARM_FRAG_STRB_POST_INC_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
173 { ARM_INSN_STRB_PRE_DEC_IMM_OFFSET, ARM_FRAG_STRB_PRE_DEC_IMM_OFFSET_MID, ARM_FRAG_STR_PRE_DEC_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
174 { ARM_INSN_STRB_PRE_DEC_REG_OFFSET, ARM_FRAG_STRB_POST_INC_NONPRIV_REG_OFFSET_HDR, ARM_FRAG_STRB_PRE_DEC_REG_OFFSET_MID, ARM_FRAG_STR_PRE_DEC_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
175 { ARM_INSN_STRB_PRE_INC_IMM_OFFSET, ARM_FRAG_STRB_PRE_INC_IMM_OFFSET_MID, ARM_FRAG_STR_PRE_DEC_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
176 { ARM_INSN_STRB_PRE_INC_REG_OFFSET, ARM_FRAG_STRB_PRE_INC_REG_OFFSET_MID, ARM_FRAG_STR_PRE_DEC_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
177 { ARM_INSN_STRB_PRE_DEC_WB_IMM_OFFSET, ARM_FRAG_STRB_PRE_DEC_WB_IMM_OFFSET_MID, ARM_FRAG_STR_PRE_DEC_WB_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
178 { ARM_INSN_STRB_PRE_DEC_WB_REG_OFFSET, ARM_FRAG_STRB_POST_INC_NONPRIV_REG_OFFSET_HDR, ARM_FRAG_STRB_PRE_DEC_WB_REG_OFFSET_MID, ARM_FRAG_STR_PRE_DEC_WB_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
179 { ARM_INSN_STRB_PRE_INC_WB_IMM_OFFSET, ARM_FRAG_STRB_PRE_INC_WB_IMM_OFFSET_MID, ARM_FRAG_STR_PRE_DEC_WB_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
180 { ARM_INSN_STRB_PRE_INC_WB_REG_OFFSET, ARM_FRAG_STRB_POST_INC_NONPRIV_REG_OFFSET_HDR, ARM_FRAG_STRB_PRE_INC_WB_REG_OFFSET_MID, ARM_FRAG_STR_PRE_DEC_WB_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
181 { ARM_INSN_STRH_PRE_DEC_IMM_OFFSET, ARM_FRAG_STRH_PRE_DEC_IMM_OFFSET_MID, ARM_FRAG_STRH_PRE_DEC_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
182 { ARM_INSN_STRH_PRE_DEC_REG_OFFSET, ARM_FRAG_STRH_PRE_DEC_REG_OFFSET_MID, ARM_FRAG_STR_PRE_DEC_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
183 { ARM_INSN_STRH_PRE_INC_IMM_OFFSET, ARM_FRAG_STRH_PRE_INC_IMM_OFFSET_MID, ARM_FRAG_STRH_PRE_DEC_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
184 { ARM_INSN_STRH_PRE_INC_REG_OFFSET, ARM_FRAG_STRH_PRE_INC_REG_OFFSET_MID, ARM_FRAG_STR_PRE_DEC_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
185 { ARM_INSN_STRH_PRE_DEC_WB_IMM_OFFSET, ARM_FRAG_STRH_PRE_DEC_WB_IMM_OFFSET_MID, ARM_FRAG_STRH_PRE_DEC_WB_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
186 { ARM_INSN_STRH_PRE_DEC_WB_REG_OFFSET, ARM_FRAG_STRH_PRE_DEC_WB_REG_OFFSET_MID, ARM_FRAG_STR_PRE_DEC_WB_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
187 { ARM_INSN_STRH_PRE_INC_WB_IMM_OFFSET, ARM_FRAG_STRH_PRE_INC_WB_IMM_OFFSET_MID, ARM_FRAG_STRH_PRE_DEC_WB_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
188 { ARM_INSN_STRH_PRE_INC_WB_REG_OFFSET, ARM_FRAG_STRH_PRE_INC_WB_REG_OFFSET_MID, ARM_FRAG_STR_PRE_DEC_WB_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
189 { ARM_INSN_STRH_POST_DEC_IMM_OFFSET, ARM_FRAG_STRH_POST_DEC_IMM_OFFSET_MID, ARM_FRAG_LIST_END },
190 { ARM_INSN_STRH_POST_DEC_REG_OFFSET, ARM_FRAG_STRH_POST_DEC_REG_OFFSET_MID, ARM_FRAG_LIST_END },
191 { ARM_INSN_STRH_POST_INC_IMM_OFFSET, ARM_FRAG_STRH_POST_INC_IMM_OFFSET_MID, ARM_FRAG_LIST_END },
192 { ARM_INSN_STRH_POST_INC_REG_OFFSET, ARM_FRAG_STRH_POST_INC_REG_OFFSET_MID, ARM_FRAG_LIST_END },
193 { ARM_INSN_LDRSB_PRE_DEC_IMM_OFFSET, ARM_FRAG_LDRSB_PRE_DEC_IMM_OFFSET_MID, ARM_FRAG_LDRSB_PRE_DEC_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
194 { ARM_INSN_LDRSB_PRE_DEC_REG_OFFSET, ARM_FRAG_LDRSB_PRE_DEC_REG_OFFSET_MID, ARM_FRAG_LDRB_PRE_DEC_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
195 { ARM_INSN_LDRSB_PRE_INC_IMM_OFFSET, ARM_FRAG_LDRSB_PRE_INC_IMM_OFFSET_MID, ARM_FRAG_LDRSB_PRE_DEC_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
196 { ARM_INSN_LDRSB_PRE_INC_REG_OFFSET, ARM_FRAG_LDRSB_PRE_INC_REG_OFFSET_MID, ARM_FRAG_LDRB_PRE_DEC_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
197 { ARM_INSN_LDRSB_PRE_DEC_WB_IMM_OFFSET, ARM_FRAG_LDRSB_PRE_DEC_WB_IMM_OFFSET_MID, ARM_FRAG_LDRSB_PRE_DEC_WB_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
198 { ARM_INSN_LDRSB_PRE_DEC_WB_REG_OFFSET, ARM_FRAG_LDRSB_PRE_DEC_WB_REG_OFFSET_MID, ARM_FRAG_LDRB_PRE_DEC_WB_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
199 { ARM_INSN_LDRSB_PRE_INC_WB_IMM_OFFSET, ARM_FRAG_LDRSB_PRE_INC_WB_IMM_OFFSET_MID, ARM_FRAG_LDRSB_PRE_DEC_WB_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
200 { ARM_INSN_LDRSB_PRE_INC_WB_REG_OFFSET, ARM_FRAG_LDRSB_PRE_INC_WB_REG_OFFSET_MID, ARM_FRAG_LDRB_PRE_DEC_WB_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
201 { ARM_INSN_LDRSB_POST_DEC_IMM_OFFSET, ARM_FRAG_LDRSB_POST_DEC_IMM_OFFSET_MID, ARM_FRAG_LIST_END },
202 { ARM_INSN_LDRSB_POST_DEC_REG_OFFSET, ARM_FRAG_LDRSB_POST_DEC_REG_OFFSET_MID, ARM_FRAG_LIST_END },
203 { ARM_INSN_LDRSB_POST_INC_IMM_OFFSET, ARM_FRAG_LDRSB_POST_INC_IMM_OFFSET_MID, ARM_FRAG_LIST_END },
204 { ARM_INSN_LDRSB_POST_INC_REG_OFFSET, ARM_FRAG_LDRSB_POST_INC_REG_OFFSET_MID, ARM_FRAG_LIST_END },
205 { ARM_INSN_LDRH_PRE_DEC_IMM_OFFSET, ARM_FRAG_LDRH_PRE_DEC_IMM_OFFSET_MID, ARM_FRAG_LDRSB_PRE_DEC_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
206 { ARM_INSN_LDRH_PRE_DEC_REG_OFFSET, ARM_FRAG_LDRH_PRE_DEC_REG_OFFSET_MID, ARM_FRAG_LDRB_PRE_DEC_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
207 { ARM_INSN_LDRH_PRE_INC_IMM_OFFSET, ARM_FRAG_LDRH_PRE_INC_IMM_OFFSET_MID, ARM_FRAG_LDRSB_PRE_DEC_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
208 { ARM_INSN_LDRH_PRE_INC_REG_OFFSET, ARM_FRAG_LDRH_PRE_INC_REG_OFFSET_MID, ARM_FRAG_LDRB_PRE_DEC_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
209 { ARM_INSN_LDRH_PRE_DEC_WB_IMM_OFFSET, ARM_FRAG_LDRH_PRE_DEC_WB_IMM_OFFSET_MID, ARM_FRAG_LDRSB_PRE_DEC_WB_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
210 { ARM_INSN_LDRH_PRE_DEC_WB_REG_OFFSET, ARM_FRAG_LDRH_PRE_DEC_WB_REG_OFFSET_MID, ARM_FRAG_LDRB_PRE_DEC_WB_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
211 { ARM_INSN_LDRH_PRE_INC_WB_IMM_OFFSET, ARM_FRAG_LDRH_PRE_INC_WB_IMM_OFFSET_MID, ARM_FRAG_LDRSB_PRE_DEC_WB_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
212 { ARM_INSN_LDRH_PRE_INC_WB_REG_OFFSET, ARM_FRAG_LDRH_PRE_INC_WB_REG_OFFSET_MID, ARM_FRAG_LDRB_PRE_DEC_WB_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
213 { ARM_INSN_LDRH_POST_DEC_IMM_OFFSET, ARM_FRAG_LDRH_POST_DEC_IMM_OFFSET_MID, ARM_FRAG_LIST_END },
214 { ARM_INSN_LDRH_POST_DEC_REG_OFFSET, ARM_FRAG_LDRH_POST_DEC_REG_OFFSET_MID, ARM_FRAG_LIST_END },
215 { ARM_INSN_LDRH_POST_INC_IMM_OFFSET, ARM_FRAG_LDRH_POST_INC_IMM_OFFSET_MID, ARM_FRAG_LIST_END },
216 { ARM_INSN_LDRH_POST_INC_REG_OFFSET, ARM_FRAG_LDRH_POST_INC_REG_OFFSET_MID, ARM_FRAG_LIST_END },
217 { ARM_INSN_LDRSH_PRE_DEC_IMM_OFFSET, ARM_FRAG_LDRSH_PRE_DEC_IMM_OFFSET_MID, ARM_FRAG_LDRSB_PRE_DEC_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
218 { ARM_INSN_LDRSH_PRE_DEC_REG_OFFSET, ARM_FRAG_LDRSH_PRE_DEC_REG_OFFSET_MID, ARM_FRAG_LDRB_PRE_DEC_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
219 { ARM_INSN_LDRSH_PRE_INC_IMM_OFFSET, ARM_FRAG_LDRSH_PRE_INC_IMM_OFFSET_MID, ARM_FRAG_LDRSB_PRE_DEC_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
220 { ARM_INSN_LDRSH_PRE_INC_REG_OFFSET, ARM_FRAG_LDRSH_PRE_INC_REG_OFFSET_MID, ARM_FRAG_LIST_END },
221 { ARM_INSN_LDRSH_PRE_DEC_WB_IMM_OFFSET, ARM_FRAG_LDRSH_PRE_DEC_WB_IMM_OFFSET_MID, ARM_FRAG_LDRSB_PRE_DEC_WB_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
222 { ARM_INSN_LDRSH_PRE_DEC_WB_REG_OFFSET, ARM_FRAG_LDRSH_PRE_DEC_WB_REG_OFFSET_MID, ARM_FRAG_LDRB_PRE_DEC_WB_REG_OFFSET_TRLR, ARM_FRAG_LIST_END },
223 { ARM_INSN_LDRSH_PRE_INC_WB_IMM_OFFSET, ARM_FRAG_LDRSH_PRE_INC_WB_IMM_OFFSET_MID, ARM_FRAG_LDRSB_PRE_DEC_WB_IMM_OFFSET_TRLR, ARM_FRAG_LIST_END },
224 { ARM_INSN_LDRSH_PRE_INC_WB_REG_OFFSET, ARM_FRAG_LDRSH_PRE_INC_WB_REG_OFFSET_MID, ARM_FRAG_LIST_END },
225 { ARM_INSN_LDRSH_POST_DEC_IMM_OFFSET, ARM_FRAG_LDRSH_POST_DEC_IMM_OFFSET_MID, ARM_FRAG_LIST_END },
226 { ARM_INSN_LDRSH_POST_DEC_REG_OFFSET, ARM_FRAG_LDRSH_POST_DEC_REG_OFFSET_MID, ARM_FRAG_LIST_END },
227 { ARM_INSN_LDRSH_POST_INC_IMM_OFFSET, ARM_FRAG_LDRSH_POST_INC_IMM_OFFSET_MID, ARM_FRAG_LIST_END },
228 { ARM_INSN_LDRSH_POST_INC_REG_OFFSET, ARM_FRAG_LDRSH_POST_INC_REG_OFFSET_MID, ARM_FRAG_LIST_END },
229 { ARM_INSN_MUL, ARM_FRAG_MUL_MID, ARM_FRAG_LIST_END },
230 { ARM_INSN_MLA, ARM_FRAG_MLA_MID, ARM_FRAG_LIST_END },
231 { ARM_INSN_UMULL, ARM_FRAG_UMULL_MID, ARM_FRAG_UMULL_TRLR, ARM_FRAG_LIST_END },
232 { ARM_INSN_UMLAL, ARM_FRAG_UMLAL_MID, ARM_FRAG_UMULL_TRLR, ARM_FRAG_LIST_END },
233 { ARM_INSN_SMULL, ARM_FRAG_SMULL_MID, ARM_FRAG_UMULL_TRLR, ARM_FRAG_LIST_END },
234 { ARM_INSN_SMLAL, ARM_FRAG_SMLAL_MID, ARM_FRAG_LIST_END },
235 { ARM_INSN_SWP, ARM_FRAG_SWP_MID, ARM_FRAG_LIST_END },
236 { ARM_INSN_SWPB, ARM_FRAG_SWPB_MID, ARM_FRAG_LIST_END },
237 { ARM_INSN_SWI, ARM_FRAG_SWI_MID, ARM_FRAG_LIST_END },
238 { ARM_INSN_AND_REG_IMM_SHIFT, ARM_FRAG_AND_REG_IMM_SHIFT_MID, ARM_FRAG_LIST_END },
239 { ARM_INSN_AND_REG_REG_SHIFT, ARM_FRAG_AND_REG_REG_SHIFT_MID, ARM_FRAG_AND_REG_REG_SHIFT_TRLR, ARM_FRAG_LIST_END },
240 { ARM_INSN_AND_IMM, ARM_FRAG_AND_IMM_MID, ARM_FRAG_AND_IMM_TRLR, ARM_FRAG_LIST_END },
241 { ARM_INSN_ORR_REG_IMM_SHIFT, ARM_FRAG_ORR_REG_IMM_SHIFT_HDR, ARM_FRAG_ORR_REG_IMM_SHIFT_MID, ARM_FRAG_ORR_REG_IMM_SHIFT_TRLR, ARM_FRAG_LIST_END },
242 { ARM_INSN_ORR_REG_REG_SHIFT, ARM_FRAG_ORR_REG_REG_SHIFT_HDR, ARM_FRAG_ORR_REG_REG_SHIFT_MID, ARM_FRAG_AND_REG_REG_SHIFT_TRLR, ARM_FRAG_LIST_END },
243 { ARM_INSN_ORR_IMM, ARM_FRAG_ORR_IMM_MID, ARM_FRAG_AND_IMM_TRLR, ARM_FRAG_LIST_END },
244 { ARM_INSN_EOR_REG_IMM_SHIFT, ARM_FRAG_ORR_REG_IMM_SHIFT_HDR, ARM_FRAG_EOR_REG_IMM_SHIFT_MID, ARM_FRAG_ORR_REG_IMM_SHIFT_TRLR, ARM_FRAG_LIST_END },
245 { ARM_INSN_EOR_REG_REG_SHIFT, ARM_FRAG_ORR_REG_REG_SHIFT_HDR, ARM_FRAG_EOR_REG_REG_SHIFT_MID, ARM_FRAG_AND_REG_REG_SHIFT_TRLR, ARM_FRAG_LIST_END },
246 { ARM_INSN_EOR_IMM, ARM_FRAG_EOR_IMM_MID, ARM_FRAG_AND_IMM_TRLR, ARM_FRAG_LIST_END },
247 { ARM_INSN_MOV_REG_IMM_SHIFT, ARM_FRAG_ORR_REG_IMM_SHIFT_HDR, ARM_FRAG_MOV_REG_IMM_SHIFT_MID, ARM_FRAG_ORR_REG_IMM_SHIFT_TRLR, ARM_FRAG_LIST_END },
248 { ARM_INSN_MOV_REG_REG_SHIFT, ARM_FRAG_ORR_REG_REG_SHIFT_HDR, ARM_FRAG_MOV_REG_REG_SHIFT_MID, ARM_FRAG_AND_REG_REG_SHIFT_TRLR, ARM_FRAG_LIST_END },
249 { ARM_INSN_MOV_IMM, ARM_FRAG_MOV_IMM_MID, ARM_FRAG_AND_IMM_TRLR, ARM_FRAG_LIST_END },
250 { ARM_INSN_BIC_REG_IMM_SHIFT, ARM_FRAG_ORR_REG_IMM_SHIFT_HDR, ARM_FRAG_BIC_REG_IMM_SHIFT_MID, ARM_FRAG_ORR_REG_IMM_SHIFT_TRLR, ARM_FRAG_LIST_END },
251 { ARM_INSN_BIC_REG_REG_SHIFT, ARM_FRAG_ORR_REG_REG_SHIFT_HDR, ARM_FRAG_BIC_REG_REG_SHIFT_MID, ARM_FRAG_AND_REG_REG_SHIFT_TRLR, ARM_FRAG_LIST_END },
252 { ARM_INSN_BIC_IMM, ARM_FRAG_BIC_IMM_MID, ARM_FRAG_AND_IMM_TRLR, ARM_FRAG_LIST_END },
253 { ARM_INSN_MVN_REG_IMM_SHIFT, ARM_FRAG_MVN_REG_IMM_SHIFT_HDR, ARM_FRAG_MVN_REG_IMM_SHIFT_MID, ARM_FRAG_ORR_REG_IMM_SHIFT_TRLR, ARM_FRAG_LIST_END },
254 { ARM_INSN_MVN_REG_REG_SHIFT, ARM_FRAG_MVN_REG_REG_SHIFT_HDR, ARM_FRAG_MVN_REG_REG_SHIFT_MID, ARM_FRAG_LIST_END },
255 { ARM_INSN_MVN_IMM, ARM_FRAG_MVN_IMM_MID, ARM_FRAG_LIST_END },
256 { ARM_INSN_ADD_REG_IMM_SHIFT, ARM_FRAG_MVN_REG_IMM_SHIFT_HDR, ARM_FRAG_ADD_REG_IMM_SHIFT_MID, ARM_FRAG_LIST_END },
257 { ARM_INSN_ADD_REG_REG_SHIFT, ARM_FRAG_MVN_REG_REG_SHIFT_HDR, ARM_FRAG_ADD_REG_REG_SHIFT_MID, ARM_FRAG_LIST_END },
258 { ARM_INSN_ADD_IMM, ARM_FRAG_ADD_IMM_MID, ARM_FRAG_LIST_END },
259 { ARM_INSN_ADC_REG_IMM_SHIFT, ARM_FRAG_MVN_REG_IMM_SHIFT_HDR, ARM_FRAG_ADC_REG_IMM_SHIFT_MID, ARM_FRAG_LIST_END },
260 { ARM_INSN_ADC_REG_REG_SHIFT, ARM_FRAG_MVN_REG_REG_SHIFT_HDR, ARM_FRAG_ADC_REG_REG_SHIFT_MID, ARM_FRAG_LIST_END },
261 { ARM_INSN_ADC_IMM, ARM_FRAG_ADC_IMM_MID, ARM_FRAG_LIST_END },
262 { ARM_INSN_SUB_REG_IMM_SHIFT, ARM_FRAG_MVN_REG_IMM_SHIFT_HDR, ARM_FRAG_SUB_REG_IMM_SHIFT_MID, ARM_FRAG_LIST_END },
263 { ARM_INSN_SUB_REG_REG_SHIFT, ARM_FRAG_MVN_REG_REG_SHIFT_HDR, ARM_FRAG_SUB_REG_REG_SHIFT_MID, ARM_FRAG_LIST_END },
264 { ARM_INSN_SUB_IMM, ARM_FRAG_SUB_IMM_MID, ARM_FRAG_LIST_END },
265 { ARM_INSN_SBC_REG_IMM_SHIFT, ARM_FRAG_MVN_REG_IMM_SHIFT_HDR, ARM_FRAG_SBC_REG_IMM_SHIFT_MID, ARM_FRAG_LIST_END },
266 { ARM_INSN_SBC_REG_REG_SHIFT, ARM_FRAG_MVN_REG_REG_SHIFT_HDR, ARM_FRAG_SBC_REG_REG_SHIFT_MID, ARM_FRAG_LIST_END },
267 { ARM_INSN_SBC_IMM, ARM_FRAG_SBC_IMM_MID, ARM_FRAG_LIST_END },
268 { ARM_INSN_RSB_REG_IMM_SHIFT, ARM_FRAG_MVN_REG_IMM_SHIFT_HDR, ARM_FRAG_RSB_REG_IMM_SHIFT_MID, ARM_FRAG_LIST_END },
269 { ARM_INSN_RSB_REG_REG_SHIFT, ARM_FRAG_MVN_REG_REG_SHIFT_HDR, ARM_FRAG_RSB_REG_REG_SHIFT_MID, ARM_FRAG_LIST_END },
270 { ARM_INSN_RSB_IMM, ARM_FRAG_RSB_IMM_MID, ARM_FRAG_LIST_END },
271 { ARM_INSN_RSC_REG_IMM_SHIFT, ARM_FRAG_MVN_REG_IMM_SHIFT_HDR, ARM_FRAG_RSC_REG_IMM_SHIFT_MID, ARM_FRAG_LIST_END },
272 { ARM_INSN_RSC_REG_REG_SHIFT, ARM_FRAG_MVN_REG_REG_SHIFT_HDR, ARM_FRAG_RSC_REG_REG_SHIFT_MID, ARM_FRAG_LIST_END },
273 { ARM_INSN_RSC_IMM, ARM_FRAG_RSC_IMM_MID, ARM_FRAG_LIST_END },
274 { ARM_INSN_TST_REG_IMM_SHIFT, ARM_FRAG_TST_REG_IMM_SHIFT_HDR, ARM_FRAG_TST_REG_IMM_SHIFT_MID, ARM_FRAG_LIST_END },
275 { ARM_INSN_TST_REG_REG_SHIFT, ARM_FRAG_TST_REG_REG_SHIFT_HDR, ARM_FRAG_TST_REG_REG_SHIFT_MID, ARM_FRAG_TST_REG_REG_SHIFT_TRLR, ARM_FRAG_LIST_END },
276 { ARM_INSN_TST_IMM, ARM_FRAG_TST_IMM_MID, ARM_FRAG_LIST_END },
277 { ARM_INSN_TEQ_REG_IMM_SHIFT, ARM_FRAG_TST_REG_IMM_SHIFT_HDR, ARM_FRAG_TEQ_REG_IMM_SHIFT_MID, ARM_FRAG_TEQ_REG_IMM_SHIFT_TRLR, ARM_FRAG_LIST_END },
278 { ARM_INSN_TEQ_REG_REG_SHIFT, ARM_FRAG_TST_REG_REG_SHIFT_HDR, ARM_FRAG_TEQ_REG_REG_SHIFT_MID, ARM_FRAG_LIST_END },
279 { ARM_INSN_TEQ_IMM, ARM_FRAG_TEQ_IMM_MID, ARM_FRAG_LIST_END },
280 { ARM_INSN_CMP_REG_IMM_SHIFT, ARM_FRAG_CMP_REG_IMM_SHIFT_HDR, ARM_FRAG_CMP_REG_IMM_SHIFT_MID, ARM_FRAG_LIST_END },
281 { ARM_INSN_CMP_REG_REG_SHIFT, ARM_FRAG_CMP_REG_REG_SHIFT_HDR, ARM_FRAG_CMP_REG_REG_SHIFT_MID, ARM_FRAG_LIST_END },
282 { ARM_INSN_CMP_IMM, ARM_FRAG_CMP_IMM_MID, ARM_FRAG_LIST_END },
283 { ARM_INSN_CMN_REG_IMM_SHIFT, ARM_FRAG_CMN_REG_IMM_SHIFT_MID, ARM_FRAG_LIST_END },
284 { ARM_INSN_CMN_REG_REG_SHIFT, ARM_FRAG_CMN_REG_REG_SHIFT_MID, ARM_FRAG_LIST_END },
285 { ARM_INSN_CMN_IMM, ARM_FRAG_CMN_IMM_MID, ARM_FRAG_LIST_END },
286 { ARM_INSN_LDMDA, ARM_FRAG_LDMDA_MID, ARM_FRAG_LIST_END },
287 { ARM_INSN_LDMDA_SW, ARM_FRAG_LDMDA_SW_MID, ARM_FRAG_LIST_END },
288 { ARM_INSN_LDMDA_WB, ARM_FRAG_LDMDA_WB_MID, ARM_FRAG_LIST_END },
289 { ARM_INSN_LDMDA_SW_WB, ARM_FRAG_LDMDA_SW_WB_MID, ARM_FRAG_LIST_END },
290 { ARM_INSN_LDMIB, ARM_FRAG_LDMIB_MID, ARM_FRAG_LIST_END },
291 { ARM_INSN_LDMIB_SW, ARM_FRAG_LDMIB_WB_HDR, ARM_FRAG_LDMIB_SW_MID, ARM_FRAG_LIST_END },
292 { ARM_INSN_LDMIB_WB, ARM_FRAG_LDMIB_WB_HDR, ARM_FRAG_LDMIB_WB_MID, ARM_FRAG_LIST_END },
293 { ARM_INSN_LDMIB_SW_WB, ARM_FRAG_LDMIB_SW_WB_MID, ARM_FRAG_LIST_END },
294 { ARM_INSN_LDMIA, ARM_FRAG_LDMIA_MID, ARM_FRAG_LIST_END },
295 { ARM_INSN_LDMIA_SW, ARM_FRAG_LDMIA_WB_HDR, ARM_FRAG_LDMIA_SW_MID, ARM_FRAG_LIST_END },
296 { ARM_INSN_LDMIA_WB, ARM_FRAG_LDMIA_WB_HDR, ARM_FRAG_LDMIA_WB_MID, ARM_FRAG_LIST_END },
297 { ARM_INSN_LDMIA_SW_WB, ARM_FRAG_LDMIA_SW_WB_MID, ARM_FRAG_LIST_END },
298 { ARM_INSN_LDMDB, ARM_FRAG_LDMDB_MID, ARM_FRAG_LIST_END },
299 { ARM_INSN_LDMDB_SW, ARM_FRAG_LDMDB_SW_MID, ARM_FRAG_LIST_END },
300 { ARM_INSN_LDMDB_WB, ARM_FRAG_LDMDB_WB_MID, ARM_FRAG_LIST_END },
301 { ARM_INSN_LDMDB_SW_WB, ARM_FRAG_LDMDB_SW_WB_MID, ARM_FRAG_LIST_END },
302 { ARM_INSN_STMDB, ARM_FRAG_STMDB_MID, ARM_FRAG_LIST_END },
303 { ARM_INSN_STMDB_SW, ARM_FRAG_STMDB_WB_HDR, ARM_FRAG_STMDB_SW_MID, ARM_FRAG_LIST_END },
304 { ARM_INSN_STMDB_WB, ARM_FRAG_STMDB_WB_HDR, ARM_FRAG_STMDB_WB_MID, ARM_FRAG_LIST_END },
305 { ARM_INSN_STMDB_SW_WB, ARM_FRAG_STMDB_SW_WB_MID, ARM_FRAG_LIST_END },
306 { ARM_INSN_STMIB, ARM_FRAG_STMIB_MID, ARM_FRAG_LIST_END },
307 { ARM_INSN_STMIB_SW, ARM_FRAG_STMIB_WB_HDR, ARM_FRAG_STMIB_SW_MID, ARM_FRAG_LIST_END },
308 { ARM_INSN_STMIB_WB, ARM_FRAG_STMIB_WB_HDR, ARM_FRAG_STMIB_WB_MID, ARM_FRAG_LIST_END },
309 { ARM_INSN_STMIB_SW_WB, ARM_FRAG_STMIB_SW_WB_MID, ARM_FRAG_LIST_END },
310 { ARM_INSN_STMIA, ARM_FRAG_STMIA_MID, ARM_FRAG_LIST_END },
311 { ARM_INSN_STMIA_SW, ARM_FRAG_STMIA_WB_HDR, ARM_FRAG_STMIA_SW_MID, ARM_FRAG_LIST_END },
312 { ARM_INSN_STMIA_WB, ARM_FRAG_STMIA_WB_HDR, ARM_FRAG_STMIA_WB_MID, ARM_FRAG_LIST_END },
313 { ARM_INSN_STMIA_SW_WB, ARM_FRAG_STMIA_SW_WB_MID, ARM_FRAG_LIST_END },
314 { ARM_INSN_STMDA, ARM_FRAG_STMDA_MID, ARM_FRAG_LIST_END },
315 { ARM_INSN_STMDA_SW, ARM_FRAG_STMDA_WB_HDR, ARM_FRAG_STMDA_SW_MID, ARM_FRAG_LIST_END },
316 { ARM_INSN_STMDA_WB, ARM_FRAG_STMDA_WB_HDR, ARM_FRAG_STMDA_WB_MID, ARM_FRAG_LIST_END },
317 { ARM_INSN_STMDA_SW_WB, ARM_FRAG_STMDA_SW_WB_MID, ARM_FRAG_LIST_END },
318 { ARM_INSN_MRS_C, ARM_FRAG_MRS_C_MID, ARM_FRAG_LIST_END },
319 { ARM_INSN_MRS_S, ARM_FRAG_MRS_S_MID, ARM_FRAG_LIST_END },
320 { ARM_INSN_MSR_C, ARM_FRAG_MSR_C_MID, ARM_FRAG_LIST_END },
321 { ARM_INSN_MSR_S, ARM_FRAG_MSR_S_MID, ARM_FRAG_LIST_END },
325 arm7f_cpu::arm_pbb_run ()
327 arm7f_cpu* current_cpu = this;
333 ARM_FRAG_TYPE* fragpc;
338 static const arm_pbb_label labels[] =
340 { ARM_FRAG_LIST_END, 0 },
341 { ARM_FRAG_MVN_REG_REG_SHIFT_HDR, && case_FRAG_MVN_REG_REG_SHIFT_HDR },
342 { ARM_FRAG_CMP_REG_REG_SHIFT_HDR, && case_FRAG_CMP_REG_REG_SHIFT_HDR },
343 { ARM_FRAG_TST_REG_REG_SHIFT_HDR, && case_FRAG_TST_REG_REG_SHIFT_HDR },
344 { ARM_FRAG_ORR_REG_REG_SHIFT_HDR, && case_FRAG_ORR_REG_REG_SHIFT_HDR },
345 { ARM_FRAG_MVN_REG_IMM_SHIFT_HDR, && case_FRAG_MVN_REG_IMM_SHIFT_HDR },
346 { ARM_FRAG_CMP_REG_IMM_SHIFT_HDR, && case_FRAG_CMP_REG_IMM_SHIFT_HDR },
347 { ARM_FRAG_TST_REG_IMM_SHIFT_HDR, && case_FRAG_TST_REG_IMM_SHIFT_HDR },
348 { ARM_FRAG_ORR_REG_IMM_SHIFT_HDR, && case_FRAG_ORR_REG_IMM_SHIFT_HDR },
349 { ARM_FRAG_STRB_POST_INC_NONPRIV_REG_OFFSET_HDR, && case_FRAG_STRB_POST_INC_NONPRIV_REG_OFFSET_HDR },
350 { ARM_FRAG_LDR_PRE_DEC_WB_REG_OFFSET_HDR, && case_FRAG_LDR_PRE_DEC_WB_REG_OFFSET_HDR },
351 { ARM_FRAG_LDR_POST_INC_NONPRIV_REG_OFFSET_HDR, && case_FRAG_LDR_POST_INC_NONPRIV_REG_OFFSET_HDR },
352 { ARM_FRAG_STR_POST_DEC_REG_OFFSET_HDR, && case_FRAG_STR_POST_DEC_REG_OFFSET_HDR },
353 { ARM_FRAG_LDR_POST_DEC_NONPRIV_REG_OFFSET_HDR, && case_FRAG_LDR_POST_DEC_NONPRIV_REG_OFFSET_HDR },
354 { ARM_FRAG_STMDA_WB_HDR, && case_FRAG_STMDA_WB_HDR },
355 { ARM_FRAG_STMIA_WB_HDR, && case_FRAG_STMIA_WB_HDR },
356 { ARM_FRAG_STMIB_WB_HDR, && case_FRAG_STMIB_WB_HDR },
357 { ARM_FRAG_STMDB_WB_HDR, && case_FRAG_STMDB_WB_HDR },
358 { ARM_FRAG_LDMIA_WB_HDR, && case_FRAG_LDMIA_WB_HDR },
359 { ARM_FRAG_LDMIB_WB_HDR, && case_FRAG_LDMIB_WB_HDR },
360 { ARM_FRAG_STRB_POST_DEC_NONPRIV_IMM_OFFSET_HDR, && case_FRAG_STRB_POST_DEC_NONPRIV_IMM_OFFSET_HDR },
361 { ARM_FRAG_LDRB_POST_DEC_NONPRIV_IMM_OFFSET_HDR, && case_FRAG_LDRB_POST_DEC_NONPRIV_IMM_OFFSET_HDR },
362 { ARM_FRAG_LDR_POST_DEC_NONPRIV_IMM_OFFSET_HDR, && case_FRAG_LDR_POST_DEC_NONPRIV_IMM_OFFSET_HDR },
363 { ARM_FRAG_X_HEADER, && case_FRAG_X_HEADER },
364 { ARM_FRAG_TST_REG_REG_SHIFT_TRLR, && case_FRAG_TST_REG_REG_SHIFT_TRLR },
365 { ARM_FRAG_TEQ_REG_IMM_SHIFT_TRLR, && case_FRAG_TEQ_REG_IMM_SHIFT_TRLR },
366 { ARM_FRAG_AND_IMM_TRLR, && case_FRAG_AND_IMM_TRLR },
367 { ARM_FRAG_AND_REG_REG_SHIFT_TRLR, && case_FRAG_AND_REG_REG_SHIFT_TRLR },
368 { ARM_FRAG_ORR_REG_IMM_SHIFT_TRLR, && case_FRAG_ORR_REG_IMM_SHIFT_TRLR },
369 { ARM_FRAG_UMULL_TRLR, && case_FRAG_UMULL_TRLR },
370 { ARM_FRAG_LDR_PRE_INC_IMM_OFFSET_TRLR, && case_FRAG_LDR_PRE_INC_IMM_OFFSET_TRLR },
371 { ARM_FRAG_LDRB_PRE_DEC_REG_OFFSET_TRLR, && case_FRAG_LDRB_PRE_DEC_REG_OFFSET_TRLR },
372 { ARM_FRAG_STR_PRE_DEC_REG_OFFSET_TRLR, && case_FRAG_STR_PRE_DEC_REG_OFFSET_TRLR },
373 { ARM_FRAG_STR_PRE_DEC_IMM_OFFSET_TRLR, && case_FRAG_STR_PRE_DEC_IMM_OFFSET_TRLR },
374 { ARM_FRAG_STRH_PRE_DEC_IMM_OFFSET_TRLR, && case_FRAG_STRH_PRE_DEC_IMM_OFFSET_TRLR },
375 { ARM_FRAG_LDRSB_PRE_DEC_IMM_OFFSET_TRLR, && case_FRAG_LDRSB_PRE_DEC_IMM_OFFSET_TRLR },
376 { ARM_FRAG_LDR_PRE_DEC_IMM_OFFSET_TRLR, && case_FRAG_LDR_PRE_DEC_IMM_OFFSET_TRLR },
377 { ARM_FRAG_LDR_PRE_INC_REG_OFFSET_TRLR, && case_FRAG_LDR_PRE_INC_REG_OFFSET_TRLR },
378 { ARM_FRAG_LDR_PRE_INC_WB_IMM_OFFSET_TRLR, && case_FRAG_LDR_PRE_INC_WB_IMM_OFFSET_TRLR },
379 { ARM_FRAG_LDRB_PRE_DEC_WB_REG_OFFSET_TRLR, && case_FRAG_LDRB_PRE_DEC_WB_REG_OFFSET_TRLR },
380 { ARM_FRAG_STR_PRE_DEC_WB_REG_OFFSET_TRLR, && case_FRAG_STR_PRE_DEC_WB_REG_OFFSET_TRLR },
381 { ARM_FRAG_STR_PRE_DEC_WB_IMM_OFFSET_TRLR, && case_FRAG_STR_PRE_DEC_WB_IMM_OFFSET_TRLR },
382 { ARM_FRAG_STRH_PRE_DEC_WB_IMM_OFFSET_TRLR, && case_FRAG_STRH_PRE_DEC_WB_IMM_OFFSET_TRLR },
383 { ARM_FRAG_LDRSB_PRE_DEC_WB_IMM_OFFSET_TRLR, && case_FRAG_LDRSB_PRE_DEC_WB_IMM_OFFSET_TRLR },
384 { ARM_FRAG_LDR_PRE_DEC_WB_IMM_OFFSET_TRLR, && case_FRAG_LDR_PRE_DEC_WB_IMM_OFFSET_TRLR },
385 { ARM_FRAG_LDR_PRE_INC_WB_REG_OFFSET_TRLR, && case_FRAG_LDR_PRE_INC_WB_REG_OFFSET_TRLR },
386 { ARM_FRAG_STRB_POST_INC_REG_OFFSET_TRLR, && case_FRAG_STRB_POST_INC_REG_OFFSET_TRLR },
387 { ARM_FRAG_STR_POST_INC_REG_OFFSET_TRLR, && case_FRAG_STR_POST_INC_REG_OFFSET_TRLR },
388 { ARM_FRAG_STR_POST_INC_IMM_OFFSET_TRLR, && case_FRAG_STR_POST_INC_IMM_OFFSET_TRLR },
389 { ARM_FRAG_LDRB_POST_INC_REG_OFFSET_TRLR, && case_FRAG_LDRB_POST_INC_REG_OFFSET_TRLR },
390 { ARM_FRAG_STRB_POST_DEC_REG_OFFSET_TRLR, && case_FRAG_STRB_POST_DEC_REG_OFFSET_TRLR },
391 { ARM_FRAG_STR_POST_DEC_REG_OFFSET_TRLR, && case_FRAG_STR_POST_DEC_REG_OFFSET_TRLR },
392 { ARM_FRAG_STR_POST_DEC_IMM_OFFSET_TRLR, && case_FRAG_STR_POST_DEC_IMM_OFFSET_TRLR },
393 { ARM_FRAG_LDRB_POST_DEC_REG_OFFSET_TRLR, && case_FRAG_LDRB_POST_DEC_REG_OFFSET_TRLR },
394 { ARM_FRAG_X_TRAILER, && case_FRAG_X_TRAILER },
395 { ARM_FRAG_X_COND_MID, && case_FRAG_X_COND_MID },
396 { ARM_FRAG_X_AFTER_MID, && case_FRAG_X_AFTER_MID },
397 { ARM_FRAG_X_BEFORE_MID, && case_FRAG_X_BEFORE_MID },
398 { ARM_FRAG_X_CTI_CHAIN_MID, && case_FRAG_X_CTI_CHAIN_MID },
399 { ARM_FRAG_X_CHAIN_MID, && case_FRAG_X_CHAIN_MID },
400 { ARM_FRAG_X_BEGIN_MID, && case_FRAG_X_BEGIN_MID },
401 { ARM_FRAG_X_INVALID_MID, && case_FRAG_X_INVALID_MID },
402 { ARM_FRAG_B_MID, && case_FRAG_B_MID },
403 { ARM_FRAG_BL_MID, && case_FRAG_BL_MID },
404 { ARM_FRAG_BX_MID, && case_FRAG_BX_MID },
405 { ARM_FRAG_LDR_POST_DEC_IMM_OFFSET_MID, && case_FRAG_LDR_POST_DEC_IMM_OFFSET_MID },
406 { ARM_FRAG_LDR_POST_DEC_REG_OFFSET_MID, && case_FRAG_LDR_POST_DEC_REG_OFFSET_MID },
407 { ARM_FRAG_LDR_POST_INC_IMM_OFFSET_MID, && case_FRAG_LDR_POST_INC_IMM_OFFSET_MID },
408 { ARM_FRAG_LDR_POST_INC_REG_OFFSET_MID, && case_FRAG_LDR_POST_INC_REG_OFFSET_MID },
409 { ARM_FRAG_LDR_POST_DEC_NONPRIV_IMM_OFFSET_MID, && case_FRAG_LDR_POST_DEC_NONPRIV_IMM_OFFSET_MID },
410 { ARM_FRAG_LDR_POST_DEC_NONPRIV_REG_OFFSET_MID, && case_FRAG_LDR_POST_DEC_NONPRIV_REG_OFFSET_MID },
411 { ARM_FRAG_LDR_POST_INC_NONPRIV_IMM_OFFSET_MID, && case_FRAG_LDR_POST_INC_NONPRIV_IMM_OFFSET_MID },
412 { ARM_FRAG_LDR_POST_INC_NONPRIV_REG_OFFSET_MID, && case_FRAG_LDR_POST_INC_NONPRIV_REG_OFFSET_MID },
413 { ARM_FRAG_LDR_PRE_DEC_IMM_OFFSET_MID, && case_FRAG_LDR_PRE_DEC_IMM_OFFSET_MID },
414 { ARM_FRAG_LDR_PRE_DEC_REG_OFFSET_MID, && case_FRAG_LDR_PRE_DEC_REG_OFFSET_MID },
415 { ARM_FRAG_LDR_PRE_INC_IMM_OFFSET_MID, && case_FRAG_LDR_PRE_INC_IMM_OFFSET_MID },
416 { ARM_FRAG_LDR_PRE_INC_REG_OFFSET_MID, && case_FRAG_LDR_PRE_INC_REG_OFFSET_MID },
417 { ARM_FRAG_LDR_PRE_DEC_WB_IMM_OFFSET_MID, && case_FRAG_LDR_PRE_DEC_WB_IMM_OFFSET_MID },
418 { ARM_FRAG_LDR_PRE_DEC_WB_REG_OFFSET_MID, && case_FRAG_LDR_PRE_DEC_WB_REG_OFFSET_MID },
419 { ARM_FRAG_LDR_PRE_INC_WB_IMM_OFFSET_MID, && case_FRAG_LDR_PRE_INC_WB_IMM_OFFSET_MID },
420 { ARM_FRAG_LDR_PRE_INC_WB_REG_OFFSET_MID, && case_FRAG_LDR_PRE_INC_WB_REG_OFFSET_MID },
421 { ARM_FRAG_LDRB_POST_DEC_IMM_OFFSET_MID, && case_FRAG_LDRB_POST_DEC_IMM_OFFSET_MID },
422 { ARM_FRAG_LDRB_POST_INC_IMM_OFFSET_MID, && case_FRAG_LDRB_POST_INC_IMM_OFFSET_MID },
423 { ARM_FRAG_LDRB_POST_DEC_NONPRIV_IMM_OFFSET_MID, && case_FRAG_LDRB_POST_DEC_NONPRIV_IMM_OFFSET_MID },
424 { ARM_FRAG_LDRB_POST_INC_NONPRIV_IMM_OFFSET_MID, && case_FRAG_LDRB_POST_INC_NONPRIV_IMM_OFFSET_MID },
425 { ARM_FRAG_LDRB_PRE_DEC_IMM_OFFSET_MID, && case_FRAG_LDRB_PRE_DEC_IMM_OFFSET_MID },
426 { ARM_FRAG_LDRB_PRE_DEC_REG_OFFSET_MID, && case_FRAG_LDRB_PRE_DEC_REG_OFFSET_MID },
427 { ARM_FRAG_LDRB_PRE_INC_IMM_OFFSET_MID, && case_FRAG_LDRB_PRE_INC_IMM_OFFSET_MID },
428 { ARM_FRAG_LDRB_PRE_INC_REG_OFFSET_MID, && case_FRAG_LDRB_PRE_INC_REG_OFFSET_MID },
429 { ARM_FRAG_LDRB_PRE_DEC_WB_IMM_OFFSET_MID, && case_FRAG_LDRB_PRE_DEC_WB_IMM_OFFSET_MID },
430 { ARM_FRAG_LDRB_PRE_DEC_WB_REG_OFFSET_MID, && case_FRAG_LDRB_PRE_DEC_WB_REG_OFFSET_MID },
431 { ARM_FRAG_LDRB_PRE_INC_WB_IMM_OFFSET_MID, && case_FRAG_LDRB_PRE_INC_WB_IMM_OFFSET_MID },
432 { ARM_FRAG_LDRB_PRE_INC_WB_REG_OFFSET_MID, && case_FRAG_LDRB_PRE_INC_WB_REG_OFFSET_MID },
433 { ARM_FRAG_STR_POST_DEC_IMM_OFFSET_MID, && case_FRAG_STR_POST_DEC_IMM_OFFSET_MID },
434 { ARM_FRAG_STR_POST_INC_IMM_OFFSET_MID, && case_FRAG_STR_POST_INC_IMM_OFFSET_MID },
435 { ARM_FRAG_STR_POST_DEC_NONPRIV_IMM_OFFSET_MID, && case_FRAG_STR_POST_DEC_NONPRIV_IMM_OFFSET_MID },
436 { ARM_FRAG_STR_POST_INC_NONPRIV_IMM_OFFSET_MID, && case_FRAG_STR_POST_INC_NONPRIV_IMM_OFFSET_MID },
437 { ARM_FRAG_STR_PRE_DEC_IMM_OFFSET_MID, && case_FRAG_STR_PRE_DEC_IMM_OFFSET_MID },
438 { ARM_FRAG_STR_PRE_DEC_REG_OFFSET_MID, && case_FRAG_STR_PRE_DEC_REG_OFFSET_MID },
439 { ARM_FRAG_STR_PRE_INC_IMM_OFFSET_MID, && case_FRAG_STR_PRE_INC_IMM_OFFSET_MID },
440 { ARM_FRAG_STR_PRE_INC_REG_OFFSET_MID, && case_FRAG_STR_PRE_INC_REG_OFFSET_MID },
441 { ARM_FRAG_STR_PRE_DEC_WB_IMM_OFFSET_MID, && case_FRAG_STR_PRE_DEC_WB_IMM_OFFSET_MID },
442 { ARM_FRAG_STR_PRE_DEC_WB_REG_OFFSET_MID, && case_FRAG_STR_PRE_DEC_WB_REG_OFFSET_MID },
443 { ARM_FRAG_STR_PRE_INC_WB_IMM_OFFSET_MID, && case_FRAG_STR_PRE_INC_WB_IMM_OFFSET_MID },
444 { ARM_FRAG_STR_PRE_INC_WB_REG_OFFSET_MID, && case_FRAG_STR_PRE_INC_WB_REG_OFFSET_MID },
445 { ARM_FRAG_STRB_POST_DEC_IMM_OFFSET_MID, && case_FRAG_STRB_POST_DEC_IMM_OFFSET_MID },
446 { ARM_FRAG_STRB_POST_INC_IMM_OFFSET_MID, && case_FRAG_STRB_POST_INC_IMM_OFFSET_MID },
447 { ARM_FRAG_STRB_POST_DEC_NONPRIV_IMM_OFFSET_MID, && case_FRAG_STRB_POST_DEC_NONPRIV_IMM_OFFSET_MID },
448 { ARM_FRAG_STRB_POST_INC_NONPRIV_IMM_OFFSET_MID, && case_FRAG_STRB_POST_INC_NONPRIV_IMM_OFFSET_MID },
449 { ARM_FRAG_STRB_POST_INC_NONPRIV_REG_OFFSET_MID, && case_FRAG_STRB_POST_INC_NONPRIV_REG_OFFSET_MID },
450 { ARM_FRAG_STRB_PRE_DEC_IMM_OFFSET_MID, && case_FRAG_STRB_PRE_DEC_IMM_OFFSET_MID },
451 { ARM_FRAG_STRB_PRE_DEC_REG_OFFSET_MID, && case_FRAG_STRB_PRE_DEC_REG_OFFSET_MID },
452 { ARM_FRAG_STRB_PRE_INC_IMM_OFFSET_MID, && case_FRAG_STRB_PRE_INC_IMM_OFFSET_MID },
453 { ARM_FRAG_STRB_PRE_INC_REG_OFFSET_MID, && case_FRAG_STRB_PRE_INC_REG_OFFSET_MID },
454 { ARM_FRAG_STRB_PRE_DEC_WB_IMM_OFFSET_MID, && case_FRAG_STRB_PRE_DEC_WB_IMM_OFFSET_MID },
455 { ARM_FRAG_STRB_PRE_DEC_WB_REG_OFFSET_MID, && case_FRAG_STRB_PRE_DEC_WB_REG_OFFSET_MID },
456 { ARM_FRAG_STRB_PRE_INC_WB_IMM_OFFSET_MID, && case_FRAG_STRB_PRE_INC_WB_IMM_OFFSET_MID },
457 { ARM_FRAG_STRB_PRE_INC_WB_REG_OFFSET_MID, && case_FRAG_STRB_PRE_INC_WB_REG_OFFSET_MID },
458 { ARM_FRAG_STRH_PRE_DEC_IMM_OFFSET_MID, && case_FRAG_STRH_PRE_DEC_IMM_OFFSET_MID },
459 { ARM_FRAG_STRH_PRE_DEC_REG_OFFSET_MID, && case_FRAG_STRH_PRE_DEC_REG_OFFSET_MID },
460 { ARM_FRAG_STRH_PRE_INC_IMM_OFFSET_MID, && case_FRAG_STRH_PRE_INC_IMM_OFFSET_MID },
461 { ARM_FRAG_STRH_PRE_INC_REG_OFFSET_MID, && case_FRAG_STRH_PRE_INC_REG_OFFSET_MID },
462 { ARM_FRAG_STRH_PRE_DEC_WB_IMM_OFFSET_MID, && case_FRAG_STRH_PRE_DEC_WB_IMM_OFFSET_MID },
463 { ARM_FRAG_STRH_PRE_DEC_WB_REG_OFFSET_MID, && case_FRAG_STRH_PRE_DEC_WB_REG_OFFSET_MID },
464 { ARM_FRAG_STRH_PRE_INC_WB_IMM_OFFSET_MID, && case_FRAG_STRH_PRE_INC_WB_IMM_OFFSET_MID },
465 { ARM_FRAG_STRH_PRE_INC_WB_REG_OFFSET_MID, && case_FRAG_STRH_PRE_INC_WB_REG_OFFSET_MID },
466 { ARM_FRAG_STRH_POST_DEC_IMM_OFFSET_MID, && case_FRAG_STRH_POST_DEC_IMM_OFFSET_MID },
467 { ARM_FRAG_STRH_POST_DEC_REG_OFFSET_MID, && case_FRAG_STRH_POST_DEC_REG_OFFSET_MID },
468 { ARM_FRAG_STRH_POST_INC_IMM_OFFSET_MID, && case_FRAG_STRH_POST_INC_IMM_OFFSET_MID },
469 { ARM_FRAG_STRH_POST_INC_REG_OFFSET_MID, && case_FRAG_STRH_POST_INC_REG_OFFSET_MID },
470 { ARM_FRAG_LDRSB_PRE_DEC_IMM_OFFSET_MID, && case_FRAG_LDRSB_PRE_DEC_IMM_OFFSET_MID },
471 { ARM_FRAG_LDRSB_PRE_DEC_REG_OFFSET_MID, && case_FRAG_LDRSB_PRE_DEC_REG_OFFSET_MID },
472 { ARM_FRAG_LDRSB_PRE_INC_IMM_OFFSET_MID, && case_FRAG_LDRSB_PRE_INC_IMM_OFFSET_MID },
473 { ARM_FRAG_LDRSB_PRE_INC_REG_OFFSET_MID, && case_FRAG_LDRSB_PRE_INC_REG_OFFSET_MID },
474 { ARM_FRAG_LDRSB_PRE_DEC_WB_IMM_OFFSET_MID, && case_FRAG_LDRSB_PRE_DEC_WB_IMM_OFFSET_MID },
475 { ARM_FRAG_LDRSB_PRE_DEC_WB_REG_OFFSET_MID, && case_FRAG_LDRSB_PRE_DEC_WB_REG_OFFSET_MID },
476 { ARM_FRAG_LDRSB_PRE_INC_WB_IMM_OFFSET_MID, && case_FRAG_LDRSB_PRE_INC_WB_IMM_OFFSET_MID },
477 { ARM_FRAG_LDRSB_PRE_INC_WB_REG_OFFSET_MID, && case_FRAG_LDRSB_PRE_INC_WB_REG_OFFSET_MID },
478 { ARM_FRAG_LDRSB_POST_DEC_IMM_OFFSET_MID, && case_FRAG_LDRSB_POST_DEC_IMM_OFFSET_MID },
479 { ARM_FRAG_LDRSB_POST_DEC_REG_OFFSET_MID, && case_FRAG_LDRSB_POST_DEC_REG_OFFSET_MID },
480 { ARM_FRAG_LDRSB_POST_INC_IMM_OFFSET_MID, && case_FRAG_LDRSB_POST_INC_IMM_OFFSET_MID },
481 { ARM_FRAG_LDRSB_POST_INC_REG_OFFSET_MID, && case_FRAG_LDRSB_POST_INC_REG_OFFSET_MID },
482 { ARM_FRAG_LDRH_PRE_DEC_IMM_OFFSET_MID, && case_FRAG_LDRH_PRE_DEC_IMM_OFFSET_MID },
483 { ARM_FRAG_LDRH_PRE_DEC_REG_OFFSET_MID, && case_FRAG_LDRH_PRE_DEC_REG_OFFSET_MID },
484 { ARM_FRAG_LDRH_PRE_INC_IMM_OFFSET_MID, && case_FRAG_LDRH_PRE_INC_IMM_OFFSET_MID },
485 { ARM_FRAG_LDRH_PRE_INC_REG_OFFSET_MID, && case_FRAG_LDRH_PRE_INC_REG_OFFSET_MID },
486 { ARM_FRAG_LDRH_PRE_DEC_WB_IMM_OFFSET_MID, && case_FRAG_LDRH_PRE_DEC_WB_IMM_OFFSET_MID },
487 { ARM_FRAG_LDRH_PRE_DEC_WB_REG_OFFSET_MID, && case_FRAG_LDRH_PRE_DEC_WB_REG_OFFSET_MID },
488 { ARM_FRAG_LDRH_PRE_INC_WB_IMM_OFFSET_MID, && case_FRAG_LDRH_PRE_INC_WB_IMM_OFFSET_MID },
489 { ARM_FRAG_LDRH_PRE_INC_WB_REG_OFFSET_MID, && case_FRAG_LDRH_PRE_INC_WB_REG_OFFSET_MID },
490 { ARM_FRAG_LDRH_POST_DEC_IMM_OFFSET_MID, && case_FRAG_LDRH_POST_DEC_IMM_OFFSET_MID },
491 { ARM_FRAG_LDRH_POST_DEC_REG_OFFSET_MID, && case_FRAG_LDRH_POST_DEC_REG_OFFSET_MID },
492 { ARM_FRAG_LDRH_POST_INC_IMM_OFFSET_MID, && case_FRAG_LDRH_POST_INC_IMM_OFFSET_MID },
493 { ARM_FRAG_LDRH_POST_INC_REG_OFFSET_MID, && case_FRAG_LDRH_POST_INC_REG_OFFSET_MID },
494 { ARM_FRAG_LDRSH_PRE_DEC_IMM_OFFSET_MID, && case_FRAG_LDRSH_PRE_DEC_IMM_OFFSET_MID },
495 { ARM_FRAG_LDRSH_PRE_DEC_REG_OFFSET_MID, && case_FRAG_LDRSH_PRE_DEC_REG_OFFSET_MID },
496 { ARM_FRAG_LDRSH_PRE_INC_IMM_OFFSET_MID, && case_FRAG_LDRSH_PRE_INC_IMM_OFFSET_MID },
497 { ARM_FRAG_LDRSH_PRE_INC_REG_OFFSET_MID, && case_FRAG_LDRSH_PRE_INC_REG_OFFSET_MID },
498 { ARM_FRAG_LDRSH_PRE_DEC_WB_IMM_OFFSET_MID, && case_FRAG_LDRSH_PRE_DEC_WB_IMM_OFFSET_MID },
499 { ARM_FRAG_LDRSH_PRE_DEC_WB_REG_OFFSET_MID, && case_FRAG_LDRSH_PRE_DEC_WB_REG_OFFSET_MID },
500 { ARM_FRAG_LDRSH_PRE_INC_WB_IMM_OFFSET_MID, && case_FRAG_LDRSH_PRE_INC_WB_IMM_OFFSET_MID },
501 { ARM_FRAG_LDRSH_PRE_INC_WB_REG_OFFSET_MID, && case_FRAG_LDRSH_PRE_INC_WB_REG_OFFSET_MID },
502 { ARM_FRAG_LDRSH_POST_DEC_IMM_OFFSET_MID, && case_FRAG_LDRSH_POST_DEC_IMM_OFFSET_MID },
503 { ARM_FRAG_LDRSH_POST_DEC_REG_OFFSET_MID, && case_FRAG_LDRSH_POST_DEC_REG_OFFSET_MID },
504 { ARM_FRAG_LDRSH_POST_INC_IMM_OFFSET_MID, && case_FRAG_LDRSH_POST_INC_IMM_OFFSET_MID },
505 { ARM_FRAG_LDRSH_POST_INC_REG_OFFSET_MID, && case_FRAG_LDRSH_POST_INC_REG_OFFSET_MID },
506 { ARM_FRAG_MUL_MID, && case_FRAG_MUL_MID },
507 { ARM_FRAG_MLA_MID, && case_FRAG_MLA_MID },
508 { ARM_FRAG_UMULL_MID, && case_FRAG_UMULL_MID },
509 { ARM_FRAG_UMLAL_MID, && case_FRAG_UMLAL_MID },
510 { ARM_FRAG_SMULL_MID, && case_FRAG_SMULL_MID },
511 { ARM_FRAG_SMLAL_MID, && case_FRAG_SMLAL_MID },
512 { ARM_FRAG_SWP_MID, && case_FRAG_SWP_MID },
513 { ARM_FRAG_SWPB_MID, && case_FRAG_SWPB_MID },
514 { ARM_FRAG_SWI_MID, && case_FRAG_SWI_MID },
515 { ARM_FRAG_AND_REG_IMM_SHIFT_MID, && case_FRAG_AND_REG_IMM_SHIFT_MID },
516 { ARM_FRAG_AND_REG_REG_SHIFT_MID, && case_FRAG_AND_REG_REG_SHIFT_MID },
517 { ARM_FRAG_AND_IMM_MID, && case_FRAG_AND_IMM_MID },
518 { ARM_FRAG_ORR_REG_IMM_SHIFT_MID, && case_FRAG_ORR_REG_IMM_SHIFT_MID },
519 { ARM_FRAG_ORR_REG_REG_SHIFT_MID, && case_FRAG_ORR_REG_REG_SHIFT_MID },
520 { ARM_FRAG_ORR_IMM_MID, && case_FRAG_ORR_IMM_MID },
521 { ARM_FRAG_EOR_REG_IMM_SHIFT_MID, && case_FRAG_EOR_REG_IMM_SHIFT_MID },
522 { ARM_FRAG_EOR_REG_REG_SHIFT_MID, && case_FRAG_EOR_REG_REG_SHIFT_MID },
523 { ARM_FRAG_EOR_IMM_MID, && case_FRAG_EOR_IMM_MID },
524 { ARM_FRAG_MOV_REG_IMM_SHIFT_MID, && case_FRAG_MOV_REG_IMM_SHIFT_MID },
525 { ARM_FRAG_MOV_REG_REG_SHIFT_MID, && case_FRAG_MOV_REG_REG_SHIFT_MID },
526 { ARM_FRAG_MOV_IMM_MID, && case_FRAG_MOV_IMM_MID },
527 { ARM_FRAG_BIC_REG_IMM_SHIFT_MID, && case_FRAG_BIC_REG_IMM_SHIFT_MID },
528 { ARM_FRAG_BIC_REG_REG_SHIFT_MID, && case_FRAG_BIC_REG_REG_SHIFT_MID },
529 { ARM_FRAG_BIC_IMM_MID, && case_FRAG_BIC_IMM_MID },
530 { ARM_FRAG_MVN_REG_IMM_SHIFT_MID, && case_FRAG_MVN_REG_IMM_SHIFT_MID },
531 { ARM_FRAG_MVN_REG_REG_SHIFT_MID, && case_FRAG_MVN_REG_REG_SHIFT_MID },
532 { ARM_FRAG_MVN_IMM_MID, && case_FRAG_MVN_IMM_MID },
533 { ARM_FRAG_ADD_REG_IMM_SHIFT_MID, && case_FRAG_ADD_REG_IMM_SHIFT_MID },
534 { ARM_FRAG_ADD_REG_REG_SHIFT_MID, && case_FRAG_ADD_REG_REG_SHIFT_MID },
535 { ARM_FRAG_ADD_IMM_MID, && case_FRAG_ADD_IMM_MID },
536 { ARM_FRAG_ADC_REG_IMM_SHIFT_MID, && case_FRAG_ADC_REG_IMM_SHIFT_MID },
537 { ARM_FRAG_ADC_REG_REG_SHIFT_MID, && case_FRAG_ADC_REG_REG_SHIFT_MID },
538 { ARM_FRAG_ADC_IMM_MID, && case_FRAG_ADC_IMM_MID },
539 { ARM_FRAG_SUB_REG_IMM_SHIFT_MID, && case_FRAG_SUB_REG_IMM_SHIFT_MID },
540 { ARM_FRAG_SUB_REG_REG_SHIFT_MID, && case_FRAG_SUB_REG_REG_SHIFT_MID },
541 { ARM_FRAG_SUB_IMM_MID, && case_FRAG_SUB_IMM_MID },
542 { ARM_FRAG_SBC_REG_IMM_SHIFT_MID, && case_FRAG_SBC_REG_IMM_SHIFT_MID },
543 { ARM_FRAG_SBC_REG_REG_SHIFT_MID, && case_FRAG_SBC_REG_REG_SHIFT_MID },
544 { ARM_FRAG_SBC_IMM_MID, && case_FRAG_SBC_IMM_MID },
545 { ARM_FRAG_RSB_REG_IMM_SHIFT_MID, && case_FRAG_RSB_REG_IMM_SHIFT_MID },
546 { ARM_FRAG_RSB_REG_REG_SHIFT_MID, && case_FRAG_RSB_REG_REG_SHIFT_MID },
547 { ARM_FRAG_RSB_IMM_MID, && case_FRAG_RSB_IMM_MID },
548 { ARM_FRAG_RSC_REG_IMM_SHIFT_MID, && case_FRAG_RSC_REG_IMM_SHIFT_MID },
549 { ARM_FRAG_RSC_REG_REG_SHIFT_MID, && case_FRAG_RSC_REG_REG_SHIFT_MID },
550 { ARM_FRAG_RSC_IMM_MID, && case_FRAG_RSC_IMM_MID },
551 { ARM_FRAG_TST_REG_IMM_SHIFT_MID, && case_FRAG_TST_REG_IMM_SHIFT_MID },
552 { ARM_FRAG_TST_REG_REG_SHIFT_MID, && case_FRAG_TST_REG_REG_SHIFT_MID },
553 { ARM_FRAG_TST_IMM_MID, && case_FRAG_TST_IMM_MID },
554 { ARM_FRAG_TEQ_REG_IMM_SHIFT_MID, && case_FRAG_TEQ_REG_IMM_SHIFT_MID },
555 { ARM_FRAG_TEQ_REG_REG_SHIFT_MID, && case_FRAG_TEQ_REG_REG_SHIFT_MID },
556 { ARM_FRAG_TEQ_IMM_MID, && case_FRAG_TEQ_IMM_MID },
557 { ARM_FRAG_CMP_REG_IMM_SHIFT_MID, && case_FRAG_CMP_REG_IMM_SHIFT_MID },
558 { ARM_FRAG_CMP_REG_REG_SHIFT_MID, && case_FRAG_CMP_REG_REG_SHIFT_MID },
559 { ARM_FRAG_CMP_IMM_MID, && case_FRAG_CMP_IMM_MID },
560 { ARM_FRAG_CMN_REG_IMM_SHIFT_MID, && case_FRAG_CMN_REG_IMM_SHIFT_MID },
561 { ARM_FRAG_CMN_REG_REG_SHIFT_MID, && case_FRAG_CMN_REG_REG_SHIFT_MID },
562 { ARM_FRAG_CMN_IMM_MID, && case_FRAG_CMN_IMM_MID },
563 { ARM_FRAG_LDMDA_MID, && case_FRAG_LDMDA_MID },
564 { ARM_FRAG_LDMDA_SW_MID, && case_FRAG_LDMDA_SW_MID },
565 { ARM_FRAG_LDMDA_WB_MID, && case_FRAG_LDMDA_WB_MID },
566 { ARM_FRAG_LDMDA_SW_WB_MID, && case_FRAG_LDMDA_SW_WB_MID },
567 { ARM_FRAG_LDMIB_MID, && case_FRAG_LDMIB_MID },
568 { ARM_FRAG_LDMIB_SW_MID, && case_FRAG_LDMIB_SW_MID },
569 { ARM_FRAG_LDMIB_WB_MID, && case_FRAG_LDMIB_WB_MID },
570 { ARM_FRAG_LDMIB_SW_WB_MID, && case_FRAG_LDMIB_SW_WB_MID },
571 { ARM_FRAG_LDMIA_MID, && case_FRAG_LDMIA_MID },
572 { ARM_FRAG_LDMIA_SW_MID, && case_FRAG_LDMIA_SW_MID },
573 { ARM_FRAG_LDMIA_WB_MID, && case_FRAG_LDMIA_WB_MID },
574 { ARM_FRAG_LDMIA_SW_WB_MID, && case_FRAG_LDMIA_SW_WB_MID },
575 { ARM_FRAG_LDMDB_MID, && case_FRAG_LDMDB_MID },
576 { ARM_FRAG_LDMDB_SW_MID, && case_FRAG_LDMDB_SW_MID },
577 { ARM_FRAG_LDMDB_WB_MID, && case_FRAG_LDMDB_WB_MID },
578 { ARM_FRAG_LDMDB_SW_WB_MID, && case_FRAG_LDMDB_SW_WB_MID },
579 { ARM_FRAG_STMDB_MID, && case_FRAG_STMDB_MID },
580 { ARM_FRAG_STMDB_SW_MID, && case_FRAG_STMDB_SW_MID },
581 { ARM_FRAG_STMDB_WB_MID, && case_FRAG_STMDB_WB_MID },
582 { ARM_FRAG_STMDB_SW_WB_MID, && case_FRAG_STMDB_SW_WB_MID },
583 { ARM_FRAG_STMIB_MID, && case_FRAG_STMIB_MID },
584 { ARM_FRAG_STMIB_SW_MID, && case_FRAG_STMIB_SW_MID },
585 { ARM_FRAG_STMIB_WB_MID, && case_FRAG_STMIB_WB_MID },
586 { ARM_FRAG_STMIB_SW_WB_MID, && case_FRAG_STMIB_SW_WB_MID },
587 { ARM_FRAG_STMIA_MID, && case_FRAG_STMIA_MID },
588 { ARM_FRAG_STMIA_SW_MID, && case_FRAG_STMIA_SW_MID },
589 { ARM_FRAG_STMIA_WB_MID, && case_FRAG_STMIA_WB_MID },
590 { ARM_FRAG_STMIA_SW_WB_MID, && case_FRAG_STMIA_SW_WB_MID },
591 { ARM_FRAG_STMDA_MID, && case_FRAG_STMDA_MID },
592 { ARM_FRAG_STMDA_SW_MID, && case_FRAG_STMDA_SW_MID },
593 { ARM_FRAG_STMDA_WB_MID, && case_FRAG_STMDA_WB_MID },
594 { ARM_FRAG_STMDA_SW_WB_MID, && case_FRAG_STMDA_SW_WB_MID },
595 { ARM_FRAG_MRS_C_MID, && case_FRAG_MRS_C_MID },
596 { ARM_FRAG_MRS_S_MID, && case_FRAG_MRS_S_MID },
597 { ARM_FRAG_MSR_C_MID, && case_FRAG_MSR_C_MID },
598 { ARM_FRAG_MSR_S_MID, && case_FRAG_MSR_S_MID },
602 if (! arm_idesc::idesc_table_initialized_p)
604 // Several tables are in play here:
605 // idesc table: const table of misc things for each insn
606 // frag usage table: const set of frags used by each insn
607 // frag label table: same as frag usage table, but contains labels
608 // selected insn frag table: table of pointers to either the frag usage
609 // table (if !gnuc) or frag label table (if gnuc) for the currently
610 // selected ISA. Insns not in the ISA are redirected to the `invalid'
611 // insn handler. FIXME: This one isn't implemented yet.
613 // Allocate frag label table and point idesc table entries at it.
614 // FIXME: Temporary hack, to be redone.
615 static void** frag_label_table;
616 int max_insns = ARM_INSN_MSR_S + 1;
617 int tabsize = max_insns * 4;
618 frag_label_table = new void* [tabsize];
619 memset (frag_label_table, 0, sizeof (void*) * tabsize);
622 for (i = 0, v = frag_label_table; i < max_insns; ++i)
624 arm_idesc::idesc_table[arm_frag_usage[i].itype].cgoto.frags = v;
625 for (int j = 0; arm_frag_usage[i].ftype[j] != ARM_FRAG_LIST_END; ++j)
626 *v++ = labels[arm_frag_usage[i].ftype[j]].label;
629 // Initialize the compiler virtual insn.
630 // FIXME: Also needed if !gnuc.
631 current_cpu->arm_engine.compile_begin_insn (current_cpu);
633 arm_idesc::idesc_table_initialized_p = true;
639 #define CASE(X) case_##X
640 // Branch to next handler without going around main loop.
641 #define NEXT_INSN(vpc, fragpc) fragpc = vpc->execute.cgoto.frags; goto * *fragpc
642 #define NEXT_FRAG(fragpc) ++fragpc; goto * *fragpc
643 // Break out of threaded interpreter and return to "main loop".
644 #define BREAK(vpc) goto end_switch
646 #define CASE(X) case ARM_##X
647 #define NEXT_INSN(vpc, fragpc) fragpc = vpc->idesc->frags; goto restart
648 #define NEXT_FRAG(fragpc) ++fragpc; goto restart
649 #define BREAK(vpc) break
652 // Get next insn to execute.
653 vpc = current_cpu->arm_engine.get_next_vpc (current_cpu->h_pc_get ());
656 // These two are used to pass data from cti insns to the cti-chain insn.
658 branch_status pbb_br_status;
659 // These two are used to build up values of the previous two.
661 branch_status br_status;
662 // Top level locals moved here so they're usable by multiple fragments.
677 fragpc = vpc->execute.cgoto.frags;
680 fragpc = vpc->idesc->frags;
686 // ********** used by: mvn-reg/reg-shift, add-reg/reg-shift, adc-reg/reg-shift, sub-reg/reg-shift, sbc-reg/reg-shift, rsb-reg/reg-shift, rsc-reg/reg-shift
688 CASE (FRAG_MVN_REG_REG_SHIFT_HDR):
692 #define FLD(f) abuf->fields.sfmt_and_reg_reg_shift.f
693 PCADDR pc = abuf->addr;
694 br_status = BRANCH_UNTAKEN;
695 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
698 operand2 = current_cpu->compute_operand2_regshift (* FLD (i_rm), FLD (f_operand2_shifttype), * FLD (i_operand2_shiftreg));
705 // ********** used only by: cmp-reg/reg-shift
707 CASE (FRAG_CMP_REG_REG_SHIFT_HDR):
711 #define FLD(f) abuf->fields.sfmt_and_reg_reg_shift.f
712 PCADDR pc = abuf->addr;
713 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
716 operand2 = current_cpu->compute_operand2_regshift (* FLD (i_rm), FLD (f_operand2_shifttype), * FLD (i_operand2_shiftreg));
723 // ********** used by: tst-reg/reg-shift, teq-reg/reg-shift
725 CASE (FRAG_TST_REG_REG_SHIFT_HDR):
729 #define FLD(f) abuf->fields.sfmt_and_reg_reg_shift.f
730 PCADDR pc = abuf->addr;
731 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
734 operand2 = current_cpu->compute_operand2_regshift (* FLD (i_rm), FLD (f_operand2_shifttype), * FLD (i_operand2_shiftreg));
735 carry_out = current_cpu->compute_carry_out_regshift (* FLD (i_rm), FLD (f_operand2_shifttype), * FLD (i_operand2_shiftreg), current_cpu->hardware.h_cbit);
742 // ********** used by: orr-reg/reg-shift, eor-reg/reg-shift, mov-reg/reg-shift, bic-reg/reg-shift
744 CASE (FRAG_ORR_REG_REG_SHIFT_HDR):
748 #define FLD(f) abuf->fields.sfmt_and_reg_reg_shift.f
749 PCADDR pc = abuf->addr;
750 br_status = BRANCH_UNTAKEN;
751 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
754 operand2 = current_cpu->compute_operand2_regshift (* FLD (i_rm), FLD (f_operand2_shifttype), * FLD (i_operand2_shiftreg));
755 carry_out = current_cpu->compute_carry_out_regshift (* FLD (i_rm), FLD (f_operand2_shifttype), * FLD (i_operand2_shiftreg), current_cpu->hardware.h_cbit);
762 // ********** used by: mvn-reg/imm-shift, add-reg/imm-shift, adc-reg/imm-shift, sub-reg/imm-shift, sbc-reg/imm-shift, rsb-reg/imm-shift, rsc-reg/imm-shift
764 CASE (FRAG_MVN_REG_IMM_SHIFT_HDR):
768 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
769 PCADDR pc = abuf->addr;
770 br_status = BRANCH_UNTAKEN;
771 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
774 operand2 = current_cpu->compute_operand2_immshift (* FLD (i_rm), FLD (f_operand2_shifttype), FLD (f_operand2_shiftimm));
781 // ********** used only by: cmp-reg/imm-shift
783 CASE (FRAG_CMP_REG_IMM_SHIFT_HDR):
787 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
788 PCADDR pc = abuf->addr;
789 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
792 operand2 = current_cpu->compute_operand2_immshift (* FLD (i_rm), FLD (f_operand2_shifttype), FLD (f_operand2_shiftimm));
799 // ********** used by: tst-reg/imm-shift, teq-reg/imm-shift
801 CASE (FRAG_TST_REG_IMM_SHIFT_HDR):
805 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
806 PCADDR pc = abuf->addr;
807 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
810 operand2 = current_cpu->compute_operand2_immshift (* FLD (i_rm), FLD (f_operand2_shifttype), FLD (f_operand2_shiftimm));
811 carry_out = current_cpu->compute_carry_out_immshift (* FLD (i_rm), FLD (f_operand2_shifttype), FLD (f_operand2_shiftimm), current_cpu->hardware.h_cbit);
818 // ********** used by: orr-reg/imm-shift, eor-reg/imm-shift, mov-reg/imm-shift, bic-reg/imm-shift
820 CASE (FRAG_ORR_REG_IMM_SHIFT_HDR):
824 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
825 PCADDR pc = abuf->addr;
826 br_status = BRANCH_UNTAKEN;
827 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
830 operand2 = current_cpu->compute_operand2_immshift (* FLD (i_rm), FLD (f_operand2_shifttype), FLD (f_operand2_shiftimm));
831 carry_out = current_cpu->compute_carry_out_immshift (* FLD (i_rm), FLD (f_operand2_shifttype), FLD (f_operand2_shiftimm), current_cpu->hardware.h_cbit);
838 // ********** used by: strb-post-inc-nonpriv-reg-offset, str-pre-dec-wb-reg-offset, str-pre-dec-reg-offset, strb-pre-dec-wb-reg-offset, strb-pre-dec-reg-offset, str-pre-inc-wb-reg-offset, str-pre-inc-reg-offset, strb-pre-inc-wb-reg-offset
840 CASE (FRAG_STRB_POST_INC_NONPRIV_REG_OFFSET_HDR):
844 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
845 PCADDR pc = abuf->addr;
846 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
849 offset = current_cpu->compute_operand2_immshift (* FLD (i_rm), FLD (f_operand2_shifttype), FLD (f_operand2_shiftimm));
856 // ********** used by: ldr-pre-dec-wb-reg-offset, ldr-pre-dec-reg-offset, ldrb-pre-dec-wb-reg-offset, ldrb-pre-dec-reg-offset, ldr-pre-inc-wb-reg-offset, ldr-pre-inc-reg-offset, ldrb-pre-inc-wb-reg-offset, ldrb-pre-inc-reg-offset
858 CASE (FRAG_LDR_PRE_DEC_WB_REG_OFFSET_HDR):
862 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
863 PCADDR pc = abuf->addr;
864 br_status = BRANCH_UNTAKEN;
865 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
868 offset = current_cpu->compute_operand2_immshift (* FLD (i_rm), FLD (f_operand2_shifttype), FLD (f_operand2_shiftimm));
875 // ********** used by: ldr-post-inc-nonpriv-reg-offset, ldrb-post-dec-reg-offset, ldrb-post-dec-nonpriv-reg-offset, ldrb-post-inc-reg-offset, ldrb-post-inc-nonpriv-reg-offset
877 CASE (FRAG_LDR_POST_INC_NONPRIV_REG_OFFSET_HDR):
881 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
882 PCADDR pc = abuf->addr;
883 br_status = BRANCH_UNTAKEN;
884 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
887 offset = current_cpu->compute_operand2_immshift (* FLD (i_rm), FLD (f_operand2_shifttype), FLD (f_operand2_shiftimm));
895 // ********** used by: str-post-dec-reg-offset, str-post-dec-nonpriv-reg-offset, str-post-inc-reg-offset, str-post-inc-nonpriv-reg-offset, strb-post-dec-reg-offset, strb-post-dec-nonpriv-reg-offset, strb-post-inc-reg-offset
897 CASE (FRAG_STR_POST_DEC_REG_OFFSET_HDR):
901 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
902 PCADDR pc = abuf->addr;
903 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
906 offset = current_cpu->compute_operand2_immshift (* FLD (i_rm), FLD (f_operand2_shifttype), FLD (f_operand2_shiftimm));
914 // ********** used by: ldr-post-dec-nonpriv-reg-offset, ldr-post-inc-reg-offset
916 CASE (FRAG_LDR_POST_DEC_NONPRIV_REG_OFFSET_HDR):
920 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
921 PCADDR pc = abuf->addr;
922 br_status = BRANCH_UNTAKEN;
923 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
926 offset = current_cpu->compute_operand2_immshift (* FLD (i_rm), FLD (f_operand2_shifttype), FLD (f_operand2_shiftimm));
928 if (EQSI (FLD (f_rd), 15)) {
929 npc = current_cpu->GETMEMSI (pc, addr); br_status = BRANCH_UNCACHEABLE;
931 * FLD (i_rd) = current_cpu->GETMEMSI (pc, addr);
939 // ********** used by: stmda-wb, stmda-sw
941 CASE (FRAG_STMDA_WB_HDR):
945 #define FLD(f) abuf->fields.sfmt_ldmda.f
946 PCADDR pc = abuf->addr;
947 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
951 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
953 current_cpu->SETMEMSI (pc, addr, ADDSI (current_cpu->hardware.h_gr[((UINT) 15)], 4));
954 addr = SUBSI (addr, 4);
963 // ********** used by: stmia-wb, stmia-sw
965 CASE (FRAG_STMIA_WB_HDR):
969 #define FLD(f) abuf->fields.sfmt_ldmda.f
970 PCADDR pc = abuf->addr;
971 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
975 if (ANDSI (FLD (f_reg_list), SLLSI (1, 0))) {
977 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 0)]);
978 addr = ADDSI (addr, 4);
981 if (ANDSI (FLD (f_reg_list), SLLSI (1, 1))) {
983 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 1)]);
984 addr = ADDSI (addr, 4);
987 if (ANDSI (FLD (f_reg_list), SLLSI (1, 2))) {
989 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 2)]);
990 addr = ADDSI (addr, 4);
993 if (ANDSI (FLD (f_reg_list), SLLSI (1, 3))) {
995 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 3)]);
996 addr = ADDSI (addr, 4);
999 if (ANDSI (FLD (f_reg_list), SLLSI (1, 4))) {
1001 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 4)]);
1002 addr = ADDSI (addr, 4);
1005 if (ANDSI (FLD (f_reg_list), SLLSI (1, 5))) {
1007 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 5)]);
1008 addr = ADDSI (addr, 4);
1011 if (ANDSI (FLD (f_reg_list), SLLSI (1, 6))) {
1013 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 6)]);
1014 addr = ADDSI (addr, 4);
1017 if (ANDSI (FLD (f_reg_list), SLLSI (1, 7))) {
1019 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 7)]);
1020 addr = ADDSI (addr, 4);
1029 // ********** used by: stmib-wb, stmib-sw
1031 CASE (FRAG_STMIB_WB_HDR):
1035 #define FLD(f) abuf->fields.sfmt_ldmda.f
1036 PCADDR pc = abuf->addr;
1037 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
1040 addr = * FLD (i_rn);
1041 if (ANDSI (FLD (f_reg_list), SLLSI (1, 0))) {
1043 addr = ADDSI (addr, 4);
1044 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 0)]);
1047 if (ANDSI (FLD (f_reg_list), SLLSI (1, 1))) {
1049 addr = ADDSI (addr, 4);
1050 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 1)]);
1053 if (ANDSI (FLD (f_reg_list), SLLSI (1, 2))) {
1055 addr = ADDSI (addr, 4);
1056 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 2)]);
1059 if (ANDSI (FLD (f_reg_list), SLLSI (1, 3))) {
1061 addr = ADDSI (addr, 4);
1062 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 3)]);
1065 if (ANDSI (FLD (f_reg_list), SLLSI (1, 4))) {
1067 addr = ADDSI (addr, 4);
1068 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 4)]);
1071 if (ANDSI (FLD (f_reg_list), SLLSI (1, 5))) {
1073 addr = ADDSI (addr, 4);
1074 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 5)]);
1077 if (ANDSI (FLD (f_reg_list), SLLSI (1, 6))) {
1079 addr = ADDSI (addr, 4);
1080 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 6)]);
1083 if (ANDSI (FLD (f_reg_list), SLLSI (1, 7))) {
1085 addr = ADDSI (addr, 4);
1086 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 7)]);
1095 // ********** used by: stmdb-wb, stmdb-sw
1097 CASE (FRAG_STMDB_WB_HDR):
1101 #define FLD(f) abuf->fields.sfmt_ldmda.f
1102 PCADDR pc = abuf->addr;
1103 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
1106 addr = * FLD (i_rn);
1107 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
1109 addr = SUBSI (addr, 4);
1110 current_cpu->SETMEMSI (pc, addr, ADDSI (current_cpu->hardware.h_gr[((UINT) 15)], 4));
1119 // ********** used by: ldmia-wb, ldmia-sw
1121 CASE (FRAG_LDMIA_WB_HDR):
1125 #define FLD(f) abuf->fields.sfmt_ldmda.f
1126 PCADDR pc = abuf->addr;
1127 br_status = BRANCH_UNTAKEN;
1128 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
1131 addr = * FLD (i_rn);
1132 if (ANDSI (FLD (f_reg_list), SLLSI (1, 0))) {
1134 current_cpu->hardware.h_gr[((UINT) 0)] = current_cpu->GETMEMSI (pc, addr);
1135 addr = ADDSI (addr, 4);
1138 if (ANDSI (FLD (f_reg_list), SLLSI (1, 1))) {
1140 current_cpu->hardware.h_gr[((UINT) 1)] = current_cpu->GETMEMSI (pc, addr);
1141 addr = ADDSI (addr, 4);
1144 if (ANDSI (FLD (f_reg_list), SLLSI (1, 2))) {
1146 current_cpu->hardware.h_gr[((UINT) 2)] = current_cpu->GETMEMSI (pc, addr);
1147 addr = ADDSI (addr, 4);
1150 if (ANDSI (FLD (f_reg_list), SLLSI (1, 3))) {
1152 current_cpu->hardware.h_gr[((UINT) 3)] = current_cpu->GETMEMSI (pc, addr);
1153 addr = ADDSI (addr, 4);
1156 if (ANDSI (FLD (f_reg_list), SLLSI (1, 4))) {
1158 current_cpu->hardware.h_gr[((UINT) 4)] = current_cpu->GETMEMSI (pc, addr);
1159 addr = ADDSI (addr, 4);
1162 if (ANDSI (FLD (f_reg_list), SLLSI (1, 5))) {
1164 current_cpu->hardware.h_gr[((UINT) 5)] = current_cpu->GETMEMSI (pc, addr);
1165 addr = ADDSI (addr, 4);
1168 if (ANDSI (FLD (f_reg_list), SLLSI (1, 6))) {
1170 current_cpu->hardware.h_gr[((UINT) 6)] = current_cpu->GETMEMSI (pc, addr);
1171 addr = ADDSI (addr, 4);
1174 if (ANDSI (FLD (f_reg_list), SLLSI (1, 7))) {
1176 current_cpu->hardware.h_gr[((UINT) 7)] = current_cpu->GETMEMSI (pc, addr);
1177 addr = ADDSI (addr, 4);
1186 // ********** used by: ldmib-wb, ldmib-sw
1188 CASE (FRAG_LDMIB_WB_HDR):
1192 #define FLD(f) abuf->fields.sfmt_ldmda.f
1193 PCADDR pc = abuf->addr;
1194 br_status = BRANCH_UNTAKEN;
1195 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
1198 addr = * FLD (i_rn);
1199 if (ANDSI (FLD (f_reg_list), SLLSI (1, 0))) {
1201 addr = ADDSI (addr, 4);
1202 current_cpu->hardware.h_gr[((UINT) 0)] = current_cpu->GETMEMSI (pc, addr);
1205 if (ANDSI (FLD (f_reg_list), SLLSI (1, 1))) {
1207 addr = ADDSI (addr, 4);
1208 current_cpu->hardware.h_gr[((UINT) 1)] = current_cpu->GETMEMSI (pc, addr);
1211 if (ANDSI (FLD (f_reg_list), SLLSI (1, 2))) {
1213 addr = ADDSI (addr, 4);
1214 current_cpu->hardware.h_gr[((UINT) 2)] = current_cpu->GETMEMSI (pc, addr);
1217 if (ANDSI (FLD (f_reg_list), SLLSI (1, 3))) {
1219 addr = ADDSI (addr, 4);
1220 current_cpu->hardware.h_gr[((UINT) 3)] = current_cpu->GETMEMSI (pc, addr);
1223 if (ANDSI (FLD (f_reg_list), SLLSI (1, 4))) {
1225 addr = ADDSI (addr, 4);
1226 current_cpu->hardware.h_gr[((UINT) 4)] = current_cpu->GETMEMSI (pc, addr);
1229 if (ANDSI (FLD (f_reg_list), SLLSI (1, 5))) {
1231 addr = ADDSI (addr, 4);
1232 current_cpu->hardware.h_gr[((UINT) 5)] = current_cpu->GETMEMSI (pc, addr);
1235 if (ANDSI (FLD (f_reg_list), SLLSI (1, 6))) {
1237 addr = ADDSI (addr, 4);
1238 current_cpu->hardware.h_gr[((UINT) 6)] = current_cpu->GETMEMSI (pc, addr);
1241 if (ANDSI (FLD (f_reg_list), SLLSI (1, 7))) {
1243 addr = ADDSI (addr, 4);
1244 current_cpu->hardware.h_gr[((UINT) 7)] = current_cpu->GETMEMSI (pc, addr);
1253 // ********** used by: strb-post-dec-nonpriv-imm-offset, strb-post-inc-imm-offset
1255 CASE (FRAG_STRB_POST_DEC_NONPRIV_IMM_OFFSET_HDR):
1259 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
1260 PCADDR pc = abuf->addr;
1261 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
1264 offset = FLD (f_uimm12);
1265 addr = * FLD (i_rn);
1266 current_cpu->SETMEMQI (pc, addr, TRUNCSIQI (* FLD (i_rd)));
1273 // ********** used by: ldrb-post-dec-nonpriv-imm-offset, ldrb-post-inc-imm-offset
1275 CASE (FRAG_LDRB_POST_DEC_NONPRIV_IMM_OFFSET_HDR):
1279 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
1280 PCADDR pc = abuf->addr;
1281 br_status = BRANCH_UNTAKEN;
1282 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
1285 offset = FLD (f_uimm12);
1286 addr = * FLD (i_rn);
1287 if (EQSI (FLD (f_rd), 15)) {
1288 npc = ZEXTQISI (current_cpu->GETMEMQI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
1290 * FLD (i_rd) = ZEXTQISI (current_cpu->GETMEMQI (pc, addr));
1298 // ********** used by: ldr-post-dec-nonpriv-imm-offset, ldr-post-inc-imm-offset
1300 CASE (FRAG_LDR_POST_DEC_NONPRIV_IMM_OFFSET_HDR):
1304 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
1305 PCADDR pc = abuf->addr;
1306 br_status = BRANCH_UNTAKEN;
1307 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
1310 offset = FLD (f_uimm12);
1311 addr = * FLD (i_rn);
1312 if (EQSI (FLD (f_rd), 15)) {
1313 npc = current_cpu->GETMEMSI (pc, addr); br_status = BRANCH_UNCACHEABLE;
1315 * FLD (i_rd) = current_cpu->GETMEMSI (pc, addr);
1323 // ********** used by:
1325 CASE (FRAG_X_HEADER):
1329 #define FLD(f) abuf->fields.fmt_empty.f
1330 PCADDR pc = abuf->addr;
1338 // ********** used only by: tst-reg/reg-shift
1340 CASE (FRAG_TST_REG_REG_SHIFT_TRLR):
1342 #define FLD(f) abuf->fields.sfmt_and_reg_reg_shift.f
1343 PCADDR pc = abuf->addr;
1346 if (EQSI (FLD (f_rd), 15)) {
1347 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
1351 current_cpu->hardware.h_zbit = EQSI (result, 0);
1352 current_cpu->hardware.h_nbit = LTSI (result, 0);
1354 current_cpu->hardware.h_cbit = carry_out;
1361 NEXT_INSN (vpc, fragpc);
1363 // ********** used only by: teq-reg/imm-shift
1365 CASE (FRAG_TEQ_REG_IMM_SHIFT_TRLR):
1367 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
1368 PCADDR pc = abuf->addr;
1371 if (EQSI (FLD (f_rd), 15)) {
1372 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
1376 current_cpu->hardware.h_zbit = EQSI (result, 0);
1377 current_cpu->hardware.h_nbit = LTSI (result, 0);
1379 current_cpu->hardware.h_cbit = carry_out;
1386 NEXT_INSN (vpc, fragpc);
1388 // ********** used by: and-imm, orr-imm, eor-imm, mov-imm, bic-imm
1390 CASE (FRAG_AND_IMM_TRLR):
1392 #define FLD(f) abuf->fields.sfmt_and_imm.f
1393 PCADDR pc = abuf->addr;
1396 if (EQSI (FLD (f_rd), 15)) {
1398 npc = result; br_status = BRANCH_UNCACHEABLE;
1399 if (FLD (f_set_cc_)) {
1400 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
1405 * FLD (i_rd) = result;
1406 if (FLD (f_set_cc_)) {
1408 current_cpu->hardware.h_zbit = EQSI (result, 0);
1409 current_cpu->hardware.h_nbit = LTSI (result, 0);
1417 pbb_br_status = br_status;
1420 NEXT_INSN (vpc, fragpc);
1422 // ********** used by: and-reg/reg-shift, orr-reg/reg-shift, eor-reg/reg-shift, mov-reg/reg-shift, bic-reg/reg-shift
1424 CASE (FRAG_AND_REG_REG_SHIFT_TRLR):
1426 #define FLD(f) abuf->fields.sfmt_and_reg_reg_shift.f
1427 PCADDR pc = abuf->addr;
1430 if (EQSI (FLD (f_rd), 15)) {
1432 npc = result; br_status = BRANCH_UNCACHEABLE;
1433 if (FLD (f_set_cc_)) {
1434 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
1439 * FLD (i_rd) = result;
1440 if (FLD (f_set_cc_)) {
1443 current_cpu->hardware.h_zbit = EQSI (result, 0);
1444 current_cpu->hardware.h_nbit = LTSI (result, 0);
1446 current_cpu->hardware.h_cbit = carry_out;
1454 pbb_br_status = br_status;
1457 NEXT_INSN (vpc, fragpc);
1459 // ********** used by: orr-reg/imm-shift, eor-reg/imm-shift, mov-reg/imm-shift, bic-reg/imm-shift, mvn-reg/imm-shift
1461 CASE (FRAG_ORR_REG_IMM_SHIFT_TRLR):
1463 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
1464 PCADDR pc = abuf->addr;
1467 if (EQSI (FLD (f_rd), 15)) {
1469 npc = result; br_status = BRANCH_UNCACHEABLE;
1470 if (FLD (f_set_cc_)) {
1471 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
1476 * FLD (i_rd) = result;
1477 if (FLD (f_set_cc_)) {
1480 current_cpu->hardware.h_zbit = EQSI (result, 0);
1481 current_cpu->hardware.h_nbit = LTSI (result, 0);
1483 current_cpu->hardware.h_cbit = carry_out;
1491 pbb_br_status = br_status;
1494 NEXT_INSN (vpc, fragpc);
1496 // ********** used by: umull, umlal, smull
1498 CASE (FRAG_UMULL_TRLR):
1500 #define FLD(f) abuf->fields.sfmt_umull.f
1501 PCADDR pc = abuf->addr;
1504 * FLD (i_rdhi) = SUBWORDDISI (mul_result, 0);
1505 * FLD (i_rdlo) = SUBWORDDISI (mul_result, 1);
1506 if (FLD (f_set_cc_)) {
1508 current_cpu->hardware.h_zbit = EQDI (mul_result, 0);
1509 current_cpu->hardware.h_nbit = LTDI (mul_result, 0);
1516 NEXT_INSN (vpc, fragpc);
1518 // ********** used by: ldr-pre-inc-imm-offset, ldrb-pre-dec-imm-offset, ldrb-pre-inc-imm-offset
1520 CASE (FRAG_LDR_PRE_INC_IMM_OFFSET_TRLR):
1522 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
1523 PCADDR pc = abuf->addr;
1531 pbb_br_status = br_status;
1534 NEXT_INSN (vpc, fragpc);
1536 // ********** used by: ldrb-pre-dec-reg-offset, ldrb-pre-inc-reg-offset, ldrsb-pre-dec-reg-offset, ldrsb-pre-inc-reg-offset, ldrh-pre-dec-reg-offset, ldrh-pre-inc-reg-offset, ldrsh-pre-dec-reg-offset
1538 CASE (FRAG_LDRB_PRE_DEC_REG_OFFSET_TRLR):
1540 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
1541 PCADDR pc = abuf->addr;
1549 pbb_br_status = br_status;
1552 NEXT_INSN (vpc, fragpc);
1554 // ********** used by: str-pre-dec-reg-offset, str-pre-inc-reg-offset, strb-pre-dec-reg-offset, strb-pre-inc-reg-offset, strh-pre-dec-reg-offset, strh-pre-inc-reg-offset
1556 CASE (FRAG_STR_PRE_DEC_REG_OFFSET_TRLR):
1558 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
1559 PCADDR pc = abuf->addr;
1568 NEXT_INSN (vpc, fragpc);
1570 // ********** used by: str-pre-dec-imm-offset, str-pre-inc-imm-offset, strb-pre-dec-imm-offset, strb-pre-inc-imm-offset
1572 CASE (FRAG_STR_PRE_DEC_IMM_OFFSET_TRLR):
1574 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
1575 PCADDR pc = abuf->addr;
1584 NEXT_INSN (vpc, fragpc);
1586 // ********** used by: strh-pre-dec-imm-offset, strh-pre-inc-imm-offset
1588 CASE (FRAG_STRH_PRE_DEC_IMM_OFFSET_TRLR):
1590 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
1591 PCADDR pc = abuf->addr;
1600 NEXT_INSN (vpc, fragpc);
1602 // ********** used by: ldrsb-pre-dec-imm-offset, ldrsb-pre-inc-imm-offset, ldrh-pre-dec-imm-offset, ldrh-pre-inc-imm-offset, ldrsh-pre-dec-imm-offset, ldrsh-pre-inc-imm-offset
1604 CASE (FRAG_LDRSB_PRE_DEC_IMM_OFFSET_TRLR):
1606 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
1607 PCADDR pc = abuf->addr;
1615 pbb_br_status = br_status;
1618 NEXT_INSN (vpc, fragpc);
1620 // ********** used only by: ldr-pre-dec-imm-offset
1622 CASE (FRAG_LDR_PRE_DEC_IMM_OFFSET_TRLR):
1624 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
1625 PCADDR pc = abuf->addr;
1628 if (EQSI (FLD (f_rd), 15)) {
1629 npc = current_cpu->GETMEMSI (pc, addr); br_status = BRANCH_UNCACHEABLE;
1631 * FLD (i_rd) = current_cpu->GETMEMSI (pc, addr);
1638 pbb_br_status = br_status;
1641 NEXT_INSN (vpc, fragpc);
1643 // ********** used only by: ldr-pre-inc-reg-offset
1645 CASE (FRAG_LDR_PRE_INC_REG_OFFSET_TRLR):
1647 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
1648 PCADDR pc = abuf->addr;
1651 if (EQSI (FLD (f_rd), 15)) {
1652 npc = current_cpu->GETMEMSI (pc, addr); br_status = BRANCH_UNCACHEABLE;
1654 * FLD (i_rd) = current_cpu->GETMEMSI (pc, addr);
1661 pbb_br_status = br_status;
1664 NEXT_INSN (vpc, fragpc);
1666 // ********** used by: ldr-pre-inc-wb-imm-offset, ldrb-pre-dec-wb-imm-offset, ldrb-pre-inc-wb-imm-offset
1668 CASE (FRAG_LDR_PRE_INC_WB_IMM_OFFSET_TRLR):
1670 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
1671 PCADDR pc = abuf->addr;
1675 * FLD (i_rn) = addr;
1679 pbb_br_status = br_status;
1682 NEXT_INSN (vpc, fragpc);
1684 // ********** used by: ldrb-pre-dec-wb-reg-offset, ldrb-pre-inc-wb-reg-offset, ldrsb-pre-dec-wb-reg-offset, ldrsb-pre-inc-wb-reg-offset, ldrh-pre-dec-wb-reg-offset, ldrh-pre-inc-wb-reg-offset, ldrsh-pre-dec-wb-reg-offset
1686 CASE (FRAG_LDRB_PRE_DEC_WB_REG_OFFSET_TRLR):
1688 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
1689 PCADDR pc = abuf->addr;
1693 * FLD (i_rn) = addr;
1697 pbb_br_status = br_status;
1700 NEXT_INSN (vpc, fragpc);
1702 // ********** used by: str-pre-dec-wb-reg-offset, str-pre-inc-wb-reg-offset, strb-pre-dec-wb-reg-offset, strb-pre-inc-wb-reg-offset, strh-pre-dec-wb-reg-offset, strh-pre-inc-wb-reg-offset
1704 CASE (FRAG_STR_PRE_DEC_WB_REG_OFFSET_TRLR):
1706 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
1707 PCADDR pc = abuf->addr;
1711 * FLD (i_rn) = addr;
1716 NEXT_INSN (vpc, fragpc);
1718 // ********** used by: str-pre-dec-wb-imm-offset, str-pre-inc-wb-imm-offset, strb-pre-dec-wb-imm-offset, strb-pre-inc-wb-imm-offset
1720 CASE (FRAG_STR_PRE_DEC_WB_IMM_OFFSET_TRLR):
1722 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
1723 PCADDR pc = abuf->addr;
1727 * FLD (i_rn) = addr;
1732 NEXT_INSN (vpc, fragpc);
1734 // ********** used by: strh-pre-dec-wb-imm-offset, strh-pre-inc-wb-imm-offset
1736 CASE (FRAG_STRH_PRE_DEC_WB_IMM_OFFSET_TRLR):
1738 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
1739 PCADDR pc = abuf->addr;
1743 * FLD (i_rn) = addr;
1748 NEXT_INSN (vpc, fragpc);
1750 // ********** used by: ldrsb-pre-dec-wb-imm-offset, ldrsb-pre-inc-wb-imm-offset, ldrh-pre-dec-wb-imm-offset, ldrh-pre-inc-wb-imm-offset, ldrsh-pre-dec-wb-imm-offset, ldrsh-pre-inc-wb-imm-offset
1752 CASE (FRAG_LDRSB_PRE_DEC_WB_IMM_OFFSET_TRLR):
1754 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
1755 PCADDR pc = abuf->addr;
1759 * FLD (i_rn) = addr;
1763 pbb_br_status = br_status;
1766 NEXT_INSN (vpc, fragpc);
1768 // ********** used only by: ldr-pre-dec-wb-imm-offset
1770 CASE (FRAG_LDR_PRE_DEC_WB_IMM_OFFSET_TRLR):
1772 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
1773 PCADDR pc = abuf->addr;
1776 if (EQSI (FLD (f_rd), 15)) {
1777 npc = current_cpu->GETMEMSI (pc, addr); br_status = BRANCH_UNCACHEABLE;
1779 * FLD (i_rd) = current_cpu->GETMEMSI (pc, addr);
1782 * FLD (i_rn) = addr;
1786 pbb_br_status = br_status;
1789 NEXT_INSN (vpc, fragpc);
1791 // ********** used only by: ldr-pre-inc-wb-reg-offset
1793 CASE (FRAG_LDR_PRE_INC_WB_REG_OFFSET_TRLR):
1795 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
1796 PCADDR pc = abuf->addr;
1799 if (EQSI (FLD (f_rd), 15)) {
1800 npc = current_cpu->GETMEMSI (pc, addr); br_status = BRANCH_UNCACHEABLE;
1802 * FLD (i_rd) = current_cpu->GETMEMSI (pc, addr);
1805 * FLD (i_rn) = addr;
1809 pbb_br_status = br_status;
1812 NEXT_INSN (vpc, fragpc);
1814 // ********** used by: strb-post-inc-reg-offset, strb-post-inc-nonpriv-reg-offset
1816 CASE (FRAG_STRB_POST_INC_REG_OFFSET_TRLR):
1818 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
1819 PCADDR pc = abuf->addr;
1822 current_cpu->SETMEMQI (pc, addr, TRUNCSIQI (* FLD (i_rd)));
1823 addr = ADDSI (* FLD (i_rn), offset);
1824 * FLD (i_rn) = addr;
1829 NEXT_INSN (vpc, fragpc);
1831 // ********** used by: str-post-inc-reg-offset, str-post-inc-nonpriv-reg-offset
1833 CASE (FRAG_STR_POST_INC_REG_OFFSET_TRLR):
1835 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
1836 PCADDR pc = abuf->addr;
1839 current_cpu->SETMEMSI (pc, addr, * FLD (i_rd));
1840 addr = ADDSI (* FLD (i_rn), offset);
1841 * FLD (i_rn) = addr;
1846 NEXT_INSN (vpc, fragpc);
1848 // ********** used only by: str-post-inc-imm-offset
1850 CASE (FRAG_STR_POST_INC_IMM_OFFSET_TRLR):
1852 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
1853 PCADDR pc = abuf->addr;
1856 current_cpu->SETMEMSI (pc, addr, * FLD (i_rd));
1857 addr = ADDSI (* FLD (i_rn), offset);
1858 * FLD (i_rn) = addr;
1863 NEXT_INSN (vpc, fragpc);
1865 // ********** used by: ldrb-post-inc-reg-offset, ldrb-post-inc-nonpriv-reg-offset
1867 CASE (FRAG_LDRB_POST_INC_REG_OFFSET_TRLR):
1869 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
1870 PCADDR pc = abuf->addr;
1873 if (EQSI (FLD (f_rd), 15)) {
1874 npc = ZEXTQISI (current_cpu->GETMEMQI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
1876 * FLD (i_rd) = ZEXTQISI (current_cpu->GETMEMQI (pc, addr));
1878 addr = ADDSI (* FLD (i_rn), offset);
1879 * FLD (i_rn) = addr;
1883 pbb_br_status = br_status;
1886 NEXT_INSN (vpc, fragpc);
1888 // ********** used by: strb-post-dec-reg-offset, strb-post-dec-nonpriv-reg-offset
1890 CASE (FRAG_STRB_POST_DEC_REG_OFFSET_TRLR):
1892 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
1893 PCADDR pc = abuf->addr;
1896 current_cpu->SETMEMQI (pc, addr, TRUNCSIQI (* FLD (i_rd)));
1897 addr = SUBSI (* FLD (i_rn), offset);
1898 * FLD (i_rn) = addr;
1903 NEXT_INSN (vpc, fragpc);
1905 // ********** used by: str-post-dec-reg-offset, str-post-dec-nonpriv-reg-offset
1907 CASE (FRAG_STR_POST_DEC_REG_OFFSET_TRLR):
1909 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
1910 PCADDR pc = abuf->addr;
1913 current_cpu->SETMEMSI (pc, addr, * FLD (i_rd));
1914 addr = SUBSI (* FLD (i_rn), offset);
1915 * FLD (i_rn) = addr;
1920 NEXT_INSN (vpc, fragpc);
1922 // ********** used only by: str-post-dec-imm-offset
1924 CASE (FRAG_STR_POST_DEC_IMM_OFFSET_TRLR):
1926 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
1927 PCADDR pc = abuf->addr;
1930 current_cpu->SETMEMSI (pc, addr, * FLD (i_rd));
1931 addr = SUBSI (* FLD (i_rn), offset);
1932 * FLD (i_rn) = addr;
1937 NEXT_INSN (vpc, fragpc);
1939 // ********** used by: ldrb-post-dec-reg-offset, ldrb-post-dec-nonpriv-reg-offset
1941 CASE (FRAG_LDRB_POST_DEC_REG_OFFSET_TRLR):
1943 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
1944 PCADDR pc = abuf->addr;
1947 if (EQSI (FLD (f_rd), 15)) {
1948 npc = ZEXTQISI (current_cpu->GETMEMQI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
1950 * FLD (i_rd) = ZEXTQISI (current_cpu->GETMEMQI (pc, addr));
1952 addr = SUBSI (* FLD (i_rn), offset);
1953 * FLD (i_rn) = addr;
1957 pbb_br_status = br_status;
1960 NEXT_INSN (vpc, fragpc);
1962 // ********** used by:
1964 CASE (FRAG_X_TRAILER):
1966 #define FLD(f) abuf->fields.fmt_empty.f
1967 PCADDR pc = abuf->addr;
1973 NEXT_INSN (vpc, fragpc);
1975 // ********** used only by: x-cond
1977 CASE (FRAG_X_COND_MID):
1981 #define FLD(f) abuf->fields.fmt_empty.f
1982 PCADDR pc = abuf->addr;
1986 // Assume branch not taken.
1987 pbb_br_status = BRANCH_UNTAKEN;
1988 UINT cond_code = abuf->cond;
1989 BI exec_p = current_cpu->eval_cond (cond_code, pc);
1997 NEXT_INSN (vpc, fragpc);
1999 // ********** used only by: x-after
2001 CASE (FRAG_X_AFTER_MID):
2005 #define FLD(f) abuf->fields.fmt_empty.f
2006 PCADDR pc = abuf->addr;
2010 current_cpu->arm_engine.pbb_after (current_cpu, abuf);
2016 NEXT_INSN (vpc, fragpc);
2018 // ********** used only by: x-before
2020 CASE (FRAG_X_BEFORE_MID):
2024 #define FLD(f) abuf->fields.fmt_empty.f
2025 PCADDR pc = abuf->addr;
2029 current_cpu->arm_engine.pbb_before (current_cpu, abuf);
2035 NEXT_INSN (vpc, fragpc);
2037 // ********** used only by: x-cti-chain
2039 CASE (FRAG_X_CTI_CHAIN_MID):
2043 #define FLD(f) abuf->fields.fmt_empty.f
2044 PCADDR pc = abuf->addr;
2048 vpc = current_cpu->arm_engine.pbb_cti_chain (current_cpu, abuf, pbb_br_status, pbb_br_npc);
2049 // If we don't have to give up control, don't.
2050 // Note that we may overrun step_insn_count since we do the test at the
2051 // end of the block. This is defined to be ok.
2052 if (UNLIKELY(current_cpu->stop_after_insns_p (abuf->fields.chain.insn_count)))
2059 NEXT_INSN (vpc, fragpc);
2061 // ********** used only by: x-chain
2063 CASE (FRAG_X_CHAIN_MID):
2067 #define FLD(f) abuf->fields.fmt_empty.f
2068 PCADDR pc = abuf->addr;
2072 vpc = current_cpu->arm_engine.pbb_chain (current_cpu, abuf);
2073 // If we don't have to give up control, don't.
2074 // Note that we may overrun step_insn_count since we do the test at the
2075 // end of the block. This is defined to be ok.
2076 if (UNLIKELY(current_cpu->stop_after_insns_p (abuf->fields.chain.insn_count)))
2083 NEXT_INSN (vpc, fragpc);
2085 // ********** used only by: x-begin
2087 CASE (FRAG_X_BEGIN_MID):
2091 #define FLD(f) abuf->fields.fmt_empty.f
2092 PCADDR pc = abuf->addr;
2096 vpc = current_cpu->arm_pbb_begin (current_cpu->h_pc_get ());
2102 NEXT_INSN (vpc, fragpc);
2104 // ********** used only by: x-invalid
2106 CASE (FRAG_X_INVALID_MID):
2110 #define FLD(f) abuf->fields.fmt_empty.f
2111 PCADDR pc = abuf->addr;
2115 current_cpu->invalid_insn (pc);
2123 NEXT_INSN (vpc, fragpc);
2125 // ********** used only by: b
2131 #define FLD(f) abuf->fields.sfmt_b.f
2132 PCADDR pc = abuf->addr;
2133 br_status = BRANCH_UNTAKEN;
2134 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
2137 npc = FLD (i_offset24); br_status = BRANCH_CACHEABLE;
2141 pbb_br_status = br_status;
2144 NEXT_INSN (vpc, fragpc);
2146 // ********** used only by: bl
2152 #define FLD(f) abuf->fields.sfmt_b.f
2153 PCADDR pc = abuf->addr;
2154 br_status = BRANCH_UNTAKEN;
2155 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
2158 current_cpu->hardware.h_gr[((UINT) 14)] = ANDSI (ADDSI (pc, 4), -4);
2159 npc = FLD (i_offset24); br_status = BRANCH_CACHEABLE;
2163 pbb_br_status = br_status;
2166 NEXT_INSN (vpc, fragpc);
2168 // ********** used only by: bx
2174 #define FLD(f) abuf->fields.sfmt_bx.f
2175 PCADDR pc = abuf->addr;
2176 br_status = BRANCH_UNTAKEN;
2177 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
2180 npc = ANDSI (* FLD (i_bx_rn), 0xfffffffe); br_status = BRANCH_UNCACHEABLE;
2181 if (ANDSI (* FLD (i_bx_rn), 1)) {
2182 current_cpu->h_tbit_set (1);
2187 pbb_br_status = br_status;
2190 NEXT_INSN (vpc, fragpc);
2192 // ********** used only by: ldr-post-dec-imm-offset
2194 CASE (FRAG_LDR_POST_DEC_IMM_OFFSET_MID):
2198 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
2199 PCADDR pc = abuf->addr;
2200 br_status = BRANCH_UNTAKEN;
2201 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
2204 offset = FLD (f_uimm12);
2205 addr = * FLD (i_rn);
2206 if (EQSI (FLD (f_rd), 15)) {
2207 npc = current_cpu->GETMEMSI (pc, addr); br_status = BRANCH_UNCACHEABLE;
2209 * FLD (i_rd) = current_cpu->GETMEMSI (pc, addr);
2211 addr = SUBSI (* FLD (i_rn), offset);
2212 * FLD (i_rn) = addr;
2216 pbb_br_status = br_status;
2219 NEXT_INSN (vpc, fragpc);
2221 // ********** used only by: ldr-post-dec-reg-offset
2223 CASE (FRAG_LDR_POST_DEC_REG_OFFSET_MID):
2227 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
2228 PCADDR pc = abuf->addr;
2229 br_status = BRANCH_UNTAKEN;
2230 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
2233 offset = current_cpu->compute_operand2_immshift (* FLD (i_rm), FLD (f_operand2_shifttype), FLD (f_operand2_shiftimm));
2234 addr = * FLD (i_rn);
2235 if (EQSI (FLD (f_rd), 15)) {
2236 npc = current_cpu->GETMEMSI (pc, addr); br_status = BRANCH_UNCACHEABLE;
2238 * FLD (i_rd) = current_cpu->GETMEMSI (pc, addr);
2240 addr = SUBSI (* FLD (i_rn), offset);
2241 * FLD (i_rn) = addr;
2245 pbb_br_status = br_status;
2248 NEXT_INSN (vpc, fragpc);
2250 // ********** used only by: ldr-post-inc-imm-offset
2252 CASE (FRAG_LDR_POST_INC_IMM_OFFSET_MID):
2254 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
2255 PCADDR pc = abuf->addr;
2258 addr = ADDSI (* FLD (i_rn), offset);
2259 * FLD (i_rn) = addr;
2263 pbb_br_status = br_status;
2266 NEXT_INSN (vpc, fragpc);
2268 // ********** used only by: ldr-post-inc-reg-offset
2270 CASE (FRAG_LDR_POST_INC_REG_OFFSET_MID):
2272 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
2273 PCADDR pc = abuf->addr;
2276 addr = ADDSI (* FLD (i_rn), offset);
2277 * FLD (i_rn) = addr;
2281 pbb_br_status = br_status;
2284 NEXT_INSN (vpc, fragpc);
2286 // ********** used only by: ldr-post-dec-nonpriv-imm-offset
2288 CASE (FRAG_LDR_POST_DEC_NONPRIV_IMM_OFFSET_MID):
2290 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
2291 PCADDR pc = abuf->addr;
2294 addr = SUBSI (* FLD (i_rn), offset);
2295 * FLD (i_rn) = addr;
2299 pbb_br_status = br_status;
2302 NEXT_INSN (vpc, fragpc);
2304 // ********** used only by: ldr-post-dec-nonpriv-reg-offset
2306 CASE (FRAG_LDR_POST_DEC_NONPRIV_REG_OFFSET_MID):
2308 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
2309 PCADDR pc = abuf->addr;
2312 addr = SUBSI (* FLD (i_rn), offset);
2313 * FLD (i_rn) = addr;
2317 pbb_br_status = br_status;
2320 NEXT_INSN (vpc, fragpc);
2322 // ********** used only by: ldr-post-inc-nonpriv-imm-offset
2324 CASE (FRAG_LDR_POST_INC_NONPRIV_IMM_OFFSET_MID):
2328 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
2329 PCADDR pc = abuf->addr;
2330 br_status = BRANCH_UNTAKEN;
2331 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
2334 offset = FLD (f_uimm12);
2335 addr = * FLD (i_rn);
2336 if (EQSI (FLD (f_rd), 15)) {
2337 npc = current_cpu->GETMEMSI (pc, addr); br_status = BRANCH_UNCACHEABLE;
2339 * FLD (i_rd) = current_cpu->GETMEMSI (pc, addr);
2341 addr = ADDSI (* FLD (i_rn), offset);
2342 * FLD (i_rn) = addr;
2346 pbb_br_status = br_status;
2349 NEXT_INSN (vpc, fragpc);
2351 // ********** used only by: ldr-post-inc-nonpriv-reg-offset
2353 CASE (FRAG_LDR_POST_INC_NONPRIV_REG_OFFSET_MID):
2355 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
2356 PCADDR pc = abuf->addr;
2359 if (EQSI (FLD (f_rd), 15)) {
2360 npc = current_cpu->GETMEMSI (pc, addr); br_status = BRANCH_UNCACHEABLE;
2362 * FLD (i_rd) = current_cpu->GETMEMSI (pc, addr);
2364 addr = ADDSI (* FLD (i_rn), offset);
2365 * FLD (i_rn) = addr;
2369 pbb_br_status = br_status;
2372 NEXT_INSN (vpc, fragpc);
2374 // ********** used only by: ldr-pre-dec-imm-offset
2376 CASE (FRAG_LDR_PRE_DEC_IMM_OFFSET_MID):
2380 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
2381 PCADDR pc = abuf->addr;
2382 br_status = BRANCH_UNTAKEN;
2383 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
2386 offset = FLD (f_uimm12);
2387 addr = SUBSI (* FLD (i_rn), offset);
2394 // ********** used only by: ldr-pre-dec-reg-offset
2396 CASE (FRAG_LDR_PRE_DEC_REG_OFFSET_MID):
2398 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
2399 PCADDR pc = abuf->addr;
2402 addr = SUBSI (* FLD (i_rn), offset);
2403 if (EQSI (FLD (f_rd), 15)) {
2404 npc = current_cpu->GETMEMSI (pc, addr); br_status = BRANCH_UNCACHEABLE;
2406 * FLD (i_rd) = current_cpu->GETMEMSI (pc, addr);
2413 pbb_br_status = br_status;
2416 NEXT_INSN (vpc, fragpc);
2418 // ********** used only by: ldr-pre-inc-imm-offset
2420 CASE (FRAG_LDR_PRE_INC_IMM_OFFSET_MID):
2424 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
2425 PCADDR pc = abuf->addr;
2426 br_status = BRANCH_UNTAKEN;
2427 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
2430 offset = FLD (f_uimm12);
2431 addr = ADDSI (* FLD (i_rn), offset);
2432 if (EQSI (FLD (f_rd), 15)) {
2433 npc = current_cpu->GETMEMSI (pc, addr); br_status = BRANCH_UNCACHEABLE;
2435 * FLD (i_rd) = current_cpu->GETMEMSI (pc, addr);
2443 // ********** used only by: ldr-pre-inc-reg-offset
2445 CASE (FRAG_LDR_PRE_INC_REG_OFFSET_MID):
2447 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
2448 PCADDR pc = abuf->addr;
2451 addr = ADDSI (* FLD (i_rn), offset);
2458 // ********** used only by: ldr-pre-dec-wb-imm-offset
2460 CASE (FRAG_LDR_PRE_DEC_WB_IMM_OFFSET_MID):
2464 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
2465 PCADDR pc = abuf->addr;
2466 br_status = BRANCH_UNTAKEN;
2467 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
2470 offset = FLD (f_uimm12);
2471 addr = SUBSI (* FLD (i_rn), offset);
2478 // ********** used only by: ldr-pre-dec-wb-reg-offset
2480 CASE (FRAG_LDR_PRE_DEC_WB_REG_OFFSET_MID):
2482 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
2483 PCADDR pc = abuf->addr;
2486 addr = SUBSI (* FLD (i_rn), offset);
2487 if (EQSI (FLD (f_rd), 15)) {
2488 npc = current_cpu->GETMEMSI (pc, addr); br_status = BRANCH_UNCACHEABLE;
2490 * FLD (i_rd) = current_cpu->GETMEMSI (pc, addr);
2493 * FLD (i_rn) = addr;
2497 pbb_br_status = br_status;
2500 NEXT_INSN (vpc, fragpc);
2502 // ********** used only by: ldr-pre-inc-wb-imm-offset
2504 CASE (FRAG_LDR_PRE_INC_WB_IMM_OFFSET_MID):
2508 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
2509 PCADDR pc = abuf->addr;
2510 br_status = BRANCH_UNTAKEN;
2511 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
2514 offset = FLD (f_uimm12);
2515 addr = ADDSI (* FLD (i_rn), offset);
2516 if (EQSI (FLD (f_rd), 15)) {
2517 npc = current_cpu->GETMEMSI (pc, addr); br_status = BRANCH_UNCACHEABLE;
2519 * FLD (i_rd) = current_cpu->GETMEMSI (pc, addr);
2527 // ********** used only by: ldr-pre-inc-wb-reg-offset
2529 CASE (FRAG_LDR_PRE_INC_WB_REG_OFFSET_MID):
2531 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
2532 PCADDR pc = abuf->addr;
2535 addr = ADDSI (* FLD (i_rn), offset);
2542 // ********** used only by: ldrb-post-dec-imm-offset
2544 CASE (FRAG_LDRB_POST_DEC_IMM_OFFSET_MID):
2548 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
2549 PCADDR pc = abuf->addr;
2550 br_status = BRANCH_UNTAKEN;
2551 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
2554 offset = FLD (f_uimm12);
2555 addr = * FLD (i_rn);
2556 if (EQSI (FLD (f_rd), 15)) {
2557 npc = ZEXTQISI (current_cpu->GETMEMQI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
2559 * FLD (i_rd) = ZEXTQISI (current_cpu->GETMEMQI (pc, addr));
2561 addr = SUBSI (* FLD (i_rn), offset);
2562 * FLD (i_rn) = addr;
2566 pbb_br_status = br_status;
2569 NEXT_INSN (vpc, fragpc);
2571 // ********** used only by: ldrb-post-inc-imm-offset
2573 CASE (FRAG_LDRB_POST_INC_IMM_OFFSET_MID):
2575 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
2576 PCADDR pc = abuf->addr;
2579 addr = ADDSI (* FLD (i_rn), offset);
2580 * FLD (i_rn) = addr;
2584 pbb_br_status = br_status;
2587 NEXT_INSN (vpc, fragpc);
2589 // ********** used only by: ldrb-post-dec-nonpriv-imm-offset
2591 CASE (FRAG_LDRB_POST_DEC_NONPRIV_IMM_OFFSET_MID):
2593 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
2594 PCADDR pc = abuf->addr;
2597 addr = SUBSI (* FLD (i_rn), offset);
2598 * FLD (i_rn) = addr;
2602 pbb_br_status = br_status;
2605 NEXT_INSN (vpc, fragpc);
2607 // ********** used only by: ldrb-post-inc-nonpriv-imm-offset
2609 CASE (FRAG_LDRB_POST_INC_NONPRIV_IMM_OFFSET_MID):
2613 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
2614 PCADDR pc = abuf->addr;
2615 br_status = BRANCH_UNTAKEN;
2616 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
2619 offset = FLD (f_uimm12);
2620 addr = * FLD (i_rn);
2621 if (EQSI (FLD (f_rd), 15)) {
2622 npc = ZEXTQISI (current_cpu->GETMEMQI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
2624 * FLD (i_rd) = ZEXTQISI (current_cpu->GETMEMQI (pc, addr));
2626 addr = ADDSI (* FLD (i_rn), offset);
2627 * FLD (i_rn) = addr;
2631 pbb_br_status = br_status;
2634 NEXT_INSN (vpc, fragpc);
2636 // ********** used only by: ldrb-pre-dec-imm-offset
2638 CASE (FRAG_LDRB_PRE_DEC_IMM_OFFSET_MID):
2642 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
2643 PCADDR pc = abuf->addr;
2644 br_status = BRANCH_UNTAKEN;
2645 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
2648 offset = FLD (f_uimm12);
2649 addr = SUBSI (* FLD (i_rn), offset);
2650 if (EQSI (FLD (f_rd), 15)) {
2651 npc = ZEXTQISI (current_cpu->GETMEMQI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
2653 * FLD (i_rd) = ZEXTQISI (current_cpu->GETMEMQI (pc, addr));
2661 // ********** used only by: ldrb-pre-dec-reg-offset
2663 CASE (FRAG_LDRB_PRE_DEC_REG_OFFSET_MID):
2665 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
2666 PCADDR pc = abuf->addr;
2669 addr = SUBSI (* FLD (i_rn), offset);
2670 if (EQSI (FLD (f_rd), 15)) {
2671 npc = ZEXTQISI (current_cpu->GETMEMQI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
2673 * FLD (i_rd) = ZEXTQISI (current_cpu->GETMEMQI (pc, addr));
2681 // ********** used only by: ldrb-pre-inc-imm-offset
2683 CASE (FRAG_LDRB_PRE_INC_IMM_OFFSET_MID):
2687 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
2688 PCADDR pc = abuf->addr;
2689 br_status = BRANCH_UNTAKEN;
2690 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
2693 offset = FLD (f_uimm12);
2694 addr = ADDSI (* FLD (i_rn), offset);
2695 if (EQSI (FLD (f_rd), 15)) {
2696 npc = ZEXTQISI (current_cpu->GETMEMQI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
2698 * FLD (i_rd) = ZEXTQISI (current_cpu->GETMEMQI (pc, addr));
2706 // ********** used only by: ldrb-pre-inc-reg-offset
2708 CASE (FRAG_LDRB_PRE_INC_REG_OFFSET_MID):
2710 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
2711 PCADDR pc = abuf->addr;
2714 addr = ADDSI (* FLD (i_rn), offset);
2715 if (EQSI (FLD (f_rd), 15)) {
2716 npc = ZEXTQISI (current_cpu->GETMEMQI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
2718 * FLD (i_rd) = ZEXTQISI (current_cpu->GETMEMQI (pc, addr));
2726 // ********** used only by: ldrb-pre-dec-wb-imm-offset
2728 CASE (FRAG_LDRB_PRE_DEC_WB_IMM_OFFSET_MID):
2732 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
2733 PCADDR pc = abuf->addr;
2734 br_status = BRANCH_UNTAKEN;
2735 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
2738 offset = FLD (f_uimm12);
2739 addr = SUBSI (* FLD (i_rn), offset);
2740 if (EQSI (FLD (f_rd), 15)) {
2741 npc = ZEXTQISI (current_cpu->GETMEMQI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
2743 * FLD (i_rd) = ZEXTQISI (current_cpu->GETMEMQI (pc, addr));
2751 // ********** used only by: ldrb-pre-dec-wb-reg-offset
2753 CASE (FRAG_LDRB_PRE_DEC_WB_REG_OFFSET_MID):
2755 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
2756 PCADDR pc = abuf->addr;
2759 addr = SUBSI (* FLD (i_rn), offset);
2760 if (EQSI (FLD (f_rd), 15)) {
2761 npc = ZEXTQISI (current_cpu->GETMEMQI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
2763 * FLD (i_rd) = ZEXTQISI (current_cpu->GETMEMQI (pc, addr));
2771 // ********** used only by: ldrb-pre-inc-wb-imm-offset
2773 CASE (FRAG_LDRB_PRE_INC_WB_IMM_OFFSET_MID):
2777 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
2778 PCADDR pc = abuf->addr;
2779 br_status = BRANCH_UNTAKEN;
2780 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
2783 offset = FLD (f_uimm12);
2784 addr = ADDSI (* FLD (i_rn), offset);
2785 if (EQSI (FLD (f_rd), 15)) {
2786 npc = ZEXTQISI (current_cpu->GETMEMQI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
2788 * FLD (i_rd) = ZEXTQISI (current_cpu->GETMEMQI (pc, addr));
2796 // ********** used only by: ldrb-pre-inc-wb-reg-offset
2798 CASE (FRAG_LDRB_PRE_INC_WB_REG_OFFSET_MID):
2800 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
2801 PCADDR pc = abuf->addr;
2804 addr = ADDSI (* FLD (i_rn), offset);
2805 if (EQSI (FLD (f_rd), 15)) {
2806 npc = ZEXTQISI (current_cpu->GETMEMQI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
2808 * FLD (i_rd) = ZEXTQISI (current_cpu->GETMEMQI (pc, addr));
2816 // ********** used only by: str-post-dec-imm-offset
2818 CASE (FRAG_STR_POST_DEC_IMM_OFFSET_MID):
2822 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
2823 PCADDR pc = abuf->addr;
2824 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
2827 offset = FLD (f_uimm12);
2828 addr = * FLD (i_rn);
2835 // ********** used only by: str-post-inc-imm-offset
2837 CASE (FRAG_STR_POST_INC_IMM_OFFSET_MID):
2841 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
2842 PCADDR pc = abuf->addr;
2843 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
2846 offset = FLD (f_uimm12);
2847 addr = * FLD (i_rn);
2854 // ********** used only by: str-post-dec-nonpriv-imm-offset
2856 CASE (FRAG_STR_POST_DEC_NONPRIV_IMM_OFFSET_MID):
2860 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
2861 PCADDR pc = abuf->addr;
2862 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
2865 offset = FLD (f_uimm12);
2866 addr = * FLD (i_rn);
2867 current_cpu->SETMEMSI (pc, addr, * FLD (i_rd));
2868 addr = SUBSI (* FLD (i_rn), offset);
2869 * FLD (i_rn) = addr;
2874 NEXT_INSN (vpc, fragpc);
2876 // ********** used only by: str-post-inc-nonpriv-imm-offset
2878 CASE (FRAG_STR_POST_INC_NONPRIV_IMM_OFFSET_MID):
2882 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
2883 PCADDR pc = abuf->addr;
2884 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
2887 offset = FLD (f_uimm12);
2888 addr = * FLD (i_rn);
2889 current_cpu->SETMEMSI (pc, addr, * FLD (i_rd));
2890 addr = ADDSI (* FLD (i_rn), offset);
2891 * FLD (i_rn) = addr;
2896 NEXT_INSN (vpc, fragpc);
2898 // ********** used only by: str-pre-dec-imm-offset
2900 CASE (FRAG_STR_PRE_DEC_IMM_OFFSET_MID):
2904 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
2905 PCADDR pc = abuf->addr;
2906 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
2909 offset = FLD (f_uimm12);
2910 addr = SUBSI (* FLD (i_rn), offset);
2911 current_cpu->SETMEMSI (pc, addr, * FLD (i_rd));
2918 // ********** used only by: str-pre-dec-reg-offset
2920 CASE (FRAG_STR_PRE_DEC_REG_OFFSET_MID):
2922 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
2923 PCADDR pc = abuf->addr;
2926 addr = SUBSI (* FLD (i_rn), offset);
2927 current_cpu->SETMEMSI (pc, addr, * FLD (i_rd));
2934 // ********** used only by: str-pre-inc-imm-offset
2936 CASE (FRAG_STR_PRE_INC_IMM_OFFSET_MID):
2940 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
2941 PCADDR pc = abuf->addr;
2942 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
2945 offset = FLD (f_uimm12);
2946 addr = ADDSI (* FLD (i_rn), offset);
2947 current_cpu->SETMEMSI (pc, addr, * FLD (i_rd));
2954 // ********** used only by: str-pre-inc-reg-offset
2956 CASE (FRAG_STR_PRE_INC_REG_OFFSET_MID):
2958 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
2959 PCADDR pc = abuf->addr;
2962 addr = ADDSI (* FLD (i_rn), offset);
2963 current_cpu->SETMEMSI (pc, addr, * FLD (i_rd));
2970 // ********** used only by: str-pre-dec-wb-imm-offset
2972 CASE (FRAG_STR_PRE_DEC_WB_IMM_OFFSET_MID):
2976 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
2977 PCADDR pc = abuf->addr;
2978 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
2981 offset = FLD (f_uimm12);
2982 addr = SUBSI (* FLD (i_rn), offset);
2983 current_cpu->SETMEMSI (pc, addr, * FLD (i_rd));
2990 // ********** used only by: str-pre-dec-wb-reg-offset
2992 CASE (FRAG_STR_PRE_DEC_WB_REG_OFFSET_MID):
2994 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
2995 PCADDR pc = abuf->addr;
2998 addr = SUBSI (* FLD (i_rn), offset);
2999 current_cpu->SETMEMSI (pc, addr, * FLD (i_rd));
3006 // ********** used only by: str-pre-inc-wb-imm-offset
3008 CASE (FRAG_STR_PRE_INC_WB_IMM_OFFSET_MID):
3012 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
3013 PCADDR pc = abuf->addr;
3014 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3017 offset = FLD (f_uimm12);
3018 addr = ADDSI (* FLD (i_rn), offset);
3019 current_cpu->SETMEMSI (pc, addr, * FLD (i_rd));
3026 // ********** used only by: str-pre-inc-wb-reg-offset
3028 CASE (FRAG_STR_PRE_INC_WB_REG_OFFSET_MID):
3030 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
3031 PCADDR pc = abuf->addr;
3034 addr = ADDSI (* FLD (i_rn), offset);
3035 current_cpu->SETMEMSI (pc, addr, * FLD (i_rd));
3042 // ********** used only by: strb-post-dec-imm-offset
3044 CASE (FRAG_STRB_POST_DEC_IMM_OFFSET_MID):
3048 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
3049 PCADDR pc = abuf->addr;
3050 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3053 offset = FLD (f_uimm12);
3054 addr = * FLD (i_rn);
3055 current_cpu->SETMEMQI (pc, addr, TRUNCSIQI (* FLD (i_rd)));
3056 addr = SUBSI (* FLD (i_rn), offset);
3057 * FLD (i_rn) = addr;
3062 NEXT_INSN (vpc, fragpc);
3064 // ********** used only by: strb-post-inc-imm-offset
3066 CASE (FRAG_STRB_POST_INC_IMM_OFFSET_MID):
3068 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
3069 PCADDR pc = abuf->addr;
3072 addr = ADDSI (* FLD (i_rn), offset);
3073 * FLD (i_rn) = addr;
3078 NEXT_INSN (vpc, fragpc);
3080 // ********** used only by: strb-post-dec-nonpriv-imm-offset
3082 CASE (FRAG_STRB_POST_DEC_NONPRIV_IMM_OFFSET_MID):
3084 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
3085 PCADDR pc = abuf->addr;
3088 addr = SUBSI (* FLD (i_rn), offset);
3089 * FLD (i_rn) = addr;
3094 NEXT_INSN (vpc, fragpc);
3096 // ********** used only by: strb-post-inc-nonpriv-imm-offset
3098 CASE (FRAG_STRB_POST_INC_NONPRIV_IMM_OFFSET_MID):
3102 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
3103 PCADDR pc = abuf->addr;
3104 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3107 offset = FLD (f_uimm12);
3108 addr = * FLD (i_rn);
3109 current_cpu->SETMEMQI (pc, addr, TRUNCSIQI (* FLD (i_rd)));
3110 addr = ADDSI (* FLD (i_rn), offset);
3111 * FLD (i_rn) = addr;
3116 NEXT_INSN (vpc, fragpc);
3118 // ********** used only by: strb-post-inc-nonpriv-reg-offset
3120 CASE (FRAG_STRB_POST_INC_NONPRIV_REG_OFFSET_MID):
3122 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
3123 PCADDR pc = abuf->addr;
3126 addr = * FLD (i_rn);
3133 // ********** used only by: strb-pre-dec-imm-offset
3135 CASE (FRAG_STRB_PRE_DEC_IMM_OFFSET_MID):
3139 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
3140 PCADDR pc = abuf->addr;
3141 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3144 offset = FLD (f_uimm12);
3145 addr = SUBSI (* FLD (i_rn), offset);
3146 current_cpu->SETMEMQI (pc, addr, TRUNCSIQI (* FLD (i_rd)));
3153 // ********** used only by: strb-pre-dec-reg-offset
3155 CASE (FRAG_STRB_PRE_DEC_REG_OFFSET_MID):
3157 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
3158 PCADDR pc = abuf->addr;
3161 addr = SUBSI (* FLD (i_rn), offset);
3162 current_cpu->SETMEMQI (pc, addr, TRUNCSIQI (* FLD (i_rd)));
3169 // ********** used only by: strb-pre-inc-imm-offset
3171 CASE (FRAG_STRB_PRE_INC_IMM_OFFSET_MID):
3175 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
3176 PCADDR pc = abuf->addr;
3177 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3180 offset = FLD (f_uimm12);
3181 addr = ADDSI (* FLD (i_rn), offset);
3182 current_cpu->SETMEMQI (pc, addr, TRUNCSIQI (* FLD (i_rd)));
3189 // ********** used only by: strb-pre-inc-reg-offset
3191 CASE (FRAG_STRB_PRE_INC_REG_OFFSET_MID):
3195 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
3196 PCADDR pc = abuf->addr;
3197 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3200 offset = current_cpu->compute_operand2_immshift (* FLD (i_rm), FLD (f_operand2_shifttype), FLD (f_operand2_shiftimm));
3201 addr = ADDSI (* FLD (i_rn), offset);
3202 current_cpu->SETMEMQI (pc, addr, TRUNCSIQI (* FLD (i_rd)));
3209 // ********** used only by: strb-pre-dec-wb-imm-offset
3211 CASE (FRAG_STRB_PRE_DEC_WB_IMM_OFFSET_MID):
3215 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
3216 PCADDR pc = abuf->addr;
3217 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3220 offset = FLD (f_uimm12);
3221 addr = SUBSI (* FLD (i_rn), offset);
3222 current_cpu->SETMEMQI (pc, addr, TRUNCSIQI (* FLD (i_rd)));
3229 // ********** used only by: strb-pre-dec-wb-reg-offset
3231 CASE (FRAG_STRB_PRE_DEC_WB_REG_OFFSET_MID):
3233 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
3234 PCADDR pc = abuf->addr;
3237 addr = SUBSI (* FLD (i_rn), offset);
3238 current_cpu->SETMEMQI (pc, addr, TRUNCSIQI (* FLD (i_rd)));
3245 // ********** used only by: strb-pre-inc-wb-imm-offset
3247 CASE (FRAG_STRB_PRE_INC_WB_IMM_OFFSET_MID):
3251 #define FLD(f) abuf->fields.sfmt_ldr_post_dec_imm_offset.f
3252 PCADDR pc = abuf->addr;
3253 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3256 offset = FLD (f_uimm12);
3257 addr = ADDSI (* FLD (i_rn), offset);
3258 current_cpu->SETMEMQI (pc, addr, TRUNCSIQI (* FLD (i_rd)));
3265 // ********** used only by: strb-pre-inc-wb-reg-offset
3267 CASE (FRAG_STRB_PRE_INC_WB_REG_OFFSET_MID):
3269 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
3270 PCADDR pc = abuf->addr;
3273 addr = ADDSI (* FLD (i_rn), offset);
3274 current_cpu->SETMEMQI (pc, addr, TRUNCSIQI (* FLD (i_rd)));
3281 // ********** used only by: strh-pre-dec-imm-offset
3283 CASE (FRAG_STRH_PRE_DEC_IMM_OFFSET_MID):
3287 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
3288 PCADDR pc = abuf->addr;
3289 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3292 offset = FLD (i_hdt_offset8);
3293 addr = SUBSI (* FLD (i_rn), offset);
3294 current_cpu->SETMEMHI (pc, addr, TRUNCSIHI (* FLD (i_rd)));
3301 // ********** used only by: strh-pre-dec-reg-offset
3303 CASE (FRAG_STRH_PRE_DEC_REG_OFFSET_MID):
3307 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
3308 PCADDR pc = abuf->addr;
3309 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3312 offset = * FLD (i_rm);
3313 addr = SUBSI (* FLD (i_rn), offset);
3314 current_cpu->SETMEMHI (pc, addr, TRUNCSIHI (* FLD (i_rd)));
3321 // ********** used only by: strh-pre-inc-imm-offset
3323 CASE (FRAG_STRH_PRE_INC_IMM_OFFSET_MID):
3327 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
3328 PCADDR pc = abuf->addr;
3329 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3332 offset = FLD (i_hdt_offset8);
3333 addr = ADDSI (* FLD (i_rn), offset);
3334 current_cpu->SETMEMHI (pc, addr, TRUNCSIHI (* FLD (i_rd)));
3341 // ********** used only by: strh-pre-inc-reg-offset
3343 CASE (FRAG_STRH_PRE_INC_REG_OFFSET_MID):
3347 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
3348 PCADDR pc = abuf->addr;
3349 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3352 offset = * FLD (i_rm);
3353 addr = ADDSI (* FLD (i_rn), offset);
3354 current_cpu->SETMEMHI (pc, addr, TRUNCSIHI (* FLD (i_rd)));
3361 // ********** used only by: strh-pre-dec-wb-imm-offset
3363 CASE (FRAG_STRH_PRE_DEC_WB_IMM_OFFSET_MID):
3367 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
3368 PCADDR pc = abuf->addr;
3369 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3372 offset = FLD (i_hdt_offset8);
3373 addr = SUBSI (* FLD (i_rn), offset);
3374 current_cpu->SETMEMHI (pc, addr, TRUNCSIHI (* FLD (i_rd)));
3381 // ********** used only by: strh-pre-dec-wb-reg-offset
3383 CASE (FRAG_STRH_PRE_DEC_WB_REG_OFFSET_MID):
3387 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
3388 PCADDR pc = abuf->addr;
3389 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3392 offset = * FLD (i_rm);
3393 addr = SUBSI (* FLD (i_rn), offset);
3394 current_cpu->SETMEMHI (pc, addr, TRUNCSIHI (* FLD (i_rd)));
3401 // ********** used only by: strh-pre-inc-wb-imm-offset
3403 CASE (FRAG_STRH_PRE_INC_WB_IMM_OFFSET_MID):
3407 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
3408 PCADDR pc = abuf->addr;
3409 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3412 offset = FLD (i_hdt_offset8);
3413 addr = ADDSI (* FLD (i_rn), offset);
3414 current_cpu->SETMEMHI (pc, addr, TRUNCSIHI (* FLD (i_rd)));
3421 // ********** used only by: strh-pre-inc-wb-reg-offset
3423 CASE (FRAG_STRH_PRE_INC_WB_REG_OFFSET_MID):
3427 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
3428 PCADDR pc = abuf->addr;
3429 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3432 offset = * FLD (i_rm);
3433 addr = ADDSI (* FLD (i_rn), offset);
3434 current_cpu->SETMEMHI (pc, addr, TRUNCSIHI (* FLD (i_rd)));
3441 // ********** used only by: strh-post-dec-imm-offset
3443 CASE (FRAG_STRH_POST_DEC_IMM_OFFSET_MID):
3447 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
3448 PCADDR pc = abuf->addr;
3449 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3452 offset = FLD (i_hdt_offset8);
3453 addr = * FLD (i_rn);
3454 current_cpu->SETMEMHI (pc, addr, TRUNCSIHI (* FLD (i_rd)));
3455 addr = SUBSI (* FLD (i_rn), offset);
3456 * FLD (i_rn) = addr;
3461 NEXT_INSN (vpc, fragpc);
3463 // ********** used only by: strh-post-dec-reg-offset
3465 CASE (FRAG_STRH_POST_DEC_REG_OFFSET_MID):
3469 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
3470 PCADDR pc = abuf->addr;
3471 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3474 offset = * FLD (i_rm);
3475 addr = * FLD (i_rn);
3476 current_cpu->SETMEMHI (pc, addr, TRUNCSIHI (* FLD (i_rd)));
3477 addr = SUBSI (* FLD (i_rn), offset);
3478 * FLD (i_rn) = addr;
3483 NEXT_INSN (vpc, fragpc);
3485 // ********** used only by: strh-post-inc-imm-offset
3487 CASE (FRAG_STRH_POST_INC_IMM_OFFSET_MID):
3491 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
3492 PCADDR pc = abuf->addr;
3493 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3496 offset = FLD (i_hdt_offset8);
3497 addr = * FLD (i_rn);
3498 current_cpu->SETMEMHI (pc, addr, TRUNCSIHI (* FLD (i_rd)));
3499 addr = ADDSI (* FLD (i_rn), offset);
3500 * FLD (i_rn) = addr;
3505 NEXT_INSN (vpc, fragpc);
3507 // ********** used only by: strh-post-inc-reg-offset
3509 CASE (FRAG_STRH_POST_INC_REG_OFFSET_MID):
3513 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
3514 PCADDR pc = abuf->addr;
3515 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3518 offset = * FLD (i_rm);
3519 addr = * FLD (i_rn);
3520 current_cpu->SETMEMHI (pc, addr, TRUNCSIHI (* FLD (i_rd)));
3521 addr = ADDSI (* FLD (i_rn), offset);
3522 * FLD (i_rn) = addr;
3527 NEXT_INSN (vpc, fragpc);
3529 // ********** used only by: ldrsb-pre-dec-imm-offset
3531 CASE (FRAG_LDRSB_PRE_DEC_IMM_OFFSET_MID):
3535 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
3536 PCADDR pc = abuf->addr;
3537 br_status = BRANCH_UNTAKEN;
3538 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3541 offset = FLD (i_hdt_offset8);
3542 addr = SUBSI (* FLD (i_rn), offset);
3543 if (EQSI (FLD (f_rd), 15)) {
3544 npc = EXTQISI (current_cpu->GETMEMQI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
3546 * FLD (i_rd) = EXTQISI (current_cpu->GETMEMQI (pc, addr));
3554 // ********** used only by: ldrsb-pre-dec-reg-offset
3556 CASE (FRAG_LDRSB_PRE_DEC_REG_OFFSET_MID):
3560 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
3561 PCADDR pc = abuf->addr;
3562 br_status = BRANCH_UNTAKEN;
3563 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3566 offset = * FLD (i_rm);
3567 addr = SUBSI (* FLD (i_rn), offset);
3568 if (EQSI (FLD (f_rd), 15)) {
3569 npc = EXTQISI (current_cpu->GETMEMQI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
3571 * FLD (i_rd) = EXTQISI (current_cpu->GETMEMQI (pc, addr));
3579 // ********** used only by: ldrsb-pre-inc-imm-offset
3581 CASE (FRAG_LDRSB_PRE_INC_IMM_OFFSET_MID):
3585 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
3586 PCADDR pc = abuf->addr;
3587 br_status = BRANCH_UNTAKEN;
3588 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3591 offset = FLD (i_hdt_offset8);
3592 addr = ADDSI (* FLD (i_rn), offset);
3593 if (EQSI (FLD (f_rd), 15)) {
3594 npc = EXTQISI (current_cpu->GETMEMQI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
3596 * FLD (i_rd) = EXTQISI (current_cpu->GETMEMQI (pc, addr));
3604 // ********** used only by: ldrsb-pre-inc-reg-offset
3606 CASE (FRAG_LDRSB_PRE_INC_REG_OFFSET_MID):
3610 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
3611 PCADDR pc = abuf->addr;
3612 br_status = BRANCH_UNTAKEN;
3613 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3616 offset = * FLD (i_rm);
3617 addr = ADDSI (* FLD (i_rn), offset);
3618 if (EQSI (FLD (f_rd), 15)) {
3619 npc = EXTQISI (current_cpu->GETMEMQI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
3621 * FLD (i_rd) = EXTQISI (current_cpu->GETMEMQI (pc, addr));
3629 // ********** used only by: ldrsb-pre-dec-wb-imm-offset
3631 CASE (FRAG_LDRSB_PRE_DEC_WB_IMM_OFFSET_MID):
3635 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
3636 PCADDR pc = abuf->addr;
3637 br_status = BRANCH_UNTAKEN;
3638 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3641 offset = FLD (i_hdt_offset8);
3642 addr = SUBSI (* FLD (i_rn), offset);
3643 if (EQSI (FLD (f_rd), 15)) {
3644 npc = EXTQISI (current_cpu->GETMEMQI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
3646 * FLD (i_rd) = EXTQISI (current_cpu->GETMEMQI (pc, addr));
3654 // ********** used only by: ldrsb-pre-dec-wb-reg-offset
3656 CASE (FRAG_LDRSB_PRE_DEC_WB_REG_OFFSET_MID):
3660 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
3661 PCADDR pc = abuf->addr;
3662 br_status = BRANCH_UNTAKEN;
3663 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3666 offset = * FLD (i_rm);
3667 addr = SUBSI (* FLD (i_rn), offset);
3668 if (EQSI (FLD (f_rd), 15)) {
3669 npc = EXTQISI (current_cpu->GETMEMQI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
3671 * FLD (i_rd) = EXTQISI (current_cpu->GETMEMQI (pc, addr));
3679 // ********** used only by: ldrsb-pre-inc-wb-imm-offset
3681 CASE (FRAG_LDRSB_PRE_INC_WB_IMM_OFFSET_MID):
3685 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
3686 PCADDR pc = abuf->addr;
3687 br_status = BRANCH_UNTAKEN;
3688 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3691 offset = FLD (i_hdt_offset8);
3692 addr = ADDSI (* FLD (i_rn), offset);
3693 if (EQSI (FLD (f_rd), 15)) {
3694 npc = EXTQISI (current_cpu->GETMEMQI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
3696 * FLD (i_rd) = EXTQISI (current_cpu->GETMEMQI (pc, addr));
3704 // ********** used only by: ldrsb-pre-inc-wb-reg-offset
3706 CASE (FRAG_LDRSB_PRE_INC_WB_REG_OFFSET_MID):
3710 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
3711 PCADDR pc = abuf->addr;
3712 br_status = BRANCH_UNTAKEN;
3713 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3716 offset = * FLD (i_rm);
3717 addr = ADDSI (* FLD (i_rn), offset);
3718 if (EQSI (FLD (f_rd), 15)) {
3719 npc = EXTQISI (current_cpu->GETMEMQI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
3721 * FLD (i_rd) = EXTQISI (current_cpu->GETMEMQI (pc, addr));
3729 // ********** used only by: ldrsb-post-dec-imm-offset
3731 CASE (FRAG_LDRSB_POST_DEC_IMM_OFFSET_MID):
3735 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
3736 PCADDR pc = abuf->addr;
3737 br_status = BRANCH_UNTAKEN;
3738 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3741 offset = FLD (i_hdt_offset8);
3742 addr = * FLD (i_rn);
3743 if (EQSI (FLD (f_rd), 15)) {
3744 npc = EXTQISI (current_cpu->GETMEMQI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
3746 * FLD (i_rd) = EXTQISI (current_cpu->GETMEMQI (pc, addr));
3748 addr = SUBSI (* FLD (i_rn), offset);
3749 * FLD (i_rn) = addr;
3753 pbb_br_status = br_status;
3756 NEXT_INSN (vpc, fragpc);
3758 // ********** used only by: ldrsb-post-dec-reg-offset
3760 CASE (FRAG_LDRSB_POST_DEC_REG_OFFSET_MID):
3764 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
3765 PCADDR pc = abuf->addr;
3766 br_status = BRANCH_UNTAKEN;
3767 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3770 offset = * FLD (i_rm);
3771 addr = * FLD (i_rn);
3772 if (EQSI (FLD (f_rd), 15)) {
3773 npc = EXTQISI (current_cpu->GETMEMQI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
3775 * FLD (i_rd) = EXTQISI (current_cpu->GETMEMQI (pc, addr));
3777 addr = SUBSI (* FLD (i_rn), offset);
3778 * FLD (i_rn) = addr;
3782 pbb_br_status = br_status;
3785 NEXT_INSN (vpc, fragpc);
3787 // ********** used only by: ldrsb-post-inc-imm-offset
3789 CASE (FRAG_LDRSB_POST_INC_IMM_OFFSET_MID):
3793 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
3794 PCADDR pc = abuf->addr;
3795 br_status = BRANCH_UNTAKEN;
3796 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3799 offset = FLD (i_hdt_offset8);
3800 addr = * FLD (i_rn);
3801 if (EQSI (FLD (f_rd), 15)) {
3802 npc = EXTQISI (current_cpu->GETMEMQI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
3804 * FLD (i_rd) = EXTQISI (current_cpu->GETMEMQI (pc, addr));
3806 addr = ADDSI (* FLD (i_rn), offset);
3807 * FLD (i_rn) = addr;
3811 pbb_br_status = br_status;
3814 NEXT_INSN (vpc, fragpc);
3816 // ********** used only by: ldrsb-post-inc-reg-offset
3818 CASE (FRAG_LDRSB_POST_INC_REG_OFFSET_MID):
3822 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
3823 PCADDR pc = abuf->addr;
3824 br_status = BRANCH_UNTAKEN;
3825 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3828 offset = * FLD (i_rm);
3829 addr = * FLD (i_rn);
3830 if (EQSI (FLD (f_rd), 15)) {
3831 npc = EXTQISI (current_cpu->GETMEMQI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
3833 * FLD (i_rd) = EXTQISI (current_cpu->GETMEMQI (pc, addr));
3835 addr = ADDSI (* FLD (i_rn), offset);
3836 * FLD (i_rn) = addr;
3840 pbb_br_status = br_status;
3843 NEXT_INSN (vpc, fragpc);
3845 // ********** used only by: ldrh-pre-dec-imm-offset
3847 CASE (FRAG_LDRH_PRE_DEC_IMM_OFFSET_MID):
3851 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
3852 PCADDR pc = abuf->addr;
3853 br_status = BRANCH_UNTAKEN;
3854 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3857 offset = FLD (i_hdt_offset8);
3858 addr = SUBSI (* FLD (i_rn), offset);
3859 if (EQSI (FLD (f_rd), 15)) {
3860 npc = ZEXTHISI (current_cpu->GETMEMHI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
3862 * FLD (i_rd) = ZEXTHISI (current_cpu->GETMEMHI (pc, addr));
3870 // ********** used only by: ldrh-pre-dec-reg-offset
3872 CASE (FRAG_LDRH_PRE_DEC_REG_OFFSET_MID):
3876 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
3877 PCADDR pc = abuf->addr;
3878 br_status = BRANCH_UNTAKEN;
3879 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3882 offset = * FLD (i_rm);
3883 addr = SUBSI (* FLD (i_rn), offset);
3884 if (EQSI (FLD (f_rd), 15)) {
3885 npc = ZEXTHISI (current_cpu->GETMEMHI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
3887 * FLD (i_rd) = ZEXTHISI (current_cpu->GETMEMHI (pc, addr));
3895 // ********** used only by: ldrh-pre-inc-imm-offset
3897 CASE (FRAG_LDRH_PRE_INC_IMM_OFFSET_MID):
3901 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
3902 PCADDR pc = abuf->addr;
3903 br_status = BRANCH_UNTAKEN;
3904 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3907 offset = FLD (i_hdt_offset8);
3908 addr = ADDSI (* FLD (i_rn), offset);
3909 if (EQSI (FLD (f_rd), 15)) {
3910 npc = ZEXTHISI (current_cpu->GETMEMHI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
3912 * FLD (i_rd) = ZEXTHISI (current_cpu->GETMEMHI (pc, addr));
3920 // ********** used only by: ldrh-pre-inc-reg-offset
3922 CASE (FRAG_LDRH_PRE_INC_REG_OFFSET_MID):
3926 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
3927 PCADDR pc = abuf->addr;
3928 br_status = BRANCH_UNTAKEN;
3929 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3932 offset = * FLD (i_rm);
3933 addr = ADDSI (* FLD (i_rn), offset);
3934 if (EQSI (FLD (f_rd), 15)) {
3935 npc = ZEXTHISI (current_cpu->GETMEMHI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
3937 * FLD (i_rd) = ZEXTHISI (current_cpu->GETMEMHI (pc, addr));
3945 // ********** used only by: ldrh-pre-dec-wb-imm-offset
3947 CASE (FRAG_LDRH_PRE_DEC_WB_IMM_OFFSET_MID):
3951 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
3952 PCADDR pc = abuf->addr;
3953 br_status = BRANCH_UNTAKEN;
3954 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3957 offset = FLD (i_hdt_offset8);
3958 addr = SUBSI (* FLD (i_rn), offset);
3959 if (EQSI (FLD (f_rd), 15)) {
3960 npc = ZEXTHISI (current_cpu->GETMEMHI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
3962 * FLD (i_rd) = ZEXTHISI (current_cpu->GETMEMHI (pc, addr));
3970 // ********** used only by: ldrh-pre-dec-wb-reg-offset
3972 CASE (FRAG_LDRH_PRE_DEC_WB_REG_OFFSET_MID):
3976 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
3977 PCADDR pc = abuf->addr;
3978 br_status = BRANCH_UNTAKEN;
3979 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
3982 offset = * FLD (i_rm);
3983 addr = SUBSI (* FLD (i_rn), offset);
3984 if (EQSI (FLD (f_rd), 15)) {
3985 npc = ZEXTHISI (current_cpu->GETMEMHI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
3987 * FLD (i_rd) = ZEXTHISI (current_cpu->GETMEMHI (pc, addr));
3995 // ********** used only by: ldrh-pre-inc-wb-imm-offset
3997 CASE (FRAG_LDRH_PRE_INC_WB_IMM_OFFSET_MID):
4001 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
4002 PCADDR pc = abuf->addr;
4003 br_status = BRANCH_UNTAKEN;
4004 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4007 offset = FLD (i_hdt_offset8);
4008 addr = ADDSI (* FLD (i_rn), offset);
4009 if (EQSI (FLD (f_rd), 15)) {
4010 npc = ZEXTHISI (current_cpu->GETMEMHI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
4012 * FLD (i_rd) = ZEXTHISI (current_cpu->GETMEMHI (pc, addr));
4020 // ********** used only by: ldrh-pre-inc-wb-reg-offset
4022 CASE (FRAG_LDRH_PRE_INC_WB_REG_OFFSET_MID):
4026 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
4027 PCADDR pc = abuf->addr;
4028 br_status = BRANCH_UNTAKEN;
4029 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4032 offset = * FLD (i_rm);
4033 addr = ADDSI (* FLD (i_rn), offset);
4034 if (EQSI (FLD (f_rd), 15)) {
4035 npc = ZEXTHISI (current_cpu->GETMEMHI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
4037 * FLD (i_rd) = ZEXTHISI (current_cpu->GETMEMHI (pc, addr));
4045 // ********** used only by: ldrh-post-dec-imm-offset
4047 CASE (FRAG_LDRH_POST_DEC_IMM_OFFSET_MID):
4051 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
4052 PCADDR pc = abuf->addr;
4053 br_status = BRANCH_UNTAKEN;
4054 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4057 offset = FLD (i_hdt_offset8);
4058 addr = * FLD (i_rn);
4059 if (EQSI (FLD (f_rd), 15)) {
4060 npc = ZEXTHISI (current_cpu->GETMEMHI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
4062 * FLD (i_rd) = ZEXTHISI (current_cpu->GETMEMHI (pc, addr));
4064 addr = SUBSI (* FLD (i_rn), offset);
4065 * FLD (i_rn) = addr;
4069 pbb_br_status = br_status;
4072 NEXT_INSN (vpc, fragpc);
4074 // ********** used only by: ldrh-post-dec-reg-offset
4076 CASE (FRAG_LDRH_POST_DEC_REG_OFFSET_MID):
4080 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
4081 PCADDR pc = abuf->addr;
4082 br_status = BRANCH_UNTAKEN;
4083 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4086 offset = * FLD (i_rm);
4087 addr = * FLD (i_rn);
4088 if (EQSI (FLD (f_rd), 15)) {
4089 npc = ZEXTHISI (current_cpu->GETMEMHI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
4091 * FLD (i_rd) = ZEXTHISI (current_cpu->GETMEMHI (pc, addr));
4093 addr = SUBSI (* FLD (i_rn), offset);
4094 * FLD (i_rn) = addr;
4098 pbb_br_status = br_status;
4101 NEXT_INSN (vpc, fragpc);
4103 // ********** used only by: ldrh-post-inc-imm-offset
4105 CASE (FRAG_LDRH_POST_INC_IMM_OFFSET_MID):
4109 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
4110 PCADDR pc = abuf->addr;
4111 br_status = BRANCH_UNTAKEN;
4112 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4115 offset = FLD (i_hdt_offset8);
4116 addr = * FLD (i_rn);
4117 if (EQSI (FLD (f_rd), 15)) {
4118 npc = ZEXTHISI (current_cpu->GETMEMHI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
4120 * FLD (i_rd) = ZEXTHISI (current_cpu->GETMEMHI (pc, addr));
4122 addr = ADDSI (* FLD (i_rn), offset);
4123 * FLD (i_rn) = addr;
4127 pbb_br_status = br_status;
4130 NEXT_INSN (vpc, fragpc);
4132 // ********** used only by: ldrh-post-inc-reg-offset
4134 CASE (FRAG_LDRH_POST_INC_REG_OFFSET_MID):
4138 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
4139 PCADDR pc = abuf->addr;
4140 br_status = BRANCH_UNTAKEN;
4141 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4144 offset = * FLD (i_rm);
4145 addr = * FLD (i_rn);
4146 if (EQSI (FLD (f_rd), 15)) {
4147 npc = ZEXTHISI (current_cpu->GETMEMHI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
4149 * FLD (i_rd) = ZEXTHISI (current_cpu->GETMEMHI (pc, addr));
4151 addr = ADDSI (* FLD (i_rn), offset);
4152 * FLD (i_rn) = addr;
4156 pbb_br_status = br_status;
4159 NEXT_INSN (vpc, fragpc);
4161 // ********** used only by: ldrsh-pre-dec-imm-offset
4163 CASE (FRAG_LDRSH_PRE_DEC_IMM_OFFSET_MID):
4167 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
4168 PCADDR pc = abuf->addr;
4169 br_status = BRANCH_UNTAKEN;
4170 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4173 offset = FLD (i_hdt_offset8);
4174 addr = SUBSI (* FLD (i_rn), offset);
4175 if (EQSI (FLD (f_rd), 15)) {
4176 npc = EXTHISI (current_cpu->GETMEMHI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
4178 * FLD (i_rd) = EXTHISI (current_cpu->GETMEMHI (pc, addr));
4186 // ********** used only by: ldrsh-pre-dec-reg-offset
4188 CASE (FRAG_LDRSH_PRE_DEC_REG_OFFSET_MID):
4192 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
4193 PCADDR pc = abuf->addr;
4194 br_status = BRANCH_UNTAKEN;
4195 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4198 offset = * FLD (i_rm);
4199 addr = SUBSI (* FLD (i_rn), offset);
4200 if (EQSI (FLD (f_rd), 15)) {
4201 npc = EXTHISI (current_cpu->GETMEMHI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
4203 * FLD (i_rd) = EXTHISI (current_cpu->GETMEMHI (pc, addr));
4211 // ********** used only by: ldrsh-pre-inc-imm-offset
4213 CASE (FRAG_LDRSH_PRE_INC_IMM_OFFSET_MID):
4217 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
4218 PCADDR pc = abuf->addr;
4219 br_status = BRANCH_UNTAKEN;
4220 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4223 offset = FLD (i_hdt_offset8);
4224 addr = ADDSI (* FLD (i_rn), offset);
4225 if (EQSI (FLD (f_rd), 15)) {
4226 npc = EXTHISI (current_cpu->GETMEMHI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
4228 * FLD (i_rd) = EXTHISI (current_cpu->GETMEMHI (pc, addr));
4236 // ********** used only by: ldrsh-pre-inc-reg-offset
4238 CASE (FRAG_LDRSH_PRE_INC_REG_OFFSET_MID):
4242 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
4243 PCADDR pc = abuf->addr;
4244 br_status = BRANCH_UNTAKEN;
4245 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4248 offset = * FLD (i_rm);
4249 addr = ADDSI (* FLD (i_rn), offset);
4250 if (EQSI (FLD (f_rd), 15)) {
4251 npc = EXTHISI (current_cpu->GETMEMHI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
4253 * FLD (i_rd) = EXTHISI (current_cpu->GETMEMHI (pc, addr));
4260 pbb_br_status = br_status;
4263 NEXT_INSN (vpc, fragpc);
4265 // ********** used only by: ldrsh-pre-dec-wb-imm-offset
4267 CASE (FRAG_LDRSH_PRE_DEC_WB_IMM_OFFSET_MID):
4271 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
4272 PCADDR pc = abuf->addr;
4273 br_status = BRANCH_UNTAKEN;
4274 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4277 offset = FLD (i_hdt_offset8);
4278 addr = SUBSI (* FLD (i_rn), offset);
4279 if (EQSI (FLD (f_rd), 15)) {
4280 npc = EXTHISI (current_cpu->GETMEMHI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
4282 * FLD (i_rd) = EXTHISI (current_cpu->GETMEMHI (pc, addr));
4290 // ********** used only by: ldrsh-pre-dec-wb-reg-offset
4292 CASE (FRAG_LDRSH_PRE_DEC_WB_REG_OFFSET_MID):
4296 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
4297 PCADDR pc = abuf->addr;
4298 br_status = BRANCH_UNTAKEN;
4299 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4302 offset = * FLD (i_rm);
4303 addr = SUBSI (* FLD (i_rn), offset);
4304 if (EQSI (FLD (f_rd), 15)) {
4305 npc = EXTHISI (current_cpu->GETMEMHI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
4307 * FLD (i_rd) = EXTHISI (current_cpu->GETMEMHI (pc, addr));
4315 // ********** used only by: ldrsh-pre-inc-wb-imm-offset
4317 CASE (FRAG_LDRSH_PRE_INC_WB_IMM_OFFSET_MID):
4321 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
4322 PCADDR pc = abuf->addr;
4323 br_status = BRANCH_UNTAKEN;
4324 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4327 offset = FLD (i_hdt_offset8);
4328 addr = ADDSI (* FLD (i_rn), offset);
4329 if (EQSI (FLD (f_rd), 15)) {
4330 npc = EXTHISI (current_cpu->GETMEMHI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
4332 * FLD (i_rd) = EXTHISI (current_cpu->GETMEMHI (pc, addr));
4340 // ********** used only by: ldrsh-pre-inc-wb-reg-offset
4342 CASE (FRAG_LDRSH_PRE_INC_WB_REG_OFFSET_MID):
4346 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
4347 PCADDR pc = abuf->addr;
4348 br_status = BRANCH_UNTAKEN;
4349 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4352 offset = * FLD (i_rm);
4353 addr = ADDSI (* FLD (i_rn), offset);
4354 if (EQSI (FLD (f_rd), 15)) {
4355 npc = EXTHISI (current_cpu->GETMEMHI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
4357 * FLD (i_rd) = EXTHISI (current_cpu->GETMEMHI (pc, addr));
4360 * FLD (i_rn) = addr;
4364 pbb_br_status = br_status;
4367 NEXT_INSN (vpc, fragpc);
4369 // ********** used only by: ldrsh-post-dec-imm-offset
4371 CASE (FRAG_LDRSH_POST_DEC_IMM_OFFSET_MID):
4375 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
4376 PCADDR pc = abuf->addr;
4377 br_status = BRANCH_UNTAKEN;
4378 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4381 offset = FLD (i_hdt_offset8);
4382 addr = * FLD (i_rn);
4383 if (EQSI (FLD (f_rd), 15)) {
4384 npc = EXTHISI (current_cpu->GETMEMHI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
4386 * FLD (i_rd) = EXTHISI (current_cpu->GETMEMHI (pc, addr));
4388 addr = SUBSI (* FLD (i_rn), offset);
4389 * FLD (i_rn) = addr;
4393 pbb_br_status = br_status;
4396 NEXT_INSN (vpc, fragpc);
4398 // ********** used only by: ldrsh-post-dec-reg-offset
4400 CASE (FRAG_LDRSH_POST_DEC_REG_OFFSET_MID):
4404 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
4405 PCADDR pc = abuf->addr;
4406 br_status = BRANCH_UNTAKEN;
4407 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4410 offset = * FLD (i_rm);
4411 addr = * FLD (i_rn);
4412 if (EQSI (FLD (f_rd), 15)) {
4413 npc = EXTHISI (current_cpu->GETMEMHI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
4415 * FLD (i_rd) = EXTHISI (current_cpu->GETMEMHI (pc, addr));
4417 addr = SUBSI (* FLD (i_rn), offset);
4418 * FLD (i_rn) = addr;
4422 pbb_br_status = br_status;
4425 NEXT_INSN (vpc, fragpc);
4427 // ********** used only by: ldrsh-post-inc-imm-offset
4429 CASE (FRAG_LDRSH_POST_INC_IMM_OFFSET_MID):
4433 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
4434 PCADDR pc = abuf->addr;
4435 br_status = BRANCH_UNTAKEN;
4436 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4439 offset = FLD (i_hdt_offset8);
4440 addr = * FLD (i_rn);
4441 if (EQSI (FLD (f_rd), 15)) {
4442 npc = EXTHISI (current_cpu->GETMEMHI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
4444 * FLD (i_rd) = EXTHISI (current_cpu->GETMEMHI (pc, addr));
4446 addr = ADDSI (* FLD (i_rn), offset);
4447 * FLD (i_rn) = addr;
4451 pbb_br_status = br_status;
4454 NEXT_INSN (vpc, fragpc);
4456 // ********** used only by: ldrsh-post-inc-reg-offset
4458 CASE (FRAG_LDRSH_POST_INC_REG_OFFSET_MID):
4462 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
4463 PCADDR pc = abuf->addr;
4464 br_status = BRANCH_UNTAKEN;
4465 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4468 offset = * FLD (i_rm);
4469 addr = * FLD (i_rn);
4470 if (EQSI (FLD (f_rd), 15)) {
4471 npc = EXTHISI (current_cpu->GETMEMHI (pc, addr)); br_status = BRANCH_UNCACHEABLE;
4473 * FLD (i_rd) = EXTHISI (current_cpu->GETMEMHI (pc, addr));
4475 addr = ADDSI (* FLD (i_rn), offset);
4476 * FLD (i_rn) = addr;
4480 pbb_br_status = br_status;
4483 NEXT_INSN (vpc, fragpc);
4485 // ********** used only by: mul
4487 CASE (FRAG_MUL_MID):
4491 #define FLD(f) abuf->fields.sfmt_mla.f
4492 PCADDR pc = abuf->addr;
4493 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4496 result = MULSI (* FLD (i_rm), * FLD (i_rs));
4497 * FLD (i_mul_rd) = result;
4498 if (FLD (f_set_cc_)) {
4500 current_cpu->hardware.h_zbit = EQSI (result, 0);
4501 current_cpu->hardware.h_nbit = LTSI (result, 0);
4508 NEXT_INSN (vpc, fragpc);
4510 // ********** used only by: mla
4512 CASE (FRAG_MLA_MID):
4516 #define FLD(f) abuf->fields.sfmt_mla.f
4517 PCADDR pc = abuf->addr;
4518 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4521 * FLD (i_mul_rd) = ADDSI (MULSI (* FLD (i_rm), * FLD (i_rs)), * FLD (i_mul_rn));
4522 if (FLD (f_set_cc_)) {
4524 current_cpu->hardware.h_zbit = EQSI (result, 0);
4525 current_cpu->hardware.h_nbit = LTSI (result, 0);
4532 NEXT_INSN (vpc, fragpc);
4534 // ********** used only by: umull
4536 CASE (FRAG_UMULL_MID):
4540 #define FLD(f) abuf->fields.sfmt_umull.f
4541 PCADDR pc = abuf->addr;
4542 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4545 mul_result = MULDI (ZEXTSIDI (* FLD (i_rs)), ZEXTSIDI (* FLD (i_rm)));
4552 // ********** used only by: umlal
4554 CASE (FRAG_UMLAL_MID):
4558 #define FLD(f) abuf->fields.sfmt_umull.f
4559 PCADDR pc = abuf->addr;
4560 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4563 mul_result = JOINSIDI (* FLD (i_rdhi), * FLD (i_rdlo));
4564 mul_result = ADDDI (MULDI (ZEXTSIDI (* FLD (i_rs)), ZEXTSIDI (* FLD (i_rm))), mul_result);
4571 // ********** used only by: smull
4573 CASE (FRAG_SMULL_MID):
4577 #define FLD(f) abuf->fields.sfmt_umull.f
4578 PCADDR pc = abuf->addr;
4579 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4582 mul_result = MULDI (EXTSIDI (* FLD (i_rs)), EXTSIDI (* FLD (i_rm)));
4589 // ********** used only by: smlal
4591 CASE (FRAG_SMLAL_MID):
4595 #define FLD(f) abuf->fields.sfmt_umull.f
4596 PCADDR pc = abuf->addr;
4597 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4600 mul_result = JOINSIDI (* FLD (i_rdhi), * FLD (i_rdlo));
4601 mul_result = ADDDI (MULDI (EXTSIDI (* FLD (i_rs)), EXTSIDI (* FLD (i_rm))), mul_result);
4602 * FLD (i_rdhi) = SUBWORDDISI (mul_result, 0);
4603 * FLD (i_rdlo) = SUBWORDDISI (mul_result, 1);
4604 if (FLD (f_set_cc_)) {
4606 current_cpu->hardware.h_zbit = EQDI (mul_result, 0);
4607 current_cpu->hardware.h_nbit = LTDI (mul_result, 0);
4614 NEXT_INSN (vpc, fragpc);
4616 // ********** used only by: swp
4618 CASE (FRAG_SWP_MID):
4622 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
4623 PCADDR pc = abuf->addr;
4624 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4627 temp = current_cpu->GETMEMSI (pc, * FLD (i_rn));
4628 current_cpu->SETMEMSI (pc, * FLD (i_rn), * FLD (i_rm));
4629 * FLD (i_rd) = temp;
4634 NEXT_INSN (vpc, fragpc);
4636 // ********** used only by: swpb
4638 CASE (FRAG_SWPB_MID):
4642 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
4643 PCADDR pc = abuf->addr;
4644 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4647 temp = current_cpu->GETMEMQI (pc, * FLD (i_rn));
4648 current_cpu->SETMEMQI (pc, * FLD (i_rn), * FLD (i_rm));
4649 * FLD (i_rd) = temp;
4654 NEXT_INSN (vpc, fragpc);
4656 // ********** used only by: swi
4658 CASE (FRAG_SWI_MID):
4662 #define FLD(f) abuf->fields.sfmt_swi.f
4663 PCADDR pc = abuf->addr;
4664 br_status = BRANCH_UNTAKEN;
4665 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4668 npc = current_cpu->arm_swi (pc, FLD (f_swi_comment)); br_status = BRANCH_UNCACHEABLE;
4672 pbb_br_status = br_status;
4675 NEXT_INSN (vpc, fragpc);
4677 // ********** used only by: and-reg/imm-shift
4679 CASE (FRAG_AND_REG_IMM_SHIFT_MID):
4683 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
4684 PCADDR pc = abuf->addr;
4685 br_status = BRANCH_UNTAKEN;
4686 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4689 operand2 = current_cpu->compute_operand2_immshift (* FLD (i_rm), FLD (f_operand2_shifttype), FLD (f_operand2_shiftimm));
4690 carry_out = current_cpu->compute_carry_out_immshift (* FLD (i_rm), FLD (f_operand2_shifttype), FLD (f_operand2_shiftimm), current_cpu->hardware.h_cbit);
4691 result = ANDSI (* FLD (i_rn), operand2);
4692 if (EQSI (FLD (f_rd), 15)) {
4694 npc = result; br_status = BRANCH_UNCACHEABLE;
4695 if (FLD (f_set_cc_)) {
4696 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
4701 * FLD (i_rd) = result;
4702 if (FLD (f_set_cc_)) {
4705 current_cpu->hardware.h_zbit = EQSI (result, 0);
4706 current_cpu->hardware.h_nbit = LTSI (result, 0);
4708 current_cpu->hardware.h_cbit = carry_out;
4716 pbb_br_status = br_status;
4719 NEXT_INSN (vpc, fragpc);
4721 // ********** used only by: and-reg/reg-shift
4723 CASE (FRAG_AND_REG_REG_SHIFT_MID):
4727 #define FLD(f) abuf->fields.sfmt_and_reg_reg_shift.f
4728 PCADDR pc = abuf->addr;
4729 br_status = BRANCH_UNTAKEN;
4730 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4733 operand2 = current_cpu->compute_operand2_regshift (* FLD (i_rm), FLD (f_operand2_shifttype), * FLD (i_operand2_shiftreg));
4734 carry_out = current_cpu->compute_carry_out_regshift (* FLD (i_rm), FLD (f_operand2_shifttype), * FLD (i_operand2_shiftreg), current_cpu->hardware.h_cbit);
4735 result = ANDSI (* FLD (i_rn), operand2);
4742 // ********** used only by: and-imm
4744 CASE (FRAG_AND_IMM_MID):
4748 #define FLD(f) abuf->fields.sfmt_and_imm.f
4749 PCADDR pc = abuf->addr;
4750 br_status = BRANCH_UNTAKEN;
4751 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4754 result = ANDSI (* FLD (i_rn), FLD (f_imm12));
4761 // ********** used only by: orr-reg/imm-shift
4763 CASE (FRAG_ORR_REG_IMM_SHIFT_MID):
4765 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
4766 PCADDR pc = abuf->addr;
4769 result = ORSI (* FLD (i_rn), operand2);
4776 // ********** used only by: orr-reg/reg-shift
4778 CASE (FRAG_ORR_REG_REG_SHIFT_MID):
4780 #define FLD(f) abuf->fields.sfmt_and_reg_reg_shift.f
4781 PCADDR pc = abuf->addr;
4784 result = ORSI (* FLD (i_rn), operand2);
4791 // ********** used only by: orr-imm
4793 CASE (FRAG_ORR_IMM_MID):
4797 #define FLD(f) abuf->fields.sfmt_and_imm.f
4798 PCADDR pc = abuf->addr;
4799 br_status = BRANCH_UNTAKEN;
4800 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4803 result = ORSI (* FLD (i_rn), FLD (f_imm12));
4810 // ********** used only by: eor-reg/imm-shift
4812 CASE (FRAG_EOR_REG_IMM_SHIFT_MID):
4814 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
4815 PCADDR pc = abuf->addr;
4818 result = XORSI (* FLD (i_rn), operand2);
4825 // ********** used only by: eor-reg/reg-shift
4827 CASE (FRAG_EOR_REG_REG_SHIFT_MID):
4829 #define FLD(f) abuf->fields.sfmt_and_reg_reg_shift.f
4830 PCADDR pc = abuf->addr;
4833 result = XORSI (* FLD (i_rn), operand2);
4840 // ********** used only by: eor-imm
4842 CASE (FRAG_EOR_IMM_MID):
4846 #define FLD(f) abuf->fields.sfmt_and_imm.f
4847 PCADDR pc = abuf->addr;
4848 br_status = BRANCH_UNTAKEN;
4849 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4852 result = XORSI (* FLD (i_rn), FLD (f_imm12));
4859 // ********** used only by: mov-reg/imm-shift
4861 CASE (FRAG_MOV_REG_IMM_SHIFT_MID):
4863 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
4864 PCADDR pc = abuf->addr;
4874 // ********** used only by: mov-reg/reg-shift
4876 CASE (FRAG_MOV_REG_REG_SHIFT_MID):
4878 #define FLD(f) abuf->fields.sfmt_and_reg_reg_shift.f
4879 PCADDR pc = abuf->addr;
4889 // ********** used only by: mov-imm
4891 CASE (FRAG_MOV_IMM_MID):
4895 #define FLD(f) abuf->fields.sfmt_and_imm.f
4896 PCADDR pc = abuf->addr;
4897 br_status = BRANCH_UNTAKEN;
4898 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4901 result = FLD (f_imm12);
4908 // ********** used only by: bic-reg/imm-shift
4910 CASE (FRAG_BIC_REG_IMM_SHIFT_MID):
4912 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
4913 PCADDR pc = abuf->addr;
4916 result = ANDSI (* FLD (i_rn), INVSI (operand2));
4923 // ********** used only by: bic-reg/reg-shift
4925 CASE (FRAG_BIC_REG_REG_SHIFT_MID):
4927 #define FLD(f) abuf->fields.sfmt_and_reg_reg_shift.f
4928 PCADDR pc = abuf->addr;
4931 result = ANDSI (* FLD (i_rn), INVSI (operand2));
4938 // ********** used only by: bic-imm
4940 CASE (FRAG_BIC_IMM_MID):
4944 #define FLD(f) abuf->fields.sfmt_and_imm.f
4945 PCADDR pc = abuf->addr;
4946 br_status = BRANCH_UNTAKEN;
4947 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
4950 result = ANDSI (* FLD (i_rn), INVSI (FLD (f_imm12)));
4957 // ********** used only by: mvn-reg/imm-shift
4959 CASE (FRAG_MVN_REG_IMM_SHIFT_MID):
4961 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
4962 PCADDR pc = abuf->addr;
4965 carry_out = current_cpu->compute_carry_out_immshift (* FLD (i_rm), FLD (f_operand2_shifttype), FLD (f_operand2_shiftimm), current_cpu->hardware.h_cbit);
4966 result = INVSI (operand2);
4973 // ********** used only by: mvn-reg/reg-shift
4975 CASE (FRAG_MVN_REG_REG_SHIFT_MID):
4977 #define FLD(f) abuf->fields.sfmt_and_reg_reg_shift.f
4978 PCADDR pc = abuf->addr;
4981 carry_out = current_cpu->compute_carry_out_regshift (* FLD (i_rm), FLD (f_operand2_shifttype), * FLD (i_operand2_shiftreg), current_cpu->hardware.h_cbit);
4982 result = INVSI (operand2);
4983 if (EQSI (FLD (f_rd), 15)) {
4985 npc = result; br_status = BRANCH_UNCACHEABLE;
4986 if (FLD (f_set_cc_)) {
4987 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
4992 * FLD (i_rd) = result;
4993 if (FLD (f_set_cc_)) {
4996 current_cpu->hardware.h_zbit = EQSI (result, 0);
4997 current_cpu->hardware.h_nbit = LTSI (result, 0);
4999 current_cpu->hardware.h_cbit = carry_out;
5007 pbb_br_status = br_status;
5010 NEXT_INSN (vpc, fragpc);
5012 // ********** used only by: mvn-imm
5014 CASE (FRAG_MVN_IMM_MID):
5018 #define FLD(f) abuf->fields.sfmt_and_imm.f
5019 PCADDR pc = abuf->addr;
5020 br_status = BRANCH_UNTAKEN;
5021 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
5024 result = INVSI (FLD (f_imm12));
5025 if (EQSI (FLD (f_rd), 15)) {
5027 npc = result; br_status = BRANCH_UNCACHEABLE;
5028 if (FLD (f_set_cc_)) {
5029 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
5034 * FLD (i_rd) = result;
5035 if (FLD (f_set_cc_)) {
5037 current_cpu->hardware.h_zbit = EQSI (result, 0);
5038 current_cpu->hardware.h_nbit = LTSI (result, 0);
5046 pbb_br_status = br_status;
5049 NEXT_INSN (vpc, fragpc);
5051 // ********** used only by: add-reg/imm-shift
5053 CASE (FRAG_ADD_REG_IMM_SHIFT_MID):
5055 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
5056 PCADDR pc = abuf->addr;
5059 temp_op1 = * FLD (i_rn);
5060 temp_op2 = operand2;
5061 result = ADDSI (* FLD (i_rn), operand2);
5062 if (EQSI (FLD (f_rd), 15)) {
5064 npc = result; br_status = BRANCH_UNCACHEABLE;
5065 if (FLD (f_set_cc_)) {
5066 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
5071 * FLD (i_rd) = result;
5072 if (FLD (f_set_cc_)) {
5075 tmp_result = ADDCSI (temp_op1, temp_op2, 0);
5077 current_cpu->hardware.h_zbit = EQSI (tmp_result, 0);
5078 current_cpu->hardware.h_nbit = LTSI (tmp_result, 0);
5080 current_cpu->hardware.h_cbit = ADDCFSI (temp_op1, temp_op2, 0);
5081 current_cpu->hardware.h_vbit = ADDOFSI (temp_op1, temp_op2, 0);
5089 pbb_br_status = br_status;
5092 NEXT_INSN (vpc, fragpc);
5094 // ********** used only by: add-reg/reg-shift
5096 CASE (FRAG_ADD_REG_REG_SHIFT_MID):
5098 #define FLD(f) abuf->fields.sfmt_and_reg_reg_shift.f
5099 PCADDR pc = abuf->addr;
5102 temp_op1 = * FLD (i_rn);
5103 temp_op2 = operand2;
5104 result = ADDSI (* FLD (i_rn), operand2);
5105 if (EQSI (FLD (f_rd), 15)) {
5107 npc = result; br_status = BRANCH_UNCACHEABLE;
5108 if (FLD (f_set_cc_)) {
5109 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
5114 * FLD (i_rd) = result;
5115 if (FLD (f_set_cc_)) {
5118 tmp_result = ADDCSI (temp_op1, temp_op2, 0);
5120 current_cpu->hardware.h_zbit = EQSI (tmp_result, 0);
5121 current_cpu->hardware.h_nbit = LTSI (tmp_result, 0);
5123 current_cpu->hardware.h_cbit = ADDCFSI (temp_op1, temp_op2, 0);
5124 current_cpu->hardware.h_vbit = ADDOFSI (temp_op1, temp_op2, 0);
5132 pbb_br_status = br_status;
5135 NEXT_INSN (vpc, fragpc);
5137 // ********** used only by: add-imm
5139 CASE (FRAG_ADD_IMM_MID):
5143 #define FLD(f) abuf->fields.sfmt_and_imm.f
5144 PCADDR pc = abuf->addr;
5145 br_status = BRANCH_UNTAKEN;
5146 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
5149 result = ADDSI (* FLD (i_rn), FLD (f_imm12));
5150 if (EQSI (FLD (f_rd), 15)) {
5152 if (FLD (f_set_cc_)) {
5153 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
5155 npc = result; br_status = BRANCH_UNCACHEABLE;
5159 if (FLD (f_set_cc_)) {
5162 tmp_result = ADDCSI (* FLD (i_rn), FLD (f_imm12), 0);
5164 current_cpu->hardware.h_zbit = EQSI (tmp_result, 0);
5165 current_cpu->hardware.h_nbit = LTSI (tmp_result, 0);
5167 current_cpu->hardware.h_cbit = ADDCFSI (* FLD (i_rn), FLD (f_imm12), 0);
5168 current_cpu->hardware.h_vbit = ADDOFSI (* FLD (i_rn), FLD (f_imm12), 0);
5171 * FLD (i_rd) = result;
5177 pbb_br_status = br_status;
5180 NEXT_INSN (vpc, fragpc);
5182 // ********** used only by: adc-reg/imm-shift
5184 CASE (FRAG_ADC_REG_IMM_SHIFT_MID):
5186 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
5187 PCADDR pc = abuf->addr;
5190 temp_op1 = * FLD (i_rn);
5191 temp_op2 = operand2;
5192 result = ADDCSI (* FLD (i_rn), operand2, current_cpu->hardware.h_cbit);
5193 if (EQSI (FLD (f_rd), 15)) {
5195 npc = result; br_status = BRANCH_UNCACHEABLE;
5196 if (FLD (f_set_cc_)) {
5197 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
5202 * FLD (i_rd) = result;
5203 if (FLD (f_set_cc_)) {
5206 tmp_result = ADDCSI (temp_op1, temp_op2, current_cpu->hardware.h_cbit);
5208 current_cpu->hardware.h_zbit = EQSI (tmp_result, 0);
5209 current_cpu->hardware.h_nbit = LTSI (tmp_result, 0);
5211 current_cpu->hardware.h_cbit = ADDCFSI (temp_op1, temp_op2, current_cpu->hardware.h_cbit);
5212 current_cpu->hardware.h_vbit = ADDOFSI (temp_op1, temp_op2, current_cpu->hardware.h_cbit);
5220 pbb_br_status = br_status;
5223 NEXT_INSN (vpc, fragpc);
5225 // ********** used only by: adc-reg/reg-shift
5227 CASE (FRAG_ADC_REG_REG_SHIFT_MID):
5229 #define FLD(f) abuf->fields.sfmt_and_reg_reg_shift.f
5230 PCADDR pc = abuf->addr;
5233 temp_op1 = * FLD (i_rn);
5234 temp_op2 = operand2;
5235 result = ADDCSI (* FLD (i_rn), operand2, current_cpu->hardware.h_cbit);
5236 if (EQSI (FLD (f_rd), 15)) {
5238 npc = result; br_status = BRANCH_UNCACHEABLE;
5239 if (FLD (f_set_cc_)) {
5240 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
5245 * FLD (i_rd) = result;
5246 if (FLD (f_set_cc_)) {
5249 tmp_result = ADDCSI (temp_op1, temp_op2, current_cpu->hardware.h_cbit);
5251 current_cpu->hardware.h_zbit = EQSI (tmp_result, 0);
5252 current_cpu->hardware.h_nbit = LTSI (tmp_result, 0);
5254 current_cpu->hardware.h_cbit = ADDCFSI (temp_op1, temp_op2, current_cpu->hardware.h_cbit);
5255 current_cpu->hardware.h_vbit = ADDOFSI (temp_op1, temp_op2, current_cpu->hardware.h_cbit);
5263 pbb_br_status = br_status;
5266 NEXT_INSN (vpc, fragpc);
5268 // ********** used only by: adc-imm
5270 CASE (FRAG_ADC_IMM_MID):
5274 #define FLD(f) abuf->fields.sfmt_and_imm.f
5275 PCADDR pc = abuf->addr;
5276 br_status = BRANCH_UNTAKEN;
5277 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
5280 result = ADDCSI (* FLD (i_rn), FLD (f_imm12), current_cpu->hardware.h_cbit);
5281 if (EQSI (FLD (f_rd), 15)) {
5283 if (FLD (f_set_cc_)) {
5284 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
5286 npc = result; br_status = BRANCH_UNCACHEABLE;
5290 if (FLD (f_set_cc_)) {
5293 tmp_result = ADDCSI (* FLD (i_rn), FLD (f_imm12), current_cpu->hardware.h_cbit);
5295 current_cpu->hardware.h_zbit = EQSI (tmp_result, 0);
5296 current_cpu->hardware.h_nbit = LTSI (tmp_result, 0);
5298 current_cpu->hardware.h_cbit = ADDCFSI (* FLD (i_rn), FLD (f_imm12), current_cpu->hardware.h_cbit);
5299 current_cpu->hardware.h_vbit = ADDOFSI (* FLD (i_rn), FLD (f_imm12), current_cpu->hardware.h_cbit);
5302 * FLD (i_rd) = result;
5308 pbb_br_status = br_status;
5311 NEXT_INSN (vpc, fragpc);
5313 // ********** used only by: sub-reg/imm-shift
5315 CASE (FRAG_SUB_REG_IMM_SHIFT_MID):
5317 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
5318 PCADDR pc = abuf->addr;
5321 temp_op1 = * FLD (i_rn);
5322 temp_op2 = operand2;
5323 result = SUBSI (* FLD (i_rn), operand2);
5324 if (EQSI (FLD (f_rd), 15)) {
5326 npc = result; br_status = BRANCH_UNCACHEABLE;
5327 if (FLD (f_set_cc_)) {
5328 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
5333 * FLD (i_rd) = result;
5334 if (FLD (f_set_cc_)) {
5337 tmp_result = SUBCSI (temp_op1, temp_op2, 0);
5339 current_cpu->hardware.h_zbit = EQSI (tmp_result, 0);
5340 current_cpu->hardware.h_nbit = LTSI (tmp_result, 0);
5342 current_cpu->hardware.h_cbit = NOTBI (SUBCFSI (temp_op1, temp_op2, 0));
5343 current_cpu->hardware.h_vbit = SUBOFSI (temp_op1, temp_op2, 0);
5351 pbb_br_status = br_status;
5354 NEXT_INSN (vpc, fragpc);
5356 // ********** used only by: sub-reg/reg-shift
5358 CASE (FRAG_SUB_REG_REG_SHIFT_MID):
5360 #define FLD(f) abuf->fields.sfmt_and_reg_reg_shift.f
5361 PCADDR pc = abuf->addr;
5364 temp_op1 = * FLD (i_rn);
5365 temp_op2 = operand2;
5366 result = SUBSI (* FLD (i_rn), operand2);
5367 if (EQSI (FLD (f_rd), 15)) {
5369 npc = result; br_status = BRANCH_UNCACHEABLE;
5370 if (FLD (f_set_cc_)) {
5371 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
5376 * FLD (i_rd) = result;
5377 if (FLD (f_set_cc_)) {
5380 tmp_result = SUBCSI (temp_op1, temp_op2, 0);
5382 current_cpu->hardware.h_zbit = EQSI (tmp_result, 0);
5383 current_cpu->hardware.h_nbit = LTSI (tmp_result, 0);
5385 current_cpu->hardware.h_cbit = NOTBI (SUBCFSI (temp_op1, temp_op2, 0));
5386 current_cpu->hardware.h_vbit = SUBOFSI (temp_op1, temp_op2, 0);
5394 pbb_br_status = br_status;
5397 NEXT_INSN (vpc, fragpc);
5399 // ********** used only by: sub-imm
5401 CASE (FRAG_SUB_IMM_MID):
5405 #define FLD(f) abuf->fields.sfmt_and_imm.f
5406 PCADDR pc = abuf->addr;
5407 br_status = BRANCH_UNTAKEN;
5408 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
5411 result = SUBSI (* FLD (i_rn), FLD (f_imm12));
5412 if (EQSI (FLD (f_rd), 15)) {
5414 if (FLD (f_set_cc_)) {
5415 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
5417 npc = result; br_status = BRANCH_UNCACHEABLE;
5421 if (FLD (f_set_cc_)) {
5424 tmp_result = SUBCSI (* FLD (i_rn), FLD (f_imm12), 0);
5426 current_cpu->hardware.h_zbit = EQSI (tmp_result, 0);
5427 current_cpu->hardware.h_nbit = LTSI (tmp_result, 0);
5429 current_cpu->hardware.h_cbit = NOTBI (SUBCFSI (* FLD (i_rn), FLD (f_imm12), 0));
5430 current_cpu->hardware.h_vbit = SUBOFSI (* FLD (i_rn), FLD (f_imm12), 0);
5433 * FLD (i_rd) = result;
5439 pbb_br_status = br_status;
5442 NEXT_INSN (vpc, fragpc);
5444 // ********** used only by: sbc-reg/imm-shift
5446 CASE (FRAG_SBC_REG_IMM_SHIFT_MID):
5448 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
5449 PCADDR pc = abuf->addr;
5452 temp_op1 = * FLD (i_rn);
5453 temp_op2 = operand2;
5454 result = SUBCSI (* FLD (i_rn), operand2, NOTBI (current_cpu->hardware.h_cbit));
5455 if (EQSI (FLD (f_rd), 15)) {
5457 npc = result; br_status = BRANCH_UNCACHEABLE;
5458 if (FLD (f_set_cc_)) {
5459 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
5464 * FLD (i_rd) = result;
5465 if (FLD (f_set_cc_)) {
5468 tmp_result = SUBCSI (temp_op1, temp_op2, NOTBI (current_cpu->hardware.h_cbit));
5470 current_cpu->hardware.h_zbit = EQSI (tmp_result, 0);
5471 current_cpu->hardware.h_nbit = LTSI (tmp_result, 0);
5473 current_cpu->hardware.h_cbit = NOTBI (SUBCFSI (temp_op1, temp_op2, NOTBI (current_cpu->hardware.h_cbit)));
5474 current_cpu->hardware.h_vbit = SUBOFSI (temp_op1, temp_op2, NOTBI (current_cpu->hardware.h_cbit));
5482 pbb_br_status = br_status;
5485 NEXT_INSN (vpc, fragpc);
5487 // ********** used only by: sbc-reg/reg-shift
5489 CASE (FRAG_SBC_REG_REG_SHIFT_MID):
5491 #define FLD(f) abuf->fields.sfmt_and_reg_reg_shift.f
5492 PCADDR pc = abuf->addr;
5495 temp_op1 = * FLD (i_rn);
5496 temp_op2 = operand2;
5497 result = SUBCSI (* FLD (i_rn), operand2, NOTBI (current_cpu->hardware.h_cbit));
5498 if (EQSI (FLD (f_rd), 15)) {
5500 npc = result; br_status = BRANCH_UNCACHEABLE;
5501 if (FLD (f_set_cc_)) {
5502 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
5507 * FLD (i_rd) = result;
5508 if (FLD (f_set_cc_)) {
5511 tmp_result = SUBCSI (temp_op1, temp_op2, NOTBI (current_cpu->hardware.h_cbit));
5513 current_cpu->hardware.h_zbit = EQSI (tmp_result, 0);
5514 current_cpu->hardware.h_nbit = LTSI (tmp_result, 0);
5516 current_cpu->hardware.h_cbit = NOTBI (SUBCFSI (temp_op1, temp_op2, NOTBI (current_cpu->hardware.h_cbit)));
5517 current_cpu->hardware.h_vbit = SUBOFSI (temp_op1, temp_op2, NOTBI (current_cpu->hardware.h_cbit));
5525 pbb_br_status = br_status;
5528 NEXT_INSN (vpc, fragpc);
5530 // ********** used only by: sbc-imm
5532 CASE (FRAG_SBC_IMM_MID):
5536 #define FLD(f) abuf->fields.sfmt_and_imm.f
5537 PCADDR pc = abuf->addr;
5538 br_status = BRANCH_UNTAKEN;
5539 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
5542 result = SUBCSI (* FLD (i_rn), FLD (f_imm12), NOTBI (current_cpu->hardware.h_cbit));
5543 if (EQSI (FLD (f_rd), 15)) {
5545 if (FLD (f_set_cc_)) {
5546 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
5548 npc = result; br_status = BRANCH_UNCACHEABLE;
5552 if (FLD (f_set_cc_)) {
5555 tmp_result = SUBCSI (* FLD (i_rn), FLD (f_imm12), NOTBI (current_cpu->hardware.h_cbit));
5557 current_cpu->hardware.h_zbit = EQSI (tmp_result, 0);
5558 current_cpu->hardware.h_nbit = LTSI (tmp_result, 0);
5560 current_cpu->hardware.h_cbit = NOTBI (SUBCFSI (* FLD (i_rn), FLD (f_imm12), NOTBI (current_cpu->hardware.h_cbit)));
5561 current_cpu->hardware.h_vbit = SUBOFSI (* FLD (i_rn), FLD (f_imm12), NOTBI (current_cpu->hardware.h_cbit));
5564 * FLD (i_rd) = result;
5570 pbb_br_status = br_status;
5573 NEXT_INSN (vpc, fragpc);
5575 // ********** used only by: rsb-reg/imm-shift
5577 CASE (FRAG_RSB_REG_IMM_SHIFT_MID):
5579 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
5580 PCADDR pc = abuf->addr;
5583 temp_op1 = * FLD (i_rn);
5584 temp_op2 = operand2;
5585 result = SUBSI (operand2, * FLD (i_rn));
5586 if (EQSI (FLD (f_rd), 15)) {
5588 npc = result; br_status = BRANCH_UNCACHEABLE;
5589 if (FLD (f_set_cc_)) {
5590 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
5595 * FLD (i_rd) = result;
5596 if (FLD (f_set_cc_)) {
5599 tmp_result = SUBCSI (temp_op2, temp_op1, 0);
5601 current_cpu->hardware.h_zbit = EQSI (tmp_result, 0);
5602 current_cpu->hardware.h_nbit = LTSI (tmp_result, 0);
5604 current_cpu->hardware.h_cbit = NOTBI (SUBCFSI (temp_op2, temp_op1, 0));
5605 current_cpu->hardware.h_vbit = SUBOFSI (temp_op2, temp_op1, 0);
5613 pbb_br_status = br_status;
5616 NEXT_INSN (vpc, fragpc);
5618 // ********** used only by: rsb-reg/reg-shift
5620 CASE (FRAG_RSB_REG_REG_SHIFT_MID):
5622 #define FLD(f) abuf->fields.sfmt_and_reg_reg_shift.f
5623 PCADDR pc = abuf->addr;
5626 temp_op1 = * FLD (i_rn);
5627 temp_op2 = operand2;
5628 result = SUBSI (operand2, * FLD (i_rn));
5629 if (EQSI (FLD (f_rd), 15)) {
5631 npc = result; br_status = BRANCH_UNCACHEABLE;
5632 if (FLD (f_set_cc_)) {
5633 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
5638 * FLD (i_rd) = result;
5639 if (FLD (f_set_cc_)) {
5642 tmp_result = SUBCSI (temp_op2, temp_op1, 0);
5644 current_cpu->hardware.h_zbit = EQSI (tmp_result, 0);
5645 current_cpu->hardware.h_nbit = LTSI (tmp_result, 0);
5647 current_cpu->hardware.h_cbit = NOTBI (SUBCFSI (temp_op2, temp_op1, 0));
5648 current_cpu->hardware.h_vbit = SUBOFSI (temp_op2, temp_op1, 0);
5656 pbb_br_status = br_status;
5659 NEXT_INSN (vpc, fragpc);
5661 // ********** used only by: rsb-imm
5663 CASE (FRAG_RSB_IMM_MID):
5667 #define FLD(f) abuf->fields.sfmt_and_imm.f
5668 PCADDR pc = abuf->addr;
5669 br_status = BRANCH_UNTAKEN;
5670 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
5673 result = SUBSI (FLD (f_imm12), * FLD (i_rn));
5674 if (EQSI (FLD (f_rd), 15)) {
5676 if (FLD (f_set_cc_)) {
5677 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
5679 npc = result; br_status = BRANCH_UNCACHEABLE;
5683 if (FLD (f_set_cc_)) {
5686 tmp_result = SUBCSI (FLD (f_imm12), * FLD (i_rn), 0);
5688 current_cpu->hardware.h_zbit = EQSI (tmp_result, 0);
5689 current_cpu->hardware.h_nbit = LTSI (tmp_result, 0);
5691 current_cpu->hardware.h_cbit = NOTBI (SUBCFSI (FLD (f_imm12), * FLD (i_rn), 0));
5692 current_cpu->hardware.h_vbit = SUBOFSI (FLD (f_imm12), * FLD (i_rn), 0);
5695 * FLD (i_rd) = result;
5701 pbb_br_status = br_status;
5704 NEXT_INSN (vpc, fragpc);
5706 // ********** used only by: rsc-reg/imm-shift
5708 CASE (FRAG_RSC_REG_IMM_SHIFT_MID):
5710 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
5711 PCADDR pc = abuf->addr;
5714 temp_op1 = * FLD (i_rn);
5715 temp_op2 = operand2;
5716 result = SUBCSI (operand2, * FLD (i_rn), NOTBI (current_cpu->hardware.h_cbit));
5717 if (EQSI (FLD (f_rd), 15)) {
5719 npc = result; br_status = BRANCH_UNCACHEABLE;
5720 if (FLD (f_set_cc_)) {
5721 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
5726 * FLD (i_rd) = result;
5727 if (FLD (f_set_cc_)) {
5730 tmp_result = SUBCSI (temp_op2, temp_op1, NOTBI (current_cpu->hardware.h_cbit));
5732 current_cpu->hardware.h_zbit = EQSI (tmp_result, 0);
5733 current_cpu->hardware.h_nbit = LTSI (tmp_result, 0);
5735 current_cpu->hardware.h_cbit = NOTBI (SUBCFSI (temp_op2, temp_op1, NOTBI (current_cpu->hardware.h_cbit)));
5736 current_cpu->hardware.h_vbit = SUBOFSI (temp_op2, temp_op1, NOTBI (current_cpu->hardware.h_cbit));
5744 pbb_br_status = br_status;
5747 NEXT_INSN (vpc, fragpc);
5749 // ********** used only by: rsc-reg/reg-shift
5751 CASE (FRAG_RSC_REG_REG_SHIFT_MID):
5753 #define FLD(f) abuf->fields.sfmt_and_reg_reg_shift.f
5754 PCADDR pc = abuf->addr;
5757 temp_op1 = * FLD (i_rn);
5758 temp_op2 = operand2;
5759 result = SUBCSI (operand2, * FLD (i_rn), NOTBI (current_cpu->hardware.h_cbit));
5760 if (EQSI (FLD (f_rd), 15)) {
5762 npc = result; br_status = BRANCH_UNCACHEABLE;
5763 if (FLD (f_set_cc_)) {
5764 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
5769 * FLD (i_rd) = result;
5770 if (FLD (f_set_cc_)) {
5773 tmp_result = SUBCSI (temp_op2, temp_op1, NOTBI (current_cpu->hardware.h_cbit));
5775 current_cpu->hardware.h_zbit = EQSI (tmp_result, 0);
5776 current_cpu->hardware.h_nbit = LTSI (tmp_result, 0);
5778 current_cpu->hardware.h_cbit = NOTBI (SUBCFSI (temp_op2, temp_op1, NOTBI (current_cpu->hardware.h_cbit)));
5779 current_cpu->hardware.h_vbit = SUBOFSI (temp_op2, temp_op1, NOTBI (current_cpu->hardware.h_cbit));
5787 pbb_br_status = br_status;
5790 NEXT_INSN (vpc, fragpc);
5792 // ********** used only by: rsc-imm
5794 CASE (FRAG_RSC_IMM_MID):
5798 #define FLD(f) abuf->fields.sfmt_and_imm.f
5799 PCADDR pc = abuf->addr;
5800 br_status = BRANCH_UNTAKEN;
5801 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
5804 result = SUBCSI (FLD (f_imm12), * FLD (i_rn), NOTBI (current_cpu->hardware.h_cbit));
5805 if (EQSI (FLD (f_rd), 15)) {
5807 if (FLD (f_set_cc_)) {
5808 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
5810 npc = result; br_status = BRANCH_UNCACHEABLE;
5814 if (FLD (f_set_cc_)) {
5817 tmp_result = SUBCSI (FLD (f_imm12), * FLD (i_rn), NOTBI (current_cpu->hardware.h_cbit));
5819 current_cpu->hardware.h_zbit = EQSI (tmp_result, 0);
5820 current_cpu->hardware.h_nbit = LTSI (tmp_result, 0);
5822 current_cpu->hardware.h_cbit = NOTBI (SUBCFSI (FLD (f_imm12), * FLD (i_rn), NOTBI (current_cpu->hardware.h_cbit)));
5823 current_cpu->hardware.h_vbit = SUBOFSI (FLD (f_imm12), * FLD (i_rn), NOTBI (current_cpu->hardware.h_cbit));
5826 * FLD (i_rd) = result;
5832 pbb_br_status = br_status;
5835 NEXT_INSN (vpc, fragpc);
5837 // ********** used only by: tst-reg/imm-shift
5839 CASE (FRAG_TST_REG_IMM_SHIFT_MID):
5841 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
5842 PCADDR pc = abuf->addr;
5845 result = ANDSI (* FLD (i_rn), operand2);
5846 if (EQSI (FLD (f_rd), 15)) {
5847 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
5851 current_cpu->hardware.h_zbit = EQSI (result, 0);
5852 current_cpu->hardware.h_nbit = LTSI (result, 0);
5854 current_cpu->hardware.h_cbit = carry_out;
5861 NEXT_INSN (vpc, fragpc);
5863 // ********** used only by: tst-reg/reg-shift
5865 CASE (FRAG_TST_REG_REG_SHIFT_MID):
5867 #define FLD(f) abuf->fields.sfmt_and_reg_reg_shift.f
5868 PCADDR pc = abuf->addr;
5871 result = ANDSI (* FLD (i_rn), operand2);
5878 // ********** used only by: tst-imm
5880 CASE (FRAG_TST_IMM_MID):
5884 #define FLD(f) abuf->fields.sfmt_tst_imm.f
5885 PCADDR pc = abuf->addr;
5886 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
5889 if (EQSI (FLD (f_ror_imm8_rotate), 0)) {
5890 carry_out = current_cpu->hardware.h_cbit;
5892 carry_out = LTBI (FLD (f_ror_imm8), 0);
5896 current_cpu->hardware.h_zbit = EQSI (ANDSI (* FLD (i_rn), FLD (f_ror_imm8)), 0);
5897 current_cpu->hardware.h_nbit = LTSI (ANDSI (* FLD (i_rn), FLD (f_ror_imm8)), 0);
5899 current_cpu->hardware.h_cbit = carry_out;
5905 NEXT_INSN (vpc, fragpc);
5907 // ********** used only by: teq-reg/imm-shift
5909 CASE (FRAG_TEQ_REG_IMM_SHIFT_MID):
5911 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
5912 PCADDR pc = abuf->addr;
5915 result = XORSI (* FLD (i_rn), operand2);
5922 // ********** used only by: teq-reg/reg-shift
5924 CASE (FRAG_TEQ_REG_REG_SHIFT_MID):
5926 #define FLD(f) abuf->fields.sfmt_and_reg_reg_shift.f
5927 PCADDR pc = abuf->addr;
5930 result = XORSI (* FLD (i_rn), operand2);
5931 if (EQSI (FLD (f_rd), 15)) {
5932 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
5936 current_cpu->hardware.h_zbit = EQSI (result, 0);
5937 current_cpu->hardware.h_nbit = LTSI (result, 0);
5939 current_cpu->hardware.h_cbit = carry_out;
5946 NEXT_INSN (vpc, fragpc);
5948 // ********** used only by: teq-imm
5950 CASE (FRAG_TEQ_IMM_MID):
5954 #define FLD(f) abuf->fields.sfmt_tst_imm.f
5955 PCADDR pc = abuf->addr;
5956 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
5959 if (EQSI (FLD (f_ror_imm8_rotate), 0)) {
5960 carry_out = current_cpu->hardware.h_cbit;
5962 carry_out = LTBI (FLD (f_ror_imm8), 0);
5966 current_cpu->hardware.h_zbit = EQSI (XORSI (* FLD (i_rn), FLD (f_ror_imm8)), 0);
5967 current_cpu->hardware.h_nbit = LTSI (XORSI (* FLD (i_rn), FLD (f_ror_imm8)), 0);
5969 current_cpu->hardware.h_cbit = carry_out;
5975 NEXT_INSN (vpc, fragpc);
5977 // ********** used only by: cmp-reg/imm-shift
5979 CASE (FRAG_CMP_REG_IMM_SHIFT_MID):
5981 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
5982 PCADDR pc = abuf->addr;
5985 if (EQSI (FLD (f_rd), 15)) {
5986 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
5990 tmp_result = SUBCSI (* FLD (i_rn), operand2, 0);
5992 current_cpu->hardware.h_zbit = EQSI (tmp_result, 0);
5993 current_cpu->hardware.h_nbit = LTSI (tmp_result, 0);
5995 current_cpu->hardware.h_cbit = NOTBI (SUBCFSI (* FLD (i_rn), operand2, 0));
5996 current_cpu->hardware.h_vbit = SUBOFSI (* FLD (i_rn), operand2, 0);
6003 NEXT_INSN (vpc, fragpc);
6005 // ********** used only by: cmp-reg/reg-shift
6007 CASE (FRAG_CMP_REG_REG_SHIFT_MID):
6009 #define FLD(f) abuf->fields.sfmt_and_reg_reg_shift.f
6010 PCADDR pc = abuf->addr;
6013 if (EQSI (FLD (f_rd), 15)) {
6014 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
6018 tmp_result = SUBCSI (* FLD (i_rn), operand2, 0);
6020 current_cpu->hardware.h_zbit = EQSI (tmp_result, 0);
6021 current_cpu->hardware.h_nbit = LTSI (tmp_result, 0);
6023 current_cpu->hardware.h_cbit = NOTBI (SUBCFSI (* FLD (i_rn), operand2, 0));
6024 current_cpu->hardware.h_vbit = SUBOFSI (* FLD (i_rn), operand2, 0);
6031 NEXT_INSN (vpc, fragpc);
6033 // ********** used only by: cmp-imm
6035 CASE (FRAG_CMP_IMM_MID):
6039 #define FLD(f) abuf->fields.sfmt_and_imm.f
6040 PCADDR pc = abuf->addr;
6041 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
6044 result = SUBCSI (* FLD (i_rn), FLD (f_imm12), 0);
6046 current_cpu->hardware.h_zbit = EQSI (result, 0);
6047 current_cpu->hardware.h_nbit = LTSI (result, 0);
6049 current_cpu->hardware.h_cbit = NOTBI (SUBCFSI (* FLD (i_rn), FLD (f_imm12), 0));
6050 current_cpu->hardware.h_vbit = SUBOFSI (* FLD (i_rn), FLD (f_imm12), 0);
6055 NEXT_INSN (vpc, fragpc);
6057 // ********** used only by: cmn-reg/imm-shift
6059 CASE (FRAG_CMN_REG_IMM_SHIFT_MID):
6063 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
6064 PCADDR pc = abuf->addr;
6065 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
6068 operand2 = current_cpu->compute_operand2_immshift (* FLD (i_rm), FLD (f_operand2_shifttype), FLD (f_operand2_shiftimm));
6069 if (EQSI (FLD (f_rd), 15)) {
6070 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
6074 tmp_result = ADDCSI (* FLD (i_rn), operand2, 0);
6076 current_cpu->hardware.h_zbit = EQSI (tmp_result, 0);
6077 current_cpu->hardware.h_nbit = LTSI (tmp_result, 0);
6079 current_cpu->hardware.h_cbit = ADDCFSI (* FLD (i_rn), operand2, 0);
6080 current_cpu->hardware.h_vbit = ADDOFSI (* FLD (i_rn), operand2, 0);
6087 NEXT_INSN (vpc, fragpc);
6089 // ********** used only by: cmn-reg/reg-shift
6091 CASE (FRAG_CMN_REG_REG_SHIFT_MID):
6095 #define FLD(f) abuf->fields.sfmt_and_reg_reg_shift.f
6096 PCADDR pc = abuf->addr;
6097 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
6100 operand2 = current_cpu->compute_operand2_regshift (* FLD (i_rm), FLD (f_operand2_shifttype), * FLD (i_operand2_shiftreg));
6101 if (EQSI (FLD (f_rd), 15)) {
6102 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
6106 tmp_result = ADDCSI (* FLD (i_rn), operand2, 0);
6108 current_cpu->hardware.h_zbit = EQSI (tmp_result, 0);
6109 current_cpu->hardware.h_nbit = LTSI (tmp_result, 0);
6111 current_cpu->hardware.h_cbit = ADDCFSI (* FLD (i_rn), operand2, 0);
6112 current_cpu->hardware.h_vbit = ADDOFSI (* FLD (i_rn), operand2, 0);
6119 NEXT_INSN (vpc, fragpc);
6121 // ********** used only by: cmn-imm
6123 CASE (FRAG_CMN_IMM_MID):
6127 #define FLD(f) abuf->fields.sfmt_and_imm.f
6128 PCADDR pc = abuf->addr;
6129 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
6132 result = ADDCSI (* FLD (i_rn), FLD (f_imm12), 0);
6134 current_cpu->hardware.h_zbit = EQSI (result, 0);
6135 current_cpu->hardware.h_nbit = LTSI (result, 0);
6137 current_cpu->hardware.h_cbit = ADDCFSI (* FLD (i_rn), FLD (f_imm12), 0);
6138 current_cpu->hardware.h_vbit = ADDOFSI (* FLD (i_rn), FLD (f_imm12), 0);
6143 NEXT_INSN (vpc, fragpc);
6145 // ********** used only by: ldmda
6147 CASE (FRAG_LDMDA_MID):
6151 #define FLD(f) abuf->fields.sfmt_ldmda.f
6152 PCADDR pc = abuf->addr;
6153 br_status = BRANCH_UNTAKEN;
6154 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
6157 addr = * FLD (i_rn);
6158 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
6160 npc = current_cpu->GETMEMSI (pc, addr); br_status = BRANCH_UNCACHEABLE;
6161 addr = SUBSI (addr, 4);
6164 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
6166 current_cpu->hardware.h_gr[((UINT) 14)] = current_cpu->GETMEMSI (pc, addr);
6167 addr = SUBSI (addr, 4);
6170 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
6172 current_cpu->hardware.h_gr[((UINT) 13)] = current_cpu->GETMEMSI (pc, addr);
6173 addr = SUBSI (addr, 4);
6176 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
6178 current_cpu->hardware.h_gr[((UINT) 12)] = current_cpu->GETMEMSI (pc, addr);
6179 addr = SUBSI (addr, 4);
6182 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
6184 current_cpu->hardware.h_gr[((UINT) 11)] = current_cpu->GETMEMSI (pc, addr);
6185 addr = SUBSI (addr, 4);
6188 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
6190 current_cpu->hardware.h_gr[((UINT) 10)] = current_cpu->GETMEMSI (pc, addr);
6191 addr = SUBSI (addr, 4);
6194 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
6196 current_cpu->hardware.h_gr[((UINT) 9)] = current_cpu->GETMEMSI (pc, addr);
6197 addr = SUBSI (addr, 4);
6200 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
6202 current_cpu->hardware.h_gr[((UINT) 8)] = current_cpu->GETMEMSI (pc, addr);
6203 addr = SUBSI (addr, 4);
6206 if (ANDSI (FLD (f_reg_list), SLLSI (1, 7))) {
6208 current_cpu->hardware.h_gr[((UINT) 7)] = current_cpu->GETMEMSI (pc, addr);
6209 addr = SUBSI (addr, 4);
6212 if (ANDSI (FLD (f_reg_list), SLLSI (1, 6))) {
6214 current_cpu->hardware.h_gr[((UINT) 6)] = current_cpu->GETMEMSI (pc, addr);
6215 addr = SUBSI (addr, 4);
6218 if (ANDSI (FLD (f_reg_list), SLLSI (1, 5))) {
6220 current_cpu->hardware.h_gr[((UINT) 5)] = current_cpu->GETMEMSI (pc, addr);
6221 addr = SUBSI (addr, 4);
6224 if (ANDSI (FLD (f_reg_list), SLLSI (1, 4))) {
6226 current_cpu->hardware.h_gr[((UINT) 4)] = current_cpu->GETMEMSI (pc, addr);
6227 addr = SUBSI (addr, 4);
6230 if (ANDSI (FLD (f_reg_list), SLLSI (1, 3))) {
6232 current_cpu->hardware.h_gr[((UINT) 3)] = current_cpu->GETMEMSI (pc, addr);
6233 addr = SUBSI (addr, 4);
6236 if (ANDSI (FLD (f_reg_list), SLLSI (1, 2))) {
6238 current_cpu->hardware.h_gr[((UINT) 2)] = current_cpu->GETMEMSI (pc, addr);
6239 addr = SUBSI (addr, 4);
6242 if (ANDSI (FLD (f_reg_list), SLLSI (1, 1))) {
6244 current_cpu->hardware.h_gr[((UINT) 1)] = current_cpu->GETMEMSI (pc, addr);
6245 addr = SUBSI (addr, 4);
6248 if (ANDSI (FLD (f_reg_list), SLLSI (1, 0))) {
6250 current_cpu->hardware.h_gr[((UINT) 0)] = current_cpu->GETMEMSI (pc, addr);
6251 addr = SUBSI (addr, 4);
6257 pbb_br_status = br_status;
6260 NEXT_INSN (vpc, fragpc);
6262 // ********** used only by: ldmda-sw
6264 CASE (FRAG_LDMDA_SW_MID):
6268 #define FLD(f) abuf->fields.sfmt_ldmda.f
6269 PCADDR pc = abuf->addr;
6270 br_status = BRANCH_UNTAKEN;
6271 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
6274 addr = * FLD (i_rn);
6275 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
6277 npc = current_cpu->GETMEMSI (pc, addr); br_status = BRANCH_UNCACHEABLE;
6278 addr = SUBSI (addr, 4);
6279 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
6282 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
6284 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
6285 current_cpu->hardware.h_gr[((UINT) 14)] = current_cpu->GETMEMSI (pc, addr);
6287 current_cpu->hardware.h_gr_usr[SUBSI (14, 8)] = current_cpu->GETMEMSI (pc, addr);
6289 addr = SUBSI (addr, 4);
6292 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
6294 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
6295 current_cpu->hardware.h_gr[((UINT) 13)] = current_cpu->GETMEMSI (pc, addr);
6297 current_cpu->hardware.h_gr_usr[SUBSI (13, 8)] = current_cpu->GETMEMSI (pc, addr);
6299 addr = SUBSI (addr, 4);
6302 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
6304 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
6305 current_cpu->hardware.h_gr[((UINT) 12)] = current_cpu->GETMEMSI (pc, addr);
6307 current_cpu->hardware.h_gr_usr[SUBSI (12, 8)] = current_cpu->GETMEMSI (pc, addr);
6309 addr = SUBSI (addr, 4);
6312 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
6314 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
6315 current_cpu->hardware.h_gr[((UINT) 11)] = current_cpu->GETMEMSI (pc, addr);
6317 current_cpu->hardware.h_gr_usr[SUBSI (11, 8)] = current_cpu->GETMEMSI (pc, addr);
6319 addr = SUBSI (addr, 4);
6322 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
6324 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
6325 current_cpu->hardware.h_gr[((UINT) 10)] = current_cpu->GETMEMSI (pc, addr);
6327 current_cpu->hardware.h_gr_usr[SUBSI (10, 8)] = current_cpu->GETMEMSI (pc, addr);
6329 addr = SUBSI (addr, 4);
6332 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
6334 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
6335 current_cpu->hardware.h_gr[((UINT) 9)] = current_cpu->GETMEMSI (pc, addr);
6337 current_cpu->hardware.h_gr_usr[SUBSI (9, 8)] = current_cpu->GETMEMSI (pc, addr);
6339 addr = SUBSI (addr, 4);
6342 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
6344 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
6345 current_cpu->hardware.h_gr[((UINT) 8)] = current_cpu->GETMEMSI (pc, addr);
6347 current_cpu->hardware.h_gr_usr[SUBSI (8, 8)] = current_cpu->GETMEMSI (pc, addr);
6349 addr = SUBSI (addr, 4);
6352 if (ANDSI (FLD (f_reg_list), SLLSI (1, 7))) {
6354 current_cpu->hardware.h_gr[((UINT) 7)] = current_cpu->GETMEMSI (pc, addr);
6355 addr = SUBSI (addr, 4);
6358 if (ANDSI (FLD (f_reg_list), SLLSI (1, 6))) {
6360 current_cpu->hardware.h_gr[((UINT) 6)] = current_cpu->GETMEMSI (pc, addr);
6361 addr = SUBSI (addr, 4);
6364 if (ANDSI (FLD (f_reg_list), SLLSI (1, 5))) {
6366 current_cpu->hardware.h_gr[((UINT) 5)] = current_cpu->GETMEMSI (pc, addr);
6367 addr = SUBSI (addr, 4);
6370 if (ANDSI (FLD (f_reg_list), SLLSI (1, 4))) {
6372 current_cpu->hardware.h_gr[((UINT) 4)] = current_cpu->GETMEMSI (pc, addr);
6373 addr = SUBSI (addr, 4);
6376 if (ANDSI (FLD (f_reg_list), SLLSI (1, 3))) {
6378 current_cpu->hardware.h_gr[((UINT) 3)] = current_cpu->GETMEMSI (pc, addr);
6379 addr = SUBSI (addr, 4);
6382 if (ANDSI (FLD (f_reg_list), SLLSI (1, 2))) {
6384 current_cpu->hardware.h_gr[((UINT) 2)] = current_cpu->GETMEMSI (pc, addr);
6385 addr = SUBSI (addr, 4);
6388 if (ANDSI (FLD (f_reg_list), SLLSI (1, 1))) {
6390 current_cpu->hardware.h_gr[((UINT) 1)] = current_cpu->GETMEMSI (pc, addr);
6391 addr = SUBSI (addr, 4);
6394 if (ANDSI (FLD (f_reg_list), SLLSI (1, 0))) {
6396 current_cpu->hardware.h_gr[((UINT) 0)] = current_cpu->GETMEMSI (pc, addr);
6397 addr = SUBSI (addr, 4);
6403 pbb_br_status = br_status;
6406 NEXT_INSN (vpc, fragpc);
6408 // ********** used only by: ldmda-wb
6410 CASE (FRAG_LDMDA_WB_MID):
6414 #define FLD(f) abuf->fields.sfmt_ldmda.f
6415 PCADDR pc = abuf->addr;
6416 br_status = BRANCH_UNTAKEN;
6417 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
6420 addr = * FLD (i_rn);
6421 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
6423 npc = current_cpu->GETMEMSI (pc, addr); br_status = BRANCH_UNCACHEABLE;
6424 addr = SUBSI (addr, 4);
6427 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
6429 current_cpu->hardware.h_gr[((UINT) 14)] = current_cpu->GETMEMSI (pc, addr);
6430 addr = SUBSI (addr, 4);
6433 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
6435 current_cpu->hardware.h_gr[((UINT) 13)] = current_cpu->GETMEMSI (pc, addr);
6436 addr = SUBSI (addr, 4);
6439 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
6441 current_cpu->hardware.h_gr[((UINT) 12)] = current_cpu->GETMEMSI (pc, addr);
6442 addr = SUBSI (addr, 4);
6445 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
6447 current_cpu->hardware.h_gr[((UINT) 11)] = current_cpu->GETMEMSI (pc, addr);
6448 addr = SUBSI (addr, 4);
6451 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
6453 current_cpu->hardware.h_gr[((UINT) 10)] = current_cpu->GETMEMSI (pc, addr);
6454 addr = SUBSI (addr, 4);
6457 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
6459 current_cpu->hardware.h_gr[((UINT) 9)] = current_cpu->GETMEMSI (pc, addr);
6460 addr = SUBSI (addr, 4);
6463 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
6465 current_cpu->hardware.h_gr[((UINT) 8)] = current_cpu->GETMEMSI (pc, addr);
6466 addr = SUBSI (addr, 4);
6469 if (ANDSI (FLD (f_reg_list), SLLSI (1, 7))) {
6471 current_cpu->hardware.h_gr[((UINT) 7)] = current_cpu->GETMEMSI (pc, addr);
6472 addr = SUBSI (addr, 4);
6475 if (ANDSI (FLD (f_reg_list), SLLSI (1, 6))) {
6477 current_cpu->hardware.h_gr[((UINT) 6)] = current_cpu->GETMEMSI (pc, addr);
6478 addr = SUBSI (addr, 4);
6481 if (ANDSI (FLD (f_reg_list), SLLSI (1, 5))) {
6483 current_cpu->hardware.h_gr[((UINT) 5)] = current_cpu->GETMEMSI (pc, addr);
6484 addr = SUBSI (addr, 4);
6487 if (ANDSI (FLD (f_reg_list), SLLSI (1, 4))) {
6489 current_cpu->hardware.h_gr[((UINT) 4)] = current_cpu->GETMEMSI (pc, addr);
6490 addr = SUBSI (addr, 4);
6493 if (ANDSI (FLD (f_reg_list), SLLSI (1, 3))) {
6495 current_cpu->hardware.h_gr[((UINT) 3)] = current_cpu->GETMEMSI (pc, addr);
6496 addr = SUBSI (addr, 4);
6499 if (ANDSI (FLD (f_reg_list), SLLSI (1, 2))) {
6501 current_cpu->hardware.h_gr[((UINT) 2)] = current_cpu->GETMEMSI (pc, addr);
6502 addr = SUBSI (addr, 4);
6505 if (ANDSI (FLD (f_reg_list), SLLSI (1, 1))) {
6507 current_cpu->hardware.h_gr[((UINT) 1)] = current_cpu->GETMEMSI (pc, addr);
6508 addr = SUBSI (addr, 4);
6511 if (ANDSI (FLD (f_reg_list), SLLSI (1, 0))) {
6513 current_cpu->hardware.h_gr[((UINT) 0)] = current_cpu->GETMEMSI (pc, addr);
6514 addr = SUBSI (addr, 4);
6517 * FLD (i_rn) = addr;
6521 pbb_br_status = br_status;
6524 NEXT_INSN (vpc, fragpc);
6526 // ********** used only by: ldmda-sw-wb
6528 CASE (FRAG_LDMDA_SW_WB_MID):
6532 #define FLD(f) abuf->fields.sfmt_ldmda.f
6533 PCADDR pc = abuf->addr;
6534 br_status = BRANCH_UNTAKEN;
6535 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
6538 addr = * FLD (i_rn);
6539 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
6541 npc = current_cpu->GETMEMSI (pc, addr); br_status = BRANCH_UNCACHEABLE;
6542 addr = SUBSI (addr, 4);
6543 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
6546 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
6548 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
6549 current_cpu->hardware.h_gr[((UINT) 14)] = current_cpu->GETMEMSI (pc, addr);
6551 current_cpu->hardware.h_gr_usr[SUBSI (14, 8)] = current_cpu->GETMEMSI (pc, addr);
6553 addr = SUBSI (addr, 4);
6556 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
6558 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
6559 current_cpu->hardware.h_gr[((UINT) 13)] = current_cpu->GETMEMSI (pc, addr);
6561 current_cpu->hardware.h_gr_usr[SUBSI (13, 8)] = current_cpu->GETMEMSI (pc, addr);
6563 addr = SUBSI (addr, 4);
6566 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
6568 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
6569 current_cpu->hardware.h_gr[((UINT) 12)] = current_cpu->GETMEMSI (pc, addr);
6571 current_cpu->hardware.h_gr_usr[SUBSI (12, 8)] = current_cpu->GETMEMSI (pc, addr);
6573 addr = SUBSI (addr, 4);
6576 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
6578 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
6579 current_cpu->hardware.h_gr[((UINT) 11)] = current_cpu->GETMEMSI (pc, addr);
6581 current_cpu->hardware.h_gr_usr[SUBSI (11, 8)] = current_cpu->GETMEMSI (pc, addr);
6583 addr = SUBSI (addr, 4);
6586 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
6588 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
6589 current_cpu->hardware.h_gr[((UINT) 10)] = current_cpu->GETMEMSI (pc, addr);
6591 current_cpu->hardware.h_gr_usr[SUBSI (10, 8)] = current_cpu->GETMEMSI (pc, addr);
6593 addr = SUBSI (addr, 4);
6596 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
6598 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
6599 current_cpu->hardware.h_gr[((UINT) 9)] = current_cpu->GETMEMSI (pc, addr);
6601 current_cpu->hardware.h_gr_usr[SUBSI (9, 8)] = current_cpu->GETMEMSI (pc, addr);
6603 addr = SUBSI (addr, 4);
6606 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
6608 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
6609 current_cpu->hardware.h_gr[((UINT) 8)] = current_cpu->GETMEMSI (pc, addr);
6611 current_cpu->hardware.h_gr_usr[SUBSI (8, 8)] = current_cpu->GETMEMSI (pc, addr);
6613 addr = SUBSI (addr, 4);
6616 if (ANDSI (FLD (f_reg_list), SLLSI (1, 7))) {
6618 current_cpu->hardware.h_gr[((UINT) 7)] = current_cpu->GETMEMSI (pc, addr);
6619 addr = SUBSI (addr, 4);
6622 if (ANDSI (FLD (f_reg_list), SLLSI (1, 6))) {
6624 current_cpu->hardware.h_gr[((UINT) 6)] = current_cpu->GETMEMSI (pc, addr);
6625 addr = SUBSI (addr, 4);
6628 if (ANDSI (FLD (f_reg_list), SLLSI (1, 5))) {
6630 current_cpu->hardware.h_gr[((UINT) 5)] = current_cpu->GETMEMSI (pc, addr);
6631 addr = SUBSI (addr, 4);
6634 if (ANDSI (FLD (f_reg_list), SLLSI (1, 4))) {
6636 current_cpu->hardware.h_gr[((UINT) 4)] = current_cpu->GETMEMSI (pc, addr);
6637 addr = SUBSI (addr, 4);
6640 if (ANDSI (FLD (f_reg_list), SLLSI (1, 3))) {
6642 current_cpu->hardware.h_gr[((UINT) 3)] = current_cpu->GETMEMSI (pc, addr);
6643 addr = SUBSI (addr, 4);
6646 if (ANDSI (FLD (f_reg_list), SLLSI (1, 2))) {
6648 current_cpu->hardware.h_gr[((UINT) 2)] = current_cpu->GETMEMSI (pc, addr);
6649 addr = SUBSI (addr, 4);
6652 if (ANDSI (FLD (f_reg_list), SLLSI (1, 1))) {
6654 current_cpu->hardware.h_gr[((UINT) 1)] = current_cpu->GETMEMSI (pc, addr);
6655 addr = SUBSI (addr, 4);
6658 if (ANDSI (FLD (f_reg_list), SLLSI (1, 0))) {
6660 current_cpu->hardware.h_gr[((UINT) 0)] = current_cpu->GETMEMSI (pc, addr);
6661 addr = SUBSI (addr, 4);
6664 * FLD (i_rn) = addr;
6668 pbb_br_status = br_status;
6671 NEXT_INSN (vpc, fragpc);
6673 // ********** used only by: ldmib
6675 CASE (FRAG_LDMIB_MID):
6679 #define FLD(f) abuf->fields.sfmt_ldmda.f
6680 PCADDR pc = abuf->addr;
6681 br_status = BRANCH_UNTAKEN;
6682 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
6685 addr = * FLD (i_rn);
6686 if (ANDSI (FLD (f_reg_list), SLLSI (1, 0))) {
6688 addr = ADDSI (addr, 4);
6689 current_cpu->hardware.h_gr[((UINT) 0)] = current_cpu->GETMEMSI (pc, addr);
6692 if (ANDSI (FLD (f_reg_list), SLLSI (1, 1))) {
6694 addr = ADDSI (addr, 4);
6695 current_cpu->hardware.h_gr[((UINT) 1)] = current_cpu->GETMEMSI (pc, addr);
6698 if (ANDSI (FLD (f_reg_list), SLLSI (1, 2))) {
6700 addr = ADDSI (addr, 4);
6701 current_cpu->hardware.h_gr[((UINT) 2)] = current_cpu->GETMEMSI (pc, addr);
6704 if (ANDSI (FLD (f_reg_list), SLLSI (1, 3))) {
6706 addr = ADDSI (addr, 4);
6707 current_cpu->hardware.h_gr[((UINT) 3)] = current_cpu->GETMEMSI (pc, addr);
6710 if (ANDSI (FLD (f_reg_list), SLLSI (1, 4))) {
6712 addr = ADDSI (addr, 4);
6713 current_cpu->hardware.h_gr[((UINT) 4)] = current_cpu->GETMEMSI (pc, addr);
6716 if (ANDSI (FLD (f_reg_list), SLLSI (1, 5))) {
6718 addr = ADDSI (addr, 4);
6719 current_cpu->hardware.h_gr[((UINT) 5)] = current_cpu->GETMEMSI (pc, addr);
6722 if (ANDSI (FLD (f_reg_list), SLLSI (1, 6))) {
6724 addr = ADDSI (addr, 4);
6725 current_cpu->hardware.h_gr[((UINT) 6)] = current_cpu->GETMEMSI (pc, addr);
6728 if (ANDSI (FLD (f_reg_list), SLLSI (1, 7))) {
6730 addr = ADDSI (addr, 4);
6731 current_cpu->hardware.h_gr[((UINT) 7)] = current_cpu->GETMEMSI (pc, addr);
6734 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
6736 addr = ADDSI (addr, 4);
6737 current_cpu->hardware.h_gr[((UINT) 8)] = current_cpu->GETMEMSI (pc, addr);
6740 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
6742 addr = ADDSI (addr, 4);
6743 current_cpu->hardware.h_gr[((UINT) 9)] = current_cpu->GETMEMSI (pc, addr);
6746 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
6748 addr = ADDSI (addr, 4);
6749 current_cpu->hardware.h_gr[((UINT) 10)] = current_cpu->GETMEMSI (pc, addr);
6752 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
6754 addr = ADDSI (addr, 4);
6755 current_cpu->hardware.h_gr[((UINT) 11)] = current_cpu->GETMEMSI (pc, addr);
6758 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
6760 addr = ADDSI (addr, 4);
6761 current_cpu->hardware.h_gr[((UINT) 12)] = current_cpu->GETMEMSI (pc, addr);
6764 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
6766 addr = ADDSI (addr, 4);
6767 current_cpu->hardware.h_gr[((UINT) 13)] = current_cpu->GETMEMSI (pc, addr);
6770 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
6772 addr = ADDSI (addr, 4);
6773 current_cpu->hardware.h_gr[((UINT) 14)] = current_cpu->GETMEMSI (pc, addr);
6776 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
6778 addr = ADDSI (addr, 4);
6779 npc = current_cpu->GETMEMSI (pc, addr); br_status = BRANCH_UNCACHEABLE;
6785 pbb_br_status = br_status;
6788 NEXT_INSN (vpc, fragpc);
6790 // ********** used only by: ldmib-sw
6792 CASE (FRAG_LDMIB_SW_MID):
6794 #define FLD(f) abuf->fields.sfmt_ldmda.f
6795 PCADDR pc = abuf->addr;
6798 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
6800 addr = ADDSI (addr, 4);
6801 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
6802 current_cpu->hardware.h_gr[((UINT) 8)] = current_cpu->GETMEMSI (pc, addr);
6804 current_cpu->hardware.h_gr_usr[SUBSI (8, 8)] = current_cpu->GETMEMSI (pc, addr);
6808 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
6810 addr = ADDSI (addr, 4);
6811 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
6812 current_cpu->hardware.h_gr[((UINT) 9)] = current_cpu->GETMEMSI (pc, addr);
6814 current_cpu->hardware.h_gr_usr[SUBSI (9, 8)] = current_cpu->GETMEMSI (pc, addr);
6818 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
6820 addr = ADDSI (addr, 4);
6821 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
6822 current_cpu->hardware.h_gr[((UINT) 10)] = current_cpu->GETMEMSI (pc, addr);
6824 current_cpu->hardware.h_gr_usr[SUBSI (10, 8)] = current_cpu->GETMEMSI (pc, addr);
6828 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
6830 addr = ADDSI (addr, 4);
6831 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
6832 current_cpu->hardware.h_gr[((UINT) 11)] = current_cpu->GETMEMSI (pc, addr);
6834 current_cpu->hardware.h_gr_usr[SUBSI (11, 8)] = current_cpu->GETMEMSI (pc, addr);
6838 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
6840 addr = ADDSI (addr, 4);
6841 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
6842 current_cpu->hardware.h_gr[((UINT) 12)] = current_cpu->GETMEMSI (pc, addr);
6844 current_cpu->hardware.h_gr_usr[SUBSI (12, 8)] = current_cpu->GETMEMSI (pc, addr);
6848 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
6850 addr = ADDSI (addr, 4);
6851 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
6852 current_cpu->hardware.h_gr[((UINT) 13)] = current_cpu->GETMEMSI (pc, addr);
6854 current_cpu->hardware.h_gr_usr[SUBSI (13, 8)] = current_cpu->GETMEMSI (pc, addr);
6858 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
6860 addr = ADDSI (addr, 4);
6861 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
6862 current_cpu->hardware.h_gr[((UINT) 14)] = current_cpu->GETMEMSI (pc, addr);
6864 current_cpu->hardware.h_gr_usr[SUBSI (14, 8)] = current_cpu->GETMEMSI (pc, addr);
6868 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
6870 addr = ADDSI (addr, 4);
6871 npc = current_cpu->GETMEMSI (pc, addr); br_status = BRANCH_UNCACHEABLE;
6872 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
6878 pbb_br_status = br_status;
6881 NEXT_INSN (vpc, fragpc);
6883 // ********** used only by: ldmib-wb
6885 CASE (FRAG_LDMIB_WB_MID):
6887 #define FLD(f) abuf->fields.sfmt_ldmda.f
6888 PCADDR pc = abuf->addr;
6891 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
6893 addr = ADDSI (addr, 4);
6894 current_cpu->hardware.h_gr[((UINT) 8)] = current_cpu->GETMEMSI (pc, addr);
6897 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
6899 addr = ADDSI (addr, 4);
6900 current_cpu->hardware.h_gr[((UINT) 9)] = current_cpu->GETMEMSI (pc, addr);
6903 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
6905 addr = ADDSI (addr, 4);
6906 current_cpu->hardware.h_gr[((UINT) 10)] = current_cpu->GETMEMSI (pc, addr);
6909 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
6911 addr = ADDSI (addr, 4);
6912 current_cpu->hardware.h_gr[((UINT) 11)] = current_cpu->GETMEMSI (pc, addr);
6915 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
6917 addr = ADDSI (addr, 4);
6918 current_cpu->hardware.h_gr[((UINT) 12)] = current_cpu->GETMEMSI (pc, addr);
6921 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
6923 addr = ADDSI (addr, 4);
6924 current_cpu->hardware.h_gr[((UINT) 13)] = current_cpu->GETMEMSI (pc, addr);
6927 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
6929 addr = ADDSI (addr, 4);
6930 current_cpu->hardware.h_gr[((UINT) 14)] = current_cpu->GETMEMSI (pc, addr);
6933 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
6935 addr = ADDSI (addr, 4);
6936 npc = current_cpu->GETMEMSI (pc, addr); br_status = BRANCH_UNCACHEABLE;
6939 * FLD (i_rn) = addr;
6943 pbb_br_status = br_status;
6946 NEXT_INSN (vpc, fragpc);
6948 // ********** used only by: ldmib-sw-wb
6950 CASE (FRAG_LDMIB_SW_WB_MID):
6954 #define FLD(f) abuf->fields.sfmt_ldmda.f
6955 PCADDR pc = abuf->addr;
6956 br_status = BRANCH_UNTAKEN;
6957 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
6960 addr = * FLD (i_rn);
6961 if (ANDSI (FLD (f_reg_list), SLLSI (1, 0))) {
6963 addr = ADDSI (addr, 4);
6964 current_cpu->hardware.h_gr[((UINT) 0)] = current_cpu->GETMEMSI (pc, addr);
6967 if (ANDSI (FLD (f_reg_list), SLLSI (1, 1))) {
6969 addr = ADDSI (addr, 4);
6970 current_cpu->hardware.h_gr[((UINT) 1)] = current_cpu->GETMEMSI (pc, addr);
6973 if (ANDSI (FLD (f_reg_list), SLLSI (1, 2))) {
6975 addr = ADDSI (addr, 4);
6976 current_cpu->hardware.h_gr[((UINT) 2)] = current_cpu->GETMEMSI (pc, addr);
6979 if (ANDSI (FLD (f_reg_list), SLLSI (1, 3))) {
6981 addr = ADDSI (addr, 4);
6982 current_cpu->hardware.h_gr[((UINT) 3)] = current_cpu->GETMEMSI (pc, addr);
6985 if (ANDSI (FLD (f_reg_list), SLLSI (1, 4))) {
6987 addr = ADDSI (addr, 4);
6988 current_cpu->hardware.h_gr[((UINT) 4)] = current_cpu->GETMEMSI (pc, addr);
6991 if (ANDSI (FLD (f_reg_list), SLLSI (1, 5))) {
6993 addr = ADDSI (addr, 4);
6994 current_cpu->hardware.h_gr[((UINT) 5)] = current_cpu->GETMEMSI (pc, addr);
6997 if (ANDSI (FLD (f_reg_list), SLLSI (1, 6))) {
6999 addr = ADDSI (addr, 4);
7000 current_cpu->hardware.h_gr[((UINT) 6)] = current_cpu->GETMEMSI (pc, addr);
7003 if (ANDSI (FLD (f_reg_list), SLLSI (1, 7))) {
7005 addr = ADDSI (addr, 4);
7006 current_cpu->hardware.h_gr[((UINT) 7)] = current_cpu->GETMEMSI (pc, addr);
7009 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
7011 addr = ADDSI (addr, 4);
7012 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7013 current_cpu->hardware.h_gr[((UINT) 8)] = current_cpu->GETMEMSI (pc, addr);
7015 current_cpu->hardware.h_gr_usr[SUBSI (8, 8)] = current_cpu->GETMEMSI (pc, addr);
7019 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
7021 addr = ADDSI (addr, 4);
7022 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7023 current_cpu->hardware.h_gr[((UINT) 9)] = current_cpu->GETMEMSI (pc, addr);
7025 current_cpu->hardware.h_gr_usr[SUBSI (9, 8)] = current_cpu->GETMEMSI (pc, addr);
7029 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
7031 addr = ADDSI (addr, 4);
7032 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7033 current_cpu->hardware.h_gr[((UINT) 10)] = current_cpu->GETMEMSI (pc, addr);
7035 current_cpu->hardware.h_gr_usr[SUBSI (10, 8)] = current_cpu->GETMEMSI (pc, addr);
7039 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
7041 addr = ADDSI (addr, 4);
7042 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7043 current_cpu->hardware.h_gr[((UINT) 11)] = current_cpu->GETMEMSI (pc, addr);
7045 current_cpu->hardware.h_gr_usr[SUBSI (11, 8)] = current_cpu->GETMEMSI (pc, addr);
7049 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
7051 addr = ADDSI (addr, 4);
7052 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7053 current_cpu->hardware.h_gr[((UINT) 12)] = current_cpu->GETMEMSI (pc, addr);
7055 current_cpu->hardware.h_gr_usr[SUBSI (12, 8)] = current_cpu->GETMEMSI (pc, addr);
7059 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
7061 addr = ADDSI (addr, 4);
7062 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7063 current_cpu->hardware.h_gr[((UINT) 13)] = current_cpu->GETMEMSI (pc, addr);
7065 current_cpu->hardware.h_gr_usr[SUBSI (13, 8)] = current_cpu->GETMEMSI (pc, addr);
7069 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
7071 addr = ADDSI (addr, 4);
7072 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7073 current_cpu->hardware.h_gr[((UINT) 14)] = current_cpu->GETMEMSI (pc, addr);
7075 current_cpu->hardware.h_gr_usr[SUBSI (14, 8)] = current_cpu->GETMEMSI (pc, addr);
7079 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7081 addr = ADDSI (addr, 4);
7082 npc = current_cpu->GETMEMSI (pc, addr); br_status = BRANCH_UNCACHEABLE;
7083 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
7086 * FLD (i_rn) = addr;
7090 pbb_br_status = br_status;
7093 NEXT_INSN (vpc, fragpc);
7095 // ********** used only by: ldmia
7097 CASE (FRAG_LDMIA_MID):
7101 #define FLD(f) abuf->fields.sfmt_ldmda.f
7102 PCADDR pc = abuf->addr;
7103 br_status = BRANCH_UNTAKEN;
7104 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
7107 addr = * FLD (i_rn);
7108 if (ANDSI (FLD (f_reg_list), SLLSI (1, 0))) {
7110 current_cpu->hardware.h_gr[((UINT) 0)] = current_cpu->GETMEMSI (pc, addr);
7111 addr = ADDSI (addr, 4);
7114 if (ANDSI (FLD (f_reg_list), SLLSI (1, 1))) {
7116 current_cpu->hardware.h_gr[((UINT) 1)] = current_cpu->GETMEMSI (pc, addr);
7117 addr = ADDSI (addr, 4);
7120 if (ANDSI (FLD (f_reg_list), SLLSI (1, 2))) {
7122 current_cpu->hardware.h_gr[((UINT) 2)] = current_cpu->GETMEMSI (pc, addr);
7123 addr = ADDSI (addr, 4);
7126 if (ANDSI (FLD (f_reg_list), SLLSI (1, 3))) {
7128 current_cpu->hardware.h_gr[((UINT) 3)] = current_cpu->GETMEMSI (pc, addr);
7129 addr = ADDSI (addr, 4);
7132 if (ANDSI (FLD (f_reg_list), SLLSI (1, 4))) {
7134 current_cpu->hardware.h_gr[((UINT) 4)] = current_cpu->GETMEMSI (pc, addr);
7135 addr = ADDSI (addr, 4);
7138 if (ANDSI (FLD (f_reg_list), SLLSI (1, 5))) {
7140 current_cpu->hardware.h_gr[((UINT) 5)] = current_cpu->GETMEMSI (pc, addr);
7141 addr = ADDSI (addr, 4);
7144 if (ANDSI (FLD (f_reg_list), SLLSI (1, 6))) {
7146 current_cpu->hardware.h_gr[((UINT) 6)] = current_cpu->GETMEMSI (pc, addr);
7147 addr = ADDSI (addr, 4);
7150 if (ANDSI (FLD (f_reg_list), SLLSI (1, 7))) {
7152 current_cpu->hardware.h_gr[((UINT) 7)] = current_cpu->GETMEMSI (pc, addr);
7153 addr = ADDSI (addr, 4);
7156 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
7158 current_cpu->hardware.h_gr[((UINT) 8)] = current_cpu->GETMEMSI (pc, addr);
7159 addr = ADDSI (addr, 4);
7162 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
7164 current_cpu->hardware.h_gr[((UINT) 9)] = current_cpu->GETMEMSI (pc, addr);
7165 addr = ADDSI (addr, 4);
7168 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
7170 current_cpu->hardware.h_gr[((UINT) 10)] = current_cpu->GETMEMSI (pc, addr);
7171 addr = ADDSI (addr, 4);
7174 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
7176 current_cpu->hardware.h_gr[((UINT) 11)] = current_cpu->GETMEMSI (pc, addr);
7177 addr = ADDSI (addr, 4);
7180 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
7182 current_cpu->hardware.h_gr[((UINT) 12)] = current_cpu->GETMEMSI (pc, addr);
7183 addr = ADDSI (addr, 4);
7186 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
7188 current_cpu->hardware.h_gr[((UINT) 13)] = current_cpu->GETMEMSI (pc, addr);
7189 addr = ADDSI (addr, 4);
7192 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
7194 current_cpu->hardware.h_gr[((UINT) 14)] = current_cpu->GETMEMSI (pc, addr);
7195 addr = ADDSI (addr, 4);
7198 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7200 npc = current_cpu->GETMEMSI (pc, addr); br_status = BRANCH_UNCACHEABLE;
7201 addr = ADDSI (addr, 4);
7207 pbb_br_status = br_status;
7210 NEXT_INSN (vpc, fragpc);
7212 // ********** used only by: ldmia-sw
7214 CASE (FRAG_LDMIA_SW_MID):
7216 #define FLD(f) abuf->fields.sfmt_ldmda.f
7217 PCADDR pc = abuf->addr;
7220 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
7222 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7223 current_cpu->hardware.h_gr[((UINT) 8)] = current_cpu->GETMEMSI (pc, addr);
7225 current_cpu->hardware.h_gr_usr[SUBSI (8, 8)] = current_cpu->GETMEMSI (pc, addr);
7227 addr = ADDSI (addr, 4);
7230 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
7232 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7233 current_cpu->hardware.h_gr[((UINT) 9)] = current_cpu->GETMEMSI (pc, addr);
7235 current_cpu->hardware.h_gr_usr[SUBSI (9, 8)] = current_cpu->GETMEMSI (pc, addr);
7237 addr = ADDSI (addr, 4);
7240 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
7242 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7243 current_cpu->hardware.h_gr[((UINT) 10)] = current_cpu->GETMEMSI (pc, addr);
7245 current_cpu->hardware.h_gr_usr[SUBSI (10, 8)] = current_cpu->GETMEMSI (pc, addr);
7247 addr = ADDSI (addr, 4);
7250 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
7252 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7253 current_cpu->hardware.h_gr[((UINT) 11)] = current_cpu->GETMEMSI (pc, addr);
7255 current_cpu->hardware.h_gr_usr[SUBSI (11, 8)] = current_cpu->GETMEMSI (pc, addr);
7257 addr = ADDSI (addr, 4);
7260 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
7262 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7263 current_cpu->hardware.h_gr[((UINT) 12)] = current_cpu->GETMEMSI (pc, addr);
7265 current_cpu->hardware.h_gr_usr[SUBSI (12, 8)] = current_cpu->GETMEMSI (pc, addr);
7267 addr = ADDSI (addr, 4);
7270 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
7272 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7273 current_cpu->hardware.h_gr[((UINT) 13)] = current_cpu->GETMEMSI (pc, addr);
7275 current_cpu->hardware.h_gr_usr[SUBSI (13, 8)] = current_cpu->GETMEMSI (pc, addr);
7277 addr = ADDSI (addr, 4);
7280 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
7282 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7283 current_cpu->hardware.h_gr[((UINT) 14)] = current_cpu->GETMEMSI (pc, addr);
7285 current_cpu->hardware.h_gr_usr[SUBSI (14, 8)] = current_cpu->GETMEMSI (pc, addr);
7287 addr = ADDSI (addr, 4);
7290 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7292 npc = current_cpu->GETMEMSI (pc, addr); br_status = BRANCH_UNCACHEABLE;
7293 addr = ADDSI (addr, 4);
7294 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
7300 pbb_br_status = br_status;
7303 NEXT_INSN (vpc, fragpc);
7305 // ********** used only by: ldmia-wb
7307 CASE (FRAG_LDMIA_WB_MID):
7309 #define FLD(f) abuf->fields.sfmt_ldmda.f
7310 PCADDR pc = abuf->addr;
7313 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
7315 current_cpu->hardware.h_gr[((UINT) 8)] = current_cpu->GETMEMSI (pc, addr);
7316 addr = ADDSI (addr, 4);
7319 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
7321 current_cpu->hardware.h_gr[((UINT) 9)] = current_cpu->GETMEMSI (pc, addr);
7322 addr = ADDSI (addr, 4);
7325 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
7327 current_cpu->hardware.h_gr[((UINT) 10)] = current_cpu->GETMEMSI (pc, addr);
7328 addr = ADDSI (addr, 4);
7331 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
7333 current_cpu->hardware.h_gr[((UINT) 11)] = current_cpu->GETMEMSI (pc, addr);
7334 addr = ADDSI (addr, 4);
7337 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
7339 current_cpu->hardware.h_gr[((UINT) 12)] = current_cpu->GETMEMSI (pc, addr);
7340 addr = ADDSI (addr, 4);
7343 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
7345 current_cpu->hardware.h_gr[((UINT) 13)] = current_cpu->GETMEMSI (pc, addr);
7346 addr = ADDSI (addr, 4);
7349 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
7351 current_cpu->hardware.h_gr[((UINT) 14)] = current_cpu->GETMEMSI (pc, addr);
7352 addr = ADDSI (addr, 4);
7355 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7357 npc = current_cpu->GETMEMSI (pc, addr); br_status = BRANCH_UNCACHEABLE;
7358 addr = ADDSI (addr, 4);
7361 * FLD (i_rn) = addr;
7365 pbb_br_status = br_status;
7368 NEXT_INSN (vpc, fragpc);
7370 // ********** used only by: ldmia-sw-wb
7372 CASE (FRAG_LDMIA_SW_WB_MID):
7376 #define FLD(f) abuf->fields.sfmt_ldmda.f
7377 PCADDR pc = abuf->addr;
7378 br_status = BRANCH_UNTAKEN;
7379 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
7382 addr = * FLD (i_rn);
7383 if (ANDSI (FLD (f_reg_list), SLLSI (1, 0))) {
7385 current_cpu->hardware.h_gr[((UINT) 0)] = current_cpu->GETMEMSI (pc, addr);
7386 addr = ADDSI (addr, 4);
7389 if (ANDSI (FLD (f_reg_list), SLLSI (1, 1))) {
7391 current_cpu->hardware.h_gr[((UINT) 1)] = current_cpu->GETMEMSI (pc, addr);
7392 addr = ADDSI (addr, 4);
7395 if (ANDSI (FLD (f_reg_list), SLLSI (1, 2))) {
7397 current_cpu->hardware.h_gr[((UINT) 2)] = current_cpu->GETMEMSI (pc, addr);
7398 addr = ADDSI (addr, 4);
7401 if (ANDSI (FLD (f_reg_list), SLLSI (1, 3))) {
7403 current_cpu->hardware.h_gr[((UINT) 3)] = current_cpu->GETMEMSI (pc, addr);
7404 addr = ADDSI (addr, 4);
7407 if (ANDSI (FLD (f_reg_list), SLLSI (1, 4))) {
7409 current_cpu->hardware.h_gr[((UINT) 4)] = current_cpu->GETMEMSI (pc, addr);
7410 addr = ADDSI (addr, 4);
7413 if (ANDSI (FLD (f_reg_list), SLLSI (1, 5))) {
7415 current_cpu->hardware.h_gr[((UINT) 5)] = current_cpu->GETMEMSI (pc, addr);
7416 addr = ADDSI (addr, 4);
7419 if (ANDSI (FLD (f_reg_list), SLLSI (1, 6))) {
7421 current_cpu->hardware.h_gr[((UINT) 6)] = current_cpu->GETMEMSI (pc, addr);
7422 addr = ADDSI (addr, 4);
7425 if (ANDSI (FLD (f_reg_list), SLLSI (1, 7))) {
7427 current_cpu->hardware.h_gr[((UINT) 7)] = current_cpu->GETMEMSI (pc, addr);
7428 addr = ADDSI (addr, 4);
7431 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
7433 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7434 current_cpu->hardware.h_gr[((UINT) 8)] = current_cpu->GETMEMSI (pc, addr);
7436 current_cpu->hardware.h_gr_usr[SUBSI (8, 8)] = current_cpu->GETMEMSI (pc, addr);
7438 addr = ADDSI (addr, 4);
7441 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
7443 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7444 current_cpu->hardware.h_gr[((UINT) 9)] = current_cpu->GETMEMSI (pc, addr);
7446 current_cpu->hardware.h_gr_usr[SUBSI (9, 8)] = current_cpu->GETMEMSI (pc, addr);
7448 addr = ADDSI (addr, 4);
7451 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
7453 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7454 current_cpu->hardware.h_gr[((UINT) 10)] = current_cpu->GETMEMSI (pc, addr);
7456 current_cpu->hardware.h_gr_usr[SUBSI (10, 8)] = current_cpu->GETMEMSI (pc, addr);
7458 addr = ADDSI (addr, 4);
7461 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
7463 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7464 current_cpu->hardware.h_gr[((UINT) 11)] = current_cpu->GETMEMSI (pc, addr);
7466 current_cpu->hardware.h_gr_usr[SUBSI (11, 8)] = current_cpu->GETMEMSI (pc, addr);
7468 addr = ADDSI (addr, 4);
7471 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
7473 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7474 current_cpu->hardware.h_gr[((UINT) 12)] = current_cpu->GETMEMSI (pc, addr);
7476 current_cpu->hardware.h_gr_usr[SUBSI (12, 8)] = current_cpu->GETMEMSI (pc, addr);
7478 addr = ADDSI (addr, 4);
7481 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
7483 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7484 current_cpu->hardware.h_gr[((UINT) 13)] = current_cpu->GETMEMSI (pc, addr);
7486 current_cpu->hardware.h_gr_usr[SUBSI (13, 8)] = current_cpu->GETMEMSI (pc, addr);
7488 addr = ADDSI (addr, 4);
7491 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
7493 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7494 current_cpu->hardware.h_gr[((UINT) 14)] = current_cpu->GETMEMSI (pc, addr);
7496 current_cpu->hardware.h_gr_usr[SUBSI (14, 8)] = current_cpu->GETMEMSI (pc, addr);
7498 addr = ADDSI (addr, 4);
7501 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7503 npc = current_cpu->GETMEMSI (pc, addr); br_status = BRANCH_UNCACHEABLE;
7504 addr = ADDSI (addr, 4);
7505 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
7508 * FLD (i_rn) = addr;
7512 pbb_br_status = br_status;
7515 NEXT_INSN (vpc, fragpc);
7517 // ********** used only by: ldmdb
7519 CASE (FRAG_LDMDB_MID):
7523 #define FLD(f) abuf->fields.sfmt_ldmda.f
7524 PCADDR pc = abuf->addr;
7525 br_status = BRANCH_UNTAKEN;
7526 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
7529 addr = * FLD (i_rn);
7530 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7532 addr = SUBSI (addr, 4);
7533 npc = current_cpu->GETMEMSI (pc, addr); br_status = BRANCH_UNCACHEABLE;
7536 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
7538 addr = SUBSI (addr, 4);
7539 current_cpu->hardware.h_gr[((UINT) 14)] = current_cpu->GETMEMSI (pc, addr);
7542 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
7544 addr = SUBSI (addr, 4);
7545 current_cpu->hardware.h_gr[((UINT) 13)] = current_cpu->GETMEMSI (pc, addr);
7548 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
7550 addr = SUBSI (addr, 4);
7551 current_cpu->hardware.h_gr[((UINT) 12)] = current_cpu->GETMEMSI (pc, addr);
7554 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
7556 addr = SUBSI (addr, 4);
7557 current_cpu->hardware.h_gr[((UINT) 11)] = current_cpu->GETMEMSI (pc, addr);
7560 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
7562 addr = SUBSI (addr, 4);
7563 current_cpu->hardware.h_gr[((UINT) 10)] = current_cpu->GETMEMSI (pc, addr);
7566 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
7568 addr = SUBSI (addr, 4);
7569 current_cpu->hardware.h_gr[((UINT) 9)] = current_cpu->GETMEMSI (pc, addr);
7572 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
7574 addr = SUBSI (addr, 4);
7575 current_cpu->hardware.h_gr[((UINT) 8)] = current_cpu->GETMEMSI (pc, addr);
7578 if (ANDSI (FLD (f_reg_list), SLLSI (1, 7))) {
7580 addr = SUBSI (addr, 4);
7581 current_cpu->hardware.h_gr[((UINT) 7)] = current_cpu->GETMEMSI (pc, addr);
7584 if (ANDSI (FLD (f_reg_list), SLLSI (1, 6))) {
7586 addr = SUBSI (addr, 4);
7587 current_cpu->hardware.h_gr[((UINT) 6)] = current_cpu->GETMEMSI (pc, addr);
7590 if (ANDSI (FLD (f_reg_list), SLLSI (1, 5))) {
7592 addr = SUBSI (addr, 4);
7593 current_cpu->hardware.h_gr[((UINT) 5)] = current_cpu->GETMEMSI (pc, addr);
7596 if (ANDSI (FLD (f_reg_list), SLLSI (1, 4))) {
7598 addr = SUBSI (addr, 4);
7599 current_cpu->hardware.h_gr[((UINT) 4)] = current_cpu->GETMEMSI (pc, addr);
7602 if (ANDSI (FLD (f_reg_list), SLLSI (1, 3))) {
7604 addr = SUBSI (addr, 4);
7605 current_cpu->hardware.h_gr[((UINT) 3)] = current_cpu->GETMEMSI (pc, addr);
7608 if (ANDSI (FLD (f_reg_list), SLLSI (1, 2))) {
7610 addr = SUBSI (addr, 4);
7611 current_cpu->hardware.h_gr[((UINT) 2)] = current_cpu->GETMEMSI (pc, addr);
7614 if (ANDSI (FLD (f_reg_list), SLLSI (1, 1))) {
7616 addr = SUBSI (addr, 4);
7617 current_cpu->hardware.h_gr[((UINT) 1)] = current_cpu->GETMEMSI (pc, addr);
7620 if (ANDSI (FLD (f_reg_list), SLLSI (1, 0))) {
7622 addr = SUBSI (addr, 4);
7623 current_cpu->hardware.h_gr[((UINT) 0)] = current_cpu->GETMEMSI (pc, addr);
7629 pbb_br_status = br_status;
7632 NEXT_INSN (vpc, fragpc);
7634 // ********** used only by: ldmdb-sw
7636 CASE (FRAG_LDMDB_SW_MID):
7640 #define FLD(f) abuf->fields.sfmt_ldmda.f
7641 PCADDR pc = abuf->addr;
7642 br_status = BRANCH_UNTAKEN;
7643 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
7646 addr = * FLD (i_rn);
7647 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7649 addr = SUBSI (addr, 4);
7650 npc = current_cpu->GETMEMSI (pc, addr); br_status = BRANCH_UNCACHEABLE;
7651 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
7654 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
7656 addr = SUBSI (addr, 4);
7657 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7658 current_cpu->hardware.h_gr[((UINT) 14)] = current_cpu->GETMEMSI (pc, addr);
7660 current_cpu->hardware.h_gr_usr[SUBSI (14, 8)] = current_cpu->GETMEMSI (pc, addr);
7664 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
7666 addr = SUBSI (addr, 4);
7667 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7668 current_cpu->hardware.h_gr[((UINT) 13)] = current_cpu->GETMEMSI (pc, addr);
7670 current_cpu->hardware.h_gr_usr[SUBSI (13, 8)] = current_cpu->GETMEMSI (pc, addr);
7674 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
7676 addr = SUBSI (addr, 4);
7677 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7678 current_cpu->hardware.h_gr[((UINT) 12)] = current_cpu->GETMEMSI (pc, addr);
7680 current_cpu->hardware.h_gr_usr[SUBSI (12, 8)] = current_cpu->GETMEMSI (pc, addr);
7684 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
7686 addr = SUBSI (addr, 4);
7687 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7688 current_cpu->hardware.h_gr[((UINT) 11)] = current_cpu->GETMEMSI (pc, addr);
7690 current_cpu->hardware.h_gr_usr[SUBSI (11, 8)] = current_cpu->GETMEMSI (pc, addr);
7694 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
7696 addr = SUBSI (addr, 4);
7697 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7698 current_cpu->hardware.h_gr[((UINT) 10)] = current_cpu->GETMEMSI (pc, addr);
7700 current_cpu->hardware.h_gr_usr[SUBSI (10, 8)] = current_cpu->GETMEMSI (pc, addr);
7704 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
7706 addr = SUBSI (addr, 4);
7707 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7708 current_cpu->hardware.h_gr[((UINT) 9)] = current_cpu->GETMEMSI (pc, addr);
7710 current_cpu->hardware.h_gr_usr[SUBSI (9, 8)] = current_cpu->GETMEMSI (pc, addr);
7714 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
7716 addr = SUBSI (addr, 4);
7717 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7718 current_cpu->hardware.h_gr[((UINT) 8)] = current_cpu->GETMEMSI (pc, addr);
7720 current_cpu->hardware.h_gr_usr[SUBSI (8, 8)] = current_cpu->GETMEMSI (pc, addr);
7724 if (ANDSI (FLD (f_reg_list), SLLSI (1, 7))) {
7726 addr = SUBSI (addr, 4);
7727 current_cpu->hardware.h_gr[((UINT) 7)] = current_cpu->GETMEMSI (pc, addr);
7730 if (ANDSI (FLD (f_reg_list), SLLSI (1, 6))) {
7732 addr = SUBSI (addr, 4);
7733 current_cpu->hardware.h_gr[((UINT) 6)] = current_cpu->GETMEMSI (pc, addr);
7736 if (ANDSI (FLD (f_reg_list), SLLSI (1, 5))) {
7738 addr = SUBSI (addr, 4);
7739 current_cpu->hardware.h_gr[((UINT) 5)] = current_cpu->GETMEMSI (pc, addr);
7742 if (ANDSI (FLD (f_reg_list), SLLSI (1, 4))) {
7744 addr = SUBSI (addr, 4);
7745 current_cpu->hardware.h_gr[((UINT) 4)] = current_cpu->GETMEMSI (pc, addr);
7748 if (ANDSI (FLD (f_reg_list), SLLSI (1, 3))) {
7750 addr = SUBSI (addr, 4);
7751 current_cpu->hardware.h_gr[((UINT) 3)] = current_cpu->GETMEMSI (pc, addr);
7754 if (ANDSI (FLD (f_reg_list), SLLSI (1, 2))) {
7756 addr = SUBSI (addr, 4);
7757 current_cpu->hardware.h_gr[((UINT) 2)] = current_cpu->GETMEMSI (pc, addr);
7760 if (ANDSI (FLD (f_reg_list), SLLSI (1, 1))) {
7762 addr = SUBSI (addr, 4);
7763 current_cpu->hardware.h_gr[((UINT) 1)] = current_cpu->GETMEMSI (pc, addr);
7766 if (ANDSI (FLD (f_reg_list), SLLSI (1, 0))) {
7768 addr = SUBSI (addr, 4);
7769 current_cpu->hardware.h_gr[((UINT) 0)] = current_cpu->GETMEMSI (pc, addr);
7775 pbb_br_status = br_status;
7778 NEXT_INSN (vpc, fragpc);
7780 // ********** used only by: ldmdb-wb
7782 CASE (FRAG_LDMDB_WB_MID):
7786 #define FLD(f) abuf->fields.sfmt_ldmda.f
7787 PCADDR pc = abuf->addr;
7788 br_status = BRANCH_UNTAKEN;
7789 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
7792 addr = * FLD (i_rn);
7793 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7795 addr = SUBSI (addr, 4);
7796 npc = current_cpu->GETMEMSI (pc, addr); br_status = BRANCH_UNCACHEABLE;
7799 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
7801 addr = SUBSI (addr, 4);
7802 current_cpu->hardware.h_gr[((UINT) 14)] = current_cpu->GETMEMSI (pc, addr);
7805 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
7807 addr = SUBSI (addr, 4);
7808 current_cpu->hardware.h_gr[((UINT) 13)] = current_cpu->GETMEMSI (pc, addr);
7811 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
7813 addr = SUBSI (addr, 4);
7814 current_cpu->hardware.h_gr[((UINT) 12)] = current_cpu->GETMEMSI (pc, addr);
7817 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
7819 addr = SUBSI (addr, 4);
7820 current_cpu->hardware.h_gr[((UINT) 11)] = current_cpu->GETMEMSI (pc, addr);
7823 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
7825 addr = SUBSI (addr, 4);
7826 current_cpu->hardware.h_gr[((UINT) 10)] = current_cpu->GETMEMSI (pc, addr);
7829 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
7831 addr = SUBSI (addr, 4);
7832 current_cpu->hardware.h_gr[((UINT) 9)] = current_cpu->GETMEMSI (pc, addr);
7835 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
7837 addr = SUBSI (addr, 4);
7838 current_cpu->hardware.h_gr[((UINT) 8)] = current_cpu->GETMEMSI (pc, addr);
7841 if (ANDSI (FLD (f_reg_list), SLLSI (1, 7))) {
7843 addr = SUBSI (addr, 4);
7844 current_cpu->hardware.h_gr[((UINT) 7)] = current_cpu->GETMEMSI (pc, addr);
7847 if (ANDSI (FLD (f_reg_list), SLLSI (1, 6))) {
7849 addr = SUBSI (addr, 4);
7850 current_cpu->hardware.h_gr[((UINT) 6)] = current_cpu->GETMEMSI (pc, addr);
7853 if (ANDSI (FLD (f_reg_list), SLLSI (1, 5))) {
7855 addr = SUBSI (addr, 4);
7856 current_cpu->hardware.h_gr[((UINT) 5)] = current_cpu->GETMEMSI (pc, addr);
7859 if (ANDSI (FLD (f_reg_list), SLLSI (1, 4))) {
7861 addr = SUBSI (addr, 4);
7862 current_cpu->hardware.h_gr[((UINT) 4)] = current_cpu->GETMEMSI (pc, addr);
7865 if (ANDSI (FLD (f_reg_list), SLLSI (1, 3))) {
7867 addr = SUBSI (addr, 4);
7868 current_cpu->hardware.h_gr[((UINT) 3)] = current_cpu->GETMEMSI (pc, addr);
7871 if (ANDSI (FLD (f_reg_list), SLLSI (1, 2))) {
7873 addr = SUBSI (addr, 4);
7874 current_cpu->hardware.h_gr[((UINT) 2)] = current_cpu->GETMEMSI (pc, addr);
7877 if (ANDSI (FLD (f_reg_list), SLLSI (1, 1))) {
7879 addr = SUBSI (addr, 4);
7880 current_cpu->hardware.h_gr[((UINT) 1)] = current_cpu->GETMEMSI (pc, addr);
7883 if (ANDSI (FLD (f_reg_list), SLLSI (1, 0))) {
7885 addr = SUBSI (addr, 4);
7886 current_cpu->hardware.h_gr[((UINT) 0)] = current_cpu->GETMEMSI (pc, addr);
7889 * FLD (i_rn) = addr;
7893 pbb_br_status = br_status;
7896 NEXT_INSN (vpc, fragpc);
7898 // ********** used only by: ldmdb-sw-wb
7900 CASE (FRAG_LDMDB_SW_WB_MID):
7904 #define FLD(f) abuf->fields.sfmt_ldmda.f
7905 PCADDR pc = abuf->addr;
7906 br_status = BRANCH_UNTAKEN;
7907 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
7910 addr = * FLD (i_rn);
7911 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7913 addr = SUBSI (addr, 4);
7914 npc = current_cpu->GETMEMSI (pc, addr); br_status = BRANCH_UNCACHEABLE;
7915 current_cpu->h_cpsr_set (current_cpu->h_spsr_get ());
7918 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
7920 addr = SUBSI (addr, 4);
7921 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7922 current_cpu->hardware.h_gr[((UINT) 14)] = current_cpu->GETMEMSI (pc, addr);
7924 current_cpu->hardware.h_gr_usr[SUBSI (14, 8)] = current_cpu->GETMEMSI (pc, addr);
7928 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
7930 addr = SUBSI (addr, 4);
7931 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7932 current_cpu->hardware.h_gr[((UINT) 13)] = current_cpu->GETMEMSI (pc, addr);
7934 current_cpu->hardware.h_gr_usr[SUBSI (13, 8)] = current_cpu->GETMEMSI (pc, addr);
7938 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
7940 addr = SUBSI (addr, 4);
7941 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7942 current_cpu->hardware.h_gr[((UINT) 12)] = current_cpu->GETMEMSI (pc, addr);
7944 current_cpu->hardware.h_gr_usr[SUBSI (12, 8)] = current_cpu->GETMEMSI (pc, addr);
7948 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
7950 addr = SUBSI (addr, 4);
7951 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7952 current_cpu->hardware.h_gr[((UINT) 11)] = current_cpu->GETMEMSI (pc, addr);
7954 current_cpu->hardware.h_gr_usr[SUBSI (11, 8)] = current_cpu->GETMEMSI (pc, addr);
7958 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
7960 addr = SUBSI (addr, 4);
7961 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7962 current_cpu->hardware.h_gr[((UINT) 10)] = current_cpu->GETMEMSI (pc, addr);
7964 current_cpu->hardware.h_gr_usr[SUBSI (10, 8)] = current_cpu->GETMEMSI (pc, addr);
7968 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
7970 addr = SUBSI (addr, 4);
7971 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7972 current_cpu->hardware.h_gr[((UINT) 9)] = current_cpu->GETMEMSI (pc, addr);
7974 current_cpu->hardware.h_gr_usr[SUBSI (9, 8)] = current_cpu->GETMEMSI (pc, addr);
7978 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
7980 addr = SUBSI (addr, 4);
7981 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
7982 current_cpu->hardware.h_gr[((UINT) 8)] = current_cpu->GETMEMSI (pc, addr);
7984 current_cpu->hardware.h_gr_usr[SUBSI (8, 8)] = current_cpu->GETMEMSI (pc, addr);
7988 if (ANDSI (FLD (f_reg_list), SLLSI (1, 7))) {
7990 addr = SUBSI (addr, 4);
7991 current_cpu->hardware.h_gr[((UINT) 7)] = current_cpu->GETMEMSI (pc, addr);
7994 if (ANDSI (FLD (f_reg_list), SLLSI (1, 6))) {
7996 addr = SUBSI (addr, 4);
7997 current_cpu->hardware.h_gr[((UINT) 6)] = current_cpu->GETMEMSI (pc, addr);
8000 if (ANDSI (FLD (f_reg_list), SLLSI (1, 5))) {
8002 addr = SUBSI (addr, 4);
8003 current_cpu->hardware.h_gr[((UINT) 5)] = current_cpu->GETMEMSI (pc, addr);
8006 if (ANDSI (FLD (f_reg_list), SLLSI (1, 4))) {
8008 addr = SUBSI (addr, 4);
8009 current_cpu->hardware.h_gr[((UINT) 4)] = current_cpu->GETMEMSI (pc, addr);
8012 if (ANDSI (FLD (f_reg_list), SLLSI (1, 3))) {
8014 addr = SUBSI (addr, 4);
8015 current_cpu->hardware.h_gr[((UINT) 3)] = current_cpu->GETMEMSI (pc, addr);
8018 if (ANDSI (FLD (f_reg_list), SLLSI (1, 2))) {
8020 addr = SUBSI (addr, 4);
8021 current_cpu->hardware.h_gr[((UINT) 2)] = current_cpu->GETMEMSI (pc, addr);
8024 if (ANDSI (FLD (f_reg_list), SLLSI (1, 1))) {
8026 addr = SUBSI (addr, 4);
8027 current_cpu->hardware.h_gr[((UINT) 1)] = current_cpu->GETMEMSI (pc, addr);
8030 if (ANDSI (FLD (f_reg_list), SLLSI (1, 0))) {
8032 addr = SUBSI (addr, 4);
8033 current_cpu->hardware.h_gr[((UINT) 0)] = current_cpu->GETMEMSI (pc, addr);
8036 * FLD (i_rn) = addr;
8040 pbb_br_status = br_status;
8043 NEXT_INSN (vpc, fragpc);
8045 // ********** used only by: stmdb
8047 CASE (FRAG_STMDB_MID):
8051 #define FLD(f) abuf->fields.sfmt_ldmda.f
8052 PCADDR pc = abuf->addr;
8053 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
8056 addr = * FLD (i_rn);
8057 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8059 addr = SUBSI (addr, 4);
8060 current_cpu->SETMEMSI (pc, addr, ADDSI (current_cpu->hardware.h_gr[((UINT) 15)], 4));
8063 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
8065 addr = SUBSI (addr, 4);
8066 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 14)]);
8069 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
8071 addr = SUBSI (addr, 4);
8072 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 13)]);
8075 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
8077 addr = SUBSI (addr, 4);
8078 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 12)]);
8081 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
8083 addr = SUBSI (addr, 4);
8084 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 11)]);
8087 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
8089 addr = SUBSI (addr, 4);
8090 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 10)]);
8093 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
8095 addr = SUBSI (addr, 4);
8096 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 9)]);
8099 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
8101 addr = SUBSI (addr, 4);
8102 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 8)]);
8105 if (ANDSI (FLD (f_reg_list), SLLSI (1, 7))) {
8107 addr = SUBSI (addr, 4);
8108 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 7)]);
8111 if (ANDSI (FLD (f_reg_list), SLLSI (1, 6))) {
8113 addr = SUBSI (addr, 4);
8114 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 6)]);
8117 if (ANDSI (FLD (f_reg_list), SLLSI (1, 5))) {
8119 addr = SUBSI (addr, 4);
8120 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 5)]);
8123 if (ANDSI (FLD (f_reg_list), SLLSI (1, 4))) {
8125 addr = SUBSI (addr, 4);
8126 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 4)]);
8129 if (ANDSI (FLD (f_reg_list), SLLSI (1, 3))) {
8131 addr = SUBSI (addr, 4);
8132 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 3)]);
8135 if (ANDSI (FLD (f_reg_list), SLLSI (1, 2))) {
8137 addr = SUBSI (addr, 4);
8138 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 2)]);
8141 if (ANDSI (FLD (f_reg_list), SLLSI (1, 1))) {
8143 addr = SUBSI (addr, 4);
8144 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 1)]);
8147 if (ANDSI (FLD (f_reg_list), SLLSI (1, 0))) {
8149 addr = SUBSI (addr, 4);
8150 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 0)]);
8157 NEXT_INSN (vpc, fragpc);
8159 // ********** used only by: stmdb-sw
8161 CASE (FRAG_STMDB_SW_MID):
8163 #define FLD(f) abuf->fields.sfmt_ldmda.f
8164 PCADDR pc = abuf->addr;
8167 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
8169 addr = SUBSI (addr, 4);
8170 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8171 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 14)]);
8173 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (14, 8)]);
8177 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
8179 addr = SUBSI (addr, 4);
8180 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8181 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 13)]);
8183 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (13, 8)]);
8187 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
8189 addr = SUBSI (addr, 4);
8190 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8191 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 12)]);
8193 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (12, 8)]);
8197 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
8199 addr = SUBSI (addr, 4);
8200 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8201 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 11)]);
8203 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (11, 8)]);
8207 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
8209 addr = SUBSI (addr, 4);
8210 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8211 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 10)]);
8213 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (10, 8)]);
8217 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
8219 addr = SUBSI (addr, 4);
8220 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8221 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 9)]);
8223 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (9, 8)]);
8227 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
8229 addr = SUBSI (addr, 4);
8230 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8231 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 8)]);
8233 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (8, 8)]);
8237 if (ANDSI (FLD (f_reg_list), SLLSI (1, 7))) {
8239 addr = SUBSI (addr, 4);
8240 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 7)]);
8243 if (ANDSI (FLD (f_reg_list), SLLSI (1, 6))) {
8245 addr = SUBSI (addr, 4);
8246 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 6)]);
8249 if (ANDSI (FLD (f_reg_list), SLLSI (1, 5))) {
8251 addr = SUBSI (addr, 4);
8252 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 5)]);
8255 if (ANDSI (FLD (f_reg_list), SLLSI (1, 4))) {
8257 addr = SUBSI (addr, 4);
8258 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 4)]);
8261 if (ANDSI (FLD (f_reg_list), SLLSI (1, 3))) {
8263 addr = SUBSI (addr, 4);
8264 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 3)]);
8267 if (ANDSI (FLD (f_reg_list), SLLSI (1, 2))) {
8269 addr = SUBSI (addr, 4);
8270 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 2)]);
8273 if (ANDSI (FLD (f_reg_list), SLLSI (1, 1))) {
8275 addr = SUBSI (addr, 4);
8276 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 1)]);
8279 if (ANDSI (FLD (f_reg_list), SLLSI (1, 0))) {
8281 addr = SUBSI (addr, 4);
8282 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 0)]);
8289 NEXT_INSN (vpc, fragpc);
8291 // ********** used only by: stmdb-wb
8293 CASE (FRAG_STMDB_WB_MID):
8295 #define FLD(f) abuf->fields.sfmt_ldmda.f
8296 PCADDR pc = abuf->addr;
8299 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
8301 addr = SUBSI (addr, 4);
8302 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 14)]);
8305 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
8307 addr = SUBSI (addr, 4);
8308 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 13)]);
8311 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
8313 addr = SUBSI (addr, 4);
8314 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 12)]);
8317 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
8319 addr = SUBSI (addr, 4);
8320 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 11)]);
8323 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
8325 addr = SUBSI (addr, 4);
8326 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 10)]);
8329 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
8331 addr = SUBSI (addr, 4);
8332 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 9)]);
8335 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
8337 addr = SUBSI (addr, 4);
8338 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 8)]);
8341 if (ANDSI (FLD (f_reg_list), SLLSI (1, 7))) {
8343 addr = SUBSI (addr, 4);
8344 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 7)]);
8347 if (ANDSI (FLD (f_reg_list), SLLSI (1, 6))) {
8349 addr = SUBSI (addr, 4);
8350 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 6)]);
8353 if (ANDSI (FLD (f_reg_list), SLLSI (1, 5))) {
8355 addr = SUBSI (addr, 4);
8356 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 5)]);
8359 if (ANDSI (FLD (f_reg_list), SLLSI (1, 4))) {
8361 addr = SUBSI (addr, 4);
8362 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 4)]);
8365 if (ANDSI (FLD (f_reg_list), SLLSI (1, 3))) {
8367 addr = SUBSI (addr, 4);
8368 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 3)]);
8371 if (ANDSI (FLD (f_reg_list), SLLSI (1, 2))) {
8373 addr = SUBSI (addr, 4);
8374 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 2)]);
8377 if (ANDSI (FLD (f_reg_list), SLLSI (1, 1))) {
8379 addr = SUBSI (addr, 4);
8380 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 1)]);
8383 if (ANDSI (FLD (f_reg_list), SLLSI (1, 0))) {
8385 addr = SUBSI (addr, 4);
8386 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 0)]);
8389 * FLD (i_rn) = addr;
8394 NEXT_INSN (vpc, fragpc);
8396 // ********** used only by: stmdb-sw-wb
8398 CASE (FRAG_STMDB_SW_WB_MID):
8402 #define FLD(f) abuf->fields.sfmt_ldmda.f
8403 PCADDR pc = abuf->addr;
8404 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
8407 addr = * FLD (i_rn);
8408 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8410 addr = SUBSI (addr, 4);
8411 current_cpu->SETMEMSI (pc, addr, ADDSI (current_cpu->hardware.h_gr[((UINT) 15)], 4));
8414 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
8416 addr = SUBSI (addr, 4);
8417 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8418 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 14)]);
8420 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (14, 8)]);
8424 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
8426 addr = SUBSI (addr, 4);
8427 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8428 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 13)]);
8430 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (13, 8)]);
8434 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
8436 addr = SUBSI (addr, 4);
8437 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8438 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 12)]);
8440 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (12, 8)]);
8444 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
8446 addr = SUBSI (addr, 4);
8447 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8448 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 11)]);
8450 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (11, 8)]);
8454 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
8456 addr = SUBSI (addr, 4);
8457 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8458 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 10)]);
8460 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (10, 8)]);
8464 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
8466 addr = SUBSI (addr, 4);
8467 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8468 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 9)]);
8470 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (9, 8)]);
8474 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
8476 addr = SUBSI (addr, 4);
8477 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8478 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 8)]);
8480 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (8, 8)]);
8484 if (ANDSI (FLD (f_reg_list), SLLSI (1, 7))) {
8486 addr = SUBSI (addr, 4);
8487 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 7)]);
8490 if (ANDSI (FLD (f_reg_list), SLLSI (1, 6))) {
8492 addr = SUBSI (addr, 4);
8493 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 6)]);
8496 if (ANDSI (FLD (f_reg_list), SLLSI (1, 5))) {
8498 addr = SUBSI (addr, 4);
8499 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 5)]);
8502 if (ANDSI (FLD (f_reg_list), SLLSI (1, 4))) {
8504 addr = SUBSI (addr, 4);
8505 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 4)]);
8508 if (ANDSI (FLD (f_reg_list), SLLSI (1, 3))) {
8510 addr = SUBSI (addr, 4);
8511 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 3)]);
8514 if (ANDSI (FLD (f_reg_list), SLLSI (1, 2))) {
8516 addr = SUBSI (addr, 4);
8517 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 2)]);
8520 if (ANDSI (FLD (f_reg_list), SLLSI (1, 1))) {
8522 addr = SUBSI (addr, 4);
8523 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 1)]);
8526 if (ANDSI (FLD (f_reg_list), SLLSI (1, 0))) {
8528 addr = SUBSI (addr, 4);
8529 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 0)]);
8532 * FLD (i_rn) = addr;
8537 NEXT_INSN (vpc, fragpc);
8539 // ********** used only by: stmib
8541 CASE (FRAG_STMIB_MID):
8545 #define FLD(f) abuf->fields.sfmt_ldmda.f
8546 PCADDR pc = abuf->addr;
8547 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
8550 addr = * FLD (i_rn);
8551 if (ANDSI (FLD (f_reg_list), SLLSI (1, 0))) {
8553 addr = ADDSI (addr, 4);
8554 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 0)]);
8557 if (ANDSI (FLD (f_reg_list), SLLSI (1, 1))) {
8559 addr = ADDSI (addr, 4);
8560 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 1)]);
8563 if (ANDSI (FLD (f_reg_list), SLLSI (1, 2))) {
8565 addr = ADDSI (addr, 4);
8566 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 2)]);
8569 if (ANDSI (FLD (f_reg_list), SLLSI (1, 3))) {
8571 addr = ADDSI (addr, 4);
8572 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 3)]);
8575 if (ANDSI (FLD (f_reg_list), SLLSI (1, 4))) {
8577 addr = ADDSI (addr, 4);
8578 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 4)]);
8581 if (ANDSI (FLD (f_reg_list), SLLSI (1, 5))) {
8583 addr = ADDSI (addr, 4);
8584 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 5)]);
8587 if (ANDSI (FLD (f_reg_list), SLLSI (1, 6))) {
8589 addr = ADDSI (addr, 4);
8590 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 6)]);
8593 if (ANDSI (FLD (f_reg_list), SLLSI (1, 7))) {
8595 addr = ADDSI (addr, 4);
8596 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 7)]);
8599 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
8601 addr = ADDSI (addr, 4);
8602 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 8)]);
8605 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
8607 addr = ADDSI (addr, 4);
8608 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 9)]);
8611 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
8613 addr = ADDSI (addr, 4);
8614 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 10)]);
8617 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
8619 addr = ADDSI (addr, 4);
8620 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 11)]);
8623 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
8625 addr = ADDSI (addr, 4);
8626 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 12)]);
8629 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
8631 addr = ADDSI (addr, 4);
8632 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 13)]);
8635 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
8637 addr = ADDSI (addr, 4);
8638 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 14)]);
8641 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8643 addr = ADDSI (addr, 4);
8644 current_cpu->SETMEMSI (pc, addr, ADDSI (current_cpu->hardware.h_gr[((UINT) 15)], 4));
8651 NEXT_INSN (vpc, fragpc);
8653 // ********** used only by: stmib-sw
8655 CASE (FRAG_STMIB_SW_MID):
8657 #define FLD(f) abuf->fields.sfmt_ldmda.f
8658 PCADDR pc = abuf->addr;
8661 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
8663 addr = ADDSI (addr, 4);
8664 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8665 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 8)]);
8667 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (8, 8)]);
8671 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
8673 addr = ADDSI (addr, 4);
8674 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8675 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 9)]);
8677 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (9, 8)]);
8681 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
8683 addr = ADDSI (addr, 4);
8684 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8685 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 10)]);
8687 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (10, 8)]);
8691 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
8693 addr = ADDSI (addr, 4);
8694 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8695 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 11)]);
8697 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (11, 8)]);
8701 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
8703 addr = ADDSI (addr, 4);
8704 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8705 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 12)]);
8707 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (12, 8)]);
8711 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
8713 addr = ADDSI (addr, 4);
8714 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8715 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 13)]);
8717 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (13, 8)]);
8721 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
8723 addr = ADDSI (addr, 4);
8724 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8725 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 14)]);
8727 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (14, 8)]);
8731 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8733 addr = ADDSI (addr, 4);
8734 current_cpu->SETMEMSI (pc, addr, ADDSI (current_cpu->hardware.h_gr[((UINT) 15)], 4));
8741 NEXT_INSN (vpc, fragpc);
8743 // ********** used only by: stmib-wb
8745 CASE (FRAG_STMIB_WB_MID):
8747 #define FLD(f) abuf->fields.sfmt_ldmda.f
8748 PCADDR pc = abuf->addr;
8751 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
8753 addr = ADDSI (addr, 4);
8754 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 8)]);
8757 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
8759 addr = ADDSI (addr, 4);
8760 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 9)]);
8763 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
8765 addr = ADDSI (addr, 4);
8766 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 10)]);
8769 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
8771 addr = ADDSI (addr, 4);
8772 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 11)]);
8775 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
8777 addr = ADDSI (addr, 4);
8778 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 12)]);
8781 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
8783 addr = ADDSI (addr, 4);
8784 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 13)]);
8787 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
8789 addr = ADDSI (addr, 4);
8790 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 14)]);
8793 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8795 addr = ADDSI (addr, 4);
8796 current_cpu->SETMEMSI (pc, addr, ADDSI (current_cpu->hardware.h_gr[((UINT) 15)], 4));
8799 * FLD (i_rn) = addr;
8804 NEXT_INSN (vpc, fragpc);
8806 // ********** used only by: stmib-sw-wb
8808 CASE (FRAG_STMIB_SW_WB_MID):
8812 #define FLD(f) abuf->fields.sfmt_ldmda.f
8813 PCADDR pc = abuf->addr;
8814 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
8817 addr = * FLD (i_rn);
8818 if (ANDSI (FLD (f_reg_list), SLLSI (1, 0))) {
8820 addr = ADDSI (addr, 4);
8821 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 0)]);
8824 if (ANDSI (FLD (f_reg_list), SLLSI (1, 1))) {
8826 addr = ADDSI (addr, 4);
8827 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 1)]);
8830 if (ANDSI (FLD (f_reg_list), SLLSI (1, 2))) {
8832 addr = ADDSI (addr, 4);
8833 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 2)]);
8836 if (ANDSI (FLD (f_reg_list), SLLSI (1, 3))) {
8838 addr = ADDSI (addr, 4);
8839 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 3)]);
8842 if (ANDSI (FLD (f_reg_list), SLLSI (1, 4))) {
8844 addr = ADDSI (addr, 4);
8845 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 4)]);
8848 if (ANDSI (FLD (f_reg_list), SLLSI (1, 5))) {
8850 addr = ADDSI (addr, 4);
8851 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 5)]);
8854 if (ANDSI (FLD (f_reg_list), SLLSI (1, 6))) {
8856 addr = ADDSI (addr, 4);
8857 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 6)]);
8860 if (ANDSI (FLD (f_reg_list), SLLSI (1, 7))) {
8862 addr = ADDSI (addr, 4);
8863 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 7)]);
8866 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
8868 addr = ADDSI (addr, 4);
8869 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8870 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 8)]);
8872 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (8, 8)]);
8876 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
8878 addr = ADDSI (addr, 4);
8879 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8880 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 9)]);
8882 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (9, 8)]);
8886 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
8888 addr = ADDSI (addr, 4);
8889 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8890 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 10)]);
8892 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (10, 8)]);
8896 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
8898 addr = ADDSI (addr, 4);
8899 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8900 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 11)]);
8902 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (11, 8)]);
8906 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
8908 addr = ADDSI (addr, 4);
8909 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8910 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 12)]);
8912 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (12, 8)]);
8916 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
8918 addr = ADDSI (addr, 4);
8919 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8920 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 13)]);
8922 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (13, 8)]);
8926 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
8928 addr = ADDSI (addr, 4);
8929 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8930 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 14)]);
8932 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (14, 8)]);
8936 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
8938 addr = ADDSI (addr, 4);
8939 current_cpu->SETMEMSI (pc, addr, ADDSI (current_cpu->hardware.h_gr[((UINT) 15)], 4));
8942 * FLD (i_rn) = addr;
8947 NEXT_INSN (vpc, fragpc);
8949 // ********** used only by: stmia
8951 CASE (FRAG_STMIA_MID):
8955 #define FLD(f) abuf->fields.sfmt_ldmda.f
8956 PCADDR pc = abuf->addr;
8957 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
8960 addr = * FLD (i_rn);
8961 if (ANDSI (FLD (f_reg_list), SLLSI (1, 0))) {
8963 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 0)]);
8964 addr = ADDSI (addr, 4);
8967 if (ANDSI (FLD (f_reg_list), SLLSI (1, 1))) {
8969 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 1)]);
8970 addr = ADDSI (addr, 4);
8973 if (ANDSI (FLD (f_reg_list), SLLSI (1, 2))) {
8975 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 2)]);
8976 addr = ADDSI (addr, 4);
8979 if (ANDSI (FLD (f_reg_list), SLLSI (1, 3))) {
8981 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 3)]);
8982 addr = ADDSI (addr, 4);
8985 if (ANDSI (FLD (f_reg_list), SLLSI (1, 4))) {
8987 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 4)]);
8988 addr = ADDSI (addr, 4);
8991 if (ANDSI (FLD (f_reg_list), SLLSI (1, 5))) {
8993 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 5)]);
8994 addr = ADDSI (addr, 4);
8997 if (ANDSI (FLD (f_reg_list), SLLSI (1, 6))) {
8999 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 6)]);
9000 addr = ADDSI (addr, 4);
9003 if (ANDSI (FLD (f_reg_list), SLLSI (1, 7))) {
9005 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 7)]);
9006 addr = ADDSI (addr, 4);
9009 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
9011 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 8)]);
9012 addr = ADDSI (addr, 4);
9015 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
9017 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 9)]);
9018 addr = ADDSI (addr, 4);
9021 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
9023 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 10)]);
9024 addr = ADDSI (addr, 4);
9027 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
9029 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 11)]);
9030 addr = ADDSI (addr, 4);
9033 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
9035 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 12)]);
9036 addr = ADDSI (addr, 4);
9039 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
9041 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 13)]);
9042 addr = ADDSI (addr, 4);
9045 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
9047 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 14)]);
9048 addr = ADDSI (addr, 4);
9051 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9053 current_cpu->SETMEMSI (pc, addr, ADDSI (current_cpu->hardware.h_gr[((UINT) 15)], 4));
9054 addr = ADDSI (addr, 4);
9061 NEXT_INSN (vpc, fragpc);
9063 // ********** used only by: stmia-sw
9065 CASE (FRAG_STMIA_SW_MID):
9067 #define FLD(f) abuf->fields.sfmt_ldmda.f
9068 PCADDR pc = abuf->addr;
9071 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
9073 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9074 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 8)]);
9076 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (8, 8)]);
9078 addr = ADDSI (addr, 4);
9081 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
9083 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9084 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 9)]);
9086 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (9, 8)]);
9088 addr = ADDSI (addr, 4);
9091 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
9093 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9094 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 10)]);
9096 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (10, 8)]);
9098 addr = ADDSI (addr, 4);
9101 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
9103 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9104 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 11)]);
9106 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (11, 8)]);
9108 addr = ADDSI (addr, 4);
9111 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
9113 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9114 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 12)]);
9116 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (12, 8)]);
9118 addr = ADDSI (addr, 4);
9121 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
9123 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9124 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 13)]);
9126 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (13, 8)]);
9128 addr = ADDSI (addr, 4);
9131 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
9133 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9134 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 14)]);
9136 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (14, 8)]);
9138 addr = ADDSI (addr, 4);
9141 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9143 current_cpu->SETMEMSI (pc, addr, ADDSI (current_cpu->hardware.h_gr[((UINT) 15)], 4));
9144 addr = ADDSI (addr, 4);
9151 NEXT_INSN (vpc, fragpc);
9153 // ********** used only by: stmia-wb
9155 CASE (FRAG_STMIA_WB_MID):
9157 #define FLD(f) abuf->fields.sfmt_ldmda.f
9158 PCADDR pc = abuf->addr;
9161 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
9163 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 8)]);
9164 addr = ADDSI (addr, 4);
9167 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
9169 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 9)]);
9170 addr = ADDSI (addr, 4);
9173 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
9175 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 10)]);
9176 addr = ADDSI (addr, 4);
9179 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
9181 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 11)]);
9182 addr = ADDSI (addr, 4);
9185 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
9187 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 12)]);
9188 addr = ADDSI (addr, 4);
9191 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
9193 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 13)]);
9194 addr = ADDSI (addr, 4);
9197 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
9199 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 14)]);
9200 addr = ADDSI (addr, 4);
9203 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9205 current_cpu->SETMEMSI (pc, addr, ADDSI (current_cpu->hardware.h_gr[((UINT) 15)], 4));
9206 addr = ADDSI (addr, 4);
9209 * FLD (i_rn) = addr;
9214 NEXT_INSN (vpc, fragpc);
9216 // ********** used only by: stmia-sw-wb
9218 CASE (FRAG_STMIA_SW_WB_MID):
9222 #define FLD(f) abuf->fields.sfmt_ldmda.f
9223 PCADDR pc = abuf->addr;
9224 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
9227 addr = * FLD (i_rn);
9228 if (ANDSI (FLD (f_reg_list), SLLSI (1, 0))) {
9230 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 0)]);
9231 addr = ADDSI (addr, 4);
9234 if (ANDSI (FLD (f_reg_list), SLLSI (1, 1))) {
9236 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 1)]);
9237 addr = ADDSI (addr, 4);
9240 if (ANDSI (FLD (f_reg_list), SLLSI (1, 2))) {
9242 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 2)]);
9243 addr = ADDSI (addr, 4);
9246 if (ANDSI (FLD (f_reg_list), SLLSI (1, 3))) {
9248 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 3)]);
9249 addr = ADDSI (addr, 4);
9252 if (ANDSI (FLD (f_reg_list), SLLSI (1, 4))) {
9254 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 4)]);
9255 addr = ADDSI (addr, 4);
9258 if (ANDSI (FLD (f_reg_list), SLLSI (1, 5))) {
9260 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 5)]);
9261 addr = ADDSI (addr, 4);
9264 if (ANDSI (FLD (f_reg_list), SLLSI (1, 6))) {
9266 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 6)]);
9267 addr = ADDSI (addr, 4);
9270 if (ANDSI (FLD (f_reg_list), SLLSI (1, 7))) {
9272 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 7)]);
9273 addr = ADDSI (addr, 4);
9276 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
9278 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9279 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 8)]);
9281 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (8, 8)]);
9283 addr = ADDSI (addr, 4);
9286 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
9288 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9289 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 9)]);
9291 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (9, 8)]);
9293 addr = ADDSI (addr, 4);
9296 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
9298 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9299 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 10)]);
9301 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (10, 8)]);
9303 addr = ADDSI (addr, 4);
9306 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
9308 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9309 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 11)]);
9311 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (11, 8)]);
9313 addr = ADDSI (addr, 4);
9316 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
9318 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9319 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 12)]);
9321 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (12, 8)]);
9323 addr = ADDSI (addr, 4);
9326 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
9328 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9329 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 13)]);
9331 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (13, 8)]);
9333 addr = ADDSI (addr, 4);
9336 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
9338 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9339 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 14)]);
9341 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (14, 8)]);
9343 addr = ADDSI (addr, 4);
9346 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9348 current_cpu->SETMEMSI (pc, addr, ADDSI (current_cpu->hardware.h_gr[((UINT) 15)], 4));
9349 addr = ADDSI (addr, 4);
9352 * FLD (i_rn) = addr;
9357 NEXT_INSN (vpc, fragpc);
9359 // ********** used only by: stmda
9361 CASE (FRAG_STMDA_MID):
9365 #define FLD(f) abuf->fields.sfmt_ldmda.f
9366 PCADDR pc = abuf->addr;
9367 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
9370 addr = * FLD (i_rn);
9371 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9373 current_cpu->SETMEMSI (pc, addr, ADDSI (current_cpu->hardware.h_gr[((UINT) 15)], 4));
9374 addr = SUBSI (addr, 4);
9377 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
9379 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 14)]);
9380 addr = SUBSI (addr, 4);
9383 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
9385 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 13)]);
9386 addr = SUBSI (addr, 4);
9389 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
9391 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 12)]);
9392 addr = SUBSI (addr, 4);
9395 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
9397 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 11)]);
9398 addr = SUBSI (addr, 4);
9401 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
9403 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 10)]);
9404 addr = SUBSI (addr, 4);
9407 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
9409 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 9)]);
9410 addr = SUBSI (addr, 4);
9413 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
9415 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 8)]);
9416 addr = SUBSI (addr, 4);
9419 if (ANDSI (FLD (f_reg_list), SLLSI (1, 7))) {
9421 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 7)]);
9422 addr = SUBSI (addr, 4);
9425 if (ANDSI (FLD (f_reg_list), SLLSI (1, 6))) {
9427 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 6)]);
9428 addr = SUBSI (addr, 4);
9431 if (ANDSI (FLD (f_reg_list), SLLSI (1, 5))) {
9433 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 5)]);
9434 addr = SUBSI (addr, 4);
9437 if (ANDSI (FLD (f_reg_list), SLLSI (1, 4))) {
9439 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 4)]);
9440 addr = SUBSI (addr, 4);
9443 if (ANDSI (FLD (f_reg_list), SLLSI (1, 3))) {
9445 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 3)]);
9446 addr = SUBSI (addr, 4);
9449 if (ANDSI (FLD (f_reg_list), SLLSI (1, 2))) {
9451 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 2)]);
9452 addr = SUBSI (addr, 4);
9455 if (ANDSI (FLD (f_reg_list), SLLSI (1, 1))) {
9457 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 1)]);
9458 addr = SUBSI (addr, 4);
9461 if (ANDSI (FLD (f_reg_list), SLLSI (1, 0))) {
9463 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 0)]);
9464 addr = SUBSI (addr, 4);
9471 NEXT_INSN (vpc, fragpc);
9473 // ********** used only by: stmda-sw
9475 CASE (FRAG_STMDA_SW_MID):
9477 #define FLD(f) abuf->fields.sfmt_ldmda.f
9478 PCADDR pc = abuf->addr;
9481 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
9483 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9484 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 14)]);
9486 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (14, 8)]);
9488 addr = SUBSI (addr, 4);
9491 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
9493 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9494 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 13)]);
9496 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (13, 8)]);
9498 addr = SUBSI (addr, 4);
9501 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
9503 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9504 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 12)]);
9506 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (12, 8)]);
9508 addr = SUBSI (addr, 4);
9511 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
9513 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9514 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 11)]);
9516 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (11, 8)]);
9518 addr = SUBSI (addr, 4);
9521 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
9523 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9524 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 10)]);
9526 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (10, 8)]);
9528 addr = SUBSI (addr, 4);
9531 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
9533 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9534 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 9)]);
9536 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (9, 8)]);
9538 addr = SUBSI (addr, 4);
9541 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
9543 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9544 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 8)]);
9546 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (8, 8)]);
9548 addr = SUBSI (addr, 4);
9551 if (ANDSI (FLD (f_reg_list), SLLSI (1, 7))) {
9553 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 7)]);
9554 addr = SUBSI (addr, 4);
9557 if (ANDSI (FLD (f_reg_list), SLLSI (1, 6))) {
9559 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 6)]);
9560 addr = SUBSI (addr, 4);
9563 if (ANDSI (FLD (f_reg_list), SLLSI (1, 5))) {
9565 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 5)]);
9566 addr = SUBSI (addr, 4);
9569 if (ANDSI (FLD (f_reg_list), SLLSI (1, 4))) {
9571 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 4)]);
9572 addr = SUBSI (addr, 4);
9575 if (ANDSI (FLD (f_reg_list), SLLSI (1, 3))) {
9577 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 3)]);
9578 addr = SUBSI (addr, 4);
9581 if (ANDSI (FLD (f_reg_list), SLLSI (1, 2))) {
9583 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 2)]);
9584 addr = SUBSI (addr, 4);
9587 if (ANDSI (FLD (f_reg_list), SLLSI (1, 1))) {
9589 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 1)]);
9590 addr = SUBSI (addr, 4);
9593 if (ANDSI (FLD (f_reg_list), SLLSI (1, 0))) {
9595 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 0)]);
9596 addr = SUBSI (addr, 4);
9603 NEXT_INSN (vpc, fragpc);
9605 // ********** used only by: stmda-wb
9607 CASE (FRAG_STMDA_WB_MID):
9609 #define FLD(f) abuf->fields.sfmt_ldmda.f
9610 PCADDR pc = abuf->addr;
9613 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
9615 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 14)]);
9616 addr = SUBSI (addr, 4);
9619 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
9621 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 13)]);
9622 addr = SUBSI (addr, 4);
9625 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
9627 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 12)]);
9628 addr = SUBSI (addr, 4);
9631 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
9633 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 11)]);
9634 addr = SUBSI (addr, 4);
9637 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
9639 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 10)]);
9640 addr = SUBSI (addr, 4);
9643 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
9645 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 9)]);
9646 addr = SUBSI (addr, 4);
9649 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
9651 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 8)]);
9652 addr = SUBSI (addr, 4);
9655 if (ANDSI (FLD (f_reg_list), SLLSI (1, 7))) {
9657 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 7)]);
9658 addr = SUBSI (addr, 4);
9661 if (ANDSI (FLD (f_reg_list), SLLSI (1, 6))) {
9663 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 6)]);
9664 addr = SUBSI (addr, 4);
9667 if (ANDSI (FLD (f_reg_list), SLLSI (1, 5))) {
9669 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 5)]);
9670 addr = SUBSI (addr, 4);
9673 if (ANDSI (FLD (f_reg_list), SLLSI (1, 4))) {
9675 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 4)]);
9676 addr = SUBSI (addr, 4);
9679 if (ANDSI (FLD (f_reg_list), SLLSI (1, 3))) {
9681 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 3)]);
9682 addr = SUBSI (addr, 4);
9685 if (ANDSI (FLD (f_reg_list), SLLSI (1, 2))) {
9687 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 2)]);
9688 addr = SUBSI (addr, 4);
9691 if (ANDSI (FLD (f_reg_list), SLLSI (1, 1))) {
9693 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 1)]);
9694 addr = SUBSI (addr, 4);
9697 if (ANDSI (FLD (f_reg_list), SLLSI (1, 0))) {
9699 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 0)]);
9700 addr = SUBSI (addr, 4);
9703 * FLD (i_rn) = addr;
9708 NEXT_INSN (vpc, fragpc);
9710 // ********** used only by: stmda-sw-wb
9712 CASE (FRAG_STMDA_SW_WB_MID):
9716 #define FLD(f) abuf->fields.sfmt_ldmda.f
9717 PCADDR pc = abuf->addr;
9718 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
9721 addr = * FLD (i_rn);
9722 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9724 current_cpu->SETMEMSI (pc, addr, ADDSI (current_cpu->hardware.h_gr[((UINT) 15)], 4));
9725 addr = SUBSI (addr, 4);
9728 if (ANDSI (FLD (f_reg_list), SLLSI (1, 14))) {
9730 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9731 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 14)]);
9733 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (14, 8)]);
9735 addr = SUBSI (addr, 4);
9738 if (ANDSI (FLD (f_reg_list), SLLSI (1, 13))) {
9740 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9741 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 13)]);
9743 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (13, 8)]);
9745 addr = SUBSI (addr, 4);
9748 if (ANDSI (FLD (f_reg_list), SLLSI (1, 12))) {
9750 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9751 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 12)]);
9753 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (12, 8)]);
9755 addr = SUBSI (addr, 4);
9758 if (ANDSI (FLD (f_reg_list), SLLSI (1, 11))) {
9760 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9761 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 11)]);
9763 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (11, 8)]);
9765 addr = SUBSI (addr, 4);
9768 if (ANDSI (FLD (f_reg_list), SLLSI (1, 10))) {
9770 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9771 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 10)]);
9773 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (10, 8)]);
9775 addr = SUBSI (addr, 4);
9778 if (ANDSI (FLD (f_reg_list), SLLSI (1, 9))) {
9780 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9781 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 9)]);
9783 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (9, 8)]);
9785 addr = SUBSI (addr, 4);
9788 if (ANDSI (FLD (f_reg_list), SLLSI (1, 8))) {
9790 if (ANDSI (FLD (f_reg_list), SLLSI (1, 15))) {
9791 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 8)]);
9793 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr_usr[SUBSI (8, 8)]);
9795 addr = SUBSI (addr, 4);
9798 if (ANDSI (FLD (f_reg_list), SLLSI (1, 7))) {
9800 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 7)]);
9801 addr = SUBSI (addr, 4);
9804 if (ANDSI (FLD (f_reg_list), SLLSI (1, 6))) {
9806 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 6)]);
9807 addr = SUBSI (addr, 4);
9810 if (ANDSI (FLD (f_reg_list), SLLSI (1, 5))) {
9812 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 5)]);
9813 addr = SUBSI (addr, 4);
9816 if (ANDSI (FLD (f_reg_list), SLLSI (1, 4))) {
9818 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 4)]);
9819 addr = SUBSI (addr, 4);
9822 if (ANDSI (FLD (f_reg_list), SLLSI (1, 3))) {
9824 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 3)]);
9825 addr = SUBSI (addr, 4);
9828 if (ANDSI (FLD (f_reg_list), SLLSI (1, 2))) {
9830 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 2)]);
9831 addr = SUBSI (addr, 4);
9834 if (ANDSI (FLD (f_reg_list), SLLSI (1, 1))) {
9836 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 1)]);
9837 addr = SUBSI (addr, 4);
9840 if (ANDSI (FLD (f_reg_list), SLLSI (1, 0))) {
9842 current_cpu->SETMEMSI (pc, addr, current_cpu->hardware.h_gr[((UINT) 0)]);
9843 addr = SUBSI (addr, 4);
9846 * FLD (i_rn) = addr;
9851 NEXT_INSN (vpc, fragpc);
9853 // ********** used only by: mrs-c
9855 CASE (FRAG_MRS_C_MID):
9859 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
9860 PCADDR pc = abuf->addr;
9861 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
9864 * FLD (i_rd) = current_cpu->h_cpsr_get ();
9869 NEXT_INSN (vpc, fragpc);
9871 // ********** used only by: mrs-s
9873 CASE (FRAG_MRS_S_MID):
9877 #define FLD(f) abuf->fields.sfmt_strh_pre_dec_imm_offset.f
9878 PCADDR pc = abuf->addr;
9879 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
9882 * FLD (i_rd) = current_cpu->h_spsr_get ();
9887 NEXT_INSN (vpc, fragpc);
9889 // ********** used only by: msr-c
9891 CASE (FRAG_MSR_C_MID):
9895 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
9896 PCADDR pc = abuf->addr;
9897 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
9900 current_cpu->h_cpsr_set (* FLD (i_rm));
9905 NEXT_INSN (vpc, fragpc);
9907 // ********** used only by: msr-s
9909 CASE (FRAG_MSR_S_MID):
9913 #define FLD(f) abuf->fields.sfmt_and_reg_imm_shift.f
9914 PCADDR pc = abuf->addr;
9915 current_cpu->hardware.h_gr[((UINT) 15)] = ADDSI (pc, GET_ATTR (R15_OFFSET));
9918 current_cpu->h_spsr_set (* FLD (i_rm));
9923 NEXT_INSN (vpc, fragpc);
9934 // Save vpc for next time.
9935 current_cpu->arm_engine.set_next_vpc (vpc);