1 /* CPU class elements for sh5.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 2000-2009 Red Hat, Inc.
7 This file is part of the Red Hat simulators.
12 // This file is included in the middle of the cpu class struct.
16 // CPU state information.
22 /* General purpose integer registers */
24 /* Control registers */
28 /* Floating point status and control register */
30 /* Single precision floating point registers */
32 /* Single/Double precision floating point registers */
34 /* floating point registers for fmov */
36 /* Branch target registers */
38 /* Current instruction set mode */
42 void stream_cgen_hardware (std::ostream &ost) const
44 ost << hardware.h_pc << ' ';
45 for (int i = 0; i < 64; i++)
46 ost << hardware.h_gr[i] << ' ';
47 for (int i = 0; i < 64; i++)
48 ost << hardware.h_cr[i] << ' ';
49 ost << hardware.h_sr << ' ';
50 ost << hardware.h_fpscr << ' ';
51 for (int i = 0; i < 64; i++)
52 ost << hardware.h_fr[i] << ' ';
53 for (int i = 0; i < 16; i++)
54 ost << hardware.h_fsd[i] << ' ';
55 for (int i = 0; i < 16; i++)
56 ost << hardware.h_fmov[i] << ' ';
57 for (int i = 0; i < 8; i++)
58 ost << hardware.h_tr[i] << ' ';
59 ost << hardware.h_ism << ' ';
61 void destream_cgen_hardware (std::istream &ist)
64 for (int i = 0; i < 64; i++)
65 ist >> hardware.h_gr[i];
66 for (int i = 0; i < 64; i++)
67 ist >> hardware.h_cr[i];
69 ist >> hardware.h_fpscr;
70 for (int i = 0; i < 64; i++)
71 ist >> hardware.h_fr[i];
72 for (int i = 0; i < 16; i++)
73 ist >> hardware.h_fsd[i];
74 for (int i = 0; i < 16; i++)
75 ist >> hardware.h_fmov[i];
76 for (int i = 0; i < 8; i++)
77 ist >> hardware.h_tr[i];
78 ist >> hardware.h_ism;
80 template <typename ST>
81 void stream_stacks (const ST &st, std::ostream &ost) const
83 for (int i = 0; i < sh5::pipe_sz; i++)
85 ost << st[i].t << ' ';
86 for (int j = 0; j <= st[i].t; j++)
88 ost << st[i].buf[j].pc << ' ';
89 ost << st[i].buf[j].val << ' ';
90 ost << st[i].buf[j].idx0 << ' ';
95 template <typename ST>
96 void destream_stacks (ST &st, std::istream &ist)
98 for (int i = 0; i < sh5::pipe_sz; i++)
101 for (int j = 0; j <= st[i].t; j++)
103 ist >> st[i].buf[j].pc;
104 ist >> st[i].buf[j].val;
105 ist >> st[i].buf[j].idx0;
110 void stream_cgen_write_stacks (std::ostream &ost, const sh5::write_stacks &stacks) const
113 void destream_cgen_write_stacks (std::istream &ist, sh5::write_stacks &stacks)
116 // C++ register access function templates
117 #define current_cpu this
119 inline UDI h_pc_get () const { return current_cpu->hardware.h_pc; }
120 inline void h_pc_set (UDI newval) { {
121 current_cpu->hardware.h_ism = ANDDI (newval, 1);
122 current_cpu->hardware.h_pc = ANDDI (newval, INVDI (1));
126 inline DI h_gr_get (UINT regno) const { return ((((regno) == (63))) ? (MAKEDI (0, 0)) : (current_cpu->hardware.h_gr[regno])); }
127 inline void h_gr_set (UINT regno, DI newval) { if (((regno) != (63))) {
128 current_cpu->hardware.h_gr[regno] = newval;
134 inline SI h_grc_get (UINT regno) const { return ANDDI (current_cpu->hardware.h_gr[regno], ZEXTSIDI (0xffffffff)); }
135 inline void h_grc_set (UINT regno, SI newval) { current_cpu->hardware.h_gr[regno] = EXTSIDI (newval);
138 inline DI h_cr_get (UINT regno) const { return ((((regno) == (0))) ? (ZEXTSIDI (current_cpu->hardware.h_sr)) : (current_cpu->hardware.h_cr[regno])); }
139 inline void h_cr_set (UINT regno, DI newval) { if (((regno) == (0))) {
140 current_cpu->hardware.h_sr = newval;
142 current_cpu->hardware.h_cr[regno] = newval;
146 inline SI h_sr_get () const { return this->hardware.h_sr; }
147 inline void h_sr_set (SI newval) { this->hardware.h_sr = newval; }
149 inline SI h_fpscr_get () const { return this->hardware.h_fpscr; }
150 inline void h_fpscr_set (SI newval) { this->hardware.h_fpscr = newval; }
152 inline BI h_frbit_get () const { return ANDSI (SRLSI (current_cpu->hardware.h_fpscr, 21), 1); }
153 inline void h_frbit_set (BI newval) { current_cpu->hardware.h_fpscr = ORSI (ANDSI (current_cpu->hardware.h_fpscr, (~ (((1) << (21))))), SLLSI (newval, 21));
156 inline BI h_szbit_get () const { return ANDSI (SRLSI (current_cpu->hardware.h_fpscr, 20), 1); }
157 inline void h_szbit_set (BI newval) { current_cpu->hardware.h_fpscr = ORSI (ANDSI (current_cpu->hardware.h_fpscr, (~ (((1) << (20))))), SLLSI (newval, 20));
160 inline BI h_prbit_get () const { return ANDSI (SRLSI (current_cpu->hardware.h_fpscr, 19), 1); }
161 inline void h_prbit_set (BI newval) { current_cpu->hardware.h_fpscr = ORSI (ANDSI (current_cpu->hardware.h_fpscr, (~ (((1) << (19))))), SLLSI (newval, 19));
164 inline BI h_sbit_get () const { return ANDSI (SRLSI (current_cpu->hardware.h_sr, 1), 1); }
165 inline void h_sbit_set (BI newval) { current_cpu->hardware.h_sr = ORSI (ANDSI (current_cpu->hardware.h_sr, (~ (2))), SLLSI (newval, 1));
168 inline BI h_mbit_get () const { return ANDSI (SRLSI (current_cpu->hardware.h_sr, 9), 1); }
169 inline void h_mbit_set (BI newval) { current_cpu->hardware.h_sr = ORSI (ANDSI (current_cpu->hardware.h_sr, (~ (((1) << (9))))), SLLSI (newval, 9));
172 inline BI h_qbit_get () const { return ANDSI (SRLSI (current_cpu->hardware.h_sr, 8), 1); }
173 inline void h_qbit_set (BI newval) { current_cpu->hardware.h_sr = ORSI (ANDSI (current_cpu->hardware.h_sr, (~ (((1) << (8))))), SLLSI (newval, 8));
176 inline SF h_fr_get (UINT regno) const { return this->hardware.h_fr[regno]; }
177 inline void h_fr_set (UINT regno, SF newval) { this->hardware.h_fr[regno] = newval; }
179 inline SF h_fp_get (UINT regno) const { return current_cpu->hardware.h_fr[regno]; }
180 inline void h_fp_set (UINT regno, SF newval) { current_cpu->hardware.h_fr[regno] = newval;
183 inline SF h_fv_get (UINT regno) const { return current_cpu->hardware.h_fr[regno]; }
184 inline void h_fv_set (UINT regno, SF newval) { current_cpu->hardware.h_fr[regno] = newval;
187 inline SF h_fmtx_get (UINT regno) const { return current_cpu->hardware.h_fr[regno]; }
188 inline void h_fmtx_set (UINT regno, SF newval) { current_cpu->hardware.h_fr[regno] = newval;
191 inline DF h_dr_get (UINT regno) const { return SUBWORDDIDF (ORDI (SLLDI (ZEXTSIDI (SUBWORDSFSI (current_cpu->hardware.h_fr[regno])), 32), ZEXTSIDI (SUBWORDSFSI (current_cpu->hardware.h_fr[((regno) + (1))])))); }
192 inline void h_dr_set (UINT regno, DF newval) { {
193 current_cpu->hardware.h_fr[regno] = SUBWORDSISF (SUBWORDDFSI (newval, 0));
194 current_cpu->hardware.h_fr[((regno) + (1))] = SUBWORDSISF (SUBWORDDFSI (newval, 1));
198 inline DF h_fsd_get (UINT regno) const { return ((current_cpu->h_prbit_get ()) ? (current_cpu->h_drc_get (regno)) : (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), current_cpu->hardware.h_fr[regno]))); }
199 inline void h_fsd_set (UINT regno, DF newval) { if (current_cpu->h_prbit_get ()) {
200 current_cpu->h_drc_set (regno, newval);
202 current_cpu->h_frc_set (regno, CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), newval));
206 inline DF h_fmov_get (UINT regno) const { return ((NOTBI (current_cpu->h_szbit_get ())) ? (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), current_cpu->h_frc_get (regno))) : (((((((regno) & (1))) == (1))) ? (current_cpu->h_xd_get (((regno) & ((~ (1)))))) : (current_cpu->h_dr_get (regno))))); }
207 inline void h_fmov_set (UINT regno, DF newval) { if (NOTBI (current_cpu->h_szbit_get ())) {
208 current_cpu->h_frc_set (regno, CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), newval));
210 if (((((regno) & (1))) == (1))) {
211 current_cpu->h_xd_set (((regno) & ((~ (1)))), newval);
213 current_cpu->h_dr_set (regno, newval);
218 inline DI h_tr_get (UINT regno) const { return this->hardware.h_tr[regno]; }
219 inline void h_tr_set (UINT regno, DI newval) { this->hardware.h_tr[regno] = newval; }
221 inline BI h_endian_get () const { return current_cpu->sh64_endian (); }
222 inline void h_endian_set (BI newval) { current_cpu->cgen_rtx_error ("cannot alter target byte order mid-program");
225 inline BI h_ism_get () const { return current_cpu->hardware.h_ism; }
226 inline void h_ism_set (BI newval) { current_cpu->cgen_rtx_error ("cannot set ism directly");
229 inline SF h_frc_get (UINT regno) const { return current_cpu->hardware.h_fr[((((16) * (current_cpu->h_frbit_get ()))) + (regno))]; }
230 inline void h_frc_set (UINT regno, SF newval) { current_cpu->hardware.h_fr[((((16) * (current_cpu->h_frbit_get ()))) + (regno))] = newval;
233 inline DF h_drc_get (UINT regno) const { return current_cpu->h_dr_get (((((16) * (current_cpu->h_frbit_get ()))) + (regno))); }
234 inline void h_drc_set (UINT regno, DF newval) { current_cpu->h_dr_set (((((16) * (current_cpu->h_frbit_get ()))) + (regno)), newval);
237 inline SF h_xf_get (UINT regno) const { return current_cpu->hardware.h_fr[((((16) * (NOTBI (current_cpu->h_frbit_get ())))) + (regno))]; }
238 inline void h_xf_set (UINT regno, SF newval) { current_cpu->hardware.h_fr[((((16) * (NOTBI (current_cpu->h_frbit_get ())))) + (regno))] = newval;
241 inline DF h_xd_get (UINT regno) const { return current_cpu->h_dr_get (((((16) * (NOTBI (current_cpu->h_frbit_get ())))) + (regno))); }
242 inline void h_xd_set (UINT regno, DF newval) { current_cpu->h_dr_set (((((16) * (NOTBI (current_cpu->h_frbit_get ())))) + (regno)), newval);
245 inline SF h_fvc_get (UINT regno) const { return current_cpu->hardware.h_fr[((((16) * (current_cpu->h_frbit_get ()))) + (regno))]; }
246 inline void h_fvc_set (UINT regno, SF newval) { current_cpu->hardware.h_fr[((((16) * (current_cpu->h_frbit_get ()))) + (regno))] = newval;
249 inline SI h_gbr_get () const { return SUBWORDDISI (current_cpu->hardware.h_gr[((UINT) 16)], 1); }
250 inline void h_gbr_set (SI newval) { current_cpu->hardware.h_gr[((UINT) 16)] = EXTSIDI (newval);
253 inline SI h_vbr_get () const { return SUBWORDDISI (current_cpu->hardware.h_gr[((UINT) 20)], 1); }
254 inline void h_vbr_set (SI newval) { current_cpu->hardware.h_gr[((UINT) 20)] = EXTSIDI (newval);
257 inline SI h_pr_get () const { return SUBWORDDISI (current_cpu->hardware.h_gr[((UINT) 18)], 1); }
258 inline void h_pr_set (SI newval) { current_cpu->hardware.h_gr[((UINT) 18)] = EXTSIDI (newval);
261 inline SI h_macl_get () const { return SUBWORDDISI (current_cpu->hardware.h_gr[((UINT) 17)], 1); }
262 inline void h_macl_set (SI newval) { current_cpu->hardware.h_gr[((UINT) 17)] = ORDI (SLLDI (ZEXTSIDI (SUBWORDDISI (current_cpu->hardware.h_gr[((UINT) 17)], 0)), 32), ZEXTSIDI (newval));
265 inline SI h_mach_get () const { return SUBWORDDISI (current_cpu->hardware.h_gr[((UINT) 17)], 0); }
266 inline void h_mach_set (SI newval) { current_cpu->hardware.h_gr[((UINT) 17)] = ORDI (SLLDI (ZEXTSIDI (newval), 32), ZEXTSIDI (SUBWORDDISI (current_cpu->hardware.h_gr[((UINT) 17)], 1)));
269 inline BI h_tbit_get () const { return ANDBI (current_cpu->hardware.h_gr[((UINT) 19)], 1); }
270 inline void h_tbit_set (BI newval) { current_cpu->hardware.h_gr[((UINT) 19)] = ORDI (ANDDI (current_cpu->hardware.h_gr[((UINT) 19)], INVDI (1)), ZEXTBIDI (newval));