manually sync from the CVS repository

diff --git a/bfd/Makefile.am b/bfd/Makefile.am
index 13ace29..b569f84 100644 (file)
--- a/bfd/Makefile.am
+++ b/bfd/Makefile.am
@@ -120,6 +120,7 @@ ALL_MACHINES = \
        cpu-plugin.lo \
        cpu-powerpc.lo \
        cpu-rs6000.lo \
+       cpu-rx.lo \
        cpu-s390.lo \
        cpu-score.lo \
        cpu-sh.lo \
@@ -191,6 +192,7 @@ ALL_MACHINES_CFILES = \
        cpu-plugin.c \
        cpu-powerpc.c \
        cpu-rs6000.c \
+       cpu-rx.c \
        cpu-s390.c \
        cpu-score.c \
        cpu-sh.c \
@@ -307,6 +309,7 @@ BFD32_BACKENDS = \
        elf32-or32.lo \
        elf32-pj.lo \
        elf32-ppc.lo \
+       elf32-rx.lo \
        elf32-s390.lo \
        elf32-sh-symbian.lo \
        elf32-sh.lo \
@@ -490,6 +493,7 @@ BFD32_BACKENDS_CFILES = \
        elf32-or32.c \
        elf32-pj.c \
        elf32-ppc.c \
+       elf32-rx.c \
        elf32-s390.c \
        elf32-sh-symbian.c \
        elf32-sh.c \

diff --git a/bfd/Makefile.in b/bfd/Makefile.in
index 721069f..5700ed3 100644 (file)
--- a/bfd/Makefile.in
+++ b/bfd/Makefile.in
@@ -415,6 +415,7 @@ ALL_MACHINES = \
        cpu-plugin.lo \
        cpu-powerpc.lo \
        cpu-rs6000.lo \
+       cpu-rx.lo \
        cpu-s390.lo \
        cpu-score.lo \
        cpu-sh.lo \
@@ -486,6 +487,7 @@ ALL_MACHINES_CFILES = \
        cpu-plugin.c \
        cpu-powerpc.c \
        cpu-rs6000.c \
+       cpu-rx.c \
        cpu-s390.c \
        cpu-score.c \
        cpu-sh.c \
@@ -603,6 +605,7 @@ BFD32_BACKENDS = \
        elf32-or32.lo \
        elf32-pj.lo \
        elf32-ppc.lo \
+       elf32-rx.lo \
        elf32-s390.lo \
        elf32-sh-symbian.lo \
        elf32-sh.lo \
@@ -786,6 +789,7 @@ BFD32_BACKENDS_CFILES = \
        elf32-or32.c \
        elf32-pj.c \
        elf32-ppc.c \
+       elf32-rx.c \
        elf32-s390.c \
        elf32-sh-symbian.c \
        elf32-sh.c \
@@ -1271,6 +1275,7 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-plugin.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-powerpc.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-rs6000.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-rx.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-s390.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-score.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-sh.Plo@am__quote@
@@ -1345,6 +1350,7 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-or32.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-pj.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-ppc.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-rx.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-s390.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-score.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-score7.Plo@am__quote@

diff --git a/bfd/aout-cris.c b/bfd/aout-cris.c
index c5f71b0..f1f3060 100644 (file)
--- a/bfd/aout-cris.c
+++ b/bfd/aout-cris.c
@@ -1,5 +1,5 @@
 /* BFD backend for CRIS a.out binaries.
-   Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2007
+   Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2009
    Free Software Foundation, Inc.
    Contributed by Axis Communications AB.
    Written by Hans-Peter Nilsson.
@@ -57,11 +57,6 @@
 #define TARGET_PAGE_SIZE SEGMENT_SIZE
 #define TARGETNAME "a.out-cris"
 
-/* N_SHARED_LIB gets this reasonable default as of 1999-07-12, but we
-   have to work with 2.9.1.  Note that N_SHARED_LIB is used in a
-   SUN-specific context, not applicable to CRIS.  */
-#define N_SHARED_LIB(x) 0
-
 /* The definition here seems not used; just provided as a convention.  */
 #define DEFAULT_ARCH bfd_arch_cris
 

diff --git a/bfd/archures.c b/bfd/archures.c
index df73b3f..8df2ce1 100644 (file)
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -380,6 +380,8 @@ DESCRIPTION
 .#define bfd_mach_cris_v0_v10  255
 .#define bfd_mach_cris_v32     32
 .#define bfd_mach_cris_v10_v32 1032
+.  bfd_arch_rx,        {* Renesas RX.  *}
+.#define bfd_mach_rx            0x75
 .  bfd_arch_s390,      {* IBM s390 *}
 .#define bfd_mach_s390_31       31
 .#define bfd_mach_s390_64       64
@@ -513,6 +515,7 @@ extern const bfd_arch_info_type bfd_plugin_arch;
 extern const bfd_arch_info_type bfd_powerpc_archs[];
 #define bfd_powerpc_arch bfd_powerpc_archs[0]
 extern const bfd_arch_info_type bfd_rs6000_arch;
+extern const bfd_arch_info_type bfd_rx_arch;
 extern const bfd_arch_info_type bfd_s390_arch;
 extern const bfd_arch_info_type bfd_score_arch;
 extern const bfd_arch_info_type bfd_sh_arch;
@@ -586,6 +589,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] =
     &bfd_pdp11_arch,
     &bfd_powerpc_arch,
     &bfd_rs6000_arch,
+    &bfd_rx_arch,
     &bfd_s390_arch,
     &bfd_score_arch,
     &bfd_sh_arch,

diff --git a/bfd/bfd-in.h b/bfd/bfd-in.h
index 516102e..c3d2d97 100644 (file)
--- a/bfd/bfd-in.h
+++ b/bfd/bfd-in.h
@@ -635,8 +635,8 @@ extern struct bfd_link_needed_list *bfd_elf_get_needed_list
 extern bfd_boolean bfd_elf_get_bfd_needed_list
   (bfd *, struct bfd_link_needed_list **);
 extern bfd_boolean bfd_elf_size_dynamic_sections
-  (bfd *, const char *, const char *, const char *, const char * const *,
-   struct bfd_link_info *, struct bfd_section **,
+  (bfd *, const char *, const char *, const char *, const char *, const char *,
+   const char * const *, struct bfd_link_info *, struct bfd_section **,
    struct bfd_elf_version_tree *);
 extern bfd_boolean bfd_elf_size_dynsym_hash_dynstr
   (bfd *, struct bfd_link_info *);

diff --git a/bfd/cofflink.c b/bfd/cofflink.c
index 12a693e..3253e5e 100644 (file)
--- a/bfd/cofflink.c
+++ b/bfd/cofflink.c
@@ -2959,7 +2959,7 @@ _bfd_coff_generic_relocate_section (bfd *output_bfd,
                     See also linker.c: generic_link_check_archive_element. */
                  asection *sec;
                  struct coff_link_hash_entry *h2 =
-                   input_bfd->tdata.coff_obj_data->sym_hashes[
+                   h->auxbfd->tdata.coff_obj_data->sym_hashes[
                    h->aux->x_sym.x_tagndx.l];
 
                  if (!h2 || h2->root.type == bfd_link_hash_undefined)

diff --git a/bfd/config.bfd b/bfd/config.bfd
index e340251..89b664c 100644 (file)
--- a/bfd/config.bfd
+++ b/bfd/config.bfd
@@ -1191,6 +1191,11 @@ case "${targ}" in
     targ_selvecs="bfd_powerpcle_pei_vec bfd_powerpc_pei_vec bfd_powerpcle_pe_vec bfd_powerpc_pe_vec"
     ;;
 
+  rx-*-elf)
+    targ_defvec=bfd_elf32_rx_le_vec
+    targ_selvecs="bfd_elf32_rx_be_vec bfd_elf32_rx_le_vec"
+    ;;
+
   s390-*-linux*)
     targ_defvec=bfd_elf32_s390_vec
     targ64_selvecs=bfd_elf64_s390_vec

diff --git a/bfd/configure b/bfd/configure
index 865ef69..d5aec74 100755 (executable)
--- a/bfd/configure
+++ b/bfd/configure
@@ -14868,6 +14868,8 @@ do
     bfd_elf32_powerpc_vec)     tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;;
     bfd_elf32_powerpcle_vec)   tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;;
     bfd_elf32_powerpc_vxworks_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;;
+    bfd_elf32_rx_le_vec)        tb="$tb elf32-rx.lo elf32.lo $elf" ;;
+    bfd_elf32_rx_be_vec)        tb="$tb elf32-rx.lo elf32.lo $elf" ;;
     bfd_elf32_s390_vec)                tb="$tb elf32-s390.lo elf32.lo $elf" ;;
     bfd_elf32_bigscore_vec)     tb="$tb elf32-score.lo elf32-score7.lo elf32.lo $elf"; want64=true; target_size=64;;
     bfd_elf32_littlescore_vec)  tb="$tb elf32-score.lo elf32-score7.lo elf32.lo $elf"; want64=true; target_size=64;;

diff --git a/bfd/configure.com b/bfd/configure.com
index 04113aa..2102415 100644 (file)
--- a/bfd/configure.com
+++ b/bfd/configure.com
@@ -318,6 +318,9 @@ $ create []config.h
 /* Disable NLS  */
 #undef ENABLE_NLS
 $!
+$ write sys$output "Copy sysdep.h"
+$ copy [.hosts]alphavms.h sysdep.h
+$
 $ write sys$output "Generate build.com"
 $!
 $ if ARCH.eqs."alpha"
@@ -362,7 +365,6 @@ $ write sys$output "Generate elf64-target.h from elfxx-target.h"
 $ edit/tpu/nojournal/nosection/nodisplay/command=substxx.tpu -
         []elfXX-target.h /output=[]elf64-target.h
 $ del substxx.tpu;*
-$ copy [.hosts]alphavms.h sysdep.h
 $ endif
 $ append sys$input build.com
 $DECK

diff --git a/bfd/configure.in b/bfd/configure.in
index bf4dc6c..7ca59b0 100644 (file)
--- a/bfd/configure.in
+++ b/bfd/configure.in
@@ -756,6 +756,8 @@ do
     bfd_elf32_powerpc_vec)     tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;;
     bfd_elf32_powerpcle_vec)   tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;;
     bfd_elf32_powerpc_vxworks_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;;
+    bfd_elf32_rx_le_vec)        tb="$tb elf32-rx.lo elf32.lo $elf" ;;
+    bfd_elf32_rx_be_vec)        tb="$tb elf32-rx.lo elf32.lo $elf" ;;
     bfd_elf32_s390_vec)                tb="$tb elf32-s390.lo elf32.lo $elf" ;;
     bfd_elf32_bigscore_vec)     tb="$tb elf32-score.lo elf32-score7.lo elf32.lo $elf"; want64=true; target_size=64;;
     bfd_elf32_littlescore_vec)  tb="$tb elf32-score.lo elf32-score7.lo elf32.lo $elf"; want64=true; target_size=64;;

diff --git a/bfd/cpu-rx.c b/bfd/cpu-rx.c
new file mode 100644 (file)
index 0000000..92eebb0
--- /dev/null
+++ b/bfd/cpu-rx.c
@@ -0,0 +1,57 @@
+/* BFD support for the RX processor.
+   Copyright (C) 2008, 2009 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#include "sysdep.h"
+#include "bfd.h"
+#include "libbfd.h"
+
+static const bfd_arch_info_type arch_info_struct[] =
+{
+  {
+    32,                                /* Bits per word.  */
+    32,                                /* Bits per address.  */
+    8,                         /* Bits per byte.  */
+    bfd_arch_rx,               /* Architecture.  */
+    bfd_mach_rx,               /* Machine.  */
+    "rx",                      /* Architecture name.  */
+    "rx",                      /* Printable name.  */
+    3,                         /* Section align power.  */
+    FALSE,                     /* The default ?  */
+    bfd_default_compatible,    /* Architecture comparison fn.  */
+    bfd_default_scan,          /* String to architecture convert fn.  */
+    NULL                       /* Next in list.  */
+  },
+};
+
+const bfd_arch_info_type bfd_rx_arch =
+{
+  32,                          /* Bits per word.  */
+  32,                          /* Bits per address.  */
+  8,                           /* Bits per byte.  */
+  bfd_arch_rx,                 /* Architecture.  */
+  bfd_mach_rx,                 /* Machine.  */
+  "rx",                                /* Architecture name.  */
+  "rx",                                /* Printable name.  */
+  4,                           /* Section align power.  */
+  TRUE,                                /* The default ?  */
+  bfd_default_compatible,      /* Architecture comparison fn.  */
+  bfd_default_scan,            /* String to architecture convert fn.  */
+  & arch_info_struct[0],       /* Next in list.  */
+};

diff --git a/bfd/doc/ChangeLog b/bfd/doc/ChangeLog
index 03eca56..b85e3a1 100644 (file)
--- a/bfd/doc/ChangeLog
+++ b/bfd/doc/ChangeLog
@@ -1,3 +1,9 @@
+2009-09-25  Martin Thuresson  <martint@google.com>
+
+       Update soruces to make alpha targets compile cleanly with
+       -Wc++-compat:
+       * chew.c: Add casts.
+
 2009-08-29  Martin Thuresson  <martin@mtme.org>
 
        * chew.c (newentry, add_intrinsic): Rename variable new to

diff --git a/bfd/doc/chew.c b/bfd/doc/chew.c
index 172bc58..2276c8a 100644 (file)
--- a/bfd/doc/chew.c
+++ b/bfd/doc/chew.c
@@ -130,7 +130,7 @@ init_string_with_size (buffer, size)
 {
   buffer->write_idx = 0;
   buffer->size = size;
-  buffer->ptr = malloc (size);
+  buffer->ptr = (char *) malloc (size);
 }
 
 static void
@@ -201,7 +201,7 @@ catchar (buffer, ch)
   if (buffer->write_idx == buffer->size)
     {
       buffer->size *= 2;
-      buffer->ptr = realloc (buffer->ptr, buffer->size);
+      buffer->ptr = (char *) realloc (buffer->ptr, buffer->size);
     }
 
   buffer->ptr[buffer->write_idx++] = ch;
@@ -228,7 +228,7 @@ catbuf (buffer, buf, len)
     {
       while (buffer->write_idx + len >= buffer->size)
        buffer->size *= 2;
-      buffer->ptr = realloc (buffer->ptr, buffer->size);
+      buffer->ptr = (char *) realloc (buffer->ptr, buffer->size);
     }
   memcpy (buffer->ptr + buffer->write_idx, buf, len);
   buffer->write_idx += len;
@@ -1177,7 +1177,7 @@ nextword (string, word)
        }
     }
 
-  *word = malloc (length + 1);
+  *word = (char *) malloc (length + 1);
 
   dst = *word;
   src = word_start;

diff --git a/bfd/dwarf2.c b/bfd/dwarf2.c
index b54ef6e..5d504c8 100644 (file)
--- a/bfd/dwarf2.c
+++ b/bfd/dwarf2.c
@@ -1495,95 +1495,27 @@ decode_line_info (struct comp_unit *unit, struct dwarf2_debug *stash)
 static bfd_boolean
 lookup_address_in_line_info_table (struct line_info_table *table,
                                   bfd_vma addr,
-                                  struct funcinfo *function,
                                   const char **filename_ptr,
                                   unsigned int *linenumber_ptr)
 {
   /* Note: table->last_line should be a descendingly sorted list. */
-  struct line_info* next_line = table->last_line;
-  struct line_info* each_line = NULL;
-  *filename_ptr = NULL;
-
-  if (!next_line)
-    return FALSE;
-
-  each_line = next_line->prev_line;
-
-  /* Check for large addresses */
-  if (addr > next_line->address)
-    each_line = NULL; /* ensure we skip over the normal case */
-
-  /* Normal case: search the list; save  */
-  while (each_line && next_line)
-    {
-      /* If we have an address match, save this info.  This allows us
-        to return as good as results as possible for strange debugging
-        info.  */
-      bfd_boolean addr_match = FALSE;
-      if (each_line->address <= addr && addr < next_line->address)
-       {
-         addr_match = TRUE;
-
-         /* If this line appears to span functions, and addr is in the
-            later function, return the first line of that function instead
-            of the last line of the earlier one.  This check is for GCC
-            2.95, which emits the first line number for a function late.  */
-
-         if (function != NULL)
-           {
-             bfd_vma lowest_pc;
-             struct arange *arange;
-
-             /* Find the lowest address in the function's range list */
-             lowest_pc = function->arange.low;
-             for (arange = &function->arange;
-                  arange;
-                  arange = arange->next)
-               {
-                 if (function->arange.low < lowest_pc)
-                   lowest_pc = function->arange.low;
-               }
-             /* Check for spanning function and set outgoing line info */
-             if (addr >= lowest_pc
-                 && each_line->address < lowest_pc
-                 && next_line->address > lowest_pc)
-               {
-                 *filename_ptr = next_line->filename;
-                 *linenumber_ptr = next_line->line;
-               }
-             else
-               {
-                 *filename_ptr = each_line->filename;
-                 *linenumber_ptr = each_line->line;
-               }
-           }
-         else
-           {
-             *filename_ptr = each_line->filename;
-             *linenumber_ptr = each_line->line;
-           }
-       }
-
-      if (addr_match && !each_line->end_sequence)
-       return TRUE; /* we have definitely found what we want */
+  struct line_info *each_line;
 
-      next_line = each_line;
-      each_line = each_line->prev_line;
-    }
+  for (each_line = table->last_line;
+       each_line;
+       each_line = each_line->prev_line)
+    if (addr >= each_line->address)
+      break;
 
-  /* At this point each_line is NULL but next_line is not.  If we found
-     a candidate end-of-sequence point in the loop above, we can return
-     that (compatibility with a bug in the Intel compiler); otherwise,
-     assuming that we found the containing function for this address in
-     this compilation unit, return the first line we have a number for
-     (compatibility with GCC 2.95).  */
-  if (*filename_ptr == NULL && function != NULL)
+  if (each_line
+      && !(each_line->end_sequence || each_line == table->last_line))
     {
-      *filename_ptr = next_line->filename;
-      *linenumber_ptr = next_line->line;
+      *filename_ptr = each_line->filename;
+      *linenumber_ptr = each_line->line;
       return TRUE;
     }
 
+  *filename_ptr = NULL;
   return FALSE;
 }
 
@@ -2298,7 +2230,7 @@ comp_unit_find_nearest_line (struct comp_unit *unit,
   if (func_p && (function->tag == DW_TAG_inlined_subroutine))
     stash->inliner_chain = function;
   line_p = lookup_address_in_line_info_table (unit->line_table, addr,
-                                             function, filename_ptr,
+                                             filename_ptr,
                                              linenumber_ptr);
   return line_p || func_p;
 }

diff --git a/bfd/ecoff.c b/bfd/ecoff.c
index cb5d82f..48ce98c 100644 (file)
--- a/bfd/ecoff.c
+++ b/bfd/ecoff.c
@@ -89,7 +89,7 @@ _bfd_ecoff_mkobject (bfd *abfd)
 {
   bfd_size_type amt = sizeof (ecoff_data_type);
 
-  abfd->tdata.ecoff_obj_data = bfd_zalloc (abfd, amt);
+  abfd->tdata.ecoff_obj_data = (struct ecoff_tdata *) bfd_zalloc (abfd, amt);
   if (abfd->tdata.ecoff_obj_data == NULL)
     return FALSE;
 
@@ -193,7 +193,7 @@ _bfd_ecoff_new_section_hook (bfd *abfd, asection *section)
 bfd_boolean
 _bfd_ecoff_set_arch_mach_hook (bfd *abfd, void * filehdr)
 {
-  struct internal_filehdr *internal_f = filehdr;
+  struct internal_filehdr *internal_f = (struct internal_filehdr *) filehdr;
   enum bfd_architecture arch;
   unsigned long mach;
 
@@ -366,7 +366,7 @@ _bfd_ecoff_styp_to_sec_flags (bfd *abfd ATTRIBUTE_UNUSED,
                              asection *section ATTRIBUTE_UNUSED,
                              flagword * flags_ptr)
 {
-  struct internal_scnhdr *internal_s = hdr;
+  struct internal_scnhdr *internal_s = (struct internal_scnhdr *) hdr;
   long styp_flags = internal_s->s_flags;
   flagword sec_flags = 0;
 
@@ -614,7 +614,7 @@ _bfd_ecoff_slurp_symbolic_info (bfd *abfd,
      the symbols, so we swap them here.  */
   amt = internal_symhdr->ifdMax;
   amt *= sizeof (struct fdr);
-  debug->fdr = bfd_alloc (abfd, amt);
+  debug->fdr = (FDR *) bfd_alloc (abfd, amt);
   if (debug->fdr == NULL)
     return FALSE;
   external_fdr_size = backend->debug_swap.external_fdr_size;
@@ -882,7 +882,7 @@ _bfd_ecoff_slurp_symbol_table (bfd *abfd)
 
   internal_size = bfd_get_symcount (abfd);
   internal_size *= sizeof (ecoff_symbol_type);
-  internal = bfd_alloc (abfd, internal_size);
+  internal = (ecoff_symbol_type *) bfd_alloc (abfd, internal_size);
   if (internal == NULL)
     return FALSE;
 
@@ -1580,11 +1580,11 @@ ecoff_slurp_reloc_table (bfd *abfd,
 
   amt = section->reloc_count;
   amt *= sizeof (arelent);
-  internal_relocs = bfd_alloc (abfd, amt);
+  internal_relocs = (arelent *) bfd_alloc (abfd, amt);
 
   external_reloc_size = backend->external_reloc_size;
   amt = external_reloc_size * section->reloc_count;
-  external_relocs = bfd_alloc (abfd, amt);
+  external_relocs = (char *) bfd_alloc (abfd, amt);
   if (internal_relocs == NULL || external_relocs == NULL)
     return FALSE;
   if (bfd_seek (abfd, section->rel_filepos, SEEK_SET) != 0)
@@ -1730,7 +1730,8 @@ _bfd_ecoff_find_nearest_line (bfd *abfd,
     {
       bfd_size_type amt = sizeof (struct ecoff_find_line);
 
-      ecoff_data (abfd)->find_line_info = bfd_zalloc (abfd, amt);
+      ecoff_data (abfd)->find_line_info =
+          (struct ecoff_find_line *) bfd_zalloc (abfd, amt);
       if (ecoff_data (abfd)->find_line_info == NULL)
        return FALSE;
     }
@@ -1955,7 +1956,7 @@ ecoff_compute_section_file_positions (bfd *abfd)
   /* Sort the sections by VMA.  */
   amt = abfd->section_count;
   amt *= sizeof (asection *);
-  sorted_hdrs = bfd_malloc (amt);
+  sorted_hdrs = (asection **) bfd_malloc (amt);
   if (sorted_hdrs == NULL)
     return FALSE;
   for (current = abfd->sections, i = 0;
@@ -2908,7 +2909,7 @@ _bfd_ecoff_slurp_armap (bfd *abfd)
   parsed_size = mapdata->parsed_size;
   bfd_release (abfd, (void *) mapdata);
 
-  raw_armap = bfd_alloc (abfd, parsed_size);
+  raw_armap = (char *) bfd_alloc (abfd, parsed_size);
   if (raw_armap == NULL)
     return FALSE;
 
@@ -2975,7 +2976,7 @@ _bfd_ecoff_slurp_armap (bfd *abfd)
 
   amt = ardata->symdef_count;
   amt *= sizeof (struct symdef);
-  symdef_ptr = bfd_alloc (abfd, amt);
+  symdef_ptr = (struct symdef *) bfd_alloc (abfd, amt);
   if (!symdef_ptr)
     return FALSE;
 
@@ -3091,7 +3092,7 @@ _bfd_ecoff_write_armap (bfd *abfd,
   if (bfd_bwrite ((void *) temp, (bfd_size_type) 4, abfd) != 4)
     return FALSE;
 
-  hashtable = bfd_zalloc (abfd, symdefsize);
+  hashtable = (bfd_byte *) bfd_zalloc (abfd, symdefsize);
   if (!hashtable)
     return FALSE;
 
@@ -3211,7 +3212,7 @@ _bfd_ecoff_bfd_link_hash_table_create (bfd *abfd)
   struct ecoff_link_hash_table *ret;
   bfd_size_type amt = sizeof (struct ecoff_link_hash_table);
 
-  ret = bfd_malloc (amt);
+  ret = (struct ecoff_link_hash_table *) bfd_malloc (amt);
   if (ret == NULL)
     return NULL;
   if (!_bfd_link_hash_table_init (&ret->root, abfd,
@@ -3269,7 +3270,7 @@ ecoff_link_add_externals (bfd *abfd,
 
   amt = ext_count;
   amt *= sizeof (struct bfd_link_hash_entry *);
-  sym_hash = bfd_alloc (abfd, amt);
+  sym_hash = (struct bfd_link_hash_entry **) bfd_alloc (abfd, amt);
   if (!sym_hash)
     return FALSE;
   ecoff_data (abfd)->sym_hashes = (struct ecoff_link_hash_entry **) sym_hash;
@@ -3483,7 +3484,7 @@ ecoff_link_add_object_symbols (bfd *abfd, struct bfd_link_info *info)
       || bfd_bread (external_ext, esize, abfd) != esize)
     goto error_return;
 
-  ssext = bfd_malloc ((bfd_size_type) symhdr->issExtMax);
+  ssext = (char *) bfd_malloc ((bfd_size_type) symhdr->issExtMax);
   if (ssext == NULL && symhdr->issExtMax != 0)
     goto error_return;
 
@@ -3549,7 +3550,7 @@ ecoff_link_check_archive_element (bfd *abfd,
       || bfd_bread (external_ext, esize, abfd) != esize)
     goto error_return;
 
-  ssext = bfd_malloc ((bfd_size_type) symhdr->issExtMax);
+  ssext = (char *) bfd_malloc ((bfd_size_type) symhdr->issExtMax);
   if (ssext == NULL && symhdr->issExtMax != 0)
     goto error_return;
 
@@ -3838,7 +3839,7 @@ ecoff_final_link_debug_accumulate (bfd *output_bfd,
   else                                                                  \
     {                                                                   \
       bfd_size_type amt = (bfd_size_type) size * symhdr->count;                 \
-      debug->ptr = bfd_malloc (amt);                                    \
+      debug->ptr = (type) bfd_malloc (amt);                              \
       if (debug->ptr == NULL)                                           \
        {                                                                \
           ret = FALSE;                                                  \
@@ -4083,7 +4084,7 @@ ecoff_reloc_link_order (bfd *output_bfd,
       bfd_byte *buf;
 
       size = bfd_get_reloc_size (rel.howto);
-      buf = bfd_zmalloc (size);
+      buf = (bfd_byte *) bfd_zmalloc (size);
       if (buf == NULL)
        return FALSE;
       rstat = _bfd_relocate_contents (rel.howto, output_bfd,
@@ -4192,7 +4193,7 @@ ecoff_reloc_link_order (bfd *output_bfd,
 
   /* Get some memory and swap out the reloc.  */
   external_reloc_size = ecoff_backend (output_bfd)->external_reloc_size;
-  rbuf = bfd_malloc (external_reloc_size);
+  rbuf = (bfd_byte *) bfd_malloc (external_reloc_size);
   if (rbuf == NULL)
     return FALSE;
 

diff --git a/bfd/ecofflink.c b/bfd/ecofflink.c
index 072c97a..25b67fa 100644 (file)
--- a/bfd/ecofflink.c
+++ b/bfd/ecofflink.c
@@ -1,6 +1,6 @@
 /* Routines to link ECOFF debugging information.
    Copyright 1993, 1994, 1995, 1996, 1997, 1999, 2000, 2001, 2002, 2003,
-   2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
+   2004, 2005, 2006, 2007, 2008, 2009  Free Software Foundation, Inc.
    Written by Ian Lance Taylor, Cygnus Support, <ian@cygnus.com>.
 
    This file is part of BFD, the Binary File Descriptor library.
@@ -1084,8 +1084,8 @@ ecoff_add_string (ainfo, info, debug, fdr, string)
   len = strlen (string);
   if (info->relocatable)
     {
-      if (!add_memory_shuffle (ainfo, &ainfo->ss, &ainfo->ss_end, (PTR) string,
-                              len + 1))
+      if (!add_memory_shuffle (ainfo, &ainfo->ss, &ainfo->ss_end,
+                               (bfd_byte *) string, len + 1))
        return -1;
       ret = symhdr->issMax;
       symhdr->issMax += len + 1;
@@ -1207,7 +1207,7 @@ bfd_ecoff_debug_accumulate_other (handle, output_bfd, output_debug,
        }
       (*swap_sym_out) (output_bfd, &internal_sym, external_sym);
       add_memory_shuffle (ainfo, &ainfo->sym, &ainfo->sym_end,
-                         external_sym,
+                         (bfd_byte *) external_sym,
                          (unsigned long) output_swap->external_sym_size);
       ++fdr.csym;
       ++output_symhdr->isymMax;
@@ -1228,7 +1228,7 @@ bfd_ecoff_debug_accumulate_other (handle, output_bfd, output_debug,
     }
   (*output_swap->swap_fdr_out) (output_bfd, &fdr, external_fdr);
   add_memory_shuffle (ainfo, &ainfo->fdr, &ainfo->fdr_end,
-                     external_fdr,
+                     (bfd_byte *) external_fdr,
                      (unsigned long) output_swap->external_fdr_size);
 
   ++output_symhdr->ifdMax;
@@ -1338,8 +1338,8 @@ bfd_ecoff_debug_one_external (abfd, debug, swap, name, esym)
                - (char *) debug->external_ext)
       < (symhdr->iextMax + 1) * external_ext_size)
     {
-      char *external_ext = debug->external_ext;
-      char *external_ext_end = debug->external_ext_end;
+      char *external_ext = (char *) debug->external_ext;
+      char *external_ext_end = (char *) debug->external_ext_end;
       if (! ecoff_add_bytes ((char **) &external_ext,
                             (char **) &external_ext_end,
                             (symhdr->iextMax + 1) * (size_t) external_ext_size))
@@ -1503,7 +1503,7 @@ ecoff_write_symhdr (abfd, debug, swap, where)
   SET (cbExtOffset, iextMax, swap->external_ext_size);
 #undef SET
 
-  buff = (PTR) bfd_malloc (swap->external_hdr_size);
+  buff = (char *) bfd_malloc (swap->external_hdr_size);
   if (buff == NULL && swap->external_hdr_size != 0)
     goto error_return;
 

diff --git a/bfd/elf-bfd.h b/bfd/elf-bfd.h
index 82c7c77..7cc420c 100644 (file)
--- a/bfd/elf-bfd.h
+++ b/bfd/elf-bfd.h
@@ -305,6 +305,10 @@ struct eh_cie_fde
        asection *sec;
       } u;
 
+      /* The offset of the personality data from the start of the CIE,
+        or 0 if the CIE doesn't have any.  */
+      unsigned int personality_offset : 8;
+
       /* True if we have marked relocations associated with this CIE.  */
       unsigned int gc_mark : 1;
 
@@ -312,8 +316,13 @@ struct eh_cie_fde
         a PC-relative one.  */
       unsigned int make_lsda_relative : 1;
 
-      /* True if the CIE contains personality data and if that data
-        uses a PC-relative encoding.  */
+      /* True if we have decided to turn an absolute personality
+        encoding into a PC-relative one.  */
+      unsigned int make_per_encoding_relative : 1;
+
+      /* True if the CIE contains personality data and if that
+        data uses a PC-relative encoding.  Always true when
+        make_per_encoding_relative is.  */
       unsigned int per_encoding_relative : 1;
 
       /* True if we need to add an 'R' (FDE encoding) entry to the
@@ -322,6 +331,9 @@ struct eh_cie_fde
 
       /* True if we have merged this CIE with another.  */
       unsigned int merged : 1;
+
+      /* Unused bits.  */
+      unsigned int pad1 : 18;
     } cie;
   } u;
   unsigned int reloc_index;
@@ -1491,6 +1503,10 @@ struct elf_obj_tdata
      one.  */
   const char *dt_name;
 
+  /* The linker emulation needs to know what audit libs
+     are used by a dynamic object.  */ 
+  const char *dt_audit;
+
   /* Records the result of `get_program_header_size'.  */
   bfd_size_type program_header_size;
 
@@ -1620,6 +1636,7 @@ struct elf_obj_tdata
 #define elf_local_got_offsets(bfd) (elf_tdata(bfd) -> local_got.offsets)
 #define elf_local_got_ents(bfd) (elf_tdata(bfd) -> local_got.ents)
 #define elf_dt_name(bfd)       (elf_tdata(bfd) -> dt_name)
+#define elf_dt_audit(bfd)      (elf_tdata(bfd) -> dt_audit)
 #define elf_dyn_lib_class(bfd) (elf_tdata(bfd) -> dyn_lib_class)
 #define elf_bad_symtab(bfd)    (elf_tdata(bfd) -> bad_symtab)
 #define elf_flags_init(bfd)    (elf_tdata(bfd) -> flags_init)

diff --git a/bfd/elf-eh-frame.c b/bfd/elf-eh-frame.c
index 5525d20..5d1def9 100644 (file)
--- a/bfd/elf-eh-frame.c
+++ b/bfd/elf-eh-frame.c
@@ -423,6 +423,28 @@ skip_non_nops (bfd_byte *buf, bfd_byte *end, unsigned int encoded_ptr_width,
   return last;
 }
 
+/* Convert absolute encoding ENCODING into PC-relative form.
+   SIZE is the size of a pointer.  */
+
+static unsigned char
+make_pc_relative (unsigned char encoding, unsigned int ptr_size)
+{
+  if ((encoding & 0x7f) == DW_EH_PE_absptr)
+    switch (ptr_size)
+      {
+      case 2:
+       encoding |= DW_EH_PE_sdata2;
+       break;
+      case 4:
+       encoding |= DW_EH_PE_sdata4;
+       break;
+      case 8:
+       encoding |= DW_EH_PE_sdata8;
+       break;
+      }
+  return encoding | DW_EH_PE_pcrel;
+}
+
 /* Called before calling _bfd_elf_parse_eh_frame on every input bfd's
    .eh_frame section.  */
 
@@ -675,11 +697,12 @@ _bfd_elf_parse_eh_frame (bfd *abfd, struct bfd_link_info *info,
                      per_width = get_DW_EH_PE_width (cie->per_encoding,
                                                      ptr_size);
                      REQUIRE (per_width);
-                     if ((cie->per_encoding & 0xf0) == DW_EH_PE_aligned)
+                     if ((cie->per_encoding & 0x70) == DW_EH_PE_aligned)
                        {
                          length = -(buf - ehbuf) & (per_width - 1);
                          REQUIRE (skip_bytes (&buf, end, length));
                        }
+                     this_inf->u.cie.personality_offset = buf - start;
                      ENSURE_NO_RELOCS (buf);
                      /* Ensure we have a reloc here.  */
                      REQUIRE (GET_RELOC (buf));
@@ -705,27 +728,23 @@ _bfd_elf_parse_eh_frame (bfd *abfd, struct bfd_link_info *info,
                  ->elf_backend_can_make_relative_eh_frame
                  (abfd, info, sec)))
            {
-             if ((cie->fde_encoding & 0xf0) == DW_EH_PE_absptr)
+             if ((cie->fde_encoding & 0x70) == DW_EH_PE_absptr)
                this_inf->make_relative = 1;
              /* If the CIE doesn't already have an 'R' entry, it's fairly
                 easy to add one, provided that there's no aligned data
                 after the augmentation string.  */
              else if (cie->fde_encoding == DW_EH_PE_omit
-                      && (cie->per_encoding & 0xf0) != DW_EH_PE_aligned)
+                      && (cie->per_encoding & 0x70) != DW_EH_PE_aligned)
                {
                  if (*cie->augmentation == 0)
                    this_inf->add_augmentation_size = 1;
                  this_inf->u.cie.add_fde_encoding = 1;
                  this_inf->make_relative = 1;
                }
-           }
 
-         if (info->shared
-             && (get_elf_backend_data (abfd)
-                 ->elf_backend_can_make_lsda_relative_eh_frame
-                 (abfd, info, sec))
-             && (cie->lsda_encoding & 0xf0) == DW_EH_PE_absptr)
-           cie->can_make_lsda_relative = 1;
+             if ((cie->lsda_encoding & 0x70) == DW_EH_PE_absptr)
+               cie->can_make_lsda_relative = 1;
+           }
 
          /* If FDE encoding was not specified, it defaults to
             DW_EH_absptr.  */
@@ -843,7 +862,7 @@ _bfd_elf_parse_eh_frame (bfd *abfd, struct bfd_link_info *info,
          cie->length -= end - insns_end;
        }
       if (set_loc_count
-         && ((cie->fde_encoding & 0xf0) == DW_EH_PE_pcrel
+         && ((cie->fde_encoding & 0x70) == DW_EH_PE_pcrel
              || this_inf->make_relative))
        {
          unsigned int cnt;
@@ -963,7 +982,7 @@ _bfd_elf_gc_mark_fdes (struct bfd_link_info *info, asection *sec,
    relocations in REL.  */
 
 static struct eh_cie_fde *
-find_merged_cie (bfd *abfd, asection *sec,
+find_merged_cie (bfd *abfd, struct bfd_link_info *info, asection *sec,
                 struct eh_frame_hdr_info *hdr_info,
                 struct elf_reloc_cookie *cookie,
                 struct eh_cie_fde *cie_inf)
@@ -993,6 +1012,8 @@ find_merged_cie (bfd *abfd, asection *sec,
 
   if (cie->per_encoding != DW_EH_PE_omit)
     {
+      bfd_boolean per_binds_local;
+
       /* Work out the address of personality routine, either as an absolute
         value or as a symbol.  */
       rel = cookie->rels + cie->personality.reloc_index;
@@ -1016,6 +1037,7 @@ find_merged_cie (bfd *abfd, asection *sec,
            h = (struct elf_link_hash_entry *) h->root.u.i.link;
 
          cie->personality.h = h;
+         per_binds_local = SYMBOL_REFERENCES_LOCAL (info, h);
        }
       else
        {
@@ -1036,6 +1058,17 @@ find_merged_cie (bfd *abfd, asection *sec,
          cie->personality.val = (sym->st_value
                                  + sym_sec->output_offset
                                  + sym_sec->output_section->vma);
+         per_binds_local = TRUE;
+       }
+
+      if (per_binds_local
+         && info->shared
+         && (cie->per_encoding & 0x70) == DW_EH_PE_absptr
+         && (get_elf_backend_data (abfd)
+             ->elf_backend_can_make_relative_eh_frame (abfd, info, sec)))
+       {
+         cie_inf->u.cie.make_per_encoding_relative = 1;
+         cie_inf->u.cie.per_encoding_relative = 1;
        }
     }
 
@@ -1110,9 +1143,9 @@ _bfd_elf_discard_section_eh_frame
        if (!(*reloc_symbol_deleted_p) (ent->offset + 8, cookie))
          {
            if (info->shared
-               && (((ent->fde_encoding & 0xf0) == DW_EH_PE_absptr
+               && (((ent->fde_encoding & 0x70) == DW_EH_PE_absptr
                     && ent->make_relative == 0)
-                   || (ent->fde_encoding & 0xf0) == DW_EH_PE_aligned))
+                   || (ent->fde_encoding & 0x70) == DW_EH_PE_aligned))
              {
                /* If a shared library uses absolute pointers
                   which we cannot turn into PC relative,
@@ -1125,8 +1158,8 @@ _bfd_elf_discard_section_eh_frame
              }
            ent->removed = 0;
            hdr_info->fde_count++;
-           ent->u.fde.cie_inf = find_merged_cie (abfd, sec, hdr_info, cookie,
-                                                 ent->u.fde.cie_inf);
+           ent->u.fde.cie_inf = find_merged_cie (abfd, info, sec, hdr_info,
+                                                 cookie, ent->u.fde.cie_inf);
          }
       }
 
@@ -1276,6 +1309,14 @@ _bfd_elf_eh_frame_section_offset (bfd *output_bfd ATTRIBUTE_UNUSED,
   if (sec_info->entry[mid].removed)
     return (bfd_vma) -1;
 
+  /* If converting personality pointers to DW_EH_PE_pcrel, there will be
+     no need for run-time relocation against the personality field.  */
+  if (sec_info->entry[mid].cie
+      && sec_info->entry[mid].u.cie.make_per_encoding_relative
+      && offset == (sec_info->entry[mid].offset + 8
+                   + sec_info->entry[mid].u.cie.personality_offset))
+    return (bfd_vma) -2;
+
   /* If converting to DW_EH_PE_pcrel, there will be no need for run-time
      relocation against FDE's initial_location field.  */
   if (!sec_info->entry[mid].cie
@@ -1435,7 +1476,7 @@ _bfd_elf_write_section_eh_frame (bfd *abfd,
                {
                  BFD_ASSERT (action & 1);
                  *aug++ = 'R';
-                 *buf++ = DW_EH_PE_pcrel;
+                 *buf++ = make_pc_relative (DW_EH_PE_absptr, ptr_size);
                  action &= ~1;
                }
 
@@ -1446,18 +1487,20 @@ _bfd_elf_write_section_eh_frame (bfd *abfd,
                    if (action & 2)
                      {
                        BFD_ASSERT (*buf == ent->lsda_encoding);
-                       *buf |= DW_EH_PE_pcrel;
+                       *buf = make_pc_relative (*buf, ptr_size);
                        action &= ~2;
                      }
                    buf++;
                    break;
                  case 'P':
+                   if (ent->u.cie.make_per_encoding_relative)
+                     *buf = make_pc_relative (*buf, ptr_size);
                    per_encoding = *buf++;
                    per_width = get_DW_EH_PE_width (per_encoding, ptr_size);
                    BFD_ASSERT (per_width != 0);
                    BFD_ASSERT (((per_encoding & 0x70) == DW_EH_PE_pcrel)
                                == ent->u.cie.per_encoding_relative);
-                   if ((per_encoding & 0xf0) == DW_EH_PE_aligned)
+                   if ((per_encoding & 0x70) == DW_EH_PE_aligned)
                      buf = (contents
                             + ((buf - contents + per_width - 1)
                                & ~((bfd_size_type) per_width - 1)));
@@ -1467,8 +1510,15 @@ _bfd_elf_write_section_eh_frame (bfd *abfd,
 
                        val = read_value (abfd, buf, per_width,
                                          get_DW_EH_PE_signed (per_encoding));
-                       val += (bfd_vma) ent->offset - ent->new_offset;
-                       val -= extra_string + extra_data;
+                       if (ent->u.cie.make_per_encoding_relative)
+                         val -= (sec->output_section->vma
+                                 + sec->output_offset
+                                 + (buf - contents));
+                       else
+                         {
+                           val += (bfd_vma) ent->offset - ent->new_offset;
+                           val -= extra_string + extra_data;
+                         }
                        write_value (abfd, buf, val, per_width);
                        action &= ~4;
                      }
@@ -1478,7 +1528,7 @@ _bfd_elf_write_section_eh_frame (bfd *abfd,
                    if (action & 1)
                      {
                        BFD_ASSERT (*buf == ent->fde_encoding);
-                       *buf |= DW_EH_PE_pcrel;
+                       *buf = make_pc_relative (*buf, ptr_size);
                        action &= ~1;
                      }
                    buf++;
@@ -1511,9 +1561,8 @@ _bfd_elf_write_section_eh_frame (bfd *abfd,
          address = value;
          if (value)
            {
-             switch (ent->fde_encoding & 0xf0)
+             switch (ent->fde_encoding & 0x70)
                {
-               case DW_EH_PE_indirect:
                case DW_EH_PE_textrel:
                  BFD_ASSERT (hdr_info == NULL);
                  break;
@@ -1550,7 +1599,7 @@ _bfd_elf_write_section_eh_frame (bfd *abfd,
                   + ent->new_offset);
            }
 
-         if ((ent->lsda_encoding & 0xf0) == DW_EH_PE_pcrel
+         if ((ent->lsda_encoding & 0x70) == DW_EH_PE_pcrel
              || cie->u.cie.make_lsda_relative)
            {
              buf += ent->lsda_offset;
@@ -1559,7 +1608,7 @@ _bfd_elf_write_section_eh_frame (bfd *abfd,
                                  get_DW_EH_PE_signed (ent->lsda_encoding));
              if (value)
                {
-                 if ((ent->lsda_encoding & 0xf0) == DW_EH_PE_pcrel)
+                 if ((ent->lsda_encoding & 0x70) == DW_EH_PE_pcrel)
                    value += (bfd_vma) ent->offset - ent->new_offset;
                  else if (cie->u.cie.make_lsda_relative)
                    value -= (sec->output_section->vma
@@ -1598,7 +1647,7 @@ _bfd_elf_write_section_eh_frame (bfd *abfd,
                  if (!value)
                    continue;
 
-                 if ((ent->fde_encoding & 0xf0) == DW_EH_PE_pcrel)
+                 if ((ent->fde_encoding & 0x70) == DW_EH_PE_pcrel)
                    value += (bfd_vma) ent->offset + 8 - new_offset;
                  if (ent->make_relative)
                    value -= (sec->output_section->vma

diff --git a/bfd/elf.c b/bfd/elf.c
index e7116d8..4a32929 100644 (file)
--- a/bfd/elf.c
+++ b/bfd/elf.c
@@ -1518,10 +1518,11 @@ bfd_section_from_shdr (bfd *abfd, unsigned int shindex)
        return FALSE;
       if (hdr->sh_link > elf_numsections (abfd))
        {
-         /* PR 10478: Accept sparc binaries with a sh_link
+         /* PR 10478: Accept Solaris binaries with a sh_link
             field set to SHN_BEFORE or SHN_AFTER.  */
          switch (bfd_get_arch (abfd))
            {
+           case bfd_arch_i386:
            case bfd_arch_sparc:
              if (hdr->sh_link == (SHN_LORESERVE & 0xffff) /* SHN_BEFORE */
                  || hdr->sh_link == ((SHN_LORESERVE + 1) & 0xffff) /* SHN_AFTER */)

diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index 157024c..b449ee8 100644 (file)
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -61,8 +61,6 @@
 #define ARM_ELF_ABI_VERSION            0
 #define ARM_ELF_OS_ABI_VERSION         ELFOSABI_ARM
 
-static struct elf_backend_data elf32_arm_vxworks_bed;
-
 static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
                                            struct bfd_link_info *link_info,
                                            asection *sec,
@@ -2523,6 +2521,17 @@ struct elf32_arm_link_hash_entry
   ((struct elf32_arm_stub_hash_entry *) \
    bfd_hash_lookup ((table), (string), (create), (copy)))
 
+/* Array to keep track of which stub sections have been created, and
+   information on stub grouping.  */
+struct map_stub
+{
+  /* This is the section to which stubs in the group will be
+     attached.  */
+  asection *link_sec;
+  /* The stub section.  */
+  asection *stub_sec;
+};
+
 /* ARM ELF linker hash table.  */
 struct elf32_arm_link_hash_table
 {
@@ -2638,14 +2647,7 @@ struct elf32_arm_link_hash_table
 
   /* Array to keep track of which stub sections have been created, and
      information on stub grouping.  */
-  struct map_stub
-  {
-    /* This is the section to which stubs in the group will be
-       attached.  */
-    asection *link_sec;
-    /* The stub section.  */
-    asection *stub_sec;
-  } *stub_group;
+  struct map_stub *stub_group;
 
   /* Assorted information used by elf32_arm_size_stubs.  */
   unsigned int bfd_count;
@@ -2666,7 +2668,8 @@ elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
   /* Allocate the structure if it has not already been allocated by a
      subclass.  */
   if (ret == NULL)
-    ret = bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
+    ret = (struct elf32_arm_link_hash_entry *)
+        bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
   if (ret == NULL)
     return (struct bfd_hash_entry *) ret;
 
@@ -2700,8 +2703,8 @@ stub_hash_newfunc (struct bfd_hash_entry *entry,
      subclass.  */
   if (entry == NULL)
     {
-      entry = bfd_hash_allocate (table,
-                                sizeof (struct elf32_arm_stub_hash_entry));
+      entry = (struct bfd_hash_entry *)
+          bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
       if (entry == NULL)
        return entry;
     }
@@ -2882,7 +2885,7 @@ elf32_arm_link_hash_table_create (bfd *abfd)
   struct elf32_arm_link_hash_table *ret;
   bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
 
-  ret = bfd_malloc (amt);
+  ret = (struct elf32_arm_link_hash_table *) bfd_malloc (amt);
   if (ret == NULL)
     return NULL;
 
@@ -3248,7 +3251,7 @@ elf32_arm_stub_name (const asection *input_section,
   if (hash)
     {
       len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1;
-      stub_name = bfd_malloc (len);
+      stub_name = (char *) bfd_malloc (len);
       if (stub_name != NULL)
        sprintf (stub_name, "%08x_%s+%x",
                 input_section->id & 0xffffffff,
@@ -3258,7 +3261,7 @@ elf32_arm_stub_name (const asection *input_section,
   else
     {
       len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1;
-      stub_name = bfd_malloc (len);
+      stub_name = (char *) bfd_malloc (len);
       if (stub_name != NULL)
        sprintf (stub_name, "%08x_%x:%x+%x",
                 input_section->id & 0xffffffff,
@@ -3343,7 +3346,7 @@ elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
 
          namelen = strlen (link_sec->name);
          len = namelen + sizeof (STUB_SUFFIX);
-         s_name = bfd_alloc (htab->stub_bfd, len);
+         s_name = (char *) bfd_alloc (htab->stub_bfd, len);
          if (s_name == NULL)
            return NULL;
 
@@ -3725,7 +3728,7 @@ elf32_arm_setup_section_lists (bfd *output_bfd,
   htab->bfd_count = bfd_count;
 
   amt = sizeof (struct map_stub) * (top_id + 1);
-  htab->stub_group = bfd_zmalloc (amt);
+  htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
   if (htab->stub_group == NULL)
     return -1;
 
@@ -3742,7 +3745,7 @@ elf32_arm_setup_section_lists (bfd *output_bfd,
 
   htab->top_index = top_index;
   amt = sizeof (asection *) * (top_index + 1);
-  input_list = bfd_malloc (amt);
+  input_list = (asection **) bfd_malloc (amt);
   htab->input_list = input_list;
   if (input_list == NULL)
     return -1;
@@ -3899,7 +3902,8 @@ group_sections (struct elf32_arm_link_hash_table *htab,
 static int
 a8_reloc_compare (const void *a, const void *b)
 {
-  const struct a8_erratum_reloc *ra = a, *rb = b;
+  const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
+  const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
 
   if (ra->from < rb->from)
     return -1;
@@ -4024,9 +4028,10 @@ cortex_a8_erratum_scan (bfd *input_bfd,
                   struct a8_erratum_reloc key, *found;
 
                   key.from = base_vma + i;
-                  found = bsearch (&key, a8_relocs, num_a8_relocs,
-                                   sizeof (struct a8_erratum_reloc),
-                                   &a8_reloc_compare);
+                  found = (struct a8_erratum_reloc *)
+                      bsearch (&key, a8_relocs, num_a8_relocs,
+                               sizeof (struct a8_erratum_reloc),
+                               &a8_reloc_compare);
 
                  if (found)
                    {
@@ -4143,9 +4148,10 @@ cortex_a8_erratum_scan (bfd *input_bfd,
                           if (num_a8_fixes == a8_fix_table_size)
                             {
                               a8_fix_table_size *= 2;
-                              a8_fixes = bfd_realloc (a8_fixes,
-                                sizeof (struct a8_erratum_fix)
-                                * a8_fix_table_size);
+                              a8_fixes = (struct a8_erratum_fix *)
+                                  bfd_realloc (a8_fixes,
+                                               sizeof (struct a8_erratum_fix)
+                                               * a8_fix_table_size);
                             }
 
                          if (num_a8_fixes < prev_num_a8_fixes)
@@ -4166,7 +4172,7 @@ cortex_a8_erratum_scan (bfd *input_bfd,
 
                          if (!stub_name)
                            {
-                             stub_name = bfd_malloc (8 + 1 + 8 + 1);
+                             stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
                              if (stub_name != NULL)
                                sprintf (stub_name, "%x:%x", section->id, i);
                            }
@@ -4225,10 +4231,10 @@ elf32_arm_size_stubs (bfd *output_bfd,
 
   if (htab->fix_cortex_a8)
     {
-      a8_fixes = bfd_zmalloc (sizeof (struct a8_erratum_fix)
-                              * a8_fix_table_size);
-      a8_relocs = bfd_zmalloc (sizeof (struct a8_erratum_reloc)
-                               * a8_reloc_table_size);
+      a8_fixes = (struct a8_erratum_fix *)
+          bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
+      a8_relocs = (struct a8_erratum_reloc *)
+          bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
     }
 
   /* Propagate mach to stub bfd, because it may not have been
@@ -4539,8 +4545,8 @@ elf32_arm_size_stubs (bfd *output_bfd,
 
                       if (sym_name == NULL)
                        sym_name = "unnamed";
-                      stub_entry->output_name
-                       = bfd_alloc (htab->stub_bfd,
+                      stub_entry->output_name = (char *)
+                          bfd_alloc (htab->stub_bfd,
                                      sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
                                      + strlen (sym_name));
                       if (stub_entry->output_name == NULL)
@@ -4591,9 +4597,10 @@ elf32_arm_size_stubs (bfd *output_bfd,
                           if (num_a8_relocs == a8_reloc_table_size)
                             {
                               a8_reloc_table_size *= 2;
-                              a8_relocs = bfd_realloc (a8_relocs,
-                                sizeof (struct a8_erratum_reloc)
-                                * a8_reloc_table_size);
+                              a8_relocs = (struct a8_erratum_reloc *)
+                                  bfd_realloc (a8_relocs,
+                                               sizeof (struct a8_erratum_reloc)
+                                               * a8_reloc_table_size);
                             }
 
                           a8_relocs[num_a8_relocs].from = from;
@@ -4757,7 +4764,7 @@ elf32_arm_build_stubs (struct bfd_link_info *info)
 
       /* Allocate memory to hold the linker stubs.  */
       size = stub_sec->size;
-      stub_sec->contents = bfd_zalloc (htab->stub_bfd, size);
+      stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
       if (stub_sec->contents == NULL && size != 0)
        return FALSE;
       stub_sec->size = 0;
@@ -4790,8 +4797,8 @@ find_thumb_glue (struct bfd_link_info *link_info,
   /* We need a pointer to the armelf specific hash table.  */
   hash_table = elf32_arm_hash_table (link_info);
 
-  tmp_name = bfd_malloc ((bfd_size_type) strlen (name)
-                        + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
+  tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
+                                  + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
 
   BFD_ASSERT (tmp_name);
 
@@ -4824,8 +4831,8 @@ find_arm_glue (struct bfd_link_info *link_info,
   /* We need a pointer to the elfarm specific hash table.  */
   hash_table = elf32_arm_hash_table (link_info);
 
-  tmp_name = bfd_malloc ((bfd_size_type) strlen (name)
-                        + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
+  tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
+                                  + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
 
   BFD_ASSERT (tmp_name);
 
@@ -4935,7 +4942,7 @@ arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * na
   s = bfd_get_section_by_name (abfd, name);
   BFD_ASSERT (s != NULL);
 
-  contents = bfd_alloc (abfd, size);
+  contents = (bfd_byte *) bfd_alloc (abfd, size);
 
   BFD_ASSERT (s->size == size);
   s->contents = contents;
@@ -4994,7 +5001,8 @@ record_arm_to_thumb_glue (struct bfd_link_info * link_info,
 
   BFD_ASSERT (s != NULL);
 
-  tmp_name = bfd_malloc ((bfd_size_type) strlen (name) + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
+  tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
+                                  + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
 
   BFD_ASSERT (tmp_name);
 
@@ -5071,7 +5079,8 @@ record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
   BFD_ASSERT (s != NULL);
 
   /* Add symbol for veneer.  */
-  tmp_name = bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
+  tmp_name = (char *)
+      bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
 
   BFD_ASSERT (tmp_name);
 
@@ -5108,7 +5117,8 @@ elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
 
   if (sec_data->map == NULL)
     {
-      sec_data->map = bfd_malloc (sizeof (elf32_arm_section_map));
+      sec_data->map = (elf32_arm_section_map *)
+          bfd_malloc (sizeof (elf32_arm_section_map));
       sec_data->mapcount = 0;
       sec_data->mapsize = 1;
     }
@@ -5118,8 +5128,9 @@ elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
   if (sec_data->mapcount > sec_data->mapsize)
     {
       sec_data->mapsize *= 2;
-      sec_data->map = bfd_realloc_or_free (sec_data->map, sec_data->mapsize
-                                          * sizeof (elf32_arm_section_map));
+      sec_data->map = (elf32_arm_section_map *)
+          bfd_realloc_or_free (sec_data->map, sec_data->mapsize
+                               * sizeof (elf32_arm_section_map));
     }
 
   if (sec_data->map)
@@ -5162,8 +5173,8 @@ record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
 
   BFD_ASSERT (s != NULL);
 
-  tmp_name = bfd_malloc ((bfd_size_type) strlen
-                        (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
+  tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
+                                  (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
 
   BFD_ASSERT (tmp_name);
 
@@ -5187,7 +5198,8 @@ record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
 
   /* Link veneer back to calling location.  */
   errcount = ++(sec_data->erratumcount);
-  newerr = bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
+  newerr = (elf32_vfp11_erratum_list *)
+      bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
 
   newerr->type = VFP11_ERRATUM_ARM_VENEER;
   newerr->vma = -1;
@@ -6033,8 +6045,8 @@ bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
 
               if (state == 3)
                 {
-                  elf32_vfp11_erratum_list *newerr
-                    = bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
+                  elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
+                      bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
                   int errcount;
 
                   errcount = ++(elf32_arm_section_data (sec)->erratumcount);
@@ -6102,8 +6114,8 @@ bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
 
   globals = elf32_arm_hash_table (link_info);
 
-  tmp_name = bfd_malloc ((bfd_size_type) strlen
-                          (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
+  tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
+                                  (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
 
   for (sec = abfd->sections; sec != NULL; sec = sec->next)
     {
@@ -8092,7 +8104,7 @@ elf32_arm_final_link_relocate (reloc_howto_type *           howto,
            (_("%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object"),
             input_bfd, input_section,
             (long) rel->r_offset, howto->name);
-         return FALSE;
+         return (bfd_reloc_status_type) FALSE;
        }
       else
        value = tpoff (info, value);
@@ -9042,7 +9054,8 @@ add_unwind_table_edit (arm_unwind_table_edit **head,
                       asection *linked_section,
                       unsigned int index)
 {
-  arm_unwind_table_edit *new_edit = xmalloc (sizeof (arm_unwind_table_edit));
+  arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
+      xmalloc (sizeof (arm_unwind_table_edit));
   
   new_edit->type = type;
   new_edit->linked_section = linked_section;
@@ -9539,7 +9552,7 @@ set_secondary_compatible_arch (bfd *abfd, int arch)
   /* Note: the tag and its argument below are uleb128 values, though
      currently-defined values fit in one byte for each.  */
   if (!attr->s)
-    attr->s = bfd_alloc (abfd, 3);
+    attr->s = (char *) bfd_alloc (abfd, 3);
   attr->s[0] = Tag_CPU_arch;
   attr->s[1] = arch;
   attr->s[2] = '\0';
@@ -10195,225 +10208,7 @@ elf32_arm_versions_compatible (unsigned iver, unsigned over)
    object file when linking.  */
 
 static bfd_boolean
-elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
-{
-  flagword out_flags;
-  flagword in_flags;
-  bfd_boolean flags_compatible = TRUE;
-  asection *sec;
-
-  /* Check if we have the same endianess.  */
-  if (! _bfd_generic_verify_endian_match (ibfd, obfd))
-    return FALSE;
-
-  if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
-    return TRUE;
-
-  if (!elf32_arm_merge_eabi_attributes (ibfd, obfd))
-    return FALSE;
-
-  /* The input BFD must have had its flags initialised.  */
-  /* The following seems bogus to me -- The flags are initialized in
-     the assembler but I don't think an elf_flags_init field is
-     written into the object.  */
-  /* BFD_ASSERT (elf_flags_init (ibfd)); */
-
-  in_flags  = elf_elfheader (ibfd)->e_flags;
-  out_flags = elf_elfheader (obfd)->e_flags;
-
-  /* In theory there is no reason why we couldn't handle this.  However
-     in practice it isn't even close to working and there is no real
-     reason to want it.  */
-  if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
-      && !(ibfd->flags & DYNAMIC)
-      && (in_flags & EF_ARM_BE8))
-    {
-      _bfd_error_handler (_("error: %B is already in final BE8 format"),
-                         ibfd);
-      return FALSE;
-    }
-
-  if (!elf_flags_init (obfd))
-    {
-      /* If the input is the default architecture and had the default
-        flags then do not bother setting the flags for the output
-        architecture, instead allow future merges to do this.  If no
-        future merges ever set these flags then they will retain their
-         uninitialised values, which surprise surprise, correspond
-         to the default values.  */
-      if (bfd_get_arch_info (ibfd)->the_default
-         && elf_elfheader (ibfd)->e_flags == 0)
-       return TRUE;
-
-      elf_flags_init (obfd) = TRUE;
-      elf_elfheader (obfd)->e_flags = in_flags;
-
-      if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
-         && bfd_get_arch_info (obfd)->the_default)
-       return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
-
-      return TRUE;
-    }
-
-  /* Determine what should happen if the input ARM architecture
-     does not match the output ARM architecture.  */
-  if (! bfd_arm_merge_machines (ibfd, obfd))
-    return FALSE;
-
-  /* Identical flags must be compatible.  */
-  if (in_flags == out_flags)
-    return TRUE;
-
-  /* Check to see if the input BFD actually contains any sections.  If
-     not, its flags may not have been initialised either, but it
-     cannot actually cause any incompatiblity.  Do not short-circuit
-     dynamic objects; their section list may be emptied by
-    elf_link_add_object_symbols.
-
-    Also check to see if there are no code sections in the input.
-    In this case there is no need to check for code specific flags.
-    XXX - do we need to worry about floating-point format compatability
-    in data sections ?  */
-  if (!(ibfd->flags & DYNAMIC))
-    {
-      bfd_boolean null_input_bfd = TRUE;
-      bfd_boolean only_data_sections = TRUE;
-
-      for (sec = ibfd->sections; sec != NULL; sec = sec->next)
-       {
-         /* Ignore synthetic glue sections.  */
-         if (strcmp (sec->name, ".glue_7")
-             && strcmp (sec->name, ".glue_7t"))
-           {
-             if ((bfd_get_section_flags (ibfd, sec)
-                  & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
-                 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
-               only_data_sections = FALSE;
-
-             null_input_bfd = FALSE;
-             break;
-           }
-       }
-
-      if (null_input_bfd || only_data_sections)
-       return TRUE;
-    }
-
-  /* Complain about various flag mismatches.  */
-  if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
-                                     EF_ARM_EABI_VERSION (out_flags)))
-    {
-      _bfd_error_handler
-       (_("error: Source object %B has EABI version %d, but target %B has EABI version %d"),
-        ibfd, obfd,
-        (in_flags & EF_ARM_EABIMASK) >> 24,
-        (out_flags & EF_ARM_EABIMASK) >> 24);
-      return FALSE;
-    }
-
-  /* Not sure what needs to be checked for EABI versions >= 1.  */
-  /* VxWorks libraries do not use these flags.  */
-  if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
-      && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
-      && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
-    {
-      if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
-       {
-         _bfd_error_handler
-           (_("error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"),
-            ibfd, obfd,
-            in_flags & EF_ARM_APCS_26 ? 26 : 32,
-            out_flags & EF_ARM_APCS_26 ? 26 : 32);
-         flags_compatible = FALSE;
-       }
-
-      if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
-       {
-         if (in_flags & EF_ARM_APCS_FLOAT)
-           _bfd_error_handler
-             (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
-              ibfd, obfd);
-         else
-           _bfd_error_handler
-             (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
-              ibfd, obfd);
-
-         flags_compatible = FALSE;
-       }
-
-      if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
-       {
-         if (in_flags & EF_ARM_VFP_FLOAT)
-           _bfd_error_handler
-             (_("error: %B uses VFP instructions, whereas %B does not"),
-              ibfd, obfd);
-         else
-           _bfd_error_handler
-             (_("error: %B uses FPA instructions, whereas %B does not"),
-              ibfd, obfd);
-
-         flags_compatible = FALSE;
-       }
-
-      if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
-       {
-         if (in_flags & EF_ARM_MAVERICK_FLOAT)
-           _bfd_error_handler
-             (_("error: %B uses Maverick instructions, whereas %B does not"),
-              ibfd, obfd);
-         else
-           _bfd_error_handler
-             (_("error: %B does not use Maverick instructions, whereas %B does"),
-              ibfd, obfd);
-
-         flags_compatible = FALSE;
-       }
-
-#ifdef EF_ARM_SOFT_FLOAT
-      if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
-       {
-         /* We can allow interworking between code that is VFP format
-            layout, and uses either soft float or integer regs for
-            passing floating point arguments and results.  We already
-            know that the APCS_FLOAT flags match; similarly for VFP
-            flags.  */
-         if ((in_flags & EF_ARM_APCS_FLOAT) != 0
-             || (in_flags & EF_ARM_VFP_FLOAT) == 0)
-           {
-             if (in_flags & EF_ARM_SOFT_FLOAT)
-               _bfd_error_handler
-                 (_("error: %B uses software FP, whereas %B uses hardware FP"),
-                  ibfd, obfd);
-             else
-               _bfd_error_handler
-                 (_("error: %B uses hardware FP, whereas %B uses software FP"),
-                  ibfd, obfd);
-
-             flags_compatible = FALSE;
-           }
-       }
-#endif
-
-      /* Interworking mismatch is only a warning.  */
-      if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
-       {
-         if (in_flags & EF_ARM_INTERWORK)
-           {
-             _bfd_error_handler
-               (_("Warning: %B supports interworking, whereas %B does not"),
-                ibfd, obfd);
-           }
-         else
-           {
-             _bfd_error_handler
-               (_("Warning: %B does not support interworking, whereas %B does"),
-                ibfd, obfd);
-           }
-       }
-    }
-
-  return flags_compatible;
-}
+elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd);
 
 /* Display the flags field.  */
 
@@ -10838,7 +10633,8 @@ elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
 
                      size = symtab_hdr->sh_info;
                      size *= (sizeof (bfd_signed_vma) + sizeof (char));
-                     local_got_refcounts = bfd_zalloc (abfd, size);
+                     local_got_refcounts = (bfd_signed_vma *)
+                          bfd_zalloc (abfd, size);
                      if (local_got_refcounts == NULL)
                        return FALSE;
                      elf_local_got_refcounts (abfd) = local_got_refcounts;
@@ -11037,7 +10833,8 @@ elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
                  {
                    bfd_size_type amt = sizeof *p;
 
-                   p = bfd_alloc (htab->root.dynobj, amt);
+                   p = (struct elf32_arm_relocs_copied *)
+                        bfd_alloc (htab->root.dynobj, amt);
                    if (p == NULL)
                      return FALSE;
                    p->next = *head;
@@ -11811,7 +11608,8 @@ elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
        {
          struct elf32_arm_relocs_copied *p;
 
-         for (p = elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
+         for (p = (struct elf32_arm_relocs_copied *)
+                   elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
            {
              if (!bfd_is_abs_section (p->section)
                  && bfd_is_abs_section (p->section->output_section))
@@ -11965,7 +11763,7 @@ elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
        continue;
 
       /* Allocate memory for the section contents.  */
-      s->contents = bfd_zalloc (dynobj, s->size);
+      s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
       if (s->contents == NULL)
        return FALSE;
     }
@@ -12760,7 +12558,7 @@ record_section_with_arm_elf_section_data (asection * sec)
 {
   struct section_list * entry;
 
-  entry = bfd_malloc (sizeof (* entry));
+  entry = (struct section_list *) bfd_malloc (sizeof (* entry));
   if (entry == NULL)
     return;
   entry->sec = sec;
@@ -13224,7 +13022,7 @@ elf32_arm_new_section_hook (bfd *abfd, asection *sec)
       _arm_elf_section_data *sdata;
       bfd_size_type amt = sizeof (*sdata);
 
-      sdata = bfd_zalloc (abfd, amt);
+      sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
       if (sdata == NULL)
        return FALSE;
       sec->used_by_bfd = sdata;
@@ -13516,7 +13314,7 @@ elf32_arm_write_section (bfd *output_bfd,
          size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
         markers) was sec->rawsize.  (This isn't the case if we perform no
         edits, then rawsize will be zero and we should use size).  */
-      bfd_byte *edited_contents = bfd_malloc (sec->size);
+      bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
       unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
       unsigned int in_index, out_index;
       bfd_vma add_to_offsets = 0;
@@ -13789,7 +13587,8 @@ elf32_arm_modify_segment_map (bfd *abfd,
        m = m->next;
       if (!m)
        {
-         m = bfd_zalloc (abfd, sizeof (struct elf_segment_map));
+         m = (struct elf_segment_map *)
+              bfd_zalloc (abfd, sizeof (struct elf_segment_map));
          if (m == NULL)
            return FALSE;
          m->p_type = PT_ARM_EXIDX;
@@ -14001,6 +13800,231 @@ elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
 #include "elf32-target.h"
 
 
+/* Merge backend specific data from an object file to the output
+   object file when linking.  */
+
+static bfd_boolean
+elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
+{
+  flagword out_flags;
+  flagword in_flags;
+  bfd_boolean flags_compatible = TRUE;
+  asection *sec;
+
+  /* Check if we have the same endianess.  */
+  if (! _bfd_generic_verify_endian_match (ibfd, obfd))
+    return FALSE;
+
+  if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
+    return TRUE;
+
+  if (!elf32_arm_merge_eabi_attributes (ibfd, obfd))
+    return FALSE;
+
+  /* The input BFD must have had its flags initialised.  */
+  /* The following seems bogus to me -- The flags are initialized in
+     the assembler but I don't think an elf_flags_init field is
+     written into the object.  */
+  /* BFD_ASSERT (elf_flags_init (ibfd)); */
+
+  in_flags  = elf_elfheader (ibfd)->e_flags;
+  out_flags = elf_elfheader (obfd)->e_flags;
+
+  /* In theory there is no reason why we couldn't handle this.  However
+     in practice it isn't even close to working and there is no real
+     reason to want it.  */
+  if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
+      && !(ibfd->flags & DYNAMIC)
+      && (in_flags & EF_ARM_BE8))
+    {
+      _bfd_error_handler (_("error: %B is already in final BE8 format"),
+                         ibfd);
+      return FALSE;
+    }
+
+  if (!elf_flags_init (obfd))
+    {
+      /* If the input is the default architecture and had the default
+        flags then do not bother setting the flags for the output
+        architecture, instead allow future merges to do this.  If no
+        future merges ever set these flags then they will retain their
+         uninitialised values, which surprise surprise, correspond
+         to the default values.  */
+      if (bfd_get_arch_info (ibfd)->the_default
+         && elf_elfheader (ibfd)->e_flags == 0)
+       return TRUE;
+
+      elf_flags_init (obfd) = TRUE;
+      elf_elfheader (obfd)->e_flags = in_flags;
+
+      if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
+         && bfd_get_arch_info (obfd)->the_default)
+       return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
+
+      return TRUE;
+    }
+
+  /* Determine what should happen if the input ARM architecture
+     does not match the output ARM architecture.  */
+  if (! bfd_arm_merge_machines (ibfd, obfd))
+    return FALSE;
+
+  /* Identical flags must be compatible.  */
+  if (in_flags == out_flags)
+    return TRUE;
+
+  /* Check to see if the input BFD actually contains any sections.  If
+     not, its flags may not have been initialised either, but it
+     cannot actually cause any incompatiblity.  Do not short-circuit
+     dynamic objects; their section list may be emptied by
+    elf_link_add_object_symbols.
+
+    Also check to see if there are no code sections in the input.
+    In this case there is no need to check for code specific flags.
+    XXX - do we need to worry about floating-point format compatability
+    in data sections ?  */
+  if (!(ibfd->flags & DYNAMIC))
+    {
+      bfd_boolean null_input_bfd = TRUE;
+      bfd_boolean only_data_sections = TRUE;
+
+      for (sec = ibfd->sections; sec != NULL; sec = sec->next)
+       {
+         /* Ignore synthetic glue sections.  */
+         if (strcmp (sec->name, ".glue_7")
+             && strcmp (sec->name, ".glue_7t"))
+           {
+             if ((bfd_get_section_flags (ibfd, sec)
+                  & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
+                 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
+               only_data_sections = FALSE;
+
+             null_input_bfd = FALSE;
+             break;
+           }
+       }
+
+      if (null_input_bfd || only_data_sections)
+       return TRUE;
+    }
+
+  /* Complain about various flag mismatches.  */
+  if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
+                                     EF_ARM_EABI_VERSION (out_flags)))
+    {
+      _bfd_error_handler
+       (_("error: Source object %B has EABI version %d, but target %B has EABI version %d"),
+        ibfd, obfd,
+        (in_flags & EF_ARM_EABIMASK) >> 24,
+        (out_flags & EF_ARM_EABIMASK) >> 24);
+      return FALSE;
+    }
+
+  /* Not sure what needs to be checked for EABI versions >= 1.  */
+  /* VxWorks libraries do not use these flags.  */
+  if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
+      && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
+      && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
+    {
+      if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
+       {
+         _bfd_error_handler
+           (_("error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"),
+            ibfd, obfd,
+            in_flags & EF_ARM_APCS_26 ? 26 : 32,
+            out_flags & EF_ARM_APCS_26 ? 26 : 32);
+         flags_compatible = FALSE;
+       }
+
+      if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
+       {
+         if (in_flags & EF_ARM_APCS_FLOAT)
+           _bfd_error_handler
+             (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
+              ibfd, obfd);
+         else
+           _bfd_error_handler
+             (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
+              ibfd, obfd);
+
+         flags_compatible = FALSE;
+       }
+
+      if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
+       {
+         if (in_flags & EF_ARM_VFP_FLOAT)
+           _bfd_error_handler
+             (_("error: %B uses VFP instructions, whereas %B does not"),
+              ibfd, obfd);
+         else
+           _bfd_error_handler
+             (_("error: %B uses FPA instructions, whereas %B does not"),
+              ibfd, obfd);
+
+         flags_compatible = FALSE;
+       }
+
+      if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
+       {
+         if (in_flags & EF_ARM_MAVERICK_FLOAT)
+           _bfd_error_handler
+             (_("error: %B uses Maverick instructions, whereas %B does not"),
+              ibfd, obfd);
+         else
+           _bfd_error_handler
+             (_("error: %B does not use Maverick instructions, whereas %B does"),
+              ibfd, obfd);
+
+         flags_compatible = FALSE;
+       }
+
+#ifdef EF_ARM_SOFT_FLOAT
+      if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
+       {
+         /* We can allow interworking between code that is VFP format
+            layout, and uses either soft float or integer regs for
+            passing floating point arguments and results.  We already
+            know that the APCS_FLOAT flags match; similarly for VFP
+            flags.  */
+         if ((in_flags & EF_ARM_APCS_FLOAT) != 0
+             || (in_flags & EF_ARM_VFP_FLOAT) == 0)
+           {
+             if (in_flags & EF_ARM_SOFT_FLOAT)
+               _bfd_error_handler
+                 (_("error: %B uses software FP, whereas %B uses hardware FP"),
+                  ibfd, obfd);
+             else
+               _bfd_error_handler
+                 (_("error: %B uses hardware FP, whereas %B uses software FP"),
+                  ibfd, obfd);
+
+             flags_compatible = FALSE;
+           }
+       }
+#endif
+
+      /* Interworking mismatch is only a warning.  */
+      if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
+       {
+         if (in_flags & EF_ARM_INTERWORK)
+           {
+             _bfd_error_handler
+               (_("Warning: %B supports interworking, whereas %B does not"),
+                ibfd, obfd);
+           }
+         else
+           {
+             _bfd_error_handler
+               (_("Warning: %B does not support interworking, whereas %B does"),
+                ibfd, obfd);
+           }
+       }
+    }
+
+  return flags_compatible;
+}
+
+
 /* Symbian OS Targets.  */
 
 #undef  TARGET_LITTLE_SYM

diff --git a/bfd/elf32-bfin.c b/bfd/elf32-bfin.c
index d4e3bbb..a767749 100644 (file)
--- a/bfd/elf32-bfin.c
+++ b/bfd/elf32-bfin.c
@@ -4166,19 +4166,17 @@ _bfinfdpic_size_got_plt (bfd *output_bfd,
     }
 
   if (elf_hash_table (info)->dynamic_sections_created)
+    bfinfdpic_pltrel_section (info)->size =
+      gpinfop->g.lzplt / LZPLT_NORMAL_SIZE * get_elf_backend_data (output_bfd)->s->sizeof_rel;
+  if (bfinfdpic_pltrel_section (info)->size == 0)
+    bfinfdpic_pltrel_section (info)->flags |= SEC_EXCLUDE;
+  else
     {
-      bfinfdpic_pltrel_section (info)->size =
-       gpinfop->g.lzplt / LZPLT_NORMAL_SIZE * get_elf_backend_data (output_bfd)->s->sizeof_rel;
-      if (bfinfdpic_pltrel_section (info)->size == 0)
-       bfinfdpic_pltrel_section (info)->flags |= SEC_EXCLUDE;
-      else
-       {
-         bfinfdpic_pltrel_section (info)->contents =
-           (bfd_byte *) bfd_zalloc (dynobj,
-                                    bfinfdpic_pltrel_section (info)->size);
-         if (bfinfdpic_pltrel_section (info)->contents == NULL)
-           return FALSE;
-       }
+      bfinfdpic_pltrel_section (info)->contents =
+       (bfd_byte *) bfd_zalloc (dynobj,
+                                bfinfdpic_pltrel_section (info)->size);
+      if (bfinfdpic_pltrel_section (info)->contents == NULL)
+       return FALSE;
     }
 
   /* Add 4 bytes for every block of at most 65535 lazy PLT entries,
@@ -4215,18 +4213,15 @@ _bfinfdpic_size_got_plt (bfd *output_bfd,
   /* Allocate the PLT section contents only after
      _bfinfdpic_assign_plt_entries has a chance to add the size of the
      non-lazy PLT entries.  */
-  if (elf_hash_table (info)->dynamic_sections_created)
+  if (bfinfdpic_plt_section (info)->size == 0)
+    bfinfdpic_plt_section (info)->flags |= SEC_EXCLUDE;
+  else
     {
-      if (bfinfdpic_plt_section (info)->size == 0)
-       bfinfdpic_plt_section (info)->flags |= SEC_EXCLUDE;
-      else
-       {
-         bfinfdpic_plt_section (info)->contents =
-           (bfd_byte *) bfd_zalloc (dynobj,
-                                    bfinfdpic_plt_section (info)->size);
-         if (bfinfdpic_plt_section (info)->contents == NULL)
-           return FALSE;
-       }
+      bfinfdpic_plt_section (info)->contents =
+       (bfd_byte *) bfd_zalloc (dynobj,
+                                bfinfdpic_plt_section (info)->size);
+      if (bfinfdpic_plt_section (info)->contents == NULL)
+       return FALSE;
     }
 
   return TRUE;
@@ -4302,12 +4297,11 @@ elf32_bfinfdpic_size_dynamic_sections (bfd *output_bfd,
          return FALSE;
     }
 
-
-  s = bfd_get_section_by_name (dynobj, ".rela.bss");
+  s = bfd_get_section_by_name (dynobj, ".dynbss");
   if (s && s->size == 0)
     s->flags |= SEC_EXCLUDE;
 
-  s = bfd_get_section_by_name (dynobj, ".rel.plt");
+  s = bfd_get_section_by_name (dynobj, ".rela.bss");
   if (s && s->size == 0)
     s->flags |= SEC_EXCLUDE;
 

diff --git a/bfd/elf32-cr16.c b/bfd/elf32-cr16.c
index 17be1ff..f82d1e9 100644 (file)
--- a/bfd/elf32-cr16.c
+++ b/bfd/elf32-cr16.c
@@ -1431,9 +1431,6 @@ elf32_cr16_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
   struct elf_link_hash_entry **sym_hashes;
   Elf_Internal_Rela *rel, *relend;
 
-  if (info->relocatable)
-    return TRUE;
-
   symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
   sym_hashes = elf_sym_hashes (input_bfd);
 

diff --git a/bfd/elf32-m68k.c b/bfd/elf32-m68k.c
index 1237935..17a5e0b 100644 (file)
--- a/bfd/elf32-m68k.c
+++ b/bfd/elf32-m68k.c
@@ -1080,7 +1080,68 @@ elf32_m68k_object_p (bfd *abfd)
   return TRUE;
 }
 
+/* Somewhat reverse of elf32_m68k_object_p, this sets the e_flag
+   field based on the machine number.  */
+
+static void
+elf_m68k_final_write_processing (bfd *abfd,
+                                bfd_boolean linker ATTRIBUTE_UNUSED)
+{
+  int mach = bfd_get_mach (abfd);
+  unsigned long e_flags = elf_elfheader (abfd)->e_flags;
+
+  if (!e_flags)
+    {
+      unsigned int arch_mask;
+
+      arch_mask = bfd_m68k_mach_to_features (mach);
+
+      if (arch_mask & m68000)
+       e_flags = EF_M68K_M68000;
+      else if (arch_mask & cpu32)
+       e_flags = EF_M68K_CPU32;
+      else if (arch_mask & fido_a)
+       e_flags = EF_M68K_FIDO;
+      else
+       {
+         switch (arch_mask
+                 & (mcfisa_a | mcfisa_aa | mcfisa_b | mcfisa_c | mcfhwdiv | mcfusp))
+           {
+           case mcfisa_a:
+             e_flags |= EF_M68K_CF_ISA_A_NODIV;
+             break;
+           case mcfisa_a | mcfhwdiv:
+             e_flags |= EF_M68K_CF_ISA_A;
+             break;
+           case mcfisa_a | mcfisa_aa | mcfhwdiv | mcfusp:
+             e_flags |= EF_M68K_CF_ISA_A_PLUS;
+             break;
+           case mcfisa_a | mcfisa_b | mcfhwdiv:
+             e_flags |= EF_M68K_CF_ISA_B_NOUSP;
+             break;
+           case mcfisa_a | mcfisa_b | mcfhwdiv | mcfusp:
+             e_flags |= EF_M68K_CF_ISA_B;
+             break;
+           case mcfisa_a | mcfisa_c | mcfhwdiv | mcfusp:
+             e_flags |= EF_M68K_CF_ISA_C;
+             break;
+           case mcfisa_a | mcfisa_c | mcfusp:
+             e_flags |= EF_M68K_CF_ISA_C_NODIV;
+             break;
+           }
+         if (arch_mask & mcfmac)
+           e_flags |= EF_M68K_CF_MAC;
+         else if (arch_mask & mcfemac)
+           e_flags |= EF_M68K_CF_EMAC;
+         if (arch_mask & cfloat)
+           e_flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
+       }
+      elf_elfheader (abfd)->e_flags = e_flags;
+    }
+}
+
 /* Keep m68k-specific flags in the ELF header.  */
+
 static bfd_boolean
 elf32_m68k_set_private_flags (abfd, flags)
      bfd *abfd;
@@ -4764,6 +4825,7 @@ elf_m68k_plt_sym_val (bfd_vma i, const asection *plt,
                                        elf_m68k_adjust_dynamic_symbol
 #define elf_backend_size_dynamic_sections \
                                        elf_m68k_size_dynamic_sections
+#define elf_backend_final_write_processing     elf_m68k_final_write_processing
 #define elf_backend_init_index_section _bfd_elf_init_1_index_section
 #define elf_backend_relocate_section   elf_m68k_relocate_section
 #define elf_backend_finish_dynamic_symbol \

diff --git a/bfd/elf32-ppc.c b/bfd/elf32-ppc.c
index ae031df..95058a2 100644 (file)
--- a/bfd/elf32-ppc.c
+++ b/bfd/elf32-ppc.c
@@ -61,6 +61,7 @@ static bfd_reloc_status_type ppc_elf_unhandled_reloc
 /* For new-style .glink and .plt.  */
 #define GLINK_PLTRESOLVE 16*4
 #define GLINK_ENTRY_SIZE 4*4
+#define TLS_GET_ADDR_GLINK_SIZE 12*4
 
 /* VxWorks uses its own plt layout, filled in by the static linker.  */
 
@@ -135,17 +136,24 @@ static const bfd_vma ppc_elf_vxworks_pic_plt0_entry
 #define ADDIS_12_12    0x3d8c0000
 #define ADDI_11_11     0x396b0000
 #define ADD_0_11_11    0x7c0b5a14
+#define ADD_3_12_2     0x7c6c1214
 #define ADD_11_0_11    0x7d605a14
 #define B              0x48000000
 #define BCL_20_31      0x429f0005
 #define BCTR           0x4e800420
+#define BEQLR          0x4d820020
+#define CMPWI_11_0     0x2c0b0000
 #define LIS_11         0x3d600000
 #define LIS_12         0x3d800000
 #define LWZU_0_12      0x840c0000
 #define LWZ_0_12       0x800c0000
+#define LWZ_11_3       0x81630000
 #define LWZ_11_11      0x816b0000
 #define LWZ_11_30      0x817e0000
+#define LWZ_12_3       0x81830000
 #define LWZ_12_12      0x818c0000
+#define MR_0_3         0x7c601b78
+#define MR_3_0         0x7c030378
 #define MFLR_0         0x7c0802a6
 #define MFLR_12                0x7d8802a6
 #define MTCTR_0                0x7c0903a6
@@ -1300,7 +1308,7 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
         16,                    /* bitsize */
         FALSE,                 /* pc_relative */
         0,                     /* bitpos */
-        complain_overflow_bitfield, /* complain_on_overflow */
+        complain_overflow_signed, /* complain_on_overflow */
         bfd_elf_generic_reloc, /* special_function */
         "R_PPC_EMB_SDAI16",    /* name */
         FALSE,                 /* partial_inplace */
@@ -1317,7 +1325,7 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
         16,                    /* bitsize */
         FALSE,                 /* pc_relative */
         0,                     /* bitpos */
-        complain_overflow_bitfield, /* complain_on_overflow */
+        complain_overflow_signed, /* complain_on_overflow */
         bfd_elf_generic_reloc, /* special_function */
         "R_PPC_EMB_SDA2I16",   /* name */
         FALSE,                 /* partial_inplace */
@@ -2754,6 +2762,9 @@ struct ppc_elf_link_hash_table
   /* Set if we should emit symbols for stubs.  */
   unsigned int emit_stub_syms:1;
 
+  /* Set if __tls_get_addr optimization should not be done.  */
+  unsigned int no_tls_get_addr_opt:1;
+
   /* True if the target system is VxWorks.  */
   unsigned int is_vxworks:1;
 
@@ -3129,9 +3140,10 @@ ppc_elf_add_symbol_hook (bfd *abfd,
 }
 \f
 static bfd_boolean
-create_sdata_sym (struct ppc_elf_link_hash_table *htab,
-                 elf_linker_section_t *lsect)
+create_sdata_sym (struct bfd_link_info *info, elf_linker_section_t *lsect)
 {
+  struct ppc_elf_link_hash_table *htab = ppc_elf_hash_table (info);
+
   lsect->sym = elf_link_hash_lookup (&htab->elf, lsect->sym_name,
                                     TRUE, FALSE, TRUE);
   if (lsect->sym == NULL)
@@ -3139,6 +3151,7 @@ create_sdata_sym (struct ppc_elf_link_hash_table *htab,
   if (lsect->sym->root.type == bfd_link_hash_new)
     lsect->sym->non_elf = 0;
   lsect->sym->ref_regular = 1;
+  _bfd_elf_link_hash_hide_symbol (info, lsect->sym, TRUE);
   return TRUE;
 }
 
@@ -3168,7 +3181,7 @@ ppc_elf_create_linker_section (bfd *abfd,
     return FALSE;
   lsect->section = s;
 
-  return create_sdata_sym (htab, lsect);
+  return create_sdata_sym (info, lsect);
 }
 
 /* Find a linker generated pointer with a given addend and type.  */
@@ -3633,13 +3646,8 @@ ppc_elf_check_relocs (bfd *abfd,
          break;
 
        case R_PPC_SDAREL16:
-         if (info->shared)
-           {
-             bad_shared_reloc (abfd, r_type);
-             return FALSE;
-           }
          if (htab->sdata[0].sym == NULL
-             && !create_sdata_sym (htab, &htab->sdata[0]))
+             && !create_sdata_sym (info, &htab->sdata[0]))
            return FALSE;
          if (h != NULL)
            {
@@ -3655,7 +3663,7 @@ ppc_elf_check_relocs (bfd *abfd,
              return FALSE;
            }
          if (htab->sdata[1].sym == NULL
-             && !create_sdata_sym (htab, &htab->sdata[1]))
+             && !create_sdata_sym (info, &htab->sdata[1]))
            return FALSE;
          if (h != NULL)
            {
@@ -3672,10 +3680,10 @@ ppc_elf_check_relocs (bfd *abfd,
              return FALSE;
            }
          if (htab->sdata[0].sym == NULL
-             && !create_sdata_sym (htab, &htab->sdata[0]))
+             && !create_sdata_sym (info, &htab->sdata[0]))
            return FALSE;
          if (htab->sdata[1].sym == NULL
-             && !create_sdata_sym (htab, &htab->sdata[1]))
+             && !create_sdata_sym (info, &htab->sdata[1]))
            return FALSE;
          if (h != NULL)
            {
@@ -4280,6 +4288,8 @@ ppc_elf_select_plt_layout (bfd *output_bfd ATTRIBUTE_UNUSED,
 
   htab = ppc_elf_hash_table (info);
 
+  htab->emit_stub_syms = emit_stub_syms;
+
   if (htab->plt_type == PLT_UNSET)
     {
       if (plt_style == PLT_OLD)
@@ -4313,8 +4323,6 @@ ppc_elf_select_plt_layout (bfd *output_bfd ATTRIBUTE_UNUSED,
   if (htab->plt_type == PLT_OLD && plt_style == PLT_NEW)
     info->callbacks->info (_("Using bss-plt due to %B"), htab->old_bfd);
 
-  htab->emit_stub_syms = emit_stub_syms;
-
   BFD_ASSERT (htab->plt_type != PLT_VXWORKS);
 
   if (htab->plt_type == PLT_NEW)
@@ -4542,11 +4550,62 @@ ppc_elf_gc_sweep_hook (bfd *abfd,
    generic ELF tls_setup function.  */
 
 asection *
-ppc_elf_tls_setup (bfd *obfd, struct bfd_link_info *info)
+ppc_elf_tls_setup (bfd *obfd,
+                  struct bfd_link_info *info,
+                  int no_tls_get_addr_opt)
 {
   struct ppc_elf_link_hash_table *htab;
 
   htab = ppc_elf_hash_table (info);
+  htab->tls_get_addr = elf_link_hash_lookup (&htab->elf, "__tls_get_addr",
+                                            FALSE, FALSE, TRUE);
+  if (!no_tls_get_addr_opt)
+    {
+      struct elf_link_hash_entry *opt, *tga;
+      opt = elf_link_hash_lookup (&htab->elf, "__tls_get_addr_opt",
+                                 FALSE, FALSE, TRUE);
+      if (opt != NULL
+         && (opt->root.type == bfd_link_hash_defined
+             || opt->root.type == bfd_link_hash_defweak))
+       {
+         /* If glibc supports an optimized __tls_get_addr call stub,
+            signalled by the presence of __tls_get_addr_opt, and we'll
+            be calling __tls_get_addr via a plt call stub, then
+            make __tls_get_addr point to __tls_get_addr_opt.  */
+         tga = htab->tls_get_addr;
+         if (htab->elf.dynamic_sections_created
+             && tga != NULL
+             && (tga->type == STT_FUNC
+                 || tga->needs_plt)
+             && !(SYMBOL_CALLS_LOCAL (info, tga)
+                  || (ELF_ST_VISIBILITY (tga->other) != STV_DEFAULT
+                      && tga->root.type == bfd_link_hash_undefweak)))
+           {
+             struct plt_entry *ent;
+             ent = find_plt_ent (&tga->plt.plist, NULL, 0);
+             if (ent != NULL
+                 && ent->plt.refcount > 0)
+               {
+                 tga->root.type = bfd_link_hash_indirect;
+                 tga->root.u.i.link = &opt->root;
+                 ppc_elf_copy_indirect_symbol (info, opt, tga);
+                 if (opt->dynindx != -1)
+                   {
+                     /* Use __tls_get_addr_opt in dynamic relocations.  */
+                     opt->dynindx = -1;
+                     _bfd_elf_strtab_delref (elf_hash_table (info)->dynstr,
+                                             opt->dynstr_index);
+                     if (!bfd_elf_link_record_dynamic_symbol (info, opt))
+                       return FALSE;
+                   }
+                 htab->tls_get_addr = opt;
+               }
+           }
+       }
+      else
+       no_tls_get_addr_opt = TRUE;
+    }
+  htab->no_tls_get_addr_opt = no_tls_get_addr_opt;
   if (htab->plt_type == PLT_NEW
       && htab->plt != NULL
       && htab->plt->output_section != NULL)
@@ -4555,8 +4614,6 @@ ppc_elf_tls_setup (bfd *obfd, struct bfd_link_info *info)
       elf_section_flags (htab->plt->output_section) = SHF_ALLOC + SHF_WRITE;
     }
 
-  htab->tls_get_addr = elf_link_hash_lookup (&htab->elf, "__tls_get_addr",
-                                            FALSE, FALSE, TRUE);
   return _bfd_elf_tls_setup (obfd, info);
 }
 
@@ -5147,6 +5204,9 @@ allocate_dynrelocs (struct elf_link_hash_entry *h, void *inf)
                      {
                        glink_offset = s->size;
                        s->size += GLINK_ENTRY_SIZE;
+                       if (h == htab->tls_get_addr
+                           && !htab->no_tls_get_addr_opt)
+                         s->size += TLS_GET_ADDR_GLINK_SIZE - GLINK_ENTRY_SIZE;
                      }
                    if (!doneone
                        && !info->shared
@@ -5660,6 +5720,18 @@ ppc_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
 
       htab->elf.hgot->root.u.def.value = g_o_t;
     }
+  if (info->shared)
+    {
+      struct elf_link_hash_entry *sda = htab->sdata[0].sym;
+      if (sda != NULL
+         && !(sda->root.type == bfd_link_hash_defined
+              || sda->root.type == bfd_link_hash_defweak))
+       {
+         sda->root.type = bfd_link_hash_defined;
+         sda->root.u.def.section = htab->elf.hgot->root.u.def.section;
+         sda->root.u.def.value = htab->elf.hgot->root.u.def.value;
+       }
+    }
 
   if (htab->glink != NULL
       && htab->glink->size != 0
@@ -5811,6 +5883,11 @@ ppc_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
        {
          if (!add_dynamic_entry (DT_PPC_GOT, 0))
            return FALSE;
+         if (!htab->no_tls_get_addr_opt
+             && htab->tls_get_addr != NULL
+             && htab->tls_get_addr->plt.plist != NULL
+             && !add_dynamic_entry (DT_PPC_TLSOPT, 0))
+           return FALSE;
        }
 
       if (relocs)
@@ -6446,9 +6523,10 @@ elf_finish_pointer_linker_section (bfd *input_bfd,
       linker_section_ptr->offset += 1;
     }
 
-  relocation = (lsect->section->output_offset
+  relocation = (lsect->section->output_section->vma
+               + lsect->section->output_offset
                + linker_section_ptr->offset - 1
-               - 0x8000);
+               - SYM_VAL (lsect->sym));
 
 #ifdef DEBUG
   fprintf (stderr,
@@ -6456,9 +6534,7 @@ elf_finish_pointer_linker_section (bfd *input_bfd,
           lsect->name, (long) relocation, (long) relocation);
 #endif
 
-  /* Subtract out the addend, because it will get added back in by the normal
-     processing.  */
-  return relocation - linker_section_ptr->addend;
+  return relocation;
 }
 
 #define PPC_LO(v) ((v) & 0xffff)
@@ -6466,18 +6542,16 @@ elf_finish_pointer_linker_section (bfd *input_bfd,
 #define PPC_HA(v) PPC_HI ((v) + 0x8000)
 
 static void
-write_glink_stub (struct plt_entry *ent, asection *plt_sec,
+write_glink_stub (struct plt_entry *ent, asection *plt_sec, unsigned char *p,
                  struct bfd_link_info *info)
 {
   struct ppc_elf_link_hash_table *htab = ppc_elf_hash_table (info);
   bfd *output_bfd = info->output_bfd;
   bfd_vma plt;
-  unsigned char *p;
 
   plt = ((ent->plt.offset & ~1)
         + plt_sec->output_section->vma
         + plt_sec->output_offset);
-  p = (unsigned char *) htab->glink->contents + ent->glink_offset;
 
   if (info->shared)
     {
@@ -6528,6 +6602,17 @@ write_glink_stub (struct plt_entry *ent, asection *plt_sec,
     }
 }
 
+/* Return true if symbol is defined statically.  */
+
+static bfd_boolean
+is_static_defined (struct elf_link_hash_entry *h)
+{
+  return ((h->root.type == bfd_link_hash_defined
+          || h->root.type == bfd_link_hash_defweak)
+         && h->root.u.def.section != NULL
+         && h->root.u.def.section->output_section != NULL);
+}
+
 /* The RELOCATE_SECTION function is called by the ELF backend linker
    to handle the relocations for a section.
 
@@ -7026,7 +7111,9 @@ ppc_elf_relocate_section (bfd *output_bfd,
                }
              if (h == NULL && (ent->glink_offset & 1) == 0)
                {
-                 write_glink_stub (ent, htab->iplt, info);
+                 unsigned char *p = ((unsigned char *) htab->glink->contents
+                                     + ent->glink_offset);
+                 write_glink_stub (ent, htab->iplt, p, info);
                  ent->glink_offset |= 1;
                }
 
@@ -7629,17 +7716,29 @@ ppc_elf_relocate_section (bfd *output_bfd,
          /* Indirect .sdata relocation.  */
        case R_PPC_EMB_SDAI16:
          BFD_ASSERT (htab->sdata[0].section != NULL);
+         if (!is_static_defined (htab->sdata[0].sym))
+           {
+             unresolved_reloc = TRUE;
+             break;
+           }
          relocation
            = elf_finish_pointer_linker_section (input_bfd, &htab->sdata[0],
                                                 h, relocation, rel);
+         addend = 0;
          break;
 
          /* Indirect .sdata2 relocation.  */
        case R_PPC_EMB_SDA2I16:
          BFD_ASSERT (htab->sdata[1].section != NULL);
+         if (!is_static_defined (htab->sdata[1].sym))
+           {
+             unresolved_reloc = TRUE;
+             break;
+           }
          relocation
            = elf_finish_pointer_linker_section (input_bfd, &htab->sdata[1],
                                                 h, relocation, rel);
+         addend = 0;
          break;
 
          /* Handle the TOC16 reloc.  We want to use the offset within the .got
@@ -7692,12 +7791,16 @@ ppc_elf_relocate_section (bfd *output_bfd,
        case R_PPC_SDAREL16:
          {
            const char *name;
+           struct elf_link_hash_entry *sda = htab->sdata[0].sym;
 
-           if (sec == NULL || sec->output_section == NULL)
+           if (sec == NULL
+               || sec->output_section == NULL
+               || !is_static_defined (sda))
              {
                unresolved_reloc = TRUE;
                break;
              }
+           addend -= SYM_VAL (sda);
 
            name = bfd_get_section_name (abfd, sec->output_section);
            if (! ((CONST_STRNEQ (name, ".sdata")
@@ -7713,7 +7816,6 @@ ppc_elf_relocate_section (bfd *output_bfd,
                   howto->name,
                   name);
              }
-           addend -= SYM_VAL (htab->sdata[0].sym);
          }
          break;
 
@@ -7721,12 +7823,16 @@ ppc_elf_relocate_section (bfd *output_bfd,
        case R_PPC_EMB_SDA2REL:
          {
            const char *name;
+           struct elf_link_hash_entry *sda = htab->sdata[1].sym;
 
-           if (sec == NULL || sec->output_section == NULL)
+           if (sec == NULL
+               || sec->output_section == NULL
+               || !is_static_defined (sda))
              {
                unresolved_reloc = TRUE;
                break;
              }
+           addend -= SYM_VAL (sda);
 
            name = bfd_get_section_name (abfd, sec->output_section);
            if (! (CONST_STRNEQ (name, ".sdata2")
@@ -7739,12 +7845,7 @@ ppc_elf_relocate_section (bfd *output_bfd,
                   sym_name,
                   howto->name,
                   name);
-
-               bfd_set_error (bfd_error_bad_value);
-               ret = FALSE;
-               continue;
              }
-           addend -= SYM_VAL (htab->sdata[1].sym);
          }
          break;
 
@@ -7754,6 +7855,7 @@ ppc_elf_relocate_section (bfd *output_bfd,
          {
            const char *name;
            int reg;
+           struct elf_link_hash_entry *sda = NULL;
 
            if (sec == NULL || sec->output_section == NULL)
              {
@@ -7768,13 +7870,13 @@ ppc_elf_relocate_section (bfd *output_bfd,
                     && (name[5] == 0 || name[5] == '.'))))
              {
                reg = 13;
-               addend -= SYM_VAL (htab->sdata[0].sym);
+               sda = htab->sdata[0].sym;
              }
            else if (CONST_STRNEQ (name, ".sdata2")
                     || CONST_STRNEQ (name, ".sbss2"))
              {
                reg = 2;
-               addend -= SYM_VAL (htab->sdata[1].sym);
+               sda = htab->sdata[1].sym;
              }
            else if (strcmp (name, ".PPC.EMB.sdata0") == 0
                     || strcmp (name, ".PPC.EMB.sbss0") == 0)
@@ -7796,6 +7898,16 @@ ppc_elf_relocate_section (bfd *output_bfd,
                continue;
              }
 
+           if (sda != NULL)
+             {
+               if (!is_static_defined (sda))
+                 {
+                   unresolved_reloc = TRUE;
+                   break;
+                 }
+               addend -= SYM_VAL (sda);
+             }
+
            if (r_type == R_PPC_EMB_SDA21)
              {                 /* fill in register field */
                insn = bfd_get_32 (output_bfd, contents + rel->r_offset);
@@ -8230,12 +8342,35 @@ ppc_elf_finish_dynamic_symbol (bfd *output_bfd,
            || !htab->elf.dynamic_sections_created
            || h->dynindx == -1)
          {
+           unsigned char *p;
            asection *splt = htab->plt;
            if (!htab->elf.dynamic_sections_created
                || h->dynindx == -1)
              splt = htab->iplt;
 
-           write_glink_stub (ent, splt, info);
+           p = (unsigned char *) htab->glink->contents + ent->glink_offset;
+
+           if (h == htab->tls_get_addr && !htab->no_tls_get_addr_opt)
+             {
+               bfd_put_32 (output_bfd, LWZ_11_3, p);
+               p += 4;
+               bfd_put_32 (output_bfd, LWZ_12_3 + 4, p);
+               p += 4;
+               bfd_put_32 (output_bfd, MR_0_3, p);
+               p += 4;
+               bfd_put_32 (output_bfd, CMPWI_11_0, p);
+               p += 4;
+               bfd_put_32 (output_bfd, ADD_3_12_2, p);
+               p += 4;
+               bfd_put_32 (output_bfd, BEQLR, p);
+               p += 4;
+               bfd_put_32 (output_bfd, MR_3_0, p);
+               p += 4;
+               bfd_put_32 (output_bfd, NOP, p);
+               p += 4;
+             }
+
+           write_glink_stub (ent, splt, p, info);
 
            if (!info->shared)
              /* We only need one non-PIC glink stub.  */

diff --git a/bfd/elf32-ppc.h b/bfd/elf32-ppc.h
index ef1f0ac..4becb30 100644 (file)
--- a/bfd/elf32-ppc.h
+++ b/bfd/elf32-ppc.h
@@ -28,6 +28,6 @@ enum ppc_elf_plt_type
 
 int ppc_elf_select_plt_layout (bfd *, struct bfd_link_info *,
                               enum ppc_elf_plt_type, int);
-asection *ppc_elf_tls_setup (bfd *, struct bfd_link_info *);
+asection *ppc_elf_tls_setup (bfd *, struct bfd_link_info *, int);
 bfd_boolean ppc_elf_tls_optimize (bfd *, struct bfd_link_info *);
 void ppc_elf_set_sdata_syms (bfd *, struct bfd_link_info *);

diff --git a/bfd/elf32-rx.c b/bfd/elf32-rx.c
new file mode 100644 (file)
index 0000000..dadd407
--- /dev/null
+++ b/bfd/elf32-rx.c
@@ -0,0 +1,3402 @@
+/* Renesas RX specific support for 32-bit ELF.
+   Copyright (C) 2008, 2009
+   Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "sysdep.h"
+#include "bfd.h"
+#include "libbfd.h"
+#include "elf-bfd.h"
+#include "elf/rx.h"
+#include "libiberty.h"
+
+#define RX_OPCODE_BIG_ENDIAN 0
+
+#ifdef DEBUG
+char * rx_get_reloc (long);
+void dump_symtab (bfd *, void *, void *);
+#endif
+
+#define RXREL(n,sz,bit,shift,complain,pcrel)                                \
+  HOWTO (R_RX_##n, shift, sz, bit, pcrel, 0, complain_overflow_ ## complain, \
+        bfd_elf_generic_reloc, "R_RX_" #n, FALSE, 0, ~0, FALSE)
+
+/* Note that the relocations around 0x7f are internal to this file;
+   feel free to move them as needed to avoid conflicts with published
+   relocation numbers.  */
+
+static reloc_howto_type rx_elf_howto_table [] =
+{
+  RXREL (NONE,         0,  0, 0, dont,     FALSE),
+  RXREL (DIR32,        2, 32, 0, signed,   FALSE),
+  RXREL (DIR24S,       2, 24, 0, signed,   FALSE),
+  RXREL (DIR16,        1, 16, 0, dont,     FALSE),
+  RXREL (DIR16U,       1, 16, 0, unsigned, FALSE),
+  RXREL (DIR16S,       1, 16, 0, signed,   FALSE),
+  RXREL (DIR8,         0,  8, 0, dont,     FALSE),
+  RXREL (DIR8U,        0,  8, 0, unsigned, FALSE),
+  RXREL (DIR8S,        0,  8, 0, signed,   FALSE),
+  RXREL (DIR24S_PCREL, 2, 24, 0, signed,   TRUE),
+  RXREL (DIR16S_PCREL, 1, 16, 0, signed,   TRUE),
+  RXREL (DIR8S_PCREL,  0,  8, 0, signed,   TRUE),
+  RXREL (DIR16UL,      1, 16, 2, unsigned, FALSE),
+  RXREL (DIR16UW,      1, 16, 1, unsigned, FALSE),
+  RXREL (DIR8UL,       0,  8, 2, unsigned, FALSE),
+  RXREL (DIR8UW,       0,  8, 1, unsigned, FALSE),
+  RXREL (DIR32_REV,    1, 16, 0, dont,     FALSE),
+  RXREL (DIR16_REV,    1, 16, 0, dont,     FALSE),
+  RXREL (DIR3U_PCREL,  0,  3, 0, dont,     TRUE),
+
+  EMPTY_HOWTO (0x13),
+  EMPTY_HOWTO (0x14),
+  EMPTY_HOWTO (0x15),
+  EMPTY_HOWTO (0x16),
+  EMPTY_HOWTO (0x17),
+  EMPTY_HOWTO (0x18),
+  EMPTY_HOWTO (0x19),
+  EMPTY_HOWTO (0x1a),
+  EMPTY_HOWTO (0x1b),
+  EMPTY_HOWTO (0x1c),
+  EMPTY_HOWTO (0x1d),
+  EMPTY_HOWTO (0x1e),
+  EMPTY_HOWTO (0x1f),
+
+  RXREL (RH_3_PCREL, 0,  3, 0, signed,   TRUE),
+  RXREL (RH_16_OP,   1, 16, 0, signed,   FALSE),
+  RXREL (RH_24_OP,   2, 24, 0, signed,   FALSE),
+  RXREL (RH_32_OP,   2, 32, 0, signed,   FALSE),
+  RXREL (RH_24_UNS,  2, 24, 0, unsigned, FALSE),
+  RXREL (RH_8_NEG,   0,  8, 0, signed,   FALSE),
+  RXREL (RH_16_NEG,  1, 16, 0, signed,   FALSE),
+  RXREL (RH_24_NEG,  2, 24, 0, signed,   FALSE),
+  RXREL (RH_32_NEG,  2, 32, 0, signed,   FALSE),
+  RXREL (RH_DIFF,    2, 32, 0, signed,   FALSE),
+  RXREL (RH_GPRELB,  1, 16, 0, unsigned, FALSE),
+  RXREL (RH_GPRELW,  1, 16, 0, unsigned, FALSE),
+  RXREL (RH_GPRELL,  1, 16, 0, unsigned, FALSE),
+  RXREL (RH_RELAX,   0,  0, 0, dont,     FALSE),
+
+  EMPTY_HOWTO (0x2e),
+  EMPTY_HOWTO (0x2f),
+  EMPTY_HOWTO (0x30),
+  EMPTY_HOWTO (0x31),
+  EMPTY_HOWTO (0x32),
+  EMPTY_HOWTO (0x33),
+  EMPTY_HOWTO (0x34),
+  EMPTY_HOWTO (0x35),
+  EMPTY_HOWTO (0x36),
+  EMPTY_HOWTO (0x37),
+  EMPTY_HOWTO (0x38),
+  EMPTY_HOWTO (0x39),
+  EMPTY_HOWTO (0x3a),
+  EMPTY_HOWTO (0x3b),
+  EMPTY_HOWTO (0x3c),
+  EMPTY_HOWTO (0x3d),
+  EMPTY_HOWTO (0x3e),
+  EMPTY_HOWTO (0x3f),
+  EMPTY_HOWTO (0x40),
+
+  RXREL (ABS32,        2, 32, 0, dont,     FALSE),
+  RXREL (ABS24S,       2, 24, 0, signed,   FALSE),
+  RXREL (ABS16,        1, 16, 0, dont,     FALSE),
+  RXREL (ABS16U,       1, 16, 0, unsigned, FALSE),
+  RXREL (ABS16S,       1, 16, 0, signed,   FALSE),
+  RXREL (ABS8,         0,  8, 0, dont,     FALSE),
+  RXREL (ABS8U,        0,  8, 0, unsigned, FALSE),
+  RXREL (ABS8S,        0,  8, 0, signed,   FALSE),
+  RXREL (ABS24S_PCREL, 2, 24, 0, signed,   TRUE),
+  RXREL (ABS16S_PCREL, 1, 16, 0, signed,   TRUE),
+  RXREL (ABS8S_PCREL,  0,  8, 0, signed,   TRUE),
+  RXREL (ABS16UL,      1, 16, 0, unsigned, FALSE),
+  RXREL (ABS16UW,      1, 16, 0, unsigned, FALSE),
+  RXREL (ABS8UL,       0,  8, 0, unsigned, FALSE),
+  RXREL (ABS8UW,       0,  8, 0, unsigned, FALSE),
+  RXREL (ABS32_REV,    2, 32, 0, dont,     FALSE),
+  RXREL (ABS16_REV,    1, 16, 0, dont,     FALSE),
+
+#define STACK_REL_P(x) ((x) <= R_RX_ABS16_REV && (x) >= R_RX_ABS32)
+
+  EMPTY_HOWTO (0x52),
+  EMPTY_HOWTO (0x53),
+  EMPTY_HOWTO (0x54),
+  EMPTY_HOWTO (0x55),
+  EMPTY_HOWTO (0x56),
+  EMPTY_HOWTO (0x57),
+  EMPTY_HOWTO (0x58),
+  EMPTY_HOWTO (0x59),
+  EMPTY_HOWTO (0x5a),
+  EMPTY_HOWTO (0x5b),
+  EMPTY_HOWTO (0x5c),
+  EMPTY_HOWTO (0x5d),
+  EMPTY_HOWTO (0x5e),
+  EMPTY_HOWTO (0x5f),
+  EMPTY_HOWTO (0x60),
+  EMPTY_HOWTO (0x61),
+  EMPTY_HOWTO (0x62),
+  EMPTY_HOWTO (0x63),
+  EMPTY_HOWTO (0x64),
+  EMPTY_HOWTO (0x65),
+  EMPTY_HOWTO (0x66),
+  EMPTY_HOWTO (0x67),
+  EMPTY_HOWTO (0x68),
+  EMPTY_HOWTO (0x69),
+  EMPTY_HOWTO (0x6a),
+  EMPTY_HOWTO (0x6b),
+  EMPTY_HOWTO (0x6c),
+  EMPTY_HOWTO (0x6d),
+  EMPTY_HOWTO (0x6e),
+  EMPTY_HOWTO (0x6f),
+  EMPTY_HOWTO (0x70),
+  EMPTY_HOWTO (0x71),
+  EMPTY_HOWTO (0x72),
+  EMPTY_HOWTO (0x73),
+  EMPTY_HOWTO (0x74),
+  EMPTY_HOWTO (0x75),
+  EMPTY_HOWTO (0x76),
+  EMPTY_HOWTO (0x77),
+
+  /* These are internal.  */
+  /* A 5-bit unsigned displacement to a B/W/L address, at bit position 8/12.  */
+  /* ---- ----   4--- 3210.  */
+#define R_RX_RH_ABS5p8B 0x78
+  RXREL (RH_ABS5p8B,   0,  0, 0, dont,     FALSE),
+#define R_RX_RH_ABS5p8W 0x79
+  RXREL (RH_ABS5p8W,   0,  0, 0, dont,     FALSE),
+#define R_RX_RH_ABS5p8L 0x7a
+  RXREL (RH_ABS5p8L,   0,  0, 0, dont,     FALSE),
+  /* A 5-bit unsigned displacement to a B/W/L address, at bit position 5/12.  */
+  /* ---- -432   1--- 0---.  */
+#define R_RX_RH_ABS5p5B 0x7b
+  RXREL (RH_ABS5p5B,   0,  0, 0, dont,     FALSE),
+#define R_RX_RH_ABS5p5W 0x7c
+  RXREL (RH_ABS5p5W,   0,  0, 0, dont,     FALSE),
+#define R_RX_RH_ABS5p5L 0x7d
+  RXREL (RH_ABS5p5L,   0,  0, 0, dont,     FALSE),
+  /* A 4-bit unsigned immediate at bit position 8.  */
+#define R_RX_RH_UIMM4p8 0x7e
+  RXREL (RH_UIMM4p8,   0,  0, 0, dont,     FALSE),
+  /* A 4-bit negative unsigned immediate at bit position 8.  */
+#define R_RX_RH_UNEG4p8 0x7f
+  RXREL (RH_UNEG4p8,   0,  0, 0, dont,     FALSE),
+  /* End of internal relocs.  */
+
+  RXREL (SYM,       2, 32, 0, dont, FALSE),
+  RXREL (OPneg,     2, 32, 0, dont, FALSE),
+  RXREL (OPadd,     2, 32, 0, dont, FALSE),
+  RXREL (OPsub,     2, 32, 0, dont, FALSE),
+  RXREL (OPmul,     2, 32, 0, dont, FALSE),
+  RXREL (OPdiv,     2, 32, 0, dont, FALSE),
+  RXREL (OPshla,    2, 32, 0, dont, FALSE),
+  RXREL (OPshra,    2, 32, 0, dont, FALSE),
+  RXREL (OPsctsize, 2, 32, 0, dont, FALSE),
+  RXREL (OPscttop,  2, 32, 0, dont, FALSE),
+  RXREL (OPand,     2, 32, 0, dont, FALSE),
+  RXREL (OPor,      2, 32, 0, dont, FALSE),
+  RXREL (OPxor,     2, 32, 0, dont, FALSE),
+  RXREL (OPnot,     2, 32, 0, dont, FALSE),
+  RXREL (OPmod,     2, 32, 0, dont, FALSE),
+  RXREL (OPromtop,  2, 32, 0, dont, FALSE),
+  RXREL (OPramtop,  2, 32, 0, dont, FALSE)
+};
+\f
+/* Map BFD reloc types to RX ELF reloc types.  */
+
+struct rx_reloc_map
+{
+  bfd_reloc_code_real_type  bfd_reloc_val;
+  unsigned int              rx_reloc_val;
+};
+
+static const struct rx_reloc_map rx_reloc_map [] =
+{
+  { BFD_RELOC_NONE,            R_RX_NONE },
+  { BFD_RELOC_8,               R_RX_DIR8S },
+  { BFD_RELOC_16,              R_RX_DIR16S },
+  { BFD_RELOC_24,              R_RX_DIR24S },
+  { BFD_RELOC_32,              R_RX_DIR32 },
+  { BFD_RELOC_RX_16_OP,                R_RX_DIR16 },
+  { BFD_RELOC_RX_DIR3U_PCREL,  R_RX_DIR3U_PCREL },
+  { BFD_RELOC_8_PCREL,         R_RX_DIR8S_PCREL },
+  { BFD_RELOC_16_PCREL,                R_RX_DIR16S_PCREL },
+  { BFD_RELOC_24_PCREL,                R_RX_DIR24S_PCREL },
+  { BFD_RELOC_RX_8U,           R_RX_DIR8U },
+  { BFD_RELOC_RX_16U,          R_RX_DIR16U },
+  { BFD_RELOC_RX_24U,          R_RX_RH_24_UNS },
+  { BFD_RELOC_RX_NEG8,         R_RX_RH_8_NEG },
+  { BFD_RELOC_RX_NEG16,                R_RX_RH_16_NEG },
+  { BFD_RELOC_RX_NEG24,                R_RX_RH_24_NEG },
+  { BFD_RELOC_RX_NEG32,                R_RX_RH_32_NEG },
+  { BFD_RELOC_RX_DIFF,         R_RX_RH_DIFF },
+  { BFD_RELOC_RX_GPRELB,       R_RX_RH_GPRELB },
+  { BFD_RELOC_RX_GPRELW,       R_RX_RH_GPRELW },
+  { BFD_RELOC_RX_GPRELL,       R_RX_RH_GPRELL },
+  { BFD_RELOC_RX_RELAX,                R_RX_RH_RELAX },
+  { BFD_RELOC_RX_SYM,          R_RX_SYM },
+  { BFD_RELOC_RX_OP_SUBTRACT,  R_RX_OPsub },
+  { BFD_RELOC_RX_ABS8,         R_RX_ABS8 },
+  { BFD_RELOC_RX_ABS16,                R_RX_ABS16 },
+  { BFD_RELOC_RX_ABS32,                R_RX_ABS32 },
+  { BFD_RELOC_RX_ABS16UL,      R_RX_ABS16UL },
+  { BFD_RELOC_RX_ABS16UW,      R_RX_ABS16UW },
+  { BFD_RELOC_RX_ABS16U,       R_RX_ABS16U }
+};
+
+#define BIGE(abfd)       ((abfd)->xvec->byteorder == BFD_ENDIAN_BIG)
+
+static reloc_howto_type *
+rx_reloc_type_lookup (bfd *                    abfd ATTRIBUTE_UNUSED,
+                     bfd_reloc_code_real_type code)
+{
+  unsigned int i;
+
+  if (code == BFD_RELOC_RX_32_OP)
+    return rx_elf_howto_table + R_RX_DIR32;
+
+  for (i = ARRAY_SIZE (rx_reloc_map); --i;)
+    if (rx_reloc_map [i].bfd_reloc_val == code)
+      return rx_elf_howto_table + rx_reloc_map[i].rx_reloc_val;
+
+  return NULL;
+}
+
+static reloc_howto_type *
+rx_reloc_name_lookup (bfd * abfd ATTRIBUTE_UNUSED, const char * r_name)
+{
+  unsigned int i;
+
+  for (i = 0; i < ARRAY_SIZE (rx_elf_howto_table); i++)
+    if (rx_elf_howto_table[i].name != NULL
+       && strcasecmp (rx_elf_howto_table[i].name, r_name) == 0)
+      return rx_elf_howto_table + i;
+
+  return NULL;
+}
+
+/* Set the howto pointer for an RX ELF reloc.  */
+
+static void
+rx_info_to_howto_rela (bfd *               abfd ATTRIBUTE_UNUSED,
+                      arelent *           cache_ptr,
+                      Elf_Internal_Rela * dst)
+{
+  unsigned int r_type;
+
+  r_type = ELF32_R_TYPE (dst->r_info);
+  BFD_ASSERT (r_type < (unsigned int) R_RX_max);
+  cache_ptr->howto = rx_elf_howto_table + r_type;
+}
+\f
+static bfd_vma
+get_symbol_value (const char *            name,
+                 bfd_reloc_status_type * stat,
+                 struct bfd_link_info *  info,
+                 bfd *                   input_bfd,
+                 asection *              input_section,
+                 int                     offset)
+{
+  bfd_vma value = 0;
+  struct bfd_link_hash_entry * h;
+
+  h = bfd_link_hash_lookup (info->hash, name, FALSE, FALSE, TRUE);
+
+  if (h == NULL
+      || (h->type != bfd_link_hash_defined
+         && h->type != bfd_link_hash_defweak))
+    * stat = info->callbacks->undefined_symbol
+      (info, name, input_bfd, input_section, offset, TRUE);
+  else
+    value = (h->u.def.value
+            + h->u.def.section->output_section->vma
+            + h->u.def.section->output_offset);
+
+  return value;
+}
+
+static bfd_vma
+get_gp (bfd_reloc_status_type * stat,
+       struct bfd_link_info *  info,
+       bfd *                   abfd,
+       asection *              sec,
+       int                     offset)
+{
+  static bfd_boolean cached = FALSE;
+  static bfd_vma     cached_value = 0;
+
+  if (!cached)
+    {
+      cached_value = get_symbol_value ("__gp", stat, info, abfd, sec, offset);
+      cached = TRUE;
+    }
+  return cached_value;
+}
+
+static bfd_vma
+get_romstart (bfd_reloc_status_type * stat,
+             struct bfd_link_info *  info,
+             bfd *                   abfd,
+             asection *              sec,
+             int                     offset)
+{
+  static bfd_boolean cached = FALSE;
+  static bfd_vma     cached_value = 0;
+
+  if (!cached)
+    {
+      cached_value = get_symbol_value ("_start", stat, info, abfd, sec, offset);
+      cached = TRUE;
+    }
+  return cached_value;
+}
+
+static bfd_vma
+get_ramstart (bfd_reloc_status_type * stat,
+             struct bfd_link_info *  info,
+             bfd *                   abfd,
+             asection *              sec,
+             int                     offset)
+{
+  static bfd_boolean cached = FALSE;
+  static bfd_vma     cached_value = 0;
+
+  if (!cached)
+    {
+      cached_value = get_symbol_value ("__datastart", stat, info, abfd, sec, offset);
+      cached = TRUE;
+    }
+  return cached_value;
+}
+
+#define NUM_STACK_ENTRIES 16
+static int32_t rx_stack [ NUM_STACK_ENTRIES ];
+static unsigned int rx_stack_top;
+
+#define RX_STACK_PUSH(val)                     \
+  do                                           \
+    {                                          \
+      if (rx_stack_top < NUM_STACK_ENTRIES)    \
+        rx_stack [rx_stack_top ++] = (val);    \
+      else                                     \
+        r = bfd_reloc_dangerous;               \
+    }                                          \
+  while (0)
+
+#define RX_STACK_POP(dest)                     \
+  do                                           \
+    {                                          \
+      if (rx_stack_top > 0)                    \
+        (dest) = rx_stack [-- rx_stack_top];   \
+      else                                     \
+        (dest) = 0, r = bfd_reloc_dangerous;   \
+    }                                          \
+  while (0)
+
+/* Relocate an RX ELF section.
+   There is some attempt to make this function usable for many architectures,
+   both USE_REL and USE_RELA ['twould be nice if such a critter existed],
+   if only to serve as a learning tool.
+
+   The RELOCATE_SECTION function is called by the new ELF backend linker
+   to handle the relocations for a section.
+
+   The relocs are always passed as Rela structures; if the section
+   actually uses Rel structures, the r_addend field will always be
+   zero.
+
+   This function is responsible for adjusting the section contents as
+   necessary, and (if using Rela relocs and generating a relocatable
+   output file) adjusting the reloc addend as necessary.
+
+   This function does not have to worry about setting the reloc
+   address or the reloc symbol index.
+
+   LOCAL_SYMS is a pointer to the swapped in local symbols.
+
+   LOCAL_SECTIONS is an array giving the section in the input file
+   corresponding to the st_shndx field of each local symbol.
+
+   The global hash table entry for the global symbols can be found
+   via elf_sym_hashes (input_bfd).
+
+   When generating relocatable output, this function must handle
+   STB_LOCAL/STT_SECTION symbols specially.  The output symbol is
+   going to be the section symbol corresponding to the output
+   section, which means that the addend must be adjusted
+   accordingly.  */
+
+static bfd_boolean
+rx_elf_relocate_section
+    (bfd *                   output_bfd,
+     struct bfd_link_info *  info,
+     bfd *                   input_bfd,
+     asection *              input_section,
+     bfd_byte *              contents,
+     Elf_Internal_Rela *     relocs,
+     Elf_Internal_Sym *      local_syms,
+     asection **             local_sections)
+{
+  Elf_Internal_Shdr *           symtab_hdr;
+  struct elf_link_hash_entry ** sym_hashes;
+  Elf_Internal_Rela *           rel;
+  Elf_Internal_Rela *           relend;
+  bfd *                                dynobj;
+  asection *                   splt;
+
+  symtab_hdr = & elf_tdata (input_bfd)->symtab_hdr;
+  sym_hashes = elf_sym_hashes (input_bfd);
+  relend     = relocs + input_section->reloc_count;
+
+  dynobj = elf_hash_table (info)->dynobj;
+  splt = NULL;
+  if (dynobj != NULL)
+    splt = bfd_get_section_by_name (dynobj, ".plt");
+
+  for (rel = relocs; rel < relend; rel ++)
+    {
+      reloc_howto_type *           howto;
+      unsigned long                r_symndx;
+      Elf_Internal_Sym *           sym;
+      asection *                   sec;
+      struct elf_link_hash_entry * h;
+      bfd_vma                      relocation;
+      bfd_reloc_status_type        r;
+      const char *                 name = NULL;
+      bfd_boolean                  unresolved_reloc = TRUE;
+      int                          r_type;
+
+      r_type = ELF32_R_TYPE (rel->r_info);
+      r_symndx = ELF32_R_SYM (rel->r_info);
+
+      howto  = rx_elf_howto_table + ELF32_R_TYPE (rel->r_info);
+      h      = NULL;
+      sym    = NULL;
+      sec    = NULL;
+      relocation = 0;
+
+      if (r_symndx < symtab_hdr->sh_info)
+       {
+         sym = local_syms + r_symndx;
+         sec = local_sections [r_symndx];
+         relocation = _bfd_elf_rela_local_sym (output_bfd, sym, & sec, rel);
+
+         name = bfd_elf_string_from_elf_section
+           (input_bfd, symtab_hdr->sh_link, sym->st_name);
+         name = (sym->st_name == 0) ? bfd_section_name (input_bfd, sec) : name;
+       }
+      else
+       {
+         bfd_boolean warned;
+
+         RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
+                                  r_symndx, symtab_hdr, sym_hashes, h,
+                                  sec, relocation, unresolved_reloc,
+                                  warned);
+
+         name = h->root.root.string;
+       }
+
+      if (sec != NULL && elf_discarded_section (sec))
+       {
+         /* For relocs against symbols from removed linkonce sections,
+            or sections discarded by a linker script, we just want the
+            section contents zeroed.  Avoid any special processing.  */
+         _bfd_clear_contents (howto, input_bfd, contents + rel->r_offset);
+         rel->r_info = 0;
+         rel->r_addend = 0;
+         continue;
+       }
+
+      if (info->relocatable)
+       {
+         /* This is a relocatable link.  We don't have to change
+             anything, unless the reloc is against a section symbol,
+             in which case we have to adjust according to where the
+             section symbol winds up in the output section.  */
+         if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
+           rel->r_addend += sec->output_offset;
+         continue;
+       }
+
+      if (h != NULL && h->root.type == bfd_link_hash_undefweak)
+       /* If the symbol is undefined and weak
+          then the relocation resolves to zero.  */
+       relocation = 0;
+      else
+       {
+         if (howto->pc_relative)
+           {
+             relocation -= (input_section->output_section->vma
+                            + input_section->output_offset
+                            + rel->r_offset);
+             if (r_type != R_RX_RH_3_PCREL
+                 && r_type != R_RX_DIR3U_PCREL)
+               relocation ++;
+           }
+
+         relocation += rel->r_addend;
+       }
+
+      r = bfd_reloc_ok;
+
+#define RANGE(a,b) if (a > (long) relocation || (long) relocation > b) r = bfd_reloc_overflow
+#define ALIGN(m)   if (relocation & m) r = bfd_reloc_other;
+#define OP(i)      (contents[rel->r_offset + (i)])
+#define WARN_REDHAT(type) \
+      _bfd_error_handler (_("%B:%A: Warning: deprecated Red Hat reloc " type " detected against: %s."), \
+      input_bfd, input_section, name)
+
+      /* Opcode relocs are always big endian.  Data relocs are bi-endian.  */
+      switch (r_type)
+       {
+       case R_RX_NONE:
+         break;
+
+       case R_RX_RH_RELAX:
+         break;
+
+       case R_RX_RH_3_PCREL:
+         WARN_REDHAT ("RX_RH_3_PCREL");
+         RANGE (3, 10);
+         OP (0) &= 0xf8;
+         OP (0) |= relocation & 0x07;
+         break;
+
+       case R_RX_RH_8_NEG:
+         WARN_REDHAT ("RX_RH_8_NEG");
+         relocation = - relocation;
+       case R_RX_DIR8S_PCREL:
+         RANGE (-128, 127);
+         OP (0) = relocation;
+         break;
+
+       case R_RX_DIR8S:
+         RANGE (-128, 255);
+         OP (0) = relocation;
+         break;
+
+       case R_RX_DIR8U:
+         RANGE (0, 255);
+         OP (0) = relocation;
+         break;
+
+       case R_RX_RH_16_NEG:
+         WARN_REDHAT ("RX_RH_16_NEG");
+         relocation = - relocation;
+       case R_RX_DIR16S_PCREL:
+         RANGE (-32768, 32767);
+#if RX_OPCODE_BIG_ENDIAN
+#else
+         OP (0) = relocation;
+         OP (1) = relocation >> 8;
+#endif
+         break;
+
+       case R_RX_RH_16_OP:
+         WARN_REDHAT ("RX_RH_16_OP");
+         RANGE (-32768, 32767);
+#if RX_OPCODE_BIG_ENDIAN
+         OP (1) = relocation;
+         OP (0) = relocation >> 8;
+#else
+         OP (0) = relocation;
+         OP (1) = relocation >> 8;
+#endif
+         break;
+
+       case R_RX_DIR16S:
+         RANGE (-32768, 65535);
+         if (BIGE (output_bfd) && !(input_section->flags & SEC_CODE))
+           {
+             OP (1) = relocation;
+             OP (0) = relocation >> 8;
+           }
+         else
+           {
+             OP (0) = relocation;
+             OP (1) = relocation >> 8;
+           }
+         break;
+
+       case R_RX_DIR16U:
+         RANGE (0, 65536);
+#if RX_OPCODE_BIG_ENDIAN
+         OP (1) = relocation;
+         OP (0) = relocation >> 8;
+#else
+         OP (0) = relocation;
+         OP (1) = relocation >> 8;
+#endif
+         break;
+
+       case R_RX_DIR16:
+         RANGE (-32768, 65536);
+#if RX_OPCODE_BIG_ENDIAN
+         OP (1) = relocation;
+         OP (0) = relocation >> 8;
+#else
+         OP (0) = relocation;
+         OP (1) = relocation >> 8;
+#endif
+         break;
+
+       case R_RX_DIR16_REV:
+         RANGE (-32768, 65536);
+#if RX_OPCODE_BIG_ENDIAN
+         OP (0) = relocation;
+         OP (1) = relocation >> 8;
+#else
+         OP (1) = relocation;
+         OP (0) = relocation >> 8;
+#endif
+         break;
+
+       case R_RX_DIR3U_PCREL:
+         RANGE (3, 10);
+         OP (0) &= 0xf8;
+         OP (0) |= relocation & 0x07;
+         break;
+
+       case R_RX_RH_24_NEG:
+         WARN_REDHAT ("RX_RH_24_NEG");
+         relocation = - relocation;
+       case R_RX_DIR24S_PCREL:
+         RANGE (-0x800000, 0x7fffff);
+#if RX_OPCODE_BIG_ENDIAN
+         OP (2) = relocation;
+         OP (1) = relocation >> 8;
+         OP (0) = relocation >> 16;
+#else
+         OP (0) = relocation;
+         OP (1) = relocation >> 8;
+         OP (2) = relocation >> 16;
+#endif
+         break;
+
+       case R_RX_RH_24_OP:
+         WARN_REDHAT ("RX_RH_24_OP");
+         RANGE (-0x800000, 0x7fffff);
+#if RX_OPCODE_BIG_ENDIAN
+         OP (2) = relocation;
+         OP (1) = relocation >> 8;
+         OP (0) = relocation >> 16;
+#else
+         OP (0) = relocation;
+         OP (1) = relocation >> 8;
+         OP (2) = relocation >> 16;
+#endif
+         break;
+
+       case R_RX_DIR24S:
+         RANGE (-0x800000, 0x7fffff);
+         if (BIGE (output_bfd) && !(input_section->flags & SEC_CODE))
+           {
+             OP (2) = relocation;
+             OP (1) = relocation >> 8;
+             OP (0) = relocation >> 16;
+           }
+         else
+           {
+             OP (0) = relocation;
+             OP (1) = relocation >> 8;
+             OP (2) = relocation >> 16;
+           }
+         break;
+
+       case R_RX_RH_24_UNS:
+         WARN_REDHAT ("RX_RH_24_UNS");
+         RANGE (0, 0xffffff);
+#if RX_OPCODE_BIG_ENDIAN
+         OP (2) = relocation;
+         OP (1) = relocation >> 8;
+         OP (0) = relocation >> 16;
+#else
+         OP (0) = relocation;
+         OP (1) = relocation >> 8;
+         OP (2) = relocation >> 16;
+#endif
+         break;
+
+       case R_RX_RH_32_NEG:
+         WARN_REDHAT ("RX_RH_32_NEG");
+         relocation = - relocation;
+#if RX_OPCODE_BIG_ENDIAN
+         OP (3) = relocation;
+         OP (2) = relocation >> 8;
+         OP (1) = relocation >> 16;
+         OP (0) = relocation >> 24;
+#else
+         OP (0) = relocation;
+         OP (1) = relocation >> 8;
+         OP (2) = relocation >> 16;
+         OP (3) = relocation >> 24;
+#endif
+         break;
+
+       case R_RX_RH_32_OP:
+         WARN_REDHAT ("RX_RH_32_OP");
+#if RX_OPCODE_BIG_ENDIAN
+         OP (3) = relocation;
+         OP (2) = relocation >> 8;
+         OP (1) = relocation >> 16;
+         OP (0) = relocation >> 24;
+#else
+         OP (0) = relocation;
+         OP (1) = relocation >> 8;
+         OP (2) = relocation >> 16;
+         OP (3) = relocation >> 24;
+#endif
+         break;
+
+       case R_RX_DIR32:
+         if (BIGE (output_bfd) && !(input_section->flags & SEC_CODE))
+           {
+             OP (3) = relocation;
+             OP (2) = relocation >> 8;
+             OP (1) = relocation >> 16;
+             OP (0) = relocation >> 24;
+           }
+         else
+           {
+             OP (0) = relocation;
+             OP (1) = relocation >> 8;
+             OP (2) = relocation >> 16;
+             OP (3) = relocation >> 24;
+           }
+         break;
+
+       case R_RX_DIR32_REV:
+         if (BIGE (output_bfd))
+           {
+             OP (0) = relocation;
+             OP (1) = relocation >> 8;
+             OP (2) = relocation >> 16;
+             OP (3) = relocation >> 24;
+           }
+         else
+           {
+             OP (3) = relocation;
+             OP (2) = relocation >> 8;
+             OP (1) = relocation >> 16;
+             OP (0) = relocation >> 24;
+           }
+         break;
+
+       case R_RX_RH_DIFF:
+         {
+           bfd_vma val;
+           WARN_REDHAT ("RX_RH_DIFF");
+           val = bfd_get_32 (output_bfd, & OP (0));
+           val -= relocation;
+           bfd_put_32 (output_bfd, val, & OP (0));
+         }
+         break;
+
+       case R_RX_RH_GPRELB:
+         WARN_REDHAT ("RX_RH_GPRELB");
+         relocation -= get_gp (&r, info, input_bfd, input_section, rel->r_offset);
+         RANGE (0, 65535);
+#if RX_OPCODE_BIG_ENDIAN
+         OP (1) = relocation;
+         OP (0) = relocation >> 8;
+#else
+         OP (0) = relocation;
+         OP (1) = relocation >> 8;
+#endif
+         break;
+
+       case R_RX_RH_GPRELW:
+         WARN_REDHAT ("RX_RH_GPRELW");
+         relocation -= get_gp (&r, info, input_bfd, input_section, rel->r_offset);
+         ALIGN (1);
+         relocation >>= 1;
+         RANGE (0, 65535);
+#if RX_OPCODE_BIG_ENDIAN
+         OP (1) = relocation;
+         OP (0) = relocation >> 8;
+#else
+         OP (0) = relocation;
+         OP (1) = relocation >> 8;
+#endif
+         break;
+
+       case R_RX_RH_GPRELL:
+         WARN_REDHAT ("RX_RH_GPRELL");
+         relocation -= get_gp (&r, info, input_bfd, input_section, rel->r_offset);
+         ALIGN (3);
+         relocation >>= 2;
+         RANGE (0, 65535);
+#if RX_OPCODE_BIG_ENDIAN
+         OP (1) = relocation;
+         OP (0) = relocation >> 8;
+#else
+         OP (0) = relocation;
+         OP (1) = relocation >> 8;
+#endif
+         break;
+
+       /* Internal relocations just for relaxation:  */
+       case R_RX_RH_ABS5p5B:
+         RX_STACK_POP (relocation);
+         RANGE (0, 31);
+         OP (0) &= 0xf8;
+         OP (0) |= relocation >> 2;
+         OP (1) &= 0x77;
+         OP (1) |= (relocation << 6) & 0x80;
+         OP (1) |= (relocation << 3) & 0x08;
+         break;
+
+       case R_RX_RH_ABS5p5W:
+         RX_STACK_POP (relocation);
+         RANGE (0, 62);
+         ALIGN (1);
+         relocation >>= 1;
+         OP (0) &= 0xf8;
+         OP (0) |= relocation >> 2;
+         OP (1) &= 0x77;
+         OP (1) |= (relocation << 6) & 0x80;
+         OP (1) |= (relocation << 3) & 0x08;
+         break;
+
+       case R_RX_RH_ABS5p5L:
+         RX_STACK_POP (relocation);
+         RANGE (0, 124);
+         ALIGN (3);
+         relocation >>= 2;
+         OP (0) &= 0xf8;
+         OP (0) |= relocation >> 2;
+         OP (1) &= 0x77;
+         OP (1) |= (relocation << 6) & 0x80;
+         OP (1) |= (relocation << 3) & 0x08;
+         break;
+
+       case R_RX_RH_ABS5p8B:
+         RX_STACK_POP (relocation);
+         RANGE (0, 31);
+         OP (0) &= 0x70;
+         OP (0) |= (relocation << 3) & 0x80;
+         OP (0) |= relocation & 0x0f;
+         break;
+
+       case R_RX_RH_ABS5p8W:
+         RX_STACK_POP (relocation);
+         RANGE (0, 62);
+         ALIGN (1);
+         relocation >>= 1;
+         OP (0) &= 0x70;
+         OP (0) |= (relocation << 3) & 0x80;
+         OP (0) |= relocation & 0x0f;
+         break;
+
+       case R_RX_RH_ABS5p8L:
+         RX_STACK_POP (relocation);
+         RANGE (0, 124);
+         ALIGN (3);
+         relocation >>= 2;
+         OP (0) &= 0x70;
+         OP (0) |= (relocation << 3) & 0x80;
+         OP (0) |= relocation & 0x0f;
+         break;
+
+       case R_RX_RH_UIMM4p8:
+         RANGE (0, 15);
+         OP (0) &= 0x0f;
+         OP (0) |= relocation << 4;
+         break;
+
+       case R_RX_RH_UNEG4p8:
+         RANGE (-15, 0);
+         OP (0) &= 0x0f;
+         OP (0) |= (-relocation) << 4;
+         break;
+
+         /* Complex reloc handling:  */
+
+       case R_RX_ABS32:
+         RX_STACK_POP (relocation);
+#if RX_OPCODE_BIG_ENDIAN
+         OP (3) = relocation;
+         OP (2) = relocation >> 8;
+         OP (1) = relocation >> 16;
+         OP (0) = relocation >> 24;
+#else
+         OP (0) = relocation;
+         OP (1) = relocation >> 8;
+         OP (2) = relocation >> 16;
+         OP (3) = relocation >> 24;
+#endif
+         break;
+
+       case R_RX_ABS32_REV:
+         RX_STACK_POP (relocation);
+#if RX_OPCODE_BIG_ENDIAN
+         OP (0) = relocation;
+         OP (1) = relocation >> 8;
+         OP (2) = relocation >> 16;
+         OP (3) = relocation >> 24;
+#else
+         OP (3) = relocation;
+         OP (2) = relocation >> 8;
+         OP (1) = relocation >> 16;
+         OP (0) = relocation >> 24;
+#endif
+         break;
+
+       case R_RX_ABS24S_PCREL:
+       case R_RX_ABS24S:
+         RX_STACK_POP (relocation);
+         RANGE (-0x800000, 0x7fffff);
+         if (BIGE (output_bfd) && !(input_section->flags & SEC_CODE))
+           {
+             OP (2) = relocation;
+             OP (1) = relocation >> 8;
+             OP (0) = relocation >> 16;
+           }
+         else
+           {
+             OP (0) = relocation;
+             OP (1) = relocation >> 8;
+             OP (2) = relocation >> 16;
+           }
+         break;
+
+       case R_RX_ABS16:
+         RX_STACK_POP (relocation);
+         RANGE (-32768, 65535);
+#if RX_OPCODE_BIG_ENDIAN
+         OP (1) = relocation;
+         OP (0) = relocation >> 8;
+#else
+         OP (0) = relocation;
+         OP (1) = relocation >> 8;
+#endif
+         break;
+
+       case R_RX_ABS16_REV:
+         RX_STACK_POP (relocation);
+         RANGE (-32768, 65535);
+#if RX_OPCODE_BIG_ENDIAN
+         OP (0) = relocation;
+         OP (1) = relocation >> 8;
+#else
+         OP (1) = relocation;
+         OP (0) = relocation >> 8;
+#endif
+         break;
+
+       case R_RX_ABS16S_PCREL:
+       case R_RX_ABS16S:
+         RX_STACK_POP (relocation);
+         RANGE (-32768, 32767);
+         if (BIGE (output_bfd) && !(input_section->flags & SEC_CODE))
+           {
+             OP (1) = relocation;
+             OP (0) = relocation >> 8;
+           }
+         else
+           {
+             OP (0) = relocation;
+             OP (1) = relocation >> 8;
+           }
+         break;
+
+       case R_RX_ABS16U:
+         RX_STACK_POP (relocation);
+         RANGE (0, 65536);
+#if RX_OPCODE_BIG_ENDIAN
+         OP (1) = relocation;
+         OP (0) = relocation >> 8;
+#else
+         OP (0) = relocation;
+         OP (1) = relocation >> 8;
+#endif
+         break;
+
+       case R_RX_ABS16UL:
+         RX_STACK_POP (relocation);
+         relocation >>= 2;
+         RANGE (0, 65536);
+#if RX_OPCODE_BIG_ENDIAN
+         OP (1) = relocation;
+         OP (0) = relocation >> 8;
+#else
+         OP (0) = relocation;
+         OP (1) = relocation >> 8;
+#endif
+         break;
+
+       case R_RX_ABS16UW:
+         RX_STACK_POP (relocation);
+         relocation >>= 1;
+         RANGE (0, 65536);
+#if RX_OPCODE_BIG_ENDIAN
+         OP (1) = relocation;
+         OP (0) = relocation >> 8;
+#else
+         OP (0) = relocation;
+         OP (1) = relocation >> 8;
+#endif
+         break;
+
+       case R_RX_ABS8:
+         RX_STACK_POP (relocation);
+         RANGE (-128, 255);
+         OP (0) = relocation;
+         break;
+
+       case R_RX_ABS8U:
+         RX_STACK_POP (relocation);
+         RANGE (0, 255);
+         OP (0) = relocation;
+         break;
+
+       case R_RX_ABS8UL:
+         RX_STACK_POP (relocation);
+         relocation >>= 2;
+         RANGE (0, 255);
+         OP (0) = relocation;
+         break;
+
+       case R_RX_ABS8UW:
+         RX_STACK_POP (relocation);
+         relocation >>= 1;
+         RANGE (0, 255);
+         OP (0) = relocation;
+         break;
+
+       case R_RX_ABS8S_PCREL:
+       case R_RX_ABS8S:
+         RX_STACK_POP (relocation);
+         RANGE (-128, 127);
+         OP (0) = relocation;
+         break;
+
+       case R_RX_SYM:
+         if (r_symndx < symtab_hdr->sh_info)
+           RX_STACK_PUSH (sec->output_section->vma
+                          + sec->output_offset
+                          + sym->st_value);
+         else
+           {
+             if (h != NULL
+                 && (h->root.type == bfd_link_hash_defined
+                     || h->root.type == bfd_link_hash_defweak))
+               RX_STACK_PUSH (h->root.u.def.value
+                              + sec->output_section->vma
+                              + sec->output_offset);
+             else
+               _bfd_error_handler (_("Warning: RX_SYM reloc with an unknown symbol"));
+           }
+         break;
+
+       case R_RX_OPneg:
+         {
+           int32_t tmp;
+
+           RX_STACK_POP (tmp);
+           tmp = - tmp;
+           RX_STACK_PUSH (tmp);
+         }
+         break;
+
+       case R_RX_OPadd:
+         {
+           int32_t tmp1, tmp2;
+
+           RX_STACK_POP (tmp1);
+           RX_STACK_POP (tmp2);
+           tmp1 += tmp2;
+           RX_STACK_PUSH (tmp1);
+         }
+         break;
+
+       case R_RX_OPsub:
+         {
+           int32_t tmp1, tmp2;
+
+           RX_STACK_POP (tmp1);
+           RX_STACK_POP (tmp2);
+           tmp2 -= tmp1;
+           RX_STACK_PUSH (tmp2);
+         }
+         break;
+
+       case R_RX_OPmul:
+         {
+           int32_t tmp1, tmp2;
+
+           RX_STACK_POP (tmp1);
+           RX_STACK_POP (tmp2);
+           tmp1 *= tmp2;
+           RX_STACK_PUSH (tmp1);
+         }
+         break;
+
+       case R_RX_OPdiv:
+         {
+           int32_t tmp1, tmp2;
+
+           RX_STACK_POP (tmp1);
+           RX_STACK_POP (tmp2);
+           tmp1 /= tmp2;
+           RX_STACK_PUSH (tmp1);
+         }
+         break;
+
+       case R_RX_OPshla:
+         {
+           int32_t tmp1, tmp2;
+
+           RX_STACK_POP (tmp1);
+           RX_STACK_POP (tmp2);
+           tmp1 <<= tmp2;
+           RX_STACK_PUSH (tmp1);
+         }
+         break;
+
+       case R_RX_OPshra:
+         {
+           int32_t tmp1, tmp2;
+
+           RX_STACK_POP (tmp1);
+           RX_STACK_POP (tmp2);
+           tmp1 >>= tmp2;
+           RX_STACK_PUSH (tmp1);
+         }
+         break;
+
+       case R_RX_OPsctsize:
+         RX_STACK_PUSH (input_section->size);
+         break;
+
+       case R_RX_OPscttop:
+         RX_STACK_PUSH (input_section->output_section->vma);
+         break;
+
+       case R_RX_OPand:
+         {
+           int32_t tmp1, tmp2;
+
+           RX_STACK_POP (tmp1);
+           RX_STACK_POP (tmp2);
+           tmp1 &= tmp2;
+           RX_STACK_PUSH (tmp1);
+         }
+         break;
+
+       case R_RX_OPor:
+         {
+           int32_t tmp1, tmp2;
+
+           RX_STACK_POP (tmp1);
+           RX_STACK_POP (tmp2);
+           tmp1 |= tmp2;
+           RX_STACK_PUSH (tmp1);
+         }
+         break;
+
+       case R_RX_OPxor:
+         {
+           int32_t tmp1, tmp2;
+
+           RX_STACK_POP (tmp1);
+           RX_STACK_POP (tmp2);
+           tmp1 ^= tmp2;
+           RX_STACK_PUSH (tmp1);
+         }
+         break;
+
+       case R_RX_OPnot:
+         {
+           int32_t tmp;
+
+           RX_STACK_POP (tmp);
+           tmp = ~ tmp;
+           RX_STACK_PUSH (tmp);
+         }
+         break;
+
+       case R_RX_OPmod:
+         {
+           int32_t tmp1, tmp2;
+
+           RX_STACK_POP (tmp1);
+           RX_STACK_POP (tmp2);
+           tmp1 %= tmp2;
+           RX_STACK_PUSH (tmp1);
+         }
+         break;
+
+       case R_RX_OPromtop:
+         RX_STACK_PUSH (get_romstart (&r, info, input_bfd, input_section, rel->r_offset));
+         break;
+
+       case R_RX_OPramtop:
+         RX_STACK_PUSH (get_ramstart (&r, info, input_bfd, input_section, rel->r_offset));
+         break;
+
+       default:
+         r = bfd_reloc_notsupported;
+         break;
+       }
+
+      if (r != bfd_reloc_ok)
+       {
+         const char * msg = NULL;
+
+         switch (r)
+           {
+           case bfd_reloc_overflow:
+             /* Catch the case of a missing function declaration
+                and emit a more helpful error message.  */
+             if (r_type == R_RX_DIR24S_PCREL)
+               msg = _("%B(%A): error: call to undefined function '%s'");
+             else
+               r = info->callbacks->reloc_overflow
+                 (info, (h ? &h->root : NULL), name, howto->name, (bfd_vma) 0,
+                  input_bfd, input_section, rel->r_offset);
+             break;
+
+           case bfd_reloc_undefined:
+             r = info->callbacks->undefined_symbol
+               (info, name, input_bfd, input_section, rel->r_offset,
+                TRUE);
+             break;
+
+           case bfd_reloc_other:
+             msg = _("%B(%A): warning: unaligned access to symbol '%s' in the small data area");
+             break;
+
+           case bfd_reloc_outofrange:
+             msg = _("%B(%A): internal error: out of range error");
+             break;
+
+           case bfd_reloc_notsupported:
+             msg = _("%B(%A): internal error: unsupported relocation error");
+             break;
+
+           case bfd_reloc_dangerous:
+             msg = _("%B(%A): internal error: dangerous relocation");
+             break;
+
+           default:
+             msg = _("%B(%A): internal error: unknown error");
+             break;
+           }
+
+         if (msg)
+           _bfd_error_handler (msg, input_bfd, input_section, name);
+
+         if (! r)
+           return FALSE;
+       }
+    }
+
+  return TRUE;
+}
+\f
+/* Relaxation Support.  */
+
+/* Progression of relocations from largest operand size to smallest
+   operand size.  */
+
+static int
+next_smaller_reloc (int r)
+{
+  switch (r)
+    {
+    case R_RX_DIR32:           return R_RX_DIR24S;
+    case R_RX_DIR24S:          return R_RX_DIR16S;
+    case R_RX_DIR16S:          return R_RX_DIR8S;
+    case R_RX_DIR8S:           return R_RX_NONE;
+
+    case R_RX_DIR16:           return R_RX_DIR8;
+    case R_RX_DIR8:            return R_RX_NONE;
+
+    case R_RX_DIR16U:          return R_RX_DIR8U;
+    case R_RX_DIR8U:           return R_RX_NONE;
+
+    case R_RX_DIR24S_PCREL:    return R_RX_DIR16S_PCREL;
+    case R_RX_DIR16S_PCREL:    return R_RX_DIR8S_PCREL;
+    case R_RX_DIR8S_PCREL:     return R_RX_DIR3U_PCREL;
+
+    case R_RX_DIR16UL:         return R_RX_DIR8UL;
+    case R_RX_DIR8UL:          return R_RX_NONE;
+    case R_RX_DIR16UW:         return R_RX_DIR8UW;
+    case R_RX_DIR8UW:          return R_RX_NONE;
+
+    case R_RX_RH_32_OP:                return R_RX_RH_24_OP;
+    case R_RX_RH_24_OP:                return R_RX_RH_16_OP;
+    case R_RX_RH_16_OP:                return R_RX_DIR8;
+
+    case R_RX_ABS32:           return R_RX_ABS24S;
+    case R_RX_ABS24S:          return R_RX_ABS16S;
+    case R_RX_ABS16:           return R_RX_ABS8;
+    case R_RX_ABS16U:          return R_RX_ABS8U;
+    case R_RX_ABS16S:          return R_RX_ABS8S;
+    case R_RX_ABS8:            return R_RX_NONE;
+    case R_RX_ABS8U:           return R_RX_NONE;
+    case R_RX_ABS8S:           return R_RX_NONE;
+    case R_RX_ABS24S_PCREL:    return R_RX_ABS16S_PCREL;
+    case R_RX_ABS16S_PCREL:    return R_RX_ABS8S_PCREL;
+    case R_RX_ABS8S_PCREL:     return R_RX_NONE;
+    case R_RX_ABS16UL:         return R_RX_ABS8UL;
+    case R_RX_ABS16UW:         return R_RX_ABS8UW;
+    case R_RX_ABS8UL:          return R_RX_NONE;
+    case R_RX_ABS8UW:          return R_RX_NONE;
+    }
+  return r;
+};
+
+/* Delete some bytes from a section while relaxing.  */
+
+static bfd_boolean
+elf32_rx_relax_delete_bytes (bfd *abfd, asection *sec, bfd_vma addr, int count,
+                            Elf_Internal_Rela *alignment_rel, int force_snip)
+{
+  Elf_Internal_Shdr * symtab_hdr;
+  unsigned int        sec_shndx;
+  bfd_byte *          contents;
+  Elf_Internal_Rela * irel;
+  Elf_Internal_Rela * irelend;
+  Elf_Internal_Rela * irelalign;
+  Elf_Internal_Sym *  isym;
+  Elf_Internal_Sym *  isymend;
+  bfd_vma             toaddr;
+  unsigned int        symcount;
+  struct elf_link_hash_entry ** sym_hashes;
+  struct elf_link_hash_entry ** end_hashes;
+
+  if (!alignment_rel)
+    force_snip = 1;
+
+  sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
+
+  contents = elf_section_data (sec)->this_hdr.contents;
+
+  /* The deletion must stop at the next alignment boundary, if
+     ALIGNMENT_REL is non-NULL.  */
+  irelalign = NULL;
+  toaddr = sec->size;
+  if (alignment_rel)
+    toaddr = alignment_rel->r_offset;
+
+  irel = elf_section_data (sec)->relocs;
+  irelend = irel + sec->reloc_count;
+
+  /* Actually delete the bytes.  */
+  memmove (contents + addr, contents + addr + count,
+          (size_t) (toaddr - addr - count));
+
+  /* If we don't have an alignment marker to worry about, we can just
+     shrink the section.  Otherwise, we have to fill in the newly
+     created gap with NOP insns (0x03).  */
+  if (force_snip)
+    sec->size -= count;
+  else
+    memset (contents + toaddr - count, 0x03, count);
+
+  /* Adjust all the relocs.  */
+  for (irel = elf_section_data (sec)->relocs; irel < irelend; irel++)
+    {
+      /* Get the new reloc address.  */
+      if (irel->r_offset > addr
+         && (irel->r_offset < toaddr
+             || (force_snip && irel->r_offset == toaddr)))
+       irel->r_offset -= count;
+
+      /* If we see an ALIGN marker at the end of the gap, we move it
+        to the beginning of the gap, since marking these gaps is what
+        they're for.  */
+      if (irel->r_offset == toaddr
+         && ELF32_R_TYPE (irel->r_info) == R_RX_RH_RELAX
+         && irel->r_addend & RX_RELAXA_ALIGN)
+       irel->r_offset -= count;
+    }
+
+  /* Adjust the local symbols defined in this section.  */
+  symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
+  isym = (Elf_Internal_Sym *) symtab_hdr->contents;
+  isymend = isym + symtab_hdr->sh_info;
+
+  for (; isym < isymend; isym++)
+    {
+      /* If the symbol is in the range of memory we just moved, we
+        have to adjust its value.  */
+      if (isym->st_shndx == sec_shndx
+         && isym->st_value > addr
+         && isym->st_value < toaddr)
+       isym->st_value -= count;
+
+      /* If the symbol *spans* the bytes we just deleted (i.e. it's
+        *end* is in the moved bytes but it's *start* isn't), then we
+        must adjust its size.  */
+      if (isym->st_shndx == sec_shndx
+         && isym->st_value < addr
+         && isym->st_value + isym->st_size > addr
+         && isym->st_value + isym->st_size < toaddr)
+       isym->st_size -= count;
+    }
+
+  /* Now adjust the global symbols defined in this section.  */
+  symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
+             - symtab_hdr->sh_info);
+  sym_hashes = elf_sym_hashes (abfd);
+  end_hashes = sym_hashes + symcount;
+
+  for (; sym_hashes < end_hashes; sym_hashes++)
+    {
+      struct elf_link_hash_entry *sym_hash = *sym_hashes;
+
+      if ((sym_hash->root.type == bfd_link_hash_defined
+          || sym_hash->root.type == bfd_link_hash_defweak)
+         && sym_hash->root.u.def.section == sec)
+       {
+         /* As above, adjust the value if needed.  */
+         if (sym_hash->root.u.def.value > addr
+             && sym_hash->root.u.def.value < toaddr)
+           sym_hash->root.u.def.value -= count;
+
+         /* As above, adjust the size if needed.  */
+         if (sym_hash->root.u.def.value < addr
+             && sym_hash->root.u.def.value + sym_hash->size > addr
+             && sym_hash->root.u.def.value + sym_hash->size < toaddr)
+           sym_hash->size -= count;
+       }
+    }
+
+  return TRUE;
+}
+
+/* Used to sort relocs by address.  If relocs have the same address,
+   we maintain their relative order, except that R_RX_RH_RELAX
+   alignment relocs must be the first reloc for any given address.  */
+
+static void
+reloc_bubblesort (Elf_Internal_Rela * r, int count)
+{
+  int i;
+  bfd_boolean again;
+  bfd_boolean swappit;
+
+  /* This is almost a classic bubblesort.  It's the slowest sort, but
+     we're taking advantage of the fact that the relocations are
+     mostly in order already (the assembler emits them that way) and
+     we need relocs with the same address to remain in the same
+     relative order.  */
+  again = TRUE;
+  while (again)
+    {
+      again = FALSE;
+      for (i = 0; i < count - 1; i ++)
+       {
+         if (r[i].r_offset > r[i + 1].r_offset)
+           swappit = TRUE;
+         else if (r[i].r_offset < r[i + 1].r_offset)
+           swappit = FALSE;
+         else if (ELF32_R_TYPE (r[i + 1].r_info) == R_RX_RH_RELAX
+                  && (r[i + 1].r_addend & RX_RELAXA_ALIGN))
+           swappit = TRUE;
+         else if (ELF32_R_TYPE (r[i + 1].r_info) == R_RX_RH_RELAX
+                  && (r[i + 1].r_addend & RX_RELAXA_ELIGN)
+                  && !(ELF32_R_TYPE (r[i].r_info) == R_RX_RH_RELAX
+                       && (r[i].r_addend & RX_RELAXA_ALIGN)))
+           swappit = TRUE;
+         else
+           swappit = FALSE;
+
+         if (swappit)
+           {
+             Elf_Internal_Rela tmp;
+
+             tmp = r[i];
+             r[i] = r[i + 1];
+             r[i + 1] = tmp;
+             /* If we do move a reloc back, re-scan to see if it
+                needs to be moved even further back.  This avoids
+                most of the O(n^2) behavior for our cases.  */
+             if (i > 0)
+               i -= 2;
+             again = TRUE;
+           }
+       }
+    }
+}
+
+
+#define OFFSET_FOR_RELOC(rel, lrel, scale) \
+  rx_offset_for_reloc (abfd, rel + 1, symtab_hdr, shndx_buf, intsyms, \
+                      lrel, abfd, sec, link_info, scale)
+
+static bfd_vma
+rx_offset_for_reloc (bfd *                    abfd,
+                    Elf_Internal_Rela *      rel,
+                    Elf_Internal_Shdr *      symtab_hdr,
+                    Elf_External_Sym_Shndx * shndx_buf,
+                    Elf_Internal_Sym *       intsyms,
+                    Elf_Internal_Rela **     lrel,
+                    bfd *                    input_bfd,
+                    asection *               input_section,
+                    struct bfd_link_info *   info,
+                    int *                    scale)
+{
+  bfd_vma symval;
+  bfd_reloc_status_type r;
+
+  *scale = 1;
+
+  /* REL is the first of 1..N relocations.  We compute the symbol
+     value for each relocation, then combine them if needed.  LREL
+     gets a pointer to the last relocation used.  */
+  while (1)
+    {
+      int32_t tmp1, tmp2;
+
+      /* Get the value of the symbol referred to by the reloc.  */
+      if (ELF32_R_SYM (rel->r_info) < symtab_hdr->sh_info)
+       {
+         /* A local symbol.  */
+         Elf_Internal_Sym *isym;
+         Elf_External_Sym_Shndx *shndx;
+         asection *ssec;
+
+         isym = intsyms + ELF32_R_SYM (rel->r_info);
+
+         if (isym->st_shndx == SHN_UNDEF)
+           ssec = bfd_und_section_ptr;
+         else if (isym->st_shndx == SHN_ABS)
+           ssec = bfd_abs_section_ptr;
+         else if (isym->st_shndx == SHN_COMMON)
+           ssec = bfd_com_section_ptr;
+         else
+           ssec = bfd_section_from_elf_index (abfd,
+                                              isym->st_shndx);
+
+         shndx = shndx_buf + (shndx_buf ? ELF32_R_SYM (rel->r_info) : 0);
+
+         /* Initial symbol value.  */
+         symval = isym->st_value;
+
+         /* GAS may have made this symbol relative to a section, in
+            which case, we have to add the addend to find the
+            symbol.  */
+         if (ELF_ST_TYPE (isym->st_info) == STT_SECTION)
+           symval += rel->r_addend;
+
+         if (ssec)
+           {
+             if ((ssec->flags & SEC_MERGE)
+                 && ssec->sec_info_type == ELF_INFO_TYPE_MERGE)
+               symval = _bfd_merged_section_offset (abfd, & ssec,
+                                                    elf_section_data (ssec)->sec_info,
+                                                    symval);
+           }
+
+         /* Now make the offset relative to where the linker is putting it.  */
+         if (ssec)
+           symval +=
+             ssec->output_section->vma + ssec->output_offset;
+
+         symval += rel->r_addend;
+       }
+      else
+       {
+         unsigned long indx;
+         struct elf_link_hash_entry * h;
+
+         /* An external symbol.  */
+         indx = ELF32_R_SYM (rel->r_info) - symtab_hdr->sh_info;
+         h = elf_sym_hashes (abfd)[indx];
+         BFD_ASSERT (h != NULL);
+
+         if (h->root.type != bfd_link_hash_defined
+             && h->root.type != bfd_link_hash_defweak)
+           {
+             /* This appears to be a reference to an undefined
+                symbol.  Just ignore it--it will be caught by the
+                regular reloc processing.  */
+             if (lrel)
+               *lrel = rel;
+             return 0;
+           }
+
+         symval = (h->root.u.def.value
+                   + h->root.u.def.section->output_section->vma
+                   + h->root.u.def.section->output_offset);
+
+         symval += rel->r_addend;
+       }
+
+      switch (ELF32_R_TYPE (rel->r_info))
+       {
+       case R_RX_SYM:
+         RX_STACK_PUSH (symval);
+         break;
+
+       case R_RX_OPneg:
+         RX_STACK_POP (tmp1);
+         tmp1 = - tmp1;
+         RX_STACK_PUSH (tmp1);
+         break;
+
+       case R_RX_OPadd:
+         RX_STACK_POP (tmp1);
+         RX_STACK_POP (tmp2);
+         tmp1 += tmp2;
+         RX_STACK_PUSH (tmp1);
+         break;
+
+       case R_RX_OPsub:
+         RX_STACK_POP (tmp1);
+         RX_STACK_POP (tmp2);
+         tmp2 -= tmp1;
+         RX_STACK_PUSH (tmp2);
+         break;
+
+       case R_RX_OPmul:
+         RX_STACK_POP (tmp1);
+         RX_STACK_POP (tmp2);
+         tmp1 *= tmp2;
+         RX_STACK_PUSH (tmp1);
+         break;
+
+       case R_RX_OPdiv:
+         RX_STACK_POP (tmp1);
+         RX_STACK_POP (tmp2);
+         tmp1 /= tmp2;
+         RX_STACK_PUSH (tmp1);
+         break;
+
+       case R_RX_OPshla:
+         RX_STACK_POP (tmp1);
+         RX_STACK_POP (tmp2);
+         tmp1 <<= tmp2;
+         RX_STACK_PUSH (tmp1);
+         break;
+
+       case R_RX_OPshra:
+         RX_STACK_POP (tmp1);
+         RX_STACK_POP (tmp2);
+         tmp1 >>= tmp2;
+         RX_STACK_PUSH (tmp1);
+         break;
+
+       case R_RX_OPsctsize:
+         RX_STACK_PUSH (input_section->size);
+         break;
+
+       case R_RX_OPscttop:
+         RX_STACK_PUSH (input_section->output_section->vma);
+         break;
+
+       case R_RX_OPand:
+         RX_STACK_POP (tmp1);
+         RX_STACK_POP (tmp2);
+         tmp1 &= tmp2;
+         RX_STACK_PUSH (tmp1);
+         break;
+
+       case R_RX_OPor:
+         RX_STACK_POP (tmp1);
+         RX_STACK_POP (tmp2);
+         tmp1 |= tmp2;
+         RX_STACK_PUSH (tmp1);
+         break;
+
+       case R_RX_OPxor:
+         RX_STACK_POP (tmp1);
+         RX_STACK_POP (tmp2);
+         tmp1 ^= tmp2;
+         RX_STACK_PUSH (tmp1);
+         break;
+
+       case R_RX_OPnot:
+         RX_STACK_POP (tmp1);
+         tmp1 = ~ tmp1;
+         RX_STACK_PUSH (tmp1);
+         break;
+
+       case R_RX_OPmod:
+         RX_STACK_POP (tmp1);
+         RX_STACK_POP (tmp2);
+         tmp1 %= tmp2;
+         RX_STACK_PUSH (tmp1);
+         break;
+
+       case R_RX_OPromtop:
+         RX_STACK_PUSH (get_romstart (&r, info, input_bfd, input_section, rel->r_offset));
+         break;
+
+       case R_RX_OPramtop:
+         RX_STACK_PUSH (get_ramstart (&r, info, input_bfd, input_section, rel->r_offset));
+         break;
+
+       case R_RX_DIR16UL:
+       case R_RX_DIR8UL:
+       case R_RX_ABS16UL:
+       case R_RX_ABS8UL:
+         if (rx_stack_top)
+           RX_STACK_POP (symval);
+         if (lrel)
+           *lrel = rel;
+         *scale = 4;
+         return symval;
+
+       case R_RX_DIR16UW:
+       case R_RX_DIR8UW:
+       case R_RX_ABS16UW:
+       case R_RX_ABS8UW:
+         if (rx_stack_top)
+           RX_STACK_POP (symval);
+         if (lrel)
+           *lrel = rel;
+         *scale = 2;
+         return symval;
+
+       default:
+         if (rx_stack_top)
+           RX_STACK_POP (symval);
+         if (lrel)
+           *lrel = rel;
+         return symval;
+       }
+
+      rel ++;
+    }
+}
+
+static void
+move_reloc (Elf_Internal_Rela * irel, Elf_Internal_Rela * srel, int delta)
+{
+  bfd_vma old_offset = srel->r_offset;
+
+  irel ++;
+  while (irel <= srel)
+    {
+      if (irel->r_offset == old_offset)
+       irel->r_offset += delta;
+      irel ++;
+    }
+}
+
+/* Relax one section.  */
+
+static bfd_boolean
+elf32_rx_relax_section (bfd *                  abfd,
+                       asection *             sec,
+                       struct bfd_link_info * link_info,
+                       bfd_boolean *          again,
+                       bfd_boolean            allow_pcrel3)
+{
+  Elf_Internal_Shdr * symtab_hdr;
+  Elf_Internal_Shdr * shndx_hdr;
+  Elf_Internal_Rela * internal_relocs;
+  Elf_Internal_Rela * free_relocs = NULL;
+  Elf_Internal_Rela * irel;
+  Elf_Internal_Rela * srel;
+  Elf_Internal_Rela * irelend;
+  Elf_Internal_Rela * next_alignment;
+  Elf_Internal_Rela * prev_alignment;
+  bfd_byte *          contents = NULL;
+  bfd_byte *          free_contents = NULL;
+  Elf_Internal_Sym *  intsyms = NULL;
+  Elf_Internal_Sym *  free_intsyms = NULL;
+  Elf_External_Sym_Shndx * shndx_buf = NULL;
+  bfd_vma pc;
+  bfd_vma sec_start;
+  bfd_vma sec_end;
+  bfd_vma symval = 0;
+  int pcrel = 0;
+  int code = 0;
+  int section_alignment_glue;
+  /* how much to scale the relocation by - 1, 2, or 4.  */
+  int scale;
+
+  /* Assume nothing changes.  */
+  *again = FALSE;
+
+  /* We don't have to do anything for a relocatable link, if
+     this section does not have relocs, or if this is not a
+     code section.  */
+  if (link_info->relocatable
+      || (sec->flags & SEC_RELOC) == 0
+      || sec->reloc_count == 0
+      || (sec->flags & SEC_CODE) == 0)
+    return TRUE;
+
+  symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
+  shndx_hdr = &elf_tdata (abfd)->symtab_shndx_hdr;
+
+  sec_start = sec->output_section->vma + sec->output_offset;
+  sec_end   = sec->output_section->vma + sec->output_offset + sec->size;
+
+  /* Get the section contents.  */
+  if (elf_section_data (sec)->this_hdr.contents != NULL)
+    contents = elf_section_data (sec)->this_hdr.contents;
+  /* Go get them off disk.  */
+  else
+    {
+      if (! bfd_malloc_and_get_section (abfd, sec, &contents))
+       goto error_return;
+      elf_section_data (sec)->this_hdr.contents = contents;
+    }
+
+  /* Read this BFD's symbols.  */
+  /* Get cached copy if it exists.  */
+  if (symtab_hdr->contents != NULL)
+    intsyms = (Elf_Internal_Sym *) symtab_hdr->contents;
+  else
+    {
+      intsyms = bfd_elf_get_elf_syms (abfd, symtab_hdr, symtab_hdr->sh_info, 0, NULL, NULL, NULL);
+      symtab_hdr->contents = (bfd_byte *) intsyms;
+    }
+
+  if (shndx_hdr->sh_size != 0)
+    {
+      bfd_size_type amt;
+
+      amt = symtab_hdr->sh_info;
+      amt *= sizeof (Elf_External_Sym_Shndx);
+      shndx_buf = (Elf_External_Sym_Shndx *) bfd_malloc (amt);
+      if (shndx_buf == NULL)
+       goto error_return;
+      if (bfd_seek (abfd, shndx_hdr->sh_offset, SEEK_SET) != 0
+         || bfd_bread ((PTR) shndx_buf, amt, abfd) != amt)
+       goto error_return;
+      shndx_hdr->contents = (bfd_byte *) shndx_buf;
+    }
+
+  /* Get a copy of the native relocations.  */
+  internal_relocs = (_bfd_elf_link_read_relocs
+                    (abfd, sec, (PTR) NULL, (Elf_Internal_Rela *) NULL,
+                     link_info->keep_memory));
+  if (internal_relocs == NULL)
+    goto error_return;
+  if (! link_info->keep_memory)
+    free_relocs = internal_relocs;
+
+  /* The RL_ relocs must be just before the operand relocs they go
+     with, so we must sort them to guarantee this.  We use bubblesort
+     instead of qsort so we can guarantee that relocs with the same
+     address remain in the same relative order.  */
+  reloc_bubblesort (internal_relocs, sec->reloc_count);
+
+  /* Walk through them looking for relaxing opportunities.  */
+  irelend = internal_relocs + sec->reloc_count;
+
+  /* This will either be NULL or a pointer to the next alignment
+     relocation.  */
+  next_alignment = internal_relocs;
+  /* This will be the previous alignment, although at first it points
+     to the first real relocation.  */
+  prev_alignment = internal_relocs;
+
+  /* We calculate worst case shrinkage caused by alignment directives.
+     No fool-proof, but better than either ignoring the problem or
+     doing heavy duty analysis of all the alignment markers in all
+     input sections.  */
+  section_alignment_glue = 0;
+  for (irel = internal_relocs; irel < irelend; irel++)
+      if (ELF32_R_TYPE (irel->r_info) == R_RX_RH_RELAX
+         && irel->r_addend & RX_RELAXA_ALIGN)
+       {
+         int this_glue = 1 << (irel->r_addend & RX_RELAXA_ANUM);
+
+         if (section_alignment_glue < this_glue)
+           section_alignment_glue = this_glue;
+       }
+  /* Worst case is all 0..N alignments, in order, causing 2*N-1 byte
+     shrinkage.  */
+  section_alignment_glue *= 2;
+
+  for (irel = internal_relocs; irel < irelend; irel++)
+    {
+      unsigned char *insn;
+      int nrelocs;
+
+      /* The insns we care about are all marked with one of these.  */
+      if (ELF32_R_TYPE (irel->r_info) != R_RX_RH_RELAX)
+       continue;
+
+      if (irel->r_addend & RX_RELAXA_ALIGN
+         || next_alignment == internal_relocs)
+       {
+         /* When we delete bytes, we need to maintain all the alignments
+            indicated.  In addition, we need to be careful about relaxing
+            jumps across alignment boundaries - these displacements
+            *grow* when we delete bytes.  For now, don't shrink
+            displacements across an alignment boundary, just in case.
+            Note that this only affects relocations to the same
+            section.  */
+         prev_alignment = next_alignment;
+         next_alignment += 2;
+         while (next_alignment < irelend
+                && (ELF32_R_TYPE (next_alignment->r_info) != R_RX_RH_RELAX
+                    || !(next_alignment->r_addend & RX_RELAXA_ELIGN)))
+           next_alignment ++;
+         if (next_alignment >= irelend || next_alignment->r_offset == 0)
+           next_alignment = NULL;
+       }
+
+      /* When we hit alignment markers, see if we've shrunk enough
+        before them to reduce the gap without violating the alignment
+        requirements.  */
+      if (irel->r_addend & RX_RELAXA_ALIGN)
+       {
+         /* At this point, the next relocation *should* be the ELIGN
+            end marker.  */
+         Elf_Internal_Rela *erel = irel + 1;
+         unsigned int alignment, nbytes;
+
+         if (ELF32_R_TYPE (erel->r_info) != R_RX_RH_RELAX)
+           continue;
+         if (!(erel->r_addend & RX_RELAXA_ELIGN))
+           continue;
+
+         alignment = 1 << (irel->r_addend & RX_RELAXA_ANUM);
+
+         if (erel->r_offset - irel->r_offset < alignment)
+           continue;
+
+         nbytes = erel->r_offset - irel->r_offset;
+         nbytes /= alignment;
+         nbytes *= alignment;
+
+         elf32_rx_relax_delete_bytes (abfd, sec, erel->r_offset-nbytes, nbytes, next_alignment,
+                                      erel->r_offset == sec->size);
+         *again = TRUE;
+
+         continue;
+       }
+
+      if (irel->r_addend & RX_RELAXA_ELIGN)
+         continue;
+
+      insn = contents + irel->r_offset;
+
+      nrelocs = irel->r_addend & RX_RELAXA_RNUM;
+
+      /* At this point, we have an insn that is a candidate for linker
+        relaxation.  There are NRELOCS relocs following that may be
+        relaxed, although each reloc may be made of more than one
+        reloc entry (such as gp-rel symbols).  */
+
+      /* Get the value of the symbol referred to by the reloc.  Just
+         in case this is the last reloc in the list, use the RL's
+         addend to choose between this reloc (no addend) or the next
+         (yes addend, which means at least one following reloc).  */
+
+      /* srel points to the "current" reloction for this insn -
+        actually the last reloc for a given operand, which is the one
+        we need to update.  We check the relaxations in the same
+        order that the relocations happen, so we'll just push it
+        along as we go.  */
+      srel = irel;
+
+      pc = sec->output_section->vma + sec->output_offset
+       + srel->r_offset;
+
+#define GET_RELOC \
+      symval = OFFSET_FOR_RELOC (srel, &srel, &scale); \
+      pcrel = symval - pc + srel->r_addend; \
+      nrelocs --;
+
+#define SNIPNR(offset, nbytes) \
+       elf32_rx_relax_delete_bytes (abfd, sec, (insn - contents) + offset, nbytes, next_alignment, 0);
+#define SNIP(offset, nbytes, newtype) \
+        SNIPNR (offset, nbytes);                                               \
+       srel->r_info = ELF32_R_INFO (ELF32_R_SYM (srel->r_info), newtype)
+
+      /* The order of these bit tests must match the order that the
+        relocs appear in.  Since we sorted those by offset, we can
+        predict them.  */
+
+      /* Note that the numbers in, say, DSP6 are the bit offsets of
+        the code fields that describe the operand.  Bits number 0 for
+        the MSB of insn[0].  */
+
+      /* DSP* codes:
+          0  00  [reg]
+          1  01  dsp:8[reg]
+          2  10  dsp:16[reg]
+          3  11  reg  */
+      if (irel->r_addend & RX_RELAXA_DSP6)
+       {
+         GET_RELOC;
+
+         code = insn[0] & 3;
+         if (code == 2 && symval/scale <= 255)
+           {
+             unsigned int newrel = ELF32_R_TYPE (srel->r_info);
+             insn[0] &= 0xfc;
+             insn[0] |= 0x01;
+             newrel = next_smaller_reloc (ELF32_R_TYPE (srel->r_info));
+             if (newrel != ELF32_R_TYPE (srel->r_info))
+               {
+                 SNIP (3, 1, newrel);
+                 *again = TRUE;
+               }
+           }
+
+         else if (code == 1 && symval == 0)
+           {
+             insn[0] &= 0xfc;
+             SNIP (2, 1, R_RX_NONE);
+             *again = TRUE;
+           }
+
+         /* Special case DSP:5 format: MOV.bwl dsp:5[Rsrc],Rdst.  */
+         else if (code == 1 && symval/scale <= 31
+                  /* Decodable bits.  */
+                  && (insn[0] & 0xcc) == 0xcc
+                  /* width */
+                  && (insn[0] & 0x30) != 3
+                  /* register MSBs */
+                  && (insn[1] & 0x88)  == 0x00)
+           {
+             int newrel = 0;
+
+             insn[0] = 0x88 | (insn[0] & 0x30);
+             /* The register fields are in the right place already.  */
+
+             /* We can't relax this new opcode.  */
+             irel->r_addend = 0;
+
+             switch ((insn[0] & 0x30) >> 4)
+               {
+               case 0:
+                 newrel = R_RX_RH_ABS5p5B;
+                 break;
+               case 1:
+                 newrel = R_RX_RH_ABS5p5W;
+                 break;
+               case 2:
+                 newrel = R_RX_RH_ABS5p5L;
+                 break;
+               }
+
+             move_reloc (irel, srel, -2);
+             SNIP (2, 1, newrel);
+           }
+
+         /* Special case DSP:5 format: MOVU.bw dsp:5[Rsrc],Rdst.  */
+         else if (code == 1 && symval/scale <= 31
+                  /* Decodable bits.  */
+                  && (insn[0] & 0xf8) == 0x58
+                  /* Register MSBs.  */
+                  && (insn[1] & 0x88)  == 0x00)
+           {
+             int newrel = 0;
+
+             insn[0] = 0xb0 | ((insn[0] & 0x04) << 1);
+             /* The register fields are in the right place already.  */
+
+             /* We can't relax this new opcode.  */
+             irel->r_addend = 0;
+
+             switch ((insn[0] & 0x08) >> 3)
+               {
+               case 0:
+                 newrel = R_RX_RH_ABS5p5B;
+                 break;
+               case 1:
+                 newrel = R_RX_RH_ABS5p5W;
+                 break;
+               }
+
+             move_reloc (irel, srel, -2);
+             SNIP (2, 1, newrel);
+           }
+       }
+
+      /* A DSP4 operand always follows a DSP6 operand, even if there's
+        no relocation for it.  We have to read the code out of the
+        opcode to calculate the offset of the operand.  */
+      if (irel->r_addend & RX_RELAXA_DSP4)
+       {
+         int code6, offset = 0;
+
+         GET_RELOC;
+
+         code6 = insn[0] & 0x03;
+         switch (code6)
+           {
+           case 0: offset = 2; break;
+           case 1: offset = 3; break;
+           case 2: offset = 4; break;
+           case 3: offset = 2; break;
+           }
+
+         code = (insn[0] & 0x0c) >> 2;
+
+         if (code == 2 && symval / scale <= 255)
+           {
+             unsigned int newrel = ELF32_R_TYPE (srel->r_info);
+
+             insn[0] &= 0xf3;
+             insn[0] |= 0x04;
+             newrel = next_smaller_reloc (ELF32_R_TYPE (srel->r_info));
+             if (newrel != ELF32_R_TYPE (srel->r_info))
+               {
+                 SNIP (offset+1, 1, newrel);
+                 *again = TRUE;
+               }
+           }
+
+         else if (code == 1 && symval == 0)
+           {
+             insn[0] &= 0xf3;
+             SNIP (offset, 1, R_RX_NONE);
+             *again = TRUE;
+           }
+         /* Special case DSP:5 format: MOV.bwl Rsrc,dsp:5[Rdst] */
+         else if (code == 1 && symval/scale <= 31
+                  /* Decodable bits.  */
+                  && (insn[0] & 0xc3) == 0xc3
+                  /* Width.  */
+                  && (insn[0] & 0x30) != 3
+                  /* Register MSBs.  */
+                  && (insn[1] & 0x88)  == 0x00)
+           {
+             int newrel = 0;
+
+             insn[0] = 0x80 | (insn[0] & 0x30);
+             /* The register fields are in the right place already.  */
+
+             /* We can't relax this new opcode.  */
+             irel->r_addend = 0;
+
+             switch ((insn[0] & 0x30) >> 4)
+               {
+               case 0:
+                 newrel = R_RX_RH_ABS5p5B;
+                 break;
+               case 1:
+                 newrel = R_RX_RH_ABS5p5W;
+                 break;
+               case 2:
+                 newrel = R_RX_RH_ABS5p5L;
+                 break;
+               }
+
+             move_reloc (irel, srel, -2);
+             SNIP (2, 1, newrel);
+           }
+       }
+
+      /* These always occur alone, but the offset depends on whether
+        it's a MEMEX opcode (0x06) or not.  */
+      if (irel->r_addend & RX_RELAXA_DSP14)
+       {
+         int offset;
+         GET_RELOC;
+
+         if (insn[0] == 0x06)
+           offset = 3;
+         else
+           offset = 4;
+
+         code = insn[1] & 3;
+
+         if (code == 2 && symval / scale <= 255)
+           {
+             unsigned int newrel = ELF32_R_TYPE (srel->r_info);
+
+             insn[1] &= 0xfc;
+             insn[1] |= 0x01;
+             newrel = next_smaller_reloc (ELF32_R_TYPE (srel->r_info));
+             if (newrel != ELF32_R_TYPE (srel->r_info))
+               {
+                 SNIP (offset, 1, newrel);
+                 *again = TRUE;
+               }
+           }
+         else if (code == 1 && symval == 0)
+           {
+             insn[1] &= 0xfc;
+             SNIP (offset, 1, R_RX_NONE);
+             *again = TRUE;
+           }
+       }
+
+      /* IMM* codes:
+          0  00  imm:32
+          1  01  simm:8
+          2  10  simm:16
+          3  11  simm:24.  */
+
+      /* These always occur alone.  */
+      if (irel->r_addend & RX_RELAXA_IMM6)
+       {
+         long ssymval;
+
+         GET_RELOC;
+
+         /* These relocations sign-extend, so we must do signed compares.  */
+         ssymval = (long) symval;
+
+         code = insn[0] & 0x03;
+
+         if (code == 0 && ssymval <= 8388607 && ssymval >= -8388608)
+           {
+             unsigned int newrel = ELF32_R_TYPE (srel->r_info);
+
+             insn[0] &= 0xfc;
+             insn[0] |= 0x03;
+             newrel = next_smaller_reloc (ELF32_R_TYPE (srel->r_info));
+             if (newrel != ELF32_R_TYPE (srel->r_info))
+               {
+                 SNIP (2, 1, newrel);
+                 *again = TRUE;
+               }
+           }
+
+         else if (code == 3 && ssymval <= 32767 && ssymval >= -32768)
+           {
+             unsigned int newrel = ELF32_R_TYPE (srel->r_info);
+
+             insn[0] &= 0xfc;
+             insn[0] |= 0x02;
+             newrel = next_smaller_reloc (ELF32_R_TYPE (srel->r_info));
+             if (newrel != ELF32_R_TYPE (srel->r_info))
+               {
+                 SNIP (2, 1, newrel);
+                 *again = TRUE;
+               }
+           }
+
+         /* Special case UIMM8 format: CMP #uimm8,Rdst.  */
+         else if (code == 2 && ssymval <= 255 && ssymval >= 16
+                  /* Decodable bits.  */
+                  && (insn[0] & 0xfc) == 0x74
+                  /* Decodable bits.  */
+                  && ((insn[1] & 0xf0) == 0x00))
+           {
+             int newrel;
+
+             insn[0] = 0x75;
+             insn[1] = 0x50 | (insn[1] & 0x0f);
+
+             /* We can't relax this new opcode.  */
+             irel->r_addend = 0;
+
+             if (STACK_REL_P (ELF32_R_TYPE (srel->r_info)))
+               newrel = R_RX_ABS8U;
+             else
+               newrel = R_RX_DIR8U;
+
+             SNIP (2, 1, newrel);
+             *again = TRUE;
+           }
+
+         else if (code == 2 && ssymval <= 127 && ssymval >= -128)
+           {
+             unsigned int newrel = ELF32_R_TYPE (srel->r_info);
+
+             insn[0] &= 0xfc;
+             insn[0] |= 0x01;
+             newrel = next_smaller_reloc (ELF32_R_TYPE (srel->r_info));
+             if (newrel != ELF32_R_TYPE (srel->r_info))
+               {
+                 SNIP (2, 1, newrel);
+                 *again = TRUE;
+               }
+           }
+
+         /* Special case UIMM4 format: CMP, MUL, AND, OR.  */
+         else if (code == 1 && ssymval <= 15 && ssymval >= 0
+                  /* Decodable bits and immediate type.  */
+                  && insn[0] == 0x75
+                  /* Decodable bits.  */
+                  && (insn[1] & 0xc0)  == 0x00)
+           {
+             static const int newop[4] = { 1, 3, 4, 5 };
+
+             insn[0] = 0x60 | newop[insn[1] >> 4];
+             /* The register number doesn't move.  */
+
+             /* We can't relax this new opcode.  */
+             irel->r_addend = 0;
+
+             move_reloc (irel, srel, -1);
+
+             SNIP (2, 1, R_RX_RH_UIMM4p8);
+             *again = TRUE;
+           }
+
+         /* Special case UIMM4 format: ADD -> ADD/SUB.  */
+         else if (code == 1 && ssymval <= 15 && ssymval >= -15
+                  /* Decodable bits and immediate type.  */
+                  && insn[0] == 0x71
+                  /* Same register for source and destination.  */
+                  && ((insn[1] >> 4) == (insn[1] & 0x0f)))
+           {
+             int newrel;
+
+             /* Note that we can't turn "add $0,Rs" into a NOP
+                because the flags need to be set right.  */
+
+             if (ssymval < 0)
+               {
+                 insn[0] = 0x60; /* Subtract.  */
+                 newrel = R_RX_RH_UNEG4p8;
+               }
+             else
+               {
+                 insn[0] = 0x62; /* Add.  */
+                 newrel = R_RX_RH_UIMM4p8;
+               }
+
+             /* The register number is in the right place.  */
+
+             /* We can't relax this new opcode.  */
+             irel->r_addend = 0;
+
+             move_reloc (irel, srel, -1);
+
+             SNIP (2, 1, newrel);
+             *again = TRUE;
+           }
+       }
+
+      /* These are either matched with a DSP6 (2-byte base) or an id24
+        (3-byte base).  */
+      if (irel->r_addend & RX_RELAXA_IMM12)
+       {
+         int dspcode, offset = 0;
+         long ssymval;
+
+         GET_RELOC;
+
+         if ((insn[0] & 0xfc) == 0xfc)
+           dspcode = 1; /* Just something with one byte operand.  */
+         else
+           dspcode = insn[0] & 3;
+         switch (dspcode)
+           {
+           case 0: offset = 2; break;
+           case 1: offset = 3; break;
+           case 2: offset = 4; break;
+           case 3: offset = 2; break;
+           }
+
+         /* These relocations sign-extend, so we must do signed compares.  */
+         ssymval = (long) symval;
+
+         code = (insn[1] >> 2) & 3;
+         if (code == 0 && ssymval <= 8388607 && ssymval >= -8388608)
+           {
+             unsigned int newrel = ELF32_R_TYPE (srel->r_info);
+
+             insn[1] &= 0xf3;
+             insn[1] |= 0x0c;
+             newrel = next_smaller_reloc (ELF32_R_TYPE (srel->r_info));
+             if (newrel != ELF32_R_TYPE (srel->r_info))
+               {
+                 SNIP (offset, 1, newrel);
+                 *again = TRUE;
+               }
+           }
+
+         else if (code == 3 && ssymval <= 32767 && ssymval >= -32768)
+           {
+             unsigned int newrel = ELF32_R_TYPE (srel->r_info);
+
+             insn[1] &= 0xf3;
+             insn[1] |= 0x08;
+             newrel = next_smaller_reloc (ELF32_R_TYPE (srel->r_info));
+             if (newrel != ELF32_R_TYPE (srel->r_info))
+               {
+                 SNIP (offset, 1, newrel);
+                 *again = TRUE;
+               }
+           }
+
+         /* Special case UIMM8 format: MOV #uimm8,Rdst.  */
+         else if (code == 2 && ssymval <= 255 && ssymval >= 16
+                  /* Decodable bits.  */
+                  && insn[0] == 0xfb
+                  /* Decodable bits.  */
+                  && ((insn[1] & 0x03) == 0x02))
+           {
+             int newrel;
+
+             insn[0] = 0x75;
+             insn[1] = 0x40 | (insn[1] >> 4);
+
+             /* We can't relax this new opcode.  */
+             irel->r_addend = 0;
+
+             if (STACK_REL_P (ELF32_R_TYPE (srel->r_info)))
+               newrel = R_RX_ABS8U;
+             else
+               newrel = R_RX_DIR8U;
+
+             SNIP (2, 1, newrel);
+             *again = TRUE;
+           }
+
+         else if (code == 2 && ssymval <= 127 && ssymval >= -128)
+           {
+             unsigned int newrel = ELF32_R_TYPE(srel->r_info);
+
+             insn[1] &= 0xf3;
+             insn[1] |= 0x04;
+             newrel = next_smaller_reloc (ELF32_R_TYPE (srel->r_info));
+             if (newrel != ELF32_R_TYPE(srel->r_info))
+               {
+                 SNIP (offset, 1, newrel);
+                 *again = TRUE;
+               }
+           }
+
+         /* Special case UIMM4 format: MOV #uimm4,Rdst.  */
+         else if (code == 1 && ssymval <= 15 && ssymval >= 0
+                  /* Decodable bits.  */
+                  && insn[0] == 0xfb
+                  /* Decodable bits.  */
+                  && ((insn[1] & 0x03) == 0x02))
+           {
+             insn[0] = 0x66;
+             insn[1] = insn[1] >> 4;
+
+             /* We can't relax this new opcode.  */
+             irel->r_addend = 0;
+
+             move_reloc (irel, srel, -1);
+
+             SNIP (2, 1, R_RX_RH_UIMM4p8);
+             *again = TRUE;
+           }
+       }
+
+      if (irel->r_addend & RX_RELAXA_BRA)
+       {
+         unsigned int newrel = ELF32_R_TYPE (srel->r_info);
+         int max_pcrel3 = 4;
+         int alignment_glue = 0;
+
+         GET_RELOC;
+
+         /* Branches over alignment chunks are problematic, as
+            deleting bytes here makes the branch *further* away.  We
+            can be agressive with branches within this alignment
+            block, but not branches outside it.  */
+         if ((prev_alignment == NULL
+              || symval < (bfd_vma)(sec_start + prev_alignment->r_offset))
+             && (next_alignment == NULL
+                 || symval > (bfd_vma)(sec_start + next_alignment->r_offset)))
+           alignment_glue = section_alignment_glue;
+
+         if (ELF32_R_TYPE(srel[1].r_info) == R_RX_RH_RELAX
+             && srel[1].r_addend & RX_RELAXA_BRA
+             && srel[1].r_offset < irel->r_offset + pcrel)
+           max_pcrel3 ++;
+
+         newrel = next_smaller_reloc (ELF32_R_TYPE (srel->r_info));
+
+         /* The values we compare PCREL with are not what you'd
+            expect; they're off by a little to compensate for (1)
+            where the reloc is relative to the insn, and (2) how much
+            the insn is going to change when we relax it.  */
+
+         /* These we have to decode.  */
+         switch (insn[0])
+           {
+           case 0x04: /* BRA pcdsp:24 */
+             if (-32768 + alignment_glue <= pcrel
+                 && pcrel <= 32765 - alignment_glue)
+               {
+                 insn[0] = 0x38;
+                 SNIP (3, 1, newrel);
+                 *again = TRUE;
+               }
+             break;
+
+           case 0x38: /* BRA pcdsp:16 */
+             if (-128 + alignment_glue <= pcrel
+                 && pcrel <= 127 - alignment_glue)
+               {
+                 insn[0] = 0x2e;
+                 SNIP (2, 1, newrel);
+                 *again = TRUE;
+               }
+             break;
+
+           case 0x2e: /* BRA pcdsp:8 */
+             /* Note that there's a risk here of shortening things so
+                much that we no longer fit this reloc; it *should*
+                only happen when you branch across a branch, and that
+                branch also devolves into BRA.S.  "Real" code should
+                be OK.  */
+             if (max_pcrel3 + alignment_glue <= pcrel
+                 && pcrel <= 10 - alignment_glue
+                 && allow_pcrel3)
+               {
+                 insn[0] = 0x08;
+                 SNIP (1, 1, newrel);
+                 move_reloc (irel, srel, -1);
+                 *again = TRUE;
+               }
+             break;
+
+           case 0x05: /* BSR pcdsp:24 */
+             if (-32768 + alignment_glue <= pcrel
+                 && pcrel <= 32765 - alignment_glue)
+               {
+                 insn[0] = 0x39;
+                 SNIP (1, 1, newrel);
+                 *again = TRUE;
+               }
+             break;
+
+           case 0x3a: /* BEQ.W pcdsp:16 */
+           case 0x3b: /* BNE.W pcdsp:16 */
+             if (-128 + alignment_glue <= pcrel
+                 && pcrel <= 127 - alignment_glue)
+               {
+                 insn[0] = 0x20 | (insn[0] & 1);
+                 SNIP (1, 1, newrel);
+                 *again = TRUE;
+               }
+             break;
+
+           case 0x20: /* BEQ.B pcdsp:8 */
+           case 0x21: /* BNE.B pcdsp:8 */
+             if (max_pcrel3 + alignment_glue <= pcrel
+                 && pcrel - alignment_glue <= 10
+                 && allow_pcrel3)
+               {
+                 insn[0] = 0x10 | ((insn[0] & 1) << 3);
+                 SNIP (1, 1, newrel);
+                 move_reloc (irel, srel, -1);
+                 *again = TRUE;
+               }
+             break;
+
+           case 0x16: /* synthetic BNE dsp24 */
+           case 0x1e: /* synthetic BEQ dsp24 */
+             if (-32767 + alignment_glue <= pcrel
+                 && pcrel <= 32766 - alignment_glue
+                 && insn[1] == 0x04)
+               {
+                 if (insn[0] == 0x16)
+                   insn[0] = 0x3b;
+                 else
+                   insn[0] = 0x3a;
+                 /* We snip out the bytes at the end else the reloc
+                    will get moved too, and too much.  */
+                 SNIP (3, 2, newrel);
+                 move_reloc (irel, srel, -1);
+                 *again = TRUE;
+               }
+             break;
+           }
+
+         /* Special case - synthetic conditional branches, pcrel24.
+            Note that EQ and NE have been handled above.  */
+         if ((insn[0] & 0xf0) == 0x20
+             && insn[1] == 0x06
+             && insn[2] == 0x04
+             && srel->r_offset != irel->r_offset + 1
+             && -32767 + alignment_glue <= pcrel
+             && pcrel <= 32766 - alignment_glue)
+           {
+             insn[1] = 0x05;
+             insn[2] = 0x38;
+             SNIP (5, 1, newrel);
+             *again = TRUE;
+           }
+
+         /* Special case - synthetic conditional branches, pcrel16 */
+         if ((insn[0] & 0xf0) == 0x20
+             && insn[1] == 0x05
+             && insn[2] == 0x38
+             && srel->r_offset != irel->r_offset + 1
+             && -127 + alignment_glue <= pcrel
+             && pcrel <= 126 - alignment_glue)
+           {
+             int cond = (insn[0] & 0x0f) ^ 0x01;
+
+             insn[0] = 0x20 | cond;
+             /* By moving the reloc first, we avoid having
+                delete_bytes move it also.  */
+             move_reloc (irel, srel, -2);
+             SNIP (2, 3, newrel);
+             *again = TRUE;
+           }
+       }
+
+      BFD_ASSERT (nrelocs == 0);
+
+      /* Special case - check MOV.bwl #IMM, dsp[reg] and see if we can
+        use MOV.bwl #uimm:8, dsp:5[r7] format.  This is tricky
+        because it may have one or two relocations.  */
+      if ((insn[0] & 0xfc) == 0xf8
+         && (insn[1] & 0x80) == 0x00
+         && (insn[0] & 0x03) != 0x03)
+       {
+         int dcode, icode, reg, ioff, dscale, ilen;
+         bfd_vma disp_val = 0;
+         long imm_val = 0;
+         Elf_Internal_Rela * disp_rel = 0;
+         Elf_Internal_Rela * imm_rel = 0;
+
+         /* Reset this.  */
+         srel = irel;
+
+         dcode = insn[0] & 0x03;
+         icode = (insn[1] >> 2) & 0x03;
+         reg = (insn[1] >> 4) & 0x0f;
+
+         ioff = dcode == 1 ? 3 : dcode == 2 ? 4 : 2;
+
+         /* Figure out what the dispacement is.  */
+         if (dcode == 1 || dcode == 2)
+           {
+             /* There's a displacement.  See if there's a reloc for it.  */
+             if (srel[1].r_offset == irel->r_offset + 2)
+               {
+                 GET_RELOC;
+                 disp_val = symval;
+                 disp_rel = srel;
+               }
+             else
+               {
+                 if (dcode == 1)
+                   disp_val = insn[2];
+                 else
+                   {
+#if RX_OPCODE_BIG_ENDIAN
+                     disp_val = insn[2] * 256 + insn[3];
+#else
+                     disp_val = insn[2] + insn[3] * 256;
+#endif
+                   }
+                 switch (insn[1] & 3)
+                   {
+                   case 1:
+                     disp_val *= 2;
+                     scale = 2;
+                     break;
+                   case 2:
+                     disp_val *= 4;
+                     scale = 4;
+                     break;
+                   }
+               }
+           }
+
+         dscale = scale;
+
+         /* Figure out what the immediate is.  */
+         if (srel[1].r_offset == irel->r_offset + ioff)
+           {
+             GET_RELOC;
+             imm_val = (long) symval;
+             imm_rel = srel;
+           }
+         else
+           {
+             unsigned char * ip = insn + ioff;
+
+             switch (icode)
+               {
+               case 1:
+                 /* For byte writes, we don't sign extend.  Makes the math easier later.  */
+                 if (scale == 1)
+                   imm_val = ip[0];
+                 else
+                   imm_val = (char) ip[0];
+                 break;
+               case 2:
+#if RX_OPCODE_BIG_ENDIAN
+                 imm_val = ((char) ip[0] << 8) | ip[1];
+#else
+                 imm_val = ((char) ip[1] << 8) | ip[0];
+#endif
+                 break;
+               case 3:
+#if RX_OPCODE_BIG_ENDIAN
+                 imm_val = ((char) ip[0] << 16) | (ip[1] << 8) | ip[2];
+#else
+                 imm_val = ((char) ip[2] << 16) | (ip[1] << 8) | ip[0];
+#endif
+                 break;
+               case 0:
+#if RX_OPCODE_BIG_ENDIAN
+                 imm_val = (ip[0] << 24) | (ip[1] << 16) | (ip[2] << 8) | ip[3];
+#else
+                 imm_val = (ip[3] << 24) | (ip[2] << 16) | (ip[1] << 8) | ip[0];
+#endif
+                 break;
+               }
+           }
+
+         ilen = 2;
+
+         switch (dcode)
+           {
+           case 1:
+             ilen += 1;
+             break;
+           case 2:
+             ilen += 2;
+             break;
+           }
+
+         switch (icode)
+           {
+           case 1:
+             ilen += 1;
+             break;
+           case 2:
+             ilen += 2;
+             break;
+           case 3:
+             ilen += 3;
+             break;
+           case 4:
+             ilen += 4;
+             break;
+           }
+
+         /* The shortcut happens when the immediate is 0..255,
+            register r0 to r7, and displacement (scaled) 0..31.  */
+
+         if (0 <= imm_val && imm_val <= 255
+             && 0 <= reg && reg <= 7
+             && disp_val / dscale <= 31)
+           {
+             insn[0] = 0x3c | (insn[1] & 0x03);
+             insn[1] = (((disp_val / dscale) << 3) & 0x80) | (reg << 4) | ((disp_val/dscale) & 0x0f);
+             insn[2] = imm_val;
+
+             if (disp_rel)
+               {
+                 int newrel = R_RX_NONE;
+
+                 switch (dscale)
+                   {
+                   case 1:
+                     newrel = R_RX_RH_ABS5p8B;
+                     break;
+                   case 2:
+                     newrel = R_RX_RH_ABS5p8W;
+                     break;
+                   case 4:
+                     newrel = R_RX_RH_ABS5p8L;
+                     break;
+                   }
+                 disp_rel->r_info = ELF32_R_INFO (ELF32_R_SYM (disp_rel->r_info), newrel);
+                 move_reloc (irel, disp_rel, -1);
+               }
+             if (imm_rel)
+               {
+                 imm_rel->r_info = ELF32_R_INFO (ELF32_R_SYM (imm_rel->r_info), R_RX_DIR8U);
+                 move_reloc (disp_rel ? disp_rel : irel,
+                             imm_rel,
+                             irel->r_offset - imm_rel->r_offset + 2);
+               }
+
+             SNIPNR (3, ilen - 3);
+             *again = TRUE;
+
+             /* We can't relax this new opcode.  */
+             irel->r_addend = 0;
+           }
+       }
+    }
+
+  /* We can't reliably relax branches to DIR3U_PCREL unless we know
+     whatever they're branching over won't shrink any more.  If we're
+     basically done here, do one more pass just for branches - but
+     don't request a pass after that one!  */
+  if (!*again && !allow_pcrel3)
+    {
+      bfd_boolean ignored;
+
+      elf32_rx_relax_section (abfd, sec, link_info, &ignored, TRUE);
+    }
+
+  return TRUE;
+
+ error_return:
+  if (free_relocs != NULL)
+    free (free_relocs);
+
+  if (free_contents != NULL)
+    free (free_contents);
+
+  if (shndx_buf != NULL)
+    {
+      shndx_hdr->contents = NULL;
+      free (shndx_buf);
+    }
+
+  if (free_intsyms != NULL)
+    free (free_intsyms);
+
+  return FALSE;
+}
+
+static bfd_boolean
+elf32_rx_relax_section_wrapper (bfd *                  abfd,
+                               asection *             sec,
+                               struct bfd_link_info * link_info,
+                               bfd_boolean *          again)
+{
+  return elf32_rx_relax_section (abfd, sec, link_info, again, FALSE);
+}
+\f
+/* Function to set the ELF flag bits.  */
+
+static bfd_boolean
+rx_elf_set_private_flags (bfd * abfd, flagword flags)
+{
+  elf_elfheader (abfd)->e_flags = flags;
+  elf_flags_init (abfd) = TRUE;
+  return TRUE;
+}
+
+static bfd_boolean no_warn_mismatch = FALSE;
+
+void bfd_elf32_rx_set_target_flags (bfd_boolean);
+
+void
+bfd_elf32_rx_set_target_flags (bfd_boolean user_no_warn_mismatch)
+{
+  no_warn_mismatch = user_no_warn_mismatch;
+}
+
+/* Merge backend specific data from an object file to the output
+   object file when linking.  */
+
+static bfd_boolean
+rx_elf_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
+{
+  flagword old_flags;
+  flagword new_flags;
+  bfd_boolean error = FALSE;
+
+  new_flags = elf_elfheader (ibfd)->e_flags;
+  old_flags = elf_elfheader (obfd)->e_flags;
+
+  if (!elf_flags_init (obfd))
+    {
+      /* First call, no flags set.  */
+      elf_flags_init (obfd) = TRUE;
+      elf_elfheader (obfd)->e_flags = new_flags;
+    }
+  else if (old_flags != new_flags)
+    {
+      flagword known_flags = E_FLAG_RX_64BIT_DOUBLES | E_FLAG_RX_DSP;
+
+      if ((old_flags ^ new_flags) & known_flags)
+       {
+         /* Only complain if flag bits we care about do not match.
+            Other bits may be set, since older binaries did use some
+            deprecated flags.  */
+         if (no_warn_mismatch)
+           {
+             elf_elfheader (obfd)->e_flags = (new_flags | old_flags) & known_flags;
+           }
+         else
+           {
+             (*_bfd_error_handler)
+               ("ELF header flags mismatch: old_flags = 0x%.8lx, new_flags = 0x%.8lx, filename = %s",
+                old_flags, new_flags, bfd_get_filename (ibfd));
+             error = TRUE;
+           }
+       }
+      else
+       elf_elfheader (obfd)->e_flags = new_flags & known_flags;
+    }
+
+  if (error)
+    bfd_set_error (bfd_error_bad_value);
+
+  return !error;
+}
+\f
+static bfd_boolean
+rx_elf_print_private_bfd_data (bfd * abfd, void * ptr)
+{
+  FILE * file = (FILE *) ptr;
+  flagword flags;
+
+  BFD_ASSERT (abfd != NULL && ptr != NULL);
+
+  /* Print normal ELF private data.  */
+  _bfd_elf_print_private_bfd_data (abfd, ptr);
+
+  flags = elf_elfheader (abfd)->e_flags;
+  fprintf (file, _("private flags = 0x%lx:"), (long) flags);
+
+  if (flags & E_FLAG_RX_64BIT_DOUBLES)
+    fprintf (file, _(" [64-bit doubles]"));
+  if (flags & E_FLAG_RX_DSP)
+    fprintf (file, _(" [dsp]"));
+
+  fputc ('\n', file);
+  return TRUE;
+}
+
+/* Return the MACH for an e_flags value.  */
+
+static int
+elf32_rx_machine (bfd * abfd)
+{
+  if ((elf_elfheader (abfd)->e_flags & EF_RX_CPU_MASK) == EF_RX_CPU_RX)
+    return bfd_mach_rx;
+
+  return 0;
+}
+
+static bfd_boolean
+rx_elf_object_p (bfd * abfd)
+{
+  bfd_default_set_arch_mach (abfd, bfd_arch_rx,
+                            elf32_rx_machine (abfd));
+  return TRUE;
+}
+ \f
+
+#ifdef DEBUG
+void
+dump_symtab (bfd * abfd, void * internal_syms, void * external_syms)
+{
+  size_t locsymcount;
+  Elf_Internal_Sym * isymbuf;
+  Elf_Internal_Sym * isymend;
+  Elf_Internal_Sym * isym;
+  Elf_Internal_Shdr * symtab_hdr;
+  bfd_boolean free_internal = FALSE, free_external = FALSE;
+  char * st_info_str;
+  char * st_info_stb_str;
+  char * st_other_str;
+  char * st_shndx_str;
+
+  if (! internal_syms)
+    {
+      internal_syms = bfd_malloc (1000);
+      free_internal = 1;
+    }
+  if (! external_syms)
+    {
+      external_syms = bfd_malloc (1000);
+      free_external = 1;
+    }
+
+  symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
+  locsymcount = symtab_hdr->sh_size / get_elf_backend_data (abfd)->s->sizeof_sym;
+  if (free_internal)
+    isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr,
+                                   symtab_hdr->sh_info, 0,
+                                   internal_syms, external_syms, NULL);
+  else
+    isymbuf = internal_syms;
+  isymend = isymbuf + locsymcount;
+
+  for (isym = isymbuf ; isym < isymend ; isym++)
+    {
+      switch (ELF_ST_TYPE (isym->st_info))
+       {
+       case STT_FUNC: st_info_str = "STT_FUNC";
+       case STT_SECTION: st_info_str = "STT_SECTION";
+       case STT_FILE: st_info_str = "STT_FILE";
+       case STT_OBJECT: st_info_str = "STT_OBJECT";
+       case STT_TLS: st_info_str = "STT_TLS";
+       default: st_info_str = "";
+       }
+      switch (ELF_ST_BIND (isym->st_info))
+       {
+       case STB_LOCAL: st_info_stb_str = "STB_LOCAL";
+       case STB_GLOBAL: st_info_stb_str = "STB_GLOBAL";
+       default: st_info_stb_str = "";
+       }
+      switch (ELF_ST_VISIBILITY (isym->st_other))
+       {
+       case STV_DEFAULT: st_other_str = "STV_DEFAULT";
+       case STV_INTERNAL: st_other_str = "STV_INTERNAL";
+       case STV_PROTECTED: st_other_str = "STV_PROTECTED";
+       default: st_other_str = "";
+       }
+      switch (isym->st_shndx)
+       {
+       case SHN_ABS: st_shndx_str = "SHN_ABS";
+       case SHN_COMMON: st_shndx_str = "SHN_COMMON";
+       case SHN_UNDEF: st_shndx_str = "SHN_UNDEF";
+       default: st_shndx_str = "";
+       }
+
+      printf ("isym = %p st_value = %lx st_size = %lx st_name = (%lu) %s "
+             "st_info = (%d) %s %s st_other = (%d) %s st_shndx = (%d) %s\n",
+             isym,
+             (unsigned long) isym->st_value,
+             (unsigned long) isym->st_size,
+             isym->st_name,
+             bfd_elf_string_from_elf_section (abfd, symtab_hdr->sh_link,
+                                              isym->st_name),
+             isym->st_info, st_info_str, st_info_stb_str,
+             isym->st_other, st_other_str,
+             isym->st_shndx, st_shndx_str);
+    }
+  if (free_internal)
+    free (internal_syms);
+  if (free_external)
+    free (external_syms);
+}
+
+char *
+rx_get_reloc (long reloc)
+{
+  if (0 <= reloc && reloc < R_RX_max)
+    return rx_elf_howto_table[reloc].name;
+  return "";
+}
+#endif /* DEBUG */
+
+\f
+/* We must take care to keep the on-disk copy of any code sections
+   that are fully linked swapped if the target is big endian, to match
+   the Renesas tools.  */
+
+/* The rule is: big endian object that are final-link executables,
+   have code sections stored with 32-bit words swapped relative to
+   what you'd get by default.  */
+
+static bfd_boolean
+rx_get_section_contents (bfd *         abfd,
+                        sec_ptr       section,
+                        void *        location,
+                        file_ptr      offset,
+                        bfd_size_type count)
+{
+  int exec = (abfd->flags & EXEC_P) ? 1 : 0;
+  int s_code = (section->flags & SEC_CODE) ? 1 : 0;
+  bfd_boolean rv;
+
+#ifdef DJDEBUG
+  fprintf (stderr, "dj: get %ld %ld from %s  %s e%d sc%d  %08lx:%08lx\n",
+          (long) offset, (long) count, section->name,
+          bfd_big_endian(abfd) ? "be" : "le",
+          exec, s_code, (long unsigned) section->filepos,
+          (long unsigned) offset);
+#endif
+
+  if (exec && s_code && bfd_big_endian (abfd))
+    {
+      char * cloc = (char *) location;
+      bfd_size_type cnt, end_cnt;
+
+      rv = TRUE;
+
+      /* Fetch and swap unaligned bytes at the beginning.  */
+      if (offset % 4)
+        {
+         char buf[4];
+
+         rv = _bfd_generic_get_section_contents (abfd, section, buf,
+                                                 (offset & -4), 4);
+         if (!rv)
+           return FALSE;
+
+         bfd_putb32 (bfd_getl32 (buf), buf);
+
+         cnt = 4 - (offset % 4);
+         if (cnt > count)
+           cnt = count;
+
+         memcpy (location, buf + (offset % 4), cnt);
+
+         count -= cnt;
+         offset += cnt;
+         cloc += count;
+       }
+
+      end_cnt = count % 4;
+
+      /* Fetch and swap the middle bytes.  */
+      if (count >= 4)
+       {
+         rv = _bfd_generic_get_section_contents (abfd, section, cloc, offset,
+                                                 count - end_cnt);
+         if (!rv)
+           return FALSE;
+
+         for (cnt = count; cnt >= 4; cnt -= 4, cloc += 4)
+           bfd_putb32 (bfd_getl32 (cloc), cloc);
+       }
+
+      /* Fetch and swap the end bytes.  */
+      if (end_cnt > 0)
+       {
+         char buf[4];
+
+         /* Fetch the end bytes.  */
+         rv = _bfd_generic_get_section_contents (abfd, section, buf,
+                                                 offset + count - end_cnt, 4);
+         if (!rv)
+           return FALSE;
+
+         bfd_putb32 (bfd_getl32 (buf), buf);
+         memcpy (cloc, buf, end_cnt);
+       }
+    }
+  else
+    rv = _bfd_generic_get_section_contents (abfd, section, location, offset, count);
+
+  return rv;
+}
+
+#ifdef DJDEBUG
+static bfd_boolean
+rx2_set_section_contents (bfd *        abfd,
+                        sec_ptr       section,
+                        const void *  location,
+                        file_ptr      offset,
+                        bfd_size_type count)
+{
+  bfd_size_type i;
+
+  fprintf (stderr, "   set sec %s %08x loc %p offset %#x count %#x\n",
+          section->name, (unsigned) section->vma, location, (int) offset, (int) count);
+  for (i = 0; i < count; i++)
+    {
+      if (i % 16 == 0 && i > 0)
+       fprintf (stderr, "\n");
+
+      if (i % 16  && i % 4 == 0)
+       fprintf (stderr, " ");
+
+      if (i % 16 == 0)
+       fprintf (stderr, "      %08x:", (int) (section->vma + offset + i));
+
+      fprintf (stderr, " %02x", ((unsigned char *) location)[i]);
+    }
+  fprintf (stderr, "\n");
+
+  return _bfd_elf_set_section_contents (abfd, section, location, offset, count);
+}
+#define _bfd_elf_set_section_contents rx2_set_section_contents
+#endif
+
+static bfd_boolean
+rx_set_section_contents (bfd *         abfd,
+                        sec_ptr       section,
+                        const void *  location,
+                        file_ptr      offset,
+                        bfd_size_type count)
+{
+  bfd_boolean exec = (abfd->flags & EXEC_P) ? TRUE : FALSE;
+  bfd_boolean s_code = (section->flags & SEC_CODE) ? TRUE : FALSE;
+  bfd_boolean rv;
+  char * swapped_data = NULL;
+  bfd_size_type i;
+  bfd_vma caddr = section->vma + offset;
+  file_ptr faddr = 0;
+  bfd_size_type scount;
+
+#ifdef DJDEBUG
+  bfd_size_type i;
+
+  fprintf (stderr, "\ndj: set %ld %ld to %s  %s e%d sc%d\n",
+          (long) offset, (long) count, section->name,
+          bfd_big_endian (abfd) ? "be" : "le",
+          exec, s_code);
+
+  for (i = 0; i < count; i++)
+    {
+      int a = section->vma + offset + i;
+
+      if (a % 16 == 0 && a > 0)
+       fprintf (stderr, "\n");
+
+      if (a % 16  && a % 4 == 0)
+       fprintf (stderr, " ");
+
+      if (a % 16 == 0 || i == 0)
+       fprintf (stderr, "      %08x:", (int) (section->vma + offset + i));
+
+      fprintf (stderr, " %02x", ((unsigned char *) location)[i]);
+    }
+
+  fprintf (stderr, "\n");
+#endif
+
+  if (! exec || ! s_code || ! bfd_big_endian (abfd))
+    return _bfd_elf_set_section_contents (abfd, section, location, offset, count);
+
+  while (count > 0 && caddr > 0 && caddr % 4)
+    {
+      switch (caddr % 4)
+       {
+       case 0: faddr = offset + 3; break;
+       case 1: faddr = offset + 1; break;
+       case 2: faddr = offset - 1; break;
+       case 3: faddr = offset - 3; break;
+       }
+
+      rv = _bfd_elf_set_section_contents (abfd, section, location, faddr, 1);
+      if (! rv)
+       return rv;
+
+      location ++;
+      offset ++;
+      count --;
+      caddr ++;
+    }
+
+  scount = (int)(count / 4) * 4;
+  if (scount > 0)
+    {
+      char * cloc = (char *) location;
+
+      swapped_data = (char *) bfd_alloc (abfd, count);
+
+      for (i = 0; i < count; i += 4)
+       {
+         bfd_vma v = bfd_getl32 (cloc + i);
+         bfd_putb32 (v, swapped_data + i);
+       }
+
+      rv = _bfd_elf_set_section_contents (abfd, section, swapped_data, offset, scount);
+
+      if (!rv)
+       return rv;
+    }
+
+  count -= scount;
+  location += scount;
+  offset += scount;
+
+  if (count > 0)
+    {
+      caddr = section->vma + offset;
+      while (count > 0)
+       {
+         switch (caddr % 4)
+           {
+           case 0: faddr = offset + 3; break;
+           case 1: faddr = offset + 1; break;
+           case 2: faddr = offset - 1; break;
+           case 3: faddr = offset - 3; break;
+           }
+         rv = _bfd_elf_set_section_contents (abfd, section, location, faddr, 1);
+         if (! rv)
+           return rv;
+
+         location ++;
+         offset ++;
+         count --;
+         caddr ++;
+       }
+    }
+
+  return TRUE;
+}
+
+static bfd_boolean
+rx_final_link (bfd * abfd, struct bfd_link_info * info)
+{
+  asection * o;
+
+  for (o = abfd->sections; o != NULL; o = o->next)
+    {
+#ifdef DJDEBUG
+      fprintf (stderr, "sec %s fl %x vma %lx lma %lx size %lx raw %lx\n",
+              o->name, o->flags, o->vma, o->lma, o->size, o->rawsize);
+#endif
+      if (o->flags & SEC_CODE
+         && bfd_big_endian (abfd)
+         && (o->size % 4 || o->rawsize % 4))
+       {
+#ifdef DJDEBUG
+         fprintf (stderr, "adjusting...\n");
+#endif
+         o->size += 4 - (o->size % 4);
+         o->rawsize += 4 - (o->rawsize % 4);
+       }
+    }
+
+  return bfd_elf_final_link (abfd, info);
+}
+
+static bfd_boolean
+elf32_rx_modify_program_headers (bfd * abfd ATTRIBUTE_UNUSED,
+                                struct bfd_link_info * info ATTRIBUTE_UNUSED)
+{
+  const struct elf_backend_data * bed;
+  struct elf_obj_tdata * tdata;
+  Elf_Internal_Phdr * phdr;
+  unsigned int count;
+  unsigned int i;
+
+  bed = get_elf_backend_data (abfd);
+  tdata = elf_tdata (abfd);
+  phdr = tdata->phdr;
+  count = tdata->program_header_size / bed->s->sizeof_phdr;
+
+  for (i = count; i-- != 0; )
+    if (phdr[i].p_type == PT_LOAD)
+      {
+       /* The Renesas tools expect p_paddr to be zero.  However,
+          there is no other way to store the writable data in ROM for
+          startup initialization.  So, we let the linker *think*
+          we're using paddr and vaddr the "usual" way, but at the
+          last minute we move the paddr into the vaddr (which is what
+          the simulator uses) and zero out paddr.  Note that this
+          does not affect the section headers, just the program
+          headers.  We hope.  */
+         phdr[i].p_vaddr = phdr[i].p_paddr;
+         /* If we zero out p_paddr, then the LMA in the section table
+            becomes wrong.  */
+         /*phdr[i].p_paddr = 0;*/
+      }
+
+  return TRUE;
+}
+\f
+#define ELF_ARCH               bfd_arch_rx
+#define ELF_MACHINE_CODE       EM_RX
+#define ELF_MAXPAGESIZE                0x1000
+
+#define TARGET_BIG_SYM         bfd_elf32_rx_be_vec
+#define TARGET_BIG_NAME                "elf32-rx-be"
+
+#define TARGET_LITTLE_SYM      bfd_elf32_rx_le_vec
+#define TARGET_LITTLE_NAME     "elf32-rx-le"
+
+#define elf_info_to_howto_rel                  NULL
+#define elf_info_to_howto                      rx_info_to_howto_rela
+#define elf_backend_object_p                   rx_elf_object_p
+#define elf_backend_relocate_section           rx_elf_relocate_section
+#define elf_symbol_leading_char                 ('_')
+#define elf_backend_can_gc_sections            1
+#define elf_backend_modify_program_headers     elf32_rx_modify_program_headers
+
+#define bfd_elf32_bfd_reloc_type_lookup                rx_reloc_type_lookup
+#define bfd_elf32_bfd_reloc_name_lookup                rx_reloc_name_lookup
+#define bfd_elf32_bfd_set_private_flags                rx_elf_set_private_flags
+#define bfd_elf32_bfd_merge_private_bfd_data   rx_elf_merge_private_bfd_data
+#define bfd_elf32_bfd_print_private_bfd_data   rx_elf_print_private_bfd_data
+#define bfd_elf32_get_section_contents         rx_get_section_contents
+#define bfd_elf32_set_section_contents         rx_set_section_contents
+#define bfd_elf32_bfd_final_link               rx_final_link
+#define bfd_elf32_bfd_relax_section            elf32_rx_relax_section_wrapper
+
+#include "elf32-target.h"

diff --git a/bfd/elf32-spu.c b/bfd/elf32-spu.c
index 13d3a53..890f260 100644 (file)
--- a/bfd/elf32-spu.c
+++ b/bfd/elf32-spu.c
@@ -678,9 +678,10 @@ spu_elf_find_overlays (struct bfd_link_info *info)
   ovl_end = alloc_sec[0]->vma + alloc_sec[0]->size;
   if (htab->params->ovly_flavour == ovly_soft_icache)
     {
+      unsigned int prev_buf = 0, set_id = 0;
+
       /* Look for an overlapping vma to find the first overlay section.  */
       bfd_vma vma_start = 0;
-      bfd_vma lma_start = 0;
 
       for (i = 1; i < n; i++)
        {
@@ -689,10 +690,6 @@ spu_elf_find_overlays (struct bfd_link_info *info)
            {
              asection *s0 = alloc_sec[i - 1];
              vma_start = s0->vma;
-             if (strncmp (s0->name, ".ovl.init", 9) != 0)
-               lma_start = s0->lma;
-             else
-               lma_start = s->lma;
              ovl_end = (s0->vma
                         + ((bfd_vma) 1
                            << (htab->num_lines_log2 + htab->line_size_log2)));
@@ -717,8 +714,10 @@ spu_elf_find_overlays (struct bfd_link_info *info)
          if (strncmp (s->name, ".ovl.init", 9) != 0)
            {
              num_buf = ((s->vma - vma_start) >> htab->line_size_log2) + 1;
-             if (((s->vma - vma_start) & (htab->params->line_size - 1))
-                 || ((s->lma - lma_start) & (htab->params->line_size - 1)))
+             set_id = (num_buf == prev_buf)? set_id + 1 : 0;
+             prev_buf = num_buf;
+
+             if ((s->vma - vma_start) & (htab->params->line_size - 1))
                {
                  info->callbacks->einfo (_("%X%P: overlay section %A "
                                            "does not start on a cache line.\n"),
@@ -737,7 +736,7 @@ spu_elf_find_overlays (struct bfd_link_info *info)
 
              alloc_sec[ovl_index++] = s;
              spu_elf_section_data (s)->u.o.ovl_index
-               = ((s->lma - lma_start) >>  htab->line_size_log2) + 1;
+               = (set_id << htab->num_lines_log2) + num_buf;
              spu_elf_section_data (s)->u.o.ovl_buf = num_buf;
            }
        }
@@ -4531,13 +4530,12 @@ spu_elf_auto_overlay (struct bfd_link_info *info)
 
   script = htab->params->spu_elf_open_overlay_script ();
 
-  if (fprintf (script, "SECTIONS\n{\n") <= 0)
-    goto file_err;
-
   if (htab->params->ovly_flavour == ovly_soft_icache)
     {
+      if (fprintf (script, "SECTIONS\n{\n") <= 0)
+       goto file_err;
+
       if (fprintf (script,
-                  " .data.icache ALIGN (16) : { *(.ovtab) *(.data.icache) }\n"
                   " . = ALIGN (%u);\n"
                   " .ovl.init : { *(.ovl.init) }\n"
                   " . = ABSOLUTE (ADDR (.ovl.init));\n",
@@ -4552,10 +4550,10 @@ spu_elf_auto_overlay (struct bfd_link_info *info)
          unsigned int vma, lma;
 
          vma = (indx & (htab->params->num_lines - 1)) << htab->line_size_log2;
-         lma = indx << htab->line_size_log2;
+         lma = vma + (((indx >> htab->num_lines_log2) + 1) << 18);
 
          if (fprintf (script, " .ovly%u ABSOLUTE (ADDR (.ovl.init)) + %u "
-                      ": AT (ALIGN (LOADADDR (.ovl.init) + SIZEOF (.ovl.init), 16) + %u) {\n",
+                              ": AT (LOADADDR (.ovl.init) + %u) {\n",
                       ovlynum, vma, lma) <= 0)
            goto file_err;
 
@@ -4573,9 +4571,15 @@ spu_elf_auto_overlay (struct bfd_link_info *info)
       if (fprintf (script, " . = ABSOLUTE (ADDR (.ovl.init)) + %u;\n",
                   1 << (htab->num_lines_log2 + htab->line_size_log2)) <= 0)
        goto file_err;
+
+      if (fprintf (script, "}\nINSERT AFTER .toe;\n") <= 0)
+       goto file_err;
     }
   else
     {
+      if (fprintf (script, "SECTIONS\n{\n") <= 0)
+       goto file_err;
+
       if (fprintf (script,
                   " . = ALIGN (16);\n"
                   " .ovl.init : { *(.ovl.init) }\n"
@@ -4627,13 +4631,13 @@ spu_elf_auto_overlay (struct bfd_link_info *info)
            goto file_err;
        }
 
+      if (fprintf (script, "}\nINSERT BEFORE .text;\n") <= 0)
+       goto file_err;
     }
 
   free (ovly_map);
   free (ovly_sections);
 
-  if (fprintf (script, "}\nINSERT BEFORE .text;\n") <= 0)
-    goto file_err;
   if (fclose (script) != 0)
     goto file_err;
 

diff --git a/bfd/elf64-alpha.c b/bfd/elf64-alpha.c
index c22b4fd..501e2ef 100644 (file)
--- a/bfd/elf64-alpha.c
+++ b/bfd/elf64-alpha.c
@@ -1,6 +1,6 @@
 /* Alpha specific support for 64-bit ELF
    Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
-   2006, 2007, 2008 Free Software Foundation, Inc.
+   2006, 2007, 2008, 2009  Free Software Foundation, Inc.
    Contributed by Richard Henderson <rth@tamu.edu>.
 
    This file is part of BFD, the Binary File Descriptor library.
@@ -103,6 +103,57 @@ bfd_boolean elf64_alpha_use_secureplt = FALSE;
 
 #define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so"
 \f
+
+/* Used to implement multiple .got subsections.  */
+struct alpha_elf_got_entry
+{
+  struct alpha_elf_got_entry *next;
+
+  /* Which .got subsection?  */
+  bfd *gotobj;
+
+  /* The addend in effect for this entry.  */
+  bfd_vma addend;
+
+  /* The .got offset for this entry.  */
+  int got_offset;
+
+  /* The .plt offset for this entry.  */
+  int plt_offset;
+
+  /* How many references to this entry?  */
+  int use_count;
+
+  /* The relocation type of this entry.  */
+  unsigned char reloc_type;
+
+  /* How a LITERAL is used.  */
+  unsigned char flags;
+
+  /* Have we initialized the dynamic relocation for this entry?  */
+  unsigned char reloc_done;
+
+  /* Have we adjusted this entry for SEC_MERGE?  */
+  unsigned char reloc_xlated;
+};
+
+struct alpha_elf_reloc_entry
+{
+  struct alpha_elf_reloc_entry *next;
+
+  /* Which .reloc section? */
+  asection *srel;
+
+  /* What kind of relocation? */
+  unsigned int rtype;
+
+  /* Is this against read-only section? */
+  unsigned int reltext : 1;
+
+  /* How many did we find?  */
+  unsigned long count;
+};
+
 struct alpha_elf_link_hash_entry
 {
   struct elf_link_hash_entry root;
@@ -125,56 +176,11 @@ struct alpha_elf_link_hash_entry
 #define ALPHA_ELF_LINK_HASH_TLS_IE      0x80
 
   /* Used to implement multiple .got subsections.  */
-  struct alpha_elf_got_entry
-  {
-    struct alpha_elf_got_entry *next;
-
-    /* Which .got subsection?  */
-    bfd *gotobj;
-
-    /* The addend in effect for this entry.  */
-    bfd_vma addend;
-
-    /* The .got offset for this entry.  */
-    int got_offset;
-
-    /* The .plt offset for this entry.  */
-    int plt_offset;
-
-    /* How many references to this entry?  */
-    int use_count;
-
-    /* The relocation type of this entry.  */
-    unsigned char reloc_type;
-
-    /* How a LITERAL is used.  */
-    unsigned char flags;
-
-    /* Have we initialized the dynamic relocation for this entry?  */
-    unsigned char reloc_done;
-
-    /* Have we adjusted this entry for SEC_MERGE?  */
-    unsigned char reloc_xlated;
-  } *got_entries;
+  struct alpha_elf_got_entry *got_entries;
 
   /* Used to count non-got, non-plt relocations for delayed sizing
      of relocation sections.  */
-  struct alpha_elf_reloc_entry
-  {
-    struct alpha_elf_reloc_entry *next;
-
-    /* Which .reloc section? */
-    asection *srel;
-
-    /* What kind of relocation? */
-    unsigned int rtype;
-
-    /* Is this against read-only section? */
-    unsigned int reltext : 1;
-
-    /* How many did we find?  */
-    unsigned long count;
-  } *reloc_entries;
+  struct alpha_elf_reloc_entry *reloc_entries;
 };
 
 /* Alpha ELF linker hash table.  */
@@ -458,8 +464,9 @@ elf64_alpha_reloc_gpdisp (bfd *abfd, arelent *reloc_entry,
    from smaller values.  Start with zero, widen, *then* decrement.  */
 #define MINUS_ONE      (((bfd_vma)0) - 1)
 
+
 #define SKIP_HOWTO(N) \
-  HOWTO(N, 0, 0, 0, 0, 0, 0, elf64_alpha_reloc_bad, 0, 0, 0, 0, 0)
+  HOWTO(N, 0, 0, 0, 0, 0, complain_overflow_dont, elf64_alpha_reloc_bad, 0, 0, 0, 0, 0)
 
 static reloc_howto_type elf64_alpha_howto_table[] =
 {
@@ -5062,7 +5069,7 @@ elf64_alpha_final_link (bfd *abfd, struct bfd_link_info *info)
                 interesting information, try to find the symbol in
                 the linker global hash table and save the information
                 for the output external symbols.  */
-             eraw_src = input_debug.external_ext;
+             eraw_src = (char *) input_debug.external_ext;
              eraw_end = (eraw_src
                          + (input_debug.symbolic_header.iextMax
                             * input_swap->external_ext_size));

diff --git a/bfd/elf64-ppc.c b/bfd/elf64-ppc.c
index f154658..35757b8 100644 (file)
--- a/bfd/elf64-ppc.c
+++ b/bfd/elf64-ppc.c
@@ -3771,6 +3771,9 @@ struct ppc_link_hash_table
   /* Set if we should emit symbols for stubs.  */
   unsigned int emit_stub_syms:1;
 
+  /* Set if __tls_get_addr optimization should not be done.  */
+  unsigned int no_tls_get_addr_opt:1;
+
   /* Support for multiple toc sections.  */
   unsigned int no_multi_toc:1;
   unsigned int multi_toc_needed:1;
@@ -4282,6 +4285,29 @@ ppc64_elf_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
   return TRUE;
 }
 
+/* Follow indirect and warning symbol links.  */
+
+static inline struct bfd_link_hash_entry *
+follow_link (struct bfd_link_hash_entry *h)
+{
+  while (h->type == bfd_link_hash_indirect
+        || h->type == bfd_link_hash_warning)
+    h = h->u.i.link;
+  return h;
+}
+
+static inline struct elf_link_hash_entry *
+elf_follow_link (struct elf_link_hash_entry *h)
+{
+  return (struct elf_link_hash_entry *) follow_link (&h->root);
+}
+
+static inline struct ppc_link_hash_entry *
+ppc_follow_link (struct ppc_link_hash_entry *h)
+{
+  return (struct ppc_link_hash_entry *) follow_link (&h->elf.root);
+}
+
 /* Merge PLT info on FROM with that on TO.  */
 
 static void
@@ -4364,6 +4390,8 @@ ppc64_elf_copy_indirect_symbol (struct bfd_link_info *info,
   edir->is_func |= eind->is_func;
   edir->is_func_descriptor |= eind->is_func_descriptor;
   edir->tls_mask |= eind->tls_mask;
+  if (eind->oh != NULL)
+    edir->oh = ppc_follow_link (eind->oh);
 
   /* If called to transfer flags for a weakdef during processing
      of elf_adjust_dynamic_symbol, don't copy NON_GOT_REF.
@@ -4433,7 +4461,7 @@ ppc64_elf_copy_indirect_symbol (struct bfd_link_info *info,
    hash entry FH.  Link the entries via their OH fields.  */
 
 static struct ppc_link_hash_entry *
-get_fdh (struct ppc_link_hash_entry *fh, struct ppc_link_hash_table *htab)
+lookup_fdh (struct ppc_link_hash_entry *fh, struct ppc_link_hash_table *htab)
 {
   struct ppc_link_hash_entry *fdh = fh->oh;
 
@@ -4443,16 +4471,16 @@ get_fdh (struct ppc_link_hash_entry *fh, struct ppc_link_hash_table *htab)
 
       fdh = (struct ppc_link_hash_entry *)
        elf_link_hash_lookup (&htab->elf, fd_name, FALSE, FALSE, FALSE);
-      if (fdh != NULL)
-       {
-         fdh->is_func_descriptor = 1;
-         fdh->oh = fh;
-         fh->is_func = 1;
-         fh->oh = fdh;
-       }
+      if (fdh == NULL)
+       return fdh;
+
+      fdh->is_func_descriptor = 1;
+      fdh->oh = fh;
+      fh->is_func = 1;
+      fh->oh = fdh;
     }
 
-  return fdh;
+  return ppc_follow_link (fdh);
 }
 
 /* Make a fake function descriptor sym for the code sym FH.  */
@@ -4574,23 +4602,24 @@ add_symbol_adjust (struct ppc_link_hash_entry *eh, struct bfd_link_info *info)
     abort ();
 
   htab = ppc_hash_table (info);
-  fdh = get_fdh (eh, htab);
-  if (fdh == NULL
-      && !info->relocatable
-      && (eh->elf.root.type == bfd_link_hash_undefined
-         || eh->elf.root.type == bfd_link_hash_undefweak)
-      && eh->elf.ref_regular)
-    {
-      /* Make an undefweak function descriptor sym, which is enough to
-        pull in an --as-needed shared lib, but won't cause link
-        errors.  Archives are handled elsewhere.  */
-      fdh = make_fdh (info, eh);
-      if (fdh == NULL)
-       return FALSE;
-      else
-       fdh->elf.ref_regular = 1;
+  fdh = lookup_fdh (eh, htab);
+  if (fdh == NULL)
+    {
+      if (!info->relocatable
+         && (eh->elf.root.type == bfd_link_hash_undefined
+             || eh->elf.root.type == bfd_link_hash_undefweak)
+         && eh->elf.ref_regular)
+       {
+         /* Make an undefweak function descriptor sym, which is enough to
+            pull in an --as-needed shared lib, but won't cause link
+            errors.  Archives are handled elsewhere.  */
+         fdh = make_fdh (info, eh);
+         if (fdh == NULL)
+           return FALSE;
+         fdh->elf.ref_regular = 1;
+       }
     }
-  else if (fdh != NULL)
+  else
     {
       unsigned entry_vis = ELF_ST_VISIBILITY (eh->elf.other) - 1;
       unsigned descr_vis = ELF_ST_VISIBILITY (fdh->elf.other) - 1;
@@ -4839,9 +4868,7 @@ ppc64_elf_check_relocs (bfd *abfd, struct bfd_link_info *info,
       else
        {
          h = sym_hashes[r_symndx - symtab_hdr->sh_info];
-         while (h->root.type == bfd_link_hash_indirect
-                || h->root.type == bfd_link_hash_warning)
-           h = (struct elf_link_hash_entry *) h->root.u.i.link;
+         h = elf_follow_link (h);
        }
 
       tls_type = 0;
@@ -5199,7 +5226,7 @@ ppc64_elf_check_relocs (bfd *abfd, struct bfd_link_info *info,
                {
                  if (h->root.root.string[0] == '.'
                      && h->root.root.string[1] != 0
-                     && get_fdh ((struct ppc_link_hash_entry *) h, htab))
+                     && lookup_fdh ((struct ppc_link_hash_entry *) h, htab))
                    ;
                  else
                    ((struct ppc_link_hash_entry *) h)->is_func = 1;
@@ -5452,9 +5479,7 @@ opd_entry_value (asection *opd_sec,
 
                  sym_hashes = elf_sym_hashes (opd_bfd);
                  rh = sym_hashes[symndx - symtab_hdr->sh_info];
-                 while (rh->root.type == bfd_link_hash_indirect
-                        || rh->root.type == bfd_link_hash_warning)
-                   rh = ((struct elf_link_hash_entry *) rh->root.u.i.link);
+                 rh = elf_follow_link (rh);
                  BFD_ASSERT (rh->root.type == bfd_link_hash_defined
                              || rh->root.type == bfd_link_hash_defweak);
                  val = rh->root.u.def.value;
@@ -5475,6 +5500,39 @@ opd_entry_value (asection *opd_sec,
   return val;
 }
 
+/* If FDH is a function descriptor symbol, return the associated code
+   entry symbol if it is defined.  Return NULL otherwise.  */
+
+static struct ppc_link_hash_entry *
+defined_code_entry (struct ppc_link_hash_entry *fdh)
+{
+  if (fdh->is_func_descriptor)
+    {
+      struct ppc_link_hash_entry *fh = ppc_follow_link (fdh->oh);
+      if (fh->elf.root.type == bfd_link_hash_defined
+         || fh->elf.root.type == bfd_link_hash_defweak)
+       return fh;
+    }
+  return NULL;
+}
+
+/* If FH is a function code entry symbol, return the associated
+   function descriptor symbol if it is defined.  Return NULL otherwise.  */
+
+static struct ppc_link_hash_entry *
+defined_func_desc (struct ppc_link_hash_entry *fh)
+{
+  if (fh->oh != NULL
+      && fh->oh->is_func_descriptor)
+    {
+      struct ppc_link_hash_entry *fdh = ppc_follow_link (fh->oh);
+      if (fdh->elf.root.type == bfd_link_hash_defined
+         || fdh->elf.root.type == bfd_link_hash_defweak)
+       return fdh;
+    }
+  return NULL;
+}
+
 /* Mark all our entry sym sections, both opd and code section.  */
 
 static void
@@ -5485,22 +5543,21 @@ ppc64_elf_gc_keep (struct bfd_link_info *info)
 
   for (sym = info->gc_sym_list; sym != NULL; sym = sym->next)
     {
-      struct ppc_link_hash_entry *eh;
+      struct ppc_link_hash_entry *eh, *fh;
       asection *sec;
 
       eh = (struct ppc_link_hash_entry *)
-       elf_link_hash_lookup (&htab->elf, sym->name, FALSE, FALSE, FALSE);
+       elf_link_hash_lookup (&htab->elf, sym->name, FALSE, FALSE, TRUE);
       if (eh == NULL)
        continue;
       if (eh->elf.root.type != bfd_link_hash_defined
          && eh->elf.root.type != bfd_link_hash_defweak)
        continue;
 
-      if (eh->is_func_descriptor
-         && (eh->oh->elf.root.type == bfd_link_hash_defined
-             || eh->oh->elf.root.type == bfd_link_hash_defweak))
+      fh = defined_code_entry (eh);
+      if (fh != NULL)
        {
-         sec = eh->oh->elf.root.u.def.section;
+         sec = fh->elf.root.u.def.section;
          sec->flags |= SEC_KEEP;
        }
       else if (get_opd_info (eh->elf.root.u.def.section) != NULL
@@ -5523,16 +5580,15 @@ ppc64_elf_gc_mark_dynamic_ref (struct elf_link_hash_entry *h, void *inf)
 {
   struct bfd_link_info *info = (struct bfd_link_info *) inf;
   struct ppc_link_hash_entry *eh = (struct ppc_link_hash_entry *) h;
+  struct ppc_link_hash_entry *fdh;
 
   if (eh->elf.root.type == bfd_link_hash_warning)
     eh = (struct ppc_link_hash_entry *) eh->elf.root.u.i.link;
 
   /* Dynamic linking info is on the func descriptor sym.  */
-  if (eh->oh != NULL
-      && eh->oh->is_func_descriptor
-      && (eh->oh->elf.root.type == bfd_link_hash_defined
-         || eh->oh->elf.root.type == bfd_link_hash_defweak))
-    eh = eh->oh;
+  fdh = defined_func_desc (eh);
+  if (fdh != NULL)
+    eh = fdh;
 
   if ((eh->elf.root.type == bfd_link_hash_defined
        || eh->elf.root.type == bfd_link_hash_defweak)
@@ -5543,15 +5599,18 @@ ppc64_elf_gc_mark_dynamic_ref (struct elf_link_hash_entry *h, void *inf)
              && ELF_ST_VISIBILITY (eh->elf.other) != STV_HIDDEN)))
     {
       asection *code_sec;
+      struct ppc_link_hash_entry *fh;
 
       eh->elf.root.u.def.section->flags |= SEC_KEEP;
 
       /* Function descriptor syms cause the associated
         function code sym section to be marked.  */
-      if (eh->is_func_descriptor
-         && (eh->oh->elf.root.type == bfd_link_hash_defined
-             || eh->oh->elf.root.type == bfd_link_hash_defweak))
-       eh->oh->elf.root.u.def.section->flags |= SEC_KEEP;
+      fh = defined_code_entry (eh);
+      if (fh != NULL)
+       {
+         code_sec = fh->elf.root.u.def.section;
+         code_sec->flags |= SEC_KEEP;
+       }
       else if (get_opd_info (eh->elf.root.u.def.section) != NULL
               && opd_entry_value (eh->elf.root.u.def.section,
                                   eh->elf.root.u.def.value,
@@ -5583,7 +5642,7 @@ ppc64_elf_gc_mark_hook (asection *sec,
   if (h != NULL)
     {
       enum elf_ppc64_reloc_type r_type;
-      struct ppc_link_hash_entry *eh;
+      struct ppc_link_hash_entry *eh, *fh, *fdh;
 
       r_type = ELF64_R_TYPE (rel->r_info);
       switch (r_type)
@@ -5598,22 +5657,19 @@ ppc64_elf_gc_mark_hook (asection *sec,
            case bfd_link_hash_defined:
            case bfd_link_hash_defweak:
              eh = (struct ppc_link_hash_entry *) h;
-             if (eh->oh != NULL
-                 && eh->oh->is_func_descriptor
-                 && (eh->oh->elf.root.type == bfd_link_hash_defined
-                     || eh->oh->elf.root.type == bfd_link_hash_defweak))
-               eh = eh->oh;
+             fdh = defined_func_desc (eh);
+             if (fdh != NULL)
+               eh = fdh;
 
              /* Function descriptor syms cause the associated
                 function code sym section to be marked.  */
-             if (eh->is_func_descriptor
-                 && (eh->oh->elf.root.type == bfd_link_hash_defined
-                     || eh->oh->elf.root.type == bfd_link_hash_defweak))
+             fh = defined_code_entry (eh);
+             if (fh != NULL)
                {
                  /* They also mark their opd section.  */
                  eh->elf.root.u.def.section->gc_mark = 1;
 
-                 rsec = eh->oh->elf.root.u.def.section;
+                 rsec = fh->elf.root.u.def.section;
                }
              else if (get_opd_info (eh->elf.root.u.def.section) != NULL
                       && opd_entry_value (eh->elf.root.u.def.section,
@@ -5693,9 +5749,7 @@ ppc64_elf_gc_sweep_hook (bfd *abfd, struct bfd_link_info *info,
          struct ppc_dyn_relocs *p;
 
          h = sym_hashes[r_symndx - symtab_hdr->sh_info];
-         while (h->root.type == bfd_link_hash_indirect
-                || h->root.type == bfd_link_hash_warning)
-           h = (struct elf_link_hash_entry *) h->root.u.i.link;
+         h = elf_follow_link (h);
          eh = (struct ppc_link_hash_entry *) h;
 
          for (pp = &eh->dyn_relocs; (p = *pp) != NULL; pp = &p->next)
@@ -6081,18 +6135,17 @@ func_desc_adjust (struct elf_link_hash_entry *h, void *inf)
      in dynamic objects are handled elsewhere.  */
   if (fh->elf.root.type == bfd_link_hash_undefweak
       && fh->was_undefined
-      && (fh->oh->elf.root.type == bfd_link_hash_defined
-         || fh->oh->elf.root.type == bfd_link_hash_defweak)
-      && get_opd_info (fh->oh->elf.root.u.def.section) != NULL
-      && opd_entry_value (fh->oh->elf.root.u.def.section,
-                         fh->oh->elf.root.u.def.value,
+      && (fdh = defined_func_desc (fh)) != NULL
+      && get_opd_info (fdh->elf.root.u.def.section) != NULL
+      && opd_entry_value (fdh->elf.root.u.def.section,
+                         fdh->elf.root.u.def.value,
                          &fh->elf.root.u.def.section,
                          &fh->elf.root.u.def.value) != (bfd_vma) -1)
     {
-      fh->elf.root.type = fh->oh->elf.root.type;
+      fh->elf.root.type = fdh->elf.root.type;
       fh->elf.forced_local = 1;
-      fh->elf.def_regular = fh->oh->elf.def_regular;
-      fh->elf.def_dynamic = fh->oh->elf.def_dynamic;
+      fh->elf.def_regular = fdh->elf.def_regular;
+      fh->elf.def_dynamic = fdh->elf.def_dynamic;
     }
 
   /* If this is a function code symbol, transfer dynamic linking
@@ -6111,12 +6164,7 @@ func_desc_adjust (struct elf_link_hash_entry *h, void *inf)
   /* Find the corresponding function descriptor symbol.  Create it
      as undefined if necessary.  */
 
-  fdh = get_fdh (fh, htab);
-  if (fdh != NULL)
-    while (fdh->elf.root.type == bfd_link_hash_indirect
-          || fdh->elf.root.type == bfd_link_hash_warning)
-      fdh = (struct ppc_link_hash_entry *) fdh->elf.root.u.i.link;
-
+  fdh = lookup_fdh (fh, htab);
   if (fdh == NULL
       && !info->executable
       && (fh->elf.root.type == bfd_link_hash_undefined
@@ -6454,9 +6502,7 @@ get_sym_h (struct elf_link_hash_entry **hp,
       struct elf_link_hash_entry *h;
 
       h = sym_hashes[r_symndx - symtab_hdr->sh_info];
-      while (h->root.type == bfd_link_hash_indirect
-            || h->root.type == bfd_link_hash_warning)
-       h = (struct elf_link_hash_entry *) h->root.u.i.link;
+      h = elf_follow_link (h);
 
       if (hp != NULL)
        *hp = h;
@@ -7024,8 +7070,8 @@ ppc64_elf_edit_opd (bfd *obfd, struct bfd_link_info *info,
                  if (h != NULL
                      && h->root.root.string[0] == '.')
                    {
-                     fdh = get_fdh ((struct ppc_link_hash_entry *) h,
-                                    ppc_hash_table (info));
+                     fdh = lookup_fdh ((struct ppc_link_hash_entry *) h,
+                                       ppc_hash_table (info));
                      if (fdh != NULL
                          && fdh->elf.root.type != bfd_link_hash_defined
                          && fdh->elf.root.type != bfd_link_hash_defweak)
@@ -7175,7 +7221,9 @@ ppc64_elf_edit_opd (bfd *obfd, struct bfd_link_info *info,
 /* Set htab->tls_get_addr and call the generic ELF tls_setup function.  */
 
 asection *
-ppc64_elf_tls_setup (bfd *obfd, struct bfd_link_info *info)
+ppc64_elf_tls_setup (bfd *obfd,
+                    struct bfd_link_info *info,
+                    int no_tls_get_addr_opt)
 {
   struct ppc_link_hash_table *htab;
 
@@ -7183,9 +7231,83 @@ ppc64_elf_tls_setup (bfd *obfd, struct bfd_link_info *info)
   htab->tls_get_addr = ((struct ppc_link_hash_entry *)
                        elf_link_hash_lookup (&htab->elf, ".__tls_get_addr",
                                              FALSE, FALSE, TRUE));
+  /* Move dynamic linking info to the function descriptor sym.  */
+  if (htab->tls_get_addr != NULL)
+    func_desc_adjust (&htab->tls_get_addr->elf, info);
   htab->tls_get_addr_fd = ((struct ppc_link_hash_entry *)
                           elf_link_hash_lookup (&htab->elf, "__tls_get_addr",
                                                 FALSE, FALSE, TRUE));
+  if (!no_tls_get_addr_opt)
+    {
+      struct elf_link_hash_entry *opt, *opt_fd, *tga, *tga_fd;
+
+      opt = elf_link_hash_lookup (&htab->elf, ".__tls_get_addr_opt",
+                                 FALSE, FALSE, TRUE);
+      if (opt != NULL)
+       func_desc_adjust (opt, info);
+      opt_fd = elf_link_hash_lookup (&htab->elf, "__tls_get_addr_opt",
+                                    FALSE, FALSE, TRUE);
+      if (opt_fd != NULL
+         && (opt_fd->root.type == bfd_link_hash_defined
+             || opt_fd->root.type == bfd_link_hash_defweak))
+       {
+         /* If glibc supports an optimized __tls_get_addr call stub,
+            signalled by the presence of __tls_get_addr_opt, and we'll
+            be calling __tls_get_addr via a plt call stub, then
+            make __tls_get_addr point to __tls_get_addr_opt.  */
+         tga_fd = &htab->tls_get_addr_fd->elf;
+         if (htab->elf.dynamic_sections_created
+             && tga_fd != NULL
+             && (tga_fd->type == STT_FUNC
+                 || tga_fd->needs_plt)
+             && !(SYMBOL_CALLS_LOCAL (info, tga_fd)
+                  || (ELF_ST_VISIBILITY (tga_fd->other) != STV_DEFAULT
+                      && tga_fd->root.type == bfd_link_hash_undefweak)))
+           {
+             struct plt_entry *ent;
+
+             for (ent = tga_fd->plt.plist; ent != NULL; ent = ent->next)
+               if (ent->plt.refcount > 0)
+                 break;
+             if (ent != NULL)
+               {
+                 tga_fd->root.type = bfd_link_hash_indirect;
+                 tga_fd->root.u.i.link = &opt_fd->root;
+                 ppc64_elf_copy_indirect_symbol (info, opt_fd, tga_fd);
+                 if (opt_fd->dynindx != -1)
+                   {
+                     /* Use __tls_get_addr_opt in dynamic relocations.  */
+                     opt_fd->dynindx = -1;
+                     _bfd_elf_strtab_delref (elf_hash_table (info)->dynstr,
+                                             opt_fd->dynstr_index);
+                     if (!bfd_elf_link_record_dynamic_symbol (info, opt_fd))
+                       return FALSE;
+                   }
+                 htab->tls_get_addr_fd = (struct ppc_link_hash_entry *) opt_fd;
+                 tga = &htab->tls_get_addr->elf;
+                 if (opt != NULL && tga != NULL)
+                   {
+                     tga->root.type = bfd_link_hash_indirect;
+                     tga->root.u.i.link = &opt->root;
+                     ppc64_elf_copy_indirect_symbol (info, opt, tga);
+                     _bfd_elf_link_hash_hide_symbol (info, opt,
+                                                     tga->forced_local);
+                     htab->tls_get_addr = (struct ppc_link_hash_entry *) opt;
+                   }
+                 htab->tls_get_addr_fd->oh = htab->tls_get_addr;
+                 htab->tls_get_addr_fd->is_func_descriptor = 1;
+                 if (htab->tls_get_addr != NULL)
+                   {
+                     htab->tls_get_addr->oh = htab->tls_get_addr_fd;
+                     htab->tls_get_addr->is_func = 1;
+                   }
+               }
+           }
+       }
+      else
+       no_tls_get_addr_opt = TRUE;
+    }
+  htab->no_tls_get_addr_opt = no_tls_get_addr_opt;
   return _bfd_elf_tls_setup (obfd, info);
 }
 
@@ -7208,9 +7330,7 @@ branch_reloc_hash_match (const bfd *ibfd,
       struct elf_link_hash_entry *h;
 
       h = sym_hashes[r_symndx - symtab_hdr->sh_info];
-      while (h->root.type == bfd_link_hash_indirect
-            || h->root.type == bfd_link_hash_warning)
-       h = (struct elf_link_hash_entry *) h->root.u.i.link;
+      h = elf_follow_link (h);
       if (h == &hash1->elf || h == &hash2->elf)
        return TRUE;
     }
@@ -8625,6 +8745,12 @@ ppc64_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
            return FALSE;
        }
 
+      if (!htab->no_tls_get_addr_opt
+         && htab->tls_get_addr_fd != NULL
+         && htab->tls_get_addr_fd->elf.plt.plist != NULL
+         && !add_dynamic_entry (DT_PPC64_TLSOPT, 0))
+       return FALSE;
+
       if (relocs)
        {
          if (!add_dynamic_entry (DT_RELA, 0)
@@ -8668,9 +8794,9 @@ ppc_type_of_stub (asection *input_sec,
     {
       struct plt_entry *ent;
       struct ppc_link_hash_entry *fdh = h;
-      if (fdh->oh != NULL
-         && fdh->oh->is_func_descriptor)
-       fdh = fdh->oh;
+      if (h->oh != NULL
+         && h->oh->is_func_descriptor)
+       fdh = ppc_follow_link (h->oh);
 
       for (ent = fdh->elf.plt.plist; ent != NULL; ent = ent->next)
        if (ent->addend == rel->r_addend
@@ -8818,6 +8944,49 @@ build_plt_stub (bfd *obfd, bfd_byte *p, int offset, Elf_Internal_Rela *r)
   return p;
 }
 
+/* Build a special .plt call stub for __tls_get_addr.  */
+
+#define LD_R11_0R3     0xe9630000
+#define LD_R12_0R3     0xe9830000
+#define MR_R0_R3       0x7c601b78
+#define CMPDI_R11_0    0x2c2b0000
+#define ADD_R3_R12_R13 0x7c6c6a14
+#define BEQLR          0x4d820020
+#define MR_R3_R0       0x7c030378
+#define MFLR_R11       0x7d6802a6
+#define STD_R11_0R1    0xf9610000
+#define BCTRL          0x4e800421
+#define LD_R11_0R1     0xe9610000
+#define LD_R2_0R1      0xe8410000
+#define MTLR_R11       0x7d6803a6
+
+static inline bfd_byte *
+build_tls_get_addr_stub (bfd *obfd, bfd_byte *p, int offset,
+                        Elf_Internal_Rela *r)
+{
+  bfd_put_32 (obfd, LD_R11_0R3 + 0, p),                p += 4;
+  bfd_put_32 (obfd, LD_R12_0R3 + 8, p),                p += 4;
+  bfd_put_32 (obfd, MR_R0_R3, p),              p += 4;
+  bfd_put_32 (obfd, CMPDI_R11_0, p),           p += 4;
+  bfd_put_32 (obfd, ADD_R3_R12_R13, p),                p += 4;
+  bfd_put_32 (obfd, BEQLR, p),                 p += 4;
+  bfd_put_32 (obfd, MR_R3_R0, p),              p += 4;
+  bfd_put_32 (obfd, MFLR_R11, p),              p += 4;
+  bfd_put_32 (obfd, STD_R11_0R1 + 32, p),      p += 4;
+
+  if (r != NULL)
+    r[0].r_offset += 9 * 4;
+  p = build_plt_stub (obfd, p, offset, r);
+  bfd_put_32 (obfd, BCTRL, p - 4);
+
+  bfd_put_32 (obfd, LD_R11_0R1 + 32, p),       p += 4;
+  bfd_put_32 (obfd, LD_R2_0R1 + 40, p),                p += 4;
+  bfd_put_32 (obfd, MTLR_R11, p),              p += 4;
+  bfd_put_32 (obfd, BLR, p),                   p += 4;
+
+  return p;
+}
+
 static Elf_Internal_Rela *
 get_relocs (asection *sec, int count)
 {
@@ -8944,7 +9113,7 @@ ppc_build_one_stub (struct bfd_hash_entry *gen_entry, void *in_arg)
              hashes[symndx] = &h->elf;
              r->r_info = ELF64_R_INFO (symndx, R_PPC64_REL24);
              if (h->oh != NULL && h->oh->is_func)
-               h = h->oh;
+               h = ppc_follow_link (h->oh);
              if (h->elf.root.u.def.section != stub_entry->target_section)
                /* H is an opd symbol.  The addend must be zero.  */
                r->r_addend = 0;
@@ -9109,22 +9278,20 @@ ppc_build_one_stub (struct bfd_hash_entry *gen_entry, void *in_arg)
       break;
 
     case ppc_stub_plt_call:
-      /* Do the best we can for shared libraries built without
-        exporting ".foo" for each "foo".  This can happen when symbol
-        versioning scripts strip all bar a subset of symbols.  */
       if (stub_entry->h != NULL
-         && stub_entry->h->oh != NULL
-         && stub_entry->h->oh->elf.root.type != bfd_link_hash_defined
-         && stub_entry->h->oh->elf.root.type != bfd_link_hash_defweak)
+         && stub_entry->h->is_func_descriptor
+         && stub_entry->h->oh != NULL)
        {
-         /* Point the symbol at the stub.  There may be multiple stubs,
-            we don't really care;  The main thing is to make this sym
-            defined somewhere.  Maybe defining the symbol in the stub
-            section is a silly idea.  If we didn't do this, htab->top_id
-            could disappear.  */
-         stub_entry->h->oh->elf.root.type = bfd_link_hash_defined;
-         stub_entry->h->oh->elf.root.u.def.section = stub_entry->stub_sec;
-         stub_entry->h->oh->elf.root.u.def.value = stub_entry->stub_offset;
+         struct ppc_link_hash_entry *fh = ppc_follow_link (stub_entry->h->oh);
+
+         /* If the old-ABI "dot-symbol" is undefined make it weak so
+            we don't get a link error from RELOC_FOR_GLOBAL_SYMBOL.
+            FIXME: We used to define the symbol on one of the call
+            stubs instead, which is why we test symbol section id
+            against htab->top_id in various places.  Likely all
+            these checks could now disappear.  */
+         if (fh->elf.root.type == bfd_link_hash_undefined)
+           fh->elf.root.type = bfd_link_hash_undefweak;
        }
 
       /* Now build the stub.  */
@@ -9188,7 +9355,13 @@ ppc_build_one_stub (struct bfd_hash_entry *gen_entry, void *in_arg)
            r[0].r_offset += 2;
          r[0].r_addend = dest;
        }
-      p = build_plt_stub (htab->stub_bfd, loc, off, r);
+      if (stub_entry->h != NULL
+         && (stub_entry->h == htab->tls_get_addr_fd
+             || stub_entry->h == htab->tls_get_addr)
+         && !htab->no_tls_get_addr_opt)
+       p = build_tls_get_addr_stub (htab->stub_bfd, loc, off, r);
+      else
+       p = build_plt_stub (htab->stub_bfd, loc, off, r);
       size = p - loc;
       break;
 
@@ -9277,6 +9450,11 @@ ppc_size_one_stub (struct bfd_hash_entry *gen_entry, void *in_arg)
        size -= 4;
       if (PPC_HA (off + 16) != PPC_HA (off))
        size += 4;
+      if (stub_entry->h != NULL
+         && (stub_entry->h == htab->tls_get_addr_fd
+             || stub_entry->h == htab->tls_get_addr)
+         && !htab->no_tls_get_addr_opt)
+       size += 13 * 4;
       if (info->emitrelocations)
        {
          stub_entry->stub_sec->reloc_count
@@ -9561,7 +9739,7 @@ toc_adjusting_stub_needed (struct bfd_link_info *info, asection *isec)
       if (eh != NULL
          && (eh->elf.plt.plist != NULL
              || (eh->oh != NULL
-                 && eh->oh->elf.plt.plist != NULL)))
+                 && ppc_follow_link (eh->oh)->elf.plt.plist != NULL)))
        {
          ret = 1;
          break;
@@ -10000,7 +10178,7 @@ ppc64_elf_size_stubs (bfd *output_bfd,
                         use the func descriptor sym instead if it is
                         defined.  */
                      if (hash->elf.root.root.string[0] == '.'
-                         && (fdh = get_fdh (hash, htab)) != NULL)
+                         && (fdh = lookup_fdh (hash, htab)) != NULL)
                        {
                          if (fdh->elf.root.type == bfd_link_hash_defined
                              || fdh->elf.root.type == bfd_link_hash_defweak)
@@ -11188,10 +11366,12 @@ ppc64_elf_relocate_section (bfd *output_bfd,
             base pointer.  */
          stub_entry = NULL;
          fdh = h;
-         if (((h != NULL
-               && (((fdh = h->oh) != NULL
-                    && fdh->elf.plt.plist != NULL)
-                   || (fdh = h)->elf.plt.plist != NULL))
+         if (h != NULL
+             && h->oh != NULL
+             && h->oh->is_func_descriptor)
+           fdh = ppc_follow_link (h->oh);
+         if (((fdh != NULL
+               && fdh->elf.plt.plist != NULL)
               || (sec != NULL
                   && sec->output_section != NULL
                   && sec->id <= htab->top_id
@@ -11214,8 +11394,16 @@ ppc64_elf_relocate_section (bfd *output_bfd,
                  if (nop == NOP
                      || nop == CROR_151515 || nop == CROR_313131)
                    {
-                     bfd_put_32 (input_bfd, LD_R2_40R1,
-                                 contents + rel->r_offset + 4);
+                     if (h != NULL
+                         && (h == htab->tls_get_addr_fd
+                             || h == htab->tls_get_addr)
+                         && !htab->no_tls_get_addr_opt)
+                       {
+                         /* Special stub used, leave nop alone.  */
+                       }
+                     else
+                       bfd_put_32 (input_bfd, LD_R2_40R1,
+                                   contents + rel->r_offset + 4);
                      can_plt_call = TRUE;
                    }
                }

diff --git a/bfd/elf64-ppc.h b/bfd/elf64-ppc.h
index 687b4a1..e5f7140 100644 (file)
--- a/bfd/elf64-ppc.h
+++ b/bfd/elf64-ppc.h
@@ -24,7 +24,7 @@ void ppc64_elf_init_stub_bfd
 bfd_boolean ppc64_elf_edit_opd
   (bfd *, struct bfd_link_info *, bfd_boolean);
 asection *ppc64_elf_tls_setup
-  (bfd *, struct bfd_link_info *);
+(bfd *, struct bfd_link_info *, int);
 bfd_boolean ppc64_elf_tls_optimize
   (bfd *, struct bfd_link_info *);
 bfd_boolean ppc64_elf_edit_toc

diff --git a/bfd/elf64-x86-64.c b/bfd/elf64-x86-64.c
index 4fb325a..779ad0f 100644 (file)
--- a/bfd/elf64-x86-64.c
+++ b/bfd/elf64-x86-64.c
@@ -2543,6 +2543,16 @@ is_32bit_relative_branch (bfd_byte *contents, bfd_vma offset)
              && (contents [offset - 1] & 0xf0) == 0x80));
 }
 
+static void
+elf64_x86_64_append_rela (bfd *abfd, asection *s, Elf_Internal_Rela *rel)
+{
+  bfd_byte *loc = s->contents;
+  loc += s->reloc_count++ * sizeof (Elf64_External_Rela);
+  BFD_ASSERT (loc + sizeof (Elf64_External_Rela)
+             <= s->contents + s->size);
+  bfd_elf64_swap_reloca_out (abfd, rel, loc);
+}
+
 /* Relocate an x86_64 ELF section.  */
 
 static bfd_boolean
@@ -2712,7 +2722,6 @@ elf64_x86_64_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
              if (info->shared && h->non_got_ref)
                {
                  Elf_Internal_Rela outrel;
-                 bfd_byte *loc;
                  asection *sreloc;
 
                  /* Need a dynamic relocation to get the real function
@@ -2745,10 +2754,7 @@ elf64_x86_64_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
                    }
 
                  sreloc = htab->elf.irelifunc;
-                 loc = sreloc->contents;
-                 loc += (sreloc->reloc_count++
-                         * sizeof (Elf64_External_Rela));
-                 bfd_elf64_swap_reloca_out (output_bfd, &outrel, loc);
+                 elf64_x86_64_append_rela (output_bfd, sreloc, &outrel);
 
                  /* If this reloc is against an external symbol, we
                     do not want to fiddle with the addend.  Otherwise,
@@ -2931,7 +2937,6 @@ elf64_x86_64_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
                    {
                      asection *s;
                      Elf_Internal_Rela outrel;
-                     bfd_byte *loc;
 
                      /* We need to generate a R_X86_64_RELATIVE reloc
                         for the dynamic linker.  */
@@ -2944,9 +2949,7 @@ elf64_x86_64_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
                                         + off);
                      outrel.r_info = ELF64_R_INFO (0, R_X86_64_RELATIVE);
                      outrel.r_addend = relocation;
-                     loc = s->contents;
-                     loc += s->reloc_count++ * sizeof (Elf64_External_Rela);
-                     bfd_elf64_swap_reloca_out (output_bfd, &outrel, loc);
+                     elf64_x86_64_append_rela (output_bfd, s, &outrel);
                    }
 
                  local_got_offsets[r_symndx] |= 1;
@@ -3135,7 +3138,6 @@ elf64_x86_64_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
                      || h->root.type == bfd_link_hash_undefined)))
            {
              Elf_Internal_Rela outrel;
-             bfd_byte *loc;
              bfd_boolean skip, relocate;
              asection *sreloc;
 
@@ -3219,9 +3221,7 @@ elf64_x86_64_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 
              BFD_ASSERT (sreloc != NULL && sreloc->contents != NULL);
 
-             loc = sreloc->contents;
-             loc += sreloc->reloc_count++ * sizeof (Elf64_External_Rela);
-             bfd_elf64_swap_reloca_out (output_bfd, &outrel, loc);
+             elf64_x86_64_append_rela (output_bfd, sreloc, &outrel);
 
              /* If this reloc is against an external symbol, we do
                 not want to fiddle with the addend.  Otherwise, we
@@ -3392,7 +3392,6 @@ elf64_x86_64_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
          else
            {
              Elf_Internal_Rela outrel;
-             bfd_byte *loc;
              int dr_type, indx;
              asection *sreloc;
 
@@ -3411,16 +3410,11 @@ elf64_x86_64_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
                                     + offplt
                                     + htab->sgotplt_jump_table_size);
                  sreloc = htab->elf.srelplt;
-                 loc = sreloc->contents;
-                 loc += sreloc->reloc_count++
-                   * sizeof (Elf64_External_Rela);
-                 BFD_ASSERT (loc + sizeof (Elf64_External_Rela)
-                             <= sreloc->contents + sreloc->size);
                  if (indx == 0)
                    outrel.r_addend = relocation - elf64_x86_64_dtpoff_base (info);
                  else
                    outrel.r_addend = 0;
-                 bfd_elf64_swap_reloca_out (output_bfd, &outrel, loc);
+                 elf64_x86_64_append_rela (output_bfd, sreloc, &outrel);
                }
 
              sreloc = htab->elf.srelgot;
@@ -3442,11 +3436,7 @@ elf64_x86_64_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
                outrel.r_addend = relocation - elf64_x86_64_dtpoff_base (info);
              outrel.r_info = ELF64_R_INFO (indx, dr_type);
 
-             loc = sreloc->contents;
-             loc += sreloc->reloc_count++ * sizeof (Elf64_External_Rela);
-             BFD_ASSERT (loc + sizeof (Elf64_External_Rela)
-                         <= sreloc->contents + sreloc->size);
-             bfd_elf64_swap_reloca_out (output_bfd, &outrel, loc);
+             elf64_x86_64_append_rela (output_bfd, sreloc, &outrel);
 
              if (GOT_TLS_GD_P (tls_type))
                {
@@ -3464,11 +3454,8 @@ elf64_x86_64_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
                      outrel.r_info = ELF64_R_INFO (indx,
                                                    R_X86_64_DTPOFF64);
                      outrel.r_offset += GOT_ENTRY_SIZE;
-                     sreloc->reloc_count++;
-                     loc += sizeof (Elf64_External_Rela);
-                     BFD_ASSERT (loc + sizeof (Elf64_External_Rela)
-                                 <= sreloc->contents + sreloc->size);
-                     bfd_elf64_swap_reloca_out (output_bfd, &outrel, loc);
+                     elf64_x86_64_append_rela (output_bfd, sreloc,
+                                               &outrel);
                    }
                }
 
@@ -3608,7 +3595,6 @@ elf64_x86_64_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
          else
            {
              Elf_Internal_Rela outrel;
-             bfd_byte *loc;
 
              if (htab->elf.srelgot == NULL)
                abort ();
@@ -3622,9 +3608,8 @@ elf64_x86_64_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
                          htab->elf.sgot->contents + off + GOT_ENTRY_SIZE);
              outrel.r_info = ELF64_R_INFO (0, R_X86_64_DTPMOD64);
              outrel.r_addend = 0;
-             loc = htab->elf.srelgot->contents;
-             loc += htab->elf.srelgot->reloc_count++ * sizeof (Elf64_External_Rela);
-             bfd_elf64_swap_reloca_out (output_bfd, &outrel, loc);
+             elf64_x86_64_append_rela (output_bfd, htab->elf.srelgot,
+                                       &outrel);
              htab->tls_ld_got.offset |= 1;
            }
          relocation = htab->elf.sgot->output_section->vma
@@ -3858,7 +3843,6 @@ elf64_x86_64_finish_dynamic_symbol (bfd *output_bfd,
       && elf64_x86_64_hash_entry (h)->tls_type != GOT_TLS_IE)
     {
       Elf_Internal_Rela rela;
-      bfd_byte *loc;
 
       /* This symbol has an entry in the global offset table.  Set it
         up.  */
@@ -3921,15 +3905,12 @@ do_glob_dat:
          rela.r_addend = 0;
        }
 
-      loc = htab->elf.srelgot->contents;
-      loc += htab->elf.srelgot->reloc_count++ * sizeof (Elf64_External_Rela);
-      bfd_elf64_swap_reloca_out (output_bfd, &rela, loc);
+      elf64_x86_64_append_rela (output_bfd, htab->elf.srelgot, &rela);
     }
 
   if (h->needs_copy)
     {
       Elf_Internal_Rela rela;
-      bfd_byte *loc;
 
       /* This symbol needs a copy reloc.  Set it up.  */
 
@@ -3944,9 +3925,7 @@ do_glob_dat:
                       + h->root.u.def.section->output_offset);
       rela.r_info = ELF64_R_INFO (h->dynindx, R_X86_64_COPY);
       rela.r_addend = 0;
-      loc = htab->srelbss->contents;
-      loc += htab->srelbss->reloc_count++ * sizeof (Elf64_External_Rela);
-      bfd_elf64_swap_reloca_out (output_bfd, &rela, loc);
+      elf64_x86_64_append_rela (output_bfd, htab->srelbss, &rela);
     }
 
   /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute.  SYM may

diff --git a/bfd/elfcode.h b/bfd/elfcode.h
index f539119..ecdc2de 100644 (file)
--- a/bfd/elfcode.h
+++ b/bfd/elfcode.h
@@ -761,10 +761,13 @@ elf_object_p (bfd *abfd)
          /* Sanity check sh_link and sh_info.  */
          if (i_shdrp[shindex].sh_link >= num_sec)
            {
-             /* PR 10478: Accept sparc binaries with a sh_link
+             /* PR 10478: Accept Solaris binaries with a sh_link
                 field set to SHN_BEFORE or SHN_AFTER.  */
              switch (ebd->elf_machine_code)
                {
+               case EM_386:
+               case EM_486:
+               case EM_X86_64:
                case EM_OLD_SPARCV9:
                case EM_SPARC32PLUS:
                case EM_SPARCV9:

diff --git a/bfd/elflink.c b/bfd/elflink.c
index c42c6e1..f8029b0 100644 (file)
--- a/bfd/elflink.c
+++ b/bfd/elflink.c
@@ -3234,6 +3234,8 @@ elf_finalize_dynstr (bfd *output_bfd, struct bfd_link_info *info)
        case DT_RUNPATH:
        case DT_FILTER:
        case DT_AUXILIARY:
+       case DT_AUDIT:
+       case DT_DEPAUDIT:
          dyn.d_un.d_val = _bfd_elf_strtab_offset (dynstr, dyn.d_un.d_val);
          break;
        default:
@@ -3525,6 +3527,7 @@ elf_link_add_object_symbols (bfd *abfd, struct bfd_link_info *info)
     {
       asection *s;
       const char *soname = NULL;
+      char *audit = NULL;
       struct bfd_link_needed_list *rpath = NULL, *runpath = NULL;
       int ret;
 
@@ -3653,6 +3656,11 @@ error_free_dyn:
                    ;
                  *pn = n;
                }
+             if (dyn.d_tag == DT_AUDIT)
+               {
+                 unsigned int tagv = dyn.d_un.d_val;
+                 audit = bfd_elf_string_from_elf_section (abfd, shlink, tagv);
+               }
            }
 
          free (dynbuf);
@@ -3705,6 +3713,9 @@ error_free_dyn:
         particular dynamic object more than once.  */
       if (ret > 0)
        return TRUE;
+
+      /* Save the DT_AUDIT entry for the linker emulation code. */
+      elf_dt_audit (abfd) = audit; 
     }
 
   /* If this is a dynamic object, we always link against the .dynsym
@@ -5451,6 +5462,8 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd,
                               const char *soname,
                               const char *rpath,
                               const char *filter_shlib,
+                              const char *audit,
+                              const char *depaudit,
                               const char * const *auxiliary_filters,
                               struct bfd_link_info *info,
                               asection **sinterpptr,
@@ -5603,6 +5616,28 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd,
            }
        }
 
+      if (audit != NULL)
+       {
+         bfd_size_type indx;
+
+         indx = _bfd_elf_strtab_add (elf_hash_table (info)->dynstr, audit,
+                                     TRUE);
+         if (indx == (bfd_size_type) -1
+             || !_bfd_elf_add_dynamic_entry (info, DT_AUDIT, indx))
+           return FALSE;
+       }
+
+      if (depaudit != NULL)
+       {
+         bfd_size_type indx;
+
+         indx = _bfd_elf_strtab_add (elf_hash_table (info)->dynstr, depaudit,
+                                     TRUE);
+         if (indx == (bfd_size_type) -1
+             || !_bfd_elf_add_dynamic_entry (info, DT_DEPAUDIT, indx))
+           return FALSE;
+       }
+
       eif.info = info;
       eif.verdefs = verdefs;
       eif.failed = FALSE;
@@ -8597,7 +8632,11 @@ elf_link_output_extsym (struct elf_link_hash_entry *h, void *data)
   sym.st_size = h->size;
   sym.st_other = h->other;
   if (h->forced_local)
-    sym.st_info = ELF_ST_INFO (STB_LOCAL, h->type);
+    {
+      sym.st_info = ELF_ST_INFO (STB_LOCAL, h->type);
+      /* Turn off visibility on local symbol.  */
+      sym.st_other &= ~ELF_ST_VISIBILITY (-1);
+    }
   else if (h->unique_global)
     sym.st_info = ELF_ST_INFO (STB_GNU_UNIQUE, h->type);
   else if (h->root.type == bfd_link_hash_undefweak
@@ -10669,13 +10708,11 @@ bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
              asection *s;
              bfd_byte *dest;
 
-             sym.st_size = e->isym.st_size;
-             sym.st_other = e->isym.st_other;
-
-             /* Copy the internal symbol as is.
+             /* Copy the internal symbol and turn off visibility.
                 Note that we saved a word of storage and overwrote
                 the original st_name with the dynstr_index.  */
              sym = e->isym;
+             sym.st_other &= ~ELF_ST_VISIBILITY (-1);
 
              s = bfd_section_from_elf_index (e->input_bfd,
                                              e->isym.st_shndx);

diff --git a/bfd/hp300bsd.c b/bfd/hp300bsd.c
index d498419..2688b80 100644 (file)
--- a/bfd/hp300bsd.c
+++ b/bfd/hp300bsd.c
@@ -1,5 +1,5 @@
 /* BFD back-end for HP 9000/300 (68000-based) machines running BSD Unix.
-   Copyright 1992, 1994, 1995, 2001, 2003, 2005, 2007
+   Copyright 1992, 1994, 1995, 2001, 2003, 2005, 2007, 2009
    Free Software Foundation, Inc.
 
    This file is part of BFD, the Binary File Descriptor library.
@@ -22,7 +22,6 @@
 #define TARGET_IS_BIG_ENDIAN_P
 #define N_HEADER_IN_TEXT(x) 0
 #define ENTRY_CAN_BE_ZERO
-#define N_SHARED_LIB(x) 0 /* Avoids warning */
 #define TEXT_START_ADDR 0
 #define TARGET_PAGE_SIZE 4096
 #define SEGMENT_SIZE TARGET_PAGE_SIZE

diff --git a/bfd/i386bsd.c b/bfd/i386bsd.c
index b59171c..d54841c 100644 (file)
--- a/bfd/i386bsd.c
+++ b/bfd/i386bsd.c
@@ -1,5 +1,5 @@
 /* BFD back-end for i386 a.out binaries under BSD.
-   Copyright 1990, 1991, 1992, 1993, 1994, 2001, 2005, 2007
+   Copyright 1990, 1991, 1992, 1993, 1994, 2001, 2005, 2007, 2009
    Free Software Foundation, Inc.
 
    This file is part of BFD, the Binary File Descriptor library.
@@ -30,7 +30,6 @@
 
 /* ZMAGIC files start at address 0.  This does not apply to QMAGIC.  */
 #define TEXT_START_ADDR 0
-#define N_SHARED_LIB(x) 0
 
 #define        TARGET_PAGE_SIZE        4096
 #define        SEGMENT_SIZE    TARGET_PAGE_SIZE

diff --git a/bfd/i386linux.c b/bfd/i386linux.c
index dee733d..a5bb77d 100644 (file)
--- a/bfd/i386linux.c
+++ b/bfd/i386linux.c
@@ -1,6 +1,6 @@
 /* BFD back-end for linux flavored i386 a.out binaries.
    Copyright 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001, 2002, 2003,
-   2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
+   2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
 
    This file is part of BFD, the Binary File Descriptor library.
 
@@ -23,7 +23,6 @@
 #define ZMAGIC_DISK_BLOCK_SIZE 1024
 #define        SEGMENT_SIZE TARGET_PAGE_SIZE
 #define TEXT_START_ADDR        0x0
-#define N_SHARED_LIB(x) 0
 
 #define MACHTYPE_OK(mtype) ((mtype) == M_386 || (mtype) == M_UNKNOWN)
 

diff --git a/bfd/i386lynx.c b/bfd/i386lynx.c
index 2e85724..45909bf 100644 (file)
--- a/bfd/i386lynx.c
+++ b/bfd/i386lynx.c
@@ -1,6 +1,6 @@
 /* BFD back-end for i386 a.out binaries under LynxOS.
    Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1999, 2001, 2002,
-   2003, 2005, 2007 Free Software Foundation, Inc.
+   2003, 2005, 2007, 2009 Free Software Foundation, Inc.
 
    This file is part of BFD, the Binary File Descriptor library.
 
@@ -19,8 +19,6 @@
    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
    MA 02110-1301, USA.  */
 
-#define N_SHARED_LIB(x) 0
-
 #define TEXT_START_ADDR 0
 #define TARGET_PAGE_SIZE 4096
 #define SEGMENT_SIZE TARGET_PAGE_SIZE

diff --git a/bfd/libbfd.h b/bfd/libbfd.h
index 2450b2d..7fe6578 100644 (file)
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -1646,6 +1646,30 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
   "BFD_RELOC_AVR_LDI",
   "BFD_RELOC_AVR_6",
   "BFD_RELOC_AVR_6_ADIW",
+  "BFD_RELOC_RX_NEG8",
+  "BFD_RELOC_RX_NEG16",
+  "BFD_RELOC_RX_NEG24",
+  "BFD_RELOC_RX_NEG32",
+  "BFD_RELOC_RX_16_OP",
+  "BFD_RELOC_RX_24_OP",
+  "BFD_RELOC_RX_32_OP",
+  "BFD_RELOC_RX_8U",
+  "BFD_RELOC_RX_16U",
+  "BFD_RELOC_RX_24U",
+  "BFD_RELOC_RX_DIR3U_PCREL",
+  "BFD_RELOC_RX_DIFF",
+  "BFD_RELOC_RX_GPRELB",
+  "BFD_RELOC_RX_GPRELW",
+  "BFD_RELOC_RX_GPRELL",
+  "BFD_RELOC_RX_SYM",
+  "BFD_RELOC_RX_OP_SUBTRACT",
+  "BFD_RELOC_RX_ABS8",
+  "BFD_RELOC_RX_ABS16",
+  "BFD_RELOC_RX_ABS32",
+  "BFD_RELOC_RX_ABS16U",
+  "BFD_RELOC_RX_ABS16UW",
+  "BFD_RELOC_RX_ABS16UL",
+  "BFD_RELOC_RX_RELAX",
   "BFD_RELOC_390_12",
   "BFD_RELOC_390_GOT12",
   "BFD_RELOC_390_PLT32",

diff --git a/bfd/m68klinux.c b/bfd/m68klinux.c
index 403e4f3..08b0010 100644 (file)
--- a/bfd/m68klinux.c
+++ b/bfd/m68klinux.c
@@ -1,6 +1,6 @@
 /* BFD back-end for linux flavored m68k a.out binaries.
    Copyright 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2000, 2001, 2002,
-   2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
+   2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
 
    This file is part of BFD, the Binary File Descriptor library.
 
@@ -23,7 +23,6 @@
 #define ZMAGIC_DISK_BLOCK_SIZE 1024
 #define        SEGMENT_SIZE TARGET_PAGE_SIZE
 #define TEXT_START_ADDR        0x0
-#define N_SHARED_LIB(x) 0
 
 #define MACHTYPE_OK(mtype) ((mtype) == M_68020 || (mtype) == M_UNKNOWN)
 

diff --git a/bfd/m88kmach3.c b/bfd/m88kmach3.c
index 2a0e2f4..d98b4c7 100644 (file)
--- a/bfd/m88kmach3.c
+++ b/bfd/m88kmach3.c
@@ -1,5 +1,5 @@
 /* BFD back-end for Motorola m88k a.out (Mach 3) binaries.
-   Copyright 1990, 1991, 1993, 1994, 1995, 2001, 2003, 2005, 2007
+   Copyright 1990, 1991, 1993, 1994, 1995, 2001, 2003, 2005, 2007, 2009
    Free Software Foundation, Inc.
 
    This file is part of BFD, the Binary File Descriptor library.
@@ -23,7 +23,6 @@
 #define SEGMENT_SIZE   0x20000
 #define TEXT_START_ADDR        0
 #define N_HEADER_IN_TEXT(x)    1               /* (N_MAGIG(x) == ZMAGIC) */
-#define N_SHARED_LIB(x) 0
 
 #define N_TXTSIZE(x)   ((x).a_text)
 

diff --git a/bfd/mipsbsd.c b/bfd/mipsbsd.c
index db4c86b..004ef6e 100644 (file)
--- a/bfd/mipsbsd.c
+++ b/bfd/mipsbsd.c
@@ -1,6 +1,6 @@
 /* BFD backend for MIPS BSD (a.out) binaries.
    Copyright 1993, 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
-   2005, 2007 Free Software Foundation, Inc.
+   2005, 2007, 2009 Free Software Foundation, Inc.
    Written by Ralph Campbell.
 
    This file is part of BFD, the Binary File Descriptor library.
@@ -23,7 +23,6 @@
 
 /* #define ENTRY_CAN_BE_ZERO */
 #define N_HEADER_IN_TEXT(x) 1
-#define N_SHARED_LIB(x) 0
 #define N_TXTADDR(x) \
     (N_MAGIC(x) != ZMAGIC ? (x).a_entry :      /* object file or NMAGIC */\
            TEXT_START_ADDR + EXEC_BYTES_SIZE   /* no padding */\

diff --git a/bfd/newsos3.c b/bfd/newsos3.c
index 5f8e1f7..650901c 100644 (file)
--- a/bfd/newsos3.c
+++ b/bfd/newsos3.c
@@ -1,5 +1,5 @@
 /* BFD back-end for NewsOS3 (Sony, 68k) binaries.
-   Copyright 1990, 1991, 1994, 1995, 2000, 2001, 2003, 2005, 2007
+   Copyright 1990, 1991, 1994, 1995, 2000, 2001, 2003, 2005, 2007, 2009
    Free Software Foundation, Inc.
 
    This file is part of BFD, the Binary File Descriptor library.
@@ -29,7 +29,6 @@
 #define MY(OP) CONCAT2 (newsos3_,OP)
 #define TARGETNAME "a.out-newsos3"
 #define ENTRY_CAN_BE_ZERO
-#define N_SHARED_LIB(x) 0 /* Avoids warning when compiled with -Wall.  */
 #define DEFAULT_ARCH bfd_arch_m68k
 #define TARGET_IS_BIG_ENDIAN_P
 #define N_HEADER_IN_TEXT(x) 0

diff --git a/bfd/pc532-mach.c b/bfd/pc532-mach.c
index e466536..b472006 100644 (file)
--- a/bfd/pc532-mach.c
+++ b/bfd/pc532-mach.c
@@ -1,5 +1,5 @@
 /* BFD back-end for Mach3/532 a.out-ish binaries.
-   Copyright 1990, 1991, 1992, 1994, 1995, 2000, 2001, 2002, 2005, 2007
+   Copyright 1990, 1991, 1992, 1994, 1995, 2000, 2001, 2002, 2005, 2007, 2009
    Free Software Foundation, Inc.
 
    This file is part of BFD, the Binary File Descriptor library.
@@ -46,7 +46,6 @@
 
 #define        SEGMENT_SIZE    TARGET_PAGE_SIZE
 
-#define N_SHARED_LIB(x) 0
 #define SEGMENT_SIZE TARGET_PAGE_SIZE
 #define DEFAULT_ARCH bfd_arch_ns32k
 

diff --git a/bfd/pdp11.c b/bfd/pdp11.c
index 620d218..e4096f3 100644 (file)
--- a/bfd/pdp11.c
+++ b/bfd/pdp11.c
@@ -58,9 +58,6 @@
 /* The header is not included in the text segment.  */
 #define N_HEADER_IN_TEXT(x)    0
 
-/* There are no shared libraries.  */
-#define N_SHARED_LIB(x)        0
-
 /* There is no flags field.  */
 #define N_FLAGS(exec)          0
 

diff --git a/bfd/po/es.po b/bfd/po/es.po
index e4410d7..da410ee 100644 (file)
--- a/bfd/po/es.po
+++ b/bfd/po/es.po
@@ -1,14 +1,14 @@
-# Mensajes en español para bfd 2.18.90.
+# Mensajes en español para bfd 2.19.90.
 # Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
 # This file is distributed under the same license as the binutils package.
 # Cristian Othón Martínez Vera <cfuga@itam.mx>, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
 #
 msgid ""
 msgstr ""
-"Project-Id-Version: bfd 2.18.90\n"
+"Project-Id-Version: bfd 2.19.90\n"
 "Report-Msgid-Bugs-To: bug-binutils@gnu.org\n"
-"POT-Creation-Date: 2008-09-09 15:56+0930\n"
-"PO-Revision-Date: 2009-03-03 22:20-0600\n"
+"POT-Creation-Date: 2009-09-07 14:05+0200\n"
+"PO-Revision-Date: 2009-09-12 14:44-0500\n"
 "Last-Translator: Cristian Othón Martínez Vera <cfuga@itam.mx>\n"
 "Language-Team: Spanish <es@li.org>\n"
 "MIME-Version: 1.0\n"
@@ -22,162 +22,162 @@ msgstr "%B: Tipo de secci
 #: aout-cris.c:204
 #, c-format
 msgid "%s: Invalid relocation type exported: %d"
-msgstr "%s: Tipo de reubicación exportado inválido: %d"
+msgstr "%s: Se exportó un tipo de reubicación inválido: %d"
 
 #: aout-cris.c:247
 msgid "%B: Invalid relocation type imported: %d"
-msgstr "%B: Tipo de reubicación importado inválido: %d"
+msgstr "%B: Se importó un tipo de reubicación inválido: %d"
 
 #: aout-cris.c:258
 msgid "%B: Bad relocation record imported: %d"
-msgstr "%B: Registro de reubicación importado erróneo: %d"
+msgstr "%B: Se importó un registro de reubicación erróneo: %d"
 
-#: aoutx.h:1268 aoutx.h:1604
+#: aoutx.h:1271 aoutx.h:1609
 #, c-format
 msgid "%s: can not represent section `%s' in a.out object file format"
-msgstr "%s: no se puede representar la sección `%s' en el fichero objeto de formato a.out"
+msgstr "%s: no se puede representar la sección `%s' en el formato de fichero objeto a.out"
 
-#: aoutx.h:1570
+#: aoutx.h:1575
 #, c-format
 msgid "%s: can not represent section for symbol `%s' in a.out object file format"
-msgstr "%s: no se puede representar la sección para el símbolo `%s' en el fichero objeto de formato a.out"
+msgstr "%s: no se puede representar la sección para el símbolo `%s' en el formato de fichero objeto a.out"
 
-#: aoutx.h:1572
+#: aoutx.h:1577
 msgid "*unknown*"
 msgstr "*desconocido*"
 
-#: aoutx.h:3989 aoutx.h:4315
+#: aoutx.h:3994 aoutx.h:4320
 msgid "%P: %B: unexpected relocation type\n"
 msgstr "%P: %B: tipo de reubicación inesperado\n"
 
-#: aoutx.h:5349
+#: aoutx.h:5354
 #, c-format
 msgid "%s: relocatable link from %s to %s not supported"
 msgstr "%s: no se admite el enlace reubicable de %s a %s"
 
-#: archive.c:2046
+#: archive.c:2056
 msgid "Warning: writing archive was slow: rewriting timestamp\n"
 msgstr "Aviso: la escritura del fichero fue lenta: se reescribe la marca de tiempo\n"
 
 # ¡Uff! Si utilizáramos file=archivo, esta traducción sería imposible. cfuga
-#: archive.c:2309
+#: archive.c:2342
 msgid "Reading archive file mod timestamp"
-msgstr "Se lee el archivo de la modificación de marca de tiempo del fichero"
+msgstr "Se lee la marca de tiempo modificada del fichero en el archivo"
 
-#: archive.c:2333
+#: archive.c:2366
 msgid "Writing updated armap timestamp"
 msgstr "Se escribe la marca de tiempo actualizada de armap"
 
-#: bfd.c:368
+#: bfd.c:375
 msgid "No error"
 msgstr "No hay error"
 
-#: bfd.c:369
+#: bfd.c:376
 msgid "System call error"
 msgstr "Error en la llamada al sistema"
 
-#: bfd.c:370
+#: bfd.c:377
 msgid "Invalid bfd target"
 msgstr "Objetivo bfd inválido"
 
-#: bfd.c:371
+#: bfd.c:378
 msgid "File in wrong format"
 msgstr "Fichero en formato erróneo"
 
-#: bfd.c:372
+#: bfd.c:379
 msgid "Archive object file in wrong format"
 msgstr "Archivo de ficheros objeto en formato erróneo"
 
-#: bfd.c:373
+#: bfd.c:380
 msgid "Invalid operation"
 msgstr "Operación inválida"
 
-#: bfd.c:374
+#: bfd.c:381
 msgid "Memory exhausted"
 msgstr "Memoria agotada"
 
-#: bfd.c:375
+#: bfd.c:382
 msgid "No symbols"
 msgstr "No hay símbolos"
 
-#: bfd.c:376
+#: bfd.c:383
 msgid "Archive has no index; run ranlib to add one"
 msgstr "El archivo no tiene índice; ejecute ranlib para agregar uno"
 
-#: bfd.c:377
+#: bfd.c:384
 msgid "No more archived files"
 msgstr "No hay más ficheros archivados"
 
-#: bfd.c:378
+#: bfd.c:385
 msgid "Malformed archive"
 msgstr "Archivo malformado"
 
-#: bfd.c:379
+#: bfd.c:386
 msgid "File format not recognized"
 msgstr "No se reconoce el formato del fichero"
 
-#: bfd.c:380
+#: bfd.c:387
 msgid "File format is ambiguous"
 msgstr "El formato del fichero es ambiguo"
 
-#: bfd.c:381
+#: bfd.c:388
 msgid "Section has no contents"
-msgstr "La sección no tiene contenidos"
+msgstr "La sección no tiene contenido"
 
-#: bfd.c:382
+#: bfd.c:389
 msgid "Nonrepresentable section on output"
 msgstr "Sección no representable en la salida"
 
-#: bfd.c:383
+#: bfd.c:390
 msgid "Symbol needs debug section which does not exist"
 msgstr "Un símbolo requiere de una sección de depuración, la cual no existe"
 
-#: bfd.c:384
+#: bfd.c:391
 msgid "Bad value"
 msgstr "Valor erróneo"
 
-#: bfd.c:385
+#: bfd.c:392
 msgid "File truncated"
 msgstr "Fichero truncado"
 
-#: bfd.c:386
+#: bfd.c:393
 msgid "File too big"
-msgstr "Fichero demasiado grande"
+msgstr "El fichero es demasiado grande"
 
-#: bfd.c:387
+#: bfd.c:394
 #, c-format
 msgid "Error reading %s: %s"
 msgstr "Error al leer %s: %s"
 
-#: bfd.c:388
+#: bfd.c:395
 msgid "#<Invalid error code>"
 msgstr "#<Código de error inválido>"
 
-#: bfd.c:912
+#: bfd.c:919
 #, c-format
 msgid "BFD %s assertion fail %s:%d"
 msgstr "falló la aseveración BFD %s %s:%d"
 
-#: bfd.c:924
+#: bfd.c:931
 #, c-format
 msgid "BFD %s internal error, aborting at %s line %d in %s\n"
 msgstr "error interno de BFD %s, se aborta en %s línea %d en %s\n"
 
-#: bfd.c:928
+#: bfd.c:935
 #, c-format
 msgid "BFD %s internal error, aborting at %s line %d\n"
 msgstr "error interno de BFD %s, se aborta en %s línea %d\n"
 
-#: bfd.c:930
+#: bfd.c:937
 msgid "Please report this bug.\n"
 msgstr "Por favor reporte este bicho.\n"
 
-#: bfdwin.c:208
+#: bfdwin.c:206
 #, c-format
 msgid "not mapping: data=%lx mapped=%d\n"
 msgstr "no se mapea: datos=%lx mapeados%d\n"
 
-#: bfdwin.c:211
+#: bfdwin.c:209
 #, c-format
 msgid "not mapping: env var not set\n"
 msgstr "no se mapea: no se estableció la variable de ambiente\n"
@@ -187,7 +187,13 @@ msgstr "no se mapea: no se estableci
 msgid "Warning: Writing section `%s' to huge (ie negative) file offset 0x%lx."
 msgstr "Aviso: Se escribe la sección `%s' a un desplazamiento de fichero grande (pe negativo) 0x%lx."
 
-#: cache.c:222
+#: bout.c:1150 elf-m10300.c:2078 elf32-avr.c:1639 elf32-frv.c:5743
+#: elf32-xtensa.c:6639 elfxx-sparc.c:2456 reloc.c:5386 reloc16.c:162
+#: vms.c:1918 elf32-ia64.c:788 elf64-ia64.c:788
+msgid "%P%F: --relax and -r may not be used together\n"
+msgstr "%P%F: --relax y -r no se pueden usar juntos\n"
+
+#: cache.c:226
 msgid "reopening %B: %s\n"
 msgstr "se reabre %B: %s\n"
 
@@ -205,7 +211,7 @@ msgstr "%B: tipo de reubicaci
 
 #: coff-alpha.c:899 coff-alpha.c:936 coff-alpha.c:2024 coff-mips.c:1003
 msgid "GP relative relocation used when GP not defined"
-msgstr "se usó una reubicación GP relativa cuando GP no estaba definido"
+msgstr "se usó una reubicación relativa a GP cuando GP no estaba definido"
 
 #: coff-alpha.c:1501
 msgid "using multiple gp values"
@@ -219,8 +225,8 @@ msgstr "%B: tipo de reubicaci
 msgid "%B: unsupported relocation: ALPHA_R_GPRELLOW"
 msgstr "%B: tipo de reubicación no admitida: ALPHA_R_GPRELLOW"
 
-#: coff-alpha.c:1574 elf32-m32r.c:2487 elf64-alpha.c:3970 elf64-alpha.c:4125
-#: elf32-ia64.c:4465 elf64-ia64.c:4465
+#: coff-alpha.c:1574 elf32-m32r.c:2477 elf64-alpha.c:3943 elf64-alpha.c:4098
+#: elf32-ia64.c:4462 elf64-ia64.c:4462
 msgid "%B: unknown relocation type %d"
 msgstr "%B: tipo de reubicación %d desconocido"
 
@@ -234,7 +240,7 @@ msgstr "%B: no se puede encontrar el pegamento THUMB '%s' para `%s'"
 msgid "%B: unable to find ARM glue '%s' for `%s'"
 msgstr "%B: no se puede encontrar el pegamento ARM '%s' para `%s'"
 
-#: coff-arm.c:1370 elf32-arm.c:5453
+#: coff-arm.c:1370 elf32-arm.c:6372
 #, c-format
 msgid ""
 "%B(%s): warning: interworking not enabled.\n"
@@ -251,10 +257,10 @@ msgid ""
 "  consider relinking with --support-old-code enabled"
 msgstr ""
 "%B(%s): aviso: no se activó la interoperabilidad.\n"
-"  primer suceso: %B: llamada arm a thumb\n"
+"  primer suceso: %B: llamada thumb a arm\n"
 "  considere reenlazar con --support-old-code activado"
 
-#: coff-arm.c:1755 coff-tic80.c:695 cofflink.c:3018
+#: coff-arm.c:1755 coff-tic80.c:695 cofflink.c:3027
 msgid "%B: bad reloc address 0x%lx in section `%A'"
 msgstr "%B: dirección de reubicación 0x%lx errónea en la sección `%A'"
 
@@ -264,35 +270,35 @@ msgstr "%B: 
 
 #: coff-arm.c:2211
 #, c-format
-msgid "ERROR: %B is compiled for APCS-%d, whereas %B is compiled for APCS-%d"
-msgstr "ERROR: %B está compilado para APCS-%d, mientras que %B está compilado para APCS-%d"
+msgid "error: %B is compiled for APCS-%d, whereas %B is compiled for APCS-%d"
+msgstr "error: %B está compilado para APCS-%d, mientras que %B está compilado para APCS-%d"
 
-#: coff-arm.c:2227 elf32-arm.c:8563
+#: coff-arm.c:2227 elf32-arm.c:10327
 #, c-format
-msgid "ERROR: %B passes floats in float registers, whereas %B passes them in integer registers"
-msgstr "ERROR: %B pasa números de coma flotante en registros de coma flotante, mientras que %B los pasa en registros enteros"
+msgid "error: %B passes floats in float registers, whereas %B passes them in integer registers"
+msgstr "error: %B pasa números de coma flotante en registros de coma flotante, mientras que %B los pasa en registros enteros"
 
-#: coff-arm.c:2230 elf32-arm.c:8567
+#: coff-arm.c:2230 elf32-arm.c:10331
 #, c-format
-msgid "ERROR: %B passes floats in integer registers, whereas %B passes them in float registers"
-msgstr "ERROR: %B pasa números de coma flotante en registros enteros, mientras que %B los pasa en registros de coma flotante"
+msgid "error: %B passes floats in integer registers, whereas %B passes them in float registers"
+msgstr "error: %B pasa números de coma flotante en registros enteros, mientras que %B los pasa en registros de coma flotante"
 
 #: coff-arm.c:2244
 #, c-format
-msgid "ERROR: %B is compiled as position independent code, whereas target %B is absolute position"
-msgstr "ERROR: %B está compilado como código independiente de posición, mientras que el objetivo %B es de posición absoluta"
+msgid "error: %B is compiled as position independent code, whereas target %B is absolute position"
+msgstr "error: %B está compilado como código independiente de posición, mientras que el objetivo %B es de posición absoluta"
 
 #: coff-arm.c:2247
 #, c-format
-msgid "ERROR: %B is compiled as absolute position code, whereas target %B is position independent"
-msgstr "ERROR: %B está compilado como código de posición absoluta, mientras que el objetivo %B es independiente de posición"
+msgid "error: %B is compiled as absolute position code, whereas target %B is position independent"
+msgstr "error: %B está compilado como código de posición absoluta, mientras que el objetivo %B es independiente de posición"
 
-#: coff-arm.c:2275 elf32-arm.c:8632
+#: coff-arm.c:2275 elf32-arm.c:10396
 #, c-format
 msgid "Warning: %B supports interworking, whereas %B does not"
 msgstr "Aviso: %B admite interoperabilidad, mientras que %B no"
 
-#: coff-arm.c:2278 elf32-arm.c:8638
+#: coff-arm.c:2278 elf32-arm.c:10402
 #, c-format
 msgid "Warning: %B does not support interworking, whereas %B does"
 msgstr "Aviso: %B no admite interoperabilidad, mientras que %B sí"
@@ -302,7 +308,7 @@ msgstr "Aviso: %B no admite interoperabilidad, mientras que %B s
 msgid "private flags = %x:"
 msgstr "opciones privadas = %x:"
 
-#: coff-arm.c:2310 elf32-arm.c:8689
+#: coff-arm.c:2310 elf32-arm.c:10453
 #, c-format
 msgid " [floats passed in float registers]"
 msgstr "[números de coma flotante pasados en registros de coma flotante]"
@@ -312,7 +318,7 @@ msgstr "[n
 msgid " [floats passed in integer registers]"
 msgstr "[números de coma flotante pasados en registros enteros]"
 
-#: coff-arm.c:2315 elf32-arm.c:8692
+#: coff-arm.c:2315 elf32-arm.c:10456
 #, c-format
 msgid " [position independent]"
 msgstr "[independiente de posición]"
@@ -337,12 +343,12 @@ msgstr "[admite interoperabilidad]"
 msgid " [interworking not supported]"
 msgstr "[no admite interoperabilidad]"
 
-#: coff-arm.c:2371 elf32-arm.c:8050
+#: coff-arm.c:2371 elf32-arm.c:9360
 #, c-format
 msgid "Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"
 msgstr "Aviso: No se establece la opción de interoperabilidad de %B ya que se había especificado con anterioridad como no interoperable"
 
-#: coff-arm.c:2375 elf32-arm.c:8054
+#: coff-arm.c:2375 elf32-arm.c:9364
 #, c-format
 msgid "Warning: Clearing the interworking flag of %B due to outside request"
 msgstr "Aviso: Se limpia la opción de interoperabilidad de %B debido a una petición externa"
@@ -357,7 +363,7 @@ msgstr "no se puede manejar la reubicaci
 msgid "Relocation `%s' not yet implemented\n"
 msgstr "La reubicación `%s' aún no está implementada\n"
 
-#: coff-i860.c:605 coff-tic54x.c:398 coffcode.h:4975
+#: coff-i860.c:605 coff-tic54x.c:398 coffcode.h:5143
 msgid "%B: warning: illegal symbol index %ld in relocs"
 msgstr "%B: aviso: índice de símbolos %ld ilegal en reubicaciones"
 
@@ -365,7 +371,7 @@ msgstr "%B: aviso: 
 msgid "uncertain calling convention for non-COFF symbol"
 msgstr "convención de llamada incierta para un símbolo que no es COFF"
 
-#: coff-m68k.c:506 elf32-bfin.c:5510 elf32-m68k.c:3938
+#: coff-m68k.c:506 elf32-bfin.c:5693 elf32-cr16.c:2965 elf32-m68k.c:4615
 msgid "unsupported reloc type"
 msgstr "no se admite el tipo de reubicación"
 
@@ -387,179 +393,183 @@ msgstr "La direcci
 
 #: coff-maxq.c:333
 msgid "Unrecognized Reloc Type"
-msgstr "Tipo de Reubicación no Reconocida"
+msgstr "No se reconoce el Tipo de Reubicación"
 
-#: coff-mips.c:688 elf32-mips.c:1014 elf32-score.c:345 elf64-mips.c:1991
-#: elfn32-mips.c:1832
+#: coff-mips.c:688 elf32-mips.c:1014 elf32-score.c:441 elf32-score7.c:341
+#: elf64-mips.c:2018 elfn32-mips.c:1832
 msgid "GP relative relocation when _gp not defined"
-msgstr "reubicación GP relativa cuando _gp no está definido"
+msgstr "reubicación relativa a GP cuando _gp no está definido"
 
 #: coff-or32.c:229
 msgid "Unrecognized reloc"
-msgstr "Reubicación no reconocida"
+msgstr "No se reconoce la reubicación"
 
-#: coff-rs6000.c:2803
+#: coff-rs6000.c:2787
 #, c-format
 msgid "%s: unsupported relocation type 0x%02x"
 msgstr "%s: no se admite el tipo de reubicación 0x%02x"
 
-#: coff-rs6000.c:2896
+#: coff-rs6000.c:2880
 #, c-format
 msgid "%s: TOC reloc at 0x%x to symbol `%s' with no TOC entry"
 msgstr "%s: reubicación de TOC en 0x%x al símbolo `%s' sin entrada TOC"
 
-#: coff-rs6000.c:3628 coff64-rs6000.c:2130
+#: coff-rs6000.c:3646 coff64-rs6000.c:2168
 msgid "%B: symbol `%s' has unrecognized smclas %d"
 msgstr "%B: el símbolo `%s' tiene smclas %d que no se reconoce"
 
 #: coff-tic4x.c:195 coff-tic54x.c:299 coff-tic80.c:458
 #, c-format
 msgid "Unrecognized reloc type 0x%x"
-msgstr "Tipo de reubicación 0x%x no reconocida"
+msgstr "No se reconoce el tipo de reubicación 0x%x"
 
 #: coff-tic4x.c:240
 #, c-format
 msgid "%s: warning: illegal symbol index %ld in relocs"
-msgstr "%s: aviso: íncide de símbolos %ld ilegal en reubicaciones"
+msgstr "%s: aviso: índice de símbolos %ld ilegal en reubicaciones"
 
 #: coff-w65.c:367
 #, c-format
 msgid "ignoring reloc %s\n"
 msgstr "se descarta la reubicación %s\n"
 
-#: coffcode.h:850
+#: coffcode.h:960
 msgid "%B: warning: COMDAT symbol '%s' does not match section name '%s'"
 msgstr "%B: aviso: el símbolo COMDAT '%s' no coincide con el nombre de sección '%s'"
 
 #. Generate a warning message rather using the 'unhandled'
 #. variable as this will allow some .sys files generate by
 #. other toolchains to be processed.  See bugzilla issue 196.
-#: coffcode.h:1062
+#: coffcode.h:1176
 msgid "%B: Warning: Ignoring section flag IMAGE_SCN_MEM_NOT_PAGED in section %s"
 msgstr "%B: Aviso: Se descarta la opción de sección IMAGE_SCN_MEM_NOT_PAGED en la sección %s"
 
-#: coffcode.h:1117
+#: coffcode.h:1240
 msgid "%B (%s): Section flag %s (0x%x) ignored"
 msgstr "%B (%s): Se descarta la opción de sección %s (0x%x)"
 
-#: coffcode.h:2244
+#: coffcode.h:2382
 #, c-format
 msgid "Unrecognized TI COFF target id '0x%x'"
-msgstr "No se reconoce el id de objetivo TI COFF '0x%x'"
+msgstr "No se reconoce el id de objetivo COFF TI '0x%x'"
 
-#: coffcode.h:2559
+#: coffcode.h:2696
 msgid "%B: reloc against a non-existant symbol index: %ld"
-msgstr "%B: reubicación contra un índice símbolo que no existe: %ld"
+msgstr "%B: reubicación contra un índice de símbolo que no existe: %ld"
+
+#: coffcode.h:3669
+msgid "%B: section %s: string table overflow at offset %ld"
+msgstr "%B: sección %s: desbordamiento de tabla de cadenas en el desplazamiento %ld"
 
-#: coffcode.h:4309
+#: coffcode.h:4477
 msgid "%B: warning: line number table read failed"
 msgstr "%B: aviso: falló la lectura de tabla de números de línea"
 
-#: coffcode.h:4339
+#: coffcode.h:4507
 msgid "%B: warning: illegal symbol index %ld in line numbers"
 msgstr "%B: aviso: índice de símbolos %ld ilegal en los números de línea"
 
-#: coffcode.h:4353
+#: coffcode.h:4521
 msgid "%B: warning: duplicate line number information for `%s'"
-msgstr "%B: aviso: información duplicada de números de línea para `%s'"
+msgstr "%B: aviso: información de números de línea duplicada para `%s'"
 
-#: coffcode.h:4744
+#: coffcode.h:4912
 msgid "%B: Unrecognized storage class %d for %s symbol `%s'"
-msgstr "%B: Clase de almacenamiento %d no reconocida para %s símbolo `%s'"
+msgstr "%B: No se reconoce la clase de almacenamiento %d para %s símbolo `%s'"
 
-#: coffcode.h:4870
+#: coffcode.h:5038
 msgid "warning: %B: local symbol `%s' has no section"
 msgstr "aviso: %B: el símbolo local `%s' no tiene sección"
 
-#: coffcode.h:5013
+#: coffcode.h:5181
 msgid "%B: illegal relocation type %d at address 0x%lx"
 msgstr "%B: tipo de reubicación %d ilegal en la dirección 0x%lx"
 
-#: coffgen.c:1518
+#: coffgen.c:1571
 msgid "%B: bad string table size %lu"
 msgstr "%B: tamaño de tabla de cadenas %lu erróneo"
 
-#: cofflink.c:513 elflink.c:4218
+#: cofflink.c:513 elflink.c:4307
 msgid "Warning: type of symbol `%s' changed from %d to %d in %B"
 msgstr "Aviso: el tipo del símbolo `%s' cambió de %d a %d en %B"
 
-#: cofflink.c:2296
+#: cofflink.c:2305
 msgid "%B: relocs in section `%A', but it has no contents"
 msgstr "%B: reubicaciones en la sección `%A', pero no tiene contenido"
 
-#: cofflink.c:2627 coffswap.h:824
+#: cofflink.c:2636 coffswap.h:826
 #, c-format
 msgid "%s: %s: reloc overflow: 0x%lx > 0xffff"
 msgstr "%s: %s: desbordamiento de reubicación: 0x%lx > 0xffff"
 
-#: cofflink.c:2636 coffswap.h:810
+#: cofflink.c:2645 coffswap.h:812
 #, c-format
 msgid "%s: warning: %s: line number overflow: 0x%lx > 0xffff"
 msgstr "%s: aviso: %s: desbordamiento de número de línea: 0x%lx > 0xffff"
 
 #: cpu-arm.c:189 cpu-arm.c:200
-msgid "ERROR: %B is compiled for the EP9312, whereas %B is compiled for XScale"
-msgstr "ERROR: %B está compilado para el EP9312, mientras que %B está compilado para XScale"
+msgid "error: %B is compiled for the EP9312, whereas %B is compiled for XScale"
+msgstr "error: %B está compilado para el EP9312, mientras que %B está compilado para XScale"
 
 #: cpu-arm.c:332
 #, c-format
 msgid "warning: unable to update contents of %s section in %s"
 msgstr "aviso: no se puede actualizar el contenido de la sección %s en %s"
 
-#: dwarf2.c:424
+#: dwarf2.c:430
 #, c-format
 msgid "Dwarf Error: Can't find %s section."
 msgstr "Error de Dwarf: No se puede encontrar la sección %s."
 
-#: dwarf2.c:452
+#: dwarf2.c:457
 #, c-format
 msgid "Dwarf Error: unable to decompress %s section."
 msgstr "Error de Dwarf: no se puede descomprimir la sección %s."
 
-#: dwarf2.c:462
+#: dwarf2.c:468
 #, c-format
 msgid "Dwarf Error: Offset (%lu) greater than or equal to %s size (%lu)."
 msgstr "Error de Dwarf: El desplazamiento (%lu) es mayor que o igual que el tamaño de %s (%lu)."
 
-#: dwarf2.c:849
+#: dwarf2.c:865
 #, c-format
 msgid "Dwarf Error: Invalid or unhandled FORM value: %u."
-msgstr "Error de Dwarf: Valor de FORM inválido o no manejado: %u."
+msgstr "Error de Dwarf: Valor de FORM sin manejar o inválido: %u."
 
-#: dwarf2.c:1063
+#: dwarf2.c:1079
 msgid "Dwarf Error: mangled line number section (bad file number)."
-msgstr "Error de Dwarf: sección de números de línea revuelta (número erróneo de fichero)."
+msgstr "Error de Dwarf: sección de números de línea revuelta (número de fichero erróneo)."
 
-#: dwarf2.c:1393
+#: dwarf2.c:1413
 msgid "Dwarf Error: mangled line number section."
 msgstr "Error de Dwarf: sección de números de línea revuelta."
 
-#: dwarf2.c:1726 dwarf2.c:1842 dwarf2.c:2114
+#: dwarf2.c:1760 dwarf2.c:1867 dwarf2.c:2139
 #, c-format
 msgid "Dwarf Error: Could not find abbrev number %u."
 msgstr "Error de Dwarf: No se puede encontrar el número de abreviatura %u."
 
-#: dwarf2.c:2075
+#: dwarf2.c:2100
 #, c-format
-msgid "Dwarf Error: found dwarf version '%u', this reader only handles version 2 information."
-msgstr "Error de Dwarf: se encontró la versión de dwarf '%u', este lector solamente maneja información de la versión 2."
+msgid "Dwarf Error: found dwarf version '%u', this reader only handles version 2 and 3 information."
+msgstr "Error de Dwarf: se encontró la versión de dwarf '%u', este lector solamente maneja información de las versiones 2 y 3."
 
-#: dwarf2.c:2082
+#: dwarf2.c:2107
 #, c-format
 msgid "Dwarf Error: found address size '%u', this reader can not handle sizes greater than '%u'."
 msgstr "Error de Dwarf: se encontró el tamaño de dirección '%u', este lector no puede manejar tamaños más grandes que '%u'."
 
-#: dwarf2.c:2105
+#: dwarf2.c:2130
 #, c-format
 msgid "Dwarf Error: Bad abbrev number: %u."
 msgstr "Error de Dwarf: Número de abreviación erróneo: %u."
 
-#: ecoff.c:1227
+#: ecoff.c:1238
 #, c-format
 msgid "Unknown basic type %d"
 msgstr "Tipo básico %d desconocido"
 
-#: ecoff.c:1484
+#: ecoff.c:1495
 #, c-format
 msgid ""
 "\n"
@@ -568,7 +578,7 @@ msgstr ""
 "\n"
 "      Símbolo final+1: %ld"
 
-#: ecoff.c:1491 ecoff.c:1494
+#: ecoff.c:1502 ecoff.c:1505
 #, c-format
 msgid ""
 "\n"
@@ -577,7 +587,7 @@ msgstr ""
 "\n"
 "      Primer símbolo: %ld"
 
-#: ecoff.c:1506
+#: ecoff.c:1517
 #, c-format
 msgid ""
 "\n"
@@ -586,7 +596,7 @@ msgstr ""
 "\n"
 "      Símbolo final+1: %-7ld Tipo: %s"
 
-#: ecoff.c:1513
+#: ecoff.c:1524
 #, c-format
 msgid ""
 "\n"
@@ -595,7 +605,7 @@ msgstr ""
 "\n"
 "      Símbolo local: %ld"
 
-#: ecoff.c:1521
+#: ecoff.c:1532
 #, c-format
 msgid ""
 "\n"
@@ -604,7 +614,7 @@ msgstr ""
 "\n"
 "      struct; símbolo final+1: %ld"
 
-#: ecoff.c:1526
+#: ecoff.c:1537
 #, c-format
 msgid ""
 "\n"
@@ -613,7 +623,7 @@ msgstr ""
 "\n"
 "      union; símbolo final+1: %ld"
 
-#: ecoff.c:1531
+#: ecoff.c:1542
 #, c-format
 msgid ""
 "\n"
@@ -622,7 +632,7 @@ msgstr ""
 "\n"
 "      enum; símbolo final+1: %ld"
 
-#: ecoff.c:1537
+#: ecoff.c:1548
 #, c-format
 msgid ""
 "\n"
@@ -631,119 +641,124 @@ msgstr ""
 "\n"
 "      Tipo: %s"
 
-#: elf-attrs.c:582
-msgid "ERROR: %B: Must be processed by '%s' toolchain"
-msgstr "ERROR: %B: Se debe procesar por la cadena de compilación '%s'"
+#: elf-attrs.c:567
+msgid "error: %B: Must be processed by '%s' toolchain"
+msgstr "error: %B: Se debe procesar por la cadena de compilación '%s'"
 
-#: elf-attrs.c:602 elf-attrs.c:621
-msgid "ERROR: %B: Incompatible object tag '%s':%d"
-msgstr "ERROR: %B: Etiqueta de objeto '%s' incompatible:%d"
+#: elf-attrs.c:575
+msgid "error: %B: Object tag '%d, %s' is incompatible with tag '%d, %s'"
+msgstr "error: %B: La etiqueta de objeto '%d, %s' es incompatible con la etiqueta '%d, %s'"
 
-#: elf-eh-frame.c:866
+#: elf-eh-frame.c:884
 msgid "%P: error in %B(%A); no .eh_frame_hdr table will be created.\n"
 msgstr "%P: error en %B(%A); no se creará la tabla .eh_frame_hdr.\n"
 
-#: elf-eh-frame.c:1102
+#: elf-eh-frame.c:1122
 msgid "%P: fde encoding in %B(%A) prevents .eh_frame_hdr table being created.\n"
 msgstr "%P: la codificación fde en %B(%A) previene la creación de la tabla .eh_frame_hdr.\n"
 
-#: elf-hppa.h:2241 elf-m10300.c:1546 elf32-arm.c:7954 elf32-i386.c:3582
-#: elf32-m32r.c:2598 elf32-m68k.c:3516 elf32-ppc.c:7223 elf32-s390.c:3058
-#: elf32-sh.c:3438 elf32-xtensa.c:3021 elf64-ppc.c:11528 elf64-s390.c:3019
-#: elf64-sh64.c:1648 elf64-x86-64.c:3239 elfxx-sparc.c:3336
-msgid "%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"
-msgstr "%B(%A+0x%lx): reubicación %s sin resolución contra el símbolo `%s'"
-
-#: elf-hppa.h:2266 elf-hppa.h:2280
-msgid "%B(%A): warning: unresolvable relocation against symbol `%s'"
-msgstr "%B(%A): aviso: reubicación sin resolución contra el símbolo `%s'"
+#: elf-ifunc.c:179
+msgid "%F%P: dynamic STT_GNU_IFUNC symbol `%s' with pointer equality in `%B' can not be used when making an executable; recompile with -fPIE and relink with -pie\n"
+msgstr "%F%P: el símbolo STT_GNU_IFUNC dinámico `%s' con igualdad de puntero en `%B' no se puede usar al hacer un ejecutable; recompile con -fPIE y reenlace con -pie\n"
 
-#: elf-m10200.c:456 elf-m10300.c:1609 elf32-avr.c:1250 elf32-bfin.c:3214
-#: elf32-cr16.c:959 elf32-cr16c.c:790 elf32-cris.c:1538 elf32-crx.c:933
+#: elf-m10200.c:456 elf-m10300.c:1575 elf32-avr.c:1251 elf32-bfin.c:3200
+#: elf32-cr16.c:1517 elf32-cr16c.c:790 elf32-cris.c:2089 elf32-crx.c:933
 #: elf32-d10v.c:516 elf32-fr30.c:616 elf32-frv.c:4114 elf32-h8300.c:516
-#: elf32-i860.c:1218 elf32-ip2k.c:1499 elf32-iq2000.c:691 elf32-m32c.c:560
-#: elf32-m32r.c:3124 elf32-m68hc1x.c:1135 elf32-mep.c:541 elf32-msp430.c:493
-#: elf32-mt.c:402 elf32-openrisc.c:411 elf32-score.c:2451 elf32-spu.c:4132
-#: elf32-v850.c:1703 elf32-xstormy16.c:948 elf64-mmix.c:1533
+#: elf32-i860.c:1218 elf32-ip2k.c:1499 elf32-iq2000.c:691 elf32-lm32.c:1171
+#: elf32-m32c.c:560 elf32-m32r.c:3102 elf32-m68hc1x.c:1136 elf32-mep.c:541
+#: elf32-microblaze.c:1226 elf32-moxie.c:291 elf32-msp430.c:493 elf32-mt.c:402
+#: elf32-openrisc.c:411 elf32-score.c:2752 elf32-score7.c:2591
+#: elf32-spu.c:5045 elf32-v850.c:1701 elf32-xstormy16.c:948 elf64-mmix.c:1533
 msgid "internal error: out of range error"
 msgstr "error interno: error fuera de rango"
 
-#: elf-m10200.c:460 elf-m10300.c:1613 elf32-avr.c:1254 elf32-bfin.c:3218
-#: elf32-cr16.c:963 elf32-cr16c.c:794 elf32-cris.c:1542 elf32-crx.c:937
+#: elf-m10200.c:460 elf-m10300.c:1579 elf32-avr.c:1255 elf32-bfin.c:3204
+#: elf32-cr16.c:1521 elf32-cr16c.c:794 elf32-cris.c:2093 elf32-crx.c:937
 #: elf32-d10v.c:520 elf32-fr30.c:620 elf32-frv.c:4118 elf32-h8300.c:520
-#: elf32-i860.c:1222 elf32-iq2000.c:695 elf32-m32c.c:564 elf32-m32r.c:3128
-#: elf32-m68hc1x.c:1139 elf32-mep.c:545 elf32-msp430.c:497
-#: elf32-openrisc.c:415 elf32-score.c:2455 elf32-spu.c:4136 elf32-v850.c:1707
-#: elf32-xstormy16.c:952 elf64-mmix.c:1537 elfxx-mips.c:9065
+#: elf32-i860.c:1222 elf32-iq2000.c:695 elf32-lm32.c:1175 elf32-m32c.c:564
+#: elf32-m32r.c:3106 elf32-m68hc1x.c:1140 elf32-mep.c:545
+#: elf32-microblaze.c:1230 elf32-moxie.c:295 elf32-msp430.c:497
+#: elf32-openrisc.c:415 elf32-score.c:2756 elf32-score7.c:2595
+#: elf32-spu.c:5049 elf32-v850.c:1705 elf32-xstormy16.c:952 elf64-mmix.c:1537
+#: elfxx-mips.c:9103
 msgid "internal error: unsupported relocation error"
-msgstr "error interno: error de reubicación no admitida"
+msgstr "error interno: no se admite el error de reubicación"
 
-#: elf-m10200.c:464 elf32-cr16.c:967 elf32-cr16c.c:798 elf32-crx.c:941
-#: elf32-d10v.c:524 elf32-h8300.c:524 elf32-m32r.c:3132 elf32-m68hc1x.c:1143
-#: elf32-score.c:2459 elf32-spu.c:4140
+#: elf-m10200.c:464 elf32-cr16.c:1525 elf32-cr16c.c:798 elf32-crx.c:941
+#: elf32-d10v.c:524 elf32-h8300.c:524 elf32-lm32.c:1179 elf32-m32r.c:3110
+#: elf32-m68hc1x.c:1144 elf32-microblaze.c:1234 elf32-score.c:2760
+#: elf32-score7.c:2599 elf32-spu.c:5053
 msgid "internal error: dangerous error"
 msgstr "error interno: error peligroso"
 
-#: elf-m10200.c:468 elf-m10300.c:1626 elf32-avr.c:1262 elf32-bfin.c:3226
-#: elf32-cr16.c:971 elf32-cr16c.c:802 elf32-cris.c:1550 elf32-crx.c:945
+#: elf-m10200.c:468 elf-m10300.c:1592 elf32-avr.c:1263 elf32-bfin.c:3212
+#: elf32-cr16.c:1529 elf32-cr16c.c:802 elf32-cris.c:2101 elf32-crx.c:945
 #: elf32-d10v.c:528 elf32-fr30.c:628 elf32-frv.c:4126 elf32-h8300.c:528
-#: elf32-i860.c:1230 elf32-ip2k.c:1514 elf32-iq2000.c:703 elf32-m32c.c:572
-#: elf32-m32r.c:3136 elf32-m68hc1x.c:1147 elf32-mep.c:553 elf32-msp430.c:505
-#: elf32-mt.c:410 elf32-openrisc.c:423 elf32-score.c:2463 elf32-spu.c:4144
-#: elf32-v850.c:1727 elf32-xstormy16.c:960 elf64-mmix.c:1545
+#: elf32-i860.c:1230 elf32-ip2k.c:1514 elf32-iq2000.c:703 elf32-lm32.c:1183
+#: elf32-m32c.c:572 elf32-m32r.c:3114 elf32-m68hc1x.c:1148 elf32-mep.c:553
+#: elf32-microblaze.c:1238 elf32-moxie.c:303 elf32-msp430.c:505 elf32-mt.c:410
+#: elf32-openrisc.c:423 elf32-score.c:2769 elf32-score7.c:2603
+#: elf32-spu.c:5057 elf32-v850.c:1725 elf32-xstormy16.c:960 elf64-mmix.c:1545
 msgid "internal error: unknown error"
 msgstr "error interno: error desconocido"
 
-#: elf-m10300.c:1618
+#: elf-m10300.c:1512 elf32-arm.c:8963 elf32-i386.c:3984 elf32-m32r.c:2588
+#: elf32-m68k.c:4099 elf32-ppc.c:7906 elf32-s390.c:3015 elf32-sh.c:3429
+#: elf32-xtensa.c:3027 elf64-ppc.c:12063 elf64-s390.c:2974 elf64-sh64.c:1648
+#: elf64-x86-64.c:3657 elfxx-sparc.c:3317
+msgid "%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"
+msgstr "%B(%A+0x%lx): reubicación %s sin resolución contra el símbolo `%s'"
+
+#: elf-m10300.c:1584
 msgid "error: inappropriate relocation type for shared library (did you forget -fpic?)"
 msgstr "error: tipo de reubicación inapropiada para la biblioteca compartida (¿olvidó -fpic?)"
 
-#: elf-m10300.c:1621
+#: elf-m10300.c:1587
 msgid "internal error: suspicious relocation type used in shared library"
-msgstr "error interno: se usó un tipo de reubicación sospechosa en una biblioteca compartida"
+msgstr "error interno: se usó un tipo de reubicación sospechosa en la biblioteca compartida"
 
-#: elf-m10300.c:4397 elf32-arm.c:9578 elf32-cris.c:2403 elf32-hppa.c:1921
-#: elf32-i370.c:506 elf32-i386.c:1807 elf32-m32r.c:1931 elf32-m68k.c:2787
-#: elf32-ppc.c:4693 elf32-s390.c:1687 elf32-sh.c:2583 elf32-vax.c:1055
-#: elf64-ppc.c:6075 elf64-s390.c:1662 elf64-sh64.c:3432 elf64-x86-64.c:1641
-#: elfxx-sparc.c:1828
+#: elf-m10300.c:4385 elf32-arm.c:11346 elf32-cr16.c:2519 elf32-cris.c:3030
+#: elf32-hppa.c:1891 elf32-i370.c:506 elf32-i386.c:1975 elf32-lm32.c:1873
+#: elf32-m32r.c:1921 elf32-m68k.c:3188 elf32-ppc.c:4953 elf32-s390.c:1650
+#: elf32-sh.c:2574 elf32-vax.c:1052 elf64-ppc.c:6348 elf64-s390.c:1623
+#: elf64-sh64.c:3396 elf64-x86-64.c:1821 elfxx-sparc.c:1802
 #, c-format
 msgid "dynamic variable `%s' is zero size"
 msgstr "la variable dinámica `%s' es de tamaño cero"
 
-#: elf.c:328
+#: elf.c:329
 msgid "%B: invalid string offset %u >= %lu for section `%s'"
 msgstr "%B: desplazamiento de cadena inválido %u >= %lu para la sección `%s'"
 
-#: elf.c:438
+#: elf.c:439
 msgid "%B symbol number %lu references nonexistent SHT_SYMTAB_SHNDX section"
 msgstr "%B el número de símbolo %lu hace referencia a la sección inexistente SHT_SYMTAB_SHNDX"
 
-#: elf.c:594
+#: elf.c:595
 msgid "%B: Corrupt size field in group section header: 0x%lx"
-msgstr "%B: Tamaño de campo corrupto en el encabezado de la sección de grupo: 0x%lx"
+msgstr "%B: Campo de tamaño corrupto en el encabezado de la sección de grupo: 0x%lx"
 
-#: elf.c:630
+#: elf.c:631
 msgid "%B: invalid SHT_GROUP entry"
 msgstr "%B: entrada SHT_GROUP inválida"
 
-#: elf.c:700
+#: elf.c:701
 msgid "%B: no group info for section %A"
 msgstr "%B: no hay información de grupo para la sección %A"
 
-#: elf.c:729 elf.c:2976 elflink.c:9746
+#: elf.c:730 elf.c:2960 elflink.c:9912
 msgid "%B: warning: sh_link not set for section `%A'"
-msgstr "%B: aviso: no se estableción sh_link para la sección `%A'"
+msgstr "%B: aviso: no se estableció sh_link para la sección `%A'"
 
-#: elf.c:748
+#: elf.c:749
 msgid "%B: sh_link [%d] in section `%A' is incorrect"
 msgstr "%B: sh_link [%d] en la sección `%A', es incorrecto"
 
-#: elf.c:783
+#: elf.c:784
 msgid "%B: unknown [%d] section `%s' in group [%s]"
 msgstr "%B: sección [%d] desconocida `%s' en el grupo [%s]"
 
-#: elf.c:1159
+#: elf.c:1104
 #, c-format
 msgid ""
 "\n"
@@ -752,7 +767,7 @@ msgstr ""
 "\n"
 "Encabezado del Programa:\n"
 
-#: elf.c:1201
+#: elf.c:1146
 #, c-format
 msgid ""
 "\n"
@@ -761,7 +776,7 @@ msgstr ""
 "\n"
 "Sección Dinámica:\n"
 
-#: elf.c:1337
+#: elf.c:1282
 #, c-format
 msgid ""
 "\n"
@@ -770,496 +785,550 @@ msgstr ""
 "\n"
 "Definiciones de versión:\n"
 
-#: elf.c:1362
+#: elf.c:1307
 #, c-format
 msgid ""
 "\n"
 "Version References:\n"
 msgstr ""
 "\n"
-"Referencias de Versión:\n"
+"Referencias de versión:\n"
 
-#: elf.c:1367
+#: elf.c:1312
 #, c-format
 msgid "  required from %s:\n"
-msgstr "  requerido desde %s:\n"
+msgstr "  se requere desde %s:\n"
 
-#: elf.c:1755
+#: elf.c:1702
 msgid "%B: invalid link %lu for reloc section %s (index %u)"
 msgstr "%B: enlace %lu inválido para la sección de reubicación %s (índice %u)"
 
-#: elf.c:1924
+#: elf.c:1870
 msgid "%B: don't know how to handle allocated, application specific section `%s' [0x%8x]"
-msgstr "%B: no se sabe cómo manejar lo reservado, aplicación específica de la sección `%s' [0x%8x]"
+msgstr "%B: no se sabe cómo manejar la sección específica alojada de la aplicación `%s' [0x%8x]"
 
-#: elf.c:1936
+#: elf.c:1882
 msgid "%B: don't know how to handle processor specific section `%s' [0x%8x]"
 msgstr "%B: no se sabe cómo manejar la sección específica de procesador `%s' [0x%8x]"
 
-#: elf.c:1947
+#: elf.c:1893
 msgid "%B: don't know how to handle OS specific section `%s' [0x%8x]"
 msgstr "%B: no se sabe cómo manejar la sección específica de SO `%s' [0x%8x]"
 
-#: elf.c:1957
+#: elf.c:1903
 msgid "%B: don't know how to handle section `%s' [0x%8x]"
 msgstr "%B: no se sabe cómo manejar la sección `%s' [0x%8x]"
 
-#: elf.c:2555
+#: elf.c:2500
 #, c-format
 msgid "warning: section `%A' type changed to PROGBITS"
 msgstr "aviso: el tipo de la sección `%A' cambió a PROGBITS"
 
-#: elf.c:2933
+#: elf.c:2917
 msgid "%B: sh_link of section `%A' points to discarded section `%A' of `%B'"
 msgstr "%B: sh_link de la sección `%A' apunta a la sección descartada `%A' de `%B'"
 
-#: elf.c:2956
+#: elf.c:2940
 msgid "%B: sh_link of section `%A' points to removed section `%A' of `%B'"
-msgstr "%B: sh_link de la sección `%A' apunta a la sección descartada `%A' de `%B'"
+msgstr "%B: sh_link de la sección `%A' apunta a la sección eliminada `%A' de `%B'"
 
-#: elf.c:4300
+#: elf.c:4311
 msgid "%B: The first section in the PT_DYNAMIC segment is not the .dynamic section"
 msgstr "%B: La primera sección en el segmento PT_DYNAMIC no es la sección .dynamic"
 
-#: elf.c:4327
+#: elf.c:4338
 msgid "%B: Not enough room for program headers, try linking with -N"
 msgstr "%B: No hay suficiente espacio para los encabezados del programa, pruebe enlazar con -N"
 
-#: elf.c:4404
+#: elf.c:4420
 msgid "%B: section %A vma 0x%lx overlaps previous sections"
 msgstr "%B: la sección %A vma 0x%lx traslapa las secciones anteriores"
 
-#: elf.c:4499
+#: elf.c:4515
 msgid "%B: section `%A' can't be allocated in segment %d"
 msgstr "%B: la sección `%A' no se puede asignar en el segmento %d"
 
-#: elf.c:4549
+#: elf.c:4565
 msgid "%B: warning: allocated section `%s' not in segment"
 msgstr "%B: aviso: la sección asignada `%s' no está en el segmento"
 
-#: elf.c:5064
+#: elf.c:5065
 msgid "%B: symbol `%s' required but not present"
 msgstr "%B: se requiere el símbolo `%s' pero no está presente"
 
-#: elf.c:5403
+#: elf.c:5404
 msgid "%B: warning: Empty loadable segment detected, is this intentional ?\n"
 msgstr "%B: aviso: Se detectó un segmento cargable vacío, ¿ esto es intencional ?\n"
 
-#: elf.c:6366
+#: elf.c:6370
 #, c-format
 msgid "Unable to find equivalent output section for symbol '%s' from section '%s'"
 msgstr "No se puede encontrar la sección de salida equivalente para el símbolo '%s' de la sección '%s'"
 
-#: elf.c:7346
+#: elf.c:7356
 msgid "%B: unsupported relocation type %s"
 msgstr "%B: no se admite el tipo de reubicación %s"
 
-#: elf32-arm.c:2846 elf32-arm.c:2878
+#: elf32-arm.c:3149
 msgid ""
 "%B(%s): warning: interworking not enabled.\n"
 "  first occurrence: %B: Thumb call to ARM"
 msgstr ""
 "%B(%s): aviso: no se activó la interoperabilidad.\n"
-"  primer suceso: %B: llamada Thumb para ARM"
+"  primer suceso: %B: llamada Thumb a ARM"
 
-#: elf32-arm.c:3041
+#: elf32-arm.c:3190
+msgid ""
+"%B(%s): warning: interworking not enabled.\n"
+"  first occurrence: %B: ARM call to Thumb"
+msgstr ""
+"%B(%s): aviso: no se activó la interoperabilidad.\n"
+"  primer suceso: %B: llamada ARM a Thumb"
+
+#: elf32-arm.c:3387 elf32-arm.c:4692
 #, c-format
 msgid "%s: cannot create stub entry %s"
 msgstr "%s: no se puede crear la entrada de cabo %s"
 
-#: elf32-arm.c:3825
+#: elf32-arm.c:4804
 #, c-format
 msgid "unable to find THUMB glue '%s' for '%s'"
 msgstr "no se puede encontrar el pegamento THUMB '%s' para `%s'"
 
-#: elf32-arm.c:3859
+#: elf32-arm.c:4838
 #, c-format
 msgid "unable to find ARM glue '%s' for '%s'"
 msgstr "no se puede encontrar el pegamento ARM '%s' para `%s'"
 
-#: elf32-arm.c:4463
+#: elf32-arm.c:5365
 msgid "%B: BE8 images only valid in big-endian mode."
 msgstr "%B: las imágenes BE8 sólo son válidas en modo big-endian."
 
 #. Give a warning, but do as the user requests anyway.
-#: elf32-arm.c:4678
+#: elf32-arm.c:5590
 msgid "%B: warning: selected VFP11 erratum workaround is not necessary for target architecture"
-msgstr "%B: aviso: no se necesita la alternativa para evita la errata del VFP11 seleccionado para la arquitectura objetivo"
+msgstr "%B: aviso: no se necesita la alternativa para evitar la errata del VFP11 seleccionado para la arquitectura objetivo"
 
-#: elf32-arm.c:5212 elf32-arm.c:5232
+#: elf32-arm.c:6130 elf32-arm.c:6150
 msgid "%B: unable to find VFP11 veneer `%s'"
 msgstr "%B: no se puede encontrar la chapa de VFP11 `%s'"
 
-#: elf32-arm.c:5278
+#: elf32-arm.c:6196
 #, c-format
 msgid "Invalid TARGET2 relocation type '%s'."
 msgstr "Tipo de reubicación TARGET2 '%s' inválido."
 
-#: elf32-arm.c:5362
+#: elf32-arm.c:6281
 msgid ""
 "%B(%s): warning: interworking not enabled.\n"
 "  first occurrence: %B: thumb call to arm"
 msgstr ""
 "%s(%s): aviso: no se activó la interoperabilidad.\n"
-"  primer suceso: %B: llamada thumb para arm"
+"  primer suceso: %B: llamada thumb a arm"
 
-#: elf32-arm.c:6094
+#: elf32-arm.c:7003
 msgid "\\%B: Warning: Arm BLX instruction targets Arm function '%s'."
 msgstr "\\%B: Aviso: La instrucción Arm BLX apunta a la función Arm '%s'."
 
-#: elf32-arm.c:6418
+#: elf32-arm.c:7405
 msgid "%B: Warning: Thumb BLX instruction targets thumb function '%s'."
 msgstr "%B: Aviso: La instrucción Thumb BLX apunta a la función thumb '%s'."
 
-#: elf32-arm.c:7095
+#: elf32-arm.c:8085
 msgid "%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object"
 msgstr "%B(%A+0x%lx): la reubicación R_ARM_TLS_LE32 no se permite en objetos compartidos"
 
-#: elf32-arm.c:7310
+#: elf32-arm.c:8300
 msgid "%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations"
-msgstr "%B(%A+0x%lx): Sólo se permiten las instrucciones ADD o SUB para la reubicación de grupo ALU"
+msgstr "%B(%A+0x%lx): Sólo se permiten las instrucciones ADD o SUB en las reubicaciones de grupo ALU"
 
-#: elf32-arm.c:7350 elf32-arm.c:7437 elf32-arm.c:7520 elf32-arm.c:7605
+#: elf32-arm.c:8340 elf32-arm.c:8427 elf32-arm.c:8510 elf32-arm.c:8595
 msgid "%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"
 msgstr "%B(%A+0x%lx): Desborde al dividirse 0x%lx para la reubicación de grupo %s"
 
-#: elf32-arm.c:7812 elf32-sh.c:3334 elf64-sh64.c:1556
+#: elf32-arm.c:8821 elf32-sh.c:3325 elf64-sh64.c:1556
 msgid "%B(%A+0x%lx): %s relocation against SEC_MERGE section"
 msgstr "%B(%A+0x%lx): reubicación %s contra la sección SEC_MERGE"
 
-#: elf32-arm.c:7930 elf32-xtensa.c:2759 elf64-ppc.c:10374
+#: elf32-arm.c:8939 elf32-m68k.c:4134 elf32-xtensa.c:2765 elf64-ppc.c:10743
 msgid "%B(%A+0x%lx): %s used with TLS symbol %s"
 msgstr "%B(%A+0x%lx): se usó %s con el símbolo TLS %s"
 
-#: elf32-arm.c:7931 elf32-xtensa.c:2760 elf64-ppc.c:10375
+#: elf32-arm.c:8940 elf32-m68k.c:4135 elf32-xtensa.c:2766 elf64-ppc.c:10744
 msgid "%B(%A+0x%lx): %s used with non-TLS symbol %s"
 msgstr "%B(%A+0x%lx): se usó %s con el símbolo %s que no es TLS"
 
-#: elf32-arm.c:7988
+#: elf32-arm.c:8997
 msgid "out of range"
 msgstr "fuera de rango"
 
-#: elf32-arm.c:7992
+#: elf32-arm.c:9001
 msgid "unsupported relocation"
 msgstr "no se admite la reubicación"
 
-#: elf32-arm.c:8000
+#: elf32-arm.c:9009
 msgid "unknown error"
 msgstr "error desconocido"
 
-#: elf32-arm.c:8099
+#: elf32-arm.c:9409
 msgid "Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"
 msgstr "Aviso: Se limpia la opción de interoperación en %B porque se ha enlazado con él código no interoperable en %B"
 
-#: elf32-arm.c:8205
-msgid "ERROR: %B uses VFP register arguments, %B does not"
-msgstr "ERROR: %B utiliza argumentos de registro VFP, mientras que %B no"
+#: elf32-arm.c:9652
+msgid "error: %B: Unknown CPU architecture"
+msgstr "error: %B: Arquitectura de CPU desconocida"
+
+#: elf32-arm.c:9690
+msgid "error: %B: Conflicting CPU architectures %d/%d"
+msgstr "error: %B: Arquitecturas de CPU en conflicto %d/%d"
 
-#: elf32-arm.c:8254
-msgid "ERROR: %B: Conflicting architecture profiles %c/%c"
-msgstr "ERROR: %B: Perfiles de arquitecturas en conflicto %c/%c"
+#: elf32-arm.c:9747
+msgid "error: %B uses VFP register arguments, %B does not"
+msgstr "error: %B utiliza argumentos de registro VFP, mientras que %B no"
 
-#: elf32-arm.c:8274
+#: elf32-arm.c:9897
+msgid "error: %B: Conflicting architecture profiles %c/%c"
+msgstr "error: %B: Perfiles de arquitecturas en conflicto %c/%c"
+
+#: elf32-arm.c:9921
 msgid "Warning: %B: Conflicting platform configuration"
 msgstr "Aviso: %B: Configuración de plataformas en conflicto"
 
-#: elf32-arm.c:8283
-msgid "ERROR: %B: Conflicting use of R9"
-msgstr "ERROR: %B: Uso en conflicto de R9"
+#: elf32-arm.c:9930
+msgid "error: %B: Conflicting use of R9"
+msgstr "error: %B: Uso en conflicto de R9"
 
-#: elf32-arm.c:8295
-msgid "ERROR: %B: SB relative addressing conflicts with use of R9"
-msgstr "ERROR: %B: El direccionamiento relativo a SB tiene conflictos con el uso de R9"
+#: elf32-arm.c:9942
+msgid "error: %B: SB relative addressing conflicts with use of R9"
+msgstr "error: %B: El direccionamiento relativo a SB tiene conflictos con el uso de R9"
 
-#: elf32-arm.c:8318
+#: elf32-arm.c:9955
 msgid "warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"
 msgstr "aviso: %B usa wchar_t de %u bytes aunque la salida usa wchar_t de %u bytes; el uso de valores wchar_t entre objetos puede fallar"
 
-#: elf32-arm.c:8347
+#: elf32-arm.c:9986
 msgid "warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"
-msgstr "aviso: %B usa %s enums aunque la salida usa %s enums; el uso de valores enum entre objetos puede fallar"
+msgstr "aviso: %B usa enums %s aunque la salida usa enums %s; el uso de valores enum entre objetos puede fallar"
+
+#: elf32-arm.c:9998
+msgid "error: %B uses iWMMXt register arguments, %B does not"
+msgstr "error: %B utiliza argumentos de registro iWMMXt, mientras que %B no"
 
-#: elf32-arm.c:8360
-msgid "ERROR: %B uses iWMMXt register arguments, %B does not"
-msgstr "ERROR: %B utiliza argumentos de registro iWMMXt, mientras que %B no"
+#: elf32-arm.c:10020
+msgid "error: fp16 format mismatch between %B and %B"
+msgstr "error: no coincide el formato fp16 entre %B y %B"
 
-#: elf32-arm.c:8400
+#: elf32-arm.c:10063 elf32-arm.c:10156
+msgid "%B: Unknown mandatory EABI object attribute %d"
+msgstr "%B: Atributo de objeto EABI obligatorio %d desconocido"
+
+#: elf32-arm.c:10071 elf32-arm.c:10164
 msgid "Warning: %B: Unknown EABI object attribute %d"
 msgstr "Aviso: %B: Atributo de objeto EABI %d desconocido"
 
-#: elf32-arm.c:8460
-msgid "ERROR: %B is already in final BE8 format"
-msgstr "ERROR: %B ya está en el formato BE8 final"
+#: elf32-arm.c:10224
+msgid "error: %B is already in final BE8 format"
+msgstr "error: %B ya está en el formato BE8 final"
 
-#: elf32-arm.c:8536
-msgid "ERROR: Source object %B has EABI version %d, but target %B has EABI version %d"
-msgstr "ERROR: El objeto fuente %B tiene EABI versión %d, pero el objetivo %B tiene EABI versión %d"
+#: elf32-arm.c:10300
+msgid "error: Source object %B has EABI version %d, but target %B has EABI version %d"
+msgstr "error: El objeto fuente %B tiene EABI versión %d, pero el objetivo %B tiene EABI versión %d"
 
-#: elf32-arm.c:8552
-msgid "ERROR: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"
-msgstr "ERROR: %B está compilado para APCS-%d mientras que el objetivo %B usa APCS-%d"
+#: elf32-arm.c:10316
+msgid "error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"
+msgstr "error: %B está compilado para APCS-%d mientras que el objetivo %B usa APCS-%d"
 
-#: elf32-arm.c:8577
-msgid "ERROR: %B uses VFP instructions, whereas %B does not"
-msgstr "ERROR: %B utiliza instrucciones VFP, mientras que %B no"
+#: elf32-arm.c:10341
+msgid "error: %B uses VFP instructions, whereas %B does not"
+msgstr "error: %B utiliza instrucciones VFP, mientras que %B no"
 
-#: elf32-arm.c:8581
-msgid "ERROR: %B uses FPA instructions, whereas %B does not"
-msgstr "ERROR: %B utiliza instrucciones FPA, mientras que %B no"
+#: elf32-arm.c:10345
+msgid "error: %B uses FPA instructions, whereas %B does not"
+msgstr "error: %B utiliza instrucciones FPA, mientras que %B no"
 
-#: elf32-arm.c:8591
-msgid "ERROR: %B uses Maverick instructions, whereas %B does not"
-msgstr "ERROR: %B utiliza instrucciones Maverick, mientras que %B no"
+#: elf32-arm.c:10355
+msgid "error: %B uses Maverick instructions, whereas %B does not"
+msgstr "error: %B utiliza instrucciones Maverick, mientras que %B no"
 
-#: elf32-arm.c:8595
-msgid "ERROR: %B does not use Maverick instructions, whereas %B does"
-msgstr "ERROR: %B no utiliza instrucciones Maverick, mientras que %B sí"
+#: elf32-arm.c:10359
+msgid "error: %B does not use Maverick instructions, whereas %B does"
+msgstr "error: %B no utiliza instrucciones Maverick, mientras que %B sí"
 
-#: elf32-arm.c:8614
-msgid "ERROR: %B uses software FP, whereas %B uses hardware FP"
-msgstr "ERROR: %B utiliza FP de software, mientras que %B utiliza FP de hardware"
+#: elf32-arm.c:10378
+msgid "error: %B uses software FP, whereas %B uses hardware FP"
+msgstr "error: %B utiliza FP de software, mientras que %B utiliza FP de hardware"
 
-#: elf32-arm.c:8618
-msgid "ERROR: %B uses hardware FP, whereas %B uses software FP"
-msgstr "ERROR: %B utiliza FP de hardware, mientras que %B utiliza FP de software"
+#: elf32-arm.c:10382
+msgid "error: %B uses hardware FP, whereas %B uses software FP"
+msgstr "error: %B utiliza FP de hardware, mientras que %B utiliza FP de software"
 
 #. Ignore init flag - it may not be set, despite the flags field
 #. containing valid data.
 #. Ignore init flag - it may not be set, despite the flags field containing valid data.
-#: elf32-arm.c:8665 elf32-bfin.c:4899 elf32-cris.c:3235 elf32-m68hc1x.c:1279
-#: elf32-m68k.c:774 elf32-score.c:3750 elf32-vax.c:538 elfxx-mips.c:12699
+#: elf32-arm.c:10429 elf32-bfin.c:5082 elf32-cris.c:4110 elf32-m68hc1x.c:1280
+#: elf32-m68k.c:1169 elf32-score.c:4039 elf32-score7.c:3876 elf32-vax.c:540
+#: elfxx-mips.c:12755
 #, c-format
 msgid "private flags = %lx:"
 msgstr "opciones privadas = %lx:"
 
-#: elf32-arm.c:8674
+#: elf32-arm.c:10438
 #, c-format
 msgid " [interworking enabled]"
 msgstr " [interoperabilidad activada]"
 
-#: elf32-arm.c:8682
+#: elf32-arm.c:10446
 #, c-format
 msgid " [VFP float format]"
 msgstr " [formato de coma flotante VFP]"
 
-#: elf32-arm.c:8684
+#: elf32-arm.c:10448
 #, c-format
 msgid " [Maverick float format]"
 msgstr " [formato de coma flotante Maverick]"
 
-#: elf32-arm.c:8686
+#: elf32-arm.c:10450
 #, c-format
 msgid " [FPA float format]"
 msgstr " [formato de coma flotante FPA]"
 
-#: elf32-arm.c:8695
+#: elf32-arm.c:10459
 #, c-format
 msgid " [new ABI]"
 msgstr " [ABI nuevo]"
 
-#: elf32-arm.c:8698
+#: elf32-arm.c:10462
 #, c-format
 msgid " [old ABI]"
 msgstr " [ABI antiguo]"
 
-#: elf32-arm.c:8701
+#: elf32-arm.c:10465
 #, c-format
 msgid " [software FP]"
 msgstr " [FP por software]"
 
-#: elf32-arm.c:8710
+#: elf32-arm.c:10474
 #, c-format
 msgid " [Version1 EABI]"
 msgstr " [EABI Version1]"
 
-#: elf32-arm.c:8713 elf32-arm.c:8724
+#: elf32-arm.c:10477 elf32-arm.c:10488
 #, c-format
 msgid " [sorted symbol table]"
 msgstr " [tabla de símbolos ordenados]"
 
-#: elf32-arm.c:8715 elf32-arm.c:8726
+#: elf32-arm.c:10479 elf32-arm.c:10490
 #, c-format
 msgid " [unsorted symbol table]"
 msgstr " [tabla de símbolos sin ordenar]"
 
-#: elf32-arm.c:8721
+#: elf32-arm.c:10485
 #, c-format
 msgid " [Version2 EABI]"
 msgstr " [EABI Version2]"
 
-#: elf32-arm.c:8729
+#: elf32-arm.c:10493
 #, c-format
 msgid " [dynamic symbols use segment index]"
 msgstr " [los símbolos dinámicos utilizan índices de segmento]"
 
-#: elf32-arm.c:8732
+#: elf32-arm.c:10496
 #, c-format
 msgid " [mapping symbols precede others]"
 msgstr " [el mapeo de símbolos precede a otros]"
 
-#: elf32-arm.c:8739
+#: elf32-arm.c:10503
 #, c-format
 msgid " [Version3 EABI]"
 msgstr " [EABI Version3]"
 
-#: elf32-arm.c:8743
+#: elf32-arm.c:10507
 #, c-format
 msgid " [Version4 EABI]"
 msgstr " [EABI Version4]"
 
-#: elf32-arm.c:8747
+#: elf32-arm.c:10511
 #, c-format
 msgid " [Version5 EABI]"
 msgstr " [EABI Version5]"
 
-#: elf32-arm.c:8750
+#: elf32-arm.c:10514
 #, c-format
 msgid " [BE8]"
 msgstr " [BE8]"
 
-#: elf32-arm.c:8753
+#: elf32-arm.c:10517
 #, c-format
 msgid " [LE8]"
 msgstr " [LE8]"
 
-#: elf32-arm.c:8759
+#: elf32-arm.c:10523
 #, c-format
 msgid " <EABI version unrecognised>"
-msgstr " <versión de EABI no reconocida>"
+msgstr " <no se reconoce la versión de EABI>"
 
-#: elf32-arm.c:8766
+#: elf32-arm.c:10530
 #, c-format
 msgid " [relocatable executable]"
 msgstr " [ejecutable reubicable]"
 
-#: elf32-arm.c:8769
+#: elf32-arm.c:10533
 #, c-format
 msgid " [has entry point]"
 msgstr " [tiene punto de entrada]"
 
-#: elf32-arm.c:8774
+#: elf32-arm.c:10538
 #, c-format
 msgid "<Unrecognised flag bits set>"
-msgstr "<Conjunto de bits de opción sin reconocer>"
+msgstr "<No se reconoce el conjunto de bits de opción>"
 
-#: elf32-arm.c:9013 elf32-i386.c:1236 elf32-s390.c:1006 elf32-xtensa.c:999
-#: elf64-s390.c:961 elf64-x86-64.c:1016 elfxx-sparc.c:1127
+#: elf32-arm.c:10783 elf32-i386.c:1300 elf32-s390.c:998 elf32-xtensa.c:1000
+#: elf64-s390.c:952 elf64-x86-64.c:1082 elfxx-sparc.c:1121
 msgid "%B: bad symbol index: %d"
 msgstr "%B: índice de símbolos erróneo: %d"
 
-#: elf32-arm.c:10125
+#: elf32-arm.c:10904 elf64-x86-64.c:1242 elf64-x86-64.c:1411 elfxx-mips.c:7870
+msgid "%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"
+msgstr "%B: no se puede usar la reubicación %s contra `%s' cuando se hace un objeto compartido; recompile con -fPIC"
+
+#: elf32-arm.c:11893
 #, c-format
 msgid "Errors encountered processing file %s"
 msgstr "Se encontraron errores al procesar el fichero %s"
 
-#: elf32-arm.c:11526 elf32-arm.c:11548
+#: elf32-arm.c:13339
+msgid "%B: error: Cortex-A8 erratum stub is allocated in unsafe location"
+msgstr "%B: error: el cabo de errores Cortex-A8 se aloja en una ubicación insegura"
+
+#. There's not much we can do apart from complain if this
+#. happens.
+#: elf32-arm.c:13366
+msgid "%B: error: Cortex-A8 erratum stub out of range (input file too large)"
+msgstr "%B: error: el cabo de errores Cortex-A8 está fuera de rango (el fichero de entrada es demasiado grande)"
+
+#: elf32-arm.c:13457 elf32-arm.c:13479
 msgid "%B: error: VFP11 veneer out of range"
 msgstr "%B: error: la chapa VFP11 está fuera de rango"
 
-#: elf32-avr.c:1258 elf32-bfin.c:3222 elf32-cris.c:1546 elf32-fr30.c:624
+#: elf32-avr.c:1259 elf32-bfin.c:3208 elf32-cris.c:2097 elf32-fr30.c:624
 #: elf32-frv.c:4122 elf32-i860.c:1226 elf32-ip2k.c:1510 elf32-iq2000.c:699
-#: elf32-m32c.c:568 elf32-mep.c:549 elf32-msp430.c:501 elf32-mt.c:406
-#: elf32-openrisc.c:419 elf32-v850.c:1711 elf32-xstormy16.c:956
+#: elf32-m32c.c:568 elf32-mep.c:549 elf32-moxie.c:299 elf32-msp430.c:501
+#: elf32-mt.c:406 elf32-openrisc.c:419 elf32-v850.c:1709 elf32-xstormy16.c:956
 #: elf64-mmix.c:1541
 msgid "internal error: dangerous relocation"
 msgstr "error interno: reubicación peligrosa"
 
-#: elf32-avr.c:2396 elf32-hppa.c:605 elf32-m68hc1x.c:164 elf64-ppc.c:3983
+#: elf32-avr.c:2409 elf32-hppa.c:605 elf32-m68hc1x.c:165 elf64-ppc.c:4141
 msgid "%B: cannot create stub entry %s"
 msgstr "%B: no se puede crear la entrada de cabo %s"
 
-#: elf32-bfin.c:1585
+#: elf32-bfin.c:1581
 msgid "%B(%A+0x%lx): unresolvable relocation against symbol `%s'"
 msgstr "%B(%A+0x%lx): reubicación sin resolución contra el símbolo `%s'"
 
-#: elf32-bfin.c:1618 elf32-i386.c:3623 elf32-m68k.c:3557 elf32-s390.c:3110
-#: elf64-s390.c:3071 elf64-x86-64.c:3278
+#: elf32-bfin.c:1614 elf32-i386.c:4026 elf32-m68k.c:4176 elf32-s390.c:3067
+#: elf64-s390.c:3026 elf64-x86-64.c:3697
 msgid "%B(%A+0x%lx): reloc against `%s': error %d"
 msgstr "%B(%A+0x%lx): reubicación contra `%s': error %d"
 
-#: elf32-bfin.c:2711
+#: elf32-bfin.c:2714
 msgid "%B: relocation at `%A+0x%x' references symbol `%s' with nonzero addend"
 msgstr "%B: la reubicación en `%A+0x%x' referencía al símbolo `%s' con adición que no es cero"
 
-#: elf32-bfin.c:2725 elf32-frv.c:2904
+#: elf32-bfin.c:2728 elf32-frv.c:2904
 msgid "relocation references symbol not defined in the module"
 msgstr "la reubicación referencía un símbolo que no está definido en el módulo"
 
-#: elf32-bfin.c:2822
+#: elf32-bfin.c:2825
 msgid "R_BFIN_FUNCDESC references dynamic symbol with nonzero addend"
 msgstr "R_BFIN_FUNCDESC referencía un símbolo dinámico con adición que no es cero"
 
-#: elf32-bfin.c:2861 elf32-bfin.c:2987 elf32-frv.c:3641 elf32-frv.c:3762
+#: elf32-bfin.c:2866 elf32-bfin.c:2989 elf32-frv.c:3641 elf32-frv.c:3762
 msgid "cannot emit fixups in read-only section"
 msgstr "no se pueden emitir composturas en la sección de sólo lectura"
 
-#: elf32-bfin.c:2889 elf32-bfin.c:3036 elf32-frv.c:3672 elf32-frv.c:3806
+#: elf32-bfin.c:2897 elf32-bfin.c:3027 elf32-frv.c:3672 elf32-frv.c:3806
+#: elf32-lm32.c:1104
 msgid "cannot emit dynamic relocations in read-only section"
 msgstr "no se pueden emitir reubicaciones dinámicas en la sección de sólo lectura"
 
-#: elf32-bfin.c:2945
+#: elf32-bfin.c:2947
 msgid "R_BFIN_FUNCDESC_VALUE references dynamic symbol with nonzero addend"
 msgstr "R_BFIN_FUNCDESC_VALUE referencía un símbolo dinámico con adición que no es cero"
 
-#: elf32-bfin.c:3126
+#: elf32-bfin.c:3112
 msgid "relocations between different segments are not supported"
 msgstr "no se admiten las reubicaciones entre segmentos diferentes"
 
-#: elf32-bfin.c:3127
+#: elf32-bfin.c:3113
 msgid "warning: relocation references a different segment"
 msgstr "aviso: la reubicación referencía un segmento diferente"
 
-#: elf32-bfin.c:4791 elf32-frv.c:6404
+#: elf32-bfin.c:4974 elf32-frv.c:6408
 msgid "%B: unsupported relocation type %i"
 msgstr "%B: no se admite el tipo de reubicación %i"
 
-#: elf32-bfin.c:4944 elf32-frv.c:6812
+#: elf32-bfin.c:5127 elf32-frv.c:6816
 #, c-format
 msgid "%s: cannot link non-fdpic object file into fdpic executable"
 msgstr "%s: no se puede enlazar el fichero objeto que no es fdpic en un ejecutable fdpic"
 
-#: elf32-bfin.c:4948 elf32-frv.c:6816
+#: elf32-bfin.c:5131 elf32-frv.c:6820
 #, c-format
 msgid "%s: cannot link fdpic object file into non-fdpic executable"
 msgstr "%s: no se puede enlazar el fichero objeto fdpic en un ejecutable que no es fdpic"
 
-#: elf32-cris.c:1060
+#: elf32-cris.c:1169
 msgid "%B, section %A: unresolvable relocation %s against symbol `%s'"
 msgstr "%B, sección %A: reubicación %s sin resolución contra el símbolo `%s'"
 
-#: elf32-cris.c:1129
+#: elf32-cris.c:1238
 msgid "%B, section %A: No PLT nor GOT for relocation %s against symbol `%s'"
 msgstr "%B, sección %A: No hay PLT ni GOT para la reubicación %s contra el símbolo `%s'"
 
-#: elf32-cris.c:1131
+#: elf32-cris.c:1240
 msgid "%B, section %A: No PLT for relocation %s against symbol `%s'"
 msgstr "%B, sección %A: No hay PLT para la reubicación %s contra el símbolo `%s'"
 
-#: elf32-cris.c:1137 elf32-cris.c:1269
+#: elf32-cris.c:1246 elf32-cris.c:1379 elf32-cris.c:1641 elf32-cris.c:1730
+#: elf32-cris.c:1883
 msgid "[whose name is lost]"
-msgstr "[cuyo nombre se pierde]"
+msgstr "[cuyo nombre está perdido]"
 
-#: elf32-cris.c:1255
+#: elf32-cris.c:1365
 msgid "%B, section %A: relocation %s with non-zero addend %d against local symbol"
 msgstr "%B, sección %A: reubicación %s con adición %d que no es cero contra el símbolo local"
 
-#: elf32-cris.c:1263
+#: elf32-cris.c:1373 elf32-cris.c:1724 elf32-cris.c:1877
 msgid "%B, section %A: relocation %s with non-zero addend %d against symbol `%s'"
 msgstr "%B, sección %A: reubicación %s con adición %d que no es cero contra el símbolo `%s'"
 
-#: elf32-cris.c:1289
+#: elf32-cris.c:1399
 msgid "%B, section %A: relocation %s is not allowed for global symbol: `%s'"
 msgstr "%B, sección %A: no se permite la reubicación %s para el símbolo global: `%s'"
 
-#: elf32-cris.c:1305
+#: elf32-cris.c:1415
 msgid "%B, section %A: relocation %s with no GOT created"
 msgstr "%B, sección %A: la reubicación %s sin GOT creado"
 
-#: elf32-cris.c:1423
-msgid "%B: Internal inconsistency; no relocation section %s"
-msgstr "%B: Inconsistencia interna; no se encuentra la sección de reubicación %s"
+#. We shouldn't get here for GCC-emitted code.
+#: elf32-cris.c:1632
+msgid "%B, section %A: relocation %s has an undefined reference to `%s', perhaps a declaration mixup?"
+msgstr "%B, sección %A: la reubicación %s tiene una referencia sin definir a `%s', ¿tal vez una confusión en la declaración?"
 
-#: elf32-cris.c:2510
+#: elf32-cris.c:2010
+msgid "%B, section %A: relocation %s is not allowed for symbol: `%s' which is defined outside the program, perhaps a declaration mixup?"
+msgstr "%B, sección %A: no se permite la reubicación %s para el símbolo: `%s' el cual se define fuera del programa, ¿tal vez una confusión en la declaración?"
+
+#: elf32-cris.c:2063
+msgid "(too many global variables for -fpic: recompile with -fPIC)"
+msgstr "(demasiadas variables globales para -fpic: recompile con -fPIC)"
+
+#: elf32-cris.c:2070
+msgid "(thread-local data too big for -fpic or -msmall-tls: recompile with -fPIC or -mno-small-tls)"
+msgstr "(datos thread-local demasiado grandes para -fpic o -msmall-tls: recompile con -fPIC o -mno-small-tls)"
+
+#: elf32-cris.c:3204
 msgid ""
 "%B, section %A:\n"
 "  v10/v32 compatible object %s must not contain a PIC relocation"
@@ -1267,7 +1336,15 @@ msgstr ""
 "%B, sección %A:\n"
 "  el objeto %s compatible con v10/v32 no debe contener una reubicación PIC"
 
-#: elf32-cris.c:2697 elf32-cris.c:2765
+#: elf32-cris.c:3309
+msgid ""
+"%B, section %A:\n"
+"  relocation %s not valid in a shared object; typically an option mixup, recompile with -fPIC"
+msgstr ""
+"%B, sección %A:\n"
+"  la reubicación %s no es válida en un objeto compartido; es una confusión de opción típica, recompile con -fPIC"
+
+#: elf32-cris.c:3523
 msgid ""
 "%B, section %A:\n"
 "  relocation %s should not be used in a shared object; recompile with -fPIC"
@@ -1275,38 +1352,46 @@ msgstr ""
 "%B, sección %A:\n"
 "  la reubicación %s no se debe usar en un objeto compartido; recompile con -fPIC"
 
-#: elf32-cris.c:3184
+#: elf32-cris.c:3940
+msgid ""
+"%B, section `%A', to symbol `%s':\n"
+"  relocation %s should not be used in a shared object; recompile with -fPIC"
+msgstr ""
+"%B, sección `%A', para el símbolo `%s':\n"
+"  la reubicación %s no se debe usar en un objeto compartido; recompile con -fPIC"
+
+#: elf32-cris.c:4059
 msgid "Unexpected machine number"
 msgstr "Número de máquina inesperado"
 
-#: elf32-cris.c:3238
+#: elf32-cris.c:4113
 #, c-format
 msgid " [symbols have a _ prefix]"
 msgstr " [los símbolos tiene un prefijo _]"
 
-#: elf32-cris.c:3241
+#: elf32-cris.c:4116
 #, c-format
 msgid " [v10 and v32]"
 msgstr " [v10 y v32]"
 
-#: elf32-cris.c:3244
+#: elf32-cris.c:4119
 #, c-format
 msgid " [v32]"
 msgstr " [v32]"
 
-#: elf32-cris.c:3289
+#: elf32-cris.c:4164
 msgid "%B: uses _-prefixed symbols, but writing file with non-prefixed symbols"
-msgstr "%B: utiliza símbolos con prefijo _, pero escribe el fichero con símbolos sin prefijo"
+msgstr "%B: se usan símbolos con prefijo _, pero se escribe el fichero con símbolos sin prefijo"
 
-#: elf32-cris.c:3290
+#: elf32-cris.c:4165
 msgid "%B: uses non-prefixed symbols, but writing file with _-prefixed symbols"
-msgstr "%B: utiliza símbolos sin prefijo, pero escribe el fichero con símbolos con prefijo _"
+msgstr "%B: se usan símbolos sin prefijo, pero se escribe el fichero con símbolos con prefijo _"
 
-#: elf32-cris.c:3309
+#: elf32-cris.c:4184
 msgid "%B contains CRIS v32 code, incompatible with previous objects"
 msgstr "%B contiene código CRIS v32, incompatible con objetos previos"
 
-#: elf32-cris.c:3311
+#: elf32-cris.c:4186
 msgid "%B contains non-CRIS-v32 code, incompatible with previous objects"
 msgstr "%B contiene código que no es CRIS v32, incompatible con objetos previos"
 
@@ -1382,22 +1467,22 @@ msgstr "%B(%A+0x%lx): reubicaci
 msgid "relocation references a different segment"
 msgstr "la reubicación referencía un segmento diferente"
 
-#: elf32-frv.c:6726
+#: elf32-frv.c:6730
 #, c-format
 msgid "%s: compiled with %s and linked with modules that use non-pic relocations"
 msgstr "%s: compilado con %s y enlazado con módulos que usan reubicaciones que no son pic"
 
-#: elf32-frv.c:6779 elf32-iq2000.c:852 elf32-m32c.c:814
+#: elf32-frv.c:6783 elf32-iq2000.c:852 elf32-m32c.c:814
 #, c-format
 msgid "%s: compiled with %s and linked with modules compiled with %s"
 msgstr "%s: compilado con %s y enlazado con módulos compilados con %s"
 
-#: elf32-frv.c:6791
+#: elf32-frv.c:6795
 #, c-format
 msgid "%s: uses different unknown e_flags (0x%lx) fields than previous modules (0x%lx)"
 msgstr "%s: usa campos e_flags desconocidos (0x%lx) diferentes a aquéllos de los módulos previos (0x%lx)"
 
-#: elf32-frv.c:6841 elf32-iq2000.c:889 elf32-m32c.c:850 elf32-mt.c:583
+#: elf32-frv.c:6845 elf32-iq2000.c:889 elf32-m32c.c:850 elf32-mt.c:583
 #, c-format
 msgid "private flags = 0x%lx:"
 msgstr "opciones privadas = 0x%lx:"
@@ -1406,79 +1491,73 @@ msgstr "opciones privadas = 0x%lx:"
 msgid "%B: Relocations in generic ELF (EM: %d)"
 msgstr "%B: Reubicaciones en ELF genérico (EM: %d)"
 
-#: elf32-hppa.c:854 elf32-hppa.c:3600
+#: elf32-hppa.c:854 elf32-hppa.c:3570
 msgid "%B(%A+0x%lx): cannot reach %s, recompile with -ffunction-sections"
 msgstr "%B(%A+0x%lx): no se puede alcanzar %s, recompile con -ffuntion-sections"
 
-#: elf32-hppa.c:1263
+#: elf32-hppa.c:1286
 msgid "%B: relocation %s can not be used when making a shared object; recompile with -fPIC"
 msgstr "%B: no se puede usar la reubicación %s cuando se hace un objeto compartido; recompile con -fPIC"
 
-#: elf32-hppa.c:1518
-#, c-format
-msgid "Could not find relocation section for %s"
-msgstr "No se puede encontrar la sección de reubicación para %s"
-
-#: elf32-hppa.c:2810
+#: elf32-hppa.c:2780
 msgid "%B: duplicate export stub %s"
 msgstr "%B: cabo de exportación %s duplicado"
 
-#: elf32-hppa.c:3436
+#: elf32-hppa.c:3406
 msgid "%B(%A+0x%lx): %s fixup for insn 0x%x is not supported in a non-shared link"
 msgstr "%B(%A+0x%lx): la compostura %s para la insn 0x%x no se admite en un enlazado que no es compartido"
 
-#: elf32-hppa.c:4290
+#: elf32-hppa.c:4260
 msgid "%B(%A+0x%lx): cannot handle %s for %s"
 msgstr "%B(%A+0x%lx): no se puede manejar %s para %s"
 
-#: elf32-hppa.c:4597
+#: elf32-hppa.c:4567
 msgid ".got section not immediately after .plt section"
 msgstr "la sección .got no está inmediatamente después de la sección .plt"
 
-#: elf32-i386.c:362 elf32-ppc.c:1616 elf32-s390.c:379 elf64-ppc.c:2153
-#: elf64-s390.c:403 elf64-x86-64.c:222
+#: elf32-i386.c:371 elf32-ppc.c:1666 elf32-s390.c:379 elf64-ppc.c:2283
+#: elf64-s390.c:403 elf64-x86-64.c:234
 msgid "%B: invalid relocation type %d"
 msgstr "%B: tipo de reubicación %d inválido"
 
-#: elf32-i386.c:1183 elf64-x86-64.c:964
+#: elf32-i386.c:1246 elf64-x86-64.c:1029
 msgid "%B: TLS transition from %s to %s against `%s' at 0x%lx in section `%A' failed"
 msgstr "%B: falló la transición TLS de %s para %s contra `%s' en 0x%lx en la sección `%A'"
 
-#: elf32-i386.c:1364 elf32-s390.c:1188 elf32-sh.c:5098 elf32-xtensa.c:1162
-#: elf64-s390.c:1152 elfxx-sparc.c:1263
-msgid "%B: `%s' accessed both as normal and thread local symbol"
-msgstr "%B: se accesó `%s' como un símbolo normal y un símbolo local de hilo"
+#: elf32-i386.c:1387 elf32-i386.c:2970 elf64-x86-64.c:1171 elf64-x86-64.c:2680
+msgid "%B: relocation %s against STT_GNU_IFUNC symbol `%s' isn't handled by %s"
+msgstr "%B: la reubicación %s contra el símbolo STT_GNU_IFUNC `%s' no es manejada por %s"
 
-#: elf32-i386.c:1479 elf32-s390.c:1297 elf64-ppc.c:5046 elf64-s390.c:1264
-#: elf64-x86-64.c:1299
-msgid "%B: bad relocation section name `%s'"
-msgstr "%B: nombre de sección de reubicación `%s' erróneo"
+#: elf32-i386.c:1548 elf32-s390.c:1180 elf32-sh.c:5065 elf32-xtensa.c:1173
+#: elf64-s390.c:1143 elfxx-sparc.c:1257
+msgid "%B: `%s' accessed both as normal and thread local symbol"
+msgstr "%B: se accedió `%s' como un símbolo normal y un símbolo local de hilo"
 
-#: elf32-i386.c:2598
+#: elf32-i386.c:2805
 msgid "%B: unrecognized relocation (0x%x) in section `%A'"
 msgstr "%B: no se reconoce la dirección de reubicación (0x%lx) en la sección `%A'"
 
-#: elf32-i386.c:2822 elf64-x86-64.c:2660
+#: elf32-i386.c:3219 elf64-x86-64.c:3081
 msgid "hidden symbol"
 msgstr "símbolo oculto"
 
-#: elf32-i386.c:2825 elf64-x86-64.c:2663
+#: elf32-i386.c:3222 elf64-x86-64.c:3084
 msgid "internal symbol"
 msgstr "símbolo interno"
 
-#: elf32-i386.c:2828 elf64-x86-64.c:2666
+#: elf32-i386.c:3225 elf64-x86-64.c:3087
 msgid "protected symbol"
-msgstr "símbolos protegido"
+msgstr "símbolo protegido"
 
-#: elf32-i386.c:2831 elf64-x86-64.c:2669
+#: elf32-i386.c:3228 elf64-x86-64.c:3090
 msgid "symbol"
 msgstr "símbolo"
 
-#: elf32-i386.c:2836
+#: elf32-i386.c:3233
 msgid "%B: relocation R_386_GOTOFF against undefined %s `%s' can not be used when making a shared object"
 msgstr "%B: no se puede usar la reubicación R_386_GOTOFF contra %s indefinida `%s' cuando se hace un objeto compartido"
 
-#: elf32-i386.c:2846
+#: elf32-i386.c:3243
 msgid "%B: relocation R_386_GOTOFF against protected function `%s' can not be used when making a shared object"
 msgstr "%B: no se puede usar la reubicación R_386_GOTOFF contra la función protegida `%s' cuando se hace un objeto compartido"
 
@@ -1493,7 +1572,7 @@ msgstr "relajador ip2k: encabezado de tabla switch corrupto."
 #: elf32-ip2k.c:1316
 #, c-format
 msgid "ip2k linker: missing page instruction at 0x%08lx (dest = 0x%08lx)."
-msgstr "enlazador ip2k: instrucción de página faltante en 0x%08lx (dest = 0x%08lx)."
+msgstr "enlazador ip2k: falta la instrucción de página en 0x%08lx (dest = 0x%08lx)."
 
 #: elf32-ip2k.c:1332
 #, c-format
@@ -1510,129 +1589,145 @@ msgstr "no se admite la reubicaci
 msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)"
 msgstr "%s: usa campos de e_flags diferentes (0x%lx) que los módulos previos (0x%lx)"
 
+#: elf32-lm32.c:698
+msgid "global pointer relative relocation when _gp not defined"
+msgstr "reubicación relativa al puntero global cuando _gp no está definido"
+
+#: elf32-lm32.c:753
+msgid "global pointer relative address out of range"
+msgstr "dirección relativa al puntero global fuera de rango"
+
+#: elf32-lm32.c:1058
+msgid "internal error: addend should be zero for R_LM32_16_GOT"
+msgstr "error interno: addend debe ser cero para R_LM32_16_GOT"
+
 #: elf32-m32r.c:1453
 msgid "SDA relocation when _SDA_BASE_ not defined"
 msgstr "reubicación SDA cuando _SDA_BASE_ no está definido"
 
-#: elf32-m32r.c:3061
+#: elf32-m32r.c:3039
 msgid "%B: The target (%s) of an %s relocation is in the wrong section (%A)"
 msgstr "%B: El objetivo (%s) de una reubicación %s está en la sección errónea (%A)"
 
-#: elf32-m32r.c:3589
+#: elf32-m32r.c:3567
 msgid "%B: Instruction set mismatch with previous modules"
-msgstr "%B: Conjunto de instrucciones no coincidente con módulos previos"
+msgstr "%B: El conjunto de instrucciones no coincide con módulos previos"
 
-#: elf32-m32r.c:3610
+#: elf32-m32r.c:3588
 #, c-format
 msgid "private flags = %lx"
 msgstr "opciones privadas = %lx"
 
-#: elf32-m32r.c:3615
+#: elf32-m32r.c:3593
 #, c-format
 msgid ": m32r instructions"
 msgstr ": instrucciones m32r"
 
-#: elf32-m32r.c:3616
+#: elf32-m32r.c:3594
 #, c-format
 msgid ": m32rx instructions"
 msgstr ": instrucciones m32rx"
 
-#: elf32-m32r.c:3617
+#: elf32-m32r.c:3595
 #, c-format
 msgid ": m32r2 instructions"
 msgstr ": instrucciones m32r2"
 
-#: elf32-m68hc1x.c:1047
+#: elf32-m68hc1x.c:1048
 #, c-format
 msgid "Reference to the far symbol `%s' using a wrong relocation may result in incorrect execution"
 msgstr "El referenciar al símbolo far `%s' usando una reubicación incorrecta puede resultar en una ejecución incorrecta"
 
-#: elf32-m68hc1x.c:1070
+#: elf32-m68hc1x.c:1071
 #, c-format
 msgid "banked address [%lx:%04lx] (%lx) is not in the same bank as current banked address [%lx:%04lx] (%lx)"
 msgstr "la dirección almacenada [%lx:%04lx] (%lx) no está en el mismo banco que la dirección almacenada actual [%lx:%04lx] (%lx)"
 
-#: elf32-m68hc1x.c:1089
+#: elf32-m68hc1x.c:1090
 #, c-format
 msgid "reference to a banked address [%lx:%04lx] in the normal address space at %04lx"
 msgstr "referencia a una dirección almacenada [%lx:%04lx] en el espacio normal de direcciones en %04lx"
 
-#: elf32-m68hc1x.c:1222
+#: elf32-m68hc1x.c:1223
 msgid "%B: linking files compiled for 16-bit integers (-mshort) and others for 32-bit integers"
 msgstr "%B: se enlazan ficheros compilados con enteros de 16-bit (-mshort) y otros con enteros de 32-bit"
 
-#: elf32-m68hc1x.c:1229
+#: elf32-m68hc1x.c:1230
 msgid "%B: linking files compiled for 32-bit double (-fshort-double) and others for 64-bit double"
 msgstr "%B: se enlazan ficheros compilados con dobles de 32-bit (-fshort-double) y otros con dobles de 64-bit"
 
-#: elf32-m68hc1x.c:1238
+#: elf32-m68hc1x.c:1239
 msgid "%B: linking files compiled for HCS12 with others compiled for HC12"
 msgstr "%B: se enlazan ficheros compilados para HCS12, con otros compilados para HC12"
 
-#: elf32-m68hc1x.c:1254 elf32-ppc.c:4046 elf64-sparc.c:697 elfxx-mips.c:12561
+#: elf32-m68hc1x.c:1255 elf32-ppc.c:4255 elf64-sparc.c:698 elfxx-mips.c:12617
 msgid "%B: uses different e_flags (0x%lx) fields than previous modules (0x%lx)"
 msgstr "%B: usa campos de e_flags diferentes (0x%lx) que los módulos previos (0x%lx)"
 
-#: elf32-m68hc1x.c:1282
+#: elf32-m68hc1x.c:1283
 #, c-format
 msgid "[abi=32-bit int, "
 msgstr "[abi=int de 32-bit, "
 
-#: elf32-m68hc1x.c:1284
+#: elf32-m68hc1x.c:1285
 #, c-format
 msgid "[abi=16-bit int, "
 msgstr "[abi=int de 16-bit, "
 
-#: elf32-m68hc1x.c:1287
+#: elf32-m68hc1x.c:1288
 #, c-format
 msgid "64-bit double, "
 msgstr "doble de 64-bit, "
 
-#: elf32-m68hc1x.c:1289
+#: elf32-m68hc1x.c:1290
 #, c-format
 msgid "32-bit double, "
 msgstr "doble de 32-bit, "
 
-#: elf32-m68hc1x.c:1292
+#: elf32-m68hc1x.c:1293
 #, c-format
 msgid "cpu=HC11]"
 msgstr "cpu=HC11]"
 
-#: elf32-m68hc1x.c:1294
+#: elf32-m68hc1x.c:1295
 #, c-format
 msgid "cpu=HCS12]"
 msgstr "cpu=HCS12]"
 
-#: elf32-m68hc1x.c:1296
+#: elf32-m68hc1x.c:1297
 #, c-format
 msgid "cpu=HC12]"
 msgstr "cpu=HC12]"
 
-#: elf32-m68hc1x.c:1299
+#: elf32-m68hc1x.c:1300
 #, c-format
 msgid " [memory=bank-model]"
 msgstr " [memoria=modelo de bancos]"
 
-#: elf32-m68hc1x.c:1301
+#: elf32-m68hc1x.c:1302
 #, c-format
 msgid " [memory=flat]"
 msgstr " [memoria=plana]"
 
-#: elf32-m68k.c:789 elf32-m68k.c:790
+#: elf32-m68k.c:1184 elf32-m68k.c:1185
 msgid "unknown"
 msgstr "desconocido"
 
-#: elf32-m68k.c:1216
-msgid "%B: GOT overflow: Number of R_68K_GOT8O relocations > %d"
-msgstr "%B: desbordamiento de GOT: Número de reubicaciones R_68K_GOT80 > %d"
+#: elf32-m68k.c:1645
+msgid "%B: GOT overflow: Number of relocations with 8-bit offset > %d"
+msgstr "%B: desbordamiento de GOT: Número de reubicaciones con desplazamiento de 8-bit > %d"
 
-#: elf32-m68k.c:1221
-msgid "%B: GOT overflow: Number of R_68K_GOT8O and R_68K_GOT16O relocations > %d"
-msgstr "%B desbordamiento de GOT: Número de reubicaciones R_68K_GOT80 Y R_68K_GOT160 > %d"
+#: elf32-m68k.c:1651
+msgid "%B: GOT overflow: Number of relocations with 8- or 16-bit offset > %d"
+msgstr "%B: desbordamiento de GOT: Número de reubicaciones con desplazamiento de 8 o 16-bit > %d"
+
+#: elf32-m68k.c:3902
+msgid "%B(%A+0x%lx): R_68K_TLS_LE32 relocation not permitted in shared object"
+msgstr "%B(%A+0x%lx): la reubicación R_68K_TLS_LE32 no se permite en objetos compartidos"
 
 #: elf32-mcore.c:99 elf32-mcore.c:442
 msgid "%B: Relocation %s (%d) is not currently supported.\n"
-msgstr "%B: La reubicación %s (%d) actualmente no se admite.\n"
+msgstr "%B: Actualmente no se admite la reubicación %s (%d).\n"
 
 #: elf32-mcore.c:428
 msgid "%B: Unknown relocation type %d\n"
@@ -1646,147 +1741,187 @@ msgstr "%B y %B son para n
 msgid "%B and %B are for different configurations"
 msgstr "%B y %B son para configuraciones diferentes"
 
-#: elf32-mep.c:709
+#: elf32-mep.c:708
 #, c-format
 msgid "private flags = 0x%lx"
 msgstr "opciones privadas = 0x%lx"
 
-#: elf32-mips.c:1045 elf64-mips.c:2056 elfn32-mips.c:1888
+#: elf32-microblaze.c:737
+#, c-format
+msgid "%s: unknown relocation type %d"
+msgstr "%s: tipo de reubicación %d desconocido"
+
+#: elf32-microblaze.c:862 elf32-microblaze.c:907
+#, c-format
+msgid "%s: The target (%s) of an %s relocation is in the wrong section (%s)"
+msgstr "%s: El objetivo (%s) de una reubicación %s está en la sección errónea (%s)"
+
+#: elf32-microblaze.c:1150 elfxx-sparc.c:2957
+msgid "%B: probably compiled without -fPIC?"
+msgstr "%B: ¿Compilado probablemente sin -fPIC?"
+
+#: elf32-microblaze.c:2086 elflink.c:12444
+msgid "%B: bad relocation section name `%s'"
+msgstr "%B: nombre de sección de reubicación `%s' erróneo"
+
+#: elf32-mips.c:1045 elf64-mips.c:2083 elfn32-mips.c:1888
 msgid "literal relocation occurs for an external symbol"
 msgstr "la reubicación literal sucede para un símbolo externo"
 
-#: elf32-mips.c:1085 elf32-score.c:484 elf64-mips.c:2099 elfn32-mips.c:1929
+#: elf32-mips.c:1085 elf32-score.c:580 elf32-score7.c:480 elf64-mips.c:2126
+#: elfn32-mips.c:1929
 msgid "32bits gp relative relocation occurs for an external symbol"
-msgstr "la reubicación gp relativa de 32bits sucede para un símbolo externo"
+msgstr "la reubicación relativa a gp de 32bits sucede para un símbolo externo"
 
-#: elf32-ppc.c:1681
+#: elf32-ppc.c:1731
 #, c-format
 msgid "generic linker can't handle %s"
 msgstr "el enlazador genérico no puede manejar %s"
 
-#: elf32-ppc.c:2161
+#: elf32-ppc.c:2211
 msgid "corrupt or empty %s section in %B"
 msgstr "sección %s corrupta o vacía en %B"
 
-#: elf32-ppc.c:2168
+#: elf32-ppc.c:2218
 msgid "unable to read in %s section from %B"
 msgstr "no se puede leer en la sección %s desde %B"
 
-#: elf32-ppc.c:2174
+#: elf32-ppc.c:2224
 msgid "corrupt %s section in %B"
 msgstr "sección %s corrupta en %B"
 
-#: elf32-ppc.c:2217
+#: elf32-ppc.c:2267
 msgid "warning: unable to set size of %s section in %B"
 msgstr "aviso: no se puede establecer el tamaño de la sección %s en %B"
 
-#: elf32-ppc.c:2265
+#: elf32-ppc.c:2315
 msgid "failed to allocate space for new APUinfo section."
 msgstr "no se puede reservar espacio para la nueva sección APUinfo."
 
-#: elf32-ppc.c:2284
+#: elf32-ppc.c:2334
 msgid "failed to compute new APUinfo section."
 msgstr "no se puede calcular la nueva sección APUinfo."
 
-#: elf32-ppc.c:2287
+#: elf32-ppc.c:2337
 msgid "failed to install new APUinfo section."
 msgstr "no se puede instalar la nueva sección APUinfo."
 
-#: elf32-ppc.c:3263
+#: elf32-ppc.c:3364
 msgid "%B: relocation %s cannot be used when making a shared object"
 msgstr "%B: no se puede usar la reubicación %s cuando se hace un objeto compartido"
 
 #. It does not make sense to have a procedure linkage
 #. table entry for a local symbol.
-#: elf32-ppc.c:3534
+#: elf32-ppc.c:3723
 msgid "%B(%A+0x%lx): %s reloc against local symbol"
 msgstr "%B(%A+0x%lx): reubicación %s contra un símbolo local"
 
-#: elf32-ppc.c:3885 elf32-ppc.c:3900 elfxx-mips.c:12268 elfxx-mips.c:12294
-#: elfxx-mips.c:12316 elfxx-mips.c:12342
+#: elf32-ppc.c:4067 elf32-ppc.c:4082 elfxx-mips.c:12324 elfxx-mips.c:12350
+#: elfxx-mips.c:12372 elfxx-mips.c:12398
 msgid "Warning: %B uses hard float, %B uses soft float"
 msgstr "Aviso: %B usa coma flotante hard, %B usa coma flotante soft"
 
-#: elf32-ppc.c:3888 elf32-ppc.c:3892
+#: elf32-ppc.c:4070 elf32-ppc.c:4074
 msgid "Warning: %B uses double-precision hard float, %B uses single-precision hard float"
 msgstr "Aviso: %B usa coma flotante hard de doble precisión, %B usa coma flotante hard de precisión simple"
 
-#: elf32-ppc.c:3896
+#: elf32-ppc.c:4078
 msgid "Warning: %B uses soft float, %B uses single-precision hard float"
 msgstr "Aviso: %B usa coma flotante soft, %B usa coma flotante hard de precisión simple"
 
-#: elf32-ppc.c:3903 elf32-ppc.c:3907 elfxx-mips.c:12248 elfxx-mips.c:12252
+#: elf32-ppc.c:4085 elf32-ppc.c:4089 elfxx-mips.c:12304 elfxx-mips.c:12308
 msgid "Warning: %B uses unknown floating point ABI %d"
 msgstr "Aviso: %B usa la ABI de coma flotante desconocida %d"
 
-#: elf32-ppc.c:3949 elf32-ppc.c:3953
+#: elf32-ppc.c:4131 elf32-ppc.c:4135
 msgid "Warning: %B uses unknown vector ABI %d"
 msgstr "Aviso: %B usa la ABI de vector desconocida %d"
 
-#: elf32-ppc.c:3957
+#: elf32-ppc.c:4139
 msgid "Warning: %B uses vector ABI \"%s\", %B uses \"%s\""
 msgstr "Aviso: %B usa la ABI de vector \"%s\", %B usa \"%s\""
 
-#: elf32-ppc.c:4011
+#: elf32-ppc.c:4156 elf32-ppc.c:4159
+msgid "Warning: %B uses r3/r4 for small structure returns, %B uses memory"
+msgstr "Aviso: %B usa r3/r4 para devoluciones de estructura small, %B usa memoria"
+
+#: elf32-ppc.c:4162 elf32-ppc.c:4166
+msgid "Warning: %B uses unknown small structure return convention %d"
+msgstr "Aviso: %B usa la convención de devolución de estructura small %d"
+
+#: elf32-ppc.c:4220
 msgid "%B: compiled with -mrelocatable and linked with modules compiled normally"
 msgstr "%B: compilado con -mrelocatable y enlazado con módulos compilados de forma normal"
 
-#: elf32-ppc.c:4019
+#: elf32-ppc.c:4228
 msgid "%B: compiled normally and linked with modules compiled with -mrelocatable"
 msgstr "%B: compilado de forma normal y enlazado con módulos compilados con -mrelocatable"
 
-#: elf32-ppc.c:4105
+#: elf32-ppc.c:4314
 msgid "Using bss-plt due to %B"
 msgstr "Se usa bss-plt debido a %B"
 
-#: elf32-ppc.c:6418 elf64-ppc.c:10881
+#: elf32-ppc.c:7056 elf64-ppc.c:11364
 msgid "%B: unknown relocation type %d for symbol %s"
 msgstr "%B: tipo de reubicación %d desconocido para el símbolo %s"
 
-#: elf32-ppc.c:6668
+#: elf32-ppc.c:7316
 msgid "%B(%A+0x%lx): non-zero addend on %s reloc against `%s'"
 msgstr "%B(%A+0x%lx): adición que no es cero en la reubicación %s contra `%s'"
 
-#: elf32-ppc.c:7024 elf32-ppc.c:7050 elf32-ppc.c:7109
+#: elf32-ppc.c:7499 elf64-ppc.c:11854
+msgid "%B(%A+0x%lx): relocation %s for indirect function %s unsupported"
+msgstr "%B(%A+0x%lx): no se admite la reubicación %s para la función indirecta %s"
+
+#: elf32-ppc.c:7709 elf32-ppc.c:7736 elf32-ppc.c:7787
 msgid "%B: the target (%s) of a %s relocation is in the wrong output section (%s)"
 msgstr "%B: el objetivo (%s) de una reubicación %s está en la sección de salida errónea (%s)"
 
-#: elf32-ppc.c:7164
+#: elf32-ppc.c:7847
 msgid "%B: relocation %s is not yet supported for symbol %s."
 msgstr "%B: la reubicación %s aún no se admite para el símbolo %s."
 
-#: elf32-ppc.c:7272 elf64-ppc.c:11575
+#: elf32-ppc.c:7955 elf64-ppc.c:12110
 msgid "%B(%A+0x%lx): %s reloc against `%s': error %d"
 msgstr "%B(%A+0x%lx): reubicación %s contra `%s': error %d"
 
-#: elf32-s390.c:2246 elf64-s390.c:2220
+#: elf32-ppc.c:8423
+#, c-format
+msgid "%s not defined in linker created %s"
+msgstr "no se definió %s en el %s creado por el enlazador"
+
+#: elf32-s390.c:2207 elf64-s390.c:2179
 msgid "%B(%A+0x%lx): invalid instruction for TLS relocation %s"
 msgstr "%B(%A+0x%lx): instrucción inválida para la reubicación TLS %s"
 
-#: elf32-score.c:1415 elfxx-mips.c:3273
+#: elf32-score.c:1533 elf32-score7.c:1424 elfxx-mips.c:3299
 msgid "not enough GOT space for local GOT entries"
 msgstr "no hay suficiente espacio GOT para entradas GOT locales"
 
-#: elf32-score.c:2545
+#: elf32-score.c:2765
+msgid "address not word align"
+msgstr "la dirección no está alineada a word"
+
+#: elf32-score.c:2850 elf32-score7.c:2685
 #, c-format
 msgid "%s: Malformed reloc detected for section %s"
 msgstr "%s: Se detectó una reubicación malformada para la sección %s"
 
-#: elf32-score.c:2596
+#: elf32-score.c:2901 elf32-score7.c:2736
 msgid "%B: CALL15 reloc at 0x%lx not against global symbol"
 msgstr "%B: la reubicación CALL15 en 0x%lx no es contra un símbolo global"
 
-#: elf32-score.c:3753
+#: elf32-score.c:4042 elf32-score7.c:3879
 #, c-format
 msgid " [pic]"
 msgstr " [pic]"
 
-#: elf32-score.c:3757
+#: elf32-score.c:4046 elf32-score7.c:3883
 #, c-format
 msgid " [fix dep]"
 msgstr " [fix dep]"
 
-#: elf32-score.c:3799
+#: elf32-score.c:4088 elf32-score7.c:3925
 msgid "%B: warning: linking PIC files with non-PIC files"
 msgstr "%B: aviso: se enlazan ficheros PIC con ficheros que no son PIC"
 
@@ -1796,9 +1931,9 @@ msgstr "%B: la directiva IMPORT AS para %s oculta un IMPORT AS previo"
 
 #: elf32-sh-symbian.c:383
 msgid "%B: Unrecognised .directive command: %s"
-msgstr "%B: Orden .directive no reconocida: %s"
+msgstr "%B: No se reconoce la orden .directive: %s"
 
-#: elf32-sh-symbian.c:504
+#: elf32-sh-symbian.c:503
 msgid "%B: Failed to add renamed symbol %s"
 msgstr "%B: Falló al agregar el símbolo renombrado %s"
 
@@ -1834,46 +1969,46 @@ msgstr "%B: 0x%lx: aviso: cuenta err
 msgid "%B: 0x%lx: fatal: reloc overflow while relaxing"
 msgstr "%B: 0x%lx: fatal: desbordamiento de reubicación durante la relajación"
 
-#: elf32-sh.c:3279 elf64-sh64.c:1526
+#: elf32-sh.c:3270 elf64-sh64.c:1526
 msgid "Unexpected STO_SH5_ISA32 on local symbol is not handled"
 msgstr "No se maneja un STO_SH5_ISA32 inesperado en un símbolo local"
 
-#: elf32-sh.c:3516
+#: elf32-sh.c:3507
 msgid "%B: 0x%lx: fatal: unaligned branch target for relax-support relocation"
 msgstr "%B: 0x%lx: fatal: objetivo de ramificación sin alineación para la reubicación de soporte de relajamiento"
 
-#: elf32-sh.c:3549 elf32-sh.c:3564
+#: elf32-sh.c:3540 elf32-sh.c:3555
 msgid "%B: 0x%lx: fatal: unaligned %s relocation 0x%lx"
 msgstr "%B: 0x%lx: fatal: reubicación %s sin alineación 0x%lx"
 
-#: elf32-sh.c:3578
+#: elf32-sh.c:3569
 msgid "%B: 0x%lx: fatal: R_SH_PSHA relocation %d not in range -32..32"
 msgstr "%B: 0x%lx: fatal: la reubicación R_SH_PSHA %d no está en el rango -32..32"
 
-#: elf32-sh.c:3592
+#: elf32-sh.c:3583
 msgid "%B: 0x%lx: fatal: R_SH_PSHL relocation %d not in range -32..32"
 msgstr "%B: 0x%lx: fatal: la reubicación R_SH_PSHL %d no está en el rango -32..32"
 
-#: elf32-sh.c:5310 elf64-alpha.c:4552
+#: elf32-sh.c:5256 elf64-alpha.c:4525
 msgid "%B: TLS local exec code cannot be linked into shared objects"
 msgstr "%B: el código de ejecución local TLS no se puede enlazar en objetos compartidos"
 
-#: elf32-sh64.c:222 elf64-sh64.c:2345
+#: elf32-sh64.c:222 elf64-sh64.c:2333
 #, c-format
 msgid "%s: compiled as 32-bit object and %s is 64-bit"
 msgstr "%s: compilado como un objeto de 32-bit y %s es de 64-bit"
 
-#: elf32-sh64.c:225 elf64-sh64.c:2348
+#: elf32-sh64.c:225 elf64-sh64.c:2336
 #, c-format
 msgid "%s: compiled as 64-bit object and %s is 32-bit"
 msgstr "%s: compilado como un objeto de 64-bit y %s es de 32-bit"
 
-#: elf32-sh64.c:227 elf64-sh64.c:2350
+#: elf32-sh64.c:227 elf64-sh64.c:2338
 #, c-format
 msgid "%s: object size does not match that of target %s"
 msgstr "%s: el tamaño del objeto no coincide con el tamaño del objetivo %s"
 
-#: elf32-sh64.c:450 elf64-sh64.c:2888
+#: elf32-sh64.c:450 elf64-sh64.c:2852
 #, c-format
 msgid "%s: encountered datalabel symbol in input"
 msgstr "%s: se encontró un símbolo datalabel en la entrada"
@@ -1889,7 +2024,7 @@ msgstr "No coincide PTA: una direcci
 #: elf32-sh64.c:548
 #, c-format
 msgid "%s: GAS error: unexpected PTB insn with R_SH_PT_16"
-msgstr "%s: error de GAS: instrucción PTB inesperada con R_SH_PT_16"
+msgstr "%s: error de GAS: insn PTB inesperada con R_SH_PT_16"
 
 #: elf32-sh64.c:597
 msgid "%B: error: unaligned relocation type %d at %08x reloc %p\n"
@@ -1913,103 +2048,119 @@ msgstr "%B: compilado para un sistema de 64 bit y el objetivo es de 32 bit"
 msgid "%B: linking little endian files with big endian files"
 msgstr "%B: se enlazan ficheros little endian con ficheros big endian"
 
-#: elf32-spu.c:607
+#: elf32-spu.c:723
+msgid "%X%P: overlay section %A does not start on a cache line.\n"
+msgstr "%X%P: la sección de sobreescritura %A no inicia en una línea de caché.\n"
+
+#: elf32-spu.c:731
+msgid "%X%P: overlay section %A is larger than a cache line.\n"
+msgstr "%X%P: la sección de sobreescritura %A es más grande que una línea de caché.\n"
+
+#: elf32-spu.c:751
+msgid "%X%P: overlay section %A is not in cache area.\n"
+msgstr "%X%P: la sección de sobreescritura %A no está en el área de caché.\n"
+
+#: elf32-spu.c:791
 msgid "%X%P: overlay sections %A and %A do not start at the same address.\n"
 msgstr "%X%P: las secciones de sobreescritura %A y %A no inician en la misma dirección.\n"
 
-#: elf32-spu.c:805
+#: elf32-spu.c:1015
 msgid "warning: call to non-function symbol %s defined in %B"
 msgstr "aviso: se llama al símbolo %s que no es función, definido en %B"
 
-#: elf32-spu.c:1406
+#: elf32-spu.c:1365
+msgid "%A:0x%v lrlive .brinfo (%u) differs from analysis (%u)\n"
+msgstr "%A:0x%v lrlive .brinfo (%u) difiere del análisis (%u)\n"
+
+#: elf32-spu.c:1884
 msgid "%B is not allowed to define %s"
-msgstr "%B no se permite para definir %s"
+msgstr "%B no tiene permitido definir %s"
 
-#: elf32-spu.c:1453
+#: elf32-spu.c:1892
+#, c-format
+msgid "you are not allowed to define %s in a script"
+msgstr "no se le permite definir %s en un guión"
+
+#: elf32-spu.c:1926
 #, c-format
 msgid "%s in overlay section"
 msgstr "%s en la sección de sobreescritura"
 
-#: elf32-spu.c:1469
+#: elf32-spu.c:1955
 msgid "overlay stub relocation overflow"
-msgstr "desbordamiento del segmento de reubicación de sobreescritura"
+msgstr "desbordamiento de la reubicación de cabo de sobreescritura"
 
-#: elf32-spu.c:1478 elf64-ppc.c:10078
+#: elf32-spu.c:1964 elf64-ppc.c:10441
 msgid "stubs don't match calculated size"
 msgstr "los cabos no coinciden con el tamaño calculado"
 
-#: elf32-spu.c:1976
+#: elf32-spu.c:2546
 #, c-format
 msgid "warning: %s overlaps %s\n"
 msgstr "aviso: %s sobreescribe %s\n"
 
-#: elf32-spu.c:1992
+#: elf32-spu.c:2562
 #, c-format
 msgid "warning: %s exceeds section size\n"
 msgstr "aviso: %s excede el tamaño de la sección\n"
 
-#: elf32-spu.c:2023
+#: elf32-spu.c:2593
 msgid "%A:0x%v not found in function table\n"
 msgstr "%A:0x%v no se encuentra en la tabla de función\n"
 
-#: elf32-spu.c:2165
+#: elf32-spu.c:2740
 msgid "%B(%A+0x%v): call to non-code section %B(%A), analysis incomplete\n"
 msgstr "%B(%A+0x%v): se llama a la sección %B(%A) que no es de código, análisis incompleto\n"
 
-#: elf32-spu.c:2339
-#, c-format
-msgid "%A link_order not found\n"
-msgstr "no se encontró link_order %A\n"
-
-#: elf32-spu.c:2706
+#: elf32-spu.c:3297
 #, c-format
 msgid "Stack analysis will ignore the call from %s to %s\n"
 msgstr "El análisis de pila descartará la llamada de %s a %s\n"
 
-#: elf32-spu.c:3348
+#: elf32-spu.c:3988
 msgid "  %s: 0x%v\n"
 msgstr "  %s: 0x%v\n"
 
-#: elf32-spu.c:3349
+#: elf32-spu.c:3989
 msgid "%s: 0x%v 0x%v\n"
 msgstr "%s: 0x%v 0x%v\n"
 
-#: elf32-spu.c:3354
+#: elf32-spu.c:3994
 msgid "  calls:\n"
 msgstr "  llama:\n"
 
-#: elf32-spu.c:3362
+#: elf32-spu.c:4002
 #, c-format
 msgid "   %s%s %s\n"
 msgstr "   %s%s %s\n"
 
-#: elf32-spu.c:3564
+#: elf32-spu.c:4304
 #, c-format
 msgid "%s duplicated in %s\n"
 msgstr "%s duplicado en %s\n"
 
-#: elf32-spu.c:3568
+#: elf32-spu.c:4308
 #, c-format
 msgid "%s duplicated\n"
 msgstr "%s duplicado\n"
 
-#: elf32-spu.c:3575
+#: elf32-spu.c:4315
 msgid "sorry, no support for duplicate object files in auto-overlay script\n"
 msgstr "perdón, no se admiten ficheros objeto duplicados en el guión de sobreescritura automática\n"
 
-#: elf32-spu.c:3605
+#: elf32-spu.c:4356
 msgid "non-overlay size of 0x%v plus maximum overlay size of 0x%v exceeds local store\n"
 msgstr "eltamaño 0x%v que no es de sobreescritura mas el tamaño de sobreescritura máximo de 0x%v excede el almacenamiento local\n"
 
-#: elf32-spu.c:3741
+#: elf32-spu.c:4512
 msgid "%B:%A%s exceeds overlay size\n"
 msgstr "%B:%A%s excede el tamaño de sobreescritura\n"
 
-#: elf32-spu.c:3862
+#: elf32-spu.c:4669
 msgid "Stack size for call graph root nodes.\n"
 msgstr "Tamaño de la pila para los nodos raíz del grafo de llamadas.\n"
 
-#: elf32-spu.c:3863
+#: elf32-spu.c:4670
 msgid ""
 "\n"
 "Stack size for functions.  Annotations: '*' max stack, 't' tail call\n"
@@ -2017,164 +2168,168 @@ msgstr ""
 "\n"
 "Tamaño de la pila para funciones. Anotaciones: '*' max de pila, 't' llamada cola\n"
 
-#: elf32-spu.c:3871
+#: elf32-spu.c:4680
 msgid "Maximum stack required is 0x%v\n"
 msgstr "La pila máxima requerida es 0x%v\n"
 
-#: elf32-spu.c:4067
+#: elf32-spu.c:4771
+msgid "fatal error while creating .fixup"
+msgstr "error fatal al crear .fixup"
+
+#: elf32-spu.c:5009
 msgid "%B(%s+0x%lx): unresolvable %s relocation against symbol `%s'"
 msgstr "%B(%s+0x%lx): reubicación %s sin resolución contra el símbolo `%s'"
 
-#: elf32-v850.c:165
+#: elf32-v850.c:163
 #, c-format
 msgid "Variable `%s' cannot occupy in multiple small data regions"
 msgstr "La variable `%s' no puede ocupar múltiples regiones de datos small"
 
-#: elf32-v850.c:168
+#: elf32-v850.c:166
 #, c-format
 msgid "Variable `%s' can only be in one of the small, zero, and tiny data regions"
-msgstr "La variable `%s' solamente puede estar en una de las regiones de datos small, cero, y tiny"
+msgstr "La variable `%s' solamente puede estar en una de las regiones de datos small, zero, y tiny"
 
-#: elf32-v850.c:171
+#: elf32-v850.c:169
 #, c-format
 msgid "Variable `%s' cannot be in both small and zero data regions simultaneously"
-msgstr "La variable `%s' no puede estar simultáneamente en las regiones de datos small y cero"
+msgstr "La variable `%s' no puede estar simultáneamente en las regiones de datos small y zero"
 
-#: elf32-v850.c:174
+#: elf32-v850.c:172
 #, c-format
 msgid "Variable `%s' cannot be in both small and tiny data regions simultaneously"
 msgstr "La variable `%s' no puede estar simultáneamente en las regiones de datos small y tiny"
 
-#: elf32-v850.c:177
+#: elf32-v850.c:175
 #, c-format
 msgid "Variable `%s' cannot be in both zero and tiny data regions simultaneously"
-msgstr "La variable `%s' no puede estar simultáneamente en las regiones de datos cero y tiny"
+msgstr "La variable `%s' no puede estar simultáneamente en las regiones de datos zero y tiny"
 
-#: elf32-v850.c:480
+#: elf32-v850.c:478
 #, c-format
 msgid "FAILED to find previous HI16 reloc\n"
 msgstr "FALLO para encontrar la reubicación HI16 previa\n"
 
-#: elf32-v850.c:1715
+#: elf32-v850.c:1713
 msgid "could not locate special linker symbol __gp"
 msgstr "no se puede localizar el símbolo especial del enlazador __gp"
 
-#: elf32-v850.c:1719
+#: elf32-v850.c:1717
 msgid "could not locate special linker symbol __ep"
 msgstr "no se puede localizar el símbolo especial del enlazador __ep"
 
-#: elf32-v850.c:1723
+#: elf32-v850.c:1721
 msgid "could not locate special linker symbol __ctbp"
 msgstr "no se puede localizar el símbolo especial del enlazador __ctbp"
 
-#: elf32-v850.c:1873
+#: elf32-v850.c:1871
 msgid "%B: Architecture mismatch with previous modules"
 msgstr "%B: No coincide la arquitectura con los módulos previos"
 
-#: elf32-v850.c:1892
+#: elf32-v850.c:1890
 #, c-format
 msgid "private flags = %lx: "
 msgstr "opciones privadas = %lx: "
 
-#: elf32-v850.c:1897
+#: elf32-v850.c:1895
 #, c-format
 msgid "v850 architecture"
 msgstr "arquitectura v850"
 
-#: elf32-v850.c:1898
+#: elf32-v850.c:1896
 #, c-format
 msgid "v850e architecture"
 msgstr "arquitectura v850e"
 
-#: elf32-v850.c:1899
+#: elf32-v850.c:1897
 #, c-format
 msgid "v850e1 architecture"
 msgstr "arquitectura v850e1"
 
-#: elf32-vax.c:541
+#: elf32-vax.c:543
 #, c-format
 msgid " [nonpic]"
 msgstr " [no pic]"
 
-#: elf32-vax.c:544
+#: elf32-vax.c:546
 #, c-format
 msgid " [d-float]"
 msgstr " [flotante-d]"
 
-#: elf32-vax.c:547
+#: elf32-vax.c:549
 #, c-format
 msgid " [g-float]"
 msgstr " [flotante-g]"
 
-#: elf32-vax.c:657
+#: elf32-vax.c:666
 #, c-format
 msgid "%s: warning: GOT addend of %ld to `%s' does not match previous GOT addend of %ld"
 msgstr "%s: aviso: la adición GOT de %ld a `%s' no coincide con la adición previa GOT de %ld"
 
-#: elf32-vax.c:1589
+#: elf32-vax.c:1608
 #, c-format
 msgid "%s: warning: PLT addend of %d to `%s' from %s section ignored"
 msgstr "%s: aviso: se descarta la adición PLT de %d a `%s' de la sección %s"
 
-#: elf32-vax.c:1726
+#: elf32-vax.c:1735
 #, c-format
 msgid "%s: warning: %s relocation against symbol `%s' from %s section"
 msgstr "%s: aviso: reubicación %s contra el símbolo `%s' de la sección %s"
 
-#: elf32-vax.c:1732
+#: elf32-vax.c:1741
 #, c-format
 msgid "%s: warning: %s relocation to 0x%x from %s section"
 msgstr "%s: aviso: reubicación %s a 0x%x de la sección %s"
 
-#: elf32-xstormy16.c:451 elf32-ia64.c:2794 elf64-ia64.c:2794
+#: elf32-xstormy16.c:451 elf32-ia64.c:2791 elf64-ia64.c:2791
 msgid "non-zero addend in @fptr reloc"
 msgstr "adición que no es cero en la reubicación @fptr"
 
-#: elf32-xtensa.c:911
+#: elf32-xtensa.c:912
 msgid "%B(%A): invalid property table"
 msgstr "%B(%A): tabla de propiedades inválida"
 
-#: elf32-xtensa.c:2734
+#: elf32-xtensa.c:2740
 msgid "%B(%A+0x%lx): relocation offset out of range (size=0x%x)"
 msgstr "%B(%A+0x%lx): desplazamiento de reubicación fuera de rango (tamaño=0x%x)"
 
-#: elf32-xtensa.c:2813 elf32-xtensa.c:2934
+#: elf32-xtensa.c:2819 elf32-xtensa.c:2940
 msgid "dynamic relocation in read-only section"
 msgstr "reubicación dinámica en la sección de sólo lectura"
 
-#: elf32-xtensa.c:2910
+#: elf32-xtensa.c:2916
 msgid "TLS relocation invalid without dynamic sections"
 msgstr "reubicación TLS inválida sin secciones dinámicas"
 
-#: elf32-xtensa.c:3127
+#: elf32-xtensa.c:3133
 msgid "internal inconsistency in size of .got.loc section"
 msgstr "inconsistencia interna en el tamaño de la sección .got.loc"
 
-#: elf32-xtensa.c:3437
+#: elf32-xtensa.c:3443
 msgid "%B: incompatible machine type. Output is 0x%x. Input is 0x%x"
 msgstr "%B: tipo de máquina incompatible. La salida es 0x%x. La entrada es 0x%x"
 
-#: elf32-xtensa.c:4666 elf32-xtensa.c:4674
+#: elf32-xtensa.c:4672 elf32-xtensa.c:4680
 msgid "Attempt to convert L32R/CALLX to CALL failed"
 msgstr "Falló el intento de convertir L32R/CALLX a CALL"
 
-#: elf32-xtensa.c:6276 elf32-xtensa.c:6352 elf32-xtensa.c:7468
+#: elf32-xtensa.c:6290 elf32-xtensa.c:6366 elf32-xtensa.c:7486
 msgid "%B(%A+0x%lx): could not decode instruction; possible configuration mismatch"
 msgstr "%B(%A+0x%lx): no se puede decodificar la instrucción; posible falta de coincidencia de la configuración"
 
-#: elf32-xtensa.c:7208
+#: elf32-xtensa.c:7226
 msgid "%B(%A+0x%lx): could not decode instruction for XTENSA_ASM_SIMPLIFY relocation; possible configuration mismatch"
 msgstr "%B(%A+0x%lx): no se puede decodificar la instrucción para la reubicación XTENSA_ASM_SIMPLIFY; posible falta de coincidencia de la configuración"
 
-#: elf32-xtensa.c:8969
+#: elf32-xtensa.c:8987
 msgid "invalid relocation address"
 msgstr "dirección de reubicación inválida"
 
-#: elf32-xtensa.c:9018
+#: elf32-xtensa.c:9036
 msgid "overflow after relaxation"
 msgstr "desbordamiento después de la relajación"
 
-#: elf32-xtensa.c:10154
+#: elf32-xtensa.c:10167
 msgid "%B(%A+0x%lx): unexpected fix for %s relocation"
 msgstr "%B(%A+0x%lx): compostura inesperada para la reubicación %s"
 
@@ -2182,51 +2337,55 @@ msgstr "%B(%A+0x%lx): compostura inesperada para la reubicaci
 msgid "GPDISP relocation did not find ldah and lda instructions"
 msgstr "la reubicación GPDISP no encontró las instrucciones ldah y lda"
 
-#: elf64-alpha.c:2416
+#: elf64-alpha.c:2389
 msgid "%B: .got subsegment exceeds 64K (size %d)"
 msgstr "%B: el subsegmento .got excede los 64K (tamaño %d)"
 
-#: elf64-alpha.c:4296 elf64-alpha.c:4308
+#: elf64-alpha.c:4269 elf64-alpha.c:4281
 msgid "%B: gp-relative relocation against dynamic symbol %s"
-msgstr "%B: reubicación gp relativa contra el símbolo dinámico %s"
+msgstr "%B: reubicación relativa a gp contra el símbolo dinámico %s"
 
-#: elf64-alpha.c:4334 elf64-alpha.c:4469
+#: elf64-alpha.c:4307 elf64-alpha.c:4442
 msgid "%B: pc-relative relocation against dynamic symbol %s"
-msgstr "%B: reubicación relativa al pc contra el símbolo dinámico %s"
+msgstr "%B: reubicación relativa a pc contra el símbolo dinámico %s"
 
-#: elf64-alpha.c:4362
+#: elf64-alpha.c:4335
 msgid "%B: change in gp: BRSGP %s"
 msgstr "%B: cambio en gp: BRSGP %s"
 
-#: elf64-alpha.c:4387
+#: elf64-alpha.c:4360
 msgid "<unknown>"
 msgstr "<desconocido>"
 
-#: elf64-alpha.c:4392
+#: elf64-alpha.c:4365
 msgid "%B: !samegp reloc against symbol without .prologue: %s"
 msgstr "%B: reubicación !samegp contra un símbolo sin .prologue: %s"
 
-#: elf64-alpha.c:4444
+#: elf64-alpha.c:4417
 msgid "%B: unhandled dynamic relocation against %s"
 msgstr "%B: reubicación dinámica sin manejar contra %s"
 
-#: elf64-alpha.c:4476
+#: elf64-alpha.c:4449
 msgid "%B: pc-relative relocation against undefined weak symbol %s"
-msgstr "%B: reubicación relativa al pc contra el símbolo débil sin definir %s"
+msgstr "%B: reubicación relativa a pc contra el símbolo débil sin definir %s"
 
-#: elf64-alpha.c:4536
+#: elf64-alpha.c:4509
 msgid "%B: dtp-relative relocation against dynamic symbol %s"
 msgstr "%B: reubicación relativa a dtp contra el símbolo dinámico %s"
 
-#: elf64-alpha.c:4559
+#: elf64-alpha.c:4532
 msgid "%B: tp-relative relocation against dynamic symbol %s"
 msgstr "%B: reubicación relativa a tp contra el símbolo dinámico %s"
 
-#: elf64-hppa.c:2071
+#: elf64-hppa.c:2091
 #, c-format
 msgid "stub entry for %s cannot load .plt, dp offset = %ld"
 msgstr "la entrada de cabo para %s no puede cargar .plt, desplazamiento dp = %ld"
 
+#: elf64-hppa.c:3273
+msgid "%B(%A+0x%lx): cannot reach %s"
+msgstr "%B(%A+0x%lx): no se puede alcanzar %s"
+
 #: elf64-mmix.c:1177
 #, c-format
 msgid ""
@@ -2284,65 +2443,65 @@ msgstr ""
 "Inconsistencia interna: %u restante != %u máximo.\n"
 "  Por favor reporte este bicho."
 
-#: elf64-ppc.c:2561 libbfd.c:978
+#: elf64-ppc.c:2691 libbfd.c:978
 msgid "%B: compiled for a big endian system and target is little endian"
 msgstr "%B: compilado para un sistema big endian y el objetivo es little endian"
 
-#: elf64-ppc.c:2564 libbfd.c:980
+#: elf64-ppc.c:2694 libbfd.c:980
 msgid "%B: compiled for a little endian system and target is big endian"
 msgstr "%B: compilado para un sistema little endian y el objetivo es big endian"
 
-#: elf64-ppc.c:6065
+#: elf64-ppc.c:6338
 #, c-format
 msgid "copy reloc against `%s' requires lazy plt linking; avoid setting LD_BIND_NOW=1 or upgrade gcc"
-msgstr "la reubicación de copia contra `%s' requiere de enlazado plt suelto; evite establecer LD_BIND_NOW=1 o actualice gcc"
+msgstr "la reubicación de copia contra `%s' requiere de enlazado plt flojo; evite establecer LD_BIND_NOW=1 o actualice gcc"
 
-#: elf64-ppc.c:6486
+#: elf64-ppc.c:6767
 msgid "dynreloc miscount for %B, section %A"
 msgstr "cuenta errónea de la reubicación dinámica de %B, sección %A"
 
-#: elf64-ppc.c:6570
+#: elf64-ppc.c:6851
 msgid "%B: .opd is not a regular array of opd entries"
 msgstr "%B: .opd no es una matriz regular de entradas opd"
 
-#: elf64-ppc.c:6579
+#: elf64-ppc.c:6860
 msgid "%B: unexpected reloc type %u in .opd section"
 msgstr "%B: tipo de reubicación %u inesperado en la sección .opd"
 
-#: elf64-ppc.c:6600
+#: elf64-ppc.c:6881
 msgid "%B: undefined sym `%s' in .opd section"
-msgstr "%B: símbolo `%s' indefinido en la sección .opd"
+msgstr "%B: símbolo `%s' sin definir en la sección .opd"
 
-#: elf64-ppc.c:7377 elf64-ppc.c:7754
+#: elf64-ppc.c:7640 elf64-ppc.c:8017
 #, c-format
 msgid "%s defined in removed toc entry"
 msgstr "se definió %s en la entrada toc eliminada"
 
-#: elf64-ppc.c:8581
+#: elf64-ppc.c:8910
 #, c-format
 msgid "long branch stub `%s' offset overflow"
 msgstr "desbordamiento del desplazamiento de stub de ramificación long `%s'"
 
-#: elf64-ppc.c:8640
+#: elf64-ppc.c:8969
 #, c-format
 msgid "can't find branch stub `%s'"
 msgstr "no se puede encontrar la ramificación de cabo `%s'"
 
-#: elf64-ppc.c:8702 elf64-ppc.c:8822
+#: elf64-ppc.c:9031 elf64-ppc.c:9169
 #, c-format
 msgid "linkage table error against `%s'"
 msgstr "error de la tabla de enlazado contra `%s'"
 
-#: elf64-ppc.c:8978
+#: elf64-ppc.c:9326
 #, c-format
 msgid "can't build branch stub `%s'"
 msgstr "no se puede construir la ramificación de cabos `%s'"
 
-#: elf64-ppc.c:9451
+#: elf64-ppc.c:9799
 msgid "%B section %A exceeds stub group size"
-msgstr "%B sección %A excede el tamaño de grupo de stub"
+msgstr "%B sección %A excede el tamaño de grupo de cabos"
 
-#: elf64-ppc.c:10090
+#: elf64-ppc.c:10453
 #, c-format
 msgid ""
 "linker stubs in %u group%s\n"
@@ -2359,19 +2518,19 @@ msgstr ""
 "  ajuste toc long %lu\n"
 "  llamada plt     %lu"
 
-#: elf64-ppc.c:10769
+#: elf64-ppc.c:11252
 msgid "%B(%A+0x%lx): automatic multiple TOCs not supported using your crt files; recompile with -mminimal-toc or upgrade gcc"
 msgstr "%B(%A+0x%lx): no se admiten los TOCs múltiples automáticos, utilizando sus ficheros crt; recompile con -mminimal-toc o actualice gcc"
 
-#: elf64-ppc.c:10777
+#: elf64-ppc.c:11260
 msgid "%B(%A+0x%lx): sibling call optimization to `%s' does not allow automatic multiple TOCs; recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make `%s' extern"
 msgstr "%B(%A+0x%lx): la optimización de llamada hermana a `%s' no permite TOCs múltiples automáticos; recompile con -mminimal-toc ó -fno-optimize-sibling-calls, o vuelva `%s' externa"
 
-#: elf64-ppc.c:11427
+#: elf64-ppc.c:11961
 msgid "%B: relocation %s is not supported for symbol %s."
 msgstr "%B: no se admite la reubicación %s para el símbolo %s."
 
-#: elf64-ppc.c:11509
+#: elf64-ppc.c:12044
 msgid "%B: error: relocation %s not a multiple of %d"
 msgstr "%B: error: la reubicación %s no es un múltiplo de %d"
 
@@ -2396,31 +2555,31 @@ msgstr "El s
 msgid "Symbol `%s' has differing types: %s in %B, previously REGISTER in %B"
 msgstr "El símbolo `%s' tiene tipos divergentes: %s en %B, previamente REGISTER en %B"
 
-#: elf64-sparc.c:678
+#: elf64-sparc.c:679
 msgid "%B: linking UltraSPARC specific with HAL specific code"
 msgstr "%B: se enlaza código específico de UltraSPARC con código específico de HAL"
 
-#: elf64-x86-64.c:1047 elf64-x86-64.c:1207 elfxx-mips.c:7834
-msgid "%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"
-msgstr "%B: no se puede usar la reubicación %s contra `%s' cuando se hace un objeto compartido; recompile con -fPIC"
-
-#: elf64-x86-64.c:1138
+#: elf64-x86-64.c:1337
 msgid "%B: '%s' accessed both as normal and thread local symbol"
 msgstr "%B: se accedió a '%s' como un símbolo normal y como un símbolo local de hilo"
 
-#: elf64-x86-64.c:2559
+#: elf64-x86-64.c:2701
+msgid "%B: relocation %s against STT_GNU_IFUNC symbol `%s' has non-zero addend: %d"
+msgstr "%B: la reubicación %s contra el símbolo STT_GNU_IFUNC `%s' con adición que no es cero: %d"
+
+#: elf64-x86-64.c:2980
 msgid "%B: relocation R_X86_64_GOTOFF64 against protected function `%s' can not be used when making a shared object"
 msgstr "%B: no se puede usar la reubicación R_X86_64_GOTOFF contra la función protegida `%s' cuando se hace un objeto compartido"
 
-#: elf64-x86-64.c:2670
+#: elf64-x86-64.c:3091
 msgid "; recompile with -fPIC"
 msgstr "; recompile con -fPIC"
 
-#: elf64-x86-64.c:2675
+#: elf64-x86-64.c:3096
 msgid "%B: relocation %s against %s `%s' can not be used when making a shared object%s"
 msgstr "%B: no se puede usar la reubicación %s contra %s `%s' cuando se hace un objeto compartido%s"
 
-#: elf64-x86-64.c:2677
+#: elf64-x86-64.c:3098
 msgid "%B: relocation %s against undefined %s `%s' can not be used when making a shared object%s"
 msgstr "%B: no se puede usar la reubicación %s contra %s sin definir `%s' cuando se hace un objeto compartido%s"
 
@@ -2434,7 +2593,7 @@ msgstr "aviso: %s tiene un 
 msgid "%s: version count (%ld) does not match symbol count (%ld)"
 msgstr "%s: la cuenta de versión (%ld) no coincide con la cuenta de símbolos (%ld)"
 
-#: elfcode.h:1435
+#: elfcode.h:1441
 #, c-format
 msgid "%s(%s): relocation %d has invalid symbol index %ld"
 msgstr "%s(%s): la reubicación %d tiene un índice de símbolo %ld inválido"
@@ -2443,305 +2602,313 @@ msgstr "%s(%s): la reubicaci
 msgid "Warning: %B is truncated: expected core file size >= %lu, found: %lu."
 msgstr "Aviso: se truncó %B: se esperaba el tamaño de fichero core >= %lu, se encontró: %lu."
 
-#: elflink.c:1028
+#: elflink.c:1113
 msgid "%s: TLS definition in %B section %A mismatches non-TLS definition in %B section %A"
 msgstr "%s: la definición TLS en %B sección %A no coincide con la definición que no es TLS en %B sección %A"
 
-#: elflink.c:1032
+#: elflink.c:1117
 msgid "%s: TLS reference in %B mismatches non-TLS reference in %B"
-msgstr "%s: la referencia TLS en %b no coincide con la referencia que no es TLS en %B"
+msgstr "%s: la referencia TLS en %B no coincide con la referencia que no es TLS en %B"
 
-#: elflink.c:1036
+#: elflink.c:1121
 msgid "%s: TLS definition in %B section %A mismatches non-TLS reference in %B"
 msgstr "%s: la definición TLS en %B sección %A no coincide con la referencia que no es TLS en %B"
 
-#: elflink.c:1040
+#: elflink.c:1125
 msgid "%s: TLS reference in %B mismatches non-TLS definition in %B section %A"
 msgstr "%s: la referencia TLS en %B no coincide con la definición que no es TLS en %B sección %A"
 
-#: elflink.c:1654
+#: elflink.c:1764
 msgid "%B: unexpected redefinition of indirect versioned symbol `%s'"
 msgstr "%B: redefinición inesperada del símbolo con versión indirecta `%s'"
 
-#: elflink.c:1982
+#: elflink.c:2077
 msgid "%B: version node not found for symbol %s"
 msgstr "%B: no se encuentra la versión del nodo para el símbolo %s"
 
-#: elflink.c:2130
+#: elflink.c:2167
 msgid "%B: bad reloc symbol index (0x%lx >= 0x%lx) for offset 0x%lx in section `%A'"
 msgstr "%B: índice de símbolos de reubicación inválido (0x%lx >= 0x%lx) erróneo para el desplazamiento 0x%lx en la sección `%A'"
 
-#: elflink.c:2327
+#: elflink.c:2178
+msgid "%B: non-zero symbol index (0x%lx) for offset 0x%lx in section `%A' when the object file has no symbol table"
+msgstr "%B: índice de símbolos que no es cero (0x%lx) para el desplazamiento 0x%lx) en la sección `%A' cuando el fichero objeto no tiene tabla de símbolos"
+
+#: elflink.c:2375
 msgid "%B: relocation size mismatch in %B section %A"
 msgstr "%B: el tamaño de reubicación no coincide en %B sección %A"
 
-#: elflink.c:2629
+#: elflink.c:2678
 #, c-format
 msgid "warning: type and size of dynamic symbol `%s' are not defined"
 msgstr "aviso: el tipo y tamaño del símbolo dinámico `%s' no están definidos"
 
-#: elflink.c:3953
+#: elflink.c:3424
+msgid "%P: alternate ELF machine code found (%d) in %B, expecting %d\n"
+msgstr "%P: se encontró código máquina ELF alternativo (%d) en %B, se espera %d\n"
+
+#: elflink.c:4032
 msgid "%B: %s: invalid version %u (max %d)"
 msgstr "%B: %s: versión %u inválida (máximo %d)"
 
-#: elflink.c:3989
+#: elflink.c:4068
 msgid "%B: %s: invalid needed version %d"
 msgstr "%B: %s: versión requerida %d inválida"
 
-#: elflink.c:4172
+#: elflink.c:4253
 msgid "Warning: alignment %u of common symbol `%s' in %B is greater than the alignment (%u) of its section %A"
 msgstr "Aviso: la alineación %u del símbolo común `%s' en %B es más grande que la alineación (%u) de su sección %A"
 
-#: elflink.c:4178
+#: elflink.c:4259
 msgid "Warning: alignment %u of symbol `%s' in %B is smaller than %u in %B"
 msgstr "Aviso: la alineación %u del símbolo `%s' en %B es más pequeña que %u en %B"
 
-#: elflink.c:4193
+#: elflink.c:4274
 msgid "Warning: size of symbol `%s' changed from %lu in %B to %lu in %B"
 msgstr "Aviso: el tamaño del símbolo `%s' cambió de %lu en %B a %lu en %B"
 
-#: elflink.c:4371
+#: elflink.c:4438
 #, c-format
 msgid "%s: invalid DSO for symbol `%s' definition"
 msgstr "%s: DSO inválido para la definición del símbolo `%s'"
 
-#: elflink.c:5621
+#: elflink.c:5688
 #, c-format
 msgid "%s: undefined version: %s"
 msgstr "%s: versión sin definir: %s"
 
-#: elflink.c:5689
+#: elflink.c:5756
 msgid "%B: .preinit_array section is not allowed in DSO"
 msgstr "%B: no se permite la sección .preinit_array en DSO"
 
-#: elflink.c:7414
+#: elflink.c:7484
 #, c-format
 msgid "undefined %s reference in complex symbol: %s"
-msgstr "referencia %s indefinida en el símbolo complejo: %s"
+msgstr "referencia %s sin definir en el símbolo complejo: %s"
 
-#: elflink.c:7568
+#: elflink.c:7638
 #, c-format
 msgid "unknown operator '%c' in complex symbol"
 msgstr "operador desconocido '%c' en el símbolo complejo"
 
-#: elflink.c:7904 elflink.c:7921 elflink.c:7958 elflink.c:7975
+#: elflink.c:7976 elflink.c:7993 elflink.c:8030 elflink.c:8047
 msgid "%B: Unable to sort relocs - they are in more than one size"
 msgstr "%B: No se pueden ordenar las reubicaciones - son de tamaños diferentes"
 
-#: elflink.c:7935 elflink.c:7989
+#: elflink.c:8007 elflink.c:8061
 msgid "%B: Unable to sort relocs - they are of an unknown size"
 msgstr "%B: No se pueden ordenar las reubicaciones - son de tamaño desconocido"
 
-#: elflink.c:8038
+#: elflink.c:8112
 msgid "Not enough memory to sort relocations"
 msgstr "No hay suficiente memoria para ordenar las reubicaciones"
 
-#: elflink.c:8227
+#: elflink.c:8304
 msgid "%B: Too many sections: %d (>= %d)"
 msgstr "%B: Demasiadas secciones:  %d (>= %d)"
 
-#: elflink.c:8461
+#: elflink.c:8540
 msgid "%B: %s symbol `%s' in %B is referenced by DSO"
 msgstr "%B: el símbolo %s `%s' en %B está referenciado por DSO"
 
-#: elflink.c:8544
+#: elflink.c:8625
 msgid "%B: could not find output section %A for input section %A"
 msgstr "%B: no se puede encontrar la sección de salida %A para la sección de entrada %A"
 
-#: elflink.c:8655
+#: elflink.c:8745
 msgid "%B: %s symbol `%s' isn't defined"
 msgstr "%B: el símbolo %s `%s' no está definido"
 
-#: elflink.c:9141
+#: elflink.c:9301
 msgid "error: %B contains a reloc (0x%s) for section %A that references a non-existent global symbol"
 msgstr "error: %B contiene una reubicación (0x%s) para la sección %A que refiere a un símbolo global que no existe"
 
-#: elflink.c:9205
+#: elflink.c:9366
 msgid "%X`%s' referenced in section `%A' of %B: defined in discarded section `%A' of %B\n"
 msgstr "%X`%s' referido en la sección `%A' de %B: se definió en la sección descartada `%A' de %B\n"
 
-#: elflink.c:9825
+#: elflink.c:9991
 msgid "%A has both ordered [`%A' in %B] and unordered [`%A' in %B] sections"
 msgstr "%A tiene tanto secciones ordenadas [`%A' en %B] como desordenadas [`%A' en %B]"
 
-#: elflink.c:9830
+#: elflink.c:9996
 #, c-format
 msgid "%A has both ordered and unordered sections"
-msgstr "%A tiene tanto secciones ordenadas como desordenadas"
+msgstr "%A tiene secciones tanto ordenadas como desordenadas"
 
-#: elflink.c:10715 elflink.c:10759
+#: elflink.c:10872 elflink.c:10916
 msgid "%B: could not find output section %s"
 msgstr "%B: no se puede encontrar la sección de salida %s"
 
-#: elflink.c:10720
+#: elflink.c:10877
 #, c-format
 msgid "warning: %s section has zero size"
 msgstr "aviso: la sección %s es de tamaño cero"
 
-#: elflink.c:10824
+#: elflink.c:10982
 msgid "%P: warning: creating a DT_TEXTREL in a shared object.\n"
 msgstr "%P: aviso: se crea un DT_TEXTREL en un objeto compartido.\n"
 
-#: elflink.c:11006
+#: elflink.c:11165
 msgid "%P%X: can not read symbols: %E\n"
 msgstr "%P%X: no se pueden leer símbolos: %E\n"
 
-#: elflink.c:11313
+#: elflink.c:11483
 msgid "Removing unused section '%s' in file '%B'"
 msgstr "Se elimina la sección sin uso '%s' en el fichero '%B'"
 
-#: elflink.c:11525
+#: elflink.c:11695
 msgid "Warning: gc-sections option ignored"
 msgstr "Aviso: se descarta la opción gc-sections"
 
-#: elflink.c:12056
+#: elflink.c:12242
 msgid "%B: ignoring duplicate section `%A'"
 msgstr "%B: se descarta la sección duplicada `%A'"
 
-#: elflink.c:12063 elflink.c:12070
+#: elflink.c:12249 elflink.c:12256
 msgid "%B: duplicate section `%A' has different size"
 msgstr "%B: la sección duplicada `%A' tiene tamaño diferente"
 
-#: elflink.c:12078 elflink.c:12083
+#: elflink.c:12264 elflink.c:12269
 msgid "%B: warning: could not read contents of section `%A'"
 msgstr "%B: aviso: no se puede leer el contenido de la sección `%A'"
 
-#: elflink.c:12087
+#: elflink.c:12273
 msgid "%B: warning: duplicate section `%A' has different contents"
 msgstr "%B: aviso: la sección duplicada `%A' tiene contenido diferente"
 
-#: elflink.c:12166 linker.c:3080
-msgid "%F%P: already_linked_table: %E"
-msgstr "%F%P: already_linked_table: %E"
+#: elflink.c:12374 linker.c:3098
+msgid "%F%P: already_linked_table: %E\n"
+msgstr "%F%P: already_linked_table: %E\n"
 
-#: elfxx-mips.c:1197
+#: elfxx-mips.c:1222
 msgid "static procedure (no name)"
 msgstr "procedimiento estático (sin nombre)"
 
-#: elfxx-mips.c:5562
+#: elfxx-mips.c:5588
 msgid "%B: %A+0x%lx: jump to stub routine which is not jal"
 msgstr "%B: %A+0x%lx: salto a una rutina cabo la cual no es jal"
 
-#: elfxx-mips.c:6206 elfxx-mips.c:6427
+#: elfxx-mips.c:6235 elfxx-mips.c:6458
 msgid "%B: Warning: bad `%s' option size %u smaller than its header"
 msgstr "%B: Aviso: el tamaño de opción `%s' %u erróneo es más pequeño que su encabezado"
 
-#: elfxx-mips.c:7174 elfxx-mips.c:7299
+#: elfxx-mips.c:7205 elfxx-mips.c:7330
 msgid "%B: Warning: cannot determine the target function for stub section `%s'"
 msgstr "%B: Aviso: no se puede determinar la función objetivo para la sección de cabo `%s'"
 
-#: elfxx-mips.c:7428
+#: elfxx-mips.c:7459
 msgid "%B: Malformed reloc detected for section %s"
 msgstr "%B: Se detectó una reubicación malformada para la sección %s"
 
-#: elfxx-mips.c:7468
+#: elfxx-mips.c:7499
 msgid "%B: GOT reloc at 0x%lx not expected in executables"
 msgstr "%B: no se esperaba la reubicación GOT en 0x%lx en ejecutables"
 
-#: elfxx-mips.c:7566
+#: elfxx-mips.c:7602
 msgid "%B: CALL16 reloc at 0x%lx not against global symbol"
 msgstr "%B: la reubicación CALL16 en 0x%lx no es contra un símbolo global"
 
-#: elfxx-mips.c:8244
+#: elfxx-mips.c:8280
 #, c-format
 msgid "non-dynamic relocations refer to dynamic symbol %s"
 msgstr "reubicaciones que no son dinámicas se refieren al símbolo dinámico %s"
 
-#: elfxx-mips.c:8947
+#: elfxx-mips.c:8985
 msgid "%B: Can't find matching LO16 reloc against `%s' for %s at 0x%lx in section `%A'"
 msgstr "%B: No se puede encontrar una reubicación LO16 coincidente contra `%s' para %s en 0x%lx en la sección `%A'"
 
-#: elfxx-mips.c:9086
+#: elfxx-mips.c:9124
 msgid "small-data section exceeds 64KB; lower small-data size limit (see option -G)"
 msgstr "la sección small-data excede los 64KB; disminuya el límite de tamaño de small-data (vea la opción -G)"
 
-#: elfxx-mips.c:11887
+#: elfxx-mips.c:11940
 #, c-format
 msgid "%s: illegal section name `%s'"
 msgstr "%s: nombre de sección `%s' ilegal"
 
-#: elfxx-mips.c:12262 elfxx-mips.c:12288
+#: elfxx-mips.c:12318 elfxx-mips.c:12344
 msgid "Warning: %B uses -msingle-float, %B uses -mdouble-float"
 msgstr "Aviso: %B usa -msingle-float, %B usa -mdouble-float"
 
-#: elfxx-mips.c:12274 elfxx-mips.c:12330
+#: elfxx-mips.c:12330 elfxx-mips.c:12386
 msgid "Warning: %B uses -msingle-float, %B uses -mips32r2 -mfp64"
 msgstr "Aviso: %B usa -msingle-float, %B usa -mips32r2 -mfp64"
 
-#: elfxx-mips.c:12300 elfxx-mips.c:12336
+#: elfxx-mips.c:12356 elfxx-mips.c:12392
 msgid "Warning: %B uses -mdouble-float, %B uses -mips32r2 -mfp64"
 msgstr "Aviso: %B usa -mdouble-float, %B usa -mips32r2 -mfp64"
 
-#: elfxx-mips.c:12378
+#: elfxx-mips.c:12434
 msgid "%B: endianness incompatible with that of the selected emulation"
 msgstr "%B: la endianez es incompatible con aquella de la emulación seleccionada"
 
-#: elfxx-mips.c:12389
+#: elfxx-mips.c:12445
 msgid "%B: ABI is incompatible with that of the selected emulation"
 msgstr "%B: la ABI es incompatible con aquella de la emulación seleccionada"
 
-#: elfxx-mips.c:12470
+#: elfxx-mips.c:12526
 msgid "%B: warning: linking abicalls files with non-abicalls files"
 msgstr "%B: aviso: se enlazan ficheros de llamadas abi con ficheros que no son de llamadas abi"
 
-#: elfxx-mips.c:12487
+#: elfxx-mips.c:12543
 msgid "%B: linking 32-bit code with 64-bit code"
 msgstr "%B: se enlaza código de 32-bit con código de 64-bit"
 
-#: elfxx-mips.c:12515
+#: elfxx-mips.c:12571
 msgid "%B: linking %s module with previous %s modules"
 msgstr "%B: se enlaza el módulo %s con módulos %s previos"
 
-#: elfxx-mips.c:12538
+#: elfxx-mips.c:12594
 msgid "%B: ABI mismatch: linking %s module with previous %s modules"
-msgstr "%B: no coincide el ABI: se enlaza el módulo %s con módulos %s previos"
+msgstr "%B: no coincide ABI: se enlaza el módulo %s con módulos %s previos"
 
-#: elfxx-mips.c:12702
+#: elfxx-mips.c:12758
 #, c-format
 msgid " [abi=O32]"
 msgstr " [abi=O32]"
 
-#: elfxx-mips.c:12704
+#: elfxx-mips.c:12760
 #, c-format
 msgid " [abi=O64]"
 msgstr " [abi=O64]"
 
-#: elfxx-mips.c:12706
+#: elfxx-mips.c:12762
 #, c-format
 msgid " [abi=EABI32]"
 msgstr " [abi=EABI32]"
 
-#: elfxx-mips.c:12708
+#: elfxx-mips.c:12764
 #, c-format
 msgid " [abi=EABI64]"
 msgstr " [abi=EABI64]"
 
-#: elfxx-mips.c:12710
+#: elfxx-mips.c:12766
 #, c-format
 msgid " [abi unknown]"
 msgstr " [abi desconocido]"
 
-#: elfxx-mips.c:12712
+#: elfxx-mips.c:12768
 #, c-format
 msgid " [abi=N32]"
 msgstr " [abi=N32]"
 
-#: elfxx-mips.c:12714
+#: elfxx-mips.c:12770
 #, c-format
 msgid " [abi=64]"
 msgstr " [abi=64]"
 
-#: elfxx-mips.c:12716
+#: elfxx-mips.c:12772
 #, c-format
 msgid " [no abi set]"
 msgstr " [no hay conjunto abi]"
 
-#: elfxx-mips.c:12737
+#: elfxx-mips.c:12793
 #, c-format
 msgid " [unknown ISA]"
 msgstr " [ISA desconocido]"
 
-#: elfxx-mips.c:12748
+#: elfxx-mips.c:12804
 #, c-format
 msgid " [not 32bitmode]"
 msgstr " [no es modo 32bit]"
@@ -2751,10 +2918,6 @@ msgstr " [no es modo 32bit]"
 msgid "invalid relocation type %d"
 msgstr "tipo de reubicación %d inválido"
 
-#: elfxx-sparc.c:2976
-msgid "%B: probably compiled without -fPIC?"
-msgstr "%B: ¿Compilado probablemente sin -fPIC?"
-
 #: i386linux.c:455 m68klinux.c:459 sparclinux.c:453
 #, c-format
 msgid "Output file requires shared library `%s'\n"
@@ -2857,15 +3020,75 @@ msgstr "%B: el s
 msgid "Attempt to do relocatable link with %s input and %s output"
 msgstr "Se intentó hacer un enlace reubicable con entrada %s y salida %s"
 
-#: linker.c:3047
+#: linker.c:3065
 msgid "%B: warning: ignoring duplicate section `%A'\n"
 msgstr "%B: aviso: se descarta la sección duplicada `%A'\n"
 
-#: linker.c:3061
+#: linker.c:3079
 msgid "%B: warning: duplicate section `%A' has different size\n"
 msgstr "%B: aviso: la sección duplicada `%A' es de tamaño diferente\n"
 
-#: merge.c:828
+#: mach-o.c:3195
+#, c-format
+msgid "Mach-O header:\n"
+msgstr "encabezado de Mach-O:\n"
+
+#: mach-o.c:3196
+#, c-format
+msgid " magic     : %08lx\n"
+msgstr " magic     : %08lx\n"
+
+#: mach-o.c:3197
+#, c-format
+msgid " cputype   : %08lx (%s)\n"
+msgstr " tipocpu   : %08lx (%s)\n"
+
+#: mach-o.c:3199
+#, c-format
+msgid " cpusubtype: %08lx\n"
+msgstr " subtipocpu: %08lx\n"
+
+#: mach-o.c:3200
+#, c-format
+msgid " filetype  : %08lx (%s)\n"
+msgstr " tipofich  : %08lx (%s)\n"
+
+#: mach-o.c:3203
+#, c-format
+msgid " ncmds     : %08lx\n"
+msgstr " nordenes  : %08lx\n"
+
+#: mach-o.c:3204
+#, c-format
+msgid " sizeofcmds: %08lx\n"
+msgstr " tamordenes: %08lx\n"
+
+#: mach-o.c:3205
+#, c-format
+msgid " flags     : %08lx ("
+msgstr " opciones  : %08lx ("
+
+#: mach-o.c:3207
+#, c-format
+msgid ")\n"
+msgstr ")\n"
+
+#: mach-o.c:3208
+#, c-format
+msgid " reserved  : %08x\n"
+msgstr " reservado : %08x\n"
+
+#: mach-o.c:3218
+#, c-format
+msgid "Segments and Sections:\n"
+msgstr "Segmentos y Secciones:\n"
+
+#: mach-o.c:3219
+#, c-format
+msgid " #: Segment name     Section name     Address\n"
+msgstr " #: Nombre segmento  Nombre sección   Dirección\n"
+
+#: merge.c:829
 #, c-format
 msgid "%s: access beyond end of merged section (%ld)"
 msgstr "%s: acceso más allá del final de la sección mezclada (%ld)"
@@ -2923,7 +3146,7 @@ msgstr "%s: fichero mmo inv
 #: mmo.c:1729
 #, c-format
 msgid "%s: invalid mmo file: leading byte of operand word must be 0 or 1, got %d for lop_fixrx\n"
-msgstr "%s: fichero mmo inválido: el byte inicial de la palabra operando debe ser 0 ó 1, se obtuvo %d para lop_fixrx\n"
+msgstr "%s: fichero mmo inválido: el byte inicial del operando word debe ser 0 ó 1, se obtuvo %d para lop_fixrx\n"
 
 #: mmo.c:1752
 #, c-format
@@ -2963,7 +3186,7 @@ msgstr "%s: tabla de s
 #: mmo.c:2894
 #, c-format
 msgid "%s: Bad symbol definition: `Main' set to %s rather than the start address %s\n"
-msgstr "%s: Definición de símbolo errónea: `Main' se estableción como %s en lugar de la dirección de inicio %s\n"
+msgstr "%s: Definición de símbolo errónea: `Main' se estableció como %s en lugar de la dirección de inicio %s\n"
 
 #: mmo.c:2986
 #, c-format
@@ -2993,7 +3216,7 @@ msgstr "%s: demasiados registros iniciados: longitud de secci
 #: mmo.c:3145
 #, c-format
 msgid "%s: invalid start address for initialized registers of length %ld: 0x%lx%08lx\n"
-msgstr "%s: dirección de inicio inválida para los registros iniciados de longitud %ld: 0x%lx%08lx\n"
+msgstr "%s: dirección de inicio inválida para los registros inicializados de longitud %ld: 0x%lx%08lx\n"
 
 #: oasys.c:881
 #, c-format
@@ -3005,7 +3228,7 @@ msgstr "%s: no se puede representar la secci
 msgid "Unhandled OSF/1 core file section type %d\n"
 msgstr "Tipo de sección de fichero núcleo OSF/1 %d sin manejar\n"
 
-#: pe-mips.c:607
+#: pe-mips.c:613
 msgid "%B: `ld -r' not supported with PE MIPS objects\n"
 msgstr "%B: `ld -r' no se admite con objetos PE MIPS\n"
 
@@ -3013,46 +3236,66 @@ msgstr "%B: `ld -r' no se admite con objetos PE MIPS\n"
 #. src = VMA of the memory we're fixing up
 #. mem = pointer to memory we're fixing up
 #. val = VMA of what we need to refer to.
-#: pe-mips.c:723
+#: pe-mips.c:729
 msgid "%B: unimplemented %s\n"
 msgstr "%B: %s sin implementar\n"
 
-#: pe-mips.c:749
+#: pe-mips.c:755
 msgid "%B: jump too far away\n"
 msgstr "%B: salto demasiado lejos\n"
 
-#: pe-mips.c:775
+#: pe-mips.c:781
 msgid "%B: bad pair/reflo after refhi\n"
 msgstr "%B: pair/reflo erróneo después de refhi\n"
 
+#: pei-x86_64.c:465
+#, c-format
+msgid "warning: .pdata section size (%ld) is not a multiple of %d\n"
+msgstr "aviso: el tamaño de la sección .pdata (%ld) no es un múltiplo de %d\n"
+
+#: pei-x86_64.c:469 peigen.c:1620 peigen.c:1799 pepigen.c:1620 pepigen.c:1799
+#: pex64igen.c:1620 pex64igen.c:1799
+#, c-format
+msgid ""
+"\n"
+"The Function Table (interpreted .pdata section contents)\n"
+msgstr ""
+"\n"
+"La Tabla de Funciones (se interpretaron los contenidos de la sección .pdata)\n"
+
+#: pei-x86_64.c:471
+#, c-format
+msgid "vma:\t\t\tBeginAddress\t EndAddress\t  UnwindData\n"
+msgstr "vma:\t\t\tDireccInicio\t DireccFin \t  InformaciónDesenvuelta\n"
+
 #. XXX code yet to be written.
-#: peicode.h:759
+#: peicode.h:752
 msgid "%B: Unhandled import type; %x"
 msgstr "%B: Tipo de importación sin manejar; %x"
 
-#: peicode.h:764
+#: peicode.h:757
 msgid "%B: Unrecognised import type; %x"
-msgstr "%B: Tipo de importación no reconocida; %x"
+msgstr "%B: No se reconocer el tipo de importación; %x"
 
-#: peicode.h:778
+#: peicode.h:771
 msgid "%B: Unrecognised import name type; %x"
-msgstr "%B: Tipo de nombre de importación no reconocida; %x"
+msgstr "%B: No se reconoce el tipo de nombre de importación; %x"
 
-#: peicode.h:1161
+#: peicode.h:1154
 msgid "%B: Unrecognised machine type (0x%x) in Import Library Format archive"
-msgstr "%B: Tipo de máquina (0x%x) no reconocida en el archivo de Formato de Importación de Bibliotecas"
+msgstr "%B: No se reconoce el tipo de máquina (0x%x) en el archivo de Formato de Importación de Bibliotecas"
 
-#: peicode.h:1173
+#: peicode.h:1166
 msgid "%B: Recognised but unhandled machine type (0x%x) in Import Library Format archive"
-msgstr "%B: Tipo de máquina (0x%x) reconocida pero sin manejar en el archivo de Formato de Importación de Bibliotecas"
+msgstr "%B: Se reconoce el tipo de máquina (0x%x) pero no se maneja en el archivo de Formato de Importación de Bibliotecas"
 
-#: peicode.h:1191
+#: peicode.h:1184
 msgid "%B: size field is zero in Import Library Format header"
 msgstr "%B: el tamaño del campo es cero en el encabezado del Formato de Importación de Bibliotecas"
 
-#: peicode.h:1222
+#: peicode.h:1215
 msgid "%B: string not null terminated in ILF object file."
-msgstr "%B: cadena no terminada en null en el fichero objeto ILF."
+msgstr "%B: cadena que no termina en null en el fichero objeto ILF."
 
 #: ppcboot.c:414
 #, c-format
@@ -3107,7 +3350,7 @@ msgstr "Partici
 msgid "Partition[%d] length = 0x%.8lx (%ld)\n"
 msgstr "Partición[%d] longitud = 0x%.8lx (%ld)\n"
 
-#: som.c:5137
+#: som.c:5114
 #, c-format
 msgid ""
 "\n"
@@ -3116,13 +3359,13 @@ msgstr ""
 "\n"
 "Encabezado Auxiliar de Ejecución\n"
 
-#: som.c:5440
+#: som.c:5417
 msgid "som_sizeof_headers unimplemented"
 msgstr "som_sizeof_headers sin implementar"
 
 #: srec.c:261
 msgid "%B:%d: Unexpected character `%s' in S-record file\n"
-msgstr "%B:%d: Caractér `%s' inesperado en el fichero S-record\n"
+msgstr "%B:%d: Carácter `%s' inesperado en el fichero S-record\n"
 
 #: srec.c:567 srec.c:600
 msgid "%B:%d: Bad checksum in S-record file\n"
@@ -3132,122 +3375,173 @@ msgstr "%B:%d: Suma de comprobaci
 msgid "%B(%A+0x%lx): Stabs entry has invalid string index."
 msgstr "%B(%A+0x%lx): La entrada de cabos tiene una cadena índice inválida."
 
-#: syms.c:1067
+#: syms.c:1079
 msgid "Unsupported .stab relocation"
 msgstr "No se admite la reubicación .stab"
 
-#: vms-gsd.c:338
+#: vms-gsd.c:350
 #, c-format
 msgid "bfd_make_section (%s) failed"
 msgstr "bfd_make_section (%s) falló"
 
-#: vms-gsd.c:353
+#: vms-gsd.c:365
 #, c-format
 msgid "bfd_set_section_flags (%s, %x) failed"
 msgstr "bfd_set_section_flags (%s, %x) falló"
 
-#: vms-gsd.c:388
+#: vms-gsd.c:399
 #, c-format
 msgid "Size mismatch section %s=%lx, %s=%lx"
 msgstr "No coincide el tamaño de la sección %s=%lx, %s=%lx"
 
-#: vms-gsd.c:679
+#: vms-gsd.c:754
 #, c-format
-msgid "unknown gsd/egsd subtype %d"
-msgstr "subtipo de gsd/egsd %d desconocido"
+msgid "Unknown GSD/EGSD subtype %d"
+msgstr "Subtipo de GSD/EGSD %d desconocido"
 
-#: vms-hdr.c:328
+#: vms-hdr.c:364
 msgid "Object module NOT error-free !\n"
 msgstr "¡ El módulo objeto NO está libre de errores !\n"
 
-#: vms-misc.c:474
+#: vms-hdr.c:878
+#, c-format
+msgid "unknown source command %d"
+msgstr "orden fuente %d desconocida"
+
+#: vms-hdr.c:951
+msgid "DST_S_C_SET_LINUM_INCR not implemented"
+msgstr "DST_S_C_SET_LINUM_INCR sin implementar"
+
+#: vms-hdr.c:957
+msgid "DST_S_C_SET_LINUM_INCR_W not implemented"
+msgstr "DST_S_C_SET_LINUM_INCR_W sin implementar"
+
+#: vms-hdr.c:963
+msgid "DST_S_C_RESET_LINUM_INCR not implemented"
+msgstr "DST_S_C_RESET_LINUM_INCR sin implementar"
+
+#: vms-hdr.c:969
+msgid "DST_S_C_BEG_STMT_MODE not implemented"
+msgstr "DST_S_C_BEG_STMT_MODE sin implementar"
+
+#: vms-hdr.c:975
+msgid "DST_S_C_END_STMT_MODE not implemented"
+msgstr "DST_S_C_END_STMT_MODE sin implementar"
+
+#: vms-hdr.c:1008
+msgid "DST_S_C_SET_PC not implemented"
+msgstr "DST_S_C_SET_PC sin implementar"
+
+#: vms-hdr.c:1014
+msgid "DST_S_C_SET_PC_W not implemented"
+msgstr "DST_S_C_SET_PC_W sin implementar"
+
+#: vms-hdr.c:1020
+msgid "DST_S_C_SET_PC_L not implemented"
+msgstr "DST_S_C_SET_PC_L sin implementar"
+
+#: vms-hdr.c:1026
+msgid "DST_S_C_SET_STMTNUM not implemented"
+msgstr "DST_S_C_SET_STMTNUM sin implementar"
+
+#: vms-hdr.c:1079
+#, c-format
+msgid "unknown line command %d"
+msgstr "orden de línea %d desconocida"
+
+#: vms-misc.c:588
 #, c-format
 msgid "Stack overflow (%d) in _bfd_vms_push"
 msgstr "Desbordamiento de la pila (%d) en _bfd_vms_push"
 
-#: vms-misc.c:489
+#: vms-misc.c:603
 msgid "Stack underflow in _bfd_vms_pop"
 msgstr "Desbordamiento por debajo de la pila en _bfd_vms_pop"
 
-#: vms-misc.c:808
+#: vms-misc.c:844
 msgid "_bfd_vms_output_counted called with zero bytes"
 msgstr "se llamó _bfd_vms_output_counted con cero bytes"
 
-#: vms-misc.c:813
+#: vms-misc.c:849
 msgid "_bfd_vms_output_counted called with too many bytes"
 msgstr "se llamó _bfd_vms_output_counted con demasiados bytes"
 
-#: vms-misc.c:931
+#: vms-misc.c:967
 #, c-format
 msgid "Symbol %s replaced by %s\n"
-msgstr "El símbolo %s fue reemplazado por %s\n"
+msgstr "Se reemplazó el símbolo %s por %s\n"
 
-#: vms-misc.c:990
+#: vms-misc.c:1026
 #, c-format
 msgid "failed to enter %s"
 msgstr "falló la introducción de %s"
 
-#: vms-tir.c:57
+#: vms-tir.c:83
 msgid "No Mem !"
 msgstr "¡ No hay Memoria !"
 
-#: vms-tir.c:300
+#. These names have not yet been added to this switch statement.
+#: vms-tir.c:346
+#, c-format
+msgid "unknown ETIR command %d"
+msgstr "orden ETIR %d desconocida"
+
+#: vms-tir.c:440
 #, c-format
 msgid "bad section index in %s"
-msgstr "Índice de sección erróneo en %s"
+msgstr "índice de sección erróneo en %s"
 
-#: vms-tir.c:313
+#: vms-tir.c:459
 #, c-format
 msgid "unsupported STA cmd %s"
 msgstr "no se admite la orden STA %s"
 
-#: vms-tir.c:318 vms-tir.c:1120
+#: vms-tir.c:464 vms-tir.c:1304
 #, c-format
 msgid "reserved STA cmd %d"
 msgstr "orden STA %d reservada"
 
-#: vms-tir.c:410 vms-tir.c:432
-#, c-format
-msgid "%s: no symbol \"%s\""
-msgstr "%s: no existe el símbolo \"%s\""
-
 #. Unsigned shift.
 #. Rotate.
 #. Redefine symbol to current location.
 #. Define a literal.
-#: vms-tir.c:497 vms-tir.c:606 vms-tir.c:704 vms-tir.c:721 vms-tir.c:728
-#: vms-tir.c:736 vms-tir.c:1440
+#: vms-tir.c:655 vms-tir.c:774 vms-tir.c:894 vms-tir.c:1624
 #, c-format
 msgid "%s: not supported"
 msgstr "%s: no se admite"
 
-#: vms-tir.c:502 vms-tir.c:1297
+#: vms-tir.c:661 vms-tir.c:1481
 #, c-format
 msgid "%s: not implemented"
 msgstr "%s: sin implementar"
 
-#: vms-tir.c:506 vms-tir.c:1301
+#: vms-tir.c:666 vms-tir.c:1485
 #, c-format
 msgid "reserved STO cmd %d"
 msgstr "orden STO %d reservada"
 
-#: vms-tir.c:621 vms-tir.c:1445
+#: vms-tir.c:789 vms-tir.c:1629
 #, c-format
 msgid "reserved OPR cmd %d"
 msgstr "orden OPR %d reservada"
 
-#: vms-tir.c:681 vms-tir.c:1509
+#: vms-tir.c:852 vms-tir.c:1693
 #, c-format
 msgid "reserved CTL cmd %d"
 msgstr "orden CTL %d reservada"
 
+#: vms-tir.c:966
+#, c-format
+msgid "reserved STC cmd %d"
+msgstr "orden STC %d reservada"
+
 #. stack byte from image
 #. arg: none.
-#: vms-tir.c:1028
+#: vms-tir.c:1212
 msgid "stack-from-image not implemented"
 msgstr "pila-desde-imagen sin implementar"
 
-#: vms-tir.c:1046
+#: vms-tir.c:1230
 msgid "stack-entry-mask not fully implemented"
 msgstr "pila-máscara-entrada no está completamente implementado"
 
@@ -3258,279 +3552,294 @@ msgstr "pila-m
 #.
 #. compare argument descriptor with symbol argument (ARG$V_PASSMECH)
 #. and stack TRUE (args match) or FALSE (args dont match) value.
-#: vms-tir.c:1060
+#: vms-tir.c:1244
 msgid "PASSMECH not fully implemented"
 msgstr "PASSMECH no está completamente implementado"
 
-#: vms-tir.c:1079
+#: vms-tir.c:1263
 msgid "stack-local-symbol not fully implemented"
 msgstr "pila-símbolo-local no está completamente implementado"
 
-#: vms-tir.c:1092
+#: vms-tir.c:1276
 msgid "stack-literal not fully implemented"
 msgstr "pila-literal no está completamente implementado"
 
-#: vms-tir.c:1113
+#: vms-tir.c:1297
 msgid "stack-local-symbol-entry-point-mask not fully implemented"
 msgstr "pila-símbolo-local-máscara-punto-entrada no está completamente implementado"
 
-#: vms-tir.c:1387 vms-tir.c:1399 vms-tir.c:1411 vms-tir.c:1423 vms-tir.c:1488
-#: vms-tir.c:1496 vms-tir.c:1504
+#: vms-tir.c:1571 vms-tir.c:1583 vms-tir.c:1595 vms-tir.c:1607 vms-tir.c:1672
+#: vms-tir.c:1680 vms-tir.c:1688
 #, c-format
 msgid "%s: not fully implemented"
 msgstr "%s: no está completamente implementado"
 
-#: vms-tir.c:1562
+#: vms-tir.c:1746
 #, c-format
 msgid "obj code %d not found"
 msgstr "no se encontró el código objeto %d"
 
-#: vms-tir.c:1870
+#: vms-tir.c:2019
+#, c-format
+msgid "Reloc size error in section %s"
+msgstr "Error del tamaño de reubicación en la sección %s"
+
+#: vms-tir.c:2112 vms-tir.c:2129 vms-tir.c:2147 vms-tir.c:2159 vms-tir.c:2170
+#: vms-tir.c:2182
+#, c-format
+msgid "Unknown reloc %s + %s"
+msgstr "Reubicación %s + %s desconocida"
+
+#: vms-tir.c:2249
+#, c-format
+msgid "Unknown symbol %s in command %s"
+msgstr "Símbolo %s desconocido en la orden %s"
+
+#: vms-tir.c:2504
 #, c-format
 msgid "SEC_RELOC with no relocs in section %s"
 msgstr "SEC_RELOC sin reubicaciones en la sección %s"
 
-#: vms-tir.c:2152
+#: vms-tir.c:2556 vms-tir.c:2783
+#, c-format
+msgid "Size error in section %s"
+msgstr "Error de tamaño en la sección %s"
+
+#: vms-tir.c:2725
+msgid "Spurious ALPHA_R_BSR reloc"
+msgstr "Reubicación ALPHA_R_BSR espuria"
+
+#: vms-tir.c:2770
 #, c-format
 msgid "Unhandled relocation %s"
 msgstr "Reubicación %s sin manejar"
 
-#: xcofflink.c:566
+#: xcofflink.c:836
 #, c-format
 msgid "%s: XCOFF shared object when not producing XCOFF output"
 msgstr "%s: objeto compartido XCOFF cuando no se produce salida XCOFF"
 
-#: xcofflink.c:587
+#: xcofflink.c:857
 #, c-format
 msgid "%s: dynamic object with no .loader section"
 msgstr "%s: objeto dinámico sin sección .loader"
 
-#: xcofflink.c:1150
+#: xcofflink.c:1415
 msgid "%B: `%s' has line numbers but no enclosing section"
 msgstr "%B: `%s' tiene números de línea pero no una sección contenedora"
 
-#: xcofflink.c:1202
+#: xcofflink.c:1467
 msgid "%B: class %d symbol `%s' has no aux entries"
 msgstr "%B: clase %d símbolo `%s' no tiene entradas auxiliares"
 
-#: xcofflink.c:1225
+#: xcofflink.c:1489
 msgid "%B: symbol `%s' has unrecognized csect type %d"
 msgstr "%B: el símbolo `%s' tiene un tipo csect %d que no se reconoce"
 
-#: xcofflink.c:1237
+#: xcofflink.c:1501
 msgid "%B: bad XTY_ER symbol `%s': class %d scnum %d scnlen %d"
 msgstr "%B: símbolo XTY_ER `%s' erróneo: clase %d scnum %d scnlen %d"
 
-#: xcofflink.c:1273
+#: xcofflink.c:1530
 msgid "%B: XMC_TC0 symbol `%s' is class %d scnlen %d"
 msgstr "%B: símbolo XMC_TCO `%s' es clase %d scnlen %d"
 
-#: xcofflink.c:1419
+#: xcofflink.c:1676
 msgid "%B: csect `%s' not in enclosing section"
 msgstr "%B: csect `%s' no está contenido en una sección"
 
-#: xcofflink.c:1526
+#: xcofflink.c:1783
 msgid "%B: misplaced XTY_LD `%s'"
 msgstr "%B: XTY_LD `%s' mal ubicado"
 
-#: xcofflink.c:1842
+#: xcofflink.c:2102
 msgid "%B: reloc %s:%d not in csect"
 msgstr "%B: la reubicación %s:%d no está en csect"
 
-#: xcofflink.c:2640
+#: xcofflink.c:3177
 #, c-format
 msgid "%s: no such symbol"
 msgstr "%s: no hay tal símbolo"
 
-#: xcofflink.c:2869
+#: xcofflink.c:3282
 #, c-format
 msgid "warning: attempt to export undefined symbol `%s'"
-msgstr "aviso: intento de exportar el símbolo sin definir `%s'"
+msgstr "aviso: se intenta exportar el símbolo sin definir `%s'"
 
-#: xcofflink.c:3036
+#: xcofflink.c:3664
 msgid "error: undefined symbol __rtinit"
-msgstr "error: símbolo __rtinit indefinido"
-
-#: xcofflink.c:3656
-#, c-format
-msgid "TOC overflow: 0x%lx > 0x10000; try -mminimal-toc when compiling"
-msgstr "Desbordamiento de TOC: 0x%lx > 0x10000; pruebe -mminimal-toc al compilar"
+msgstr "error: símbolo __rtinit sin definir"
 
-#: xcofflink.c:4492
-msgid "%B: loader reloc in unrecognized section `%A'"
-msgstr "%B: reubicación del cargador en la sección `%A' no reconocida"
+#: xcofflink.c:4041
+msgid "%B: loader reloc in unrecognized section `%s'"
+msgstr "%B: reubicación del cargador en la sección `%s' que no se reconoce"
 
-#: xcofflink.c:4513
+#: xcofflink.c:4052
 msgid "%B: `%s' in loader reloc but not loader sym"
 msgstr "%B: `%s' en la reubicación del cargador pero no es un símbolo del cargador"
 
-#: xcofflink.c:4528
+#: xcofflink.c:4068
 msgid "%B: loader reloc in read-only section %A"
 msgstr "%B: reubicación del cargador en la sección de sólo lectura %A"
 
-#: xcofflink.c:4937 xcofflink.c:4999 xcofflink.c:5294
-#, c-format
-msgid "%s: loader reloc in unrecognized section `%s'"
-msgstr "%s: reubicación del cargador en la sección `%s' no reconocida"
-
-#: xcofflink.c:5305
+#: xcofflink.c:5086
 #, c-format
-msgid "%s: `%s' in loader reloc but not loader sym"
-msgstr "%s: `%s' en la reubicación del cargador pero no es un símbolo del cargador"
+msgid "TOC overflow: 0x%lx > 0x10000; try -mminimal-toc when compiling"
+msgstr "Desbordamiento de TOC: 0x%lx > 0x10000; pruebe -mminimal-toc al compilar"
 
-#: elf32-ia64.c:1037 elf64-ia64.c:1037
+#: elf32-ia64.c:1050 elf64-ia64.c:1050
 msgid "%B: Can't relax br at 0x%lx in section `%A'. Please use brl or indirect branch."
 msgstr "%B: No se puede relajar br en 0x%lx en la sección `%A'. Por favor use brl o ramificación indirecta."
 
-#: elf32-ia64.c:2742 elf64-ia64.c:2742
+#: elf32-ia64.c:2739 elf64-ia64.c:2739
 msgid "@pltoff reloc against local symbol"
 msgstr "reubicación @pltoff contra un símbolo local"
 
-#: elf32-ia64.c:4317 elf64-ia64.c:4317
+#: elf32-ia64.c:4314 elf64-ia64.c:4314
 #, c-format
 msgid "%s: short data segment overflowed (0x%lx >= 0x400000)"
 msgstr "%s: segmento de datos short desbordado (0x%lx >= 0x400000)"
 
-#: elf32-ia64.c:4328 elf64-ia64.c:4328
+#: elf32-ia64.c:4325 elf64-ia64.c:4325
 #, c-format
 msgid "%s: __gp does not cover short data segment"
 msgstr "%s: __gp no cubre el segmento de datos short"
 
-#: elf32-ia64.c:4598 elf64-ia64.c:4598
+#: elf32-ia64.c:4595 elf64-ia64.c:4595
 msgid "%B: non-pic code with imm relocation against dynamic symbol `%s'"
 msgstr "%B: código que no es pic con reubicación imm contra el símbolo dinámico %s"
 
-#: elf32-ia64.c:4665 elf64-ia64.c:4665
+#: elf32-ia64.c:4662 elf64-ia64.c:4662
 msgid "%B: @gprel relocation against dynamic symbol %s"
 msgstr "%B: reubicación @gprel contra el símbolo dinámico %s"
 
-#: elf32-ia64.c:4728 elf64-ia64.c:4728
+#: elf32-ia64.c:4725 elf64-ia64.c:4725
 msgid "%B: linking non-pic code in a position independent executable"
 msgstr "%B: se enlaza código que no es pic en un ejecutable independiente de posición"
 
-#: elf32-ia64.c:4865 elf64-ia64.c:4865
+#: elf32-ia64.c:4862 elf64-ia64.c:4862
 msgid "%B: @internal branch to dynamic symbol %s"
 msgstr "%B: ramificación @internal al símbolo dinámico %s"
 
-#: elf32-ia64.c:4867 elf64-ia64.c:4867
+#: elf32-ia64.c:4864 elf64-ia64.c:4864
 msgid "%B: speculation fixup to dynamic symbol %s"
 msgstr "%B: compostura de especulación al símbolo dinámico %s"
 
-#: elf32-ia64.c:4869 elf64-ia64.c:4869
+#: elf32-ia64.c:4866 elf64-ia64.c:4866
 msgid "%B: @pcrel relocation against dynamic symbol %s"
 msgstr "%B: reubicación @pcrel contra el símbolo dinámico %s"
 
-#: elf32-ia64.c:5066 elf64-ia64.c:5066
+#: elf32-ia64.c:5063 elf64-ia64.c:5063
 msgid "unsupported reloc"
 msgstr "no se admite la reubicación"
 
-#: elf32-ia64.c:5104 elf64-ia64.c:5104
+#: elf32-ia64.c:5101 elf64-ia64.c:5101
 msgid "%B: missing TLS section for relocation %s against `%s' at 0x%lx in section `%A'."
 msgstr "%B: falta la sección TLS para la reubicación %s contra `%s' en 0x%lx en la sección `%A'."
 
-#: elf32-ia64.c:5119 elf64-ia64.c:5119
+#: elf32-ia64.c:5116 elf64-ia64.c:5116
 msgid "%B: Can't relax br (%s) to `%s' at 0x%lx in section `%A' with size 0x%lx (> 0x1000000)."
 msgstr "%B: No se puede relajar br (%s) a `%s' en 0x%lx en la sección `%A' con tamaño 0x%lx (> 0x1000000)."
 
-#: elf32-ia64.c:5375 elf64-ia64.c:5375
+#: elf32-ia64.c:5372 elf64-ia64.c:5372
 msgid "%B: linking trap-on-NULL-dereference with non-trapping files"
 msgstr "%B: se enlaza deferencias-captura-en-NULL con ficheros que no son de captura"
 
-#: elf32-ia64.c:5384 elf64-ia64.c:5384
+#: elf32-ia64.c:5381 elf64-ia64.c:5381
 msgid "%B: linking big-endian files with little-endian files"
 msgstr "%B: se enlazan ficheros big-endian con ficheros little-endian"
 
-#: elf32-ia64.c:5393 elf64-ia64.c:5393
+#: elf32-ia64.c:5390 elf64-ia64.c:5390
 msgid "%B: linking 64-bit files with 32-bit files"
 msgstr "%B: se enlazan ficheros de 64-bit con ficheros de 32-bit"
 
-#: elf32-ia64.c:5402 elf64-ia64.c:5402
+#: elf32-ia64.c:5399 elf64-ia64.c:5399
 msgid "%B: linking constant-gp files with non-constant-gp files"
 msgstr "%B: se enlazan ficheros de gp constante con ficheros con gp no constante"
 
-#: elf32-ia64.c:5412 elf64-ia64.c:5412
+#: elf32-ia64.c:5409 elf64-ia64.c:5409
 msgid "%B: linking auto-pic files with non-auto-pic files"
 msgstr "%B: se enlazan ficheros de pic automático con ficheros sin pic automático"
 
-#: peigen.c:1000 pepigen.c:1000 pex64igen.c:1000
+#: peigen.c:999 pepigen.c:999 pex64igen.c:999
 #, c-format
 msgid "%s: line number overflow: 0x%lx > 0xffff"
 msgstr "%s: desbordamiento de número de línea: 0x%lx > 0xffff"
 
-#: peigen.c:1027 pepigen.c:1027 pex64igen.c:1027
+#: peigen.c:1026 pepigen.c:1026 pex64igen.c:1026
 msgid "Export Directory [.edata (or where ever we found it)]"
 msgstr "Directorio de Exportación [.edata (o donde quiera que se encuentre)]"
 
-#: peigen.c:1028 pepigen.c:1028 pex64igen.c:1028
+#: peigen.c:1027 pepigen.c:1027 pex64igen.c:1027
 msgid "Import Directory [parts of .idata]"
 msgstr "Directorio de Importación [partes de .idata]"
 
-#: peigen.c:1029 pepigen.c:1029 pex64igen.c:1029
+#: peigen.c:1028 pepigen.c:1028 pex64igen.c:1028
 msgid "Resource Directory [.rsrc]"
 msgstr "Directorio de Recursos [.rsrc]"
 
-#: peigen.c:1030 pepigen.c:1030 pex64igen.c:1030
+#: peigen.c:1029 pepigen.c:1029 pex64igen.c:1029
 msgid "Exception Directory [.pdata]"
 msgstr "Directorio de Excepciones [.pdata]"
 
-#: peigen.c:1031 pepigen.c:1031 pex64igen.c:1031
+#: peigen.c:1030 pepigen.c:1030 pex64igen.c:1030
 msgid "Security Directory"
 msgstr "Directorio de Seguridad"
 
-#: peigen.c:1032 pepigen.c:1032 pex64igen.c:1032
+#: peigen.c:1031 pepigen.c:1031 pex64igen.c:1031
 msgid "Base Relocation Directory [.reloc]"
 msgstr "Directorio de Reubicación Base [.reloc]"
 
-#: peigen.c:1033 pepigen.c:1033 pex64igen.c:1033
+#: peigen.c:1032 pepigen.c:1032 pex64igen.c:1032
 msgid "Debug Directory"
 msgstr "Directorio de Depuración"
 
-#: peigen.c:1034 pepigen.c:1034 pex64igen.c:1034
+#: peigen.c:1033 pepigen.c:1033 pex64igen.c:1033
 msgid "Description Directory"
 msgstr "Directorio de Descripciones"
 
-#: peigen.c:1035 pepigen.c:1035 pex64igen.c:1035
+#: peigen.c:1034 pepigen.c:1034 pex64igen.c:1034
 msgid "Special Directory"
 msgstr "Directorio Especial"
 
-#: peigen.c:1036 pepigen.c:1036 pex64igen.c:1036
+#: peigen.c:1035 pepigen.c:1035 pex64igen.c:1035
 msgid "Thread Storage Directory [.tls]"
 msgstr "Directorio de Almacenamiento de Hilos [.tls]"
 
-#: peigen.c:1037 pepigen.c:1037 pex64igen.c:1037
+#: peigen.c:1036 pepigen.c:1036 pex64igen.c:1036
 msgid "Load Configuration Directory"
 msgstr "Directorio de Carga de Configuraciones"
 
-#: peigen.c:1038 pepigen.c:1038 pex64igen.c:1038
+#: peigen.c:1037 pepigen.c:1037 pex64igen.c:1037
 msgid "Bound Import Directory"
 msgstr "Directorio de Importación de Relaciones"
 
-#: peigen.c:1039 pepigen.c:1039 pex64igen.c:1039
+#: peigen.c:1038 pepigen.c:1038 pex64igen.c:1038
 msgid "Import Address Table Directory"
-msgstr "Directorio de Importación de Tablas de Direcciones"
+msgstr "Directorio de Tablas de Direcciones de Importación"
 
-#: peigen.c:1040 pepigen.c:1040 pex64igen.c:1040
+#: peigen.c:1039 pepigen.c:1039 pex64igen.c:1039
 msgid "Delay Import Directory"
 msgstr "Directorio de Retardo de Importación"
 
-#: peigen.c:1041 pepigen.c:1041 pex64igen.c:1041
+#: peigen.c:1040 pepigen.c:1040 pex64igen.c:1040
 msgid "CLR Runtime Header"
 msgstr "Encabezado de Tiempo de Ejecución CLR"
 
-#: peigen.c:1042 pepigen.c:1042 pex64igen.c:1042
+#: peigen.c:1041 pepigen.c:1041 pex64igen.c:1041
 msgid "Reserved"
 msgstr "Reservado"
 
-#: peigen.c:1102 pepigen.c:1102 pex64igen.c:1102
+#: peigen.c:1101 pepigen.c:1101 pex64igen.c:1101
 #, c-format
 msgid ""
 "\n"
 "There is an import table, but the section containing it could not be found\n"
 msgstr ""
 "\n"
-"Hay una tabla de importación, pero la sección que la contiene no se puede encontrar\n"
+"Hay una tabla de importación, pero no se puede encontrar la sección que la contiene\n"
 
-#: peigen.c:1107 pepigen.c:1107 pex64igen.c:1107
+#: peigen.c:1106 pepigen.c:1106 pex64igen.c:1106
 #, c-format
 msgid ""
 "\n"
@@ -3539,7 +3848,7 @@ msgstr ""
 "\n"
 "Hay una tabla de importación en %s en 0x%lx\n"
 
-#: peigen.c:1150 pepigen.c:1150 pex64igen.c:1150
+#: peigen.c:1149 pepigen.c:1149 pex64igen.c:1149
 #, c-format
 msgid ""
 "\n"
@@ -3548,12 +3857,12 @@ msgstr ""
 "\n"
 "Se localizó el descriptor de función en la dirección de inicio: %04lx\n"
 
-#: peigen.c:1153 pepigen.c:1153 pex64igen.c:1153
+#: peigen.c:1152 pepigen.c:1152 pex64igen.c:1152
 #, c-format
 msgid "\tcode-base %08lx toc (loadable/actual) %08lx/%08lx\n"
 msgstr "\tcódigo-base %08lx tabla-de-contenidos (cargable/actual) %08lx/%08lx\n"
 
-#: peigen.c:1161 pepigen.c:1161 pex64igen.c:1161
+#: peigen.c:1160 pepigen.c:1160 pex64igen.c:1160
 #, c-format
 msgid ""
 "\n"
@@ -3562,7 +3871,7 @@ msgstr ""
 "\n"
 "¡No está la sección reldata! No se decodificó el descriptor de función.\n"
 
-#: peigen.c:1166 pepigen.c:1166 pex64igen.c:1166
+#: peigen.c:1165 pepigen.c:1165 pex64igen.c:1165
 #, c-format
 msgid ""
 "\n"
@@ -3571,7 +3880,7 @@ msgstr ""
 "\n"
 "Las Tablas de Importación (se interpretaron los contenidos de la sección %s)\n"
 
-#: peigen.c:1169 pepigen.c:1169 pex64igen.c:1169
+#: peigen.c:1168 pepigen.c:1168 pex64igen.c:1168
 #, c-format
 msgid ""
 " vma:            Hint    Time      Forward  DLL       First\n"
@@ -3580,7 +3889,7 @@ msgstr ""
 " vma:            Pista   Fecha     Adelante DLL       Primero\n"
 "                 Tabla   Estampa   Cadena   Nombre    Thunk\n"
 
-#: peigen.c:1217 pepigen.c:1217 pex64igen.c:1217
+#: peigen.c:1216 pepigen.c:1216 pex64igen.c:1216
 #, c-format
 msgid ""
 "\n"
@@ -3589,30 +3898,30 @@ msgstr ""
 "\n"
 "\tNombre de la DLL: %s\n"
 
-#: peigen.c:1228 pepigen.c:1228 pex64igen.c:1228
+#: peigen.c:1227 pepigen.c:1227 pex64igen.c:1227
 #, c-format
 msgid "\tvma:  Hint/Ord Member-Name Bound-To\n"
 msgstr "\tvma:  Pista/Ord Nombre-Miembro Unido-A\n"
 
-#: peigen.c:1253 pepigen.c:1253 pex64igen.c:1253
+#: peigen.c:1252 pepigen.c:1252 pex64igen.c:1252
 #, c-format
 msgid ""
 "\n"
 "There is a first thunk, but the section containing it could not be found\n"
 msgstr ""
 "\n"
-"Hay un thunk inicial, pero la sección que lo contiene no se puede encontrar\n"
+"Hay un thunk inicial, pero no se puede encontrar la sección que lo contiene\n"
 
-#: peigen.c:1418 pepigen.c:1418 pex64igen.c:1418
+#: peigen.c:1417 pepigen.c:1417 pex64igen.c:1417
 #, c-format
 msgid ""
 "\n"
 "There is an export table, but the section containing it could not be found\n"
 msgstr ""
 "\n"
-"Hay una tabla de exportación, pero la sección que la contiene no se puede encontrar\n"
+"Hay una tabla de exportación, pero no se puede encontrar la sección que la contiene\n"
 
-#: peigen.c:1427 pepigen.c:1427 pex64igen.c:1427
+#: peigen.c:1426 pepigen.c:1426 pex64igen.c:1426
 #, c-format
 msgid ""
 "\n"
@@ -3621,7 +3930,7 @@ msgstr ""
 "\n"
 "Hay una tabla de exportación en %s, pero no cabe en esa sección\n"
 
-#: peigen.c:1433 pepigen.c:1433 pex64igen.c:1433
+#: peigen.c:1432 pepigen.c:1432 pex64igen.c:1432
 #, c-format
 msgid ""
 "\n"
@@ -3630,7 +3939,7 @@ msgstr ""
 "\n"
 "Hay una tabla de exportación en %s en 0x%lx\n"
 
-#: peigen.c:1461 pepigen.c:1461 pex64igen.c:1461
+#: peigen.c:1460 pepigen.c:1460 pex64igen.c:1460
 #, c-format
 msgid ""
 "\n"
@@ -3641,68 +3950,68 @@ msgstr ""
 "Las Tablas de Exportación (se interpretaron los contenidos de la sección %s)\n"
 "\n"
 
-#: peigen.c:1465 pepigen.c:1465 pex64igen.c:1465
+#: peigen.c:1464 pepigen.c:1464 pex64igen.c:1464
 #, c-format
 msgid "Export Flags \t\t\t%lx\n"
 msgstr "Opciones de Exportación \t\t\t%lx\n"
 
-#: peigen.c:1468 pepigen.c:1468 pex64igen.c:1468
+#: peigen.c:1467 pepigen.c:1467 pex64igen.c:1467
 #, c-format
 msgid "Time/Date stamp \t\t%lx\n"
 msgstr "marca de Hora/Fecha \t\t%lx\n"
 
-#: peigen.c:1471 pepigen.c:1471 pex64igen.c:1471
+#: peigen.c:1470 pepigen.c:1470 pex64igen.c:1470
 #, c-format
 msgid "Major/Minor \t\t\t%d/%d\n"
 msgstr "Mayor/Menor \t\t\t%d/%d\n"
 
-#: peigen.c:1474 pepigen.c:1474 pex64igen.c:1474
+#: peigen.c:1473 pepigen.c:1473 pex64igen.c:1473
 #, c-format
 msgid "Name \t\t\t\t"
 msgstr "Nombre \t\t\t\t"
 
-#: peigen.c:1480 pepigen.c:1480 pex64igen.c:1480
+#: peigen.c:1479 pepigen.c:1479 pex64igen.c:1479
 #, c-format
 msgid "Ordinal Base \t\t\t%ld\n"
 msgstr "Base Ordinal \t\t\t%ld\n"
 
-#: peigen.c:1483 pepigen.c:1483 pex64igen.c:1483
+#: peigen.c:1482 pepigen.c:1482 pex64igen.c:1482
 #, c-format
 msgid "Number in:\n"
 msgstr "Número en:\n"
 
-#: peigen.c:1486 pepigen.c:1486 pex64igen.c:1486
+#: peigen.c:1485 pepigen.c:1485 pex64igen.c:1485
 #, c-format
 msgid "\tExport Address Table \t\t%08lx\n"
 msgstr "\tTabla de Exportación de Direcciones \t\t%08lx\n"
 
-#: peigen.c:1490 pepigen.c:1490 pex64igen.c:1490
+#: peigen.c:1489 pepigen.c:1489 pex64igen.c:1489
 #, c-format
 msgid "\t[Name Pointer/Ordinal] Table\t%08lx\n"
 msgstr "\tTabla [Nombre Puntero/Ordinal]\t%08lx\n"
 
-#: peigen.c:1493 pepigen.c:1493 pex64igen.c:1493
+#: peigen.c:1492 pepigen.c:1492 pex64igen.c:1492
 #, c-format
 msgid "Table Addresses\n"
 msgstr "Direcciones de la Tabla\n"
 
-#: peigen.c:1496 pepigen.c:1496 pex64igen.c:1496
+#: peigen.c:1495 pepigen.c:1495 pex64igen.c:1495
 #, c-format
 msgid "\tExport Address Table \t\t"
 msgstr "\tTabla de Exportación de Direcciones \t\t"
 
-#: peigen.c:1501 pepigen.c:1501 pex64igen.c:1501
+#: peigen.c:1500 pepigen.c:1500 pex64igen.c:1500
 #, c-format
 msgid "\tName Pointer Table \t\t"
 msgstr "\tNombre de la Tabla de Punteros \t\t"
 
 # continuar aqui
-#: peigen.c:1506 pepigen.c:1506 pex64igen.c:1506
+#: peigen.c:1505 pepigen.c:1505 pex64igen.c:1505
 #, c-format
 msgid "\tOrdinal Table \t\t\t"
 msgstr "\tTabla Ordinal \t\t\t"
 
-#: peigen.c:1520 pepigen.c:1520 pex64igen.c:1520
+#: peigen.c:1519 pepigen.c:1519 pex64igen.c:1519
 #, c-format
 msgid ""
 "\n"
@@ -3711,15 +4020,15 @@ msgstr ""
 "\n"
 "Tabla de Exportación de Direcciones -- Base Ordinal %ld\n"
 
-#: peigen.c:1539 pepigen.c:1539 pex64igen.c:1539
+#: peigen.c:1538 pepigen.c:1538 pex64igen.c:1538
 msgid "Forwarder RVA"
 msgstr "RVA Adelantador"
 
-#: peigen.c:1550 pepigen.c:1550 pex64igen.c:1550
+#: peigen.c:1549 pepigen.c:1549 pex64igen.c:1549
 msgid "Export RVA"
 msgstr "RVA Exportador"
 
-#: peigen.c:1557 pepigen.c:1557 pex64igen.c:1557
+#: peigen.c:1556 pepigen.c:1556 pex64igen.c:1556
 #, c-format
 msgid ""
 "\n"
@@ -3728,28 +4037,18 @@ msgstr ""
 "\n"
 "Tabla [Puntero a Ordinal/Nombre]\n"
 
-#: peigen.c:1617 peigen.c:1796 pepigen.c:1617 pepigen.c:1796 pex64igen.c:1617
-#: pex64igen.c:1796
+#: peigen.c:1616 peigen.c:1795 pepigen.c:1616 pepigen.c:1795 pex64igen.c:1616
+#: pex64igen.c:1795
 #, c-format
 msgid "Warning, .pdata section size (%ld) is not a multiple of %d\n"
 msgstr "Aviso, el tamaño de la sección .pdata (%ld) no es un múltiplo de %d\n"
 
-#: peigen.c:1621 peigen.c:1800 pepigen.c:1621 pepigen.c:1800 pex64igen.c:1621
-#: pex64igen.c:1800
-#, c-format
-msgid ""
-"\n"
-"The Function Table (interpreted .pdata section contents)\n"
-msgstr ""
-"\n"
-"La Tabla de Funciones (se interpretaron los contenidos de la sección .pdata)\n"
-
-#: peigen.c:1624 pepigen.c:1624 pex64igen.c:1624
+#: peigen.c:1623 pepigen.c:1623 pex64igen.c:1623
 #, c-format
 msgid " vma:\t\t\tBegin Address    End Address      Unwind Info\n"
 msgstr " vma:\t\t\tDirección Inicio Dirección Fin    Información Desenvuelta\n"
 
-#: peigen.c:1626 pepigen.c:1626 pex64igen.c:1626
+#: peigen.c:1625 pepigen.c:1625 pex64igen.c:1625
 #, c-format
 msgid ""
 " vma:\t\tBegin    End      EH       EH       PrologEnd  Exception\n"
@@ -3758,22 +4057,22 @@ msgstr ""
 " vma:\t\tInicio   Fin      EH       EH       FinPrólogo Excepción\n"
 "     \t\tDirecc   Direcc   Asa      Datos    Dirección  Máscara\n"
 
-#: peigen.c:1696 pepigen.c:1696 pex64igen.c:1696
+#: peigen.c:1695 pepigen.c:1695 pex64igen.c:1695
 #, c-format
 msgid " Register save millicode"
 msgstr " Registro para guardar milicódigo"
 
-#: peigen.c:1699 pepigen.c:1699 pex64igen.c:1699
+#: peigen.c:1698 pepigen.c:1698 pex64igen.c:1698
 #, c-format
 msgid " Register restore millicode"
 msgstr " Registro para restaurar milicódigo"
 
-#: peigen.c:1702 pepigen.c:1702 pex64igen.c:1702
+#: peigen.c:1701 pepigen.c:1701 pex64igen.c:1701
 #, c-format
 msgid " Glue code sequence"
 msgstr " Secuencia de código pegamento"
 
-#: peigen.c:1802 pepigen.c:1802 pex64igen.c:1802
+#: peigen.c:1801 pepigen.c:1801 pex64igen.c:1801
 #, c-format
 msgid ""
 " vma:\t\tBegin    Prolog   Function Flags    Exception EH\n"
@@ -3819,26 +4118,53 @@ msgstr ""
 "\n"
 "Características 0x%x\n"
 
-#: peigen.c:2289 pepigen.c:2289 pex64igen.c:2289
+#: peigen.c:2292 pepigen.c:2292 pex64igen.c:2292
 msgid "%B: unable to fill in DataDictionary[1] because .idata$2 is missing"
 msgstr "%B: no se puede llenar DataDictionary[1] porque falta .idata$2"
 
-#: peigen.c:2307 pepigen.c:2307 pex64igen.c:2307
+#: peigen.c:2312 pepigen.c:2312 pex64igen.c:2312
 msgid "%B: unable to fill in DataDictionary[1] because .idata$4 is missing"
 msgstr "%B: no se puede llenar DataDictionary[1] porque falta .idata$4"
 
-#: peigen.c:2326 pepigen.c:2326 pex64igen.c:2326
+#: peigen.c:2333 pepigen.c:2333 pex64igen.c:2333
 msgid "%B: unable to fill in DataDictionary[12] because .idata$5 is missing"
 msgstr "%B: no se puede llenar DataDictionary[12] porque falta .idata$5"
 
-#: peigen.c:2344 pepigen.c:2344 pex64igen.c:2344
+#: peigen.c:2353 pepigen.c:2353 pex64igen.c:2353
 msgid "%B: unable to fill in DataDictionary[PE_IMPORT_ADDRESS_TABLE (12)] because .idata$6 is missing"
 msgstr "%B: no se puede llenar DataDictionary[PE_IMPORT_ADDRESS_TABLE (12)] porque falta .idata$6"
 
-#: peigen.c:2364 pepigen.c:2364 pex64igen.c:2364
+#: peigen.c:2375 pepigen.c:2375 pex64igen.c:2375
 msgid "%B: unable to fill in DataDictionary[9] because __tls_used is missing"
 msgstr "%B: no se puede llenar DataDictionary[9] porque falta __tls_used"
 
+#~ msgid "ERROR: %B: Incompatible object tag '%s':%d"
+#~ msgstr "ERROR: %B: Etiqueta de objeto '%s' incompatible:%d"
+
+#~ msgid "%B(%A): warning: unresolvable relocation against symbol `%s'"
+#~ msgstr "%B(%A): aviso: reubicación sin resolución contra el símbolo `%s'"
+
+#~ msgid "%B: Internal inconsistency; no relocation section %s"
+#~ msgstr "%B: Inconsistencia interna; no se encuentra la sección de reubicación %s"
+
+#~ msgid "Could not find relocation section for %s"
+#~ msgstr "No se puede encontrar la sección de reubicación para %s"
+
+#~ msgid "%B: GOT overflow: Number of R_68K_GOT8O and R_68K_GOT16O relocations > %d"
+#~ msgstr "%B desbordamiento de GOT: Número de reubicaciones R_68K_GOT80 Y R_68K_GOT160 > %d"
+
+#~ msgid "%A link_order not found\n"
+#~ msgstr "no se encontró link_order %A\n"
+
+#~ msgid "%s: no symbol \"%s\""
+#~ msgstr "%s: no existe el símbolo \"%s\""
+
+#~ msgid "%s: loader reloc in unrecognized section `%s'"
+#~ msgstr "%s: reubicación del cargador en la sección `%s' no reconocida"
+
+#~ msgid "%s: `%s' in loader reloc but not loader sym"
+#~ msgstr "%s: `%s' en la reubicación del cargador pero no es un símbolo del cargador"
+
 #~ msgid "Dwarf Error: DW_FORM_strp offset (%lu) greater than or equal to .debug_str size (%lu)."
 #~ msgstr "Error de Dwarf: El desplazamiento DW_FROM_strp (%lu) es más grande o igual que el tamaño de .debug_str (%lu)."
 
@@ -3959,9 +4285,6 @@ msgstr "%B: no se puede llenar DataDictionary[9] porque falta __tls_used"
 #~ msgid "reloc against unsupported section"
 #~ msgstr "reubicación contra una sección no admitida"
 
-#~ msgid "reloc not properly aligned"
-#~ msgstr "reubicación no alineada adecuadamente"
-
 #~ msgid "Error: First section in segment (%s) starts at 0x%x whereas the segment starts at 0x%x"
 #~ msgstr "Error: La primera sección en el segmento (%s) inicia en 0x%x mientras que el segmento inicia en 0x%x"
 
@@ -4081,12 +4404,6 @@ msgstr "%B: no se puede llenar DataDictionary[9] porque falta __tls_used"
 #~ msgid "ETIR_S_C_STO_LP_PSB: Not supported"
 #~ msgstr "ETIR_S_C_STO_LP_PSB: No se admite"
 
-#~ msgid "ETIR_S_C_STO_HINT_GBL: not implemented"
-#~ msgstr "ETIR_S_C_STO_HINT_GBL: sin implementar"
-
-#~ msgid "ETIR_S_C_STO_HINT_PS: not implemented"
-#~ msgstr "ETIR_S_C_STO_HINT_PS: sin implementar"
-
 #~ msgid "ETIR_S_C_OPR_INSV: Not supported"
 #~ msgstr "ETIR_S_C_OPR_INSV: No se admite"
 

diff --git a/bfd/po/vi.po b/bfd/po/vi.po
index e0f3e12..8664ce7 100644 (file)
--- a/bfd/po/vi.po
+++ b/bfd/po/vi.po
@@ -1,22 +1,22 @@
 # Vietnamese translation for BFD.
-# Copyright © 2008 Free Software Foundation, Inc.
+# Copyright © 2009 Free Software Foundation, Inc.
 # This file is distributed under the same license as the binutils package.
 # Phần Vĩnh Thịnh <teppi@gmail.com>, 2005.
-# Clytie Siddall <clytie@riverland.net.au>, 2008.
+# Clytie Siddall <clytie@riverland.net.au>, 2008-2009.
 #
 msgid ""
 msgstr ""
-"Project-Id-Version: bfd 2.18.90\n"
+"Project-Id-Version: bfd 2.19.90\n"
 "Report-Msgid-Bugs-To: bug-binutils@gnu.org\n"
-"POT-Creation-Date: 2008-09-09 15:56+0930\n"
-"PO-Revision-Date: 2008-09-23 22:51+0930\n"
+"POT-Creation-Date: 2009-09-07 14:05+0200\n"
+"PO-Revision-Date: 2009-09-18 16:56+0930\n"
 "Last-Translator: Clytie Siddall <clytie@riverland.net.au>\n"
 "Language-Team: Vietnamese <vi-VN@googlegroups.com>\n"
 "MIME-Version: 1.0\n"
 "Content-Type: text/plain; charset=UTF-8\n"
 "Content-Transfer-Encoding: 8bit\n"
 "Plural-Forms: nplurals=1; plural=0;\n"
-"X-Generator: LocFactoryEditor 1.7b3\n"
+"X-Generator: LocFactoryEditor 1.8\n"
 
 #: aout-adobe.c:127
 msgid "%B: Unknown section type in a.out.adobe file: %x\n"
@@ -35,151 +35,151 @@ msgstr "%B: Đã nhập kiểu định vị lại không hợp lệ: %d"
 msgid "%B: Bad relocation record imported: %d"
 msgstr "%B: Đã nhập mục ghi định vị lại sai: %d"
 
-#: aoutx.h:1268 aoutx.h:1604
+#: aoutx.h:1271 aoutx.h:1609
 #, c-format
 msgid "%s: can not represent section `%s' in a.out object file format"
 msgstr "%s: không thể đại diện phân « %s » trong định dạng tập tin đối tượng a.out"
 
-#: aoutx.h:1570
+#: aoutx.h:1575
 #, c-format
 msgid "%s: can not represent section for symbol `%s' in a.out object file format"
 msgstr "%s: không thể đại diện phân cho ký hiệu « %s » trong định dạng tập tin đối tượng a.ou"
 
-#: aoutx.h:1572
+#: aoutx.h:1577
 msgid "*unknown*"
 msgstr "• không rõ •"
 
-#: aoutx.h:3989 aoutx.h:4315
+#: aoutx.h:3994 aoutx.h:4320
 msgid "%P: %B: unexpected relocation type\n"
 msgstr "%P: %B: kiểu định vị lại bất thường\n"
 
-#: aoutx.h:5349
+#: aoutx.h:5354
 #, c-format
 msgid "%s: relocatable link from %s to %s not supported"
 msgstr "%s: không hỗ trợ liên kết có khả năng định vị lại từ %s sang %s"
 
-#: archive.c:2046
+#: archive.c:2056
 msgid "Warning: writing archive was slow: rewriting timestamp\n"
 msgstr "Cảnh báo : ghi kho quá chậm nên đang ghi lại nhãn thời gian\n"
 
-#: archive.c:2309
+#: archive.c:2342
 msgid "Reading archive file mod timestamp"
 msgstr "Đang đọc nhãn thời gian sửa đổi tập tin kho"
 
-#: archive.c:2333
+#: archive.c:2366
 msgid "Writing updated armap timestamp"
 msgstr "Đang ghi nhãn thời gian armap đã cập nhật"
 
-#: bfd.c:368
+#: bfd.c:375
 msgid "No error"
 msgstr "Không có lỗi"
 
-#: bfd.c:369
+#: bfd.c:376
 msgid "System call error"
 msgstr "Lỗi gọi hệ thống"
 
-#: bfd.c:370
+#: bfd.c:377
 msgid "Invalid bfd target"
 msgstr "Đích bfd không hợp lệ"
 
-#: bfd.c:371
+#: bfd.c:378
 msgid "File in wrong format"
 msgstr "Tập tin có định dạng không đúng"
 
-#: bfd.c:372
+#: bfd.c:379
 msgid "Archive object file in wrong format"
 msgstr "Tập tin đối tượng kho có định dạng không đúng"
 
-#: bfd.c:373
+#: bfd.c:380
 msgid "Invalid operation"
 msgstr "Thao tác không hợp lệ"
 
-#: bfd.c:374
+#: bfd.c:381
 msgid "Memory exhausted"
 msgstr "Cạn bộ nhớ"
 
-#: bfd.c:375
+#: bfd.c:382
 msgid "No symbols"
 msgstr "Không có ký hiệu"
 
-#: bfd.c:376
+#: bfd.c:383
 msgid "Archive has no index; run ranlib to add one"
 msgstr "Kho không có chỉ mục: hãy chạy ranlib để thêm"
 
-#: bfd.c:377
+#: bfd.c:384
 msgid "No more archived files"
 msgstr "Không còn có tập tin đã lưu trữ nào nữa"
 
-#: bfd.c:378
+#: bfd.c:385
 msgid "Malformed archive"
 msgstr "Kho dạng sai"
 
-#: bfd.c:379
+#: bfd.c:386
 msgid "File format not recognized"
 msgstr "Không nhận ra định dạng tập tin"
 
-#: bfd.c:380
+#: bfd.c:387
 msgid "File format is ambiguous"
 msgstr "Định dạng tập tin mơ hồ"
 
-#: bfd.c:381
+#: bfd.c:388
 msgid "Section has no contents"
 msgstr "Phần không có nội dung"
 
-#: bfd.c:382
+#: bfd.c:389
 msgid "Nonrepresentable section on output"
 msgstr "Kết xuất có phần không thể đại diện được"
 
-#: bfd.c:383
+#: bfd.c:390
 msgid "Symbol needs debug section which does not exist"
 msgstr "Ký hiệu cần phần gỡ lỗi mà không tồn tại"
 
-#: bfd.c:384
+#: bfd.c:391
 msgid "Bad value"
 msgstr "Giá trị sai"
 
-#: bfd.c:385
+#: bfd.c:392
 msgid "File truncated"
 msgstr "Tập tin bị cắt ngắn"
 
-#: bfd.c:386
+#: bfd.c:393
 msgid "File too big"
 msgstr "Tập tin quá lớn"
 
-#: bfd.c:387
+#: bfd.c:394
 #, c-format
 msgid "Error reading %s: %s"
 msgstr "Gặp lỗi khi đọc %s: %s"
 
-#: bfd.c:388
+#: bfd.c:395
 msgid "#<Invalid error code>"
 msgstr "#<mã lỗi không hợp lệ>"
 
-#: bfd.c:912
+#: bfd.c:919
 #, c-format
 msgid "BFD %s assertion fail %s:%d"
 msgstr "BFD %s khắng định bị lỗi %s:%d"
 
-#: bfd.c:924
+#: bfd.c:931
 #, c-format
 msgid "BFD %s internal error, aborting at %s line %d in %s\n"
 msgstr "BFD %s lỗi nội bộ nên hủy bỏ tại %s dòng %d trong %s\n"
 
-#: bfd.c:928
+#: bfd.c:935
 #, c-format
 msgid "BFD %s internal error, aborting at %s line %d\n"
 msgstr "BFD %s lỗi nội bộ nên hủy bỏ tại %s dòng %d\n"
 
-#: bfd.c:930
+#: bfd.c:937
 msgid "Please report this bug.\n"
 msgstr "Hãy thông báo lỗi này.\n"
 
-#: bfdwin.c:208
+#: bfdwin.c:206
 #, c-format
 msgid "not mapping: data=%lx mapped=%d\n"
 msgstr "không đang ánh xạ: dữ liệu=%lx đã ánh xạ=%d\n"
 
-#: bfdwin.c:211
+#: bfdwin.c:209
 #, c-format
 msgid "not mapping: env var not set\n"
 msgstr "không đang ánh xạ: chưa đặt biến môi trường\n"
@@ -189,7 +189,13 @@ msgstr "không đang ánh xạ: chưa đặt biến môi trường\n"
 msgid "Warning: Writing section `%s' to huge (ie negative) file offset 0x%lx."
 msgstr "Cảnh báo : đang ghi phần « %s » vào khoảng bù tập tin rất lớn (tức là âm) 0x%lx."
 
-#: cache.c:222
+#: bout.c:1150 elf-m10300.c:2078 elf32-avr.c:1639 elf32-frv.c:5743
+#: elf32-xtensa.c:6639 elfxx-sparc.c:2456 reloc.c:5386 reloc16.c:162
+#: vms.c:1918 elf32-ia64.c:788 elf64-ia64.c:788
+msgid "%P%F: --relax and -r may not be used together\n"
+msgstr "%P%F: không thể dùng với nhau hai tuỳ chọn « --relax » và « -r »\n"
+
+#: cache.c:226
 msgid "reopening %B: %s\n"
 msgstr "đang mở lại %B: %s\n"
 
@@ -221,8 +227,8 @@ msgstr "%B: định vị lại không được hỗ trợ : ALPHA_R_GPRELHIGH"
 msgid "%B: unsupported relocation: ALPHA_R_GPRELLOW"
 msgstr "%B: định vị lại không được hỗ trợ : ALPHA_R_GPRELLOW"
 
-#: coff-alpha.c:1574 elf32-m32r.c:2487 elf64-alpha.c:3970 elf64-alpha.c:4125
-#: elf32-ia64.c:4465 elf64-ia64.c:4465
+#: coff-alpha.c:1574 elf32-m32r.c:2477 elf64-alpha.c:3943 elf64-alpha.c:4098
+#: elf32-ia64.c:4462 elf64-ia64.c:4462
 msgid "%B: unknown relocation type %d"
 msgstr "%B: không rõ kiểu định vị lại %d"
 
@@ -236,7 +242,7 @@ msgstr "%B: không tìm thấy keo hồ THUMB « %s » cho « %s »"
 msgid "%B: unable to find ARM glue '%s' for `%s'"
 msgstr "%B: không tìm thấy keo hồ ARM « %s » cho « %s »"
 
-#: coff-arm.c:1370 elf32-arm.c:5453
+#: coff-arm.c:1370 elf32-arm.c:6372
 #, c-format
 msgid ""
 "%B(%s): warning: interworking not enabled.\n"
@@ -256,7 +262,7 @@ msgstr ""
 "  lần xuất hiện đầu tiên: %B: gọi thumb tới arm\n"
 "  coi như liên kết lại với « --support-old-code » được bật"
 
-#: coff-arm.c:1755 coff-tic80.c:695 cofflink.c:3018
+#: coff-arm.c:1755 coff-tic80.c:695 cofflink.c:3027
 msgid "%B: bad reloc address 0x%lx in section `%A'"
 msgstr "%B: địa chỉ định vị lại sai 0x%lx trong phần « %A »"
 
@@ -266,35 +272,35 @@ msgstr "%B: chỉ mục ký hiệu cấm trong định vị lại: %d"
 
 #: coff-arm.c:2211
 #, c-format
-msgid "ERROR: %B is compiled for APCS-%d, whereas %B is compiled for APCS-%d"
-msgstr "LỖI: %B được biên dịch cho APCS-%d, còn %B được biên dịch cho APCS-%d"
+msgid "error: %B is compiled for APCS-%d, whereas %B is compiled for APCS-%d"
+msgstr "lỗi: %B được biên dịch cho APCS-%d, còn %B được biên dịch cho APCS-%d"
 
-#: coff-arm.c:2227 elf32-arm.c:8563
+#: coff-arm.c:2227 elf32-arm.c:10327
 #, c-format
-msgid "ERROR: %B passes floats in float registers, whereas %B passes them in integer registers"
-msgstr "LỖI: %B gửi trôi qua trong thanh ghi trôi, còn %B gửi chúng qua trong thanh ghi số nguyên"
+msgid "error: %B passes floats in float registers, whereas %B passes them in integer registers"
+msgstr "lỗi: %B gửi trôi qua trong thanh ghi trôi, còn %B gửi chúng qua trong thanh ghi số nguyên"
 
-#: coff-arm.c:2230 elf32-arm.c:8567
+#: coff-arm.c:2230 elf32-arm.c:10331
 #, c-format
-msgid "ERROR: %B passes floats in integer registers, whereas %B passes them in float registers"
-msgstr "LỖI: %B gửi trôi qua trong thanh ghi số nguyên, còn %B gửi chúng qua trong thanh ghi trôi"
+msgid "error: %B passes floats in integer registers, whereas %B passes them in float registers"
+msgstr "lỗi: %B gửi trôi qua trong thanh ghi số nguyên, còn %B gửi chúng qua trong thanh ghi trôi"
 
 #: coff-arm.c:2244
 #, c-format
-msgid "ERROR: %B is compiled as position independent code, whereas target %B is absolute position"
-msgstr "LỖI: %B được biên dịch như mã không phụ thuộc vào vị trí, còn %B là vị trí tuyệt đối"
+msgid "error: %B is compiled as position independent code, whereas target %B is absolute position"
+msgstr "lỗi: %B được biên dịch như mã không phụ thuộc vào vị trí, còn %B là vị trí tuyệt đối"
 
 #: coff-arm.c:2247
 #, c-format
-msgid "ERROR: %B is compiled as absolute position code, whereas target %B is position independent"
-msgstr "LỖI: %B được biên dịch như mã vị trí tuyệt đối, còn %B không phụ thuộc vào vị trí"
+msgid "error: %B is compiled as absolute position code, whereas target %B is position independent"
+msgstr "lỗi: %B được biên dịch như mã vị trí tuyệt đối, còn %B không phụ thuộc vào vị trí"
 
-#: coff-arm.c:2275 elf32-arm.c:8632
+#: coff-arm.c:2275 elf32-arm.c:10396
 #, c-format
 msgid "Warning: %B supports interworking, whereas %B does not"
 msgstr "Cảnh báo : %B hỗ trợ ảnh hưởng lẫn nhau, còn %B thì không"
 
-#: coff-arm.c:2278 elf32-arm.c:8638
+#: coff-arm.c:2278 elf32-arm.c:10402
 #, c-format
 msgid "Warning: %B does not support interworking, whereas %B does"
 msgstr "Cảnh báo : %B không hỗ trợ ảnh hưởng lẫn nhau, còn %B thì có"
@@ -304,7 +310,7 @@ msgstr "Cảnh báo : %B không hỗ trợ ảnh hưởng lẫn nhau, còn %B th
 msgid "private flags = %x:"
 msgstr "các cờ riêng = %x:"
 
-#: coff-arm.c:2310 elf32-arm.c:8689
+#: coff-arm.c:2310 elf32-arm.c:10453
 #, c-format
 msgid " [floats passed in float registers]"
 msgstr " [các trôi được gửi qua trong thanh ghi trôi]"
@@ -314,7 +320,7 @@ msgstr " [các trôi được gửi qua trong thanh ghi trôi]"
 msgid " [floats passed in integer registers]"
 msgstr " [các trôi được gửi qua trong thanh ghi số nguyên]"
 
-#: coff-arm.c:2315 elf32-arm.c:8692
+#: coff-arm.c:2315 elf32-arm.c:10456
 #, c-format
 msgid " [position independent]"
 msgstr " [không phụ thuộc vào vị trí]"
@@ -339,12 +345,12 @@ msgstr " [hỗ trợ ảnh hưởng lẫn nhau]"
 msgid " [interworking not supported]"
 msgstr " [không hỗ trợ ảnh hưởng lẫn nhau]"
 
-#: coff-arm.c:2371 elf32-arm.c:8050
+#: coff-arm.c:2371 elf32-arm.c:9360
 #, c-format
 msgid "Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"
 msgstr "Cảnh báo : không đang đặt cờ ảnh hưởng lẫn nhau của %B vì nó đã được xác định là không ảnh hưởng lẫn nhau"
 
-#: coff-arm.c:2375 elf32-arm.c:8054
+#: coff-arm.c:2375 elf32-arm.c:9364
 #, c-format
 msgid "Warning: Clearing the interworking flag of %B due to outside request"
 msgstr "Cảnh báo : Đang xoá cờ ảnh hưởng lẫn nhau của %B theo yêu cầu bên ngoài"
@@ -359,7 +365,7 @@ msgstr "không thể xử lý định vị lại R_MEM_INDIRECT khi sử dụng
 msgid "Relocation `%s' not yet implemented\n"
 msgstr "Chưa thực hiện định vị lại « %s »\n"
 
-#: coff-i860.c:605 coff-tic54x.c:398 coffcode.h:4975
+#: coff-i860.c:605 coff-tic54x.c:398 coffcode.h:5143
 msgid "%B: warning: illegal symbol index %ld in relocs"
 msgstr "%B: cảnh báo : chỉ mục ký hiệu cấm %ld trong định vị lại"
 
@@ -367,7 +373,7 @@ msgstr "%B: cảnh báo : chỉ mục ký hiệu cấm %ld trong định vị l
 msgid "uncertain calling convention for non-COFF symbol"
 msgstr "quy ước gọi không chắc chắn cho ký hiệu khác COFF"
 
-#: coff-m68k.c:506 elf32-bfin.c:5510 elf32-m68k.c:3938
+#: coff-m68k.c:506 elf32-bfin.c:5693 elf32-cr16.c:2965 elf32-m68k.c:4615
 msgid "unsupported reloc type"
 msgstr "kiểu định vị lại không được hỗ trợ"
 
@@ -391,8 +397,8 @@ msgstr "Địa chỉ tuyệt đối vượt quá phạm vi 8 bit"
 msgid "Unrecognized Reloc Type"
 msgstr "Kiểu định vị lại không được nhận ra"
 
-#: coff-mips.c:688 elf32-mips.c:1014 elf32-score.c:345 elf64-mips.c:1991
-#: elfn32-mips.c:1832
+#: coff-mips.c:688 elf32-mips.c:1014 elf32-score.c:441 elf32-score7.c:341
+#: elf64-mips.c:2018 elfn32-mips.c:1832
 msgid "GP relative relocation when _gp not defined"
 msgstr "Có định vị lại tương đối GP khi chưa xác định _gp"
 
@@ -400,17 +406,17 @@ msgstr "Có định vị lại tương đối GP khi chưa xác định _gp"
 msgid "Unrecognized reloc"
 msgstr "Định vị lại không được nhận ra"
 
-#: coff-rs6000.c:2803
+#: coff-rs6000.c:2787
 #, c-format
 msgid "%s: unsupported relocation type 0x%02x"
 msgstr "%s: kiểu định vị lại không được hỗ trợ 0x%02x"
 
-#: coff-rs6000.c:2896
+#: coff-rs6000.c:2880
 #, c-format
 msgid "%s: TOC reloc at 0x%x to symbol `%s' with no TOC entry"
 msgstr "%s: định vị lại TOC tại 0x%x tới ký hiệu « %s » không có mục nhập TOC"
 
-#: coff-rs6000.c:3628 coff64-rs6000.c:2130
+#: coff-rs6000.c:3646 coff64-rs6000.c:2168
 msgid "%B: symbol `%s' has unrecognized smclas %d"
 msgstr "%B: ký tự « %s » có smclas không nhận ra %d"
 
@@ -429,139 +435,143 @@ msgstr "%s: cảnh báo : chỉ mục ký hiệu cấm %ld trong các định v
 msgid "ignoring reloc %s\n"
 msgstr "Đang lờ đi định vị lại %s\n"
 
-#: coffcode.h:850
+#: coffcode.h:960
 msgid "%B: warning: COMDAT symbol '%s' does not match section name '%s'"
 msgstr "%B: cảnh báo : ký hiệu COMDAT « %s » không tương ứng vơi tên phần « %s »"
 
 #. Generate a warning message rather using the 'unhandled'
 #. variable as this will allow some .sys files generate by
 #. other toolchains to be processed.  See bugzilla issue 196.
-#: coffcode.h:1062
+#: coffcode.h:1176
 msgid "%B: Warning: Ignoring section flag IMAGE_SCN_MEM_NOT_PAGED in section %s"
 msgstr "%B: Cảnh báo: Đang lờ đi cờ của phần IMAGE_SCN_MEM_NOT_PAGED trong phần %s"
 
-#: coffcode.h:1117
+#: coffcode.h:1240
 msgid "%B (%s): Section flag %s (0x%x) ignored"
 msgstr "%B (%s): Đã lờ đi cờ của phần %s (0x%x)"
 
-#: coffcode.h:2244
+#: coffcode.h:2382
 #, c-format
 msgid "Unrecognized TI COFF target id '0x%x'"
 msgstr "Không nhận ra mã số đích TI COFF « 0x%x »"
 
-#: coffcode.h:2559
+#: coffcode.h:2696
 msgid "%B: reloc against a non-existant symbol index: %ld"
 msgstr "%B: định vị lại so với một chỉ mục ký hiệu không tồn tại: %ld"
 
-#: coffcode.h:4309
+#: coffcode.h:3669
+msgid "%B: section %s: string table overflow at offset %ld"
+msgstr "%B: phần %s: tràn bảng chuỗi ở hiệu %ld"
+
+#: coffcode.h:4477
 msgid "%B: warning: line number table read failed"
 msgstr "%B: Cảnh bảo : lỗi đọc bảng số thứ tự dòng"
 
-#: coffcode.h:4339
+#: coffcode.h:4507
 msgid "%B: warning: illegal symbol index %ld in line numbers"
 msgstr "%B: cảnh báo : chỉ mục ký hiệu cấm %ld trong các số thứ tự dòng"
 
-#: coffcode.h:4353
+#: coffcode.h:4521
 msgid "%B: warning: duplicate line number information for `%s'"
 msgstr "%B: cảnh báo : thông tin số thứ tự dòng trùng đối với « %s »"
 
-#: coffcode.h:4744
+#: coffcode.h:4912
 msgid "%B: Unrecognized storage class %d for %s symbol `%s'"
 msgstr "%B: Không nhận ra hạng lưu trữ %d cho ký hiệu %s « %s »"
 
-#: coffcode.h:4870
+#: coffcode.h:5038
 msgid "warning: %B: local symbol `%s' has no section"
 msgstr "cảnh báo : %B: ký hiệu cục bộ « %s » không có phần đoạn"
 
-#: coffcode.h:5013
+#: coffcode.h:5181
 msgid "%B: illegal relocation type %d at address 0x%lx"
 msgstr "%B: kiểu định vị lại cấm %d ở địa chỉ 0x%lx"
 
-#: coffgen.c:1518
+#: coffgen.c:1571
 msgid "%B: bad string table size %lu"
 msgstr "%B: kích cỡ bảng chuỗi sai %lu"
 
-#: cofflink.c:513 elflink.c:4218
+#: cofflink.c:513 elflink.c:4307
 msgid "Warning: type of symbol `%s' changed from %d to %d in %B"
 msgstr "Cảnh báo : kiểu ký hiệu « %s » bị thay đổi từ %d thành %d trong %B"
 
-#: cofflink.c:2296
+#: cofflink.c:2305
 msgid "%B: relocs in section `%A', but it has no contents"
 msgstr "%B: định vị lại trong phần « %A », nhưng nó không có nội dung"
 
-#: cofflink.c:2627 coffswap.h:824
+#: cofflink.c:2636 coffswap.h:826
 #, c-format
 msgid "%s: %s: reloc overflow: 0x%lx > 0xffff"
 msgstr "%s: %s: tràn định vị lại: 0x%lx > 0xffff"
 
-#: cofflink.c:2636 coffswap.h:810
+#: cofflink.c:2645 coffswap.h:812
 #, c-format
 msgid "%s: warning: %s: line number overflow: 0x%lx > 0xffff"
 msgstr "%s: cảnh báo : %s: tràn số thứ tự dòng: 0x%lx > 0xffff"
 
 #: cpu-arm.c:189 cpu-arm.c:200
-msgid "ERROR: %B is compiled for the EP9312, whereas %B is compiled for XScale"
-msgstr "LỖI: %B được biên dịch cho EP9312, còn %B được biên dịch cho XScale"
+msgid "error: %B is compiled for the EP9312, whereas %B is compiled for XScale"
+msgstr "lỗi: %B được biên dịch cho EP9312, còn %B được biên dịch cho XScale"
 
 #: cpu-arm.c:332
 #, c-format
 msgid "warning: unable to update contents of %s section in %s"
 msgstr "cảnh báo : không thể cập nhật nội dung của phần %s trong %s"
 
-#: dwarf2.c:424
+#: dwarf2.c:430
 #, c-format
 msgid "Dwarf Error: Can't find %s section."
 msgstr "Lỗi Dwarf: không tìm thấy phần %s."
 
-#: dwarf2.c:452
+#: dwarf2.c:457
 #, c-format
 msgid "Dwarf Error: unable to decompress %s section."
 msgstr "Lỗi Dwarf: không thể giải nén phần %s."
 
-#: dwarf2.c:462
+#: dwarf2.c:468
 #, c-format
 msgid "Dwarf Error: Offset (%lu) greater than or equal to %s size (%lu)."
 msgstr "Lỗi Dwarf: Khoảng bù dòng (%lu) lớn hơn hoặc bằng kích cỡ %s (%lu)."
 
-#: dwarf2.c:849
+#: dwarf2.c:865
 #, c-format
 msgid "Dwarf Error: Invalid or unhandled FORM value: %u."
 msgstr "Lỗi Dwarf: Giá trị FORM sai hoặc chưa được xử lý: %u."
 
-#: dwarf2.c:1063
+#: dwarf2.c:1079
 msgid "Dwarf Error: mangled line number section (bad file number)."
 msgstr "Lỗi Dwarf: phần số thứ tự dòng đã rối (số thứ tự tập tin sai)."
 
-#: dwarf2.c:1393
+#: dwarf2.c:1413
 msgid "Dwarf Error: mangled line number section."
 msgstr "Lỗi Dwarf: phần số thứ tự dòng đã rối."
 
-#: dwarf2.c:1726 dwarf2.c:1842 dwarf2.c:2114
+#: dwarf2.c:1760 dwarf2.c:1867 dwarf2.c:2139
 #, c-format
 msgid "Dwarf Error: Could not find abbrev number %u."
 msgstr "Lỗi Dwarf: Không tìm thấy số viết tắt %u."
 
-#: dwarf2.c:2075
+#: dwarf2.c:2100
 #, c-format
-msgid "Dwarf Error: found dwarf version '%u', this reader only handles version 2 information."
-msgstr "Lỗi Dwarf: tìm thấy dwarf phiên bản « %u », nhưng trình đọc này chỉ điều khiển thông tin của phiên bản 2."
+msgid "Dwarf Error: found dwarf version '%u', this reader only handles version 2 and 3 information."
+msgstr "Lỗi Dwarf: tìm thấy dwarf phiên bản « %u », nhưng trình đọc này chỉ điều khiển thông tin của phiên bản 2 và 3."
 
-#: dwarf2.c:2082
+#: dwarf2.c:2107
 #, c-format
 msgid "Dwarf Error: found address size '%u', this reader can not handle sizes greater than '%u'."
 msgstr "Lỗi Dwarf: tìm thấy kích cỡ địa chỉ « %u », nhưng trình đọc này không điều khiển được kích cỡ lớn hơn « %u »."
 
-#: dwarf2.c:2105
+#: dwarf2.c:2130
 #, c-format
 msgid "Dwarf Error: Bad abbrev number: %u."
 msgstr "Lỗi Dwarf: Số viết tắt sai: %u."
 
-#: ecoff.c:1227
+#: ecoff.c:1238
 #, c-format
 msgid "Unknown basic type %d"
 msgstr "Không rõ kiểu cơ bản %d"
 
-#: ecoff.c:1484
+#: ecoff.c:1495
 #, c-format
 msgid ""
 "\n"
@@ -570,7 +580,7 @@ msgstr ""
 "\n"
 "      Ký hiệu End+1: %ld"
 
-#: ecoff.c:1491 ecoff.c:1494
+#: ecoff.c:1502 ecoff.c:1505
 #, c-format
 msgid ""
 "\n"
@@ -579,7 +589,7 @@ msgstr ""
 "\n"
 "      Ký hiệu đầu tiên: %ld"
 
-#: ecoff.c:1506
+#: ecoff.c:1517
 #, c-format
 msgid ""
 "\n"
@@ -588,7 +598,7 @@ msgstr ""
 "\n"
 "      Ký hiệu End+1: %-7ld   Kiểu :  %s"
 
-#: ecoff.c:1513
+#: ecoff.c:1524
 #, c-format
 msgid ""
 "\n"
@@ -597,7 +607,7 @@ msgstr ""
 "\n"
 "      Ký hiệu cục bộ : %ld"
 
-#: ecoff.c:1521
+#: ecoff.c:1532
 #, c-format
 msgid ""
 "\n"
@@ -606,7 +616,7 @@ msgstr ""
 "\n"
 "      cấu trúc; ký hiệu End+1: %ld"
 
-#: ecoff.c:1526
+#: ecoff.c:1537
 #, c-format
 msgid ""
 "\n"
@@ -615,7 +625,7 @@ msgstr ""
 "\n"
 "      kết hợp; ký hiệu End+1: %ld"
 
-#: ecoff.c:1531
+#: ecoff.c:1542
 #, c-format
 msgid ""
 "\n"
@@ -624,7 +634,7 @@ msgstr ""
 "\n"
 "      đếm; ký hiệu End+1: %ld"
 
-#: ecoff.c:1537
+#: ecoff.c:1548
 #, c-format
 msgid ""
 "\n"
@@ -633,119 +643,124 @@ msgstr ""
 "\n"
 "      Kiểu : %s"
 
-#: elf-attrs.c:582
-msgid "ERROR: %B: Must be processed by '%s' toolchain"
-msgstr "LỖI: %B: Phải được dãy công cụ « %s » xử lý"
+#: elf-attrs.c:567
+msgid "error: %B: Must be processed by '%s' toolchain"
+msgstr "lỗi: %B: Phải được dãy công cụ « %s » xử lý"
 
-#: elf-attrs.c:602 elf-attrs.c:621
-msgid "ERROR: %B: Incompatible object tag '%s':%d"
-msgstr "LỖI: %B: Thẻ đối tượng không tương thích « %s »:%s"
+#: elf-attrs.c:575
+msgid "error: %B: Object tag '%d, %s' is incompatible with tag '%d, %s'"
+msgstr "lỗi: %B: thẻ đối tượng « %d, %s » không tương thích với thẻ « %d, %s »"
 
-#: elf-eh-frame.c:866
+#: elf-eh-frame.c:884
 msgid "%P: error in %B(%A); no .eh_frame_hdr table will be created.\n"
 msgstr "%P: gặp lỗi trong %B(%A); sẽ không tạo bảng .eh_frame_hdr nào.\n"
 
-#: elf-eh-frame.c:1102
+#: elf-eh-frame.c:1122
 msgid "%P: fde encoding in %B(%A) prevents .eh_frame_hdr table being created.\n"
 msgstr "%P: biên mã fde trong %B(%A) thì ngăn cản tạo bảng .eh_frame_hdr.\n"
 
-#: elf-hppa.h:2241 elf-m10300.c:1546 elf32-arm.c:7954 elf32-i386.c:3582
-#: elf32-m32r.c:2598 elf32-m68k.c:3516 elf32-ppc.c:7223 elf32-s390.c:3058
-#: elf32-sh.c:3438 elf32-xtensa.c:3021 elf64-ppc.c:11528 elf64-s390.c:3019
-#: elf64-sh64.c:1648 elf64-x86-64.c:3239 elfxx-sparc.c:3336
-msgid "%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"
-msgstr "%B(%A+0x%lx): định vị lại không thể giải quyết %s đối với ký hiệu « %s »"
-
-#: elf-hppa.h:2266 elf-hppa.h:2280
-msgid "%B(%A): warning: unresolvable relocation against symbol `%s'"
-msgstr "%B(%A): cảnh báo : định vị lại không thể giải quyết được so với ký hiệu « %s »"
+#: elf-ifunc.c:179
+msgid "%F%P: dynamic STT_GNU_IFUNC symbol `%s' with pointer equality in `%B' can not be used when making an executable; recompile with -fPIE and relink with -pie\n"
+msgstr "%F%P: ký hiệu STT_GNU_IFUNC động « %s » với tình trạng chất lượng con trỏ trong « %B » thì không dùng được khi tạo bản thực thi; hãy biên dịch lại với « -fPIE » và liên kết lại với « -pie »\n"
 
-#: elf-m10200.c:456 elf-m10300.c:1609 elf32-avr.c:1250 elf32-bfin.c:3214
-#: elf32-cr16.c:959 elf32-cr16c.c:790 elf32-cris.c:1538 elf32-crx.c:933
+#: elf-m10200.c:456 elf-m10300.c:1575 elf32-avr.c:1251 elf32-bfin.c:3200
+#: elf32-cr16.c:1517 elf32-cr16c.c:790 elf32-cris.c:2089 elf32-crx.c:933
 #: elf32-d10v.c:516 elf32-fr30.c:616 elf32-frv.c:4114 elf32-h8300.c:516
-#: elf32-i860.c:1218 elf32-ip2k.c:1499 elf32-iq2000.c:691 elf32-m32c.c:560
-#: elf32-m32r.c:3124 elf32-m68hc1x.c:1135 elf32-mep.c:541 elf32-msp430.c:493
-#: elf32-mt.c:402 elf32-openrisc.c:411 elf32-score.c:2451 elf32-spu.c:4132
-#: elf32-v850.c:1703 elf32-xstormy16.c:948 elf64-mmix.c:1533
+#: elf32-i860.c:1218 elf32-ip2k.c:1499 elf32-iq2000.c:691 elf32-lm32.c:1171
+#: elf32-m32c.c:560 elf32-m32r.c:3102 elf32-m68hc1x.c:1136 elf32-mep.c:541
+#: elf32-microblaze.c:1226 elf32-moxie.c:291 elf32-msp430.c:493 elf32-mt.c:402
+#: elf32-openrisc.c:411 elf32-score.c:2752 elf32-score7.c:2591
+#: elf32-spu.c:5045 elf32-v850.c:1701 elf32-xstormy16.c:948 elf64-mmix.c:1533
 msgid "internal error: out of range error"
 msgstr "lỗi nội bộ : lỗi ở ngoại phạm vi"
 
-#: elf-m10200.c:460 elf-m10300.c:1613 elf32-avr.c:1254 elf32-bfin.c:3218
-#: elf32-cr16.c:963 elf32-cr16c.c:794 elf32-cris.c:1542 elf32-crx.c:937
+#: elf-m10200.c:460 elf-m10300.c:1579 elf32-avr.c:1255 elf32-bfin.c:3204
+#: elf32-cr16.c:1521 elf32-cr16c.c:794 elf32-cris.c:2093 elf32-crx.c:937
 #: elf32-d10v.c:520 elf32-fr30.c:620 elf32-frv.c:4118 elf32-h8300.c:520
-#: elf32-i860.c:1222 elf32-iq2000.c:695 elf32-m32c.c:564 elf32-m32r.c:3128
-#: elf32-m68hc1x.c:1139 elf32-mep.c:545 elf32-msp430.c:497
-#: elf32-openrisc.c:415 elf32-score.c:2455 elf32-spu.c:4136 elf32-v850.c:1707
-#: elf32-xstormy16.c:952 elf64-mmix.c:1537 elfxx-mips.c:9065
+#: elf32-i860.c:1222 elf32-iq2000.c:695 elf32-lm32.c:1175 elf32-m32c.c:564
+#: elf32-m32r.c:3106 elf32-m68hc1x.c:1140 elf32-mep.c:545
+#: elf32-microblaze.c:1230 elf32-moxie.c:295 elf32-msp430.c:497
+#: elf32-openrisc.c:415 elf32-score.c:2756 elf32-score7.c:2595
+#: elf32-spu.c:5049 elf32-v850.c:1705 elf32-xstormy16.c:952 elf64-mmix.c:1537
+#: elfxx-mips.c:9103
 msgid "internal error: unsupported relocation error"
 msgstr "lỗi nội bộ : lỗi định vị lại không được hỗ trợ"
 
-#: elf-m10200.c:464 elf32-cr16.c:967 elf32-cr16c.c:798 elf32-crx.c:941
-#: elf32-d10v.c:524 elf32-h8300.c:524 elf32-m32r.c:3132 elf32-m68hc1x.c:1143
-#: elf32-score.c:2459 elf32-spu.c:4140
+#: elf-m10200.c:464 elf32-cr16.c:1525 elf32-cr16c.c:798 elf32-crx.c:941
+#: elf32-d10v.c:524 elf32-h8300.c:524 elf32-lm32.c:1179 elf32-m32r.c:3110
+#: elf32-m68hc1x.c:1144 elf32-microblaze.c:1234 elf32-score.c:2760
+#: elf32-score7.c:2599 elf32-spu.c:5053
 msgid "internal error: dangerous error"
 msgstr "lỗi nội bộ : lỗi nguy hiểm"
 
-#: elf-m10200.c:468 elf-m10300.c:1626 elf32-avr.c:1262 elf32-bfin.c:3226
-#: elf32-cr16.c:971 elf32-cr16c.c:802 elf32-cris.c:1550 elf32-crx.c:945
+#: elf-m10200.c:468 elf-m10300.c:1592 elf32-avr.c:1263 elf32-bfin.c:3212
+#: elf32-cr16.c:1529 elf32-cr16c.c:802 elf32-cris.c:2101 elf32-crx.c:945
 #: elf32-d10v.c:528 elf32-fr30.c:628 elf32-frv.c:4126 elf32-h8300.c:528
-#: elf32-i860.c:1230 elf32-ip2k.c:1514 elf32-iq2000.c:703 elf32-m32c.c:572
-#: elf32-m32r.c:3136 elf32-m68hc1x.c:1147 elf32-mep.c:553 elf32-msp430.c:505
-#: elf32-mt.c:410 elf32-openrisc.c:423 elf32-score.c:2463 elf32-spu.c:4144
-#: elf32-v850.c:1727 elf32-xstormy16.c:960 elf64-mmix.c:1545
+#: elf32-i860.c:1230 elf32-ip2k.c:1514 elf32-iq2000.c:703 elf32-lm32.c:1183
+#: elf32-m32c.c:572 elf32-m32r.c:3114 elf32-m68hc1x.c:1148 elf32-mep.c:553
+#: elf32-microblaze.c:1238 elf32-moxie.c:303 elf32-msp430.c:505 elf32-mt.c:410
+#: elf32-openrisc.c:423 elf32-score.c:2769 elf32-score7.c:2603
+#: elf32-spu.c:5057 elf32-v850.c:1725 elf32-xstormy16.c:960 elf64-mmix.c:1545
 msgid "internal error: unknown error"
 msgstr "lỗi nội bộ : lỗi không rõ"
 
-#: elf-m10300.c:1618
+#: elf-m10300.c:1512 elf32-arm.c:8963 elf32-i386.c:3984 elf32-m32r.c:2588
+#: elf32-m68k.c:4099 elf32-ppc.c:7906 elf32-s390.c:3015 elf32-sh.c:3429
+#: elf32-xtensa.c:3027 elf64-ppc.c:12063 elf64-s390.c:2974 elf64-sh64.c:1648
+#: elf64-x86-64.c:3657 elfxx-sparc.c:3317
+msgid "%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"
+msgstr "%B(%A+0x%lx): định vị lại không thể giải quyết %s đối với ký hiệu « %s »"
+
+#: elf-m10300.c:1584
 msgid "error: inappropriate relocation type for shared library (did you forget -fpic?)"
 msgstr "lỗi: kiểu định vị lại không thích hợp cho thư viện chia sẻ (bạn đã quên đặt -fpic không?)"
 
-#: elf-m10300.c:1621
+#: elf-m10300.c:1587
 msgid "internal error: suspicious relocation type used in shared library"
 msgstr "lỗi nội bộ: kiểu định vị lại đáng ngờ được dùng trong thư viện chia sẻ"
 
-#: elf-m10300.c:4397 elf32-arm.c:9578 elf32-cris.c:2403 elf32-hppa.c:1921
-#: elf32-i370.c:506 elf32-i386.c:1807 elf32-m32r.c:1931 elf32-m68k.c:2787
-#: elf32-ppc.c:4693 elf32-s390.c:1687 elf32-sh.c:2583 elf32-vax.c:1055
-#: elf64-ppc.c:6075 elf64-s390.c:1662 elf64-sh64.c:3432 elf64-x86-64.c:1641
-#: elfxx-sparc.c:1828
+#: elf-m10300.c:4385 elf32-arm.c:11346 elf32-cr16.c:2519 elf32-cris.c:3030
+#: elf32-hppa.c:1891 elf32-i370.c:506 elf32-i386.c:1975 elf32-lm32.c:1873
+#: elf32-m32r.c:1921 elf32-m68k.c:3188 elf32-ppc.c:4953 elf32-s390.c:1650
+#: elf32-sh.c:2574 elf32-vax.c:1052 elf64-ppc.c:6348 elf64-s390.c:1623
+#: elf64-sh64.c:3396 elf64-x86-64.c:1821 elfxx-sparc.c:1802
 #, c-format
 msgid "dynamic variable `%s' is zero size"
 msgstr "biến động « %s » có kích cỡ số không"
 
-#: elf.c:328
+#: elf.c:329
 msgid "%B: invalid string offset %u >= %lu for section `%s'"
 msgstr "%B: khoảng bù chuỗi không hợp lệ %u≥%lu cho phần « %s »"
 
-#: elf.c:438
+#: elf.c:439
 msgid "%B symbol number %lu references nonexistent SHT_SYMTAB_SHNDX section"
 msgstr "%B số thứ tự ký hiệu %lu tham chiếu đến phần SHT_SYMTAB_SHNDX không tồn tại"
 
-#: elf.c:594
+#: elf.c:595
 msgid "%B: Corrupt size field in group section header: 0x%lx"
 msgstr "%B: Trường kích cỡ bị hỏng trong phần đầu của phần nhóm: 0x%lx"
 
-#: elf.c:630
+#: elf.c:631
 msgid "%B: invalid SHT_GROUP entry"
 msgstr "%B: mục nhập SHT_GROUP không hợp lệ"
 
-#: elf.c:700
+#: elf.c:701
 msgid "%B: no group info for section %A"
 msgstr "%B: không có thông tin nhóm về phần %A"
 
-#: elf.c:729 elf.c:2976 elflink.c:9746
+#: elf.c:730 elf.c:2960 elflink.c:9912
 msgid "%B: warning: sh_link not set for section `%A'"
 msgstr "%B: cảnh báo : « sh_link » chưa được đặt cho phần « %A »"
 
-#: elf.c:748
+#: elf.c:749
 msgid "%B: sh_link [%d] in section `%A' is incorrect"
 msgstr "%B: sh_link [%d] không đúng trong phần « %A »"
 
-#: elf.c:783
+#: elf.c:784
 msgid "%B: unknown [%d] section `%s' in group [%s]"
 msgstr "%B: không rõ [%d] phần « %s » trong nhóm [%s]"
 
-#: elf.c:1159
+#: elf.c:1104
 #, c-format
 msgid ""
 "\n"
@@ -754,7 +769,7 @@ msgstr ""
 "\n"
 "Phần đầu chương trình:\n"
 
-#: elf.c:1201
+#: elf.c:1146
 #, c-format
 msgid ""
 "\n"
@@ -763,7 +778,7 @@ msgstr ""
 "\n"
 "Phần động:\n"
 
-#: elf.c:1337
+#: elf.c:1282
 #, c-format
 msgid ""
 "\n"
@@ -772,7 +787,7 @@ msgstr ""
 "\n"
 "Phần định nghĩa phiên bản:\n"
 
-#: elf.c:1362
+#: elf.c:1307
 #, c-format
 msgid ""
 "\n"
@@ -781,82 +796,82 @@ msgstr ""
 "\n"
 "Tham chiếu phiên bản:\n"
 
-#: elf.c:1367
+#: elf.c:1312
 #, c-format
 msgid "  required from %s:\n"
 msgstr "  cần thiết từ %s:\n"
 
-#: elf.c:1755
+#: elf.c:1702
 msgid "%B: invalid link %lu for reloc section %s (index %u)"
 msgstr "%B: liên kết không hợp lệ %lu cho phần định vị lại %s (chỉ mục %u)"
 
-#: elf.c:1924
+#: elf.c:1870
 msgid "%B: don't know how to handle allocated, application specific section `%s' [0x%8x]"
 msgstr "%B: không biết cách xử lý phần đã cấp phát mà đặc trưng cho ứng dụng « %s » [0x%8x]"
 
-#: elf.c:1936
+#: elf.c:1882
 msgid "%B: don't know how to handle processor specific section `%s' [0x%8x]"
 msgstr "%B: không biết cách xử lý phần đặc trưng cho bộ xử lý « %s » [0x%8x]"
 
-#: elf.c:1947
+#: elf.c:1893
 msgid "%B: don't know how to handle OS specific section `%s' [0x%8x]"
 msgstr "%B: không biết cách xử lý phần đặc trưng cho HĐH « %s » [0x%8x]"
 
-#: elf.c:1957
+#: elf.c:1903
 msgid "%B: don't know how to handle section `%s' [0x%8x]"
 msgstr "%B: không biết cách xử lý phần « %s » [0x%8x]"
 
-#: elf.c:2555
+#: elf.c:2500
 #, c-format
 msgid "warning: section `%A' type changed to PROGBITS"
 msgstr "cảnh báo : phần « %A » có kiểu bị thay đổi thành PROGBITS"
 
-#: elf.c:2933
+#: elf.c:2917
 msgid "%B: sh_link of section `%A' points to discarded section `%A' of `%B'"
 msgstr "%B: sh_link của phần « %A » chỉ tới phần bị hủy « %A » của « %B »"
 
-#: elf.c:2956
+#: elf.c:2940
 msgid "%B: sh_link of section `%A' points to removed section `%A' of `%B'"
 msgstr "%B: sh_link của phần « %A » chỉ tới phần bị gỡ bỏ « %A » của « %B »"
 
-#: elf.c:4300
+#: elf.c:4311
 msgid "%B: The first section in the PT_DYNAMIC segment is not the .dynamic section"
 msgstr "%B: Phần thứ nhất trong đoạn PT_DYNAMIC không phải là phần .dynamic"
 
-#: elf.c:4327
+#: elf.c:4338
 msgid "%B: Not enough room for program headers, try linking with -N"
 msgstr "%B: Không đủ sức chứa cho các phần đầu của chương trình: hãy thử liên kết với « -N »"
 
-#: elf.c:4404
+#: elf.c:4420
 msgid "%B: section %A vma 0x%lx overlaps previous sections"
 msgstr "%B: phần %A vma 0x%lx đè lên phần trước"
 
-#: elf.c:4499
+#: elf.c:4515
 msgid "%B: section `%A' can't be allocated in segment %d"
 msgstr "%B: phần « %A » không thể được cấp phát trong đoạn %d"
 
-#: elf.c:4549
+#: elf.c:4565
 msgid "%B: warning: allocated section `%s' not in segment"
 msgstr "%B: cảnh báo : phần đã cấp phát « %s » không nằm trong đoạn"
 
-#: elf.c:5064
+#: elf.c:5065
 msgid "%B: symbol `%s' required but not present"
 msgstr "%B: ký hiệu « %s » cần thiết mà không có"
 
-#: elf.c:5403
+#: elf.c:5404
 msgid "%B: warning: Empty loadable segment detected, is this intentional ?\n"
 msgstr "%B: cảnh báo : Phát hiện một đoạn rỗng có thể nạp được: trường hợp này có ý định trước không?\n"
 
-#: elf.c:6366
+#: elf.c:6370
 #, c-format
 msgid "Unable to find equivalent output section for symbol '%s' from section '%s'"
 msgstr "Không tìm thấy phần kết xuất tương đương cho ký hiệu « %s » từ phần « %s »"
 
-#: elf.c:7346
+#: elf.c:7356
 msgid "%B: unsupported relocation type %s"
 msgstr "%B: kiểu định vị lại không được hỗ trợ %s"
 
-#: elf32-arm.c:2846 elf32-arm.c:2878
+#: elf32-arm.c:3149
 msgid ""
 "%B(%s): warning: interworking not enabled.\n"
 "  first occurrence: %B: Thumb call to ARM"
@@ -864,40 +879,48 @@ msgstr ""
 "%B(%s): cảnh báo : chưa bật dùng ảnh hưởng lẫn nhau.\n"
 "  lần xuất hiện đầu: %B: thumb gọi tới ARM"
 
-#: elf32-arm.c:3041
+#: elf32-arm.c:3190
+msgid ""
+"%B(%s): warning: interworking not enabled.\n"
+"  first occurrence: %B: ARM call to Thumb"
+msgstr ""
+"%B(%s): cảnh báo : chưa bật dùng ảnh hưởng lẫn nhau.\n"
+"  lần xuất hiện đầu tiên: %B: gọi ARM tới Thumb"
+
+#: elf32-arm.c:3387 elf32-arm.c:4692
 #, c-format
 msgid "%s: cannot create stub entry %s"
 msgstr "%s: không thể tạo mục nhập mẩu %s"
 
-#: elf32-arm.c:3825
+#: elf32-arm.c:4804
 #, c-format
 msgid "unable to find THUMB glue '%s' for '%s'"
 msgstr "không tìm thấy keo hồ THUMB « %s » cho « %s »"
 
-#: elf32-arm.c:3859
+#: elf32-arm.c:4838
 #, c-format
 msgid "unable to find ARM glue '%s' for '%s'"
 msgstr "không tìm thấy keo hồ ARM « %s » cho « %s »"
 
-#: elf32-arm.c:4463
+#: elf32-arm.c:5365
 msgid "%B: BE8 images only valid in big-endian mode."
 msgstr "%B: hình ảnh BE8 chỉ đúng trong chế độ về cuối lớn."
 
 #. Give a warning, but do as the user requests anyway.
-#: elf32-arm.c:4678
+#: elf32-arm.c:5590
 msgid "%B: warning: selected VFP11 erratum workaround is not necessary for target architecture"
 msgstr "%B: cảnh báo : sự khắc phúc các lỗi VFP11 đã chọn không cần thiết cho kiến trúc đích"
 
-#: elf32-arm.c:5212 elf32-arm.c:5232
+#: elf32-arm.c:6130 elf32-arm.c:6150
 msgid "%B: unable to find VFP11 veneer `%s'"
 msgstr "%B: không tìm thấy lớp gỗ mặt VFP11 « %s »"
 
-#: elf32-arm.c:5278
+#: elf32-arm.c:6196
 #, c-format
 msgid "Invalid TARGET2 relocation type '%s'."
 msgstr "Kiểu định vị lại TARGET2 không hợp lệ « %s »"
 
-#: elf32-arm.c:5362
+#: elf32-arm.c:6281
 msgid ""
 "%B(%s): warning: interworking not enabled.\n"
 "  first occurrence: %B: thumb call to arm"
@@ -905,363 +928,409 @@ msgstr ""
 "%B(%s): cảnh báo : chưa bật dùng ảnh hưởng lẫn nhau.\n"
 "  lần xuất hiện đầu: %B: thumb gọi tới arm"
 
-#: elf32-arm.c:6094
+#: elf32-arm.c:7003
 msgid "\\%B: Warning: Arm BLX instruction targets Arm function '%s'."
 msgstr "\\%B: Cảnh báo : Chỉ dẫn Arm BLX đăt mục tiêu hàm Arm « %s »."
 
-#: elf32-arm.c:6418
+#: elf32-arm.c:7405
 msgid "%B: Warning: Thumb BLX instruction targets thumb function '%s'."
 msgstr "%B: Cảnh báo : Chỉ dẫn Thumb BLX đăt mục tiêu hàm thumb « %s »."
 
-#: elf32-arm.c:7095
+#: elf32-arm.c:8085
 msgid "%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object"
 msgstr "%B(%A+0x%lx): R_ARM_TLS_LE32 không cho phép định vị lại trong đối tượng dùng chung"
 
-#: elf32-arm.c:7310
+#: elf32-arm.c:8300
 msgid "%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations"
 msgstr "%B(%A+0x%lx): Chỉ cho phép chỉ dẫn kiểu ADD (cộng) hoặc SUB (trừ) khi định vị lại nhóm ALU"
 
-#: elf32-arm.c:7350 elf32-arm.c:7437 elf32-arm.c:7520 elf32-arm.c:7605
+#: elf32-arm.c:8340 elf32-arm.c:8427 elf32-arm.c:8510 elf32-arm.c:8595
 msgid "%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"
 msgstr "%B(%A+0x%lx): Tràn trong khi tách ra 0x%lx để định vị lại nhóm %s"
 
-#: elf32-arm.c:7812 elf32-sh.c:3334 elf64-sh64.c:1556
+#: elf32-arm.c:8821 elf32-sh.c:3325 elf64-sh64.c:1556
 msgid "%B(%A+0x%lx): %s relocation against SEC_MERGE section"
 msgstr "%B(%A+0x%lx): %s định vị lại đối lại phần SEC_MERGE"
 
-#: elf32-arm.c:7930 elf32-xtensa.c:2759 elf64-ppc.c:10374
+#: elf32-arm.c:8939 elf32-m68k.c:4134 elf32-xtensa.c:2765 elf64-ppc.c:10743
 msgid "%B(%A+0x%lx): %s used with TLS symbol %s"
 msgstr "%B(%A+0x%lx): %s được dùng với ký hiệu TLS %s"
 
-#: elf32-arm.c:7931 elf32-xtensa.c:2760 elf64-ppc.c:10375
+#: elf32-arm.c:8940 elf32-m68k.c:4135 elf32-xtensa.c:2766 elf64-ppc.c:10744
 msgid "%B(%A+0x%lx): %s used with non-TLS symbol %s"
 msgstr "%B(%A+0x%lx): %s được dùng với ký hiệu khác TLS %s"
 
-#: elf32-arm.c:7988
+#: elf32-arm.c:8997
 msgid "out of range"
 msgstr "ở ngoại phạm vi"
 
-#: elf32-arm.c:7992
+#: elf32-arm.c:9001
 msgid "unsupported relocation"
 msgstr "định vị lại không được hỗ trợ"
 
-#: elf32-arm.c:8000
+#: elf32-arm.c:9009
 msgid "unknown error"
 msgstr "lỗi không rõ"
 
-#: elf32-arm.c:8099
+#: elf32-arm.c:9409
 msgid "Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"
 msgstr "Cảnh báo : Đang xóa cờ ảnh hưởng lẫn nhau của %B vì mã không ảnh hưởng lẫn nhau trong %B đã được liên kết với nó"
 
-#: elf32-arm.c:8205
-msgid "ERROR: %B uses VFP register arguments, %B does not"
-msgstr "LỖI: %B sử dụng các đối số thanh ghi VFP, còn %B thì không"
+#: elf32-arm.c:9652
+msgid "error: %B: Unknown CPU architecture"
+msgstr "lỗi: %B: không rõ kiến trúc CPU"
+
+#: elf32-arm.c:9690
+msgid "error: %B: Conflicting CPU architectures %d/%d"
+msgstr "lỗi: %B: Các kiến trúc CPU xung đột với nhau %d/%d"
 
-#: elf32-arm.c:8254
-msgid "ERROR: %B: Conflicting architecture profiles %c/%c"
-msgstr "LỖI: %B: Các hồ sơ kiến trúc xung đột với nhau %c/%c"
+#: elf32-arm.c:9747
+msgid "error: %B uses VFP register arguments, %B does not"
+msgstr "lỗi: %B sử dụng các đối số thanh ghi VFP, còn %B thì không"
 
-#: elf32-arm.c:8274
+#: elf32-arm.c:9897
+msgid "error: %B: Conflicting architecture profiles %c/%c"
+msgstr "lỗi: %B: Các hồ sơ kiến trúc xung đột với nhau %c/%c"
+
+#: elf32-arm.c:9921
 msgid "Warning: %B: Conflicting platform configuration"
 msgstr "Cảnh báo : %B: cấu trúc nền tảng xung đột"
 
-#: elf32-arm.c:8283
-msgid "ERROR: %B: Conflicting use of R9"
-msgstr "LỖI; %B: cách dùng R9 xung đột"
+#: elf32-arm.c:9930
+msgid "error: %B: Conflicting use of R9"
+msgstr "lỗi; %B: Dùng R9 một cách xung đột"
 
-#: elf32-arm.c:8295
-msgid "ERROR: %B: SB relative addressing conflicts with use of R9"
-msgstr "LỖI: %B: đạt địa chỉ tương đối SB xung đột với cách dùng R9"
+#: elf32-arm.c:9942
+msgid "error: %B: SB relative addressing conflicts with use of R9"
+msgstr "lỗi: %B: đạt địa chỉ tương đối SB cũng xung đột với cách dùng R9"
 
-#: elf32-arm.c:8318
+#: elf32-arm.c:9955
 msgid "warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"
 msgstr "cảnh báo : %B dùng wchar_t %u-byte, còn kết xuất nên dùng wchar_t %u-byte; vì vậy có thể không thành công dùng giá trị wchar_t qua các đối tượng"
 
-#: elf32-arm.c:8347
+#: elf32-arm.c:9986
 msgid "warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"
 msgstr "cảnh báo : %B dùng sự đếm %s, còn kết xuất nên dùng sự đếm %s; vì vậy có thể không thành công dùng giá trị đếm qua các đối tượng"
 
-#: elf32-arm.c:8360
-msgid "ERROR: %B uses iWMMXt register arguments, %B does not"
-msgstr "LỖI: %B sử dụng các đối số thanh ghi iWMMXt, còn %B thì không"
+#: elf32-arm.c:9998
+msgid "error: %B uses iWMMXt register arguments, %B does not"
+msgstr "lỗi: %B sử dụng các đối số thanh ghi iWMMXt, còn %B thì không"
+
+#: elf32-arm.c:10020
+msgid "error: fp16 format mismatch between %B and %B"
+msgstr "lỗi: định dạng fp16 không tương ứng giữa %B và %B"
 
-#: elf32-arm.c:8400
+#: elf32-arm.c:10063 elf32-arm.c:10156
+msgid "%B: Unknown mandatory EABI object attribute %d"
+msgstr "%B: Không rõ thuộc tính đối tượng EABI %d"
+
+#: elf32-arm.c:10071 elf32-arm.c:10164
 msgid "Warning: %B: Unknown EABI object attribute %d"
 msgstr "Cảnh báo : %B: Không rõ thuộc tính đối tượng EABI %d"
 
-#: elf32-arm.c:8460
-msgid "ERROR: %B is already in final BE8 format"
-msgstr "LỖI: %B đã theo định dạng BE8 cuối cùng"
+#: elf32-arm.c:10224
+msgid "error: %B is already in final BE8 format"
+msgstr "lỗi: %B đã theo định dạng BE8 cuối cùng"
 
-#: elf32-arm.c:8536
-msgid "ERROR: Source object %B has EABI version %d, but target %B has EABI version %d"
-msgstr "LỖI: Đối tượng nguồn %B có phiên bản EABI %d, nhưng đích %B có phiên bản EABI %d"
+#: elf32-arm.c:10300
+msgid "error: Source object %B has EABI version %d, but target %B has EABI version %d"
+msgstr "lỗi: Đối tượng nguồn %B có phiên bản EABI %d, còn đích %B có phiên bản EABI %d"
 
-#: elf32-arm.c:8552
-msgid "ERROR: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"
-msgstr "LỖI: %B được biên dịch cho APCS-%d, còn đích %B sử dụng APCS-%d"
+#: elf32-arm.c:10316
+msgid "error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"
+msgstr "lỗi: %B được biên dịch cho APCS-%d, còn đích %B sử dụng APCS-%d"
 
-#: elf32-arm.c:8577
-msgid "ERROR: %B uses VFP instructions, whereas %B does not"
-msgstr "LỖI: %B sử dụng các chỉ dẫn VFP, còn %B thì không"
+#: elf32-arm.c:10341
+msgid "error: %B uses VFP instructions, whereas %B does not"
+msgstr "lỗi: %B sử dụng chỉ dẫn VFP, còn %B thì không"
 
-#: elf32-arm.c:8581
-msgid "ERROR: %B uses FPA instructions, whereas %B does not"
-msgstr "LỖI: %B sử dụng các chỉ dẫn FPA, còn %B thì không"
+#: elf32-arm.c:10345
+msgid "error: %B uses FPA instructions, whereas %B does not"
+msgstr "lỗi: %B sử dụng chỉ dẫn FPA, còn %B thì không"
 
-#: elf32-arm.c:8591
-msgid "ERROR: %B uses Maverick instructions, whereas %B does not"
-msgstr "LỖI: %B sử dụng các chỉ dẫn Maverick, còn %B thì không"
+#: elf32-arm.c:10355
+msgid "error: %B uses Maverick instructions, whereas %B does not"
+msgstr "lỗi: %B sử dụng chỉ dẫn Maverick, còn %B thì không"
 
-#: elf32-arm.c:8595
-msgid "ERROR: %B does not use Maverick instructions, whereas %B does"
-msgstr "LỖI: %B không sử dụng các chỉ dẫn Maverick, còn %B thì có"
+#: elf32-arm.c:10359
+msgid "error: %B does not use Maverick instructions, whereas %B does"
+msgstr "lỗi: %B không sử dụng chỉ dẫn Maverick, còn %B thì có"
 
-#: elf32-arm.c:8614
-msgid "ERROR: %B uses software FP, whereas %B uses hardware FP"
-msgstr "LỖI: %B sử dụng FP phần mềm, còn %B sử dụng FP phần cứng"
+#: elf32-arm.c:10378
+msgid "error: %B uses software FP, whereas %B uses hardware FP"
+msgstr "lỗi: %B sử dụng FP phần mềm, còn %B sử dụng FP phần cứng"
 
-#: elf32-arm.c:8618
-msgid "ERROR: %B uses hardware FP, whereas %B uses software FP"
-msgstr "LỖI: %B sử dụng FP phần cứng, còn %B sử dụng FP phần mềm"
+#: elf32-arm.c:10382
+msgid "error: %B uses hardware FP, whereas %B uses software FP"
+msgstr "lỗi: %B sử dụng FP phần cứng, còn %B sử dụng FP phần mềm"
 
 #. Ignore init flag - it may not be set, despite the flags field
 #. containing valid data.
 #. Ignore init flag - it may not be set, despite the flags field containing valid data.
-#: elf32-arm.c:8665 elf32-bfin.c:4899 elf32-cris.c:3235 elf32-m68hc1x.c:1279
-#: elf32-m68k.c:774 elf32-score.c:3750 elf32-vax.c:538 elfxx-mips.c:12699
+#: elf32-arm.c:10429 elf32-bfin.c:5082 elf32-cris.c:4110 elf32-m68hc1x.c:1280
+#: elf32-m68k.c:1169 elf32-score.c:4039 elf32-score7.c:3876 elf32-vax.c:540
+#: elfxx-mips.c:12755
 #, c-format
 msgid "private flags = %lx:"
 msgstr "các cờ riêng = %lx:"
 
-#: elf32-arm.c:8674
+#: elf32-arm.c:10438
 #, c-format
 msgid " [interworking enabled]"
 msgstr " [ảnh hưởng lẫn nhau đã bật]"
 
-#: elf32-arm.c:8682
+#: elf32-arm.c:10446
 #, c-format
 msgid " [VFP float format]"
 msgstr " [Định dạng trôi VFP]"
 
-#: elf32-arm.c:8684
+#: elf32-arm.c:10448
 #, c-format
 msgid " [Maverick float format]"
 msgstr " [Định dạng trôi Maverick]"
 
-#: elf32-arm.c:8686
+#: elf32-arm.c:10450
 #, c-format
 msgid " [FPA float format]"
 msgstr " [Định dạng trôi FPA]"
 
-#: elf32-arm.c:8695
+#: elf32-arm.c:10459
 #, c-format
 msgid " [new ABI]"
 msgstr " [ABI mới]"
 
-#: elf32-arm.c:8698
+#: elf32-arm.c:10462
 #, c-format
 msgid " [old ABI]"
 msgstr " [ABI cũ]"
 
-#: elf32-arm.c:8701
+#: elf32-arm.c:10465
 #, c-format
 msgid " [software FP]"
 msgstr " [FP phần mềm]"
 
-#: elf32-arm.c:8710
+#: elf32-arm.c:10474
 #, c-format
 msgid " [Version1 EABI]"
 msgstr " [EABI phiên bản 1]"
 
-#: elf32-arm.c:8713 elf32-arm.c:8724
+#: elf32-arm.c:10477 elf32-arm.c:10488
 #, c-format
 msgid " [sorted symbol table]"
 msgstr " [bảng ký hiệu đã sắp xếp]"
 
-#: elf32-arm.c:8715 elf32-arm.c:8726
+#: elf32-arm.c:10479 elf32-arm.c:10490
 #, c-format
 msgid " [unsorted symbol table]"
 msgstr " [bảng ký hiệu chưa sắp xếp]"
 
-#: elf32-arm.c:8721
+#: elf32-arm.c:10485
 #, c-format
 msgid " [Version2 EABI]"
 msgstr " [EABI phiên bản 2]"
 
-#: elf32-arm.c:8729
+#: elf32-arm.c:10493
 #, c-format
 msgid " [dynamic symbols use segment index]"
 msgstr " [các ký hiệu động sử dụng chỉ mục đoạn]"
 
-#: elf32-arm.c:8732
+#: elf32-arm.c:10496
 #, c-format
 msgid " [mapping symbols precede others]"
 msgstr " [ký hiệu ánh xạ đứng trước]"
 
-#: elf32-arm.c:8739
+#: elf32-arm.c:10503
 #, c-format
 msgid " [Version3 EABI]"
 msgstr " [EABI phiên bản 3]"
 
-#: elf32-arm.c:8743
+#: elf32-arm.c:10507
 #, c-format
 msgid " [Version4 EABI]"
 msgstr " [EABI phiên bản 4]"
 
-#: elf32-arm.c:8747
+#: elf32-arm.c:10511
 #, c-format
 msgid " [Version5 EABI]"
 msgstr " [EABI phiên bản 5]"
 
-#: elf32-arm.c:8750
+#: elf32-arm.c:10514
 #, c-format
 msgid " [BE8]"
 msgstr " [BE8]"
 
-#: elf32-arm.c:8753
+#: elf32-arm.c:10517
 #, c-format
 msgid " [LE8]"
 msgstr " [LE8]"
 
-#: elf32-arm.c:8759
+#: elf32-arm.c:10523
 #, c-format
 msgid " <EABI version unrecognised>"
 msgstr "<Phiên bản EABI không được nhận ra>"
 
-#: elf32-arm.c:8766
+#: elf32-arm.c:10530
 #, c-format
 msgid " [relocatable executable]"
 msgstr " [tập tin có thể thực hiện và định vị lại]"
 
-#: elf32-arm.c:8769
+#: elf32-arm.c:10533
 #, c-format
 msgid " [has entry point]"
 msgstr " [có điểm vào]"
 
-#: elf32-arm.c:8774
+#: elf32-arm.c:10538
 #, c-format
 msgid "<Unrecognised flag bits set>"
 msgstr "<Các bit cờ không được nhận ra đã được đặt>"
 
-#: elf32-arm.c:9013 elf32-i386.c:1236 elf32-s390.c:1006 elf32-xtensa.c:999
-#: elf64-s390.c:961 elf64-x86-64.c:1016 elfxx-sparc.c:1127
+#: elf32-arm.c:10783 elf32-i386.c:1300 elf32-s390.c:998 elf32-xtensa.c:1000
+#: elf64-s390.c:952 elf64-x86-64.c:1082 elfxx-sparc.c:1121
 msgid "%B: bad symbol index: %d"
 msgstr "%B: chỉ mục ký hiệu sai: %d"
 
-#: elf32-arm.c:10125
+#: elf32-arm.c:10904 elf64-x86-64.c:1242 elf64-x86-64.c:1411 elfxx-mips.c:7870
+msgid "%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"
+msgstr "%B: định vị lại %s so với « %s » không thể được dùng khi tạo một đối tượng chia sẻ; hãy biên dịch lại với « -fPIC »"
+
+#: elf32-arm.c:11893
 #, c-format
 msgid "Errors encountered processing file %s"
 msgstr "Gặp lỗi khi xử lý tập tin %s"
 
-#: elf32-arm.c:11526 elf32-arm.c:11548
+#: elf32-arm.c:13339
+msgid "%B: error: Cortex-A8 erratum stub is allocated in unsafe location"
+msgstr "%B: lỗi: mẩu mục lỗi Cortex-A8 được cấp phát ở vị trí không an toàn"
+
+#. There's not much we can do apart from complain if this
+#. happens.
+#: elf32-arm.c:13366
+msgid "%B: error: Cortex-A8 erratum stub out of range (input file too large)"
+msgstr "%B: lỗi: mẩu mục lỗi Cortex-A8 ở ngoại phạm vi (tập tin nhập quá dài)"
+
+#: elf32-arm.c:13457 elf32-arm.c:13479
 msgid "%B: error: VFP11 veneer out of range"
 msgstr "%B: lỗi: lớp gỗ mặt VFP11 ở ngoại phạm vi"
 
-#: elf32-avr.c:1258 elf32-bfin.c:3222 elf32-cris.c:1546 elf32-fr30.c:624
+#: elf32-avr.c:1259 elf32-bfin.c:3208 elf32-cris.c:2097 elf32-fr30.c:624
 #: elf32-frv.c:4122 elf32-i860.c:1226 elf32-ip2k.c:1510 elf32-iq2000.c:699
-#: elf32-m32c.c:568 elf32-mep.c:549 elf32-msp430.c:501 elf32-mt.c:406
-#: elf32-openrisc.c:419 elf32-v850.c:1711 elf32-xstormy16.c:956
+#: elf32-m32c.c:568 elf32-mep.c:549 elf32-moxie.c:299 elf32-msp430.c:501
+#: elf32-mt.c:406 elf32-openrisc.c:419 elf32-v850.c:1709 elf32-xstormy16.c:956
 #: elf64-mmix.c:1541
 msgid "internal error: dangerous relocation"
 msgstr "lỗi nội bộ : định vị lại nguy hiểm"
 
-#: elf32-avr.c:2396 elf32-hppa.c:605 elf32-m68hc1x.c:164 elf64-ppc.c:3983
+#: elf32-avr.c:2409 elf32-hppa.c:605 elf32-m68hc1x.c:165 elf64-ppc.c:4141
 msgid "%B: cannot create stub entry %s"
 msgstr "%B: không thể tạo mục nhập mẩu %s"
 
-#: elf32-bfin.c:1585
+#: elf32-bfin.c:1581
 msgid "%B(%A+0x%lx): unresolvable relocation against symbol `%s'"
 msgstr "%B(%A+0x%lx): định vị lại không thể giải quyết đối với ký hiệu « %s »"
 
-#: elf32-bfin.c:1618 elf32-i386.c:3623 elf32-m68k.c:3557 elf32-s390.c:3110
-#: elf64-s390.c:3071 elf64-x86-64.c:3278
+#: elf32-bfin.c:1614 elf32-i386.c:4026 elf32-m68k.c:4176 elf32-s390.c:3067
+#: elf64-s390.c:3026 elf64-x86-64.c:3697
 msgid "%B(%A+0x%lx): reloc against `%s': error %d"
 msgstr "%B(%A+0x%lx): định vị lại đối với « %s »: lỗi %d"
 
-#: elf32-bfin.c:2711
+#: elf32-bfin.c:2714
 msgid "%B: relocation at `%A+0x%x' references symbol `%s' with nonzero addend"
 msgstr "%B: định vị lại ở « %A+0x%x » tham chiếu đến ký hiệu « %s » với số hạng khác không"
 
-#: elf32-bfin.c:2725 elf32-frv.c:2904
+#: elf32-bfin.c:2728 elf32-frv.c:2904
 msgid "relocation references symbol not defined in the module"
 msgstr "định vị lại tham chiếu đến ký hiệu không được định nghĩa trong mô-đun"
 
-#: elf32-bfin.c:2822
+#: elf32-bfin.c:2825
 msgid "R_BFIN_FUNCDESC references dynamic symbol with nonzero addend"
 msgstr "R_FRV_FUNCDESC tham chiếu đến ký hiệu động với số hạng khác không"
 
-#: elf32-bfin.c:2861 elf32-bfin.c:2987 elf32-frv.c:3641 elf32-frv.c:3762
+#: elf32-bfin.c:2866 elf32-bfin.c:2989 elf32-frv.c:3641 elf32-frv.c:3762
 msgid "cannot emit fixups in read-only section"
 msgstr "Không thể phát ra sự sửa chữa trong phần chỉ đọc"
 
-#: elf32-bfin.c:2889 elf32-bfin.c:3036 elf32-frv.c:3672 elf32-frv.c:3806
+#: elf32-bfin.c:2897 elf32-bfin.c:3027 elf32-frv.c:3672 elf32-frv.c:3806
+#: elf32-lm32.c:1104
 msgid "cannot emit dynamic relocations in read-only section"
 msgstr "không thể phát ra định vị lại động trong phần chỉ đọc"
 
-#: elf32-bfin.c:2945
+#: elf32-bfin.c:2947
 msgid "R_BFIN_FUNCDESC_VALUE references dynamic symbol with nonzero addend"
 msgstr "R_FRV_FUNCDESC_VALUE tham chiếu đến ký hiệu động với số hạng khác không"
 
-#: elf32-bfin.c:3126
+#: elf32-bfin.c:3112
 msgid "relocations between different segments are not supported"
 msgstr "không hỗ trợ định vị lại giữa các đoạn khác nhau"
 
-#: elf32-bfin.c:3127
+#: elf32-bfin.c:3113
 msgid "warning: relocation references a different segment"
 msgstr "cảnh báo : định vị lại tham chiếu đến một đoạn khác"
 
-#: elf32-bfin.c:4791 elf32-frv.c:6404
+#: elf32-bfin.c:4974 elf32-frv.c:6408
 msgid "%B: unsupported relocation type %i"
 msgstr "%B: kiểu định vị lại không được hỗ trợ %i"
 
-#: elf32-bfin.c:4944 elf32-frv.c:6812
+#: elf32-bfin.c:5127 elf32-frv.c:6816
 #, c-format
 msgid "%s: cannot link non-fdpic object file into fdpic executable"
 msgstr "%s: không thể liên kết tập tin đối tượng khác fdpic vào tập tin fdpic có thể thực hiện"
 
-#: elf32-bfin.c:4948 elf32-frv.c:6816
+#: elf32-bfin.c:5131 elf32-frv.c:6820
 #, c-format
 msgid "%s: cannot link fdpic object file into non-fdpic executable"
 msgstr "%s: không thể liên kết tập tin đối tượng khác fdpic vào tập tin khác fdpic có thể thực hiện"
 
-#: elf32-cris.c:1060
+#: elf32-cris.c:1169
 msgid "%B, section %A: unresolvable relocation %s against symbol `%s'"
 msgstr "%B, phần %A: định vị lại không thể giải quyết %s đối với ký hiệu « %s »"
 
-#: elf32-cris.c:1129
+#: elf32-cris.c:1238
 msgid "%B, section %A: No PLT nor GOT for relocation %s against symbol `%s'"
 msgstr "%B, phần %A: Không có PLT hoặc GOT cho định vị lại %s đối với ký hiệu « %s »"
 
-#: elf32-cris.c:1131
+#: elf32-cris.c:1240
 msgid "%B, section %A: No PLT for relocation %s against symbol `%s'"
 msgstr "%B, phần %A: Không có PLT cho định vị lại %s đối với ký hiệu « %s »"
 
-#: elf32-cris.c:1137 elf32-cris.c:1269
+#: elf32-cris.c:1246 elf32-cris.c:1379 elf32-cris.c:1641 elf32-cris.c:1730
+#: elf32-cris.c:1883
 msgid "[whose name is lost]"
 msgstr "[mất tên của ai]"
 
-#: elf32-cris.c:1255
+#: elf32-cris.c:1365
 msgid "%B, section %A: relocation %s with non-zero addend %d against local symbol"
 msgstr "%B, phần %A: định vị lại %s với số hạng khác không %d đối với ký hiệu cục bộ"
 
-#: elf32-cris.c:1263
+#: elf32-cris.c:1373 elf32-cris.c:1724 elf32-cris.c:1877
 msgid "%B, section %A: relocation %s with non-zero addend %d against symbol `%s'"
 msgstr "%B, phần %A: định vị lại %s với số hạng khác không %d đối với ký hiệu « %s »"
 
-#: elf32-cris.c:1289
+#: elf32-cris.c:1399
 msgid "%B, section %A: relocation %s is not allowed for global symbol: `%s'"
 msgstr "%B, phần %A: định vị lại %s không được phép cho ký hiệu toàn cục: « %s »"
 
-#: elf32-cris.c:1305
+#: elf32-cris.c:1415
 msgid "%B, section %A: relocation %s with no GOT created"
 msgstr "%B, phần %A: đã tạo định vị lại %s không có GOT"
 
-#: elf32-cris.c:1423
-msgid "%B: Internal inconsistency; no relocation section %s"
-msgstr "%s: Sự mâu thuẫn nội bộ ; không có phần định vị lại %s"
+#. We shouldn't get here for GCC-emitted code.
+#: elf32-cris.c:1632
+msgid "%B, section %A: relocation %s has an undefined reference to `%s', perhaps a declaration mixup?"
+msgstr "%B: phần %A: sự định vị lại $s có một thàm chiếu chưa xác định đến « %s », có thể khai báo không rõ ?"
+
+#: elf32-cris.c:2010
+msgid "%B, section %A: relocation %s is not allowed for symbol: `%s' which is defined outside the program, perhaps a declaration mixup?"
+msgstr "%B, phần %A: sự định vị lại %s không được phép cho ký hiệu « %s » mà được xác định bên ngoài chương trình, có thể khai báo không rõ ?"
 
-#: elf32-cris.c:2510
+#: elf32-cris.c:2063
+msgid "(too many global variables for -fpic: recompile with -fPIC)"
+msgstr "(quá nhiều biến toàn cục đối với « -fpic »: hãy biên dịch lại với « -fPIC »)"
+
+#: elf32-cris.c:2070
+msgid "(thread-local data too big for -fpic or -msmall-tls: recompile with -fPIC or -mno-small-tls)"
+msgstr "(dữ liệu cục bộ với mạch cũng quá lớn đối với « fpic » hoặc « -msmall-tls »: hãy biên dịch lại với « -fPIC » hay « -mno-small-tls »)"
+
+#: elf32-cris.c:3204
 msgid ""
 "%B, section %A:\n"
 "  v10/v32 compatible object %s must not contain a PIC relocation"
@@ -1269,46 +1338,62 @@ msgstr ""
 "%B, phần %A:\n"
 "  đối tượng tương thích v10/v32 %s không được chứa định vị lại PIC"
 
-#: elf32-cris.c:2697 elf32-cris.c:2765
+#: elf32-cris.c:3309
+msgid ""
+"%B, section %A:\n"
+"  relocation %s not valid in a shared object; typically an option mixup, recompile with -fPIC"
+msgstr ""
+"%B, phần %A:\n"
+"  không được sử dụng sự định vị lại %s trong một đối tượng chia sẻ; bình thường do khai báo không rõ, hãy biên dịch lại với « -fPIC »"
+
+#: elf32-cris.c:3523
 msgid ""
 "%B, section %A:\n"
 "  relocation %s should not be used in a shared object; recompile with -fPIC"
 msgstr ""
 "%B, phần %A:\n"
-"  không được sử dụng định vị lại %s trong một đối tượng chia sẻ; hãy biên dịch lại với -fPIC"
+"  không được sử dụng sự định vị lại %s trong một đối tượng chia sẻ; hãy biên dịch lại với « -fPIC »"
+
+#: elf32-cris.c:3940
+msgid ""
+"%B, section `%A', to symbol `%s':\n"
+"  relocation %s should not be used in a shared object; recompile with -fPIC"
+msgstr ""
+"%B, phần « %A », tới ký hiệu « %s »:\n"
+"  không được sử dụng sự định vị lại %s trong một đối tượng chia sẻ; hãy biên dịch lại với « -fPIC »"
 
-#: elf32-cris.c:3184
+#: elf32-cris.c:4059
 msgid "Unexpected machine number"
 msgstr "Số thứ tự máy bất thường"
 
-#: elf32-cris.c:3238
+#: elf32-cris.c:4113
 #, c-format
 msgid " [symbols have a _ prefix]"
 msgstr " [ký hiệu có một tiền tố _]"
 
-#: elf32-cris.c:3241
+#: elf32-cris.c:4116
 #, c-format
 msgid " [v10 and v32]"
 msgstr " [v10 và v32]"
 
-#: elf32-cris.c:3244
+#: elf32-cris.c:4119
 #, c-format
 msgid " [v32]"
 msgstr " [v32]"
 
-#: elf32-cris.c:3289
+#: elf32-cris.c:4164
 msgid "%B: uses _-prefixed symbols, but writing file with non-prefixed symbols"
 msgstr "%B: dùng ký hiệu tiền tố _, nhưng đang ghi tập tin với ký hiệu không phải tiền tố"
 
-#: elf32-cris.c:3290
+#: elf32-cris.c:4165
 msgid "%B: uses non-prefixed symbols, but writing file with _-prefixed symbols"
 msgstr "%B: dùng ký hiệu không phải tiền tố, nhưng đang ghi tập tin với ký hiệu có tiền tố _"
 
-#: elf32-cris.c:3309
+#: elf32-cris.c:4184
 msgid "%B contains CRIS v32 code, incompatible with previous objects"
 msgstr "%B chứa mã CRIS v32, không tương thích với các đối tượng trước"
 
-#: elf32-cris.c:3311
+#: elf32-cris.c:4186
 msgid "%B contains non-CRIS-v32 code, incompatible with previous objects"
 msgstr "%B chứa mã khác CRIS v32, không tương thích với các đối tượng trước"
 
@@ -1384,22 +1469,22 @@ msgstr "%B(%A+0x%lx): định vị lại đối với « %s »: %s"
 msgid "relocation references a different segment"
 msgstr "định vị lại tham chiếu đến một đoạn khác"
 
-#: elf32-frv.c:6726
+#: elf32-frv.c:6730
 #, c-format
 msgid "%s: compiled with %s and linked with modules that use non-pic relocations"
 msgstr "%s: biên dịch với %s và liên kết với môđun sử dụng định vị lại khác pic"
 
-#: elf32-frv.c:6779 elf32-iq2000.c:852 elf32-m32c.c:814
+#: elf32-frv.c:6783 elf32-iq2000.c:852 elf32-m32c.c:814
 #, c-format
 msgid "%s: compiled with %s and linked with modules compiled with %s"
 msgstr "%s: biên dịch với %s và liên kết với môđun biên dịch với %s"
 
-#: elf32-frv.c:6791
+#: elf32-frv.c:6795
 #, c-format
 msgid "%s: uses different unknown e_flags (0x%lx) fields than previous modules (0x%lx)"
 msgstr "%s: sử dụng trường e_flags không rõ (0x%lx) khác với mođun trước (0x%lx)"
 
-#: elf32-frv.c:6841 elf32-iq2000.c:889 elf32-m32c.c:850 elf32-mt.c:583
+#: elf32-frv.c:6845 elf32-iq2000.c:889 elf32-m32c.c:850 elf32-mt.c:583
 #, c-format
 msgid "private flags = 0x%lx:"
 msgstr "các cờ riêng = 0x%lx:"
@@ -1408,79 +1493,73 @@ msgstr "các cờ riêng = 0x%lx:"
 msgid "%B: Relocations in generic ELF (EM: %d)"
 msgstr "%B: Định vị lại trong ELF chung (EM: %d)"
 
-#: elf32-hppa.c:854 elf32-hppa.c:3600
+#: elf32-hppa.c:854 elf32-hppa.c:3570
 msgid "%B(%A+0x%lx): cannot reach %s, recompile with -ffunction-sections"
 msgstr "%B(%A+0x%lx): không thể tới %s, hãy biên dịch lại với « -ffunction-sections »"
 
-#: elf32-hppa.c:1263
+#: elf32-hppa.c:1286
 msgid "%B: relocation %s can not be used when making a shared object; recompile with -fPIC"
 msgstr "%B: không dùng được định vị lại %s khi tạo một đối tượng chia sẽ, hãy biên dịch lại với « -fPIC »"
 
-#: elf32-hppa.c:1518
-#, c-format
-msgid "Could not find relocation section for %s"
-msgstr "Không tìm thấy phần định vị lại cho %s"
-
-#: elf32-hppa.c:2810
+#: elf32-hppa.c:2780
 msgid "%B: duplicate export stub %s"
 msgstr "%B: mẩu xuất trùng %s"
 
-#: elf32-hppa.c:3436
+#: elf32-hppa.c:3406
 msgid "%B(%A+0x%lx): %s fixup for insn 0x%x is not supported in a non-shared link"
 msgstr "%B(%A+0x%lx): %s sự sửa chữa cho chỉ dẫn 0x%x không được hỗ trợ trong một liên kết không chia sẻ"
 
-#: elf32-hppa.c:4290
+#: elf32-hppa.c:4260
 msgid "%B(%A+0x%lx): cannot handle %s for %s"
 msgstr "%B(%A+0x%lx): không thể xử lý %s cho %s"
 
-#: elf32-hppa.c:4597
+#: elf32-hppa.c:4567
 msgid ".got section not immediately after .plt section"
 msgstr "Phần .got không nằm ngay sau phần .pit"
 
-#: elf32-i386.c:362 elf32-ppc.c:1616 elf32-s390.c:379 elf64-ppc.c:2153
-#: elf64-s390.c:403 elf64-x86-64.c:222
+#: elf32-i386.c:371 elf32-ppc.c:1666 elf32-s390.c:379 elf64-ppc.c:2283
+#: elf64-s390.c:403 elf64-x86-64.c:234
 msgid "%B: invalid relocation type %d"
 msgstr "%B: kiểu định vị lại không hợp lệ %d"
 
-#: elf32-i386.c:1183 elf64-x86-64.c:964
+#: elf32-i386.c:1246 elf64-x86-64.c:1029
 msgid "%B: TLS transition from %s to %s against `%s' at 0x%lx in section `%A' failed"
 msgstr "%B: không thành công chuyển tiếp TLS từ %s sang %s đối với « %s » ở 0x%lx trong phần « %A »"
 
-#: elf32-i386.c:1364 elf32-s390.c:1188 elf32-sh.c:5098 elf32-xtensa.c:1162
-#: elf64-s390.c:1152 elfxx-sparc.c:1263
+#: elf32-i386.c:1387 elf32-i386.c:2970 elf64-x86-64.c:1171 elf64-x86-64.c:2680
+msgid "%B: relocation %s against STT_GNU_IFUNC symbol `%s' isn't handled by %s"
+msgstr "%B: sự định vị lại %s đối với ký hiệu STT_GNU_IFUNC « %s » không phải được %s quản lý"
+
+#: elf32-i386.c:1548 elf32-s390.c:1180 elf32-sh.c:5065 elf32-xtensa.c:1173
+#: elf64-s390.c:1143 elfxx-sparc.c:1257
 msgid "%B: `%s' accessed both as normal and thread local symbol"
 msgstr "%B: đã truy cập « %s » theo ký hiệu cả hai kiểu bình thường và cục bộ cho mạch"
 
-#: elf32-i386.c:1479 elf32-s390.c:1297 elf64-ppc.c:5046 elf64-s390.c:1264
-#: elf64-x86-64.c:1299
-msgid "%B: bad relocation section name `%s'"
-msgstr "%B: tên phần định vị lại sai « %s »"
-
-#: elf32-i386.c:2598
+#: elf32-i386.c:2805
 msgid "%B: unrecognized relocation (0x%x) in section `%A'"
 msgstr "%B: định vị lại không được nhận ra (0x%x) trong phần « %A »"
 
-#: elf32-i386.c:2822 elf64-x86-64.c:2660
+#: elf32-i386.c:3219 elf64-x86-64.c:3081
 msgid "hidden symbol"
 msgstr "ký hiệu bị ẩn"
 
-#: elf32-i386.c:2825 elf64-x86-64.c:2663
+#: elf32-i386.c:3222 elf64-x86-64.c:3084
 msgid "internal symbol"
 msgstr "ký hiệu nội bộ"
 
-#: elf32-i386.c:2828 elf64-x86-64.c:2666
+#: elf32-i386.c:3225 elf64-x86-64.c:3087
 msgid "protected symbol"
 msgstr "ký hiệu bị bảo vệ"
 
-#: elf32-i386.c:2831 elf64-x86-64.c:2669
+#: elf32-i386.c:3228 elf64-x86-64.c:3090
 msgid "symbol"
 msgstr "ký hiệu"
 
-#: elf32-i386.c:2836
+#: elf32-i386.c:3233
 msgid "%B: relocation R_386_GOTOFF against undefined %s `%s' can not be used when making a shared object"
 msgstr "%B: không dùng được định vị lại R_386_GOTOFF đối với %s chưa xác định « %s » khi tạo một đối tượng chia sẻ"
 
-#: elf32-i386.c:2846
+#: elf32-i386.c:3243
 msgid "%B: relocation R_386_GOTOFF against protected function `%s' can not be used when making a shared object"
 msgstr "%B: không dùng được định vị lại R_386_GOTOFF đối với hàm số đã bảo vệ « %s » khi tạo một đối tượng chia sẻ"
 
@@ -1512,125 +1591,141 @@ msgstr "gặp định vị lại không được hỗ trợ giữa vùng địa
 msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)"
 msgstr "%s: sử dụng trường e_flags (0x%lx) khác với mo-đun trước (0x%lx)"
 
+#: elf32-lm32.c:698
+msgid "global pointer relative relocation when _gp not defined"
+msgstr "có định vị lại tương đối với con trỏ toàn cục khi chưa xác định _gp"
+
+#: elf32-lm32.c:753
+msgid "global pointer relative address out of range"
+msgstr "địa chỉ tương đối với con trỏ toàn cục vẫn ở ngoại phạm vi"
+
+#: elf32-lm32.c:1058
+msgid "internal error: addend should be zero for R_LM32_16_GOT"
+msgstr "lỗi nội bộ : phần cộng nên là số không cho R_LM32_16_GOT"
+
 #: elf32-m32r.c:1453
 msgid "SDA relocation when _SDA_BASE_ not defined"
 msgstr "định vị lại SDA khi chưa xác định _SDA_BASE_"
 
-#: elf32-m32r.c:3061
+#: elf32-m32r.c:3039
 msgid "%B: The target (%s) of an %s relocation is in the wrong section (%A)"
 msgstr "%B: Đích (%s) của một định vị lại %s nằm trong phần sai (%A)"
 
-#: elf32-m32r.c:3589
+#: elf32-m32r.c:3567
 msgid "%B: Instruction set mismatch with previous modules"
 msgstr "%B: Bộ chỉ dẫn không tương ứng với các mô-đun trước"
 
-#: elf32-m32r.c:3610
+#: elf32-m32r.c:3588
 #, c-format
 msgid "private flags = %lx"
 msgstr "các cờ riêng — %lx"
 
-#: elf32-m32r.c:3615
+#: elf32-m32r.c:3593
 #, c-format
 msgid ": m32r instructions"
 msgstr ": chỉ dẫn m32r"
 
-#: elf32-m32r.c:3616
+#: elf32-m32r.c:3594
 #, c-format
 msgid ": m32rx instructions"
 msgstr ": chỉ dẫn m32rx"
 
-#: elf32-m32r.c:3617
+#: elf32-m32r.c:3595
 #, c-format
 msgid ": m32r2 instructions"
 msgstr ": chỉ dẫn m32r2"
 
-#: elf32-m68hc1x.c:1047
+#: elf32-m68hc1x.c:1048
 #, c-format
 msgid "Reference to the far symbol `%s' using a wrong relocation may result in incorrect execution"
 msgstr "Tham chiếu đến ký hiệu ở xa « %s » khi sử dụng một định vị lại sai thì có thể dẫn đến sự thực hiện sai"
 
-#: elf32-m68hc1x.c:1070
+#: elf32-m68hc1x.c:1071
 #, c-format
 msgid "banked address [%lx:%04lx] (%lx) is not in the same bank as current banked address [%lx:%04lx] (%lx)"
 msgstr "địa chỉ đã đặt vào khối nhớ [%lx:%04lx] (%lx) không trong cùng khối nhớ với địa chỉ được đặt hiện thời vào khối nhớ [%lx:%04lx] (%lx)"
 
-#: elf32-m68hc1x.c:1089
+#: elf32-m68hc1x.c:1090
 #, c-format
 msgid "reference to a banked address [%lx:%04lx] in the normal address space at %04lx"
 msgstr "tham chiếu đến một địa chỉ đã đặt vào khối nhớ [%lx:%04lx] trong vùng địa chỉ thông thường tại %04lx"
 
-#: elf32-m68hc1x.c:1222
+#: elf32-m68hc1x.c:1223
 msgid "%B: linking files compiled for 16-bit integers (-mshort) and others for 32-bit integers"
 msgstr "%B: đang liên kết các tập tin được biên dịch cho số nguyên 16 bit (-mshort) và các tập tin khác cho số nguyên 32 bit"
 
-#: elf32-m68hc1x.c:1229
+#: elf32-m68hc1x.c:1230
 msgid "%B: linking files compiled for 32-bit double (-fshort-double) and others for 64-bit double"
 msgstr "%B: đang liên kết các tập tin được biên dịch 32 bit đôi (-mshort) và các tập tin khác cho 64 bit đôi"
 
-#: elf32-m68hc1x.c:1238
+#: elf32-m68hc1x.c:1239
 msgid "%B: linking files compiled for HCS12 with others compiled for HC12"
 msgstr "%B: đang liên kết tập tin được biên dịch cho HCS12 với các tập tin khác biên dịch cho HC12"
 
-#: elf32-m68hc1x.c:1254 elf32-ppc.c:4046 elf64-sparc.c:697 elfxx-mips.c:12561
+#: elf32-m68hc1x.c:1255 elf32-ppc.c:4255 elf64-sparc.c:698 elfxx-mips.c:12617
 msgid "%B: uses different e_flags (0x%lx) fields than previous modules (0x%lx)"
 msgstr "%B: sử dụng trường e_flags (0x%lx) khác với mo-đun trước (0x%lx)"
 
-#: elf32-m68hc1x.c:1282
+#: elf32-m68hc1x.c:1283
 #, c-format
 msgid "[abi=32-bit int, "
 msgstr "[abi=số nguyên 32-bit, "
 
-#: elf32-m68hc1x.c:1284
+#: elf32-m68hc1x.c:1285
 #, c-format
 msgid "[abi=16-bit int, "
 msgstr "[abi=số nguyên 16-bit, "
 
-#: elf32-m68hc1x.c:1287
+#: elf32-m68hc1x.c:1288
 #, c-format
 msgid "64-bit double, "
 msgstr "64-bit đôi, "
 
-#: elf32-m68hc1x.c:1289
+#: elf32-m68hc1x.c:1290
 #, c-format
 msgid "32-bit double, "
 msgstr "32-bit đôi, "
 
-#: elf32-m68hc1x.c:1292
+#: elf32-m68hc1x.c:1293
 #, c-format
 msgid "cpu=HC11]"
 msgstr "cpu=HC11]"
 
-#: elf32-m68hc1x.c:1294
+#: elf32-m68hc1x.c:1295
 #, c-format
 msgid "cpu=HCS12]"
 msgstr "cpu=HCS12]"
 
-#: elf32-m68hc1x.c:1296
+#: elf32-m68hc1x.c:1297
 #, c-format
 msgid "cpu=HC12]"
 msgstr "cpu=HC12]"
 
-#: elf32-m68hc1x.c:1299
+#: elf32-m68hc1x.c:1300
 #, c-format
 msgid " [memory=bank-model]"
 msgstr " [bộ nhớ=chế độ khối]"
 
-#: elf32-m68hc1x.c:1301
+#: elf32-m68hc1x.c:1302
 #, c-format
 msgid " [memory=flat]"
 msgstr " [bộ nhớ=phẳng]"
 
-#: elf32-m68k.c:789 elf32-m68k.c:790
+#: elf32-m68k.c:1184 elf32-m68k.c:1185
 msgid "unknown"
 msgstr "không rõ"
 
-#: elf32-m68k.c:1216
-msgid "%B: GOT overflow: Number of R_68K_GOT8O relocations > %d"
-msgstr "%B: tràn GOT: số các bố trí lại kiểu R_68K_GOT8O > %d"
+#: elf32-m68k.c:1645
+msgid "%B: GOT overflow: Number of relocations with 8-bit offset > %d"
+msgstr "%B: tràn GOT: số các sự định vị lại với hiệu 8-bit  > %d"
+
+#: elf32-m68k.c:1651
+msgid "%B: GOT overflow: Number of relocations with 8- or 16-bit offset > %d"
+msgstr "%B: tràn GOT: số các sự định vị lại với hiệu 8-bit hay 16-bit  > %d"
 
-#: elf32-m68k.c:1221
-msgid "%B: GOT overflow: Number of R_68K_GOT8O and R_68K_GOT16O relocations > %d"
-msgstr "%B: tràn GOT: số các bố trí lại kiểu R_68K_GOT8O và R_68K_GOT16O > %d"
+#: elf32-m68k.c:3902
+msgid "%B(%A+0x%lx): R_68K_TLS_LE32 relocation not permitted in shared object"
+msgstr "%B(%A+0x%lx): R_68K_TLS_LE32 không cho phép định vị lại trong đối tượng chia sẻ"
 
 #: elf32-mcore.c:99 elf32-mcore.c:442
 msgid "%B: Relocation %s (%d) is not currently supported.\n"
@@ -1648,147 +1743,187 @@ msgstr "%B và %B dành cho lõi khác nhau"
 msgid "%B and %B are for different configurations"
 msgstr "%B và %B dành cho cấu hình khác nhau"
 
-#: elf32-mep.c:709
+#: elf32-mep.c:708
 #, c-format
 msgid "private flags = 0x%lx"
 msgstr "các cờ riêng = 0x%lx"
 
-#: elf32-mips.c:1045 elf64-mips.c:2056 elfn32-mips.c:1888
+#: elf32-microblaze.c:737
+#, c-format
+msgid "%s: unknown relocation type %d"
+msgstr "%s: không rõ loại định vị lại %d"
+
+#: elf32-microblaze.c:862 elf32-microblaze.c:907
+#, c-format
+msgid "%s: The target (%s) of an %s relocation is in the wrong section (%s)"
+msgstr "%s: Đích (%s) của một sự định vị lại %s nằm trong phần không đúng (%s)"
+
+#: elf32-microblaze.c:1150 elfxx-sparc.c:2957
+msgid "%B: probably compiled without -fPIC?"
+msgstr "%B: rất có thể được biên dịch không có « -fPIC » ?"
+
+#: elf32-microblaze.c:2086 elflink.c:12444
+msgid "%B: bad relocation section name `%s'"
+msgstr "%B: tên phần định vị lại sai « %s »"
+
+#: elf32-mips.c:1045 elf64-mips.c:2083 elfn32-mips.c:1888
 msgid "literal relocation occurs for an external symbol"
 msgstr "định vị lại nghĩa chữ xảy ra cho một ký hiệu bên ngoài"
 
-#: elf32-mips.c:1085 elf32-score.c:484 elf64-mips.c:2099 elfn32-mips.c:1929
+#: elf32-mips.c:1085 elf32-score.c:580 elf32-score7.c:480 elf64-mips.c:2126
+#: elfn32-mips.c:1929
 msgid "32bits gp relative relocation occurs for an external symbol"
 msgstr "định vị lại tương đối 32-bit gp xảy ra cho một ký hiệu bên ngoài"
 
-#: elf32-ppc.c:1681
+#: elf32-ppc.c:1731
 #, c-format
 msgid "generic linker can't handle %s"
 msgstr "trình liên kết chung không thể xử lý %s"
 
-#: elf32-ppc.c:2161
+#: elf32-ppc.c:2211
 msgid "corrupt or empty %s section in %B"
 msgstr "Gặp phần %s bị hỏng hoặc còn rỗng trong %B"
 
-#: elf32-ppc.c:2168
+#: elf32-ppc.c:2218
 msgid "unable to read in %s section from %B"
 msgstr "không thể đọc trong phần %s từ %B"
 
-#: elf32-ppc.c:2174
+#: elf32-ppc.c:2224
 msgid "corrupt %s section in %B"
 msgstr "phần %s bị hỏng trong %b"
 
-#: elf32-ppc.c:2217
+#: elf32-ppc.c:2267
 msgid "warning: unable to set size of %s section in %B"
 msgstr "cảnh báo : không thể đặt kích cỡ của phần %s trong %B"
 
-#: elf32-ppc.c:2265
+#: elf32-ppc.c:2315
 msgid "failed to allocate space for new APUinfo section."
 msgstr "lỗi cấp phát sức chứa cho phần thông tin APUinfo mới."
 
-#: elf32-ppc.c:2284
+#: elf32-ppc.c:2334
 msgid "failed to compute new APUinfo section."
 msgstr "lỗi tính phần thông tin APUinfo mới."
 
-#: elf32-ppc.c:2287
+#: elf32-ppc.c:2337
 msgid "failed to install new APUinfo section."
 msgstr "lỗi cài đặt phần thông tin APUinfo mới."
 
-#: elf32-ppc.c:3263
+#: elf32-ppc.c:3364
 msgid "%B: relocation %s cannot be used when making a shared object"
 msgstr "%B: không dùng được định vị lại %s khi tạo một đối tượng chia sẻ"
 
 #. It does not make sense to have a procedure linkage
 #. table entry for a local symbol.
-#: elf32-ppc.c:3534
+#: elf32-ppc.c:3723
 msgid "%B(%A+0x%lx): %s reloc against local symbol"
 msgstr "%B(%A+0x%lx): %s định vị lại đối với ký hiệu cục bộ"
 
-#: elf32-ppc.c:3885 elf32-ppc.c:3900 elfxx-mips.c:12268 elfxx-mips.c:12294
-#: elfxx-mips.c:12316 elfxx-mips.c:12342
+#: elf32-ppc.c:4067 elf32-ppc.c:4082 elfxx-mips.c:12324 elfxx-mips.c:12350
+#: elfxx-mips.c:12372 elfxx-mips.c:12398
 msgid "Warning: %B uses hard float, %B uses soft float"
 msgstr "Cảnh báo : %B dùng trôi cứng, còn %B dùng trôi mềm"
 
-#: elf32-ppc.c:3888 elf32-ppc.c:3892
+#: elf32-ppc.c:4070 elf32-ppc.c:4074
 msgid "Warning: %B uses double-precision hard float, %B uses single-precision hard float"
 msgstr "Cảnh báo : %B dùng trôi cứng chính xác đôi, còn %B dùng trôi cứng chính xác đơn"
 
-#: elf32-ppc.c:3896
+#: elf32-ppc.c:4078
 msgid "Warning: %B uses soft float, %B uses single-precision hard float"
 msgstr "Cảnh báo : %B dùng trôi mềm, còn %B dùng trôi cứng chính xác đơn"
 
-#: elf32-ppc.c:3903 elf32-ppc.c:3907 elfxx-mips.c:12248 elfxx-mips.c:12252
+#: elf32-ppc.c:4085 elf32-ppc.c:4089 elfxx-mips.c:12304 elfxx-mips.c:12308
 msgid "Warning: %B uses unknown floating point ABI %d"
 msgstr "Cảnh báo : %B dùng điểm trôi không rõ ABI %d"
 
-#: elf32-ppc.c:3949 elf32-ppc.c:3953
+#: elf32-ppc.c:4131 elf32-ppc.c:4135
 msgid "Warning: %B uses unknown vector ABI %d"
 msgstr "Cảnh báo : %B dùng véc-tơ không nhận ra ABI %d"
 
-#: elf32-ppc.c:3957
+#: elf32-ppc.c:4139
 msgid "Warning: %B uses vector ABI \"%s\", %B uses \"%s\""
 msgstr "Cảnh báo : %B dùng véc-tơ ABI « %s », còn %B dùng « %s »"
 
-#: elf32-ppc.c:4011
+#: elf32-ppc.c:4156 elf32-ppc.c:4159
+msgid "Warning: %B uses r3/r4 for small structure returns, %B uses memory"
+msgstr "Cảnh báo : %B dùng r3/r4 để trả lại cấu trúc nhỏ, %B dùng phần nhớ"
+
+#: elf32-ppc.c:4162 elf32-ppc.c:4166
+msgid "Warning: %B uses unknown small structure return convention %d"
+msgstr "Cảnh báo : %B dùng quy ước trả lại cấu trúc nhỏ không rõ %d"
+
+#: elf32-ppc.c:4220
 msgid "%B: compiled with -mrelocatable and linked with modules compiled normally"
 msgstr "%B: đã biên dịch với « -mrelocatable » và đã liên kết với các môđun biên dịch bình thường"
 
-#: elf32-ppc.c:4019
+#: elf32-ppc.c:4228
 msgid "%B: compiled normally and linked with modules compiled with -mrelocatable"
 msgstr "%B: đã biên dịch bình thường và đã liên kết với các môđun biên dịch với « -mrelocatable »"
 
-#: elf32-ppc.c:4105
+#: elf32-ppc.c:4314
 msgid "Using bss-plt due to %B"
 msgstr "Đang dùng biss-pit do %B"
 
-#: elf32-ppc.c:6418 elf64-ppc.c:10881
+#: elf32-ppc.c:7056 elf64-ppc.c:11364
 msgid "%B: unknown relocation type %d for symbol %s"
 msgstr "%B: không rõ kiểu định vị lại %d cho ký hiệu %s"
 
-#: elf32-ppc.c:6668
+#: elf32-ppc.c:7316
 msgid "%B(%A+0x%lx): non-zero addend on %s reloc against `%s'"
 msgstr "%B(%A+0x%lx): số hạng khác không trên định vị lại %s đối với « %s »"
 
-#: elf32-ppc.c:7024 elf32-ppc.c:7050 elf32-ppc.c:7109
+#: elf32-ppc.c:7499 elf64-ppc.c:11854
+msgid "%B(%A+0x%lx): relocation %s for indirect function %s unsupported"
+msgstr "%B(%A+0x%lx): không hỗ trợ sự định vị lại %s cho hàm gián tiếp %s"
+
+#: elf32-ppc.c:7709 elf32-ppc.c:7736 elf32-ppc.c:7787
 msgid "%B: the target (%s) of a %s relocation is in the wrong output section (%s)"
 msgstr "%B: đích (%s) của một định vị lại %s nằm trong phần kết xuất không đúng (%s)"
 
-#: elf32-ppc.c:7164
+#: elf32-ppc.c:7847
 msgid "%B: relocation %s is not yet supported for symbol %s."
 msgstr "%B: định vị lại %s chưa được hỗ trợ cho ký hiệu %s."
 
-#: elf32-ppc.c:7272 elf64-ppc.c:11575
+#: elf32-ppc.c:7955 elf64-ppc.c:12110
 msgid "%B(%A+0x%lx): %s reloc against `%s': error %d"
 msgstr "%B(%A+0x%lx): %s định vị lại đối với « %s »: lỗi %d"
 
-#: elf32-s390.c:2246 elf64-s390.c:2220
+#: elf32-ppc.c:8423
+#, c-format
+msgid "%s not defined in linker created %s"
+msgstr "%s chưa được xác định trong bộ liên kết được tạo %s"
+
+#: elf32-s390.c:2207 elf64-s390.c:2179
 msgid "%B(%A+0x%lx): invalid instruction for TLS relocation %s"
 msgstr "%B(%A+0x%lx): chỉ dẫn không hợp lệ cho định vị lại TLS %s"
 
-#: elf32-score.c:1415 elfxx-mips.c:3273
+#: elf32-score.c:1533 elf32-score7.c:1424 elfxx-mips.c:3299
 msgid "not enough GOT space for local GOT entries"
 msgstr "không đủ sức chứa GOT cho các mục nhập GOT cục bộ"
 
-#: elf32-score.c:2545
+#: elf32-score.c:2765
+msgid "address not word align"
+msgstr "địa chỉ không sắp hàng từ"
+
+#: elf32-score.c:2850 elf32-score7.c:2685
 #, c-format
 msgid "%s: Malformed reloc detected for section %s"
 msgstr "%s: định vị lại dạng sai được phát hiện cho phần %s"
 
-#: elf32-score.c:2596
+#: elf32-score.c:2901 elf32-score7.c:2736
 msgid "%B: CALL15 reloc at 0x%lx not against global symbol"
 msgstr "%B: CALL15 định vị lại tại 0x%lx không phải so với ký hiệu toàn cục"
 
-#: elf32-score.c:3753
+#: elf32-score.c:4042 elf32-score7.c:3879
 #, c-format
 msgid " [pic]"
-msgstr " [pic]"
+msgstr " [ảnh]"
 
-#: elf32-score.c:3757
+#: elf32-score.c:4046 elf32-score7.c:3883
 #, c-format
 msgid " [fix dep]"
 msgstr " [sửa quan hệ phụ thuộc]"
 
-#: elf32-score.c:3799
+#: elf32-score.c:4088 elf32-score7.c:3925
 msgid "%B: warning: linking PIC files with non-PIC files"
 msgstr "%B: cảnh báo : đang liên kết tập tin PIC với tập tin khác PIC"
 
@@ -1800,7 +1935,7 @@ msgstr "%B: chỉ thị IMPORT AS (nhập dạng) cho %s cũng ẩn chỉ thị
 msgid "%B: Unrecognised .directive command: %s"
 msgstr "%B: Không nhận ra câu lệnh .directive: %s"
 
-#: elf32-sh-symbian.c:504
+#: elf32-sh-symbian.c:503
 msgid "%B: Failed to add renamed symbol %s"
 msgstr "%B: Lỗi thêm ký hiệu đã đặt tên lại %s"
 
@@ -1836,46 +1971,46 @@ msgstr "%B: 0x%lx: cảnh báo : đếm sai"
 msgid "%B: 0x%lx: fatal: reloc overflow while relaxing"
 msgstr "%B: 0x%lx: lỗi nặng: tràn định vị lại trong khi giảm nhẹ"
 
-#: elf32-sh.c:3279 elf64-sh64.c:1526
+#: elf32-sh.c:3270 elf64-sh64.c:1526
 msgid "Unexpected STO_SH5_ISA32 on local symbol is not handled"
 msgstr "Không xử lý được STO_SH5_ISA32 không mong đợi trên ký hiệu cục bộ"
 
-#: elf32-sh.c:3516
+#: elf32-sh.c:3507
 msgid "%B: 0x%lx: fatal: unaligned branch target for relax-support relocation"
 msgstr "%B: 0x%lx: lỗi nặng: có đích nhánh chưa sắp hàng cho định vị lại hỗ trợ giảm nhẹ"
 
-#: elf32-sh.c:3549 elf32-sh.c:3564
+#: elf32-sh.c:3540 elf32-sh.c:3555
 msgid "%B: 0x%lx: fatal: unaligned %s relocation 0x%lx"
 msgstr "%B: 0x%lx: lỗi nặng: định vị lại %s chưa sắp hàng 0x%lx"
 
-#: elf32-sh.c:3578
+#: elf32-sh.c:3569
 msgid "%B: 0x%lx: fatal: R_SH_PSHA relocation %d not in range -32..32"
 msgstr "%B: 0x%lx: lỗi nặng: R_SH_PSHA định vị lại %d không nằm trong phạm vi -32..32"
 
-#: elf32-sh.c:3592
+#: elf32-sh.c:3583
 msgid "%B: 0x%lx: fatal: R_SH_PSHL relocation %d not in range -32..32"
 msgstr "%B: 0x%lx: lỗi nặng: R_SH_PSHL định vị lại %d không nằm trong phạm vi -32..32"
 
-#: elf32-sh.c:5310 elf64-alpha.c:4552
+#: elf32-sh.c:5256 elf64-alpha.c:4525
 msgid "%B: TLS local exec code cannot be linked into shared objects"
 msgstr "%B: mã thực hiện cục bộ TLS không thể được liên kết vào đối tượng chia sẻ"
 
-#: elf32-sh64.c:222 elf64-sh64.c:2345
+#: elf32-sh64.c:222 elf64-sh64.c:2333
 #, c-format
 msgid "%s: compiled as 32-bit object and %s is 64-bit"
 msgstr "%s: biên dịch như một đối tượng 32-bit và %s là 64-bit"
 
-#: elf32-sh64.c:225 elf64-sh64.c:2348
+#: elf32-sh64.c:225 elf64-sh64.c:2336
 #, c-format
 msgid "%s: compiled as 64-bit object and %s is 32-bit"
 msgstr "%s: biên dịch như một đối tượng 64-bit và %s là 32-bit"
 
-#: elf32-sh64.c:227 elf64-sh64.c:2350
+#: elf32-sh64.c:227 elf64-sh64.c:2338
 #, c-format
 msgid "%s: object size does not match that of target %s"
 msgstr "%s: kích cỡ đối tượng không tương ứng với kích cỡ của đích %s"
 
-#: elf32-sh64.c:450 elf64-sh64.c:2888
+#: elf32-sh64.c:450 elf64-sh64.c:2852
 #, c-format
 msgid "%s: encountered datalabel symbol in input"
 msgstr "%s: gặp ký hiệu nhãn dữ liệu trong dữ liệu nhập vào"
@@ -1915,103 +2050,119 @@ msgstr "%B: được biên dịch cho hệ thống 64-bit, còn đích là 32-bi
 msgid "%B: linking little endian files with big endian files"
 msgstr "%B: đang liên kết tập tin về cuối nhỏ với tập tin về cuối lớn"
 
-#: elf32-spu.c:607
+#: elf32-spu.c:723
+msgid "%X%P: overlay section %A does not start on a cache line.\n"
+msgstr "%X%P: phần phủ %A không bắt đầu ở một dòng nhớ tạm.\n"
+
+#: elf32-spu.c:731
+msgid "%X%P: overlay section %A is larger than a cache line.\n"
+msgstr "%X%P: phần phủ %A lớn hơn một dòng nhớ tạm.\n"
+
+#: elf32-spu.c:751
+msgid "%X%P: overlay section %A is not in cache area.\n"
+msgstr "%X%P: phần phủ %A không phải trong vùng nhớ tạm.\n"
+
+#: elf32-spu.c:791
 msgid "%X%P: overlay sections %A and %A do not start at the same address.\n"
 msgstr "%X%P: hai phần phủ %A và %A không bắt đầu ở cùng một địa chỉ.\n"
 
-#: elf32-spu.c:805
+#: elf32-spu.c:1015
 msgid "warning: call to non-function symbol %s defined in %B"
 msgstr "cảnh báo : cuộc gọi ký hiệu khác hàm %s được xác định trong %B"
 
-#: elf32-spu.c:1406
+#: elf32-spu.c:1365
+msgid "%A:0x%v lrlive .brinfo (%u) differs from analysis (%u)\n"
+msgstr "%A:0x%v lrlive .brinfo (%u) khác với phân tích (%u)\n"
+
+#: elf32-spu.c:1884
 msgid "%B is not allowed to define %s"
 msgstr "không cho phép %B xác định %s"
 
-#: elf32-spu.c:1453
+#: elf32-spu.c:1892
+#, c-format
+msgid "you are not allowed to define %s in a script"
+msgstr "không cho phép bạn xác định %s trong một văn lệnh"
+
+#: elf32-spu.c:1926
 #, c-format
 msgid "%s in overlay section"
 msgstr "%s trong phần phủ"
 
-#: elf32-spu.c:1469
+#: elf32-spu.c:1955
 msgid "overlay stub relocation overflow"
 msgstr "tràn định vị lại mẩu phủ"
 
-#: elf32-spu.c:1478 elf64-ppc.c:10078
+#: elf32-spu.c:1964 elf64-ppc.c:10441
 msgid "stubs don't match calculated size"
 msgstr "các mẩu không tương ứng với kích cỡ đã tính"
 
-#: elf32-spu.c:1976
+#: elf32-spu.c:2546
 #, c-format
 msgid "warning: %s overlaps %s\n"
 msgstr "cảnh báo : %s đè lên %s\n"
 
-#: elf32-spu.c:1992
+#: elf32-spu.c:2562
 #, c-format
 msgid "warning: %s exceeds section size\n"
 msgstr "cảnh báo : %s vượt quá kích cỡ phần\n"
 
-#: elf32-spu.c:2023
+#: elf32-spu.c:2593
 msgid "%A:0x%v not found in function table\n"
 msgstr "%A:0x%v không tìm thấy trong bảng hàm\n"
 
-#: elf32-spu.c:2165
+#: elf32-spu.c:2740
 msgid "%B(%A+0x%v): call to non-code section %B(%A), analysis incomplete\n"
 msgstr "%B(%A+0x%v): gọi phần khác mã %B(%A), chưa phân tích hoàn toàn\n"
 
-#: elf32-spu.c:2339
-#, c-format
-msgid "%A link_order not found\n"
-msgstr "%A link_order không tìm thấy\n"
-
-#: elf32-spu.c:2706
+#: elf32-spu.c:3297
 #, c-format
 msgid "Stack analysis will ignore the call from %s to %s\n"
 msgstr "Tiến trình phân tích đống sẽ bỏ qua cuộc gọi từ %s cho %s\n"
 
-#: elf32-spu.c:3348
+#: elf32-spu.c:3988
 msgid "  %s: 0x%v\n"
 msgstr "  %s: 0x%v\n"
 
-#: elf32-spu.c:3349
+#: elf32-spu.c:3989
 msgid "%s: 0x%v 0x%v\n"
 msgstr "%s: 0x%v 0x%v\n"
 
-#: elf32-spu.c:3354
+#: elf32-spu.c:3994
 msgid "  calls:\n"
 msgstr "  cuộc gọi:\n"
 
-#: elf32-spu.c:3362
+#: elf32-spu.c:4002
 #, c-format
 msgid "   %s%s %s\n"
 msgstr "   %s%s %s\n"
 
-#: elf32-spu.c:3564
+#: elf32-spu.c:4304
 #, c-format
 msgid "%s duplicated in %s\n"
 msgstr "%s bị nhân đôi trong %s\n"
 
-#: elf32-spu.c:3568
+#: elf32-spu.c:4308
 #, c-format
 msgid "%s duplicated\n"
 msgstr "%s bị nhân đôi\n"
 
-#: elf32-spu.c:3575
+#: elf32-spu.c:4315
 msgid "sorry, no support for duplicate object files in auto-overlay script\n"
 msgstr "tiếc là văn lệnh tự động phủ không hỗ trợ tập tin đối tượng tăng đôi\n"
 
-#: elf32-spu.c:3605
+#: elf32-spu.c:4356
 msgid "non-overlay size of 0x%v plus maximum overlay size of 0x%v exceeds local store\n"
 msgstr "kích cỡ khác phủ 0x%v cộng với kích cỡ phủ tối đa 0x%v thì vượt quá kho cục bộ\n"
 
-#: elf32-spu.c:3741
+#: elf32-spu.c:4512
 msgid "%B:%A%s exceeds overlay size\n"
 msgstr "%B:%A%s vượt quá kích cỡ phủ\n"
 
-#: elf32-spu.c:3862
+#: elf32-spu.c:4669
 msgid "Stack size for call graph root nodes.\n"
 msgstr "Kích cỡ đống cho các nút thông tin gốc đồ thị cuộc gọi.\n"
 
-#: elf32-spu.c:3863
+#: elf32-spu.c:4670
 msgid ""
 "\n"
 "Stack size for functions.  Annotations: '*' max stack, 't' tail call\n"
@@ -2021,164 +2172,168 @@ msgstr ""
 " *\tđống tối đa\n"
 " t\tcuộc gọi đuôi\n"
 
-#: elf32-spu.c:3871
+#: elf32-spu.c:4680
 msgid "Maximum stack required is 0x%v\n"
 msgstr "Đống tối đa cần thiết là 0x%v\n"
 
-#: elf32-spu.c:4067
+#: elf32-spu.c:4771
+msgid "fatal error while creating .fixup"
+msgstr "gặp lỗi nghiêm trọng trong khi tạo .fixup"
+
+#: elf32-spu.c:5009
 msgid "%B(%s+0x%lx): unresolvable %s relocation against symbol `%s'"
 msgstr "%B(%s+0x%lx): không thể giải quyết định vị lại %s so với ký hiệu « %s »"
 
-#: elf32-v850.c:165
+#: elf32-v850.c:163
 #, c-format
 msgid "Variable `%s' cannot occupy in multiple small data regions"
 msgstr "Biến « %s » không thể chiếm nhiều vùng dữ liệu nhỏ"
 
-#: elf32-v850.c:168
+#: elf32-v850.c:166
 #, c-format
 msgid "Variable `%s' can only be in one of the small, zero, and tiny data regions"
 msgstr "Biến « %s » chỉ có thể nằm trong một của vùng dữ liệu kiểu nhỏ, số không và rất nhỏ"
 
-#: elf32-v850.c:171
+#: elf32-v850.c:169
 #, c-format
 msgid "Variable `%s' cannot be in both small and zero data regions simultaneously"
 msgstr "Biến « %s » không thể nằm đồng thời trong cả hai vùng dữ liệu kiểu nhỏ và số không"
 
-#: elf32-v850.c:174
+#: elf32-v850.c:172
 #, c-format
 msgid "Variable `%s' cannot be in both small and tiny data regions simultaneously"
 msgstr "Biến « %s » không thể nằm đồng thời trong cả hai vùng dữ liệu kiểu nhỏ và rất nhỏ"
 
-#: elf32-v850.c:177
+#: elf32-v850.c:175
 #, c-format
 msgid "Variable `%s' cannot be in both zero and tiny data regions simultaneously"
 msgstr "Biến « %s » không thể nằm đồng thời trong cả hai vùng dữ liệu kiểu rất nhỏ và số không"
 
-#: elf32-v850.c:480
+#: elf32-v850.c:478
 #, c-format
 msgid "FAILED to find previous HI16 reloc\n"
 msgstr "LỖI tìm định vị lại HI16 trước\n"
 
-#: elf32-v850.c:1715
+#: elf32-v850.c:1713
 msgid "could not locate special linker symbol __gp"
 msgstr "không tìm thấy ký hiệu liên kết đặc biệt __gp"
 
-#: elf32-v850.c:1719
+#: elf32-v850.c:1717
 msgid "could not locate special linker symbol __ep"
 msgstr "không tìm thấy ký hiệu liên kết đặc biệt __ep"
 
-#: elf32-v850.c:1723
+#: elf32-v850.c:1721
 msgid "could not locate special linker symbol __ctbp"
 msgstr "không tìm thấy ký hiệu liên kết đặc biệt __ctbp"
 
-#: elf32-v850.c:1873
+#: elf32-v850.c:1871
 msgid "%B: Architecture mismatch with previous modules"
 msgstr "%B: sai khớp kiến trúc với mô-đun khác"
 
-#: elf32-v850.c:1892
+#: elf32-v850.c:1890
 #, c-format
 msgid "private flags = %lx: "
 msgstr "các cờ riêng — %lx: "
 
-#: elf32-v850.c:1897
+#: elf32-v850.c:1895
 #, c-format
 msgid "v850 architecture"
 msgstr "Kiến trúc v850"
 
-#: elf32-v850.c:1898
+#: elf32-v850.c:1896
 #, c-format
 msgid "v850e architecture"
 msgstr "Kiến trúc v850e"
 
-#: elf32-v850.c:1899
+#: elf32-v850.c:1897
 #, c-format
 msgid "v850e1 architecture"
 msgstr "Kiến trúc v850e1"
 
-#: elf32-vax.c:541
+#: elf32-vax.c:543
 #, c-format
 msgid " [nonpic]"
 msgstr " [khác pic]"
 
-#: elf32-vax.c:544
+#: elf32-vax.c:546
 #, c-format
 msgid " [d-float]"
 msgstr " [trôi d]"
 
-#: elf32-vax.c:547
+#: elf32-vax.c:549
 #, c-format
 msgid " [g-float]"
 msgstr " [trôi g]"
 
-#: elf32-vax.c:657
+#: elf32-vax.c:666
 #, c-format
 msgid "%s: warning: GOT addend of %ld to `%s' does not match previous GOT addend of %ld"
 msgstr "%s: cảnh báo : số hạng GOT của %ld cho « %s » không tương ứng với số hạng GOT trước của %ld"
 
-#: elf32-vax.c:1589
+#: elf32-vax.c:1608
 #, c-format
 msgid "%s: warning: PLT addend of %d to `%s' from %s section ignored"
 msgstr "%s: cảnh báo : số hạng PLT của %d cho « %s » từ phần %s bị bỏ qua"
 
-#: elf32-vax.c:1726
+#: elf32-vax.c:1735
 #, c-format
 msgid "%s: warning: %s relocation against symbol `%s' from %s section"
 msgstr "%s: cảnh báo : định vị lại %s so với ký hiệu « %s » từ phần %s"
 
-#: elf32-vax.c:1732
+#: elf32-vax.c:1741
 #, c-format
 msgid "%s: warning: %s relocation to 0x%x from %s section"
 msgstr "%s: cảnh báo : định vị lại %s sang 0x%x từ phần %s"
 
-#: elf32-xstormy16.c:451 elf32-ia64.c:2794 elf64-ia64.c:2794
+#: elf32-xstormy16.c:451 elf32-ia64.c:2791 elf64-ia64.c:2791
 msgid "non-zero addend in @fptr reloc"
 msgstr "số hạng khác không trong định vị lại @fptr"
 
-#: elf32-xtensa.c:911
+#: elf32-xtensa.c:912
 msgid "%B(%A): invalid property table"
 msgstr "%B(%A): bảng thuộc tính sai"
 
-#: elf32-xtensa.c:2734
+#: elf32-xtensa.c:2740
 msgid "%B(%A+0x%lx): relocation offset out of range (size=0x%x)"
 msgstr "%B(%A+0x%lx): khoảng bù định vị lại ở ngoại phạm vi (kích cỡ=0x%x)"
 
-#: elf32-xtensa.c:2813 elf32-xtensa.c:2934
+#: elf32-xtensa.c:2819 elf32-xtensa.c:2940
 msgid "dynamic relocation in read-only section"
 msgstr "định vị lại động trong vùng chỉ đọc"
 
-#: elf32-xtensa.c:2910
+#: elf32-xtensa.c:2916
 msgid "TLS relocation invalid without dynamic sections"
 msgstr "Định vị lại TLS không hợp lệ mà không có phần động"
 
-#: elf32-xtensa.c:3127
+#: elf32-xtensa.c:3133
 msgid "internal inconsistency in size of .got.loc section"
 msgstr "sự mâu thuẫn nội bộ trong kích cỡ của phần .got.loc"
 
-#: elf32-xtensa.c:3437
+#: elf32-xtensa.c:3443
 msgid "%B: incompatible machine type. Output is 0x%x. Input is 0x%x"
 msgstr "%B: kiểu máy không tương thích. Kết xuất là 0x%x. Dữ liệu nhập vào là 0x%x."
 
-#: elf32-xtensa.c:4666 elf32-xtensa.c:4674
+#: elf32-xtensa.c:4672 elf32-xtensa.c:4680
 msgid "Attempt to convert L32R/CALLX to CALL failed"
 msgstr "Lỗi thử chuyển đổi L32R/CALLX sang CALL"
 
-#: elf32-xtensa.c:6276 elf32-xtensa.c:6352 elf32-xtensa.c:7468
+#: elf32-xtensa.c:6290 elf32-xtensa.c:6366 elf32-xtensa.c:7486
 msgid "%B(%A+0x%lx): could not decode instruction; possible configuration mismatch"
 msgstr "%B(%A+0x%lx): không thể giải mã chỉ dẫn; có thể sai khớp cấu hình"
 
-#: elf32-xtensa.c:7208
+#: elf32-xtensa.c:7226
 msgid "%B(%A+0x%lx): could not decode instruction for XTENSA_ASM_SIMPLIFY relocation; possible configuration mismatch"
 msgstr "%B(%A+0x%lx): không thể giải mã chỉ dẫn cho định vị lại XTENSA_ASM_SIMPLIFY; có thể sai khớp cấu hình"
 
-#: elf32-xtensa.c:8969
+#: elf32-xtensa.c:8987
 msgid "invalid relocation address"
 msgstr "địa chỉ định vị lại không hợp lệ"
 
-#: elf32-xtensa.c:9018
+#: elf32-xtensa.c:9036
 msgid "overflow after relaxation"
 msgstr "tràn sau khi giảm nhẹ"
 
-#: elf32-xtensa.c:10154
+#: elf32-xtensa.c:10167
 msgid "%B(%A+0x%lx): unexpected fix for %s relocation"
 msgstr "%B(%A+0x%lx): sửa chữa bất thường cho định vị lại %s"
 
@@ -2186,51 +2341,55 @@ msgstr "%B(%A+0x%lx): sửa chữa bất thường cho định vị lại %s"
 msgid "GPDISP relocation did not find ldah and lda instructions"
 msgstr "Định vị lại GPDISP không tìm thấy các chỉ dẫn ldah và lda"
 
-#: elf64-alpha.c:2416
+#: elf64-alpha.c:2389
 msgid "%B: .got subsegment exceeds 64K (size %d)"
 msgstr "%B: đoạn phụ .got vượt quá 64 K (kích cỡ %d)"
 
-#: elf64-alpha.c:4296 elf64-alpha.c:4308
+#: elf64-alpha.c:4269 elf64-alpha.c:4281
 msgid "%B: gp-relative relocation against dynamic symbol %s"
 msgstr "%B: định vị lại tương đối với gp (gp-relative) so với ký hiệu động %s"
 
-#: elf64-alpha.c:4334 elf64-alpha.c:4469
+#: elf64-alpha.c:4307 elf64-alpha.c:4442
 msgid "%B: pc-relative relocation against dynamic symbol %s"
 msgstr "%B: định vị lại tương đối với pc (pc-relative) so với ký hiệu động %s"
 
-#: elf64-alpha.c:4362
+#: elf64-alpha.c:4335
 msgid "%B: change in gp: BRSGP %s"
 msgstr "%B: thay đổi trong gp: BRSGP %s"
 
-#: elf64-alpha.c:4387
+#: elf64-alpha.c:4360
 msgid "<unknown>"
 msgstr "<không rõ>"
 
-#: elf64-alpha.c:4392
+#: elf64-alpha.c:4365
 msgid "%B: !samegp reloc against symbol without .prologue: %s"
 msgstr "%B: định vị lại !samegp so với ký hiệu không có .prologue: %s"
 
-#: elf64-alpha.c:4444
+#: elf64-alpha.c:4417
 msgid "%B: unhandled dynamic relocation against %s"
 msgstr "%B: không xử lý được định vị lại động so với %s"
 
-#: elf64-alpha.c:4476
+#: elf64-alpha.c:4449
 msgid "%B: pc-relative relocation against undefined weak symbol %s"
 msgstr "%B: định vị lại tương đối với pc (pc-relative) so với ký hiệu yếu chưa được xác định %s"
 
-#: elf64-alpha.c:4536
+#: elf64-alpha.c:4509
 msgid "%B: dtp-relative relocation against dynamic symbol %s"
 msgstr "%B: định vị lại tương đối với dtp (dtp-relative) so với ký hiệu động %s"
 
-#: elf64-alpha.c:4559
+#: elf64-alpha.c:4532
 msgid "%B: tp-relative relocation against dynamic symbol %s"
 msgstr "%B: định vị lại tương đối với tp (tp-relative) so với ký hiệu động %s"
 
-#: elf64-hppa.c:2071
+#: elf64-hppa.c:2091
 #, c-format
 msgid "stub entry for %s cannot load .plt, dp offset = %ld"
 msgstr "mục nhập mẩu cho %s không thể nạp .plt, khoảng bù dp = %ld"
 
+#: elf64-hppa.c:3273
+msgid "%B(%A+0x%lx): cannot reach %s"
+msgstr "%B(%A+0x%lx): không thể tới %s"
+
 #: elf64-mmix.c:1177
 #, c-format
 msgid ""
@@ -2293,65 +2452,65 @@ msgstr ""
 "Sự mâu thuẫn nội bộ : còn lại %u != tối đa %u.\n"
 "  Hãy thông báo lỗi này."
 
-#: elf64-ppc.c:2561 libbfd.c:978
+#: elf64-ppc.c:2691 libbfd.c:978
 msgid "%B: compiled for a big endian system and target is little endian"
 msgstr "%B: được biên dịch cho một hệ thống về cuối lớn, còn đích về cuối nhỏ"
 
-#: elf64-ppc.c:2564 libbfd.c:980
+#: elf64-ppc.c:2694 libbfd.c:980
 msgid "%B: compiled for a little endian system and target is big endian"
 msgstr "%B: được biên dịch cho một hệ thống về cuối nhỏ, còn đích về cuối lớn"
 
-#: elf64-ppc.c:6065
+#: elf64-ppc.c:6338
 #, c-format
 msgid "copy reloc against `%s' requires lazy plt linking; avoid setting LD_BIND_NOW=1 or upgrade gcc"
 msgstr "định vị lại sao chép so với « %s » thì cần thiết chức năng liên kết plt uể oải; hãy tránh đặtLD_BIND_NOW=1, hoặc nân cấp GCC"
 
-#: elf64-ppc.c:6486
+#: elf64-ppc.c:6767
 msgid "dynreloc miscount for %B, section %A"
 msgstr "sai đếm định vị lại động cho %B, phần %A"
 
-#: elf64-ppc.c:6570
+#: elf64-ppc.c:6851
 msgid "%B: .opd is not a regular array of opd entries"
 msgstr "%B: .opd không phải là một mảng chính quy các mục nhập opd"
 
-#: elf64-ppc.c:6579
+#: elf64-ppc.c:6860
 msgid "%B: unexpected reloc type %u in .opd section"
 msgstr "%B: gặp kiểu định vị lại bất thường %u trong phần .opd"
 
-#: elf64-ppc.c:6600
+#: elf64-ppc.c:6881
 msgid "%B: undefined sym `%s' in .opd section"
 msgstr "%B: gặp sym (liên kết mềm?) chưa được xác định « %s » trong phần .opd"
 
-#: elf64-ppc.c:7377 elf64-ppc.c:7754
+#: elf64-ppc.c:7640 elf64-ppc.c:8017
 #, c-format
 msgid "%s defined in removed toc entry"
 msgstr "%s được xác định trong mục nhập toc bị gỡ bỏ"
 
-#: elf64-ppc.c:8581
+#: elf64-ppc.c:8910
 #, c-format
 msgid "long branch stub `%s' offset overflow"
 msgstr "mẩu nhánh dài « %s » tràn khoảng bù"
 
-#: elf64-ppc.c:8640
+#: elf64-ppc.c:8969
 #, c-format
 msgid "can't find branch stub `%s'"
 msgstr "không tìm thấy mẩu nhánh « %s »"
 
-#: elf64-ppc.c:8702 elf64-ppc.c:8822
+#: elf64-ppc.c:9031 elf64-ppc.c:9169
 #, c-format
 msgid "linkage table error against `%s'"
 msgstr "lỗi bảng liên kết so với « %s »"
 
-#: elf64-ppc.c:8978
+#: elf64-ppc.c:9326
 #, c-format
 msgid "can't build branch stub `%s'"
 msgstr "không thể xây dựng mẩu nhánh « %s »"
 
-#: elf64-ppc.c:9451
+#: elf64-ppc.c:9799
 msgid "%B section %A exceeds stub group size"
 msgstr "%B phần %A vượt quá kích cỡ nhóm mẩu"
 
-#: elf64-ppc.c:10090
+#: elf64-ppc.c:10453
 #, c-format
 msgid ""
 "linker stubs in %u group%s\n"
@@ -2368,19 +2527,19 @@ msgstr ""
 "  điều chỉnh toc dài\t\t%lu\n"
 "  cuộc gọi pit\t\t\t%lu"
 
-#: elf64-ppc.c:10769
+#: elf64-ppc.c:11252
 msgid "%B(%A+0x%lx): automatic multiple TOCs not supported using your crt files; recompile with -mminimal-toc or upgrade gcc"
 msgstr "%B(%A+0x%lx): tự động tạo nhiều TOC không được hỗ trợ khi dùng các tập tin CRT của bạn; hãy biên dịch lại với « -mminimal-toc », hoặc nâng cấp GCC"
 
-#: elf64-ppc.c:10777
+#: elf64-ppc.c:11260
 msgid "%B(%A+0x%lx): sibling call optimization to `%s' does not allow automatic multiple TOCs; recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make `%s' extern"
 msgstr "%B(%A+0x%lx): tối ưu hoá cuộc gọi cùng chỗ cho « %s » không cho phép tự động tạo nhiều TOC; hãy biên dịch lại với « -mminimal-toc » hoặc « -fno-optimize-sibling-calls », hoặc làm cho « %s » là bên ngoài"
 
-#: elf64-ppc.c:11427
+#: elf64-ppc.c:11961
 msgid "%B: relocation %s is not supported for symbol %s."
 msgstr "%B: không hỗ trợ định vị lại %s cho ký hiệu %s."
 
-#: elf64-ppc.c:11509
+#: elf64-ppc.c:12044
 msgid "%B: error: relocation %s not a multiple of %d"
 msgstr "%B: lỗi: định vị lại %s không phải là bội số cho %d"
 
@@ -2405,31 +2564,31 @@ msgstr "Ký hiệu « %s » có các kiểu khác hau: REGISTER (thanh ghi) tron
 msgid "Symbol `%s' has differing types: %s in %B, previously REGISTER in %B"
 msgstr "Ký hiệu « %s » có các kiểu khác hau: %s trong %b, trước là REGISTER (thanh ghi) trong %B"
 
-#: elf64-sparc.c:678
+#: elf64-sparc.c:679
 msgid "%B: linking UltraSPARC specific with HAL specific code"
 msgstr "%B: đang liên kết UltraSPARC dứt khoát với mã đặc trưng cho HAL"
 
-#: elf64-x86-64.c:1047 elf64-x86-64.c:1207 elfxx-mips.c:7834
-msgid "%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"
-msgstr "%B: định vị lại %s so với « %s » không thể được dùng khi tạo một đối tượng chia sẻ; hãy biên dịch lại với « -fPIC »"
-
-#: elf64-x86-64.c:1138
+#: elf64-x86-64.c:1337
 msgid "%B: '%s' accessed both as normal and thread local symbol"
 msgstr "%B; « %s » được truy cập như là ký hiệu cả hai kiểu bình thường và mạch cục bộ"
 
-#: elf64-x86-64.c:2559
+#: elf64-x86-64.c:2701
+msgid "%B: relocation %s against STT_GNU_IFUNC symbol `%s' has non-zero addend: %d"
+msgstr "%B: sự định vị lại %s đối với ký hiệu STT_GNU_IFUNC « %s » có phần cộng khác số không: %d"
+
+#: elf64-x86-64.c:2980
 msgid "%B: relocation R_X86_64_GOTOFF64 against protected function `%s' can not be used when making a shared object"
 msgstr "%B: định vị lại R_X86_64_GOTOFF64 so với hàm đã bảo vệ « %s » thì không thể được dùng khi tạo một đối tượng chia sẻ"
 
-#: elf64-x86-64.c:2670
+#: elf64-x86-64.c:3091
 msgid "; recompile with -fPIC"
 msgstr "; biên dịch lại với « -fPIC »"
 
-#: elf64-x86-64.c:2675
+#: elf64-x86-64.c:3096
 msgid "%B: relocation %s against %s `%s' can not be used when making a shared object%s"
 msgstr "%B: không dùng được định vị lại %s đối với %s « %s » khi tạo một đối tượng chia sẻ %s"
 
-#: elf64-x86-64.c:2677
+#: elf64-x86-64.c:3098
 msgid "%B: relocation %s against undefined %s `%s' can not be used when making a shared object%s"
 msgstr "%B: không dùng được định vị lại %s đối với %s chưa xác định « %s » khi tạo một đối tượng chia sẻ %s"
 
@@ -2443,7 +2602,7 @@ msgstr "cảnh báo : %s có một chỉ mục bảng chuỗi bị hỏng: nên
 msgid "%s: version count (%ld) does not match symbol count (%ld)"
 msgstr "%s: số đếm phiên bản (%ld) không tương ứng với số đếm ký hiệu (%ld)"
 
-#: elfcode.h:1435
+#: elfcode.h:1441
 #, c-format
 msgid "%s(%s): relocation %d has invalid symbol index %ld"
 msgstr "%s(%s): định vị lại %d có chỉ mục ký hiệu không hợp lệ %ld"
@@ -2452,305 +2611,313 @@ msgstr "%s(%s): định vị lại %d có chỉ mục ký hiệu không hợp l
 msgid "Warning: %B is truncated: expected core file size >= %lu, found: %lu."
 msgstr "Cảnh báo : %B bị cắt ngắn: kích cỡ tập tin lõi mong đợi ≥%lu còn tìm %lu."
 
-#: elflink.c:1028
+#: elflink.c:1113
 msgid "%s: TLS definition in %B section %A mismatches non-TLS definition in %B section %A"
 msgstr "%s: lời định nghĩa TLS trong %B phần %A không tương ứng với lời định nghĩa TLS trong %B phần %A"
 
-#: elflink.c:1032
+#: elflink.c:1117
 msgid "%s: TLS reference in %B mismatches non-TLS reference in %B"
 msgstr "%s: lời định nghĩa TLS trong %B không tương ứng với lời định nghĩa khác TLS trong %B"
 
-#: elflink.c:1036
+#: elflink.c:1121
 msgid "%s: TLS definition in %B section %A mismatches non-TLS reference in %B"
 msgstr "%s: lời định nghĩa TLS trong %B phần %A không tương ứng với lời định nghĩa khác TLS trong %B"
 
-#: elflink.c:1040
+#: elflink.c:1125
 msgid "%s: TLS reference in %B mismatches non-TLS definition in %B section %A"
 msgstr "%s: lời định nghĩa TLS trong %B không tương ứng với lời định nghĩa khác TLS trong %B phần %A"
 
-#: elflink.c:1654
+#: elflink.c:1764
 msgid "%B: unexpected redefinition of indirect versioned symbol `%s'"
 msgstr "%B: gặp lời định nghĩa lại bất thường của ký hiệu gián tiếp đặt phiên bản « %s »"
 
-#: elflink.c:1982
+#: elflink.c:2077
 msgid "%B: version node not found for symbol %s"
 msgstr "%B: không tìm thấy nút thông tin phiên bản cho ký hiệu %s"
 
-#: elflink.c:2130
+#: elflink.c:2167
 msgid "%B: bad reloc symbol index (0x%lx >= 0x%lx) for offset 0x%lx in section `%A'"
 msgstr "%B: chỉ mục ký hiệu định vị lại sai (0x%lx ≥ 0x%lx) cho khoảng bù 0x%lx trong phần « %A »"
 
-#: elflink.c:2327
+#: elflink.c:2178
+msgid "%B: non-zero symbol index (0x%lx) for offset 0x%lx in section `%A' when the object file has no symbol table"
+msgstr "%B: chỉ mục ký hiệu khác số không (0x%lx) cho hiệu 0x%lx trong phần « %A » mà tập tin đối tượng không có bảng ký hiệu"
+
+#: elflink.c:2375
 msgid "%B: relocation size mismatch in %B section %A"
 msgstr "%B: sai khớp kích cỡ định vị lại trong %B phần %A"
 
-#: elflink.c:2629
+#: elflink.c:2678
 #, c-format
 msgid "warning: type and size of dynamic symbol `%s' are not defined"
 msgstr "cảnh báo : chưa xác định kiểu và kích cỡ của ký hiệu động « %s »"
 
-#: elflink.c:3953
+#: elflink.c:3424
+msgid "%P: alternate ELF machine code found (%d) in %B, expecting %d\n"
+msgstr "%P: mã máy ELF luân phiên được tìm (%d) trong %B, còn mong đợi %d\n"
+
+#: elflink.c:4032
 msgid "%B: %s: invalid version %u (max %d)"
 msgstr "%B: %s: phiên bản không hợp lệ %u (tối đa %d)"
 
-#: elflink.c:3989
+#: elflink.c:4068
 msgid "%B: %s: invalid needed version %d"
 msgstr "%B: %s: phiên bản cần thiết mà không hợp lệ %d"
 
-#: elflink.c:4172
+#: elflink.c:4253
 msgid "Warning: alignment %u of common symbol `%s' in %B is greater than the alignment (%u) of its section %A"
 msgstr "Cảnh báo : vị trí sắp hàng %u của ký hiệu dùng chung « %s » trong %B là lớn hơn vị trí sắp hàng (%u) của phần %A của nó"
 
-#: elflink.c:4178
+#: elflink.c:4259
 msgid "Warning: alignment %u of symbol `%s' in %B is smaller than %u in %B"
 msgstr "Cảnh báo : vị trí sắp hàng %u của ký hiệu « %s » trong %B là nhỏ hơn %u trong %B"
 
-#: elflink.c:4193
+#: elflink.c:4274
 msgid "Warning: size of symbol `%s' changed from %lu in %B to %lu in %B"
 msgstr "Cảnh báo : kích cỡ của ký hiệu « %s » đã thay đổi từ %lu trong %B thành %lu trong %B"
 
-#: elflink.c:4371
+#: elflink.c:4438
 #, c-format
 msgid "%s: invalid DSO for symbol `%s' definition"
 msgstr "%s: DSO không hợp lệ cho lời định nghĩa ký hiệu « %s »"
 
-#: elflink.c:5621
+#: elflink.c:5688
 #, c-format
 msgid "%s: undefined version: %s"
 msgstr "%s: phiên bản chưa được xác định: %s"
 
-#: elflink.c:5689
+#: elflink.c:5756
 msgid "%B: .preinit_array section is not allowed in DSO"
 msgstr "%B: không cho phép phần « .preinit_array » trong DSO"
 
-#: elflink.c:7414
+#: elflink.c:7484
 #, c-format
 msgid "undefined %s reference in complex symbol: %s"
 msgstr "gặp tham chiếu %s chưa được xác định trong ký hiệu phức tạp %s"
 
-#: elflink.c:7568
+#: elflink.c:7638
 #, c-format
 msgid "unknown operator '%c' in complex symbol"
 msgstr "không rõ toán tử « %c » trong ký hiệu phức tạp"
 
-#: elflink.c:7904 elflink.c:7921 elflink.c:7958 elflink.c:7975
+#: elflink.c:7976 elflink.c:7993 elflink.c:8030 elflink.c:8047
 msgid "%B: Unable to sort relocs - they are in more than one size"
 msgstr "%B: Không thể sắp xếp các sự định vị lại: chúng có kích cỡ khác nhau"
 
-#: elflink.c:7935 elflink.c:7989
+#: elflink.c:8007 elflink.c:8061
 msgid "%B: Unable to sort relocs - they are of an unknown size"
 msgstr "%B: Không thể sắp xếp các sự định vị lại: chúng có kích cỡ không rõ"
 
-#: elflink.c:8038
+#: elflink.c:8112
 msgid "Not enough memory to sort relocations"
 msgstr "Không đủ bộ nhớ để sắp xếp các sự định vị lại"
 
-#: elflink.c:8227
+#: elflink.c:8304
 msgid "%B: Too many sections: %d (>= %d)"
 msgstr "%B: Quá nhiều phần: %d (≥ %d)"
 
-#: elflink.c:8461
+#: elflink.c:8540
 msgid "%B: %s symbol `%s' in %B is referenced by DSO"
 msgstr "%B: %s ký hiệu « %s » trong %B được DSO tham chiếu"
 
-#: elflink.c:8544
+#: elflink.c:8625
 msgid "%B: could not find output section %A for input section %A"
 msgstr "%B: không thể tìm thấy phần kết xuất %A cho phần dữ liệu nhập vào %A"
 
-#: elflink.c:8655
+#: elflink.c:8745
 msgid "%B: %s symbol `%s' isn't defined"
 msgstr "%B: %s: chưa xác định ký hiệu « %s »"
 
-#: elflink.c:9141
+#: elflink.c:9301
 msgid "error: %B contains a reloc (0x%s) for section %A that references a non-existent global symbol"
 msgstr "lỗi: %B chứa một định vị lại (0x%s) cho phần %A mà tham chiếu đến một ký hiệu toàn cục không tồn tại"
 
-#: elflink.c:9205
+#: elflink.c:9366
 msgid "%X`%s' referenced in section `%A' of %B: defined in discarded section `%A' of %B\n"
 msgstr "%X« %s » được tham chiếu trong phần « %A » của %B: được định nghĩa trong phần bị hủy « %A » của %B\n"
 
-#: elflink.c:9825
+#: elflink.c:9991
 msgid "%A has both ordered [`%A' in %B] and unordered [`%A' in %B] sections"
 msgstr "%A có phần cả hai được sắp xếp [« %A » trong %B] và chưa sắp xếp [« %A » trong %B]"
 
-#: elflink.c:9830
+#: elflink.c:9996
 #, c-format
 msgid "%A has both ordered and unordered sections"
 msgstr "%A có phần cả hai được sắp xếp và chưa sắp xếp"
 
-#: elflink.c:10715 elflink.c:10759
+#: elflink.c:10872 elflink.c:10916
 msgid "%B: could not find output section %s"
 msgstr "%B: không tìm thấy phần kết xuất %s"
 
-#: elflink.c:10720
+#: elflink.c:10877
 #, c-format
 msgid "warning: %s section has zero size"
 msgstr "cảnh báo : phần %s có kích cỡ số không"
 
-#: elflink.c:10824
+#: elflink.c:10982
 msgid "%P: warning: creating a DT_TEXTREL in a shared object.\n"
 msgstr "%P: cảnh báo : đang tạo một DT_TEXTREL trong một đối tượng chia sẻ.\n"
 
-#: elflink.c:11006
+#: elflink.c:11165
 msgid "%P%X: can not read symbols: %E\n"
 msgstr "%P%X: không thể đọc các ký hiệu : %E\n"
 
-#: elflink.c:11313
+#: elflink.c:11483
 msgid "Removing unused section '%s' in file '%B'"
 msgstr "Đang gỡ bỏ phần không dùng « %s » trong tập tin « %B »"
 
-#: elflink.c:11525
+#: elflink.c:11695
 msgid "Warning: gc-sections option ignored"
 msgstr "Cảnh báo : tùy chọn gc-sections bị bỏ qua"
 
-#: elflink.c:12056
+#: elflink.c:12242
 msgid "%B: ignoring duplicate section `%A'"
 msgstr "%B: đang bỏ qua phần trùng « %A »"
 
-#: elflink.c:12063 elflink.c:12070
+#: elflink.c:12249 elflink.c:12256
 msgid "%B: duplicate section `%A' has different size"
 msgstr "%B: phần trùng « %A » có kích cỡ khác"
 
-#: elflink.c:12078 elflink.c:12083
+#: elflink.c:12264 elflink.c:12269
 msgid "%B: warning: could not read contents of section `%A'"
 msgstr "%B: cảnh báo : không thể đọc nội dung của phần « %A »"
 
-#: elflink.c:12087
+#: elflink.c:12273
 msgid "%B: warning: duplicate section `%A' has different contents"
 msgstr "%B: cảnh báo : phần trùng « %A » có nội dung khác"
 
-#: elflink.c:12166 linker.c:3080
-msgid "%F%P: already_linked_table: %E"
-msgstr "%F%P: already_linked_table: %E"
+#: elflink.c:12374 linker.c:3098
+msgid "%F%P: already_linked_table: %E\n"
+msgstr "%F%P: already_linked_table: %E\n"
 
-#: elfxx-mips.c:1197
+#: elfxx-mips.c:1222
 msgid "static procedure (no name)"
 msgstr "thủ tục tĩnh (không có tên)"
 
-#: elfxx-mips.c:5562
+#: elfxx-mips.c:5588
 msgid "%B: %A+0x%lx: jump to stub routine which is not jal"
 msgstr "%B: %A+0x%lx: nhảy tới hàm mẩu mà không phải jal"
 
-#: elfxx-mips.c:6206 elfxx-mips.c:6427
+#: elfxx-mips.c:6235 elfxx-mips.c:6458
 msgid "%B: Warning: bad `%s' option size %u smaller than its header"
 msgstr "%B: Cảnh báo : kích cỡ tùy chọn « %s » sai: nhỏ hơn phần đầu của nó"
 
-#: elfxx-mips.c:7174 elfxx-mips.c:7299
+#: elfxx-mips.c:7205 elfxx-mips.c:7330
 msgid "%B: Warning: cannot determine the target function for stub section `%s'"
 msgstr "%B: cảnh báo : không thể quyết định hàm đích cho phần mẩu « %s »"
 
-#: elfxx-mips.c:7428
+#: elfxx-mips.c:7459
 msgid "%B: Malformed reloc detected for section %s"
 msgstr "%B: Phát hiện sự định vị lại dạng sai cho phần %s"
 
-#: elfxx-mips.c:7468
+#: elfxx-mips.c:7499
 msgid "%B: GOT reloc at 0x%lx not expected in executables"
 msgstr "%B: định vị lại GOT ở 0x%lx không mong đợi trong tập tin có khả năng thực hiện"
 
-#: elfxx-mips.c:7566
+#: elfxx-mips.c:7602
 msgid "%B: CALL16 reloc at 0x%lx not against global symbol"
 msgstr "%B: định vị lại CALL16 ở 0x%lx không phải so với ký hiệu toàn cục"
 
-#: elfxx-mips.c:8244
+#: elfxx-mips.c:8280
 #, c-format
 msgid "non-dynamic relocations refer to dynamic symbol %s"
 msgstr "định vị lại khác động cũng tham chiếu đến ký hiệu động %s"
 
-#: elfxx-mips.c:8947
+#: elfxx-mips.c:8985
 msgid "%B: Can't find matching LO16 reloc against `%s' for %s at 0x%lx in section `%A'"
 msgstr "%B: Không tìm thấy định vị lại LO16 tương ứng so với « %s » cho %s ở 0x%lx trong phần « %A »"
 
-#: elfxx-mips.c:9086
+#: elfxx-mips.c:9124
 msgid "small-data section exceeds 64KB; lower small-data size limit (see option -G)"
 msgstr "Phần small-data (dữ liệu nhỏ) vượt quá 64 KB; hãy giảm giới hạn dữ liệu nhỏ (xem tùy chọn « -G »)"
 
-#: elfxx-mips.c:11887
+#: elfxx-mips.c:11940
 #, c-format
 msgid "%s: illegal section name `%s'"
 msgstr "%s: tên phần cấm « %s »"
 
-#: elfxx-mips.c:12262 elfxx-mips.c:12288
+#: elfxx-mips.c:12318 elfxx-mips.c:12344
 msgid "Warning: %B uses -msingle-float, %B uses -mdouble-float"
 msgstr "Cảnh báo : %B dùng « -msingle-float », còn %B dùng « -mdouble-float »"
 
-#: elfxx-mips.c:12274 elfxx-mips.c:12330
+#: elfxx-mips.c:12330 elfxx-mips.c:12386
 msgid "Warning: %B uses -msingle-float, %B uses -mips32r2 -mfp64"
 msgstr "Cảnh báo : %B dùng « -msingle-float », còn %B dùng « -mips32r2 -mfp64 »"
 
-#: elfxx-mips.c:12300 elfxx-mips.c:12336
+#: elfxx-mips.c:12356 elfxx-mips.c:12392
 msgid "Warning: %B uses -mdouble-float, %B uses -mips32r2 -mfp64"
 msgstr "Cảnh báo : %B dùng « -mdouble-float », còn %B dùng « -mips32r2 -mfp64 »"
 
-#: elfxx-mips.c:12378
+#: elfxx-mips.c:12434
 msgid "%B: endianness incompatible with that of the selected emulation"
 msgstr "%B: tình trạng về cuối không tương thích với cái của bản mô phỏng đã chọn"
 
-#: elfxx-mips.c:12389
+#: elfxx-mips.c:12445
 msgid "%B: ABI is incompatible with that of the selected emulation"
 msgstr "%B: ABI không tương thích với cái của bản mô phỏng đã chọn"
 
-#: elfxx-mips.c:12470
+#: elfxx-mips.c:12526
 msgid "%B: warning: linking abicalls files with non-abicalls files"
 msgstr "%B: cảnh báo : đang liên kết tập tin abicalls với tập tin khác abicalls"
 
-#: elfxx-mips.c:12487
+#: elfxx-mips.c:12543
 msgid "%B: linking 32-bit code with 64-bit code"
 msgstr "%B: đang liên kết mã 32-bit với mã 64-bit"
 
-#: elfxx-mips.c:12515
+#: elfxx-mips.c:12571
 msgid "%B: linking %s module with previous %s modules"
 msgstr "%B: đang liên kết mô-đun %s với các mô-đun %s trước"
 
-#: elfxx-mips.c:12538
+#: elfxx-mips.c:12594
 msgid "%B: ABI mismatch: linking %s module with previous %s modules"
 msgstr "%B: sai khớp ABI: đang liên kết mô-đun %s với các mô-đun %s trước"
 
-#: elfxx-mips.c:12702
+#: elfxx-mips.c:12758
 #, c-format
 msgid " [abi=O32]"
 msgstr " [abi=O32]"
 
-#: elfxx-mips.c:12704
+#: elfxx-mips.c:12760
 #, c-format
 msgid " [abi=O64]"
 msgstr " [abi=O64]"
 
-#: elfxx-mips.c:12706
+#: elfxx-mips.c:12762
 #, c-format
 msgid " [abi=EABI32]"
 msgstr " [abi=EABI32]"
 
-#: elfxx-mips.c:12708
+#: elfxx-mips.c:12764
 #, c-format
 msgid " [abi=EABI64]"
 msgstr " [abi=EABI64]"
 
-#: elfxx-mips.c:12710
+#: elfxx-mips.c:12766
 #, c-format
 msgid " [abi unknown]"
 msgstr " [abi không rõ]"
 
-#: elfxx-mips.c:12712
+#: elfxx-mips.c:12768
 #, c-format
 msgid " [abi=N32]"
 msgstr " [abi=N32]"
 
-#: elfxx-mips.c:12714
+#: elfxx-mips.c:12770
 #, c-format
 msgid " [abi=64]"
 msgstr " [abi=64]"
 
-#: elfxx-mips.c:12716
+#: elfxx-mips.c:12772
 #, c-format
 msgid " [no abi set]"
 msgstr " [chưa đặt abi]"
 
-#: elfxx-mips.c:12737
+#: elfxx-mips.c:12793
 #, c-format
 msgid " [unknown ISA]"
 msgstr " [không rõ ISA]"
 
-#: elfxx-mips.c:12748
+#: elfxx-mips.c:12804
 #, c-format
 msgid " [not 32bitmode]"
 msgstr " [không phải 32bitmode]"
@@ -2760,10 +2927,6 @@ msgstr " [không phải 32bitmode]"
 msgid "invalid relocation type %d"
 msgstr "kiểu định vị lại không hợp lệ %d"
 
-#: elfxx-sparc.c:2976
-msgid "%B: probably compiled without -fPIC?"
-msgstr "%B: rất có thể được biên dịch không có « -fPIC » ?"
-
 #: i386linux.c:455 m68klinux.c:459 sparclinux.c:453
 #, c-format
 msgid "Output file requires shared library `%s'\n"
@@ -2866,15 +3029,75 @@ msgstr "%B: ký hiệu gián tiếp « %s » tới « %s » thì tạo một vò
 msgid "Attempt to do relocatable link with %s input and %s output"
 msgstr "Thử làm liên kết có khả năng định vị lại với đầu vào %s và đầu ra %s"
 
-#: linker.c:3047
+#: linker.c:3065
 msgid "%B: warning: ignoring duplicate section `%A'\n"
 msgstr "%B: cảnh báo : đang bỏ qua phần trùng « %A »\n"
 
-#: linker.c:3061
+#: linker.c:3079
 msgid "%B: warning: duplicate section `%A' has different size\n"
 msgstr "%B: cảnh báo : phần trùng « %A » có kích cỡ khác\n"
 
-#: merge.c:828
+#: mach-o.c:3195
+#, c-format
+msgid "Mach-O header:\n"
+msgstr "Phần đầu Mach-O :\n"
+
+#: mach-o.c:3196
+#, c-format
+msgid " magic     : %08lx\n"
+msgstr " ma thuật : %08lx\n"
+
+#: mach-o.c:3197
+#, c-format
+msgid " cputype   : %08lx (%s)\n"
+msgstr " kiểu CPU : %08lx (%s)\n"
+
+#: mach-o.c:3199
+#, c-format
+msgid " cpusubtype: %08lx\n"
+msgstr " kiểu phụ CPU : %08lx\n"
+
+#: mach-o.c:3200
+#, c-format
+msgid " filetype  : %08lx (%s)\n"
+msgstr " kiểu tập tin : %08lx (%s)\n"
+
+#: mach-o.c:3203
+#, c-format
+msgid " ncmds     : %08lx\n"
+msgstr " ncmds     : %08lx\n"
+
+#: mach-o.c:3204
+#, c-format
+msgid " sizeofcmds: %08lx\n"
+msgstr " kích cỡ cmds : %08lx\n"
+
+#: mach-o.c:3205
+#, c-format
+msgid " flags     : %08lx ("
+msgstr " cờ     : %08lx ("
+
+#: mach-o.c:3207
+#, c-format
+msgid ")\n"
+msgstr ")\n"
+
+#: mach-o.c:3208
+#, c-format
+msgid " reserved  : %08x\n"
+msgstr " dành riêng  : %08x\n"
+
+#: mach-o.c:3218
+#, c-format
+msgid "Segments and Sections:\n"
+msgstr "Đoạn và Phần:\n"
+
+#: mach-o.c:3219
+#, c-format
+msgid " #: Segment name     Section name     Address\n"
+msgstr " #: Tên đoạn     Tên phần     Địa chỉ\n"
+
+#: merge.c:829
 #, c-format
 msgid "%s: access beyond end of merged section (%ld)"
 msgstr "%s: truy cập vượt quá kết thúc của phần đã gộp lại (%ld)"
@@ -3014,7 +3237,7 @@ msgstr "%s: không thể đại diện phần « %s » theo oasys"
 msgid "Unhandled OSF/1 core file section type %d\n"
 msgstr "Kiểu phần tập tin lõi OSF/1 không được quản lý %d\n"
 
-#: pe-mips.c:607
+#: pe-mips.c:613
 msgid "%B: `ld -r' not supported with PE MIPS objects\n"
 msgstr "%B: « ld -r » không được hỗ trợ với đối tượng MIPS PE\n"
 
@@ -3022,44 +3245,64 @@ msgstr "%B: « ld -r » không được hỗ trợ với đối tượng MIPS PE
 #. src = VMA of the memory we're fixing up
 #. mem = pointer to memory we're fixing up
 #. val = VMA of what we need to refer to.
-#: pe-mips.c:723
+#: pe-mips.c:729
 msgid "%B: unimplemented %s\n"
 msgstr "%B: %s chưa được thực hiện\n"
 
-#: pe-mips.c:749
+#: pe-mips.c:755
 msgid "%B: jump too far away\n"
 msgstr "%B: bước nhảy quá xa\n"
 
-#: pe-mips.c:775
+#: pe-mips.c:781
 msgid "%B: bad pair/reflo after refhi\n"
 msgstr "%B: pair/reflo sai đằng sau refhi\n"
 
+#: pei-x86_64.c:465
+#, c-format
+msgid "warning: .pdata section size (%ld) is not a multiple of %d\n"
+msgstr "cảnh báo : kích cỡ phần .pdata (%ld) không phải là bội số cho %d\n"
+
+#: pei-x86_64.c:469 peigen.c:1620 peigen.c:1799 pepigen.c:1620 pepigen.c:1799
+#: pex64igen.c:1620 pex64igen.c:1799
+#, c-format
+msgid ""
+"\n"
+"The Function Table (interpreted .pdata section contents)\n"
+msgstr ""
+"\n"
+"Bảng Hàm (phiên dịch nội dung phần .pdata)\n"
+
+#: pei-x86_64.c:471
+#, c-format
+msgid "vma:\t\t\tBeginAddress\t EndAddress\t  UnwindData\n"
+msgstr "vma:\t\t\tĐịa chi đầu    Địa chỉ cuối     Thông tin tháo ra\n"
+
 #. XXX code yet to be written.
-#: peicode.h:759
+#: peicode.h:752
 msgid "%B: Unhandled import type; %x"
 msgstr "%B: Kiểu nhập không được quản lý; %x"
 
-#: peicode.h:764
+#: peicode.h:757
 msgid "%B: Unrecognised import type; %x"
 msgstr "%B: Kiểu nhập không được nhận ra; %x"
 
-#: peicode.h:778
+#: peicode.h:771
 msgid "%B: Unrecognised import name type; %x"
 msgstr "%B: Kiểu tên nhập không được nhận ra; %x"
 
-#: peicode.h:1161
+#: peicode.h:1154
 msgid "%B: Unrecognised machine type (0x%x) in Import Library Format archive"
 msgstr "%B: Kiểu máy không được nhận ra (0x%x) trong kho lưu Định dạng Thư viện Nhập"
 
-#: peicode.h:1173
+#: peicode.h:1166
 msgid "%B: Recognised but unhandled machine type (0x%x) in Import Library Format archive"
 msgstr "%B: Kiểu máy được nhận ra còn không được quản lý (0x%x) trong kho lưu Định dạng Thư viện Nhập"
 
-#: peicode.h:1191
+#: peicode.h:1184
 msgid "%B: size field is zero in Import Library Format header"
 msgstr "%B: trường kích cỡ là số không trong phần đầu Định dạng Thư viện Nhập"
 
-#: peicode.h:1222
+#: peicode.h:1215
 msgid "%B: string not null terminated in ILF object file."
 msgstr "%B: chuỗi không phải kết thúc vô hiệu lực trong tập tin đối tượng ILF. "
 
@@ -3116,7 +3359,7 @@ msgstr "Phân vùng[%d] rãnh ghi = 0x%.8lx (%ld)\n"
 msgid "Partition[%d] length = 0x%.8lx (%ld)\n"
 msgstr "Phân vùng[%d] dài = 0x%.8lx (%ld)\n"
 
-#: som.c:5137
+#: som.c:5114
 #, c-format
 msgid ""
 "\n"
@@ -3125,7 +3368,7 @@ msgstr ""
 "\n"
 "Phần đầu phụ thực hiện\n"
 
-#: som.c:5440
+#: som.c:5417
 msgid "som_sizeof_headers unimplemented"
 msgstr "som_sizeof_headers chưa được thực hiện"
 
@@ -3141,122 +3384,173 @@ msgstr "%B:%d: sai tổng kiểm trong tập tin S-record\n"
 msgid "%B(%A+0x%lx): Stabs entry has invalid string index."
 msgstr "%B(%A+0x%lx): Mục nhập Stabs có chỉ mục chuỗi không hợp lệ."
 
-#: syms.c:1067
+#: syms.c:1079
 msgid "Unsupported .stab relocation"
 msgstr "Định vị lại .stab không được hỗ trợ"
 
-#: vms-gsd.c:338
+#: vms-gsd.c:350
 #, c-format
 msgid "bfd_make_section (%s) failed"
 msgstr "bfd_make_section (%s) bị lỗi"
 
-#: vms-gsd.c:353
+#: vms-gsd.c:365
 #, c-format
 msgid "bfd_set_section_flags (%s, %x) failed"
 msgstr "bfd_set_section_flags (%s, %x) bị lỗi"
 
-#: vms-gsd.c:388
+#: vms-gsd.c:399
 #, c-format
 msgid "Size mismatch section %s=%lx, %s=%lx"
 msgstr "Sai khớp phần %s=%lx, %s=%lx"
 
-#: vms-gsd.c:679
+#: vms-gsd.c:754
 #, c-format
-msgid "unknown gsd/egsd subtype %d"
-msgstr "Không rõ kiểu phụ gsd/egsd %d"
+msgid "Unknown GSD/EGSD subtype %d"
+msgstr "Không rõ kiểu phụ GSD/EGSD %d"
 
-#: vms-hdr.c:328
+#: vms-hdr.c:364
 msgid "Object module NOT error-free !\n"
 msgstr "Mô-đun đối tượng KHÔNG phải miễn lỗi !\n"
 
-#: vms-misc.c:474
+#: vms-hdr.c:878
+#, c-format
+msgid "unknown source command %d"
+msgstr "không rõ câu lệnh nguồn %d"
+
+#: vms-hdr.c:951
+msgid "DST_S_C_SET_LINUM_INCR not implemented"
+msgstr "DST_S_C_SET_LINUM_INCR chưa được thực hiện"
+
+#: vms-hdr.c:957
+msgid "DST_S_C_SET_LINUM_INCR_W not implemented"
+msgstr "DST_S_C_SET_LINUM_INCR_W chưa được thực hiện"
+
+#: vms-hdr.c:963
+msgid "DST_S_C_RESET_LINUM_INCR not implemented"
+msgstr "DST_S_C_RESET_LINUM_INCR chưa được thực hiện"
+
+#: vms-hdr.c:969
+msgid "DST_S_C_BEG_STMT_MODE not implemented"
+msgstr "DST_S_C_BEG_STMT_MODE chưa được thực hiện"
+
+#: vms-hdr.c:975
+msgid "DST_S_C_END_STMT_MODE not implemented"
+msgstr "DST_S_C_END_STMT_MODE chưa được thực hiện"
+
+#: vms-hdr.c:1008
+msgid "DST_S_C_SET_PC not implemented"
+msgstr "DST_S_C_SET_PC chưa được thực hiện"
+
+#: vms-hdr.c:1014
+msgid "DST_S_C_SET_PC_W not implemented"
+msgstr "DST_S_C_SET_PC_W chưa được thực hiện"
+
+#: vms-hdr.c:1020
+msgid "DST_S_C_SET_PC_L not implemented"
+msgstr "DST_S_C_SET_PC_L chưa được thực hiện"
+
+#: vms-hdr.c:1026
+msgid "DST_S_C_SET_STMTNUM not implemented"
+msgstr "DST_S_C_SET_STMTNUM chưa được thực hiện"
+
+#: vms-hdr.c:1079
+#, c-format
+msgid "unknown line command %d"
+msgstr "không rõ câu lệnh dòng %d"
+
+#: vms-misc.c:588
 #, c-format
 msgid "Stack overflow (%d) in _bfd_vms_push"
 msgstr "Tràn đống (%d) trong _bfd_vms_push"
 
-#: vms-misc.c:489
+#: vms-misc.c:603
 msgid "Stack underflow in _bfd_vms_pop"
 msgstr "Trán ngược đống trong _bfd_vms_pop"
 
-#: vms-misc.c:808
+#: vms-misc.c:844
 msgid "_bfd_vms_output_counted called with zero bytes"
 msgstr "_bfd_vms_output_counted được gọi với số không byte"
 
-#: vms-misc.c:813
+#: vms-misc.c:849
 msgid "_bfd_vms_output_counted called with too many bytes"
 msgstr "_bfd_vms_output_counted được gọi với quá nhiều byte"
 
-#: vms-misc.c:931
+#: vms-misc.c:967
 #, c-format
 msgid "Symbol %s replaced by %s\n"
 msgstr "Ký hiệu %s đã bị thay thế bằng %s\n"
 
-#: vms-misc.c:990
+#: vms-misc.c:1026
 #, c-format
 msgid "failed to enter %s"
 msgstr "lỗi vào %s"
 
-#: vms-tir.c:57
+#: vms-tir.c:83
 msgid "No Mem !"
 msgstr "Không có Mem !"
 
-#: vms-tir.c:300
+#. These names have not yet been added to this switch statement.
+#: vms-tir.c:346
+#, c-format
+msgid "unknown ETIR command %d"
+msgstr "không rõ câu lệnh ETIR %d"
+
+#: vms-tir.c:440
 #, c-format
 msgid "bad section index in %s"
 msgstr "chỉ mục phần sai trong %s"
 
-#: vms-tir.c:313
+#: vms-tir.c:459
 #, c-format
 msgid "unsupported STA cmd %s"
 msgstr "câu lệnh STA không được hỗ trợ %s"
 
-#: vms-tir.c:318 vms-tir.c:1120
+#: vms-tir.c:464 vms-tir.c:1304
 #, c-format
 msgid "reserved STA cmd %d"
 msgstr "câu lệnh STA dành riêng %d"
 
-#: vms-tir.c:410 vms-tir.c:432
-#, c-format
-msgid "%s: no symbol \"%s\""
-msgstr "%s: không có ký hiệu « %s »"
-
 #. Unsigned shift.
 #. Rotate.
 #. Redefine symbol to current location.
 #. Define a literal.
-#: vms-tir.c:497 vms-tir.c:606 vms-tir.c:704 vms-tir.c:721 vms-tir.c:728
-#: vms-tir.c:736 vms-tir.c:1440
+#: vms-tir.c:655 vms-tir.c:774 vms-tir.c:894 vms-tir.c:1624
 #, c-format
 msgid "%s: not supported"
 msgstr "%s: không được hỗ trợ"
 
-#: vms-tir.c:502 vms-tir.c:1297
+#: vms-tir.c:661 vms-tir.c:1481
 #, c-format
 msgid "%s: not implemented"
 msgstr "%s: chưa được thực hiện"
 
-#: vms-tir.c:506 vms-tir.c:1301
+#: vms-tir.c:666 vms-tir.c:1485
 #, c-format
 msgid "reserved STO cmd %d"
 msgstr "câu lệnh STO dành riêng %d"
 
-#: vms-tir.c:621 vms-tir.c:1445
+#: vms-tir.c:789 vms-tir.c:1629
 #, c-format
 msgid "reserved OPR cmd %d"
 msgstr "câu lệnh OPR dành riêng %d"
 
-#: vms-tir.c:681 vms-tir.c:1509
+#: vms-tir.c:852 vms-tir.c:1693
 #, c-format
 msgid "reserved CTL cmd %d"
 msgstr "câu lệnh CTL dành riêng %d"
 
+#: vms-tir.c:966
+#, c-format
+msgid "reserved STC cmd %d"
+msgstr "câu lệnh STC dành riêng %d"
+
 #. stack byte from image
 #. arg: none.
-#: vms-tir.c:1028
+#: vms-tir.c:1212
 msgid "stack-from-image not implemented"
 msgstr "stack-from-image chưa được thực hiện"
 
-#: vms-tir.c:1046
+#: vms-tir.c:1230
 msgid "stack-entry-mask not fully implemented"
 msgstr "stack-entry-mask chưa được thực hiện hoàn toàn"
 
@@ -3267,270 +3561,285 @@ msgstr "stack-entry-mask chưa được thực hiện hoàn toàn"
 #.
 #. compare argument descriptor with symbol argument (ARG$V_PASSMECH)
 #. and stack TRUE (args match) or FALSE (args dont match) value.
-#: vms-tir.c:1060
+#: vms-tir.c:1244
 msgid "PASSMECH not fully implemented"
 msgstr "PASSMECH chưa được thực hiện hoàn toàn"
 
-#: vms-tir.c:1079
+#: vms-tir.c:1263
 msgid "stack-local-symbol not fully implemented"
 msgstr "stack-local-symbol chưa được thực hiện hoàn toàn"
 
-#: vms-tir.c:1092
+#: vms-tir.c:1276
 msgid "stack-literal not fully implemented"
 msgstr "stack-literal chưa được thực hiện hoàn toàn"
 
-#: vms-tir.c:1113
+#: vms-tir.c:1297
 msgid "stack-local-symbol-entry-point-mask not fully implemented"
 msgstr "stack-local-symbol-entry-point-mask chưa được thực hiện hoàn toàn"
 
-#: vms-tir.c:1387 vms-tir.c:1399 vms-tir.c:1411 vms-tir.c:1423 vms-tir.c:1488
-#: vms-tir.c:1496 vms-tir.c:1504
+#: vms-tir.c:1571 vms-tir.c:1583 vms-tir.c:1595 vms-tir.c:1607 vms-tir.c:1672
+#: vms-tir.c:1680 vms-tir.c:1688
 #, c-format
 msgid "%s: not fully implemented"
 msgstr "%s: chưa được thực hiện hoàn toàn"
 
-#: vms-tir.c:1562
+#: vms-tir.c:1746
 #, c-format
 msgid "obj code %d not found"
 msgstr "Không tìm thấy mã đối tượng %d"
 
-#: vms-tir.c:1870
+#: vms-tir.c:2019
+#, c-format
+msgid "Reloc size error in section %s"
+msgstr "Gặp lỗi kích cỡ sự định vị lại trong phần %s"
+
+#: vms-tir.c:2112 vms-tir.c:2129 vms-tir.c:2147 vms-tir.c:2159 vms-tir.c:2170
+#: vms-tir.c:2182
+#, c-format
+msgid "Unknown reloc %s + %s"
+msgstr "Không rõ sự định vị lại %s + %s"
+
+#: vms-tir.c:2249
+#, c-format
+msgid "Unknown symbol %s in command %s"
+msgstr "Gặp ký hiệu lạ %s trong câu lệnh %s"
+
+#: vms-tir.c:2504
 #, c-format
 msgid "SEC_RELOC with no relocs in section %s"
 msgstr "SEC_RELOC không có định vị lại trong phần %s"
 
-#: vms-tir.c:2152
+#: vms-tir.c:2556 vms-tir.c:2783
+#, c-format
+msgid "Size error in section %s"
+msgstr "Gặp lỗi kích cỡ trong phần %s"
+
+#: vms-tir.c:2725
+msgid "Spurious ALPHA_R_BSR reloc"
+msgstr "Gặp sự định vị lại ALPHA_R_BSR giả"
+
+#: vms-tir.c:2770
 #, c-format
 msgid "Unhandled relocation %s"
 msgstr "Định vị lại không được quản lý %s"
 
-#: xcofflink.c:566
+#: xcofflink.c:836
 #, c-format
 msgid "%s: XCOFF shared object when not producing XCOFF output"
 msgstr "%s: có đối tượng dùng chung XCOFF khi không xuất dữ liệu XCOFF"
 
-#: xcofflink.c:587
+#: xcofflink.c:857
 #, c-format
 msgid "%s: dynamic object with no .loader section"
 msgstr "%s đối tượng động không có phần .loader"
 
-#: xcofflink.c:1150
+#: xcofflink.c:1415
 msgid "%B: `%s' has line numbers but no enclosing section"
 msgstr "%B: « %s » có số thứ tự dòng mà không có phần bao bọc"
 
-#: xcofflink.c:1202
+#: xcofflink.c:1467
 msgid "%B: class %d symbol `%s' has no aux entries"
 msgstr "%B: hạng %d ký hiệu « %s » không có mục nhập phụ"
 
-#: xcofflink.c:1225
+#: xcofflink.c:1489
 msgid "%B: symbol `%s' has unrecognized csect type %d"
 msgstr "%B: ký hiệu « %s » có kiểu csect không được nhận ra %d"
 
-#: xcofflink.c:1237
+#: xcofflink.c:1501
 msgid "%B: bad XTY_ER symbol `%s': class %d scnum %d scnlen %d"
 msgstr "%B: ký hiệu XTY_ER sai « %s » hạng %d scnum %d scnlen %d"
 
-#: xcofflink.c:1273
+#: xcofflink.c:1530
 msgid "%B: XMC_TC0 symbol `%s' is class %d scnlen %d"
 msgstr "%B: ký hiệu XMC_TC0 « %s » là hạng %d scnlen %d"
 
-#: xcofflink.c:1419
+#: xcofflink.c:1676
 msgid "%B: csect `%s' not in enclosing section"
 msgstr "%B: csect « %s » không phải trong phần bao bọc"
 
-#: xcofflink.c:1526
+#: xcofflink.c:1783
 msgid "%B: misplaced XTY_LD `%s'"
 msgstr "%B: không đúng chỗ XTY_LD « %s »"
 
-#: xcofflink.c:1842
+#: xcofflink.c:2102
 msgid "%B: reloc %s:%d not in csect"
 msgstr "%B: định vị lại %s:%d không phải trong csect"
 
-#: xcofflink.c:2640
+#: xcofflink.c:3177
 #, c-format
 msgid "%s: no such symbol"
 msgstr "%s: không có ký hiệu như vậy"
 
-#: xcofflink.c:2869
+#: xcofflink.c:3282
 #, c-format
 msgid "warning: attempt to export undefined symbol `%s'"
 msgstr "cảnh báo : thử xuất ký hiệu chưa được xác định « %s »"
 
-#: xcofflink.c:3036
+#: xcofflink.c:3664
 msgid "error: undefined symbol __rtinit"
 msgstr "lỗi: chưa xác định ký hiệu __rtinit"
 
-#: xcofflink.c:3656
-#, c-format
-msgid "TOC overflow: 0x%lx > 0x10000; try -mminimal-toc when compiling"
-msgstr "Tràn TOC: 0x%lx > 0x10000; hãy thử « -mminimal-toc » khi biên dịch"
-
-#: xcofflink.c:4492
-msgid "%B: loader reloc in unrecognized section `%A'"
-msgstr "%B: định vị lại bộ nạp trong phần không được nhận ra « %A »"
+#: xcofflink.c:4041
+msgid "%B: loader reloc in unrecognized section `%s'"
+msgstr "%B: gặp sự định vị lại bộ nạp trong phần không được nhận ra « %s »"
 
-#: xcofflink.c:4513
+#: xcofflink.c:4052
 msgid "%B: `%s' in loader reloc but not loader sym"
 msgstr "%B: « %s » trong định vị lại bộ nạp nhưng không phải liên kết mềm đến bộ nạp"
 
-#: xcofflink.c:4528
+#: xcofflink.c:4068
 msgid "%B: loader reloc in read-only section %A"
 msgstr "%B: định vị lại bộ nạp trong phần chỉ đọc %A"
 
-#: xcofflink.c:4937 xcofflink.c:4999 xcofflink.c:5294
-#, c-format
-msgid "%s: loader reloc in unrecognized section `%s'"
-msgstr "%s: định vị lại bộ nạp trong phần không được nhận ra « %s »"
-
-#: xcofflink.c:5305
+#: xcofflink.c:5086
 #, c-format
-msgid "%s: `%s' in loader reloc but not loader sym"
-msgstr "%s: « %s » trong định vị lại bộ nạp nhưng không phải liên kết mềm đến bộ nạp"
+msgid "TOC overflow: 0x%lx > 0x10000; try -mminimal-toc when compiling"
+msgstr "Tràn TOC: 0x%lx > 0x10000; hãy thử « -mminimal-toc » khi biên dịch"
 
-#: elf32-ia64.c:1037 elf64-ia64.c:1037
+#: elf32-ia64.c:1050 elf64-ia64.c:1050
 msgid "%B: Can't relax br at 0x%lx in section `%A'. Please use brl or indirect branch."
 msgstr "%B: Không thể giảm nhẹ br ở 0x%lx trong phần « %A ». Hãy dùng brl hoặc nhánh gián tiếp."
 
-#: elf32-ia64.c:2742 elf64-ia64.c:2742
+#: elf32-ia64.c:2739 elf64-ia64.c:2739
 msgid "@pltoff reloc against local symbol"
 msgstr "định vị lại @pltoff so với ký hiệu cục bộ"
 
-#: elf32-ia64.c:4317 elf64-ia64.c:4317
+#: elf32-ia64.c:4314 elf64-ia64.c:4314
 #, c-format
 msgid "%s: short data segment overflowed (0x%lx >= 0x400000)"
 msgstr "%s: tràn đoạn dữ liệu ngắn (0x%lx ≥ 0x400000)"
 
-#: elf32-ia64.c:4328 elf64-ia64.c:4328
+#: elf32-ia64.c:4325 elf64-ia64.c:4325
 #, c-format
 msgid "%s: __gp does not cover short data segment"
 msgstr "%s: __gp không trải ra đoạn dữ liệu ngắn"
 
-#: elf32-ia64.c:4598 elf64-ia64.c:4598
+#: elf32-ia64.c:4595 elf64-ia64.c:4595
 msgid "%B: non-pic code with imm relocation against dynamic symbol `%s'"
 msgstr "%B: mã khác pic với định vị lại imm so với ký hiệu động « %s »"
 
-#: elf32-ia64.c:4665 elf64-ia64.c:4665
+#: elf32-ia64.c:4662 elf64-ia64.c:4662
 msgid "%B: @gprel relocation against dynamic symbol %s"
 msgstr "%B: định vị lại @gprel so với ký hiệu động « %s »"
 
-#: elf32-ia64.c:4728 elf64-ia64.c:4728
+#: elf32-ia64.c:4725 elf64-ia64.c:4725
 msgid "%B: linking non-pic code in a position independent executable"
 msgstr "%B: đang liên kết mã khác pin trong một tập tin có khả năng thực hiện mà không phụ thuộc vào vị trí"
 
-#: elf32-ia64.c:4865 elf64-ia64.c:4865
+#: elf32-ia64.c:4862 elf64-ia64.c:4862
 msgid "%B: @internal branch to dynamic symbol %s"
 msgstr "%B: nhánh @internal (nội bộ) tới ký hiệu động %s"
 
-#: elf32-ia64.c:4867 elf64-ia64.c:4867
+#: elf32-ia64.c:4864 elf64-ia64.c:4864
 msgid "%B: speculation fixup to dynamic symbol %s"
 msgstr "%B: sự sửa chữa suy đoán so với ký hiệu động %s"
 
-#: elf32-ia64.c:4869 elf64-ia64.c:4869
+#: elf32-ia64.c:4866 elf64-ia64.c:4866
 msgid "%B: @pcrel relocation against dynamic symbol %s"
 msgstr "%B: định vị lại @pcrel so với ký hiệu động %s"
 
-#: elf32-ia64.c:5066 elf64-ia64.c:5066
+#: elf32-ia64.c:5063 elf64-ia64.c:5063
 msgid "unsupported reloc"
 msgstr "định vị lại không được hỗ trợ"
 
-#: elf32-ia64.c:5104 elf64-ia64.c:5104
+#: elf32-ia64.c:5101 elf64-ia64.c:5101
 msgid "%B: missing TLS section for relocation %s against `%s' at 0x%lx in section `%A'."
 msgstr "%B: thiếu phần TLS để định vị lại %s đối với « %s » ở 0x%lx trong phần « %A »."
 
-#: elf32-ia64.c:5119 elf64-ia64.c:5119
+#: elf32-ia64.c:5116 elf64-ia64.c:5116
 msgid "%B: Can't relax br (%s) to `%s' at 0x%lx in section `%A' with size 0x%lx (> 0x1000000)."
 msgstr "%B: Không thể giảm nhẹ br (%s) tới « %s » tại 0x%lx trong phần « %A » với kích cỡ 0x%lx (> 0x1000000)."
 
-#: elf32-ia64.c:5375 elf64-ia64.c:5375
+#: elf32-ia64.c:5372 elf64-ia64.c:5372
 msgid "%B: linking trap-on-NULL-dereference with non-trapping files"
 msgstr "%B: đang liên kết trap-on-NULL-dereference với tập tin không đặt bẫy"
 
-#: elf32-ia64.c:5384 elf64-ia64.c:5384
+#: elf32-ia64.c:5381 elf64-ia64.c:5381
 msgid "%B: linking big-endian files with little-endian files"
 msgstr "%B: đang liên kết tập tin về cuối lớn với tập tin về cuối nhỏ"
 
-#: elf32-ia64.c:5393 elf64-ia64.c:5393
+#: elf32-ia64.c:5390 elf64-ia64.c:5390
 msgid "%B: linking 64-bit files with 32-bit files"
 msgstr "%B: đang liên kết tập tin 64-bit với tập tin 32-bit"
 
-#: elf32-ia64.c:5402 elf64-ia64.c:5402
+#: elf32-ia64.c:5399 elf64-ia64.c:5399
 msgid "%B: linking constant-gp files with non-constant-gp files"
 msgstr "%B: đang liên kết tập tin constant-gp với tập tin non-constant-gp"
 
-#: elf32-ia64.c:5412 elf64-ia64.c:5412
+#: elf32-ia64.c:5409 elf64-ia64.c:5409
 msgid "%B: linking auto-pic files with non-auto-pic files"
 msgstr "%B: đang liên kết tập tin auto-pic với tập tin non-auto-pic"
 
-#: peigen.c:1000 pepigen.c:1000 pex64igen.c:1000
+#: peigen.c:999 pepigen.c:999 pex64igen.c:999
 #, c-format
 msgid "%s: line number overflow: 0x%lx > 0xffff"
 msgstr "%s: tràn số thứ tự dòng: 0x%lx > 0xffff"
 
-#: peigen.c:1027 pepigen.c:1027 pex64igen.c:1027
+#: peigen.c:1026 pepigen.c:1026 pex64igen.c:1026
 msgid "Export Directory [.edata (or where ever we found it)]"
 msgstr "Thư mục Xuất [.edata (hoặc ở nơi nào chúng ta đã tìm nó)]"
 
-#: peigen.c:1028 pepigen.c:1028 pex64igen.c:1028
+#: peigen.c:1027 pepigen.c:1027 pex64igen.c:1027
 msgid "Import Directory [parts of .idata]"
 msgstr "Thư mục Nhập [các phần của .idata]"
 
-#: peigen.c:1029 pepigen.c:1029 pex64igen.c:1029
+#: peigen.c:1028 pepigen.c:1028 pex64igen.c:1028
 msgid "Resource Directory [.rsrc]"
 msgstr "Thư mục Tài nguyên [.rsrc]"
 
-#: peigen.c:1030 pepigen.c:1030 pex64igen.c:1030
+#: peigen.c:1029 pepigen.c:1029 pex64igen.c:1029
 msgid "Exception Directory [.pdata]"
 msgstr "Thư mục Ngoại lệ [.pdata]"
 
-#: peigen.c:1031 pepigen.c:1031 pex64igen.c:1031
+#: peigen.c:1030 pepigen.c:1030 pex64igen.c:1030
 msgid "Security Directory"
 msgstr "Thư mục Bảo mật"
 
-#: peigen.c:1032 pepigen.c:1032 pex64igen.c:1032
+#: peigen.c:1031 pepigen.c:1031 pex64igen.c:1031
 msgid "Base Relocation Directory [.reloc]"
 msgstr "Thư mục Định vị lại Cơ bản [.reloc]"
 
-#: peigen.c:1033 pepigen.c:1033 pex64igen.c:1033
+#: peigen.c:1032 pepigen.c:1032 pex64igen.c:1032
 msgid "Debug Directory"
 msgstr "Thư mục Gỡ lỗi"
 
-#: peigen.c:1034 pepigen.c:1034 pex64igen.c:1034
+#: peigen.c:1033 pepigen.c:1033 pex64igen.c:1033
 msgid "Description Directory"
 msgstr "Thư mục Mô tả"
 
-#: peigen.c:1035 pepigen.c:1035 pex64igen.c:1035
+#: peigen.c:1034 pepigen.c:1034 pex64igen.c:1034
 msgid "Special Directory"
 msgstr "Thư mục Đặc biệt"
 
-#: peigen.c:1036 pepigen.c:1036 pex64igen.c:1036
+#: peigen.c:1035 pepigen.c:1035 pex64igen.c:1035
 msgid "Thread Storage Directory [.tls]"
 msgstr "Thư mục Lưu trữ Mạch [.tls]"
 
-#: peigen.c:1037 pepigen.c:1037 pex64igen.c:1037
+#: peigen.c:1036 pepigen.c:1036 pex64igen.c:1036
 msgid "Load Configuration Directory"
 msgstr "Thư mục Cấu hình Nạp"
 
-#: peigen.c:1038 pepigen.c:1038 pex64igen.c:1038
+#: peigen.c:1037 pepigen.c:1037 pex64igen.c:1037
 msgid "Bound Import Directory"
 msgstr "Thư mục Nhập đã Đóng kết"
 
-#: peigen.c:1039 pepigen.c:1039 pex64igen.c:1039
+#: peigen.c:1038 pepigen.c:1038 pex64igen.c:1038
 msgid "Import Address Table Directory"
 msgstr "Thư mục Bảng Địa chỉ Nhập"
 
-#: peigen.c:1040 pepigen.c:1040 pex64igen.c:1040
+#: peigen.c:1039 pepigen.c:1039 pex64igen.c:1039
 msgid "Delay Import Directory"
 msgstr "Thư mục Nhập Hoãn"
 
-#: peigen.c:1041 pepigen.c:1041 pex64igen.c:1041
+#: peigen.c:1040 pepigen.c:1040 pex64igen.c:1040
 msgid "CLR Runtime Header"
 msgstr "Phần đầu Lúc chạy CLR"
 
-#: peigen.c:1042 pepigen.c:1042 pex64igen.c:1042
+#: peigen.c:1041 pepigen.c:1041 pex64igen.c:1041
 msgid "Reserved"
 msgstr "Dành riêng"
 
-#: peigen.c:1102 pepigen.c:1102 pex64igen.c:1102
+#: peigen.c:1101 pepigen.c:1101 pex64igen.c:1101
 #, c-format
 msgid ""
 "\n"
@@ -3539,7 +3848,7 @@ msgstr ""
 "\n"
 "Có một bảng nhập, nhưng không tìm thấy phần chứa nó\n"
 
-#: peigen.c:1107 pepigen.c:1107 pex64igen.c:1107
+#: peigen.c:1106 pepigen.c:1106 pex64igen.c:1106
 #, c-format
 msgid ""
 "\n"
@@ -3548,7 +3857,7 @@ msgstr ""
 "\n"
 "Có một bảng nhập trong %s tại 0x%lx\n"
 
-#: peigen.c:1150 pepigen.c:1150 pex64igen.c:1150
+#: peigen.c:1149 pepigen.c:1149 pex64igen.c:1149
 #, c-format
 msgid ""
 "\n"
@@ -3557,12 +3866,12 @@ msgstr ""
 "\n"
 "Bộ mô tả hàm được tìm tại địa chỉ đầu : %04lx\n"
 
-#: peigen.c:1153 pepigen.c:1153 pex64igen.c:1153
+#: peigen.c:1152 pepigen.c:1152 pex64igen.c:1152
 #, c-format
 msgid "\tcode-base %08lx toc (loadable/actual) %08lx/%08lx\n"
 msgstr "\tcơ bản mã %08lx toc (nạp được/thật) %08lx/%08lx\n"
 
-#: peigen.c:1161 pepigen.c:1161 pex64igen.c:1161
+#: peigen.c:1160 pepigen.c:1160 pex64igen.c:1160
 #, c-format
 msgid ""
 "\n"
@@ -3571,7 +3880,7 @@ msgstr ""
 "\n"
 "Không có phần reldata ! Vì thế chưa giải mã bộ mô tả hàm.\n"
 
-#: peigen.c:1166 pepigen.c:1166 pex64igen.c:1166
+#: peigen.c:1165 pepigen.c:1165 pex64igen.c:1165
 #, c-format
 msgid ""
 "\n"
@@ -3580,7 +3889,7 @@ msgstr ""
 "\n"
 "Các Bảng Nhập (phiên dịch %s nội dung phần)\n"
 
-#: peigen.c:1169 pepigen.c:1169 pex64igen.c:1169
+#: peigen.c:1168 pepigen.c:1168 pex64igen.c:1168
 #, c-format
 msgid ""
 " vma:            Hint    Time      Forward  DLL       First\n"
@@ -3589,7 +3898,7 @@ msgstr ""
 " vma:            Gợi ý    Giờ      Tiếp  DLL       Đầu\n"
 "                 Bảng   Nhãn     Dây    Tên      Thunk\n"
 
-#: peigen.c:1217 pepigen.c:1217 pex64igen.c:1217
+#: peigen.c:1216 pepigen.c:1216 pex64igen.c:1216
 #, c-format
 msgid ""
 "\n"
@@ -3598,12 +3907,12 @@ msgstr ""
 "\n"
 "\tTên DLL: %s\n"
 
-#: peigen.c:1228 pepigen.c:1228 pex64igen.c:1228
+#: peigen.c:1227 pepigen.c:1227 pex64igen.c:1227
 #, c-format
 msgid "\tvma:  Hint/Ord Member-Name Bound-To\n"
 msgstr "\tvma:  Gợi_ý/Thứ_tự Tên_thành_viên Đóng_kết_với\n"
 
-#: peigen.c:1253 pepigen.c:1253 pex64igen.c:1253
+#: peigen.c:1252 pepigen.c:1252 pex64igen.c:1252
 #, c-format
 msgid ""
 "\n"
@@ -3612,7 +3921,7 @@ msgstr ""
 "\n"
 "Có một thunk đầu tiên, nhưng không tìm thấy phần chứa nó\n"
 
-#: peigen.c:1418 pepigen.c:1418 pex64igen.c:1418
+#: peigen.c:1417 pepigen.c:1417 pex64igen.c:1417
 #, c-format
 msgid ""
 "\n"
@@ -3621,7 +3930,7 @@ msgstr ""
 "\n"
 "Có một bảng xuất, nhưng không tìm thấy phần chứa nó\n"
 
-#: peigen.c:1427 pepigen.c:1427 pex64igen.c:1427
+#: peigen.c:1426 pepigen.c:1426 pex64igen.c:1426
 #, c-format
 msgid ""
 "\n"
@@ -3630,7 +3939,7 @@ msgstr ""
 "\n"
 "Có một bảng xuất trong %s, nhưng nó không vừa trong phần đó\n"
 
-#: peigen.c:1433 pepigen.c:1433 pex64igen.c:1433
+#: peigen.c:1432 pepigen.c:1432 pex64igen.c:1432
 #, c-format
 msgid ""
 "\n"
@@ -3639,7 +3948,7 @@ msgstr ""
 "\n"
 "Có một bảng xuất trong %s tại 0x%lx\n"
 
-#: peigen.c:1461 pepigen.c:1461 pex64igen.c:1461
+#: peigen.c:1460 pepigen.c:1460 pex64igen.c:1460
 #, c-format
 msgid ""
 "\n"
@@ -3649,67 +3958,67 @@ msgstr ""
 "\n"
 "Các Bảng Xuất (phiên dịch %s nội dung phần)\n"
 
-#: peigen.c:1465 pepigen.c:1465 pex64igen.c:1465
+#: peigen.c:1464 pepigen.c:1464 pex64igen.c:1464
 #, c-format
 msgid "Export Flags \t\t\t%lx\n"
 msgstr "Cờ xuất \t\t\t%lx\n"
 
-#: peigen.c:1468 pepigen.c:1468 pex64igen.c:1468
+#: peigen.c:1467 pepigen.c:1467 pex64igen.c:1467
 #, c-format
 msgid "Time/Date stamp \t\t%lx\n"
 msgstr "Nhãn Ngày/Giờ \t\t%lx\n"
 
-#: peigen.c:1471 pepigen.c:1471 pex64igen.c:1471
+#: peigen.c:1470 pepigen.c:1470 pex64igen.c:1470
 #, c-format
 msgid "Major/Minor \t\t\t%d/%d\n"
 msgstr "Chính/Phụ \t\t\t%d/%d\n"
 
-#: peigen.c:1474 pepigen.c:1474 pex64igen.c:1474
+#: peigen.c:1473 pepigen.c:1473 pex64igen.c:1473
 #, c-format
 msgid "Name \t\t\t\t"
 msgstr "Tên \t\t\t\t"
 
-#: peigen.c:1480 pepigen.c:1480 pex64igen.c:1480
+#: peigen.c:1479 pepigen.c:1479 pex64igen.c:1479
 #, c-format
 msgid "Ordinal Base \t\t\t%ld\n"
 msgstr "Cơ bản thứ tự \t\t\t%ld\n"
 
-#: peigen.c:1483 pepigen.c:1483 pex64igen.c:1483
+#: peigen.c:1482 pepigen.c:1482 pex64igen.c:1482
 #, c-format
 msgid "Number in:\n"
 msgstr "Số trong:\n"
 
-#: peigen.c:1486 pepigen.c:1486 pex64igen.c:1486
+#: peigen.c:1485 pepigen.c:1485 pex64igen.c:1485
 #, c-format
 msgid "\tExport Address Table \t\t%08lx\n"
 msgstr "\tBảng Địa chỉ Xuất \t\t%08lx\n"
 
-#: peigen.c:1490 pepigen.c:1490 pex64igen.c:1490
+#: peigen.c:1489 pepigen.c:1489 pex64igen.c:1489
 #, c-format
 msgid "\t[Name Pointer/Ordinal] Table\t%08lx\n"
 msgstr "\t[Cái_chỉ_tên/Thứ_tự] Bảng\t%08lx\n"
 
-#: peigen.c:1493 pepigen.c:1493 pex64igen.c:1493
+#: peigen.c:1492 pepigen.c:1492 pex64igen.c:1492
 #, c-format
 msgid "Table Addresses\n"
 msgstr "Địa chỉ bảng\n"
 
-#: peigen.c:1496 pepigen.c:1496 pex64igen.c:1496
+#: peigen.c:1495 pepigen.c:1495 pex64igen.c:1495
 #, c-format
 msgid "\tExport Address Table \t\t"
 msgstr "\tBảng Địa chỉ Xuất \t\t"
 
-#: peigen.c:1501 pepigen.c:1501 pex64igen.c:1501
+#: peigen.c:1500 pepigen.c:1500 pex64igen.c:1500
 #, c-format
 msgid "\tName Pointer Table \t\t"
 msgstr "\tBảng Cái Chỉ Tên \t\t"
 
-#: peigen.c:1506 pepigen.c:1506 pex64igen.c:1506
+#: peigen.c:1505 pepigen.c:1505 pex64igen.c:1505
 #, c-format
 msgid "\tOrdinal Table \t\t\t"
 msgstr "\tBảng Thứ Tự \t\t\t"
 
-#: peigen.c:1520 pepigen.c:1520 pex64igen.c:1520
+#: peigen.c:1519 pepigen.c:1519 pex64igen.c:1519
 #, c-format
 msgid ""
 "\n"
@@ -3718,15 +4027,15 @@ msgstr ""
 "\n"
 "Bảng Địa chỉ Xuất — Cơ bản Thứ tự %ld\n"
 
-#: peigen.c:1539 pepigen.c:1539 pex64igen.c:1539
+#: peigen.c:1538 pepigen.c:1538 pex64igen.c:1538
 msgid "Forwarder RVA"
 msgstr "Bộ chuyển tiếp RVA"
 
-#: peigen.c:1550 pepigen.c:1550 pex64igen.c:1550
+#: peigen.c:1549 pepigen.c:1549 pex64igen.c:1549
 msgid "Export RVA"
 msgstr "Xuất RVA"
 
-#: peigen.c:1557 pepigen.c:1557 pex64igen.c:1557
+#: peigen.c:1556 pepigen.c:1556 pex64igen.c:1556
 #, c-format
 msgid ""
 "\n"
@@ -3735,28 +4044,18 @@ msgstr ""
 "\n"
 "Bảng [Cái chỉ Thứ tự/Tên]\n"
 
-#: peigen.c:1617 peigen.c:1796 pepigen.c:1617 pepigen.c:1796 pex64igen.c:1617
-#: pex64igen.c:1796
+#: peigen.c:1616 peigen.c:1795 pepigen.c:1616 pepigen.c:1795 pex64igen.c:1616
+#: pex64igen.c:1795
 #, c-format
 msgid "Warning, .pdata section size (%ld) is not a multiple of %d\n"
 msgstr "Cảnh báo : kích cỡ phần .pdata (%ld) không phải là bội số cho %d\n"
 
-#: peigen.c:1621 peigen.c:1800 pepigen.c:1621 pepigen.c:1800 pex64igen.c:1621
-#: pex64igen.c:1800
-#, c-format
-msgid ""
-"\n"
-"The Function Table (interpreted .pdata section contents)\n"
-msgstr ""
-"\n"
-"Bảng Hàm (phiên dịch nội dung phần .pdata)\n"
-
-#: peigen.c:1624 pepigen.c:1624 pex64igen.c:1624
+#: peigen.c:1623 pepigen.c:1623 pex64igen.c:1623
 #, c-format
 msgid " vma:\t\t\tBegin Address    End Address      Unwind Info\n"
 msgstr " vma:\t\t\tĐịa chi đầu    Địa chỉ cuối     Thông tin tháo ra\n"
 
-#: peigen.c:1626 pepigen.c:1626 pex64igen.c:1626
+#: peigen.c:1625 pepigen.c:1625 pex64igen.c:1625
 #, c-format
 msgid ""
 " vma:\t\tBegin    End      EH       EH       PrologEnd  Exception\n"
@@ -3765,22 +4064,22 @@ msgstr ""
 " vma:\t\tĐầu    Cuối      EH       EH       PrologEnd  Ngoại lệ\n"
 "     \t\tĐịa chỉ  Địa chỉ  Bộ quản lý  Dữ liệu     Địa chỉ    Mặt nạ\n"
 
-#: peigen.c:1696 pepigen.c:1696 pex64igen.c:1696
+#: peigen.c:1695 pepigen.c:1695 pex64igen.c:1695
 #, c-format
 msgid " Register save millicode"
 msgstr " Mili-mã lưu thanh ghi"
 
-#: peigen.c:1699 pepigen.c:1699 pex64igen.c:1699
+#: peigen.c:1698 pepigen.c:1698 pex64igen.c:1698
 #, c-format
 msgid " Register restore millicode"
 msgstr " Mili-mã phục hồi thanh ghi"
 
-#: peigen.c:1702 pepigen.c:1702 pex64igen.c:1702
+#: peigen.c:1701 pepigen.c:1701 pex64igen.c:1701
 #, c-format
 msgid " Glue code sequence"
 msgstr " Dãy mã nối lại"
 
-#: peigen.c:1802 pepigen.c:1802 pex64igen.c:1802
+#: peigen.c:1801 pepigen.c:1801 pex64igen.c:1801
 #, c-format
 msgid ""
 " vma:\t\tBegin    Prolog   Function Flags    Exception EH\n"
@@ -3826,22 +4125,22 @@ msgstr ""
 "\n"
 "Đặc tính 0x%x\n"
 
-#: peigen.c:2289 pepigen.c:2289 pex64igen.c:2289
+#: peigen.c:2292 pepigen.c:2292 pex64igen.c:2292
 msgid "%B: unable to fill in DataDictionary[1] because .idata$2 is missing"
 msgstr "%B: không thể điền vào DataDictionary[1] vì .idata$2 còn thiếu"
 
-#: peigen.c:2307 pepigen.c:2307 pex64igen.c:2307
+#: peigen.c:2312 pepigen.c:2312 pex64igen.c:2312
 msgid "%B: unable to fill in DataDictionary[1] because .idata$4 is missing"
 msgstr "%B: không thể điền vào DataDictionary[1] vì .idata$4 còn thiếu"
 
-#: peigen.c:2326 pepigen.c:2326 pex64igen.c:2326
+#: peigen.c:2333 pepigen.c:2333 pex64igen.c:2333
 msgid "%B: unable to fill in DataDictionary[12] because .idata$5 is missing"
 msgstr "%B: không thể điền vào DataDictionary[12] vì .idata$5 còn thiếu"
 
-#: peigen.c:2344 pepigen.c:2344 pex64igen.c:2344
+#: peigen.c:2353 pepigen.c:2353 pex64igen.c:2353
 msgid "%B: unable to fill in DataDictionary[PE_IMPORT_ADDRESS_TABLE (12)] because .idata$6 is missing"
 msgstr "%B: không thể điền vào DataDictionary[PE_IMPORT_ADDRESS_TABLE (12)] vì .idata$6 còn thiếu"
 
-#: peigen.c:2364 pepigen.c:2364 pex64igen.c:2364
+#: peigen.c:2375 pepigen.c:2375 pex64igen.c:2375
 msgid "%B: unable to fill in DataDictionary[9] because __tls_used is missing"
 msgstr "%B: không thể điền vào DataDictionary[9] vì __tls_used còn thiếu"

diff --git a/bfd/reloc.c b/bfd/reloc.c
index 3be29fe..0ea7a85 100644 (file)
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -4052,6 +4052,57 @@ ENUMDOC
   instructions
 
 ENUM
+  BFD_RELOC_RX_NEG8
+ENUMX
+  BFD_RELOC_RX_NEG16
+ENUMX
+  BFD_RELOC_RX_NEG24
+ENUMX
+  BFD_RELOC_RX_NEG32
+ENUMX
+  BFD_RELOC_RX_16_OP
+ENUMX
+  BFD_RELOC_RX_24_OP
+ENUMX
+  BFD_RELOC_RX_32_OP
+ENUMX
+  BFD_RELOC_RX_8U
+ENUMX
+  BFD_RELOC_RX_16U
+ENUMX
+  BFD_RELOC_RX_24U
+ENUMX
+  BFD_RELOC_RX_DIR3U_PCREL
+ENUMX
+  BFD_RELOC_RX_DIFF
+ENUMX
+  BFD_RELOC_RX_GPRELB
+ENUMX
+  BFD_RELOC_RX_GPRELW
+ENUMX
+  BFD_RELOC_RX_GPRELL
+ENUMX
+  BFD_RELOC_RX_SYM
+ENUMX
+  BFD_RELOC_RX_OP_SUBTRACT
+ENUMX
+  BFD_RELOC_RX_ABS8
+ENUMX
+  BFD_RELOC_RX_ABS16
+ENUMX
+  BFD_RELOC_RX_ABS32
+ENUMX
+  BFD_RELOC_RX_ABS16U
+ENUMX
+  BFD_RELOC_RX_ABS16UW
+ENUMX
+  BFD_RELOC_RX_ABS16UL
+ENUMX
+  BFD_RELOC_RX_RELAX
+ENUMDOC
+  Renesas RX Relocations.
+
+ENUM
   BFD_RELOC_390_12
 ENUMDOC
    Direct 12 bit.

diff --git a/bfd/sparclinux.c b/bfd/sparclinux.c
index f0c1e4a..7bb10d8 100644 (file)
--- a/bfd/sparclinux.c
+++ b/bfd/sparclinux.c
@@ -1,6 +1,6 @@
 /* BFD back-end for linux flavored sparc a.out binaries.
    Copyright 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2000, 2001, 2002,
-   2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
+   2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
 
    This file is part of BFD, the Binary File Descriptor library.
 
@@ -23,7 +23,6 @@
 #define ZMAGIC_DISK_BLOCK_SIZE 1024
 #define SEGMENT_SIZE           TARGET_PAGE_SIZE
 #define TEXT_START_ADDR                0x0
-#define N_SHARED_LIB(x)                0
 
 #define MACHTYPE_OK(mtype) ((mtype) == M_SPARC || (mtype) == M_UNKNOWN)
 

diff --git a/bfd/targets.c b/bfd/targets.c
index a33790b..347c6cd 100644 (file)
--- a/bfd/targets.c
+++ b/bfd/targets.c
@@ -641,6 +641,8 @@ extern const bfd_target bfd_elf32_pjl_vec;
 extern const bfd_target bfd_elf32_powerpc_vec;
 extern const bfd_target bfd_elf32_powerpcle_vec;
 extern const bfd_target bfd_elf32_powerpc_vxworks_vec;
+extern const bfd_target bfd_elf32_rx_le_vec;
+extern const bfd_target bfd_elf32_rx_be_vec;
 extern const bfd_target bfd_elf32_s390_vec;
 extern const bfd_target bfd_elf32_bigscore_vec;
 extern const bfd_target bfd_elf32_littlescore_vec;
@@ -978,6 +980,8 @@ static const bfd_target * const _bfd_target_vector[] =
        &bfd_elf32_powerpc_vec,
        &bfd_elf32_powerpc_vxworks_vec,
        &bfd_elf32_powerpcle_vec,
+       &bfd_elf32_rx_be_vec,
+       &bfd_elf32_rx_le_vec,
        &bfd_elf32_s390_vec,
 #ifdef BFD64
        &bfd_elf32_bigscore_vec,

diff --git a/bfd/vaxbsd.c b/bfd/vaxbsd.c
index cf566b9..21fbe58 100644 (file)
--- a/bfd/vaxbsd.c
+++ b/bfd/vaxbsd.c
@@ -1,5 +1,5 @@
 /* BFD back-end for BSD and Ultrix/VAX (1K page size) a.out-ish binaries.
-   Copyright 2002, 2003, 2005, 2007 Free Software Foundation, Inc.
+   Copyright 2002, 2003, 2005, 2007, 2009 Free Software Foundation, Inc.
 
    This file is part of BFD, the Binary File Descriptor library.
 
@@ -20,7 +20,6 @@
 
 #define N_HEADER_IN_TEXT(x) 0
 #define ENTRY_CAN_BE_ZERO
-#define N_SHARED_LIB(x) 0 /* Avoids warning */
 #define TEXT_START_ADDR 0
 #define TARGET_PAGE_SIZE 1024
 #define SEGMENT_SIZE TARGET_PAGE_SIZE

diff --git a/config.guess b/config.guess
index e3a2116..4ac8133 100755 (executable)
--- a/config.guess
+++ b/config.guess
@@ -4,7 +4,7 @@
 #   2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
 #   Free Software Foundation, Inc.
 
-timestamp='2009-06-10'
+timestamp='2009-09-23'
 
 # This file is free software; you can redistribute it and/or modify it
 # under the terms of the GNU General Public License as published by
@@ -27,16 +27,16 @@ timestamp='2009-06-10'
 # the same distribution terms that you use for the rest of that program.
 
 
-# Originally written by Per Bothner <per@bothner.com>.
-# Please send patches to <config-patches@gnu.org>.  Submit a context
-# diff and a properly formatted ChangeLog entry.
+# Originally written by Per Bothner.  Please send patches (context
+# diff format) to <config-patches@gnu.org> and include a ChangeLog
+# entry.
 #
 # This script attempts to guess a canonical system name similar to
 # config.sub.  If it succeeds, it prints the system name on stdout, and
 # exits with 0.  Otherwise, it exits with 1.
 #
-# The plan is that this can be called by configure scripts if you
-# don't specify an explicit build system type.
+# You can get the latest version of this script from:
+# http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.guess;hb=HEAD
 
 me=`echo "$0" | sed -e 's,.*/,,'`
 
@@ -854,6 +854,20 @@ EOF
     i*86:Minix:*:*)
        echo ${UNAME_MACHINE}-pc-minix
        exit ;;
+    alpha:Linux:*:*)
+       case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in
+         EV5)   UNAME_MACHINE=alphaev5 ;;
+         EV56)  UNAME_MACHINE=alphaev56 ;;
+         PCA56) UNAME_MACHINE=alphapca56 ;;
+         PCA57) UNAME_MACHINE=alphapca56 ;;
+         EV6)   UNAME_MACHINE=alphaev6 ;;
+         EV67)  UNAME_MACHINE=alphaev67 ;;
+         EV68*) UNAME_MACHINE=alphaev68 ;;
+        esac
+       objdump --private-headers /bin/sh | grep -q ld.so.1
+       if test "$?" = 0 ; then LIBC="libc1" ; else LIBC="" ; fi
+       echo ${UNAME_MACHINE}-unknown-linux-gnu${LIBC}
+       exit ;;
     arm*:Linux:*:*)
        eval $set_cc_for_build
        if echo __ARM_EABI__ | $CC_FOR_BUILD -E - 2>/dev/null \
@@ -876,6 +890,9 @@ EOF
     frv:Linux:*:*)
        echo frv-unknown-linux-gnu
        exit ;;
+    i*86:Linux:*:*)
+       echo ${UNAME_MACHINE}-pc-linux-gnu
+       exit ;;
     ia64:Linux:*:*)
        echo ${UNAME_MACHINE}-unknown-linux-gnu
        exit ;;
@@ -911,29 +928,12 @@ EOF
     or32:Linux:*:*)
        echo or32-unknown-linux-gnu
        exit ;;
-    ppc:Linux:*:*)
-       echo powerpc-unknown-linux-gnu
-       exit ;;
-    ppc64:Linux:*:*)
-       echo powerpc64-unknown-linux-gnu
-       exit ;;
-    alpha:Linux:*:*)
-       case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in
-         EV5)   UNAME_MACHINE=alphaev5 ;;
-         EV56)  UNAME_MACHINE=alphaev56 ;;
-         PCA56) UNAME_MACHINE=alphapca56 ;;
-         PCA57) UNAME_MACHINE=alphapca56 ;;
-         EV6)   UNAME_MACHINE=alphaev6 ;;
-         EV67)  UNAME_MACHINE=alphaev67 ;;
-         EV68*) UNAME_MACHINE=alphaev68 ;;
-        esac
-       objdump --private-headers /bin/sh | grep -q ld.so.1
-       if test "$?" = 0 ; then LIBC="libc1" ; else LIBC="" ; fi
-       echo ${UNAME_MACHINE}-unknown-linux-gnu${LIBC}
-       exit ;;
     padre:Linux:*:*)
        echo sparc-unknown-linux-gnu
        exit ;;
+    parisc64:Linux:*:* | hppa64:Linux:*:*)
+       echo hppa64-unknown-linux-gnu
+       exit ;;
     parisc:Linux:*:* | hppa:Linux:*:*)
        # Look for CPU level
        case `grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2` in
@@ -942,8 +942,11 @@ EOF
          *)    echo hppa-unknown-linux-gnu ;;
        esac
        exit ;;
-    parisc64:Linux:*:* | hppa64:Linux:*:*)
-       echo hppa64-unknown-linux-gnu
+    ppc64:Linux:*:*)
+       echo powerpc64-unknown-linux-gnu
+       exit ;;
+    ppc:Linux:*:*)
+       echo powerpc-unknown-linux-gnu
        exit ;;
     s390:Linux:*:* | s390x:Linux:*:*)
        echo ${UNAME_MACHINE}-ibm-linux
@@ -966,58 +969,6 @@ EOF
     xtensa*:Linux:*:*)
        echo ${UNAME_MACHINE}-unknown-linux-gnu
        exit ;;
-    i*86:Linux:*:*)
-       # The BFD linker knows what the default object file format is, so
-       # first see if it will tell us. cd to the root directory to prevent
-       # problems with other programs or directories called `ld' in the path.
-       # Set LC_ALL=C to ensure ld outputs messages in English.
-       ld_supported_targets=`cd /; LC_ALL=C ld --help 2>&1 \
-                        | sed -ne '/supported targets:/!d
-                                   s/[         ][      ]*/ /g
-                                   s/.*supported targets: *//
-                                   s/ .*//
-                                   p'`
-        case "$ld_supported_targets" in
-         elf32-i386)
-               TENTATIVE="${UNAME_MACHINE}-pc-linux-gnu"
-               ;;
-       esac
-       # Determine whether the default compiler is a.out or elf
-       eval $set_cc_for_build
-       sed 's/^        //' << EOF >$dummy.c
-       #include <features.h>
-       #ifdef __ELF__
-       # ifdef __GLIBC__
-       #  if __GLIBC__ >= 2
-       LIBC=gnu
-       #  else
-       LIBC=gnulibc1
-       #  endif
-       # else
-       LIBC=gnulibc1
-       # endif
-       #else
-       #if defined(__INTEL_COMPILER) || defined(__PGI) || defined(__SUNPRO_C) || defined(__SUNPRO_CC)
-       LIBC=gnu
-       #else
-       LIBC=gnuaout
-       #endif
-       #endif
-       #ifdef __dietlibc__
-       LIBC=dietlibc
-       #endif
-EOF
-       eval "`$CC_FOR_BUILD -E $dummy.c 2>/dev/null | sed -n '
-           /^LIBC/{
-               s: ::g
-               p
-           }'`"
-       test x"${LIBC}" != x && {
-               echo "${UNAME_MACHINE}-pc-linux-${LIBC}"
-               exit
-       }
-       test x"${TENTATIVE}" != x && { echo "${TENTATIVE}"; exit; }
-       ;;
     i*86:DYNIX/ptx:4*:*)
        # ptx 4.0 does uname -s correctly, with DYNIX/ptx in there.
        # earlier versions are messed up and put the nodename in both
@@ -1247,6 +1198,16 @@ EOF
     *:Darwin:*:*)
        UNAME_PROCESSOR=`uname -p` || UNAME_PROCESSOR=unknown
        case $UNAME_PROCESSOR in
+           i386)
+               eval $set_cc_for_build
+               if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then
+                 if (echo '#ifdef __LP64__'; echo IS_64BIT_ARCH; echo '#endif') | \
+                     (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \
+                     grep IS_64BIT_ARCH >/dev/null
+                 then
+                     UNAME_PROCESSOR="x86_64"
+                 fi
+               fi ;;
            unknown) UNAME_PROCESSOR=powerpc ;;
        esac
        echo ${UNAME_PROCESSOR}-apple-darwin${UNAME_RELEASE}

diff --git a/config.sub b/config.sub
index 32d764c..b26b47a 100755 (executable)
--- a/config.sub
+++ b/config.sub
@@ -4,7 +4,7 @@
 #   2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
 #   Free Software Foundation, Inc.
 
-timestamp='2009-08-17'
+timestamp='2009-09-23'
 
 # This file is (in principle) common to ALL GNU software.
 # The presence of a machine in this file suggests that SOME GNU software
@@ -32,13 +32,16 @@ timestamp='2009-08-17'
 
 
 # Please send patches to <config-patches@gnu.org>.  Submit a context
-# diff and a properly formatted ChangeLog entry.
+# diff and a properly formatted GNU ChangeLog entry.
 #
 # Configuration subroutine to validate and canonicalize a configuration type.
 # Supply the specified configuration type as an argument.
 # If it is invalid, we print an error message on stderr and exit with code 1.
 # Otherwise, we print the canonical config type on stdout and succeed.
 
+# You can get the latest version of this script from:
+# http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.sub;hb=HEAD
+
 # This file is supposed to be the same for all GNU packages
 # and recognize all the CPU types, system types and aliases
 # that are meaningful with *any* GNU software.
@@ -284,6 +287,7 @@ case $basic_machine in
        | pdp10 | pdp11 | pj | pjl \
        | powerpc | powerpc64 | powerpc64le | powerpcle | ppcbe \
        | pyramid \
+       | rx \
        | score \
        | sh | sh[1234] | sh[24]a | sh[24]aeb | sh[23]e | sh[34]eb | sheb | shbe | shle | sh[1234]le | sh3ele \
        | sh64 | sh64le \
@@ -368,7 +372,7 @@ case $basic_machine in
        | pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \
        | powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* | ppcbe-* \
        | pyramid-* \
-       | romp-* | rs6000-* \
+       | romp-* | rs6000-* | rx-* \
        | sh-* | sh[1234]-* | sh[24]a-* | sh[24]aeb-* | sh[23]e-* | sh[34]eb-* | sheb-* | shbe-* \
        | shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \
        | sparc-* | sparc64-* | sparc64b-* | sparc64v-* | sparc86x-* | sparclet-* \

diff --git a/cpu/ChangeLog b/cpu/ChangeLog
new file mode 100644 (file)
index 0000000..2b8c45a
--- /dev/null
+++ b/cpu/ChangeLog
@@ -0,0 +1,707 @@
+2009-09-25  Alan Modra  <amodra@bigpond.net.au>
+
+       * m32r.cpu (stb-plus): Typo fix.
+
+2009-09-23  Doug Evans  <dje@sebabeach.org>
+
+       * m32r.cpu (sth-plus): Fix address mode and calculation.
+       (stb-plus): Ditto.
+       (clrpsw): Fix mask calculation.
+       (bset, bclr, btst): Make mode in bit calculation match expression.
+
+       * xc16x.cpu (rtl-version): Set to 0.8.
+       (gr-names, ext-names,psw-names): Update, print-name -> enum-prefix,
+       make uppercase.  Remove unnecessary name-prefix spec.
+       (grb-names, conditioncode-names, extconditioncode-names): Ditto.
+       (grb8-names, r8-names, regmem8-names, regdiv8-names): Ditto.
+       (reg0-name, reg0-name1, regbmem8-names, memgr8-names): Ditto.
+       (h-cr): New hardware.
+       (muls): Comment out parts that won't compile, add fixme.
+       (mulu, divl, divlu, jmpabs, jmpa-, jmprel, jbc, jnbs, callr): Ditto.
+       (scxti, scxtmg, scxtm, bclear, bclr18, bset19, bitset, bmov): Ditto.
+       (bmovn, band, bor, bxor, bcmp, bfldl, bfldh): Ditto.
+
+2009-07-16  Doug Evans  <dje@sebabeach.org>
+
+       * cpu/simplify.inc (*): One line doc strings don't need \n.
+       (df): Invoke define-full-ifield instead of claiming it's an alias.
+       (dno): Define.
+       (dnop): Mark as deprecated.
+
+2009-06-22  Alan Modra  <amodra@bigpond.net.au>
+
+       * m32c.opc (parse_lab_5_3): Use correct enum.
+
+2009-01-07  Hans-Peter Nilsson  <hp@axis.com>
+
+       * frv.cpu (mabshs): Explicitly sign-extend arguments of abs to DI.
+       (DI-ext-HI, DI-ext-UHI, DI-ext-DI): New pmacros.
+       (media-arith-sat-semantics): Explicitly sign- or zero-extend
+       arguments of "operation" to DI using "mode" and the new pmacros.
+
+2009-01-03  Hans-Peter Nilsson  <hp@axis.com>
+
+       * cris.cpu (cris-implemented-writable-specregs-v32): Correct size
+       of number 2, PID.
+
+2008-12-23  Jon Beniston <jon@beniston.com>
+
+       * lm32.cpu: New file.
+       * lm32.opc: New file.
+
+2008-01-29  Alan Modra  <amodra@bigpond.net.au>
+
+       * mt.opc (parse_imm16): Apply 2007-09-26 opcodes/mt-asm.c change
+       to source.
+
+2007-10-22  Hans-Peter Nilsson  <hp@axis.com>
+
+       * cris.cpu (movs, movu): Use result of extension operation when
+       updating flags.
+
+2007-07-04  Nick Clifton  <nickc@redhat.com>
+
+       * cris.cpu: Update copyright notice to refer to GPLv3.
+       * frv.cpu, frv.opc, iq10.cpu, iq2000m.cpu, iq2000.opc, m32c.cpu,
+       m32c.opc, m32r.cpu, m32r.opc, mt.cpu, mt.opc, sh64-compact.cpu,
+       sh64-media.cpu, sh.cpu, sh.opc, simplify.inc, xc16x.cpu,
+       xc16x.opc: Likewise.
+       * iq2000.cpu: Fix copyright notice to refer to FSF.
+
+2007-04-30  Mark Salter  <msalter@sadr.localdomain>
+
+       * frv.cpu (spr-names): Support new coprocessor SPR registers.
+
+2007-04-20  Nick Clifton  <nickc@redhat.com>
+
+       * xc16x.cpu: Restore after accidentally overwriting this file with
+       xc16x.opc.
+
+2007-03-29  DJ Delorie  <dj@redhat.com>
+
+       * m32c.cpu (Imm-8-s4n): Fix print hook.
+       (Lab-24-8, Lab-32-8, Lab-40-8): Fix.
+       (arith-jnz-imm4-dst-defn): Make relaxable.
+       (arith-jnz16-imm4-dst-defn): Fix encodings.
+
+2007-03-20  DJ Delorie  <dj@redhat.com>
+
+       * m32c.cpu (f-dsp-40-u20, f-dsp-48-u20, Dsp-40-u20, Dsp-40-u20,
+       mem20): New.
+       (src16-16-20-An-relative-*): New.
+       (dst16-*-20-An-relative-*): New.
+       (dst16-16-16sa-*): New
+       (dst16-16-16ar-*): New
+       (dst32-16-16sa-Unprefixed-*): New
+       (jsri): Fix operands.
+       (setzx): Fix encoding.
+       
+2007-03-08  Alan Modra  <amodra@bigpond.net.au>
+
+       * m32r.opc: Formatting.
+
+2006-05-22  Nick Clifton  <nickc@redhat.com>
+
+       * iq2000.cpu: Fix include paths for iq2000m.cpu and iq10.cpu.
+
+2006-04-10  DJ Delorie  <dj@redhat.com>
+
+       * m32c.opc (parse_unsigned_bitbase): Take a new parameter which
+       decides if this function accepts symbolic constants or not.
+       (parse_signed_bitbase): Likewise.
+       (parse_unsigned_bitbase8): Pass the new parameter.
+       (parse_unsigned_bitbase11): Likewise.
+       (parse_unsigned_bitbase16): Likewise.
+       (parse_unsigned_bitbase19): Likewise.
+       (parse_unsigned_bitbase27): Likewise.
+       (parse_signed_bitbase8): Likewise.
+       (parse_signed_bitbase11): Likewise.
+       (parse_signed_bitbase19): Likewise.
+       
+2006-03-13  DJ Delorie  <dj@redhat.com>
+
+       * m32c.cpu (Bit3-S): New.
+       (btst:s): New.
+       * m32c.opc (parse_bit3_S): New.
+
+       * m32c.cpu (decimal-subtraction16-insn): Add second operand.
+       (btst): Add optional :G suffix for MACH32.
+       (or.b:S): New.
+       (pop.w:G): Add optional :G suffix for MACH16.
+       (push.b.imm): Fix syntax.
+
+2006-03-10  DJ Delorie  <dj@redhat.com>
+
+       * m32c.cpu (mul.l): New.
+       (mulu.l): New.
+
+2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
+
+       * xc16x.opc (parse_hash): Return NULL if the input was parsed or
+       an error message otherwise.
+       (parse_dot, parse_pof, parse_pag, parse_sof, parse_seg): Likewise.
+       Fix up comments to correctly describe the functions.
+
+2006-02-24  DJ Delorie  <dj@redhat.com>
+
+       * m32c.cpu (RL_TYPE): New attribute, with macros.
+       (Lab-8-24): Add RELAX.
+       (unary-insn-defn-g, binary-arith-imm-dst-defn,
+       binary-arith-imm4-dst-defn): Add 1ADDR attribute.
+       (binary-arith-src-dst-defn): Add 2ADDR attribute.
+       (jcnd16-5, jcnd16, jcnd32, jmp16.s, jmp16.b, jmp16.w, jmp16.a,
+       jmp32.s, jmp32.b, jmp32.w, jmp32.a, jsr16.w, jsr16.a): Add JUMP
+       attribute.
+       (jsri16, jsri32): Add 1ADDR attribute.
+       (jsr32.w, jsr32.a): Add JUMP attribute.
+       
+2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
+            Anil Paranjape   <anilp1@kpitcummins.com>
+            Shilin Shakti    <shilins@kpitcummins.com>
+
+       * xc16x.cpu: New file containing complete CGEN specific XC16X CPU
+       description.
+       * xc16x.opc: New file containing supporting XC16C routines.
+
+2006-02-10  Nick Clifton  <nickc@redhat.com>
+
+       * iq2000.opc (parse_hi16): Truncate shifted values to 16 bits.
+
+2006-01-06  DJ Delorie  <dj@redhat.com>
+
+       * m32c.cpu (mov.w:q): Fix mode.
+       (push32.b.imm): Likewise, for the comment.
+
+2005-12-16  Nathan Sidwell  <nathan@codesourcery.com>
+
+       Second part of ms1 to mt renaming.
+       * mt.cpu (define-arch, define-isa): Set name to mt.
+       (define-mach): Adjust.
+       * mt.opc (CGEN_ASM_HASH): Update.
+       (mt_asm_hash, mt_cgen_insn_supported): Renamed.
+       (parse_loopsize, parse_imm16): Adjust.
+
+2005-12-13  DJ Delorie  <dj@redhat.com>
+
+       * m32c.cpu (jsri): Fix order so register names aren't treated as
+       symbols.
+       (indexb, indexbd, indexbs, indexl, indexld, indexls, indexw,
+       indexwd, indexws): Fix encodings.
+
+2005-12-12  Nathan Sidwell  <nathan@codesourcery.com>
+
+       * mt.cpu: Rename from ms1.cpu.
+       * mt.opc: Rename from ms1.opc.
+
+2005-12-06  Hans-Peter Nilsson  <hp@axis.com>
+
+       * cris.cpu (simplecris-common-writable-specregs)
+       (simplecris-common-readable-specregs): Split from
+       simplecris-common-specregs.  All users changed.
+       (cris-implemented-writable-specregs-v0)
+       (cris-implemented-readable-specregs-v0): Similar from
+       cris-implemented-specregs-v0.
+       (cris-implemented-writable-specregs-v3)
+       (cris-implemented-readable-specregs-v3)
+       (cris-implemented-writable-specregs-v8)
+       (cris-implemented-readable-specregs-v8)
+       (cris-implemented-writable-specregs-v10)
+       (cris-implemented-readable-specregs-v10)
+       (cris-implemented-writable-specregs-v32)
+       (cris-implemented-readable-specregs-v32): Similar.
+       (bdap-32-pc, move-m-pcplus-p0, move-m-spplus-p8): New
+       insns and specializations.
+
+2005-11-08  Nathan Sidwell  <nathan@codesourcery.com>
+
+       Add ms2
+       * ms1.cpu (ms2, ms2bf): New architecture variant, cpu, machine and
+       model.
+       (f-uu8, f-uu1, f-imm16l, f-loopo, f-cb1sel, f-cb2sel, f-cb1incr,
+       f-cb2incr, f-rc3): New fields.
+       (LOOP): New instruction.
+       (JAL-HAZARD): New hazard.
+       (imm16o, loopsize, imm16l, rc3, cb1sel, cb2sel, cb1incr, cb2incr):
+       New operands.
+       (mul, muli, dbnz, iflush): Enable for ms2
+       (jal, reti): Has JAL-HAZARD.
+       (ldctxt, ldfb, stfb): Only ms1.
+       (fbcb): Only ms1,ms1-003.
+       (wfbinc, mefbinc, wfbincr, mwfbincr, fbcbincs, mfbcbincs,
+       fbcbincrs, mfbcbincrs): Enable for ms2.
+       (loop, loopu, dfbc, dwfb, fbwfb, dfbr): New ms2 insns.
+       * ms1.opc (parse_loopsize): New.
+       (parse_imm16): hi16/lo16 relocs are applicable to IMM16L.
+       (print_pcrel): New.
+
+2005-10-28  Dave Brolley  <brolley@redhat.com>
+
+       Contribute the following change:
+       2003-09-24  Dave Brolley  <brolley@redhat.com>
+
+       * frv.opc: Use CGEN_ATTR_VALUE_ENUM_TYPE in place of
+       CGEN_ATTR_VALUE_TYPE.
+       * m32c.opc (m32c_cgen_insn_supported): Use CGEN_INSN_BITSET_ATTR_VALUE.
+       Use cgen_bitset_intersect_p.
+
+2005-10-27  DJ Delorie  <dj@redhat.com>
+
+       * m32c.cpu (Imm-8-s4n, Imm-12-s4n): New.
+       (arith-jnz16-imm4-dst-defn, arith-jnz32-imm4-dst-defn,
+       arith-jnz-imm4-dst-mach, arith-jnz-imm4-dst): Keep track of which
+       imm operand is needed.
+       (adjnz, sbjnz): Pass the right operands.
+       (unary-insn-defn, unary16-defn, unary32-defn, unary-insn-mach,
+       unary-insn): Add -g variants for opcodes that need to support :G.
+       (not.BW:G, push.BW:G): Call it.
+       (stzx16-imm8-imm8-dsp8sb, stzx16-imm8-imm8-dsp8fb,
+       stzx16-imm8-imm8-abs16): Fix operand typos.
+       * m32c.opc (m32c_asm_hash): Support bnCND.
+       (parse_signed4n, print_signed4n): New.
+       
+2005-10-26  DJ Delorie  <dj@redhat.com>
+
+       * m32c.cpu (f-dsp-8-s24, Dsp-8-s24): New.
+       (mov-dspsp-dst-defn, mov-src-dspsp-defn, mov16-dspsp-dst-defn,
+       mov16-src-dspsp-defn, mov32-dspsp-dst-defn, mov32-src-dspsp-defn):
+       dsp8[sp] is signed.
+       (mov.WL:S #imm,A0/A1): dsp24 is signed (i.e. -0x800000..0xffffff).
+       (mov.BW:S r0,r1): Fix typo r1l->r1.
+       (tst): Allow :G suffix.
+       * m32c.opc (parse_signed24): New, for -0x800000..0xffffff.
+
+2005-10-26  Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
+
+       * m32r.opc (parse_hi16): Do not assume a 32-bit host word size.
+
+2005-10-25  DJ Delorie  <dj@redhat.com>
+
+       * m32c.cpu (add16-bQ-sp,add16-wQ-sp): Fix to allow either width by
+       making one a macro of the other.
+
+2005-10-21  DJ Delorie  <dj@redhat.com>
+
+       * m32c.cpu (lde, ste): Add dsp[a0] and [a1a] addressing.
+       (indexb, indexbd, indexbs, indexw, indexwd, indexws, indexl,
+       indexld, indexls): .w variants have `1' bit.
+       (rot32.b): QI, not SI.
+       (rot32.w): HI, not SI.
+       (xchg16): HI for .w variant.
+
+2005-10-19  Nick Clifton  <nickc@redhat.com>
+
+       * m32r.opc (parse_slo16): Fix bad application of previous patch.
+
+2005-10-18  Andreas Schwab  <schwab@suse.de>
+
+       * m32r.opc (parse_slo16): Better version of previous patch.
+
+2005-10-14  Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
+
+       * cpu/m32r.opc (parse_slo16): Do not assume a 32-bit host word
+       size.
+
+2005-07-25  DJ Delorie  <dj@redhat.com>
+
+       * m32c.opc (parse_unsigned8): Add %dsp8().
+       (parse_signed8): Add %hi8().
+       (parse_unsigned16): Add %dsp16().
+       (parse_signed16): Add %lo16() and %hi16().
+       (parse_lab_5_3): Make valuep a bfd_vma *.
+
+2005-07-18  Nick Clifton  <nickc@redhat.com>
+
+       * m32c.cpu (f-16-8, f-24-8, f-32-16, f-dsp-8-u24): New opcode
+       components.
+       (f-lab32-jmp-s): Fix insertion sequence.
+       (Dsp-8-u24, Lab-5-3, Lab32-jmp-s): New operands.
+       (Dsp-40-s8): Make parameter be signed.
+       (Dsp-40-s16): Likewise.
+       (Dsp-48-s8): Likewise.
+       (Dsp-48-s16): Likewise.
+       (Imm-13-u3): Likewise. (Despite its name!)
+       (BitBase16-16-s8): Make the parameter be unsigned.
+       (BitBase16-8-u11-S): Likewise.
+       (Lab-8-8, Lab-8-16, Lab-16-8, jcnd16-5, jcnd16, jcnd32, jmp16.s,
+       jmp16.b, jmp16.w, jmp32.s, jmp32.b, jmp32.w, jsp16.w, jsr32.w): Allow
+       relaxation.
+
+       * m32c.opc: Fix formatting.
+       Use safe-ctype.h instead of ctype.h
+       Move duplicated code sequences into a macro.
+       Fix compile time warnings about signedness mismatches.
+       Remove dead code.
+       (parse_lab_5_3): New parser function.
+       
+2005-07-16  Jim Blandy  <jimb@redhat.com>
+
+       * m32c.opc (m32c_cgen_insn_supported): Use int, not CGEN_BITSET,
+       to represent isa sets.
+
+2005-07-15  Jim Blandy  <jimb@redhat.com>
+
+       * m32c.cpu, m32c.opc: Fix copyright.
+
+2005-07-14  Jim Blandy  <jimb@redhat.com>
+
+       * m32c.cpu, m32c.opc: Machine description for the Renesas M32C.
+
+2005-07-14  Alan Modra  <amodra@bigpond.net.au>
+
+       * ms1.opc (print_dollarhex): Correct format string.
+
+2005-07-06  Alan Modra  <amodra@bigpond.net.au>
+
+       * iq2000.cpu: Include from binutils cpu dir.
+
+2005-07-05  Nick Clifton  <nickc@redhat.com>
+
+       * iq2000.opc (parse_lo16, parse_mlo16): Make value parameter
+       unsigned in order to avoid compile time warnings about sign
+       conflicts.
+
+       * ms1.opc (parse_*): Likewise.
+       (parse_imm16): Use a "void *" as it is passed both signed and
+       unsigned arguments.
+
+2005-07-01  Nick Clifton  <nickc@redhat.com>
+
+       * frv.opc: Update to ISO C90 function declaration style.
+       * iq2000.opc: Likewise.
+       * m32r.opc: Likewise.
+       * sh.opc: Likewise.
+
+2005-06-15  Dave Brolley  <brolley@redhat.com>
+
+       Contributed by Red Hat.
+       * ms1.cpu: New file.  Written by Nick Clifton, Stan Cox.
+       * ms1.opc: New file.  Written by Stan Cox.
+
+2005-05-10  Nick Clifton  <nickc@redhat.com>
+
+       * Update the address and phone number of the FSF organization in
+       the GPL notices in the following files:
+       cris.cpu, frv.cpu, frv.opc, iq10.cpu, iq2000.opc, iq2000m.cpu,
+       m32r.cpu, m32r.opc, sh.cpu, sh.opc, sh64-compact.cpu,
+       sh64-media.cpu, simplify.inc
+
+2005-02-24  Alan Modra  <amodra@bigpond.net.au>
+
+       * frv.opc (parse_A): Warning fix.
+
+2005-02-23  Nick Clifton  <nickc@redhat.com>
+
+       * frv.opc: Fixed compile time warnings about differing signed'ness
+       of pointers passed to functions.
+       * m32r.opc: Likewise.
+
+2005-02-11  Nick Clifton  <nickc@redhat.com>
+
+       * iq2000.opc (parse_jtargq10): Change type of valuep argument to
+       'bfd_vma *' in order avoid compile time warning message.
+
+2005-01-28  Hans-Peter Nilsson  <hp@axis.com>
+
+       * cris.cpu (mstep): Add missing insn.
+
+2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
+
+       2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
+       * frv.cpu: Add support for TLS annotations in loads and calll.
+       * frv.opc (parse_symbolic_address): New.
+       (parse_ldd_annotation): New.
+       (parse_call_annotation): New.
+       (parse_ld_annotation): New.
+       (parse_ulo16, parse_uslo16): Use parse_symbolic_address.
+       Introduce TLS relocations.
+       (parse_d12, parse_s12, parse_u12): Likewise.
+       (parse_uhi16): Likewise.  Fix constant checking on 64-bit host.
+       (parse_call_label, print_at): New.
+
+2004-12-21  Mikael Starvik  <starvik@axis.com>
+
+       * cris.cpu (cris-set-mem): Correct integral write semantics.
+
+2004-11-29  Hans-Peter Nilsson  <hp@axis.com>
+
+       * cris.cpu: New file.
+
+2004-11-15  Michael K. Lechner <mike.lechner@gmail.com>
+
+       * iq2000.cpu: Added quotes around macro arguments so that they
+       will work with newer versions of guile.
+
+2004-10-27  Nick Clifton  <nickc@redhat.com>
+
+       * iq2000m.cpu (pkrlr1, pkrlr30, rbr1, rbr30, rxr1, rxr30, wbr1,
+       wbr1u, wbr30, wbr30u, wxr1, wxr1u, wxr30, wxr30u): Add an index
+       operand.
+       * iq2000.cpu (dnop index): Rename to _index to avoid complications
+       with guile.
+
+2004-08-27  Richard Sandiford  <rsandifo@redhat.com>
+
+       * frv.cpu (cfmovs): Change UNIT attribute to FMALL.
+
+2004-05-15  Nick Clifton  <nickc@redhat.com>
+
+       * iq2000.opc (iq2000_cgen_insn_supported): Make 'insn' argument const.
+
+2004-03-30  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
+
+       * m32r.opc (parse_hi16): Fixed shigh(0xffff8000) bug.
+
+2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
+
+       * frv.cpu (define-arch frv): Add fr450 mach.
+       (define-mach fr450): New.
+       (define-model fr450): New.  Add profile units to every fr450 insn.
+       (define-attr UNIT): Add MDCUTSSI.
+       (define-attr FR450-MAJOR): New enum.  Add to every fr450 insn.
+       (define-attr AUDIO): New boolean.
+       (f-LRAE, f-LRAD, f-LRAS, f-TLBPRopx, f-TLBPRL)
+       (f-LRA-null, f-TLBPR-null): New fields.
+       (scr0, scr1, scr2, scr3, imavr1, damvr1, cxnr, ttbr)
+       (tplr, tppr, tpxr, timerh, timerl, timerd, btbr): New SPRs.
+       (LRAE, LRAD, LRAS, TLBPRopx, TLBPRL): New operands.
+       (LRA-null, TLBPR-null): New macros.
+       (iacc-multiply-r-r, slass, scutss, int-arith-ss-r-r): Add AUDIO attr.
+       (load-real-address): New macro.
+       (lrai, lrad, tlbpr): New instructions.
+       (media-cut-acc, media-cut-acc-ss): Add fr450-major argument.
+       (mcut, mcuti, mcutss, mcutssi): Adjust accordingly.
+       (mdcutssi): Change UNIT attribute to MDCUTSSI.
+       (media-low-clear-semantics, media-scope-limit-semantics)
+       (media-quad-limit, media-quad-shift): New macros.
+       (mqlclrhs, mqlmths, mqsllhi, mqsrahi): New instructions.
+       * frv.opc (frv_is_branch_major, frv_is_float_major, frv_is_media_major)
+       (frv_is_branch_insn, frv_is_float_insn, frv_is_media_insn)
+       (frv_vliw_reset, frv_vliw_add_insn): Handle bfd_mach_fr450.
+       (fr450_unit_mapping): New array.
+       (fr400_unit_mapping, fr500_unit_mapping, fr550_unit_mapping): Add entry
+       for new MDCUTSSI unit.
+       (fr450_check_insn_major_constraints): New function.
+       (check_insn_major_constraints): Use it.
+
+2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
+
+       * frv.cpu (nsdiv, nudiv, nsdivi, nudivi): Remove fr400 profiling unit.
+       (scutss): Change unit to I0.
+       (calll, callil, ccalll): Add missing FR550-MAJOR and profile unit.
+       (mqsaths): Fix FR400-MAJOR categorization.
+       (media-quad-multiply-cross-acc, media-quad-cross-multiply-cross-acc)
+       (media-quad-cross-multiply-acc): Change unit from MDUALACC to FMALL.
+       * frv.opc (fr400_check_insn_major_constraints): Check for (M-2,M-1)
+       combinations.
+
+2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
+
+       * frv.cpu (r-store, r-store-dual, r-store-quad): Delete.
+       (rstb, rsth, rst, rstd, rstq): Delete.
+       (rstbf, rsthf, rstf, rstdf, rstqf): Delete.
+
+2004-02-23  Nick Clifton  <nickc@redhat.com>
+
+       * Apply these patches from Renesas:
+
+       2004-02-10  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
+
+       * cpu/m32r.opc (my_print_insn): Fixed incorrect output when
+       disassembling codes for 0x*2 addresses.
+
+       2003-12-15  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
+
+       * cpu/m32r.cpu: Add PIPE_O attribute to "pop" instruction.
+
+       2003-12-03  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
+
+       * cpu/m32r.cpu : Add new model m32r2.
+       Add new instructions.
+       Replace occurrances of 'Mitsubishi' with 'Renesas'.
+       Changed PIPE attr of push from O to OS.
+       Care for Little-endian of M32R.
+       * cpu/m32r.opc (CGEN_DIS_HASH, my_print_insn):
+       Care for Little-endian of M32R.
+       (parse_slo16): signed extension for value.
+
+2004-02-20  Andrew Cagney  <cagney@redhat.com>
+
+       * m32r.opc, m32r.cpu: New files.  Written by , Doug Evans, Nick
+       Clifton, Ben Elliston, Matthew Green, and Andrew Haley.
+
+       * sh.cpu, sh.opc, sh64-compact.cpu, sh64-media.cpu: New files, all
+       written by Ben Elliston.
+
+2004-01-14  Richard Sandiford  <rsandifo@redhat.com>
+
+       * frv.cpu (UNIT): Add IACC.
+       (iacc-multiply-r-r): Use it.
+       * frv.opc (fr400_unit_mapping): Add entry for IACC.
+       (fr500_unit_mapping, fr550_unit_mapping): Likewise.
+
+2004-01-06  Alexandre Oliva  <aoliva@redhat.com>
+
+       2003-12-19  Alexandre Oliva  <aoliva@redhat.com>
+       * frv.opc (parse_ulo16, parse_uhi16, parse_d12): Fix some
+       cut&paste errors in shifting/truncating numerical operands.
+       2003-08-08  Alexandre Oliva  <aoliva@redhat.com>
+       * frv.opc (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
+       (parse_uslo16): Likewise.
+       (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
+       (parse_d12): Parse gotoff12 and gotofffuncdesc12.
+       (parse_s12): Likewise.
+       2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
+       * frv.opc (parse_ulo16): Parse gotlo and gotfuncdesclo.
+       (parse_uslo16): Likewise.
+       (parse_uhi16): Parse gothi and gotfuncdeschi.
+       (parse_d12): Parse got12 and gotfuncdesc12.
+       (parse_s12): Likewise.
+
+2003-10-10  Dave Brolley  <brolley@redhat.com>
+
+       * frv.cpu (dnpmop): New p-macro.
+       (GRdoublek): Use dnpmop.
+       (CPRdoublek, FRdoublei, FRdoublej, FRdoublek): Ditto.
+       (store-double-r-r): Use (.sym regtype doublek).
+       (r-store-double): Ditto.
+       (store-double-r-r-u): Ditto.
+       (conditional-store-double): Ditto.
+       (conditional-store-double-u): Ditto.
+       (store-double-r-simm): Ditto.
+       (fmovs): Assign to UNIT FMALL.
+
+2003-10-06  Dave Brolley  <brolley@redhat.com>
+
+       * frv.cpu, frv.opc: Add support for fr550.
+
+2003-09-24  Dave Brolley  <brolley@redhat.com>
+
+       * frv.cpu (u-commit): New modelling unit for fr500.
+       (mwtaccg): Use frv_ref_SI to reference ACC40Sk as an input operand.
+       (commit-r): Use u-commit model for fr500.
+       (commit): Ditto.
+       (conditional-float-binary-op): Take profiling data as an argument.
+       Update callers.
+       (ne-float-binary-op): Ditto.
+
+2003-09-19  Michael Snyder  <msnyder@redhat.com>
+
+       * frv.cpu (nldqi): Delete unimplemented instruction.
+
+2003-09-12  Dave Brolley  <brolley@redhat.com>
+
+       * frv.cpu (u-clrgr, u-clrfr): New units of model fr500.
+       (clear-ne-flag-r): Pass insn profiling in as an argument. Call
+       frv_ref_SI to get input register referenced for profiling.
+       (clear-ne-flag-all): Pass insn profiling in as an argument.
+       (clrgr,clrfr,clrga,clrfa): Add profiling information.
+
+2003-09-11  Michael Snyder  <msnyder@redhat.com>
+
+       * frv.cpu: Typographical corrections.
+
+2003-09-09  Dave Brolley  <brolley@redhat.com>
+
+       * frv.cpu (media-dual-complex): Change UNIT to FMALL.
+       (conditional-media-dual-complex, media-quad-complex): Likewise.
+
+2003-09-04  Dave Brolley  <brolley@redhat.com>
+
+       * frv.cpu (register-transfer): Pass in all attributes in on argument.
+       Update all callers.
+       (conditional-register-transfer): Ditto.
+       (cache-preload): Ditto.
+       (floating-point-conversion): Ditto.
+       (floating-point-neg): Ditto.
+       (float-abs): Ditto.
+       (float-binary-op-s): Ditto.
+       (conditional-float-binary-op): Ditto.
+       (ne-float-binary-op): Ditto.
+       (float-dual-arith): Ditto.
+       (ne-float-dual-arith): Ditto.
+
+2003-09-03  Dave Brolley  <brolley@redhat.com>
+
+       * frv.opc (parse_A, parse_A0, parse_A1): New parse handlers.
+       * frv.cpu (UNIT): Add IALL, FMALL, FMLOW, STORE, SCAN, DCPL, MDUALACC,
+       MCLRACC-1.
+       (A): Removed operand.
+       (A0,A1): New operands replace operand A.
+       (mnop): Now a real insn
+       (mclracc): Removed insn.
+       (mclracc-0, mclracc-1): New insns replace mclracc.
+       (all insns): Use new UNIT attributes.
+
+2003-08-21  Nick Clifton  <nickc@redhat.com>
+
+       * frv.cpu (mbtoh): Replace input parameter to u-media-dual-expand
+       and u-media-dual-btoh with output parameter.
+       (cmbtoh): Add profiling hack.
+
+2003-08-19  Michael Snyder  <msnyder@redhat.com>
+
+       * frv.cpu: Fix typo, Frintkeven -> FRintkeven
+
+2003-06-10  Doug Evans  <dje@sebabeach.org>
+
+       * frv.cpu: Add IDOC attribute.
+
+2003-06-06  Andrew Cagney  <cagney@redhat.com>
+
+       Contributed by Red Hat.
+       * iq2000.cpu: New file.  Written by Ben Elliston, Jeff Johnston,
+       Stan Cox, and Frank Ch. Eigler.
+       * iq2000.opc: New file.  Written by Ben Elliston, Frank
+       Ch. Eigler, Chris Moller, Jeff Johnston, and Stan Cox.
+       * iq2000m.cpu: New file.  Written by Jeff Johnston.
+       * iq10.cpu: New file.  Written by Jeff Johnston.
+
+2003-06-05  Nick Clifton  <nickc@redhat.com>
+
+       * frv.cpu (FRintieven): New operand.  An even-numbered only
+       version of the FRinti operand.
+       (FRintjeven): Likewise for FRintj.
+       (FRintkeven): Likewise for FRintk.
+       (mdcutssi, media-dual-word-rotate-r-r, mqsaths,
+       media-quad-arith-sat-semantics, media-quad-arith-sat,
+       conditional-media-quad-arith-sat, mdunpackh,
+       media-quad-multiply-semantics, media-quad-multiply,
+       conditional-media-quad-multiply, media-quad-complex-i,
+       media-quad-multiply-acc-semantics, media-quad-multiply-acc,
+       conditional-media-quad-multiply-acc, munpackh,
+       media-quad-multiply-cross-acc-semantics, mdpackh,
+       media-quad-multiply-cross-acc, mbtoh-semantics,
+       media-quad-cross-multiply-cross-acc-semantics,
+       media-quad-cross-multiply-cross-acc, mbtoh, mhtob-semantics,
+       media-quad-cross-multiply-acc-semantics, cmbtoh,
+       media-quad-cross-multiply-acc, media-quad-complex, mhtob,
+       media-expand-halfword-to-double-semantics, mexpdhd, cmexpdhd,
+       cmhtob): Use new operands.
+       * frv.opc (CGEN_VERBOSE_ASSEMBLER_ERRORS): Define.
+       (parse_even_register): New function.
+
+2003-06-03  Nick Clifton  <nickc@redhat.com>
+
+       * frv.cpu (media-dual-word-rotate-r-r): Use a signed 6-bit
+       immediate value not unsigned.
+
+2003-06-03  Andrew Cagney  <cagney@redhat.com>
+
+       Contributed by Red Hat.
+       * frv.cpu: New file.  Written by Dave Brolley, Catherine Moore,
+       and Eric Christopher.
+       * frv.opc: New file.  Written by Catherine Moore, and Dave
+       Brolley.
+       * simplify.inc: New file.  Written by Doug Evans.
+
+2003-05-02  Andrew Cagney  <cagney@redhat.com>
+
+       * New file.
+
+\f
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:

diff --git a/cpu/cris.cpu b/cpu/cris.cpu
new file mode 100644 (file)
index 0000000..97b4458
--- /dev/null
+++ b/cpu/cris.cpu
@@ -0,0 +1,4553 @@
+; CRIS CPU description.  -*- Scheme -*-
+;
+; Copyright 2003, 2004, 2007, 2009 Free Software Foundation, Inc.
+;
+; Contributed by Axis Communications AB.
+;
+; This file is part of the GNU Binutils.
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 3 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, write to the Free Software
+; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+; MA 02110-1301, USA.
+
+(include "simplify.inc")
+
+;;;;;;;;;;;;;;;;;; -pmacro (generic ones)
+
+(define-pmacro (.car2 l) (.apply (.pmacro (a b) a) l))
+(define-pmacro (.cadr2 l) (.apply (.pmacro (a b) b) l))
+(define-pmacro (SI-ext x) "How to sign-extend a dword to dword (a nop)" x)
+(define-pmacro (HI-ext x) "How to sign-extend a word to dword" (ext SI x))
+(define-pmacro (QI-ext x) "How to sign-extend a byte to dword" (ext SI x))
+(define-pmacro (SI-zext x) "How to zero-extend a dword to dword (a nop)" x)
+(define-pmacro (HI-zext x) "How to zero-extend a word to dword" (zext SI x))
+(define-pmacro (QI-zext x) "How to zero-extend a byte to dword" (zext SI x))
+(define-pmacro
+  (define-pmacro-map x)
+  "On a list ((x0 y0) .. (xN yN)), 0 <= m <= N, (define-pmacro xm ym)"
+  (.splice
+   begin
+   (.unsplice
+    (.map
+     (.pmacro (l) (.apply (.pmacro (xm ym) (define-pmacro xm ym)) l)) x)))
+)
+
+;;;;;;;;;;;;;;;;;; -arch -isa -cpu -model
+
+(define-arch
+  (name cris)
+  (comment "Axis Communications CRIS")
+  (default-alignment unaligned)
+  (insn-lsb0? #t)
+  (machs crisv0 crisv3 crisv8 crisv10 crisv32)
+  (isas cris)
+)
+
+(define-isa
+  (name cris)
+  (base-insn-bitsize 16)
+  (liw-insns 1)
+  (parallel-insns 1)
+)
+
+(define-pmacro
+  (define-cpu-cris x-suffix x-comment)
+  "Define a CRIS CPU family"
+  (define-cpu
+    (name (.sym cris x-suffix f))
+    (comment x-comment)
+    (endian little)
+    ; CGEN-FIXME: Should be deduced from the default?
+    (word-bitsize 32)
+    (file-transform (.str x-suffix))
+  )
+)
+
+; Useful when there's a need to iterate over all models.
+(define-pmacro (cris-cpu-model-numbers)
+  "List of CRIS CPU model numbers (version register contents)"
+  (0 3 8 10 32)
+)
+
+(define-pmacro (cris-cpu-models)
+  "List of CRIS CPU model names"
+  (.map (.pmacro (n) (.sym v n)) (cris-cpu-model-numbers))
+)
+
+; Mapping from model name to number.
+(define-pmacro-map
+  (.map (.pmacro (n) ((.sym v n -number) n))
+       (cris-cpu-model-numbers)))
+
+; FIXME: Rationalize these rules.
+; CPU names must be distinct from the architecture name and machine names.
+; The "b" suffix stands for "base" and is the convention.
+; The "f" suffix stands for "family" and is the convention.
+; We ignore the "b" convention, partly because v0 isn't really a "base", at
+; least not for some aspects of v32.
+(define-cpu-cris v0 "CRIS base family")
+(define-cpu-cris v3 "CRIS v3 family")
+(define-cpu-cris v8 "CRIS v8 family")
+(define-cpu-cris v10 "CRIS v10 family")
+(define-cpu-cris v32 "CRIS v32 family")
+
+(define-pmacro MACH-PRE-V32 (MACH crisv0,crisv3,crisv8,crisv10))
+(define-pmacro MACH-V3-UP (MACH crisv3,crisv8,crisv10,crisv32))
+(define-pmacro MACH-V32 (MACH crisv32))
+(define-pmacro MACH-PC MACH-PRE-V32)
+(define-pmacro MACH-ACR MACH-V32)
+(define-pmacro MACH-BRANCH-OFFSET-AT-INSN MACH-V32)
+(define-pmacro MACH-BRANCH-OFFSET-AFTER-INSN MACH-PRE-V32)
+
+(define-pmacro
+  current-mach-is-v32
+  "Whether the generated code is for V32.  See comment at h-v32."
+  (reg h-v32)
+)
+
+(define-pmacro (define-mach-cris x-suffix x-comment x-name)
+  "Define a CRIS mach"
+  (define-mach
+    (name (.sym cris x-suffix))
+    ; They're all called "cris" in bfd.  Watch out for breakages for some
+    ; uses.
+    (bfd-name x-name)
+    (comment x-comment)
+    (cpu (.sym cris x-suffix f)))
+)
+
+(define-mach-cris v0 "Generic CRIS v0 CPU, ETRAX 1 .. 3" "cris")
+(define-mach-cris v3 "Generic CRIS v3 CPU, ETRAX 4" "cris")
+(define-mach-cris v8 "Generic CRIS v8 CPU, ETRAX 100" "cris")
+(define-mach-cris v10 "Generic CRIS v10 CPU, ETRAX 100 LX" "cris")
+(define-mach-cris v32 "Generic CRIS v32 CPU, ETRAX FS" "crisv32")
+
+(define-pmacro (define-model-simplecris x-name x-comment)
+  "Define a simple CRIS model"
+  (define-model
+    (name (.sym cris x-name))
+    (comment x-comment)
+    (mach (.sym cris x-name))
+
+    (unit u-exec "Execution Unit" () 1 1 () () () ())
+    (unit u-mem "Memory Unit" () 1 1 () () () ())
+
+    (unit u-const16 "Fetch 16-bit operand" () 1 1 () () () ())
+    (unit u-const32 "Fetch 32-bit operand" () 1 1
+         () () () ())
+    ; Used in special-case insn, for example arithmetic with PC destination.
+    (unit u-stall "Stall unit" () 1 1 () () () ())
+    (unit u-skip4 "Skip 4 bytes" () 1 1 () () () ())
+    (unit u-multiply "Multiply Unit" () 1 1 ((MACH crisv10)) () () ())
+    (unit u-movem "Movem Unit" () 1 1 ()
+         ((Rd INT -1))
+         () ()))
+)
+
+(define-model-simplecris v0 "Model of CRIS v0, ETRAX 1 .. 3")
+(define-model-simplecris v3 "Model of CRIS v3, ETRAX 4")
+(define-model-simplecris v8 "Model of CRIS v8, ETRAX 100")
+(define-model-simplecris v10 "Model of CRIS v10, ETRAX 100 LX")
+
+; For some reason, we get an error:
+;  Generating arch.h ...
+;  ERROR: In procedure vector-ref:
+;  ERROR: Wrong type argument in position 1: ()
+; if we include timings for machs that we don't generate sims for.
+; Last checked: CVS as of 2004-11-18.
+; CGEN-FIXME: Looks like another CGEN bug.  When it's fixed (or when
+; generating sims for v0, v3 or v8), add 0, 3 and 8 to
+; simplecris-timing-models.  But before that, simplecris-timing-x has to
+; be rewritten to work on a multiple-element-list, not assume a single
+; element.  (A change which seems likely to depend on lexical scoping for
+; macros to be introduced: try the obvious implementation.)
+(define-pmacro simplecris-timing-models (10))
+(define-pmacro (simplecris-common-timing x-units)
+  "Make timing models, using x-units for all simplecris-timing-models"
+  ; CGEN-FIXME: Another CGEN bug: the part (.unsplice (10)) will remain
+  ; unexpanded in (.sym crisv (.unsplice (10)) if we write this as
+  ; ((.splice (.sym crisv (.unsplice simplecris-timing-models))
+  ;          (.unsplice x-units)))
+  ((.splice (.sym crisv (.apply (.pmacro (x) x) simplecris-timing-models))
+           (.unsplice x-units)))
+)
+
+(define-pmacro-map
+  (
+   ; Timing for memory instructions running on a simple cris model.
+   ((simplecris-mem-timing)    (simplecris-common-timing
+                                ((unit u-mem) (unit u-exec))))
+   ; Timing for movem instructions running on a simple cris model.
+   ((simplecris-movem-timing)  (simplecris-common-timing
+                                ((unit u-movem) (unit u-exec))))
+   ; Similar, for an 8- or 16-bit constant ([PC+]) operand.
+   ((simplecris-const-timing-HI)
+                               (simplecris-common-timing
+                                ((unit u-const16) (unit u-exec))))
+   ; Similar, for a 32-bit constant ([PC+]) operand.
+   ((simplecris-const-timing-SI)
+                               (simplecris-common-timing
+                                ((unit u-const32) (unit u-exec))))
+   ; Similar, no particular operand.
+   ((simplecris-timing)                (simplecris-common-timing
+                                ((unit u-exec)))))
+)
+
+(define-model
+  (name crisv32)
+  (comment "Model of CRISv32")
+  (mach crisv32)
+
+  (state
+    ; Bitmask of h-gr register (0..15) and h-sr register (17..31)
+    ; modified by 3rd previous insn, updated by the u-exec unit.
+    ; Because there's no need to mark writes to special registers BZ and
+    ; WZ, bit 16 is for jump mark and bit 20 for memory-write mark.
+    (prev-prev-prev-modf-regs UINT)
+
+    ; Ditto for the 2nd previous insn.
+    (prev-prev-modf-regs UINT)
+
+    ; Ditto for the previous insn.
+    (prev-modf-regs UINT)
+
+    ; Bit-mask for regs modified by the current insn, propagated to
+    ; prev-modf-regs.
+    (modf-regs UINT)
+
+    ; Registers loaded by movem are not forwarded to the execution
+    ; stage, so we need to insert stall-cycles for ordinary insns
+    ; accessing such registers.  In addition to the *modf-regs
+    ; above, these are set to tell *ordinary* insns which registers
+    ; are inaccessible.
+
+    (prev-prev-prev-movem-dest-regs UINT)
+
+    ; Ditto for the 2nd previous insn.
+    (prev-prev-movem-dest-regs UINT)
+
+    ; Ditto for the previous insn.
+    (prev-movem-dest-regs UINT)
+
+    ; Bit-mask for regs modified by the current insn, propagated to
+    ; prev-movem-dest-regs.
+    (movem-dest-regs UINT))
+
+  ; It seems this pipeline description isn't used at all; this is just
+  ; for show.
+  ; Noteworthy is the placement of the memory stage before the execute stage.
+  (pipeline all "" () ((fetch) (decode) (memory) (execute) (writeback)))
+
+  ; Units that contribute only a constant pipeline delay are not included.
+  (unit u-mem "Memory Unit" () 1 1 ()
+       ((Rs INT -1))
+       () ())
+
+  ; Artificial units for read/write-related hazard accounting.
+  (unit u-mem-r "Memory Unit Read" () 1 1 () () () ())
+  (unit u-mem-w "Memory Unit Write" () 1 1 () () () ())
+
+  (unit u-movem-rtom "Movem-to-memory Unit" () 1 1 ()
+       ((Rs INT -1) (Rd INT -1))
+       () ())
+  (unit u-movem-mtor "Movem-to-register Unit" () 1 1 ()
+       ((Rs INT -1) (Rd INT -1))
+       () ())
+  (unit u-multiply "Multiply Unit" () 1 1 ()
+       ((Rs INT -1) (Rd INT -1))
+       () ())
+  (unit u-branch "Branch Unit" () 1 1 ()
+       ()
+       () ())
+  (unit u-jump-r "Jump-to-register Unit" () 1 1 ()
+       ((Rs INT -1))
+       () ())
+  (unit u-jump-sr "Jump-to-special-register Unit" () 1 1 ()
+       ((Ps INT -1))
+       () ())
+  (unit u-jump "JAS/BAS Unit, saving PC" () 1 1 ()
+       ()
+       ((Pd INT -1)) ())
+
+  ; To keep track of PC; not really functional units.
+  (unit u-const16 "Fetch 16-bit operand" () 1 1 () () () ())
+  (unit u-const32 "Fetch 32-bit operand" () 1 1 () () () ())
+  (unit u-skip4 "Skip 4 bytes" () 1 1 () () () ())
+
+  ; For v32, we need to keep track of inputs (for movem destination
+  ; cycle penalties) and output (for e.g. memory source and jump
+  ; source cycle penalties).
+  (unit u-exec "Execution Unit" () 1 1 ()
+       ((Rd INT -1) (Rs INT -1))
+       ((Rd INT -1))
+       ())
+
+  ; Special case of u-exec for movem: don't treat Rd as an incoming
+  ; parameter.
+  (unit u-exec-movem "Execution Unit" () 1 1 ()
+       ((Rs INT -1))
+       ((Rd INT -1))
+       ())
+
+  ; Special case of u-exec when the destination is a special
+  ; register.
+  (unit u-exec-to-sr "Execution Unit" () 1 1 ()
+       ((Rs INT -1))
+       ((Pd INT -1)) ())
+)
+
+(define-pmacro (crisv32-timing-destreg d)
+  "Timing for instructions running on a crisv32 model"
+  ((crisv32
+    (.splice unit u-exec (.unsplice d))))
+)
+(define-pmacro (crisv32-timing) (crisv32-timing-destreg ()))
+
+(define-pmacro (cris-timing-Rd-sfield)
+  (crisv32-timing-destreg ((out Rd Rd-sfield)))
+)
+
+(define-pmacro (crisv32-timing-c-HI)
+  ((crisv32 (unit u-const16) (unit u-exec)))
+)
+
+(define-pmacro-map
+  ((crisv32-timing-c-QI crisv32-timing-c-HI)
+   ((crisv32-timing-c-SI) ((crisv32 (unit u-const32) (unit u-exec))))
+   ((crisv32-timing-c-sr-SI) ((crisv32 (unit u-const32) (unit u-exec-to-sr))))
+   ((crisv32-reg-sr-timing) ((crisv32 (unit u-exec-to-sr))))
+   ((crisv32-mem-sr-timing)
+    ((crisv32 (unit u-mem) (unit u-mem-r) (unit u-exec-to-sr))))
+   ((crisv32-mem-timing) ((crisv32 (unit u-mem) (unit u-mem-r) (unit u-exec))))
+   ((crisv32-mem-write-timing) ((crisv32 (unit u-mem) (unit u-exec) (unit u-mem-w)))))
+)
+
+(define-pmacro-map
+  (
+   ; Timing for instructions using memory operands.
+   ((cris-mem-timing)          (.splice (.unsplice (simplecris-mem-timing))
+                                        (.unsplice (crisv32-mem-timing))))
+  ; Timing for instructions using memory operands.
+   ((cris-mem-write-timing)    (.splice
+                                (.unsplice (simplecris-mem-timing))
+                                (.unsplice (crisv32-mem-write-timing))))
+   ; Timing for moves from general register to special register.
+   ((cris-reg-sr-timing)       (.splice (.unsplice (simplecris-timing))
+                                        (.unsplice (crisv32-reg-sr-timing))))
+   ; Timing for moves from memory to special register.
+   ((cris-mem-sr-timing)       (.splice (.unsplice (simplecris-mem-timing))
+                                        (.unsplice (crisv32-mem-sr-timing))))
+   ; Timing for non-mul, non-memory, non-special-register, 16-bit instructions.
+   ((cris-timing)              (.splice (.unsplice (simplecris-timing))
+                                        (.unsplice (crisv32-timing))))
+   ; Timing for instructions with 8- or 16-bit constant operand ([PC+]).
+   ((cris-timing-const-HI)     (.splice
+                                (.unsplice (simplecris-const-timing-HI))
+                                (.unsplice (crisv32-timing-c-HI))))
+   ; Timing for instructions with a 32-bit constant operand ([PC+]).
+   ((cris-timing-const-SI)     (.splice
+                                (.unsplice (simplecris-const-timing-SI))
+                                (.unsplice (crisv32-timing-c-SI))))
+   ; Like cris-timing-const-SI, but destination special register.
+   ((cris-timing-const-sr-SI)  (.splice
+                                (.unsplice (simplecris-const-timing-SI))
+                                (.unsplice (crisv32-timing-c-sr-SI))))
+   ; Like cris-timing-const-HI, but destination special register.
+   ((cris-timing-const-sr-HI)  (.splice
+                                (.unsplice (simplecris-const-timing-HI))
+                                (.unsplice (crisv32-timing-c-sr-SI)))))
+)
+
+(define-pmacro cris-timing-const-QI cris-timing-const-HI)
+(define-pmacro cris-timing-const-sr-QI cris-timing-const-sr-HI)
+
+(define-pmacro (simplecris-common-writable-specregs)
+  "The common writable special registers in pre-v32 models."
+  ((HI 5) (SI 9) (SI 10) (SI 11) (SI 12) (SI 13))
+)
+
+(define-pmacro (simplecris-common-readable-specregs)
+  "The common readable special registers in pre-v32 models."
+  (.splice (.unsplice (simplecris-common-writable-specregs))
+          (QI 0) (QI 1) (HI 4) (SI 8))
+)
+
+(define-pmacro (cris-implemented-writable-specregs-v0)
+  "Special writable registers in v0 and their sizes"
+  (.splice (.unsplice (simplecris-common-writable-specregs)) (HI 6) (HI 7))
+)
+(define-pmacro
+  cris-implemented-specregs-const-v0
+  cris-implemented-writable-specregs-v0
+)
+(define-pmacro (cris-implemented-readable-specregs-v0)
+  "Special readable registers in v0 and their sizes"
+  (.splice (.unsplice (simplecris-common-readable-specregs)) (HI 6) (HI 7))
+)
+
+(define-pmacro (cris-implemented-writable-specregs-v3)
+  "Special writable registers in v3 and their sizes"
+  (.splice (.unsplice (cris-implemented-writable-specregs-v0)) (SI 14))
+)
+(define-pmacro
+  cris-implemented-specregs-const-v3
+  cris-implemented-writable-specregs-v3
+)
+(define-pmacro (cris-implemented-readable-specregs-v3)
+  "Special readable registers in v3 and their sizes"
+  (.splice (.unsplice (cris-implemented-readable-specregs-v0)) (SI 14))
+)
+
+(define-pmacro (cris-implemented-writable-specregs-v8)
+  "Special writable registers in v8 and their sizes"
+  (.splice (.unsplice (simplecris-common-writable-specregs)) (SI 14))
+)
+(define-pmacro
+  cris-implemented-specregs-const-v8
+  cris-implemented-writable-specregs-v8
+)
+(define-pmacro (cris-implemented-readable-specregs-v8)
+  "Special readable registers in v8 and their sizes"
+  (.splice (.unsplice (simplecris-common-readable-specregs)) (SI 14))
+)
+
+(define-pmacro (cris-implemented-writable-specregs-v10)
+  "Special writable registers in v10 and their sizes"
+  (.splice (.unsplice (simplecris-common-writable-specregs))
+          (SI 7) (SI 14) (SI 15))
+)
+(define-pmacro
+  cris-implemented-specregs-const-v10
+  cris-implemented-writable-specregs-v10
+)
+(define-pmacro (cris-implemented-readable-specregs-v10)
+  "Special registers in v10 and their sizes"
+  (.splice (.unsplice (simplecris-common-readable-specregs))
+          (SI 7) (SI 14) (SI 15))
+)
+
+(define-pmacro (cris-implemented-writable-specregs-v32)
+  "Special writable registers in v32 and their sizes"
+  ((SI 2) (QI 3)
+   (SI 5) (SI 6) (SI 7) (SI 9)
+   (SI 10) (SI 11) (SI 12) (SI 13) (SI 14) (SI 15))
+)
+(define-pmacro (cris-implemented-readable-specregs-v32)
+  "Special readable registers in v32 and their sizes"
+  (.splice (.unsplice (cris-implemented-writable-specregs-v32))
+          (QI 0) (QI 1) (HI 4) (SI 8))
+)
+
+; For v32, all special register operations on constants (that is,
+; move) take 32-bit operands, not the real size of the register, as in
+; other move operations.
+(define-pmacro (cris-implemented-specregs-const-v32)
+  (.map (.pmacro (x) (SI (.cadr2 x)))
+       (cris-implemented-writable-specregs-v32))
+)
+
+(define-pmacro cris-swap-codes
+  "CRIS Swap codes in numeric order (no zero)"
+  (   r  b  br  w  wr  wb  wbr
+   n nr nb nbr nw nwr nwb nwbr)
+)
+
+(define-pmacro cris-flagnames
+  "CRIS flag field values, dest and src fields concatenated"
+  (c v z n x i u p) ; ... b m for pre-v32
+)
+
+(define-pmacro-map
+  ; Bitnumber for each respective flag.
+  (.map (.pmacro (x num) ((.sym x -bitnumber) num))
+       cris-flagnames (.iota 8))
+)
+
+; I give up.  Here's a perl-script to get the values I want for this macro
+; (not working along list principles, though).  You can run this region.
+; perl -e '$x = "cvznxiup"; for ($i = 0; $i < 256; $i++) { $s = "";
+;  for ($j = 0; $j < 8; $j++) { if ($i & (1 << $j)) {
+; $s .= substr ($x, $j, 1);}}
+; printf ("%s%s", $s eq "" ? "_" : $s, (($i + 1) % 8) == 0 ? "\n   " : " "); }'
+(define-pmacro cris-flag-combinations
+  "Combinations of flags in numeric order"
+  (_ c v cv z cz vz cvz
+   n cn vn cvn zn czn vzn cvzn
+   x cx vx cvx zx czx vzx cvzx
+   nx cnx vnx cvnx znx cznx vznx cvznx
+   i ci vi cvi zi czi vzi cvzi
+   ni cni vni cvni zni czni vzni cvzni
+   xi cxi vxi cvxi zxi czxi vzxi cvzxi
+   nxi cnxi vnxi cvnxi znxi cznxi vznxi cvznxi
+   u cu vu cvu zu czu vzu cvzu
+   nu cnu vnu cvnu znu cznu vznu cvznu
+   xu cxu vxu cvxu zxu czxu vzxu cvzxu
+   nxu cnxu vnxu cvnxu znxu cznxu vznxu cvznxu
+   iu ciu viu cviu ziu cziu vziu cvziu
+   niu cniu vniu cvniu zniu czniu vzniu cvzniu
+   xiu cxiu vxiu cvxiu zxiu czxiu vzxiu cvzxiu
+   nxiu cnxiu vnxiu cvnxiu znxiu cznxiu vznxiu cvznxiu
+   p cp vp cvp zp czp vzp cvzp
+   np cnp vnp cvnp znp cznp vznp cvznp
+   xp cxp vxp cvxp zxp czxp vzxp cvzxp
+   nxp cnxp vnxp cvnxp znxp cznxp vznxp cvznxp
+   ip cip vip cvip zip czip vzip cvzip
+   nip cnip vnip cvnip znip cznip vznip cvznip
+   xip cxip vxip cvxip zxip czxip vzxip cvzxip
+   nxip cnxip vnxip cvnxip znxip cznxip vznxip cvznxip
+   up cup vup cvup zup czup vzup cvzup
+   nup cnup vnup cvnup znup cznup vznup cvznup
+   xup cxup vxup cvxup zxup czxup vzxup cvzxup
+   nxup cnxup vnxup cvnxup znxup cznxup vznxup cvznxup
+   iup ciup viup cviup ziup cziup vziup cvziup
+   niup cniup vniup cvniup zniup czniup vzniup cvzniup
+   xiup cxiup vxiup cvxiup zxiup czxiup vzxiup cvzxiup
+   nxiup cnxiup vnxiup cvnxiup znxiup cznxiup vznxiup cvznxiup
+  )
+)
+
+(define-pmacro cc-condition (not cbit))
+(define-pmacro cs-condition cbit)
+(define-pmacro ne-condition (not zbit))
+(define-pmacro eq-condition zbit)
+(define-pmacro vc-condition (not vbit))
+(define-pmacro vs-condition vbit)
+(define-pmacro pl-condition (not nbit))
+(define-pmacro mi-condition nbit)
+(define-pmacro ls-condition (or cbit zbit))
+(define-pmacro hi-condition (not (or cbit zbit)))
+(define-pmacro ge-condition (not (xor vbit nbit)))
+(define-pmacro lt-condition (xor vbit nbit))
+(define-pmacro gt-condition (not (or (xor vbit nbit) zbit)))
+(define-pmacro le-condition (or (xor vbit nbit) zbit))
+(define-pmacro a-condition 1)
+
+; FIXME: define this properly for v10 and pre-v10.
+(define-pmacro wf-condition pbit)
+
+(define-pmacro (cris-condition condno)
+  "Return condition state for condition number CONDNO"
+  (sequence
+    BI
+    ((SI tmpcond) (BI condres))
+    (set tmpcond condno)
+     (.splice
+      cond
+      (.unsplice
+       (.map
+       (.pmacro
+        (condn condc)
+        ((eq tmpcond condn) (set condres (.sym condc -condition))))
+       (.iota 16)
+       cris-condition-codes)))
+     condres)
+)
+
+;;;;;;;;;;;;;;;;;; -keyword
+
+; General registers.
+(define-pmacro (cris-general-gregs)
+  (.splice (SP 14) (.unsplice (.map (.pmacro (n) ((.sym R n) n)) (.iota 15))))
+)
+
+; Can't keep more than one gr-names definition at the same time;
+; generated enum declarations in sim/cris/cris-desc.h will collide.
+; FIXME: (include "different-mach-parts")
+
+(define-keyword
+  (name gr-names-pcreg)
+  (attrs MACH-PC)
+  (print-name h-gr-real-pc)
+  ; Put PC first so it is preferred over r15.
+  (.splice values (PC 15) (.unsplice (cris-general-gregs)))
+)
+
+(define-keyword
+  (name gr-names-acr)
+  (attrs MACH-ACR)
+  ; The print-name directive will control the enum prefix.  With the
+  ; arguably more appropriate h-gr-v32 or h-gr-acr, we'd get names like
+  ; H_GR_ACR_R0 instead of H_GR_R0.  Since we have to choose something for
+  ; unprefixed names, we use the CRISv32 names.  FIXME: All users should
+  ; change to use H_GR_V32_R0 (etc.), then change this to h-gr-v32.
+  (print-name h-gr)
+  ; Put ACR first so it is preferred over r15.
+  (.splice values (ACR 15) (.unsplice (cris-general-gregs)))
+)
+
+(define-keyword
+  (name gr-names-v32)
+  (attrs MACH-V32)
+  ; In preparation for implementing the FIXME above.
+  (print-name h-gr-v32)
+  ; Put ACR first so it is preferred over r15.
+  (.splice values (ACR 15) (.unsplice (cris-general-gregs)))
+)
+
+; Special registers with names common to all.
+(define-pmacro (cris-general-pregs)
+  (.splice
+   (VR 1)
+   (SRP 11)
+   (.unsplice (.map (.pmacro (n) ((.sym P n) n)) (.iota 15))))
+)
+
+(define-keyword
+  (name p-names-v10)
+  (attrs MACH-PRE-V32)
+  (print-name h-sr-pre-v32)
+  (.splice
+   values
+   (CCR 5)
+   (MOF 7)
+   (IBR 9)
+   (IRP 10)
+   (BAR 12)
+   (DCCR 13)
+   (BRP 14)
+   (USP 15)
+   (.unsplice (cris-general-pregs)))
+)
+
+(define-keyword
+  (name p-names-v32)
+  (attrs MACH-V32)
+  ; See comment for gr-names-acr.
+  (print-name h-sr)
+  (.splice
+   values
+   (BZ 0)
+   (PID 2)
+   (SRS 3)
+   (WZ 4)
+   (EXS 5)
+   (EDA 6)
+   (MOF 7)
+   (DZ 8)
+   (EBP 9)
+   (ERP 10)
+   (NRP 12)
+   (CCS 13)
+   (USP 14)
+   (SPC 15)
+   (.unsplice (cris-general-pregs)))
+)
+
+; Similarly as for h-gr-v32, in preparation.
+(define-keyword
+  (name p-names-v32-x)
+  (attrs MACH-V32)
+  ; See comment for gr-names-acr.
+  (print-name h-sr-v32)
+  (.splice
+   values
+   (BZ 0)
+   (PID 2)
+   (SRS 3)
+   (WZ 4)
+   (EXS 5)
+   (EDA 6)
+   (MOF 7)
+   (DZ 8)
+   (EBP 9)
+   (ERP 10)
+   (NRP 12)
+   (CCS 13)
+   (USP 14)
+   (SPC 15)
+   (.unsplice (cris-general-pregs)))
+)
+
+(define-pmacro p0 (reg h-sr 0))
+(define-pmacro vr (reg h-sr 1))
+(define-pmacro pid (reg h-sr 2))
+(define-pmacro srs (reg h-sr 3))
+(define-pmacro p4 (reg h-sr 4))
+(define-pmacro ccr (reg h-sr 5))
+(define-pmacro mof (reg h-sr 7))
+(define-pmacro p8 (reg h-sr 8))
+(define-pmacro ibr (reg h-sr 9))
+(define-pmacro ebp (reg h-sr 9))
+(define-pmacro erp (reg h-sr 10))
+(define-pmacro srp (reg h-sr 11))
+(define-pmacro ccs (reg h-sr 13))
+(define-pmacro dccr (reg h-sr 13))
+(define-pmacro usp (reg h-sr 14))
+(define-pmacro spc (reg h-sr 15))
+
+(define-pmacro sp (reg h-gr 14))
+(define-pmacro acr (reg h-gr 15))
+
+(define-pmacro cris-condition-codes
+  "CRIS condition codes in numeric order"
+  (cc cs ne eq vc vs pl mi ls hi ge lt gt le a wf)
+)
+
+; No use having different lists; this is the only CC that
+; differs between v10 and v32, and mostly in the name.
+(define-pmacro sb wf)
+
+
+;;;;;;;;;;;;;;;;;; -hardware
+
+;; Various constant generators.
+
+(define-hardware
+  (name h-inc)
+  (comment "autoincrement-bit syntax specifier")
+  (type immediate (UINT 1))
+  (values keyword "" (("" 0) ("+" 1)))
+)
+
+(define-hardware
+  (name h-ccode)
+  (comment "Condition code specifier")
+  (type immediate (UINT 4))
+  (values keyword ""
+         (.map (.pmacro (x y) ((.str x) y))
+               cris-condition-codes (.iota 16)))
+)
+
+(define-hardware
+  (name h-swap)
+  (comment "Swap option specifier")
+  (type immediate (UINT 4))
+  (values
+   keyword ""
+   (.splice
+    (" " 0)
+    (.unsplice
+     (.map
+      (.pmacro (x y) ((.str x) y)) cris-swap-codes (.iota 15 1)))))
+)
+
+(define-hardware
+  (name h-flagbits)
+  (comment "Flag bits specifier")
+  (type immediate (UINT 8))
+  (values
+   keyword ""
+   (.map (.pmacro (x y) ((.str x) y)) cris-flag-combinations (.iota 256)))
+)
+
+; Apparently, the semantic-name isn't used for accessors, so external
+; users like the sim glue and SID sees the -v32 and -pre-v32 munged names.
+; Defining "dispatchers"; virtual registers whose getter and setter works
+; on the "real" mach variants, seems to help.  CGEN-FIXME: Make
+; semantic-name set the generated names.
+(define-pmacro (cris-d-hwreg x-name x-type)
+  (define-hardware
+    (name x-name)
+    (comment (.str "Dispatcher for " x-name))
+    (attrs VIRTUAL)
+    (type register x-type)
+    (get () (reg (.sym x-name -x)))
+    (set (val) (set (reg (.sym x-name -x)) val)))
+)
+(define-pmacro (cris-d-hwregf-a x-name x-type x-n x-attrs)
+  (define-hardware
+    (name x-name)
+    (comment (.str "Dispatcher for " x-name))
+    (.splice attrs VIRTUAL (.unsplice x-attrs))
+    (type register x-type (x-n))
+    (get (index) (reg (.sym x-name -x) index))
+    (set (index val) (set-quiet (reg (.sym x-name -x) index) val)))
+)
+(define-pmacro (cris-d-hwregf x-name x-type x-n)
+  (cris-d-hwregf-a x-name x-type x-n ())
+)
+(define-pmacro (cris-d-hwregf-p x-name x-type x-n)
+  (cris-d-hwregf-a x-name x-type x-n (PROFILE))
+)
+
+; At first glance we could use (eq-attr (current-mach) ...) for
+; everything, but that seems sometimes (always?) to yield false.  For
+; ifields, it causes noncompilable C-code.  For the insn semantics code,
+; it causes tests movei.ms and mulv32.ms to fail, apparently because the
+; current-mach-is-v32 usage in flags setting is miscompiled as 0 (or
+; rather, misgenerated).  Instead we use different definitions of a
+; MACH-tagged virtual register yielding a constant, together with a
+; pmacro.  CGEN-FIXME: If eq-attr is someday fixed, we could just remove
+; these h-v32 virtual register definitions and change the pmacro
+; definition for current-mach-is-v32.
+(define-hardware
+  (semantic-name h-v32)
+  (name h-v32-v32)
+  (attrs MACH-V32 VIRTUAL)
+  (type register BI)
+  (get () (const BI 1))
+  (set (val) (error "Can't set h-v32"))
+)
+(define-hardware
+  (semantic-name h-v32)
+  (name h-v32-non-v32)
+  (attrs MACH-PRE-V32 VIRTUAL)
+  (type register BI)
+  (get () (const BI 0))
+  (set (val) (error "Can't set h-v32"))
+)
+
+;; "Real" hardware.
+
+(define-hardware
+  (name h-pc)
+  (comment "program counter")
+  (attrs PC PROFILE)
+  (type pc)
+  ; There's no bit 0 in PC, so just ignore it when jumping etc.
+  (set (val) (set (raw-reg h-pc) (and val (inv 1))))
+)
+
+; Note that setting register 15 isn't handled here, but in each insn, so
+; the proper "jump" attributes and other special stuff for speedy
+; execution can be present.
+(cris-d-hwregf-p h-gr SI 16)
+(define-hardware
+  (semantic-name h-gr-x)
+  (name h-gr-pc)
+  (attrs MACH-PC VIRTUAL)
+  (comment "General purpose registers, aborting on PC access")
+  (type register SI (16))
+  (indices extern-keyword gr-names-pcreg)
+  (get
+   (index)
+   (if SI (eq index 15)
+       (error SI "General register read of PC is not implemented.")
+       (reg SI h-gr-real-pc index)))
+  (set
+   (index val)
+   (sequence
+     ()
+     (if (eq index 15)
+        (error "General register write to PC is not implemented."))
+     (set (reg SI h-gr-real-pc index) val)))
+)
+(define-hardware
+  (name h-gr-real-pc)
+  (attrs MACH-PC)
+  (comment "General purpose registers")
+  (type register SI (16))
+  (indices extern-keyword gr-names-pcreg)
+)
+
+; We have to use a virtual register trick to get the "raw", unaccounted
+; contents of the global register; the raw-reg RTX only works for
+; non-virtual register files.
+(define-hardware
+  (semantic-name h-raw-gr)
+  (name h-raw-gr-pc)
+  (attrs MACH-PC VIRTUAL)
+  (comment "Unaccounted version of general purpose registers")
+  (type register SI (16))
+  (get (index) (raw-reg h-gr-real-pc index))
+  (set (index val) (set-quiet (raw-reg h-gr-real-pc index) val))
+)
+(define-hardware
+  (semantic-name h-gr-x)
+  (name h-gr-acr)
+  (attrs MACH-ACR)
+  (comment "General purpose registers")
+  (type register SI (16))
+  (indices extern-keyword gr-names-acr)
+)
+(define-hardware
+  (semantic-name h-raw-gr)
+  (name h-raw-gr-acr)
+  (attrs MACH-ACR VIRTUAL)
+  (comment "Unaccounted version of general purpose registers")
+  (type register SI (16))
+  (get (index) (raw-reg h-gr-x index))
+  (set (index val) (set-quiet (raw-reg h-gr-x index) val))
+)
+
+; FIXME: get and set semantics?  Unknown how to split semantics best; with
+; get/set semantics or within the insn specification.  Doing the former for
+; now.  Should use different names for pre-v10.
+; FIXME: No dccr for v0 and v3.  Different high flag bits.
+(cris-d-hwregf-p h-sr SI 16)
+(define-pmacro
+  (cris-h-sr machver)
+  (define-hardware
+    (semantic-name h-sr-x)
+    (name (.sym h-sr-v machver))
+    (attrs (MACH (.sym crisv machver)))
+    (comment (.str "Special registers for v" machver))
+    (type register SI (16))
+    (indices extern-keyword p-names-v10)
+    (get
+     (index)
+     (cond
+      SI
+      ((orif (orif (eq index (regno p0)) (eq index (regno p4)))
+            (eq index (regno p8))) 0)
+      ((eq index (regno vr)) machver)
+      ((orif (eq index (regno ccr))
+            (eq index (regno dccr)))
+       ; Return "P U I X N Z V C" for the low 8 bits.
+       ; FIXME: More bits.
+       (or SI
+          (and SI (raw-reg SI h-sr-x (regno ccr)) #xffffff00)
+          (or
+           (zext SI (reg BI h-cbit))
+           (or
+            (sll (zext SI (reg BI h-vbit)) 1)
+            (or
+             (sll (zext SI (reg BI h-zbit)) 2)
+             (or
+              (sll (zext SI (reg BI h-nbit)) 3)
+              (or
+               (sll (zext SI (reg BI h-xbit)) 4)
+               (or
+                (sll (zext SI (reg BI h-ibit)) 5)
+                (or
+                 (sll (zext SI (reg BI h-ubit)) 6)
+                 (or
+                  (sll (zext SI (reg BI h-pbit)) 7)
+                  0))))))))))
+      (else (raw-reg SI h-sr-x index))))
+    (set
+     (index val)
+     (cond
+      ((orif (orif (eq index (regno p0)) (eq index (regno p4)))
+            (orif (eq index (regno p8)) (eq index (regno vr))))
+       (nop))
+      ((orif (eq index (regno ccr)) (eq index (regno dccr)))
+       (sequence
+        ()
+        (set (reg BI h-cbit) (if BI (ne SI (and val (sll 1 0)) 0) 1 0))
+        (set (reg BI h-vbit) (if BI (ne SI (and val (sll 1 1)) 0) 1 0))
+        (set (reg BI h-zbit) (if BI (ne SI (and val (sll 1 2)) 0) 1 0))
+        (set (reg BI h-nbit) (if BI (ne SI (and val (sll 1 3)) 0) 1 0))
+        (set (reg BI h-xbit) (if BI (ne SI (and val (sll 1 4)) 0) 1 0))
+        (set (reg BI h-ibit) (if BI (ne SI (and val (sll 1 5)) 0) 1 0))
+        (set (reg BI h-ubit) (if BI (ne SI (and val (sll 1 6)) 0) 1 0))
+        (set (reg BI h-pbit) (if BI (ne SI (and val (sll 1 7)) 0) 1 0))
+        (set-quiet (raw-reg SI h-sr-x (regno ccr)) val)
+        (set-quiet (raw-reg SI h-sr-x (regno dccr)) val)))
+      (else (set-quiet (raw-reg SI h-sr-x index) val)))))
+)
+
+(cris-h-sr 0)
+(cris-h-sr 3)
+(cris-h-sr 8)
+(cris-h-sr 10)
+
+(define-hardware
+  (semantic-name h-sr-x)
+  (name h-sr-v32)
+  (attrs MACH-V32)
+  (comment "Special registers for v32")
+  (type register SI (16))
+  (indices extern-keyword p-names-v32)
+
+  (get
+   (index)
+   (cond
+    SI
+    ((orif (orif (eq index (regno p0)) (eq index (regno p4)))
+          (eq index (regno p8))) 0)
+    ((eq index (regno vr)) 32)
+    ((eq index (regno ccs))
+     ; Return "S R P U I X N Z V C" for the low 10 bits.
+     (or SI
+        (and SI (raw-reg SI h-sr-x (regno ccs)) #x3ffffc00)
+        (or
+         (zext SI (reg BI h-cbit))
+         (or
+          (sll (zext SI (reg BI h-vbit)) 1)
+          (or
+           (sll (zext SI (reg BI h-zbit)) 2)
+           (or
+            (sll (zext SI (reg BI h-nbit)) 3)
+            (or
+             (sll (zext SI (reg BI h-xbit)) 4)
+             (or
+              (sll (zext SI (reg BI h-ibit)) 5)
+              (or
+               (sll (zext SI (reg BI h-ubit)) 6)
+               (or
+                (sll (zext SI (reg BI h-pbit)) 7)
+                (or
+                 (sll (zext SI (reg BI h-rbit)) 8)
+                 (or
+                  (sll (zext SI (reg BI h-sbit)) 9)
+                  (or
+                   (sll (zext SI (reg BI h-mbit)) 30)
+                   (or
+                    (sll (zext SI (reg BI h-qbit)) 31)
+                    0))))))))))))))
+    ((eq index (regno usp))
+     ; In user mode, return general stack pointer.
+     (if BI (reg BI h-ubit)
+        (raw-reg SI h-gr-x (regno sp))
+        (raw-reg SI h-sr-x (regno usp))))
+    (else (raw-reg SI h-sr-x index))))
+
+  (set
+   (index val)
+   (cond
+    ((orif (orif (eq index (regno p0)) (eq index (regno p4)))
+          (orif (eq index (regno p8)) (eq index (regno vr))))
+     (nop))
+    ((eq index (regno ccs))
+     (sequence
+       ()
+       ; Protected bits are handled as such in the respective setter function.
+       (set (reg BI h-cbit) (if BI (ne SI (and val (sll 1 0)) 0) 1 0))
+       (set (reg BI h-vbit) (if BI (ne SI (and val (sll 1 1)) 0) 1 0))
+       (set (reg BI h-zbit) (if BI (ne SI (and val (sll 1 2)) 0) 1 0))
+       (set (reg BI h-nbit) (if BI (ne SI (and val (sll 1 3)) 0) 1 0))
+       (set (reg BI h-xbit) (if BI (ne SI (and val (sll 1 4)) 0) 1 0))
+       (set (reg BI h-ibit) (if BI (ne SI (and val (sll 1 5)) 0) 1 0))
+       (set (reg BI h-sbit) (if BI (ne SI (and val (sll 1 9)) 0) 1 0))
+       (set (reg BI h-mbit) (if BI (ne SI (and val (sll 1 30)) 0) 1 0))
+       (set (reg BI h-pbit) (if BI (ne SI (and val (sll 1 7)) 0) 1 0))
+       (set (reg BI h-rbit) (if BI (ne SI (and val (sll 1 8)) 0) 1 0))
+       (set (reg BI h-qbit) (if BI (ne SI (and val (sll 1 31)) 0) 1 0))
+       ; Set the U bit last, so the setter functions for the other bits
+       ; don't see it as set from this operation.  It is not cleared from
+       ; this operation, so we don't have to handle that; it's only
+       ; cleared "manually" from within simulator-specific context-switch
+       ; machinery.
+       (set (reg BI h-ubit) (if BI (ne SI (and val (sll 1 6)) 0) 1 0))
+       (set-quiet (raw-reg SI h-sr-x index) val)))
+    ((eq index (regno usp))
+     ; In user mode, set general register 14 too, whenever setting USP.
+     (sequence
+       ()
+       (if (reg BI h-ubit) (set (raw-reg SI h-gr-x (regno sp)) val))
+       (set (raw-reg SI h-sr-x (regno usp)) val)))
+    ((eq index (regno srs))
+     (if (not (reg BI h-ubit)) (set (raw-reg h-sr-x (regno srs)) val)))
+    ((eq index (regno ebp))
+     (if (not (reg BI h-ubit)) (set (raw-reg h-sr-x (regno ebp)) val)))
+    ((eq index (regno pid))
+     (if (not (reg BI h-ubit))
+        (sequence
+          ()
+          (c-call VOID "@cpu@_write_pid_handler" val)
+          (set (raw-reg h-sr-x (regno pid)) val))))
+    ((eq index (regno spc))
+     (if (not (reg BI h-ubit)) (set (raw-reg h-sr-x (regno spc)) val)))
+    (else (set-quiet (raw-reg SI h-sr-x index) val))))
+)
+
+(define-hardware
+  (name h-supr)
+  (attrs MACH-V32 VIRTUAL)
+  (comment "Support registers")
+  (type register SI (16))
+  (values keyword "" (.map (.pmacro (y) ((.str S y) y)) (.iota 16)))
+  (get (index) (c-call SI "@cpu@_read_supr" index))
+  (set (index val) (c-call VOID "@cpu@_write_supr" index val))
+)
+
+(define-pmacro (cris-dsh semantic-name name comment attrs type)
+  "Like dsh, but the semantic-name is separate"
+  (define-full-hardware
+    name comment attrs semantic-name type () () () () () ())
+)
+
+; We define the condition codes that hold arithmetic flags separately
+; and "or" them in, in the get and set methods of the special
+; registers.  We define arithmetic flags as any of C V Z N X.  They
+; thankfully have that order (zero-based) in all processor versions.
+
+; To avoid having two variants of most move-type instructions because V32
+; doesn't set C and V (and N and Z), we fake the setting to virtual
+; registers which have two different implementations.
+(define-pmacro (cris-move-flag f f-name f-whence)
+  "Flag set differently in pre-v32 and v32 in some cases"
+  (begin
+    (dsh (.sym h- f bit) (.str f-name " bit") () (register BI))
+    (cris-d-hwreg (.sym h- f bit-move) BI)
+    (define-hardware
+      (semantic-name (.sym h- f bit-move-x))
+      (name (.sym h- f bit-move-v32))
+      (comment (.str f-name " bit set in " f-whence " instructions, ignored"))
+      (attrs MACH-V32 VIRTUAL)
+      (type register BI)
+      (get
+       ()
+       (sequence BI ()
+                (error (.str "Can't get h-" f "bit-move on CRISv32")) 0))
+      (set (val) (nop)))
+    (define-hardware
+      (semantic-name (.sym h- f bit-move-x))
+      (name (.sym h- f bit-move-pre-v32))
+      (comment
+       (.str
+       f-name " bit set in " f-whence " instructions, same as " f "bit"))
+      (attrs MACH-PRE-V32 VIRTUAL)
+      (type register BI)
+      (get () (reg (.sym h- f bit)))
+      (set (val) (set (reg (.sym h- f bit)) val))))
+)
+
+(cris-move-flag c "carry" "move-type")
+(cris-move-flag v "overflow" "move-type")
+(cris-move-flag z "zero" "moveq")
+(cris-move-flag n "sign" "moveq")
+
+(dsh h-xbit "extended-arithmetic bit" () (register BI))
+(cris-d-hwreg h-ibit BI)
+(cris-dsh h-ibit-x h-ibit-pre-v32
+         "interrupt-enable bit" (MACH-PRE-V32) (register BI))
+(dsh h-pbit "sequence-broken bit" ((MACH crisv10,crisv32)) (register BI))
+(dsh h-rbit "carry bit for MCP+restore-p bit" (MACH-V32) (register BI))
+(cris-d-hwreg h-ubit BI)
+(cris-dsh h-ubit-x h-ubit-pre-v32
+         "user mode bit" ((MACH crisv10)) (register BI))
+(dsh h-gbit "guru mode bit" (MACH-V32) (register BI))
+
+; When doing a transition from kernel to user mode on V32, we save the
+; stack pointer in an internal register and copy USP to R14, so we don't
+; need non-trivial handlers for general registers.
+(dsh
+ h-kernel-sp
+ "Kernel stack pointer during user mode"
+ (MACH-V32)
+ (register SI)
+)
+
+(define-hardware
+  (semantic-name h-ubit-x)
+  (name h-ubit-v32)
+  (comment "User mode bit")
+  (attrs MACH-V32)
+  (type register BI)
+  (set
+   (val)
+   (sequence
+     ()
+     (if (andif val (not (raw-reg BI h-ubit-x)))
+        (sequence
+          ()
+          (set (reg SI h-kernel-sp) (raw-reg h-gr-x (regno sp)))
+          (set (raw-reg h-gr-x (regno sp)) (raw-reg h-sr-x (regno usp)))
+          (set (raw-reg BI h-ubit-x) val)
+          (c-call VOID "@cpu@_usermode_enabled")))))
+)
+
+(define-hardware
+  (semantic-name h-ibit-x)
+  (name h-ibit-v32)
+  (comment "Interrupt-enable bit")
+  (attrs MACH-V32)
+  (type register BI)
+  (set
+   (val)
+   (sequence
+     ()
+     (if (not (reg BI h-ubit))
+        (sequence
+          ((BI enabled))
+          (set enabled (andif val (not (raw-reg BI h-ibit-x))))
+          (set (raw-reg BI h-ibit-x) val)
+          ; Call handler when enabling.
+          (if enabled (c-call VOID "@cpu@_interrupts_enabled"))))))
+)
+
+(define-hardware
+  (name h-mbit)
+  (comment "NMI enable bit")
+  (attrs MACH-V32)
+  (type register BI)
+  (set
+   (val)
+   (sequence
+     ()
+     ; Don't allow clearing (through this handler) when once set.
+     (if (andif val (andif (not (raw-reg BI h-mbit)) (not (reg BI h-ubit))))
+        (sequence
+          ()
+          (set (raw-reg BI h-mbit) 1)
+          ; Call handler when enabling.
+          (c-call VOID "@cpu@_nmi_enabled")))))
+)
+
+(define-pmacro
+  (dsh-cond-bit-v32 x-name x-comment x-cond)
+  "dsh bit for MACH-V32, with bit only changeable when X-COND"
+  (define-hardware
+    (name x-name)
+    (comment x-comment)
+    (attrs MACH-V32)
+    (type register BI)
+    (set (val) (sequence () (if x-cond (set (raw-reg BI x-name) val)))))
+)
+(define-pmacro
+  (dsh-protected-bit-v32 x-name x-comment)
+  "dsh bit for MACH-V32, with bit only changeable in kernel mode"
+  (dsh-cond-bit-v32 x-name x-comment (not (reg BI h-ubit)))
+)
+(dsh-protected-bit-v32 h-qbit "Pending single-step bit")
+
+(define-hardware
+  (name h-sbit)
+  (comment "Cause single step exception on ... [see CRISv32 ref] bit")
+  (attrs MACH-V32)
+  (type register BI)
+  (set
+   (val)
+   (sequence
+     ()
+     (if (not (reg BI h-ubit))
+        (sequence
+          ((BI enabled))
+          (set enabled (andif val (not (raw-reg BI h-sbit))))
+          (set (raw-reg BI h-sbit) val)
+          ; Call handler when enabling.
+          (if enabled (c-call VOID "@cpu@_single_step_enabled"))))))
+)
+
+(dnop cbit "" (SEM-ONLY) h-cbit f-nil)
+(dnop cbit-move
+      "cbit for pre-V32, nothing for newer" (SEM-ONLY) h-cbit-move f-nil)
+(dnop vbit "" (SEM-ONLY) h-vbit f-nil)
+(dnop vbit-move
+      "vbit for pre-V32, nothing for newer" (SEM-ONLY) h-vbit-move f-nil)
+(dnop zbit "" (SEM-ONLY) h-zbit f-nil)
+(dnop zbit-move
+      "zbit for pre-V32, nothing for newer" (SEM-ONLY) h-zbit-move f-nil)
+(dnop nbit "" (SEM-ONLY) h-nbit f-nil)
+(dnop nbit-move
+      "nbit for pre-V32, nothing for newer" (SEM-ONLY) h-nbit-move f-nil)
+(dnop xbit "" (SEM-ONLY) h-xbit f-nil)
+(dnop ibit "" (SEM-ONLY) h-ibit f-nil)
+(dnop ubit "" (SEM-ONLY (MACH crisv10,crisv32)) h-ubit f-nil)
+(dnop pbit "" (SEM-ONLY (MACH crisv10,crisv32)) h-pbit f-nil)
+(dnop
+ rbit "carry bit for MCP+restore-P flag bit" (SEM-ONLY MACH-V32) h-rbit f-nil)
+(dnop sbit "" (SEM-ONLY MACH-V32) h-sbit f-nil)
+(dnop mbit "" (SEM-ONLY MACH-V32) h-mbit f-nil)
+(dnop qbit "" (SEM-ONLY MACH-V32) h-qbit f-nil)
+
+(cris-d-hwreg h-insn-prefixed-p BI)
+(cris-dsh
+ h-insn-prefixed-p-x
+ h-insn-prefixed-p-pre-v32
+ "instruction-is-prefixed bit"
+ (MACH-PRE-V32)
+ (register BI)
+)
+
+; CRISv32 has no prefixing on memory accesses.  CGEN-FIXME: [Once (eq-attr
+; (current-mach) ...) works]: can we change andif and/or orif so it
+; doesn't look too close at short-circuited operands and avoid defining an
+; operand that doesn't apply to a certain mach?
+(define-hardware
+ (semantic-name h-insn-prefixed-p-x)
+ (name h-insn-prefixed-p-v32)
+ (attrs MACH-V32 VIRTUAL)
+ (comment "instruction-is-prefixed bit")
+ (type register BI)
+ (get () (const BI 0))
+ (set (val) (nop))
+)
+(dnop
+ prefix-set
+ "Instruction-prefixed flag"
+ (SEM-ONLY)
+ h-insn-prefixed-p
+ f-nil
+)
+
+(cris-dsh
+ h-prefixreg h-prefixreg-pre-v32
+ "Prefix-address register" (MACH-PRE-V32) (register SI))
+(define-hardware
+  (semantic-name h-prefixreg)
+  (name h-prefixreg-v32)
+  (comment "Prefix-address register, redirecting to ACR")
+  (attrs MACH-V32 VIRTUAL)
+  (type register SI)
+  ; Why can't we have just a "acr" a.k.a "(reg h-gr 15)" here?
+  (get () acr)
+  (set (value) (set acr value))
+)
+
+(dnop
+ prefixreg
+ "Prefix address"
+ (SEM-ONLY)
+ h-prefixreg
+ f-nil
+)
+
+;;;;;;;;;;;;;;;;;; -ifield
+
+;        15                                            0
+;       +-----------+-----+-----------+-----+-----------+
+;       | Operand2  | Mode| Opcode    | Size| Operand1  |
+;       +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+;
+;       Figure 5.  General instruction format.
+;
+; Some deviations from this format exist, [see below].
+
+; Field specifiers in CGEN specify the highest numbered bit followed by
+; the number of bits.
+
+(dnf f-operand1 "Operand1" () 3 4)
+(dnf f-size "Size" () 5 2)
+(dnf f-opcode "Opcode" () 9 4)
+(dnf f-mode "Mode" () 11 2)
+(dnf f-operand2 "Operand2" () 15 4)
+
+; Subfields.  FIXME: unfortunately there's some limitation in CGEN so we
+; can't (as would be somewhat intuitive) make f-mode a multi-ifield
+; consisting of these two, concatenated.
+(dnf f-memmode "Indirect of autoincrement" () 10 1)
+(dnf f-membit "Memory specifier" () 11 1)
+
+(dnf f-b5 "Bit 5 (zero for some quick operands)" () 5 1)
+
+; When the addressing mode is quick immediate, the low bits are
+; part of the operand.
+(dnf f-opcode-hi "Opcode field, high bits" () 9 2)
+
+; Common synonyms for those fields.
+(define-pmacro f-source f-operand1)
+(define-pmacro f-dest f-operand2)
+
+(dnmf
+ f-dstsrc "Dest and source fields concatenated" () UINT
+ (f-dest f-source)
+ ; Insert-code.
+ (sequence
+   ((SI tmpval))
+   (set tmpval (ifield f-dstsrc))
+   (set (ifield f-dest) (and (srl tmpval 4) #xf))
+   (set (ifield f-source) (and tmpval #xf)))
+ ; Extract-code.
+ (set
+  (ifield f-dstsrc)
+  (and (or (ifield f-source) (sll (ifield f-dest) 4)) #xff))
+)
+
+;The 6-bit value may be sign or zero extended depending on the instruction.
+;
+;        15                                            0
+;       +-----------+-----+-----------+-----+-----------+
+;       | Operand2  | Mode| Opcode    | Immediate value |
+;       +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+;
+;   Figure 6.  Quick immediate addressing mode instruction format.
+
+(dnf f-u6 "Quick immediate unsigned 6-bit" () 5 6)
+(df f-s6 "Quick signed 6-bit" () 5 6 INT #f #f)
+
+; There's also a variant used with shift insns, with one bit larger opcode
+; and one bit smaller immediate value, though it doesn't have a general
+; graphic description.
+(dnf f-u5 "Quick unsigned 5-bit" () 4 5)
+
+; Similarly, a four-bit immediate field.
+(dnf f-u4 "Quick unsigned 4-bit" () 3 4)
+
+; An 8-bit signed value, which doesn't have a general graphic description.
+(df f-s8 "Source signed byte" () 7 8 INT #f #f)
+
+; The 9-bit branch offset, with bit 0 in the field being bit 8 in the
+; offset, and bit 0 in the offset always 0.
+(df f-disp9-hi "PC-relative 9-bit offset, sign bit" () 0 1 INT #f #f)
+(dnf f-disp9-lo "PC-relative 9-bit offset, low bits" () 7 7)
+
+; It would work to have this in two mach-specific variants, but
+; considering that current-mach-is-v32 is a compile-time constant, we
+; don't win any simulator performance.
+(dnmf
+ f-disp9 "PC-relative 9-bit offset"
+ (PCREL-ADDR)
+ INT
+ (f-disp9-hi f-disp9-lo)
+ ; Insert-code.
+ (sequence
+   ((SI absval))
+   (set absval (srl (sub (sub SI (ifield f-disp9) pc)
+                        (if SI current-mach-is-v32 0 2)) 1))
+   (set (ifield f-disp9-hi) (if (lt absval 0) 1 0))
+   (set (ifield f-disp9-lo) (and absval) #x7f))
+ ; Extract-code.
+ (sequence
+   ((SI abslo) (SI absval))
+   (set abslo (sll (ifield f-disp9-lo) 1))
+   (set absval
+       (or (if SI (ne (ifield f-disp9-hi) 0)
+               (inv SI #xff)
+               0)
+           abslo))
+   (set (ifield f-disp9)
+       (add SI (add SI pc absval) (if SI current-mach-is-v32 0 2))))
+)
+
+; The operand of LAPCQ is PC-relative, similar to f-disp9 but unsigned,
+; and only four bits.
+(df
+ f-qo
+ "PC-relative 4-bit unsigned offset, counted from start of insn"
+ (MACH-V32 PCREL-ADDR)
+ 3 4
+ UINT
+ ; Insert-code.
+ ((value pc) (srl SI (sub SI value pc) 1))
+ ; Extract-code.
+ ((value pc) (add SI pc (sll SI value 1)))
+)
+
+; 8-bit, 16-bit and 32-bit immediates.  The 8-bit values are constructed
+; through encoding/decoding functions, since the PC increment is by a
+; word.
+(define-pmacro (dcrisf x-name x-comment x-attrs x-word-offset x-word-length
+                      x-start x-length x-mode x-encode x-decode)
+  (define-ifield
+    (name x-name)
+    (comment x-comment)
+    (.splice attrs (.unsplice x-attrs))
+    (word-offset x-word-offset)
+    (word-length x-word-length)
+    (start x-start)
+    (length x-length)
+    (mode x-mode)
+    (.splice encode (.unsplice x-encode))
+    (.splice decode (.unsplice x-decode))
+  )
+)
+
+(dcrisf
+ f-indir-pc+-byte "[PC+] 8-bit field" (SIGN-OPT)
+ 16 16
+ 15 16 ; CGEN-FIXME: Should be 7 8
+ INT (#f) (#f)
+)
+
+(dcrisf
+ f-indir-pc+-word "[PC+] 16-bit field" (SIGN-OPT)
+ 16 16 15 16 INT (#f) (#f)
+)
+
+; CGEN-FIXME: I shouldn't have to use trunc here, should I?
+; Sign-extension should be implicit through use of SI (as opposed to USI)
+; and additionally through SIGN-OPT.  The ext isn't actually needed, but
+; having it there rather than implicit makes more sense than to just have
+; the trunc.
+(dcrisf
+ f-indir-pc+-word-pcrel "[PC+] PC-relative 16-bit field"
+ (PCREL-ADDR SIGN-OPT)
+ 16 16 15 16 SI
+ ((value pc) (sub SI value (add SI pc (if SI current-mach-is-v32 0 4))))
+ ((value pc) (add SI (ext SI (trunc HI value)) (add SI pc (if SI current-mach-is-v32 0 4))))
+)
+
+(dcrisf
+ f-indir-pc+-dword "PC autoincrement - 32-bit field" (SIGN-OPT)
+ 16 32 31 32 INT (#f) (#f)
+)
+
+(dcrisf
+ f-indir-pc+-dword-pcrel
+ "[PC+] PC-relative 32-bit field, counted from start of insn"
+ (SIGN-OPT MACH-V32 PCREL-ADDR)
+ 16 32 31 32 INT
+ ((value pc) (sub SI value pc))
+ ((value pc) (add SI pc value))
+)
+
+;;;;;;;;;;;;;;;;;; -insn-enum -normal-operand -normal-derived-operand
+
+;; How different fields are transformed into something we put in insns.
+
+;       m       := size modifier, byte (00), word (01) or dword (10)
+;       z       := size modifier, byte (0) or word (1)
+; (For the latter, the "higher" bit is always 0, mapping trivially on m.)
+
+(define-normal-insn-enum
+  insn-size
+  "Standard instruction operand size"
+  ()
+  SIZE_
+  f-size
+  ("BYTE" "WORD" "DWORD" "FIXED")
+)
+
+; The mode field for insns with "s" operand (perhaps with a partial set of
+; operand types).
+(define-normal-insn-enum
+  insn-mode
+  "Standard instruction addressing modes"
+  ()
+  MODE_
+  f-mode
+  ("QUICK_IMMEDIATE" "REGISTER" "INDIRECT" "AUTOINCREMENT")
+)
+
+(define-normal-insn-enum
+  insn-memoryness-mode
+  "Whether the operand is indirect"
+  ()
+  MODEMEMP_
+  f-membit
+  ("NO" "YES")
+)
+
+; FIXME: Needed?
+(define-normal-insn-enum
+  insn-memincness-mode
+  "Whether the indirect operand is autoincrement"
+  ()
+  MODEINCP_
+  f-memmode
+  ("NO" "YES")
+)
+
+; Special semantics for multiply.
+(define-pmacro MODE_MULU MODE_INDIRECT)
+(define-pmacro MODE_MULS MODE_AUTOINCREMENT)
+
+(define-normal-insn-enum
+  insn-signed-size
+  "Signed instruction operand size"
+  ()
+  SIGNED_
+  f-size
+  ("UNDEF_SIZE_0" "UNDEF_SIZE_1" "BYTE" "WORD")
+)
+
+(define-normal-insn-enum
+  insn-unsigned-size
+  "Unsigned instruction operand size"
+  ()
+  UNSIGNED_
+  f-size
+  ("BYTE" "WORD" "UNDEF_SIZE_2" "UNDEF_SIZE_3")
+)
+
+;       Rs      := source operand, register addressing mode
+(dnop Rs "Source general register" () h-gr f-source)
+
+;       [Rs]    := source operand, indirect addressing mode
+; = MODE_INDIRECT Rs
+
+;       [Rs+]   := source operand, autoincrement addressing mode  (see note!)
+; = MODE_AUTOINCREMENT Rs
+
+; The union of [Rs] and [Rs(+)]
+; = MODEMEMP_YES Rs
+
+; Whether an indirect operand is increment can be obtained as an operand by
+; = inc
+(dnop inc "Incrementness of indirect operand" () h-inc f-memmode)
+
+; or as an affirmative specifier
+; = MODEINCP_YES
+; (or MODEINCP_NO)
+
+;       s       := source operand, any of the modes Rs, [Rs] or [Rs+]
+; No common operand; each are handled separately, using the above definitions.
+
+;       Ps      := source operand, special register
+; It's in the field usually used for the destination.
+(dnop Ps "Source special register" () h-sr f-dest)
+
+;       Ss      := source operand, support register
+; It's in the field usually used for the destination.
+(dnop Ss "Source support register" (MACH-V32) h-supr f-dest)
+
+;       Sd      := source operand, support register
+(dnop Sd "Destination support register" (MACH-V32) h-supr f-dest)
+
+;       i       := 6-bit signed immediate operand
+(dnop i "Quick signed 6-bit" () h-sint f-s6)
+
+;       j       := 6-bit unsigned immediate operand
+(dnop j "Quick unsigned 6-bit" () h-uint f-u6)
+
+;       c       := 5-bit immediate shift value
+(dnop c "Quick unsigned 5-bit" () h-uint f-u5)
+
+;       qo      := 4-bit unsigned immediate operand
+(dnop qo "Quick unsigned 4-bit, PC-relative" (MACH-V32) h-addr f-qo)
+
+;       Rd      := destination operand, register addressing mode
+(dnop Rd "Destination general register" () h-gr f-dest)
+(define-pmacro Rd-sfield Rs)
+(define-pmacro Rs-dfield Rd)
+
+;       [Rd]    := destination operand, indirect addressing mode
+; = MODE_INDIRECT Rd
+
+;       [Rd+]   := destination operand, autoincrement addressing mode
+; = MODE_AUTOINCREMENT Rd
+
+;       [PC+]   := destination operand PC, autoincrement addressing mode
+; = MODE_AUTOINCREMENT (f-dest 15) X
+; where X is one of sconst8, uconst8, sconst16, uconst16 or const32.
+(dnop sconst8 "Signed byte [PC+]" () h-sint f-indir-pc+-byte)
+(dnop uconst8 "Unsigned byte [PC+]" () h-uint f-indir-pc+-byte)
+(dnop sconst16 "Signed word [PC+]" () h-sint f-indir-pc+-word)
+(dnop uconst16 "Unsigned word [PC+]" () h-uint f-indir-pc+-word)
+(dnop const32 "Dword [PC+]" () h-uint f-indir-pc+-dword)
+(dnop const32-pcrel "Dword [PC+]" () h-addr f-indir-pc+-dword-pcrel)
+
+;       d       := destination operand, any of the modes Rd, [Rd] or [Rd+]
+; No common operand; each are handled separately, using the above definitions.
+
+;       Pd      := destination operand, special register
+(dnop Pd "Destination special register" () h-sr f-dest)
+
+;       o       := 8-bit immediate offset value
+(dnop o "Signed 8-bit" () h-sint f-s8)
+
+; The division of operand semantics and insn fields in the CRIS
+; instruction set reference doesn't permit a simple mapping to a
+; simulator description, and the division of insn fields and
+; semantics in CGEN is not between the define-normal-ifield
+; vs. define-normal-operand.  For example, the "o" operand is
+; PC-relative for branch insns, as described by the CGEN f-disp9
+; field.
+; See comment at f-disp9; thankfully the mach
+; attribute works here to have two different definitions by the
+; same name.
+(dnop o-pcrel "9-bit signed immediate PC-rel"
+      ()
+      h-iaddr f-disp9)
+
+(dnop o-word-pcrel "16-bit signed immediate PC-rel"
+      ()
+      h-iaddr f-indir-pc+-word-pcrel)
+
+;       cc      := condition code
+(dnop cc "Condition codes" () h-ccode f-dest)
+
+;       n       := 4 bit breakpoint exception vector index
+(dnop n "Quick unsigned 4-bit" () h-uint f-u4)
+
+; The "option" in the SWAP insn.
+(dnop swapoption "Swap option" () h-swap f-dest)
+
+(dnop list-of-flags "Flag bits as operand" () h-flagbits f-dstsrc)
+
+; Enumerations for insn codes, for use in insn definitions
+; instead of raw numbers.  See it as operand definitions for the
+; opcode field.
+
+(define-normal-insn-enum
+  insn-qi-opc
+  "Insns for MODE_QUICK_IMMEDIATE"
+  ()
+  Q_
+  f-opcode
+  ("BCC_0" "BCC_1" "BCC_2" "BCC_3"
+   "BDAP_0" "BDAP_1" "BDAP_2" "BDAP_3"
+   "ADDQ" "MOVEQ" "SUBQ" "CMPQ"
+   "ANDQ" "ORQ" "ASHQ" "LSHQ")
+)
+
+(define-normal-insn-enum
+  insn-qihi-opc
+  "Same as insn-qi-opc, though using only the high two bits of the opcode"
+  ()
+  QHI_
+  f-opcode-hi
+  ("BCC" "BDAP" "OTHER2" "OTHER3")
+)
+(define-pmacro QHI_ADDOQ QHI_BDAP)
+
+(define-normal-insn-enum
+  insn-r-opc
+  "Insns for MODE_REGISTER and either SIZE_BYTE, SIZE_WORD or SIZE_DWORD"
+  ()
+  R_
+  f-opcode
+  ("ADDX" "MOVX" "SUBX" "LSL"
+   "ADDI" "BIAP" "NEG" "BOUND"
+   "ADD" "MOVE" "SUB" "CMP"
+   "AND" "OR" "ASR" "LSR")
+)
+(define-pmacro R_ADDI_ACR R_BIAP)
+
+(define-normal-insn-enum
+  insn-rfix-opc
+  "Insns for MODE_REGISTER and SIZE_FIXED"
+  ()
+  RFIX_
+  f-opcode
+  ("ADDX" "MOVX" "SUBX" "BTST"
+   "SCC" "ADDC" "SETF" "CLEARF"
+   "MOVE_R_S" "MOVE_S_R" "ABS" "DSTEP"
+   "LZ" "SWAP" "XOR" "MSTEP")
+)
+(define-pmacro RFIX_MCP RFIX_MSTEP)
+
+(define-normal-insn-enum
+  insn-indir-opc
+  "Insns for (MODE_INDIRECT or MODE_AUTOINCREMENT) and either SIZE_BYTE, SIZE_WORD or SIZE_DWORD"
+  ()
+  INDIR_
+  f-opcode
+  ("ADDX" "MOVX" "SUBX" "CMPX"
+   "MUL" "BDAP_M" "ADDC" "BOUND"
+   "ADD" "MOVE_M_R" "SUB" "CMP"
+   "AND" "OR" "TEST" "MOVE_R_M")
+)
+(define-pmacro INDIR_ADDO INDIR_BDAP_M)
+
+(define-normal-insn-enum
+  insn-infix-opc
+  "Insns for (MODE_INDIRECT or MODE_AUTOINCREMENT) and SIZE_FIXED"
+  ()
+  INFIX_
+  f-opcode
+  ("ADDX" "MOVX" "SUBX" "CMPX"
+   "JUMP_M" "DIP" "JUMP_R" "BCC_M"
+   "MOVE_M_S" "MOVE_S_M" "BMOD" "BSTORE"
+   "RBF" "SBFS" "MOVEM_M_R" "MOVEM_R_M")
+)
+
+(define-pmacro INFIX_MOVE_SS INFIX_SBFS)
+(define-pmacro INFIX_LAPC INFIX_DIP)
+(define-pmacro INFIX_RFE INFIX_JUMP_M)
+(define-pmacro INFIX_RFN INFIX_JUMP_M)
+(define-pmacro INFIX_HALT INFIX_JUMP_M)
+(define-pmacro INFIX_SFE INFIX_JUMP_M)
+(define-pmacro INFIX_RFG INFIX_JUMP_M)
+(define-pmacro INFIX_JAS_R INFIX_JUMP_R)
+(define-pmacro INFIX_JAS_M INFIX_JUMP_R)
+(define-pmacro INFIX_JASC INFIX_RBF)
+(define-pmacro INFIX_JUMP_P INFIX_BCC_M)
+(define-pmacro INFIX_BAS INFIX_BMOD)
+(define-pmacro INFIX_BASC INFIX_BSTORE)
+(define-pmacro INFIX_BREAK INFIX_JUMP_M)
+(define-pmacro INFIX_FIDXI INFIX_JUMP_M)
+(define-pmacro INFIX_FIDXD INFIX_BAS)
+(define-pmacro INFIX_FTAGI INFIX_JUMP_M)
+(define-pmacro INFIX_FTAGD INFIX_BAS)
+
+; Classes of insns:
+; Move-to-register, move-to-memory, move-to/from-other-register,
+; logical, arithmetic, branch.
+; Classes of operands:
+; quick, register, memory-indirect, memory-postinc.
+
+
+;;;;;;;;;;;;;;;;;; -normal-insn
+
+(define-pmacro (dni-bwd-attr name comment attr syntax fmt fsem timing)
+  (begin
+    (dni (.sym name .b) (.str "byte " comment) attr (.str name ".b " syntax)
+        (.splice (.unsplice fmt) SIZE_BYTE)
+        (fsem QI)
+        timing)
+    (dni (.sym name .w) (.str "word " comment) attr (.str name ".w " syntax)
+        (.splice (.unsplice fmt) SIZE_WORD)
+        (fsem HI)
+        timing)
+    (dni (.sym name .d) (.str "dword " comment) attr (.str name ".d " syntax)
+        (.splice (.unsplice fmt) SIZE_DWORD)
+        (fsem SI)
+        timing))
+)
+
+(define-pmacro (dni-cdt-attr name comment attr syntax fmt semantics)
+  "dni without specifying timing"
+  (dni name comment attr syntax fmt semantics (cris-timing))
+)
+
+(define-pmacro (dni-cdt-bwd-attr name comment attr syntax fmt fsem)
+  (begin
+    (dni-cdt-attr (.sym name .b-r) (.str "byte " comment) attr (.str name ".b " syntax)
+                 (.splice (.unsplice fmt) SIZE_BYTE)
+                 (fsem QI))
+    (dni-cdt-attr (.sym name .w-r) (.str "word " comment) attr (.str name ".w " syntax)
+                 (.splice (.unsplice fmt) SIZE_WORD)
+                 (fsem HI))
+    (dni-cdt-attr (.sym name .d-r) (.str "dword " comment) attr (.str name ".d " syntax)
+                 (.splice (.unsplice fmt) SIZE_DWORD)
+                 (fsem SI)))
+)
+
+; Some convenience macros based on the above ones.
+(define-pmacro (dni-cdt-bwd name comment syntax fmt fsem)
+  (dni-cdt-bwd-attr name comment () syntax fmt fsem)
+)
+
+(define-pmacro (dni-bwd name comment syntax fmt fsem timing)
+  (dni-bwd-attr comment () syntax fmt fsem timing)
+)
+
+(define-pmacro-map
+  (((dni-cdt name comment syntax fmt semantics)
+    (dni-cdt-attr name comment () syntax fmt semantics))
+   ((dni-c-QI-attr name comment attr syntax fmt fsem)
+    (dni name comment attr syntax fmt fsem (cris-timing-const-QI)))
+   ((dni-c-HI-attr name comment attr syntax fmt fsem)
+    (dni name comment attr syntax fmt fsem (cris-timing-const-HI)))
+   ((dni-c-SI-attr name comment attr syntax fmt fsem)
+    (dni name comment attr syntax fmt fsem (cris-timing-const-SI))))
+)
+
+(define-pmacro-map
+  (((dni-c-QI name comment syntax fmt fsem)
+    (dni-c-QI-attr name comment () syntax fmt fsem))
+   ((dni-c-HI name comment syntax fmt fsem)
+    (dni-c-HI-attr name comment () syntax fmt fsem))
+   ((dni-c-SI name comment syntax fmt fsem)
+    (dni-c-SI-attr name comment () syntax fmt fsem)))
+)
+
+; These flags are both cleared by all insns except prefixes (before
+; CRISv32) and "setf x", so we put them in a handy macro.
+(define-pmacro
+  (reset-x-p)
+  (sequence
+    ()
+    (set xbit 0)
+    (set prefix-set 0))
+)
+
+;        NOP           | 0  0  0  0| 0  1| 0  1  0  0| 0  0| 1  1  1  1|
+; (For V32, "SETF" (no flags) is used.)
+(dni-cdt-attr
+ nop "nop" (MACH-PC) "nop"
+ (+ (f-operand2 0) R_ADDI MODE_REGISTER SIZE_BYTE (f-operand1 15))
+ (reset-x-p)
+)
+
+; Pre- and v32+ variants MOVE insns set flags differently.  These two
+; macros for flag settings are meant to be used in all MOVE insns.
+(define-pmacro (setf-moveq value)
+  (sequence
+    ()
+    (set-quiet nbit-move (lt SI value 0))
+    (set-quiet zbit-move (andif BI (eq SI value 0) (if BI xbit zbit 1)))
+    (set-quiet cbit-move 0)
+    (set-quiet vbit-move 0)
+    (reset-x-p))
+)
+
+(define-pmacro (setf-move size value)
+  (sequence
+    ()
+    (set nbit (lt size value 0))
+    (set zbit (andif BI (eq size value 0) (if BI xbit zbit 1)))
+    (set-quiet cbit-move 0)
+    (set-quiet vbit-move 0)
+    (reset-x-p))
+)
+; The CGEN binop-with-bit operations are not documented well enough that I
+; trust their semantics to remain stable.  Better define local ones: the
+; semantics become explicit.
+(define-pmacro-map
+  (((add-overflow size R D S carry)
+    (orif BI (andif BI (andif BI (lt size S 0) (lt size D 0)) (ge size R 0))
+         (andif BI (andif BI (ge size S 0) (ge size D 0)) (lt size R 0))))
+   ((add-carry size R D S carry)
+    (orif BI (andif BI (lt size S 0) (lt size D 0))
+         (orif BI (andif BI (lt size D 0) (ge size R 0))
+               (andif BI (lt size S 0) (ge size R 0)))))
+   ((sub-overflow size R D S carry)
+    (orif BI (andif BI (andif BI (ge size S 0) (lt size D 0)) (ge size R 0))
+         (andif BI (andif BI (lt size S 0) (ge size D 0)) (lt size R 0))))
+   ((sub-carry size R D S carry)
+    (orif BI (andif BI (lt size S 0) (ge size D 0))
+         (orif BI (andif BI (ge size D 0) (lt size R 0))
+               (andif BI (lt size S 0) (lt size R 0)))))
+   ; Only valid for size := DI
+   ((mulu-overflow size R D S carry)
+    (ne DI R (zext DI (trunc SI R))))
+   ((mulu-carry size R D S carry)
+    (andif current-mach-is-v32 carry))
+   ((muls-overflow size R D S carry)
+    (ne DI R (ext DI (trunc SI R))))
+   ((muls-carry size R D S carry)
+    (andif current-mach-is-v32 carry)))
+)
+
+(define-pmacro (setf-arit2 size op source1 source2 result carryin carryout)
+  "Set no-prefix, x=0, carryout, v, z and n according to operation OP in size SIZE"
+  (sequence
+    ()
+    (set carryout ((.sym op -carry) size result source1 source2 carryin))
+    (set nbit (lt size result 0))
+    (set zbit (andif BI (eq size result 0) (orif BI zbit (not BI xbit))))
+    (set vbit ((.sym op -overflow) size result source1 source2 carryin))
+    (reset-x-p))
+)
+(define-pmacro (setf-arit size op source1 source2 result carry)
+  "Set no-prefix, x=0, c, v, z and n according to operation OP in size SIZE"
+  (setf-arit2 size op source1 source2 result carry cbit)
+)
+
+; Let's have convienence macros for arithmetic, including evaluation of the
+; operation, destination modification, flag setting and carry propagation.
+(define-pmacro
+  (cris-arit6-int arit size fdest fdest_op srcop1 srcop2 carryout carryin)
+  "Core for performing some three-operand arithmetic with carry as parameter"
+  (sequence
+   ((size tmpopd) (size tmpops) (BI carry) (size newval))
+   (set tmpops srcop2)
+   (set tmpopd srcop1)
+   (set carry carryin)
+   (set newval ((.sym arit c) tmpopd tmpops (if BI (eq xbit 0) 0 carry)))
+   (fdest size fdest_op newval)
+   (setf-arit2 size arit tmpopd tmpops newval carry carryout))
+)
+
+(define-pmacro
+  (cris-arit5-int arit size destregno srcop1 srcop2 carryout carryin)
+  "As cris-arit6-int, but to set a part of a general register"
+  (cris-arit6-int
+   arit
+   size
+   (.pmacro (sz regno val) (set-subreg-gr sz regno val))
+   destregno
+   srcop1
+   srcop2
+   carryout
+   carryin)
+)
+
+(define-pmacro (cris-arit5 arit size destreg srcop1 srcop2 carryout carryin)
+  "As cris-arit5-int, but takes a register as parameter, not register number"
+  (cris-arit5-int arit size (regno destreg) srcop1 srcop2 carryout carryin)
+)
+(define-pmacro (cris-arit3-int arit size destregno srcop1 srcop2)
+  "As cris-arit5-int, but with carry-in same as carry-out"
+  (cris-arit5-int arit size destregno srcop1 srcop2 cbit cbit)
+)
+(define-pmacro (cris-arit3 arit size destreg srcop1 srcop2)
+  "As cris-arit3-int, but takes a register as parameter, not register number"
+  (cris-arit3-int arit size (regno destreg) srcop1 srcop2)
+)
+(define-pmacro (cris-arit arit size destreg srcop)
+  "As cris-arit3, but with destination same as srcop1"
+  (cris-arit3 arit size destreg destreg srcop)
+)
+(define-pmacro (cris-arit-3op arit size destsrcop2 srcop1 dest-3op)
+  "Similar to cris-arit3-int, but for prefixed operand only"
+  (cris-arit3-int arit size
+                 (if SI (andif prefix-set (not inc))
+                     (regno dest-3op)
+                     (regno destsrcop2))
+                 destsrcop2 srcop1)
+)
+
+; Convenience macros to select a part of a value and its complement, for
+; the <op>.b, <op>.w and <op>.d operations.
+(define-pmacro (QI-part val) (and SI val #xff))
+(define-pmacro (non-QI-part val) (and SI val #xffffff00))
+(define-pmacro (HI-part val) (and SI val #xffff))
+(define-pmacro (non-HI-part val) (and SI val #xffff0000))
+(define-pmacro (SI-part val) val)
+(define-pmacro (non-SI-part val) 0)
+(define-pmacro
+  (set-subreg-gr-bw BWD gregno newval)
+  "Set a byte or word part or full dword of a general register"
+  (sequence
+    ((SI oldregval))
+    (set oldregval (reg h-raw-gr gregno))
+    (set (reg h-gr gregno)
+        (or SI ((.sym BWD -part) newval) ((.sym non- BWD -part) oldregval))))
+)
+(define-pmacro (set-subreg-gr BWD gregno newval)
+  ((.sym set-subreg-gr- BWD) BWD gregno newval)
+)
+(define-pmacro (set-subreg-gr-SI SI gregno newval)
+  (set (reg h-gr gregno) newval)
+)
+(define-pmacro set-subreg-gr-HI set-subreg-gr-bw)
+(define-pmacro set-subreg-gr-QI set-subreg-gr-bw)
+
+; MOVE.m  Rs,Rd           [ Rd | 011001mm | Rs ]
+(dni-cdt-bwd
+ move "move.m r,R"
+ "move.m ${Rs},${Rd}"
+ (+ Rd MODE_REGISTER R_MOVE Rs)
+ (.pmacro
+  (BWD)
+  (sequence
+    ((BWD newval))
+    (set newval Rs)
+    (set-subreg-gr BWD (regno Rd) newval)
+    (setf-move BWD newval)))
+)
+
+; MOVE.D  PC,Rd           [ Rd | 01100110 | 1111 ]
+; This insn is used in PIC code to find out the code address.  It's an
+; exception to the (guarded) non-implementation of PC operands in this
+; file.
+(dni-cdt-attr
+ movepcr "move.d PC,R"
+ (MACH-PC UNCOND-CTI)
+ "move.d PC,${Rd}"
+ (+ Rd MODE_REGISTER R_MOVE SIZE_DWORD (f-source 15))
+ (sequence
+   ((SI pcval))
+   (set pcval (add SI pc 2))
+   (set Rd pcval)
+   (setf-move SI pcval))
+)
+
+; MOVEQ   i,Rd            [ Rd | 001001 | i ]
+(dni-cdt
+ moveq "moveq"
+ "moveq $i,$Rd"
+ (+ Rd MODE_QUICK_IMMEDIATE Q_MOVEQ i)
+ (sequence
+   ((SI newval))
+   (set newval i)
+   (set Rd newval)
+   (setf-moveq newval))
+)
+
+(define-pmacro (dni-cdt-sbw name comment syntax fmt fsem)
+  "Insn generator for insns with signed <op>.b and <op>.w variants"
+  (begin
+    (dni-cdt
+     (.sym name .b-r) (.str "byte " comment) (.str name ".b " syntax)
+     (.splice (.unsplice fmt) SIGNED_BYTE)
+     (fsem QI))
+    (dni-cdt
+     (.sym name .w-r) (.str "word " comment) (.str name ".w " syntax)
+     (.splice (.unsplice fmt) SIGNED_WORD)
+     (fsem HI)))
+)
+
+; MOVS.z  Rs,Rd           [ Rd | 0100011z | Rs ]
+(dni-cdt-sbw
+ movs "movs.m r,R"
+ "movs.m ${Rs},${Rd}"
+ (+ Rd MODE_REGISTER R_MOVX Rs)
+ (.pmacro
+  (BW)
+  (sequence
+    ((BW tmpops) (SI newval))
+    (set tmpops Rs)
+    (set newval (ext SI tmpops))
+    (set Rd newval)
+    (setf-move SI newval)))
+)
+
+(define-pmacro (dni-cdt-ubw name comment syntax fmt fsem)
+  "Similar to dni-cdt-sbw but for unsigned operations"
+  (begin
+    (dni-cdt
+     (.sym name .b-r) (.str "byte " comment) (.str name ".b " syntax)
+     (.splice (.unsplice fmt) UNSIGNED_BYTE)
+     (fsem QI))
+    (dni-cdt
+     (.sym name .w-r) (.str "word " comment) (.str name ".w " syntax)
+     (.splice (.unsplice fmt) UNSIGNED_WORD)
+     (fsem HI)))
+)
+
+; MOVU.z  Rs,Rd           [ Rd | 0100010z | Rs ]
+(dni-cdt-ubw
+ movu "movu.m r,R"
+ "movu.m ${Rs},${Rd}"
+ (+ Rd MODE_REGISTER R_MOVX Rs)
+ (.pmacro
+  (BW)
+  (sequence
+    ((BW tmpops) (SI newval))
+    (set tmpops Rs)
+    (set newval (zext SI tmpops))
+    (set Rd newval)
+    (setf-move SI newval)))
+)
+
+; (MOVE.m  [PC+],Rd        [ Rd | 111001mm | 1111 ])
+; For the moment, it doesn't seem worthwhile to make a dni-c-bwd macro;
+; too many places to parametrize.
+(dni-c-QI
+ movecbr "move.b [PC+],R"
+ "move.b ${sconst8},${Rd}"
+ (+ Rd MODE_AUTOINCREMENT INDIR_MOVE_M_R SIZE_BYTE (f-source 15) sconst8)
+ (sequence
+   ((QI newval))
+   (set newval sconst8)
+   (set-subreg-gr QI (regno Rd) newval)
+   (setf-move QI newval))
+)
+
+(dni-c-HI
+ movecwr "move.w [PC+],R"
+ "move.w ${sconst16},${Rd}"
+ (+ Rd MODE_AUTOINCREMENT INDIR_MOVE_M_R SIZE_WORD (f-source 15) sconst16)
+ (sequence
+   ((HI newval))
+   (set newval sconst16)
+   (set-subreg-gr HI (regno Rd) newval)
+   (setf-move HI newval))
+)
+
+(dni-c-SI
+ movecdr "move.d [PC+],R"
+ "move.d ${const32},${Rd}"
+ (+ Rd MODE_AUTOINCREMENT INDIR_MOVE_M_R SIZE_DWORD (f-source 15) const32)
+ (sequence
+   ((SI newval))
+   (set newval const32)
+   (set Rd newval)
+   (setf-move SI newval))
+)
+
+; (MOVS.z  [PC+],Rd        [ Rd | 1100011z | 1111 ])
+; Similarly, no likely net improvement for a dni-c-bw.
+(dni-c-QI
+ movscbr "movs.b [PC+],R"
+ "movs.b ${sconst8},${Rd}"
+ (+ Rd MODE_AUTOINCREMENT INDIR_MOVX SIGNED_BYTE (f-source 15) sconst8)
+ (sequence
+   ((SI newval))
+   ; FIXME: Make trunc unnecessary.
+   (set newval (ext SI (trunc QI sconst8)))
+   (set Rd newval)
+   (setf-move SI newval))
+)
+
+(dni-c-HI
+ movscwr "movs.w [PC+],R"
+ "movs.w ${sconst16},${Rd}"
+ (+ Rd MODE_AUTOINCREMENT INDIR_MOVX SIGNED_WORD (f-source 15) sconst16)
+ (sequence
+   ((SI newval))
+   ; FIXME: Make trunc unnecessary.
+   (set newval (ext SI (trunc HI sconst16)))
+   (set Rd newval)
+   (setf-move SI newval))
+)
+
+; (MOVU.z  [PC+],Rd        [ Rd | 1100010z | 1111 ])
+(dni-c-QI
+ movucbr "movu.b [PC+],R"
+ "movu.b ${uconst8},${Rd}"
+ (+ Rd MODE_AUTOINCREMENT INDIR_MOVX UNSIGNED_BYTE (f-source 15) uconst8)
+ (sequence
+   ((SI newval))
+   ; FIXME: Make trunc unnecessary.
+   (set newval (zext SI (trunc QI uconst8)))
+   (set Rd newval)
+   (setf-move SI newval))
+)
+
+(dni-c-HI
+ movucwr "movu.w [PC+],R"
+ "movu.w ${uconst16},${Rd}"
+ (+ Rd MODE_AUTOINCREMENT INDIR_MOVX UNSIGNED_WORD (f-source 15) uconst16)
+ (sequence
+   ((SI newval))
+   ; FIXME: Make trunc unnecessary.
+   (set newval (zext SI (trunc HI uconst16)))
+   (set Rd newval)
+   (setf-move SI newval))
+)
+
+; ADDQ    j,Rd            [ Rd | 001000 | j ]
+(dni-cdt
+ addq "addq j,Rd"
+ "addq $j,$Rd"
+ (+ Rd MODE_QUICK_IMMEDIATE Q_ADDQ j)
+ (cris-arit add SI Rd j)
+)
+
+; SUBQ    j,Rd            [ Rd | 001010| j ]
+(dni-cdt
+ subq "subq j,Rd"
+ "subq $j,$Rd"
+ (+ Rd MODE_QUICK_IMMEDIATE Q_SUBQ j)
+ (cris-arit sub SI Rd j)
+)
+
+; Convenience macros for insns with a memory operand.
+(define-pmacro
+  (dni-cmt-attr-tim name comment attr syntax fmt semantics timing)
+  "dni with memory-access"
+  (dni name comment attr syntax
+       ; Specifying MODE_INDIRECT and MODE_AUTOINCREMENT in this
+       ; manner makes the autoincrementness handily available.
+       ; It also effectively excludes non-memory use of dni-cmt.
+       (.splice (.unsplice fmt) MODEMEMP_YES inc)
+       semantics
+       timing)
+)
+
+(define-pmacro (dni-cmt-attr name comment attr syntax fmt semantics)
+  "dni with read memory-access timing"
+  (dni-cmt-attr-tim name comment attr syntax fmt semantics
+                   (cris-mem-timing))
+)
+
+(define-pmacro (dni-cmwt-attr  name comment attr syntax fmt semantics)
+  "dni with write memory-access timing"
+  (dni-cmt-attr-tim name comment attr syntax fmt semantics
+                   (cris-mem-write-timing))
+)
+
+(define-pmacro QI-size 1)
+(define-pmacro HI-size 2)
+(define-pmacro SI-size 4)
+
+(define-pmacro (cris-get-mem size regop)
+  "Handle reading memory in <size>, with source address register\
+ (read once, maybe set once) in <regop> or prefixed"
+  (sequence
+    size
+    ((SI addr) (size tmp-mem) (BI postinc))
+
+    ; Cache the incrementness of the operand.
+    (set postinc inc)
+
+    ; Get the address from somewhere.
+    (set addr
+        (if SI (eq prefix-set 0)
+            ; If the insn was prefixed, it's in the prefix-register.
+            regop
+            prefixreg))
+
+    ; Get the memory contents.
+    (set tmp-mem (mem size addr))
+
+    ; For non-prefixed post-increment, we increment the address by the
+    ; size of the memory access.
+    (if (ne postinc 0)
+       (sequence
+         ()
+         (if (eq prefix-set 0)
+             (set addr (add addr (.sym size -size))))
+         ; Update the source-register for post-increments.
+         (set regop addr)))
+
+    ; Don't forget the return-value.
+    tmp-mem)
+)
+
+(define-pmacro (cris-set-mem size regop value)
+  "Handle writing <value> of <size> to memory, with memory address register\
+ (read once, maybe set once) in <regop> or prefixed."
+  (sequence
+    ((SI addr) (BI postinc))
+
+    ; Cache the incrementness of the operand.
+    (set postinc inc)
+
+    ; Get the address from somewhere.
+    (set addr
+        (if SI (eq prefix-set 0)
+            ; If the insn was prefixed, it's in the prefix-register.
+            regop
+            prefixreg))
+
+    ; Set the memory contents.  Integral-write semantics apply.
+    ; FIXME: currently v32 only; when proper semantics needed, fix v10.
+    (if (andif current-mach-is-v32 (ne xbit 0))
+       (if (eq pbit 0)
+           (sequence
+             ()
+             (set (mem size addr) value)
+             ; Write failures are signalled (by whatever entity "sends
+             ; the signal") by setting P at time of the write above, if X
+             ; is set.  Here, we just need to copy P into C.
+             (set cbit pbit))
+           (set cbit 1))
+       (set (mem size addr) value))
+
+    ; For non-prefixed post-increment, we increment the address by the
+    ; size of the memory access.  As for the integral-write, this needs to
+    ; be tweaked for pre-v32: increment should have been performed if
+    ; there's a fault at the memory access above.
+    (if (ne postinc 0)
+       (sequence
+         ()
+         (if (eq prefix-set 0)
+             (set addr (add addr (.sym size -size))))
+         ; Update the source-register for post-increments.
+         (set regop addr))))
+)
+
+(define-pmacro
+  (dni-cmt-bwd-attr-tim name comment attr syntax fmt fsem timing)
+  "Core generator macro for insns with <op>.b, <op>.w and <op>.d variants\
+ and a memory operand."
+  (begin
+    (dni-cmt-attr-tim
+     (.sym name .b-m)
+     (.str "byte mem " comment)
+     attr
+     (.str name ".b " syntax)
+     (.splice (.unsplice fmt) SIZE_BYTE)
+     (fsem QI)
+     timing)
+    (dni-cmt-attr-tim
+     (.sym name .w-m)
+     (.str "word mem " comment)
+     attr
+     (.str name ".w " syntax)
+     (.splice (.unsplice fmt) SIZE_WORD)
+     (fsem HI)
+     timing)
+    (dni-cmt-attr-tim
+     (.sym name .d-m)
+     (.str "dword mem " comment)
+     attr
+     (.str name ".d " syntax)
+     (.splice (.unsplice fmt) SIZE_DWORD)
+     (fsem SI)
+     timing))
+)
+
+; Further refinement macros.
+(define-pmacro (dni-cmt-bwd-attr name comment attr syntax fmt fsem)
+  (dni-cmt-bwd-attr-tim name comment attr syntax fmt fsem
+                       (cris-mem-timing))
+)
+
+(define-pmacro (dni-cmwt-bwd name comment syntax fmt fsem)
+  (dni-cmt-bwd-attr-tim name comment () syntax fmt fsem
+                       (cris-mem-write-timing))
+)
+
+(define-pmacro (dni-cmt-bwd name comment syntax fmt fsem)
+  (dni-cmt-bwd-attr name comment () syntax fmt fsem)
+)
+
+(define-pmacro (dni-cmt-sbw name comment syntax fmt fsem)
+  "Core generator macro for insns with <op>.b and <op>.w variants\
+ and a signed memory operand."
+  (begin
+    (dni-cmt-attr
+     (.sym name .b-m) (.str "byte mem " comment)
+     ()
+     (.str name ".b " syntax)
+     (.splice (.unsplice fmt) SIGNED_BYTE)
+     (fsem QI))
+    (dni-cmt-attr
+     (.sym name .w-m) (.str "word mem " comment)
+     ()
+     (.str name ".w " syntax)
+     (.splice (.unsplice fmt) SIGNED_WORD)
+     (fsem HI)))
+)
+
+(define-pmacro (dni-cmt-ubw name comment syntax fmt fsem)
+  "Core generator macro for insns with <op>.b and <op>.w variants\
+ and an unsigned memory operand."
+  (begin
+    (dni-cmt-attr
+     (.sym name .b-m) (.str "byte mem " comment)
+     ()
+     (.str name ".b " syntax)
+     (.splice (.unsplice fmt) UNSIGNED_BYTE)
+     (fsem QI))
+    (dni-cmt-attr
+     (.sym name .w-m) (.str "word mem " comment)
+     ()
+     (.str name ".w " syntax)
+     (.splice (.unsplice fmt) UNSIGNED_WORD)
+     (fsem HI)))
+)
+
+; CMP.m   Rs,Rd           [ Rd | 011011mm | Rs ]
+(dni-cdt-bwd
+ cmp-r "compare register to register"
+ "$Rs,$Rd"
+ (+ Rd MODE_REGISTER R_CMP Rs)
+ (.pmacro
+  (BWD)
+  (cris-arit6-int
+   sub BWD (.pmacro (sz regno val) (nop)) 0
+   Rd Rs cbit cbit))
+)
+
+; CMP.m   [Rs],Rd         [ Rd | 101011mm | Rs ]
+; CMP.m   [Rs+],Rd        [ Rd | 111011mm | Rs ]
+(dni-cmt-bwd
+ cmp-m "compare memory to register"
+ "[${Rs}${inc}],${Rd}"
+ (+ INDIR_CMP Rs Rd)
+ (.pmacro
+  (BWD)
+  (cris-arit6-int
+   sub BWD (.pmacro (sz regno val) (nop)) 0
+   Rd (cris-get-mem BWD Rs) cbit cbit))
+)
+
+; (CMP.m   [PC+],Rd        [ Rd | 111011mm | 1111 ])
+(dni-c-QI
+ cmpcbr "cmp constant byte to register"
+ "cmp.b $sconst8,$Rd"
+ (+ Rd MODE_AUTOINCREMENT INDIR_CMP SIZE_BYTE (f-source 15) sconst8)
+ (cris-arit6-int
+  sub QI (.pmacro (sz regno val) (nop)) 0
+  Rd (trunc QI sconst8) cbit cbit)
+)
+
+(dni-c-HI
+ cmpcwr "cmp constant word to register"
+ "cmp.w $sconst16,$Rd"
+ (+ Rd MODE_AUTOINCREMENT INDIR_CMP SIZE_WORD (f-source 15) sconst16)
+ (cris-arit6-int
+  sub HI (.pmacro (sz regno val) (nop)) 0
+  Rd (trunc HI sconst16) cbit cbit)
+)
+
+(dni-c-SI
+ cmpcdr "cmp constant dword to register"
+ "cmp.d $const32,$Rd"
+ (+ Rd MODE_AUTOINCREMENT INDIR_CMP SIZE_DWORD (f-source 15) const32)
+ (cris-arit6-int
+  sub SI (.pmacro (sz regno val) (nop)) 0
+  Rd const32 cbit cbit)
+)
+
+; CMPQ    i,Rd            [ Rd | 001011 | i ]
+(dni-cdt
+ cmpq "cmpq i,Rd"
+ "cmpq $i,$Rd"
+ (+ Rd MODE_QUICK_IMMEDIATE Q_CMPQ i)
+ (cris-arit6-int
+  sub SI (.pmacro (sz regno val) (nop)) 0
+  Rd i cbit cbit)
+)
+
+; CMPS.z  [Rs],Rd         [ Rd | 1000111z | Rs ]
+; CMPS.z  [Rs+],Rd        [ Rd | 1100111z | Rs ]
+(dni-cmt-sbw
+ cmps-m "cmp sign-extended from memory to register"
+ "[${Rs}${inc}],$Rd"
+ (+ Rd INDIR_CMPX Rs)
+ (.pmacro
+  (BW)
+  (cris-arit6-int
+   sub SI (.pmacro (sz regno val) (nop)) 0
+   Rd ((.sym BW -ext) (cris-get-mem BW Rs)) cbit cbit))
+)
+
+; (CMPS.z  [PC+],Rd        [ Rd | 1100111z | 1111 ])
+(dni-c-QI
+ cmpscbr "cmp sign-extended constant byte to register"
+ "[${Rs}${inc}],$Rd"
+ (+ Rd MODE_AUTOINCREMENT INDIR_CMPX SIGNED_BYTE (f-source 15) sconst8)
+ (cris-arit6-int
+  sub SI (.pmacro (sz regno val) (nop)) 0
+  Rd (ext SI (trunc QI sconst8)) cbit cbit)
+)
+(dni-c-HI
+ cmpscwr "cmp sign-extended constant word to register"
+ "[${Rs}${inc}],$Rd"
+ (+ Rd MODE_AUTOINCREMENT INDIR_CMPX SIGNED_WORD (f-source 15) sconst16)
+ (cris-arit6-int
+  sub SI (.pmacro (sz regno val) (nop)) 0
+  Rd (ext SI (trunc HI sconst16)) cbit cbit)
+)
+
+; CMPU.z  [Rs],Rd         [ Rd | 1000110z | Rs ]
+; CMPU.z  [Rs+],Rd        [ Rd | 1100110z | Rs ]
+(dni-cmt-ubw
+ cmpu-m "cmp zero-extended from memory to register"
+ "[${Rs}${inc}],$Rd"
+ (+ Rd INDIR_CMPX Rs)
+ (.pmacro
+  (BW)
+  (cris-arit6-int
+   sub SI (.pmacro (sz regno val) (nop)) 0
+   Rd ((.sym BW -zext) (cris-get-mem BW Rs)) cbit cbit))
+)
+
+; (CMPU.z  [PC+],Rd        [ Rd | 1100110z | 1111 ])
+(dni-c-QI
+ cmpucbr "cmp zero-extended constant byte to register"
+ "[${Rs}${inc}],$Rd"
+ (+ Rd MODE_AUTOINCREMENT INDIR_CMPX UNSIGNED_BYTE (f-source 15) uconst8)
+ (cris-arit6-int
+  sub SI (.pmacro (sz regno val) (nop)) 0
+  Rd (zext SI (trunc QI uconst8)) cbit cbit)
+)
+(dni-c-HI
+ cmpucwr "cmp zero-extended constant word to register"
+ "[${Rs}${inc}],$Rd"
+ (+ Rd MODE_AUTOINCREMENT INDIR_CMPX UNSIGNED_WORD (f-source 15) uconst16)
+ (cris-arit6-int
+  sub SI (.pmacro (sz regno val) (nop)) 0
+  Rd (zext SI (trunc HI uconst16)) cbit cbit)
+)
+
+; MOVE.m  [Rs],Rd         [ Rd | 101001mm | Rs ]
+; MOVE.m  [Rs+],Rd        [ Rd | 111001mm | Rs ]
+(dni-cmt-bwd
+ move-m "move from memory to register"
+ "[${Rs}${inc}],${Rd}"
+ (+ INDIR_MOVE_M_R Rs Rd)
+ (.pmacro
+  (BWD)
+  (sequence
+    ((SI tmp))
+    (set tmp (cris-get-mem BWD Rs))
+    (set-subreg-gr
+     BWD
+     (if SI (andif prefix-set (not inc)) (regno Rs) (regno Rd))
+     tmp)
+    (setf-move BWD tmp)))
+)
+
+; MOVS.z  [Rs],Rd         [ Rd | 1000011z | Rs ]
+; MOVS.z  [Rs+],Rd        [ Rd | 1100011z | Rs ]
+(dni-cmt-sbw
+ movs-m "movs from memory to register"
+ "[${Rs}${inc}],${Rd}"
+ (+ INDIR_MOVX Rs Rd)
+ (.pmacro
+  (BW)
+  (sequence
+    ((SI tmp))
+    (set tmp (ext SI (cris-get-mem BW Rs)))
+    (if (andif prefix-set (not inc))
+       (set Rs tmp)
+       (set Rd tmp))
+    (setf-move SI tmp)))
+)
+
+; MOVU.z  [Rs],Rd         [ Rd | 1000010z | Rs ]
+; MOVU.z  [Rs+],Rd        [ Rd | 1100010z | Rs ]
+(dni-cmt-ubw
+ movu-m "movu from memory to register"
+ "[${Rs}${inc}],${Rd}"
+ (+ INDIR_MOVX Rs Rd)
+ (.pmacro
+  (BW)
+  (sequence
+    ((SI tmp))
+    (set tmp (zext SI (cris-get-mem BW Rs)))
+    (if (andif prefix-set (not inc))
+       (set Rs tmp)
+       (set Rd tmp))
+    (setf-move SI tmp)))
+)
+
+; MOVE    Rs,Pd           [ Pd | 01100011 | Rs ]
+(.splice
+ begin
+ (.unsplice
+  (.map
+   (.pmacro
+    (VER)
+    (dni
+     (.sym move-r-spr VER)
+     "Move from general register to special register"
+     ((MACH (.sym cris VER)))
+     "move ${Rs},${Pd}"
+     (+ RFIX_MOVE_R_S MODE_REGISTER SIZE_FIXED Rs Pd)
+     (sequence
+       ((SI tmp) (SI rno))
+       (set tmp Rs)
+       (set rno (regno Pd))
+       (cond
+       ; See reg-sr setter for most of the special-register semantics.
+       ; The sanity check for known read-only registers is for program
+       ; debug help; the real insn would be harmless and have no effect.
+       ; CGEN-FIXME: regno of symbolic h-sr names doesn't work here.
+       ((orif (orif (eq rno 0) (eq rno 1)) (orif (eq rno 4) (eq rno 8)))
+        (error "move-r-spr: trying to set a read-only special register"))
+       (else (set Pd tmp)))
+       (reset-x-p))
+     (cris-reg-sr-timing)))
+   (cris-cpu-models)))
+)
+
+(define-pmacro (dni-cdt-ver-attr name comment fattr syntax fmt fsem)
+  "Generator for each MACH, using default timing."
+  (.splice
+   begin
+   (.unsplice
+    (.map
+     (.pmacro (v) (dni-cdt-attr name comment (fattr v) syntax fmt (fsem v)))
+     (cris-cpu-models))))
+)
+
+; MOVE    Ps,Rd           [ Ps | 01100111 | Rd ]
+; Note that in the insn format, the Rd operand is in the Rs field (the
+; Rd field by the definition used everywhere else is the Ps position in
+; this insn).
+; It gets a little weird here because we can't get this insn into a
+; define-pmacro unless we make named pmacros for e.g. a separate attr
+; function and a semantics function: a .pmacro can't refer to the
+; parameters of the outer define-pmacro.  (The manual refers to this as
+; not implementing "lexical scoping").
+(.splice
+ begin
+ (.unsplice
+  (.map
+   (.pmacro
+    (VER)
+    (dni-cdt-attr
+     (.sym move-spr-r VER)
+     "Move from special register to general register"
+     ((MACH (.sym cris VER)))
+     "move ${Ps},${Rd-sfield}"
+     (+ Ps RFIX_MOVE_S_R MODE_REGISTER SIZE_FIXED Rd-sfield)
+     (sequence
+       ((SI grno) (SI prno) (SI newval))
+       (set prno (regno Ps))
+       ; CGEN-FIXME: Can't use the following and then "grno" below because
+       ; CGEN will emit a "tmp_grno" *also* in decodev32.c:crisv32f_decode
+       ; (set grno (regno Rd-sfield))
+       (set newval Ps)
+       (.splice
+       cond
+       (.unsplice
+        (.map
+         (.pmacro
+          (r)
+          ((eq prno (.cadr2 r))
+           (set-subreg-gr (.car2 r) (regno Rd-sfield) newval)))
+         ((.sym cris-implemented-readable-specregs- VER))))
+       (else (error "move-spr-r from unimplemented register")))
+       (reset-x-p))))
+   (cris-cpu-models)))
+)
+
+; MOVE    Ps,PC           [ Ps | 01100111 | 1111 ]
+; The move-special-register-to-pc insns are return-type instructions and
+; have to be special-cased to get the delay-slot and avoid being indicated
+; as invalid.
+(dni-cdt-attr
+ ret-type
+ "ret-type"
+ (MACH-PC)
+ "ret/reti/retb"
+ (+ Ps MODE_REGISTER RFIX_MOVE_S_R SIZE_FIXED (f-source 15))
+ (sequence
+   ((SI retaddr))
+   (set retaddr Ps)
+   (reset-x-p)
+   (delay 1 (set pc retaddr)))
+)
+
+; MOVE    [Rs],Pd         [ Pd | 10100011 | Rs ]
+; MOVE    [Rs+],Pd        [ Pd | 11100011 | Rs ]
+; We make variants that loads constants or memory for each MACH version,
+; since each consider some subset of the "special registers" to have
+; different sizes.  FIXME: Should be able to simplify this.
+(.splice
+ begin
+ (.unsplice
+  (.map
+   (.pmacro
+    (VER)
+    (dni
+     (.sym move-m-spr VER)
+     "Move from memory to special register"
+     ((MACH (.sym cris VER)))
+     "move [${Rs}${inc}],${Pd}"
+     (+ Pd INFIX_MOVE_M_S MODEMEMP_YES inc SIZE_FIXED Rs)
+     (sequence
+       ((SI rno) (SI newval))
+       (set rno (regno Pd))
+       (.splice
+       cond
+       ; No sanity check for constant special register here, since the
+       ; memory read side-effect or post-increment may be the goal, or
+       ; for pre-v32 a prefix assignment side-effect.
+       (.unsplice
+        (.map
+         (.pmacro
+          (r)
+          ((eq rno (.cadr2 r))
+           (set newval ((.sym (.car2 r) -ext) (cris-get-mem (.car2 r) Rs)))))
+         ((.sym cris-implemented-writable-specregs- VER))))
+       (else (error "Trying to set unimplemented special register")))
+       (set Pd newval)
+       (reset-x-p))
+     (cris-mem-sr-timing)))
+   (cris-cpu-models)))
+)
+
+(define-pmacro QI-operand sconst8)
+(define-pmacro HI-operand sconst16)
+(define-pmacro SI-operand const32)
+
+(define-pmacro
+  (cris-move-c-spr VER VERFN)
+  "Generator for loading constant into special register"
+  (.splice
+   begin
+   (.unsplice
+    (.map
+     (.pmacro
+      (srdef v)
+      (dni
+       (.sym move-c-spr v -p (.cadr2 srdef))
+       (.str "Move constant to special register p" (.cadr2 srdef))
+       ((MACH (.sym cris v)))
+       (.str "move ${" (.sym (.car2 srdef) -operand) "},${Pd}")
+       ; We use Pd in semantics without naming it in the format (which
+       ; would CGEN-FIXME: cause a CGEN error for some reason, likely
+       ; related to specifying an insn field multiple times).  This
+       ; currently works and is guarded with test-cases (specifically
+       ; wrt. the timing model) but may need to be tweaked in the future.
+       ; Note that using instead (ifield f-dest) causes incorrect timing
+       ; model to be generated; the timing model requires that Pd is set.
+       (+ (f-dest (.cadr2 srdef)) MODE_AUTOINCREMENT INFIX_MOVE_M_S SIZE_FIXED
+         (f-source 15) (.sym (.car2 srdef) -operand))
+       (sequence
+        ()
+        (set Pd (.sym (.car2 srdef) -operand)) ; (reg h-sr (.cadr2 srdef))
+        (reset-x-p))
+       ((.sym cris-timing-const-sr- (.car2 srdef)))))
+     ((.sym cris-implemented-specregs-const- VER))
+     (.map VERFN ((.sym cris-implemented-specregs-const- VER))))))
+)
+
+; CGEN-FIXME:
+; Unfortunately we can't iterate over the list of models due to the
+; problem with referring to the parameters of a surrounding pmacro from
+; within an enclosed .pmacro (perhaps related to "lexical scoping").
+; We get e.g. 'insn already defined:: (move-c-sprvn-p0)' with this:
+;(.splice
+; begin (.unsplice (.map (.pmacro (vn) (cris-move-c-spr vn (.pmacro (x) vn)))
+;                      (cris-cpu-models)))
+;)
+(cris-move-c-spr v0 (.pmacro (x) v0))
+(cris-move-c-spr v3 (.pmacro (x) v3))
+(cris-move-c-spr v8 (.pmacro (x) v8))
+(cris-move-c-spr v10 (.pmacro (x) v10))
+(cris-move-c-spr v32 (.pmacro (x) v32))
+
+; MOVE    Ps,[Rd]         [ Ps | 10100111 | Rd ]
+; MOVE    Ps,[Rd+]        [ Ps | 11100111 | Rd ]
+(.splice
+ begin
+ (.unsplice
+  (.map
+   (.pmacro
+    (VER)
+    (dni-cmwt-attr
+     (.sym move-spr-m VER)
+     "Move from special register to memory"
+     ((MACH (.sym cris VER)))
+     "move ${Ps},[${Rd-sfield}${inc}]"
+     (+ INFIX_MOVE_S_M SIZE_FIXED Rd-sfield Ps)
+     (sequence
+       ((SI rno))
+       (set rno (regno Ps))
+       (.splice
+       cond
+       (.unsplice
+        (.map
+         (.pmacro
+          (r)
+          ((eq rno (.cadr2 r))
+           (cris-set-mem (.car2 r) Rd-sfield Ps)))
+         ((.sym cris-implemented-readable-specregs- VER))))
+       (else (error "write from unimplemented special register")))
+       (reset-x-p))))
+   (cris-cpu-models)))
+)
+
+; SBFS [Rs(+)]
+;  Instruction format:     |0 0 1 1 1 m 1 1 0 1 1 1| Dest. |
+(dni-cdt-attr
+ sbfs
+ "sbfs"
+ ((MACH crisv10))
+ "sbfs [${Rd-sfield}${inc}]"
+ (+ (f-dest 3) INFIX_SBFS SIZE_FIXED MODEMEMP_YES inc Rd-sfield)
+ (error "SBFS isn't implemented")
+)
+
+;  MOVE    Ss,Rd            [ Ss | 11110111 | Rd ]
+(dni-cdt-attr
+ move-ss-r
+ "move from support register to general register"
+ (MACH-V32)
+ "move ${Ss},${Rd-sfield}"
+ (+ Ss INFIX_MOVE_SS SIZE_FIXED (f-mode 3) Rd-sfield)
+ (sequence
+   ()
+   (set Rd-sfield Ss)
+   (reset-x-p))
+)
+
+; MOVE    Rs,Sd            [ Sd | 10110111 | Rs ]
+(dni-cdt-attr
+ move-r-ss
+ "move from general register to support register"
+ (MACH-V32)
+ "move ${Rs},${Sd}"
+ (+ Sd INFIX_MOVE_SS SIZE_FIXED (f-mode 2) Rs)
+ (sequence
+   ()
+   (set Sd Rs)
+   (reset-x-p))
+)
+
+; MOVEM   Rs,[Rd]         [ Rs | 10111111 | Rd ]
+; MOVEM   Rs,[Rd+]        [ Rs | 11111111 | Rd ]
+
+(define-pmacro (movem-to-mem-step regn)
+  ; Without the SI attribute, UINT is generated, which isn't supported by
+  ; the sim framework.
+  (if (ge SI (regno Rs-dfield) regn)
+      (sequence
+       ((SI tmp))
+       (set tmp (reg h-gr regn))
+       (set (mem SI addr) tmp)
+       (set addr (add addr 4))))
+)
+
+(dni
+ movem-r-m
+ "movem to memory"
+ (MACH-PRE-V32)
+ "movem ${Rs-dfield},[${Rd-sfield}${inc}]"
+ (+ INFIX_MOVEM_R_M MODEMEMP_YES inc SIZE_FIXED Rs-dfield Rd-sfield)
+ (sequence
+   ((SI addr) (BI postinc))
+   ; FIXME: A copy of what's in cris-get-mem.
+
+   ; Cache the incrementness of the operand.
+   (set postinc inc)
+
+   ; CGEN-FIXME: Kludge to work around a CGEN bug: it doesn't see that
+   ; Rs-dfield is used as an input, causing the timing model to be wrong.
+   (sequence ((SI dummy)) (set dummy Rs-dfield))
+
+   ; Get the address from somewhere.  If the insn was prefixed, it's in
+   ; the prefix-register.
+   (set addr
+       (if SI (eq prefix-set 0)
+           Rd-sfield
+           prefixreg))
+
+   (.splice
+    sequence ()
+    (.unsplice (.map movem-to-mem-step (.iota 16 15 -1))))
+
+   ; Update the source-register for post-increments.
+   (if (ne postinc 0)
+       (set Rd-sfield
+           (if SI (eq prefix-set 0) addr prefixreg)))
+   (reset-x-p))
+   (simplecris-movem-timing)
+)
+
+(dni
+ movem-r-m-v32
+ "movem to memory"
+ (MACH-V32)
+ "movem ${Rs-dfield},[${Rd-sfield}${inc}]"
+ (+ INFIX_MOVEM_R_M MODEMEMP_YES inc SIZE_FIXED Rs-dfield Rd-sfield)
+ (sequence
+   ((SI addr) (BI postinc))
+   ; FIXME: Mostly a copy of what's in cris-get-mem.
+
+   ; Cache the incrementness of the operand.
+   (set postinc inc)
+
+   ; CGEN-FIXME: See movem-r-m.
+   (sequence ((SI dummy)) (set dummy Rs-dfield))
+
+   (set addr Rd-sfield)
+
+   (.splice
+    sequence ()
+    (.unsplice (.map movem-to-mem-step (.iota 16))))
+
+   ; Update the source-register for post-increments.
+   (if (ne postinc 0)
+       (set Rd-sfield addr))
+   (reset-x-p))
+ ; Unit u-mem must be specified before the u-movem-* for memory address
+ ; register stall count to be right.
+ ((crisv32 (unit u-mem) (unit u-movem-rtom) (unit u-exec-movem)
+          (unit u-mem-w)))
+)
+
+; MOVEM   [Rs],Rd         [ Rd | 10111011 | Rs ]
+; MOVEM   [Rs+],Rd        [ Rd | 11111011 | Rs ]
+
+(define-pmacro
+  (movem-to-reg-step regn)
+  ; Without the SI attribute, UINT is generated, which isn't supported by
+  ; the sim framework.
+  (if (ge SI (regno Rd) regn)
+      (sequence
+       ((SI tmp))
+       (set tmp (mem SI addr))
+       (set (reg h-gr regn) tmp)
+       (set addr (add addr 4))))
+)
+
+(dni
+ movem-m-r
+ "movem to register"
+ (MACH-PRE-V32)
+ "movem [${Rs}${inc}],${Rd}"
+ (+ Rd INFIX_MOVEM_M_R MODEMEMP_YES inc SIZE_FIXED Rs)
+ (sequence
+   ((SI addr) (BI postinc))
+   ; FIXME: Mostly a copy of what's in cris-get-mem.
+
+   ; Cache the incrementness of the operand.
+   (set postinc inc)
+
+   ; Get the address from somewhere.  If the insn was prefixed, it's in
+   ; the prefix-register.
+   (set addr
+       (if SI (eq prefix-set 0)
+           Rs
+           prefixreg))
+
+   ; CGEN-FIXME: See movem-r-m.
+   (sequence ((SI dummy)) (set dummy Rd))
+
+   (.splice
+    sequence ()
+    ; The first movem step is left out because it can't happen; it's for
+    ; PC destination.  See the pattern below.
+    (.unsplice (.map movem-to-reg-step (.iota 15 14 -1))))
+
+   ; Update the source-register for post-increments.
+   ; FIXME: No postinc-prefixed for v0 IIRC.
+   (if (ne postinc 0)
+       (set Rs (if SI (eq prefix-set 0) addr prefixreg)))
+   (reset-x-p))
+   (simplecris-movem-timing)
+)
+
+; (MOVEM   [Rs],PC         [ 1111 | 10111011 | Rs ])
+; (MOVEM   [Rs+],PC        [ 1111 | 11111011 | Rs ])
+; We have to special-case it for PC destination; used in longjump.
+; We shouldn't *have* to special-case it; the main reason is (FIXME:)
+; misgeneration of the simulator when the PC case is folded into the
+; generic PRE-V32 movem; possibly related to then being a COND-CTI rather
+; than an UNCOND-CTI.
+(dni-cmt-attr
+ movem-m-pc
+ "movem to register, ending with PC"
+ (MACH-PRE-V32)
+ "movem [${Rs}${inc}],${Rd}"
+ (+ (f-dest 15) INFIX_MOVEM_M_R SIZE_FIXED Rs)
+ (sequence
+   ((SI addr) (BI postinc))
+   ; FIXME: Mostly a copy of what's in cris-get-mem.
+
+   ; Cache the incrementness of the operand.
+   (set postinc inc)
+
+   ; Get the address from somewhere.  If the insn was prefixed, it's in
+   ; the prefix-register.
+   (set addr
+       (if SI (eq prefix-set 0)
+           Rs
+           prefixreg))
+
+   ; FIXME: Add kludge here too *and* a test-case.
+
+   (.splice
+    sequence ()
+    ; The first movem step is for PC destination, used in longjmp.
+    (set pc (mem SI addr))
+    (set addr (add addr 4))
+    (.unsplice
+     (.map
+      (.pmacro
+       (regn)
+       (sequence
+        ((SI tmp))
+        (set tmp (mem SI addr))
+        (set (reg h-gr regn) tmp)
+        (set addr (add addr 4))))
+      (.iota 15 14 -1))))
+
+   ; Update the source-register for post-increments.
+   ; FIXME: No postinc-prefixed for v0.
+   (if (ne postinc 0)
+       (set Rs (if SI (eq prefix-set 0) addr prefixreg)))
+   (reset-x-p))
+)
+
+(dni
+ movem-m-r-v32
+ "movem to register"
+ (MACH-V32)
+ "movem [${Rs}${inc}],${Rd}"
+ (+ INFIX_MOVEM_M_R MODEMEMP_YES inc SIZE_FIXED Rs Rd)
+ (sequence
+   ((SI addr) (BI postinc))
+   ; FIXME: A copy of what's in cris-get-mem
+
+   ; Cache the incrementness of the operand.
+   (set postinc inc)
+
+   ; Get the address from somewhere.
+   (set addr Rs)
+
+   ; CGEN-FIXME: See movem-r-m.
+   (sequence ((SI dummy)) (set dummy Rd))
+
+   (.splice
+    sequence ()
+    (.unsplice (.map movem-to-reg-step (.iota 16))))
+
+   ; Update the source-register for post-increments.
+   ; FIXME: No postinc-prefixed for v0 IIRC.
+   (if (ne postinc 0)
+       (set Rs addr))
+   (reset-x-p))
+ ; u-mem must be specified before the u-movem-* for memory source
+ ; register stall count to be right.
+ ((crisv32 (unit u-mem) (unit u-mem-r) (unit u-movem-mtor)
+          (unit u-exec-movem)))
+)
+
+; ADD.m   Rs,Rd           [ Rd | 011000mm | Rs ]
+(dni-cdt-bwd
+ add "add from register to register"
+ "$Rs,$Rd"
+ (+ Rd MODE_REGISTER R_ADD Rs)
+ (.pmacro (BWD) (cris-arit add BWD Rd Rs))
+)
+
+; ADD.m   [Rs],Rd         [ Rd | 101000mm | Rs ]
+; ADD.m   [Rs+],Rd        [ Rd | 111000mm | Rs ]
+(dni-cmt-bwd
+ add-m "add from memory to register"
+ "[${Rs}${inc}],${Rd}"
+ (+ INDIR_ADD Rs Rd)
+ (.pmacro (BWD) (cris-arit-3op add BWD Rd (cris-get-mem BWD Rs) Rs))
+)
+; (ADD.m   [PC+],Rd        [ Rd | 111000mm | 1111 ])
+(dni-c-QI
+ addcbr "add constant byte to register"
+ "add.b ${sconst8}],${Rd}"
+ (+ Rd MODE_AUTOINCREMENT INDIR_ADD SIZE_BYTE (f-source 15) sconst8)
+ (cris-arit add QI Rd sconst8)
+)
+
+(dni-c-HI
+ addcwr "add constant word to register"
+ "add.w ${sconst16}],${Rd}"
+ (+ Rd MODE_AUTOINCREMENT INDIR_ADD SIZE_WORD (f-source 15) sconst16)
+ (cris-arit add HI Rd sconst16)
+)
+
+(dni-c-SI
+ addcdr "add constant dword to register"
+ "add.d ${const32}],${Rd}"
+ (+ Rd MODE_AUTOINCREMENT INDIR_ADD SIZE_DWORD (f-source 15) const32)
+ (cris-arit add SI Rd const32)
+)
+
+; (ADD.D   [PC+],PC        [ 1111 | 11100010 | 1111 ])
+; This insn is used for DSO-local jumps in PIC code.
+(dni
+ addcpc "Relative jump by adding constant to PC"
+ (MACH-PC)
+ "add.d ${sconst32},PC"
+ (+ (f-dest 15) MODE_AUTOINCREMENT INDIR_ADD SIZE_DWORD (f-source 15) const32)
+ (sequence
+   ((SI newpc) (SI oldpc) (SI offs))
+   (set offs const32)
+   (set oldpc (add SI pc 6))
+   (set newpc (add SI oldpc offs))
+   (set pc newpc)
+   (setf-arit SI add oldpc offs newpc cbit))
+ (simplecris-common-timing ((unit u-const32) (unit u-stall) (unit u-exec)))
+)
+
+; ADDS.z  Rs,Rd           [ Rd | 0100001z | Rs ]
+(dni-cdt-sbw
+ adds "add sign-extended from register to register"
+ "$Rs,$Rd"
+ (+ Rd MODE_REGISTER R_ADDX Rs)
+ (.pmacro (BW) (cris-arit add SI Rd ((.sym BW -ext) (trunc BW Rs))))
+)
+
+; ADDS.z  [Rs],Rd         [ Rd | 1000001z | Rs ]
+; ADDS.z  [Rs+],Rd        [ Rd | 1100001z | Rs ]
+(dni-cmt-sbw
+ adds-m "add sign-extended from memory to register"
+ "[${Rs}${inc}],$Rd"
+ (+ Rd INDIR_ADDX Rs)
+ (.pmacro (BW) (cris-arit-3op add SI Rd ((.sym BW -ext) (cris-get-mem BW Rs)) Rs))
+)
+
+; (ADDS.z  [PC+],Rd        [ Rd | 1100001z | 1111 ])
+(dni-c-QI
+ addscbr "add sign-extended constant byte to register"
+ "[${Rs}${inc}],$Rd"
+ (+ Rd MODE_AUTOINCREMENT INDIR_ADDX SIGNED_BYTE (f-source 15) sconst8)
+ (cris-arit add SI Rd (ext SI (trunc QI sconst8)))
+)
+(dni-c-HI
+ addscwr "add sign-extended constant word to register"
+ "[${Rs}${inc}],$Rd"
+ (+ Rd MODE_AUTOINCREMENT INDIR_ADDX SIGNED_WORD (f-source 15) sconst16)
+ (cris-arit add SI Rd (ext SI (trunc HI sconst16)))
+)
+
+; (ADDS.w  [],PC         [ 1111 | 10000011 | 1111 ])
+; For a PC destination, we support only the two-operand case
+; (dest == src), which is used in switch/case statements.
+; FIXME: Should implement ADD.D [PC],PC and ADDS.B [PC],PC for use if/when
+; implementing CASE_VECTOR_SHORTEN_MODE.
+(dni
+ addspcpc "add sign-extended prefixed arg to PC"
+ (MACH-PC)
+ "adds.w [PC],PC"
+ (+ (f-dest 15) MODE_INDIRECT INDIR_ADDX SIGNED_WORD (f-source 15))
+ (sequence
+   ((SI newpc) (SI oldpc) (HI offs))
+   (if (not prefix-set)
+       (error "Unexpected adds.w [PC],PC without prefix"))
+   ; We don't use cris-get-mem but instead special-case this one, since we
+   ; have most instruction fields fixed where cris-get-mem expects
+   ; field-parametrization by certain names.
+   (set offs (mem HI prefixreg))
+   (set oldpc (add SI pc 2))
+   (set newpc (add SI oldpc offs))
+   (set pc newpc)
+   (setf-arit SI add oldpc (ext SI offs) newpc cbit))
+ (simplecris-common-timing ((unit u-mem) (unit u-stall) (unit u-exec)))
+)
+
+; ADDU.z  Rs,Rd           [ Rd | 0100000z | Rs ]
+(dni-cdt-ubw
+ addu "add zero-extended from register to register"
+ "$Rs,$Rd"
+ (+ Rd MODE_REGISTER R_ADDX Rs)
+ (.pmacro (BW) (cris-arit add SI Rd ((.sym BW -zext) (trunc BW Rs))))
+)
+
+; ADDU.z  [Rs],Rd         [ Rd | 1000000z | Rs ]
+; ADDU.z  [Rs+],Rd        [ Rd | 1100000z | Rs ]
+(dni-cmt-ubw
+ addu-m "add zero-extended from memory to register"
+ "[${Rs}${inc}],$Rd"
+ (+ Rd INDIR_ADDX Rs)
+ (.pmacro (BW)
+         (cris-arit-3op add SI Rd ((.sym BW -zext) (cris-get-mem BW Rs)) Rs))
+)
+
+; (ADDU.z  [PC+],Rd        [ Rd | 1100000z | 1111 ])
+(dni-c-QI
+ adducbr "add zero-extended constant byte to register"
+ "[${Rs}${inc}],$Rd"
+ (+ Rd MODE_AUTOINCREMENT INDIR_ADDX UNSIGNED_BYTE (f-source 15) sconst8)
+ (cris-arit add SI Rd (zext SI (trunc QI sconst8)))
+)
+(dni-c-HI
+ adducwr "add zero-extended constant word to register"
+ "[${Rs}${inc}],$Rd"
+ (+ Rd MODE_AUTOINCREMENT INDIR_ADDX UNSIGNED_WORD (f-source 15) sconst16)
+ (cris-arit add SI Rd (zext SI (trunc HI sconst16)))
+)
+
+; SUB.m   Rs,Rd           [ Rd | 011010mm | Rs ]
+(dni-cdt-bwd
+ sub "subtract from register to register"
+ "$Rs,$Rd"
+ (+ Rd MODE_REGISTER R_SUB Rs)
+ (.pmacro (BWD) (cris-arit sub BWD Rd Rs))
+)
+
+; SUB.m   [Rs],Rd         [ Rd | 101010mm | Rs ]
+; SUB.m   [Rs+],Rd        [ Rd | 111010mm | Rs ]
+(dni-cmt-bwd
+ sub-m "subtract from memory to register"
+ "[${Rs}${inc}],${Rd}"
+ (+ INDIR_SUB Rs Rd)
+ (.pmacro (BWD) (cris-arit-3op sub BWD Rd (cris-get-mem BWD Rs) Rs))
+)
+
+; (SUB.m   [PC+],Rd        [ Rd | 111010mm | 1111 ]
+(dni-c-QI
+ subcbr "subtract constant byte from register"
+ "sub.b ${sconst8}],${Rd}"
+ (+ Rd MODE_AUTOINCREMENT INDIR_SUB SIZE_BYTE (f-source 15) sconst8)
+ (cris-arit sub QI Rd sconst8)
+)
+
+(dni-c-HI
+ subcwr "subtract constant word from register"
+ "sub.w ${sconst16}],${Rd}"
+ (+ Rd MODE_AUTOINCREMENT INDIR_SUB SIZE_WORD (f-source 15) sconst16)
+ (cris-arit sub HI Rd sconst16)
+)
+
+(dni-c-SI
+ subcdr "subtract constant dword from register"
+ "sub.d ${const32}],${Rd}"
+ (+ Rd MODE_AUTOINCREMENT INDIR_SUB SIZE_DWORD (f-source 15) const32)
+ (cris-arit sub SI Rd const32)
+)
+
+; SUBS.z  Rs,Rd           [ Rd | 0100101z | Rs ]
+(dni-cdt-sbw
+ subs "sub sign-extended from register to register"
+ "$Rs,$Rd"
+ (+ Rd MODE_REGISTER R_SUBX Rs)
+ (.pmacro (BW) (cris-arit sub SI Rd ((.sym BW -ext) (trunc BW Rs))))
+)
+
+; SUBS.z  [Rs],Rd         [ Rd | 1000101z | Rs ]
+; SUBS.z  [Rs+],Rd        [ Rd | 1100101z | Rs ]
+(dni-cmt-sbw
+ subs-m "sub sign-extended from memory to register"
+ "[${Rs}${inc}],$Rd"
+ (+ Rd INDIR_SUBX Rs)
+ (.pmacro (BW)
+         (cris-arit-3op sub SI Rd ((.sym BW -ext) (cris-get-mem BW Rs)) Rs))
+)
+
+; (SUBS.z  [PC+],Rd        [ Rd | 1100101z | 1111 ])
+(dni-c-QI
+ subscbr "sub sign-extended constant byte to register"
+ "[${Rs}${inc}],$Rd"
+ (+ Rd MODE_AUTOINCREMENT INDIR_SUBX SIGNED_BYTE (f-source 15) sconst8)
+ (cris-arit sub SI Rd (ext SI (trunc QI sconst8)))
+)
+(dni-c-HI
+ subscwr "sub sign-extended constant word to register"
+ "[${Rs}${inc}],$Rd"
+ (+ Rd MODE_AUTOINCREMENT INDIR_SUBX SIGNED_WORD (f-source 15) sconst16)
+ (cris-arit sub SI Rd (ext SI (trunc HI sconst16)))
+)
+
+; SUBU.z  Rs,Rd           [ Rd | 0100100z | Rs ]
+(dni-cdt-ubw
+ subu "sub zero-extended from register to register"
+ "$Rs,$Rd"
+ (+ Rd MODE_REGISTER R_SUBX Rs)
+ (.pmacro (BW) (cris-arit sub SI Rd ((.sym BW -zext) (trunc BW Rs))))
+)
+
+; SUBU.z  [Rs],Rd         [ Rd | 1000100z | Rs ]
+; SUBU.z  [Rs+],Rd        [ Rd | 1100100z | Rs ]
+(dni-cmt-ubw
+ subu-m "sub zero-extended from memory to register"
+ "[${Rs}${inc}],$Rd"
+ (+ Rd INDIR_SUBX Rs)
+ (.pmacro (BW)
+         (cris-arit-3op sub SI Rd ((.sym BW -zext) (cris-get-mem BW Rs)) Rs))
+)
+
+; (SUBU.z  [PC+],Rd        [ Rd | 1100100z | 1111 ])
+(dni-c-QI
+ subucbr "sub zero-extended constant byte to register"
+ "[${Rs}${inc}],$Rd"
+ (+ Rd MODE_AUTOINCREMENT INDIR_SUBX UNSIGNED_BYTE (f-source 15) sconst8)
+ (cris-arit sub SI Rd (zext SI (trunc QI sconst8)))
+)
+(dni-c-HI
+ subucwr "sub zero-extended constant word to register"
+ "[${Rs}${inc}],$Rd"
+ (+ Rd MODE_AUTOINCREMENT INDIR_SUBX UNSIGNED_WORD (f-source 15) sconst16)
+ (cris-arit sub SI Rd (zext SI (trunc HI sconst16)))
+)
+
+; ADDC    Rs,Rd           [ Rd | 01010111 | Rs ]
+(dni-cdt-attr
+ addc-r "addc from register to register"
+ (MACH-V32)
+ "addc $Rs,$Rd"
+ (+ Rd MODE_REGISTER RFIX_ADDC SIZE_FIXED Rs)
+ ; Since this is equivalent to "ax" plus "add.d Rs,Rd", we'll just do
+ ; that, semantically.
+ (sequence
+   ()
+   (set-quiet xbit 1)
+   (cris-arit add SI Rd Rs))
+)
+
+; ADDC    [Rs],Rd         [ Rd | 10011010 | Rs ]
+; ADDC    [Rs+],Rd        [ Rd | 11011010 | Rs ]
+(dni-cmt-attr
+ addc-m "addc from memory to register"
+ (MACH-V32)
+ "addc [${Rs}${inc}],${Rd}"
+ (+ Rd INDIR_ADDC SIZE_DWORD Rs)
+ (sequence
+   ()
+   (set-quiet xbit 1)
+   (cris-arit add SI Rd (cris-get-mem SI Rs)))
+)
+
+; (ADDC    [Rs+],Rd        [ Rd | 11011010 | 1111 ])
+(dni-c-SI-attr
+ addc-c "addc constant to register"
+ (MACH-V32)
+ "addc ${const32},${Rd}"
+ (+ Rd MODE_AUTOINCREMENT INDIR_ADDC SIZE_DWORD (f-source 15) const32)
+ (sequence
+   ()
+   (set-quiet xbit 1)
+   (cris-arit add SI Rd const32))
+)
+
+; LAPC   [PC+],Rd         [ Rd | 11010111 1111 ]
+(dni-c-SI-attr
+ lapc-d "lapc.d"
+ (MACH-V32)
+ "lapc.d ${const32-pcrel},${Rd}"
+ (+ Rd MODE_AUTOINCREMENT INFIX_LAPC SIZE_FIXED (f-source 15) const32-pcrel)
+ (sequence
+   ()
+   (set Rd const32-pcrel)
+   (reset-x-p))
+)
+
+; LAPCQ  qo,Rd            [ Rd | 10010111 | qo ]
+(dni-cdt-attr
+ lapcq "lapcq"
+ (MACH-V32)
+ "lapcq ${qo},${Rd}"
+ (+ Rd MODE_INDIRECT INFIX_LAPC SIZE_FIXED qo)
+ (sequence
+   ()
+   (set Rd qo)
+   (reset-x-p))
+)
+
+; ADDI    Rs.m,Rd         [ Rs | 010100mm | Rd ]
+(dni-cdt-bwd
+ addi "addi"
+ "${Rs-dfield}.m,${Rd-sfield}"
+ (+ Rd-sfield MODE_REGISTER R_ADDI Rs-dfield)
+ (.pmacro
+  (BWD)
+  (sequence
+    ()
+    (set Rd-sfield (add SI Rd-sfield (mul Rs-dfield (.sym BWD -size))))
+    (reset-x-p)))
+)
+
+;  NEG.m   Rs,Rd           [ Rd | 010110mm | Rs ]
+(dni-cdt-bwd
+ neg "neg.m Rs,Rd"
+ "$Rs,$Rd"
+ (+ Rd MODE_REGISTER R_NEG Rs)
+ (.pmacro (BWD) (cris-arit3 sub BWD Rd 0 Rs))
+)
+
+; TEST.m  [Rs]            [ 0000101110mm | Rs ]
+; TEST.m  [Rs+]           [ 0000111110mm | Rs ]
+(dni-cmt-bwd
+ test-m "test.m [Rs(+)]"
+ "[${Rs}${inc}]"
+ (+ (f-dest 0) INDIR_TEST Rs)
+ (.pmacro
+  (BWD)
+  (sequence
+    ((BWD tmpd))
+    (set tmpd (cris-get-mem BWD Rs))
+    ; This is supposed to be the same result as for cmpq 0,X, hence same code.
+    (cris-arit6-int
+     sub BWD (.pmacro (sz regno val) (nop)) 0 tmpd 0 cbit cbit)))
+)
+
+; MOVE.m  Rs,[Rd]         [ Rs | 101111mm | Rd ]
+; MOVE.m  Rs,[Rd+]        [ Rs | 111111mm | Rd ]
+
+(dni-cmwt-bwd
+ move-r-m "move.m R,[]"
+ "${Rs-dfield},[${Rd-sfield}${inc}]"
+ (+ Rs-dfield INDIR_MOVE_R_M Rd-sfield)
+ (.pmacro
+  (BWD)
+  (sequence
+    ((BWD tmpd))
+    (set tmpd Rs-dfield)
+    (cris-set-mem BWD Rd-sfield tmpd)
+    (reset-x-p)))
+)
+
+; MULS.m  Rs,Rd           [ Rd | 110100mm | Rs ]
+(dni-bwd-attr
+ muls "muls.m Rs,Rd"
+ ((MACH crisv10,crisv32))
+ "$Rs,$Rd"
+ (+ Rd MODE_MULS INDIR_MUL Rs)
+ (.pmacro
+  (BWD)
+  (sequence
+    ((DI src1) (DI src2) (DI tmpr))
+    (set src1 (ext DI (trunc BWD Rs)))
+    (set src2 (ext DI (trunc BWD Rd)))
+    (set tmpr (mul src1 src2))
+    (set Rd (trunc SI tmpr))
+    (set mof (trunc SI (srl tmpr 32)))
+    (setf-arit DI muls src1 src2 tmpr cbit)))
+ ((crisv10 (unit u-multiply) (unit u-exec))
+  (crisv32 (unit u-multiply) (unit u-exec)))
+)
+
+; MULU.m  Rs,Rd           [ Rd | 100100mm | Rs ]
+(dni-bwd-attr
+ mulu "mulu.m Rs,Rd"
+ ((MACH crisv10,crisv32))
+ "$Rs,$Rd"
+ (+ Rd MODE_MULU INDIR_MUL Rs)
+ (.pmacro
+  (BWD)
+  (sequence
+    ((DI src1) (DI src2) (DI tmpr))
+    (set src1 (zext DI (trunc BWD Rs)))
+    (set src2 (zext DI (trunc BWD Rd)))
+    (set tmpr (mul src1 src2))
+    (set Rd (trunc SI tmpr))
+    (set mof (trunc SI (srl tmpr 32)))
+    (setf-arit DI mulu src1 src2 tmpr cbit)))
+ ((crisv10 (unit u-multiply) (unit u-exec))
+  (crisv32 (unit u-multiply) (unit u-exec)))
+)
+
+; MCP     Ps,Rd           [ Ps | 01111111 | Rd ]
+(dni-cdt-attr
+ mcp "Multiply Carry Propagation"
+ (MACH-V32)
+ "mcp $Ps,$Rd"
+ (+ Ps MODE_REGISTER RFIX_MCP SIZE_FIXED Rd-sfield)
+ (sequence
+   ()
+   (set-quiet xbit 1)
+   (set-quiet zbit 1)
+   (cris-arit5 add SI Rd-sfield Rd-sfield Ps rbit rbit))
+)
+
+; MSTEP   Rs,Rd           [ Rd | 01111111 | Rs ]
+(dni-cdt-attr
+ mstep "Multiply step"
+ (MACH-PRE-V32)
+ "mstep $Rs,$Rd"
+ (+ Rd MODE_REGISTER RFIX_MSTEP SIZE_FIXED Rs)
+ (sequence
+   ((SI tmpd) (SI tmps))
+   (set tmps Rs)
+   (set tmpd (add (sll Rd 1) (if SI nbit tmps 0)))
+   (set Rd tmpd)
+   (setf-move SI tmpd))
+)
+
+; DSTEP   Rs,Rd           [ Rd | 01101111 | Rs ]
+(dni-cdt
+ dstep "Division step"
+ "dstep $Rs,$Rd"
+ (+ Rd MODE_REGISTER RFIX_DSTEP SIZE_FIXED Rs)
+ (sequence
+   ((SI tmp) (SI tmps) (SI tmpd))
+   (set tmps Rs)
+   (set tmp (sll Rd 1))
+   (set tmpd (if SI (geu tmp tmps) (sub tmp tmps) tmp))
+   (set Rd tmpd)
+   (setf-move SI tmpd))
+)
+
+;  ABS     Rs,Rd           [ Rd | 01101011 | Rs ]
+(dni-cdt
+ abs "Absolut Instruction"
+ "abs $Rs,$Rd"
+ (+ Rd MODE_REGISTER RFIX_ABS SIZE_FIXED Rs)
+ (sequence
+   ((SI tmpd))
+   (set tmpd (abs Rs))
+   (set Rd tmpd)
+   (setf-move SI tmpd))
+)
+
+; AND.m   Rs,Rd           [ Rd | 011100mm | Rs ]
+(dni-cdt-bwd
+ and "And from register to register"
+ "$Rs,$Rd"
+ (+ Rd MODE_REGISTER R_AND Rs)
+ (.pmacro
+  (BWD)
+  (sequence
+    ((BWD tmpd))
+    (set tmpd (and BWD Rd Rs))
+    (set-subreg-gr BWD (regno Rd) tmpd)
+    (setf-move BWD tmpd)))
+)
+
+; AND.m   [Rs],Rd         [ Rd | 101100mm | Rs ]
+; AND.m   [Rs+],Rd        [ Rd | 111100mm | Rs ]
+(dni-cmt-bwd
+ and-m "And from memory to register"
+ "[${Rs}${inc}],${Rd}"
+ (+ INDIR_AND Rs Rd)
+ (.pmacro
+  (BWD)
+  (sequence
+    ((BWD tmpd))
+    (set tmpd (and BWD Rd (cris-get-mem BWD Rs)))
+    (set-subreg-gr
+     BWD
+     (if SI (andif prefix-set (not inc)) (regno Rs) (regno Rd))
+     tmpd)
+    (setf-move BWD tmpd)))
+)
+
+; (AND.m   [PC+],Rd        [ Rd | 111100mm | 1111 ])
+(dni-c-QI
+ andcbr "And constant byte to register"
+ "and.b ${sconst8}],${Rd}"
+ (+ Rd MODE_AUTOINCREMENT INDIR_AND SIZE_BYTE (f-source 15) sconst8)
+ (sequence
+   ((QI tmpd))
+   (set tmpd (and QI Rd sconst8))
+   (set-subreg-gr QI (regno Rd) tmpd)
+   (setf-move QI tmpd))
+)
+
+(dni-c-HI
+ andcwr "And constant word to register"
+ "and.w ${sconst16}],${Rd}"
+ (+ Rd MODE_AUTOINCREMENT INDIR_AND SIZE_WORD (f-source 15) sconst16)
+ (sequence
+   ((HI tmpd))
+   (set tmpd (and HI Rd sconst16))
+   (set-subreg-gr HI (regno Rd) tmpd)
+   (setf-move HI tmpd))
+)
+
+(dni-c-SI
+ andcdr "And constant dword to register"
+ "and.d ${const32}],${Rd}"
+ (+ Rd MODE_AUTOINCREMENT INDIR_AND SIZE_DWORD (f-source 15) const32)
+ (sequence
+   ((SI tmpd))
+   (set tmpd (and SI Rd const32))
+   (set-subreg-gr SI (regno Rd) tmpd)
+   (setf-move SI tmpd))
+)
+
+; ANDQ    i,Rd            [ Rd | 001100 | i ]
+(dni-cdt
+ andq "And quick-immediate to register"
+ "andq $i,$Rd"
+ (+ Rd MODE_QUICK_IMMEDIATE Q_ANDQ i)
+ (sequence
+   ((SI tmpd))
+   (set tmpd (and SI Rd i))
+   (set-subreg-gr SI (regno Rd) tmpd)
+   (setf-move SI tmpd))
+)
+
+; OR.m    Rs,Rd           [ Rd | 011101mm | Rs ]
+(dni-cdt-bwd
+ orr "Or from register to register"
+ "$Rs,$Rd"
+ (+ Rd MODE_REGISTER R_OR Rs)
+ (.pmacro
+  (BWD)
+  (sequence
+    ((BWD tmpd))
+    (set tmpd (or BWD Rd Rs))
+    (set-subreg-gr BWD (regno Rd) tmpd)
+    (setf-move BWD tmpd)))
+)
+
+; OR.m    [Rs],Rd         [ Rd | 101101mm | Rs ]
+; OR.m    [Rs+],Rd        [ Rd | 111101mm | Rs ]
+(dni-cmt-bwd
+ or-m "Or from memory to register"
+ "[${Rs}${inc}],${Rd}"
+ (+ INDIR_OR Rs Rd)
+ (.pmacro
+  (BWD)
+  (sequence
+    ((BWD tmpd))
+    (set tmpd (or BWD Rd (cris-get-mem BWD Rs)))
+    (set-subreg-gr
+     BWD
+     (if SI (andif prefix-set (not inc)) (regno Rs) (regno Rd))
+     tmpd)
+    (setf-move BWD tmpd)))
+)
+
+; (OR.m    [PC+],Rd        [ Rd | 111101mm | 1111 ])
+(dni-c-QI
+ orcbr "Or constant byte to register"
+ "or.b ${sconst8}],${Rd}"
+ (+ Rd MODE_AUTOINCREMENT INDIR_OR SIZE_BYTE (f-source 15) sconst8)
+ (sequence
+   ((QI tmpd))
+   (set tmpd (or QI Rd sconst8))
+   (set-subreg-gr QI (regno Rd) tmpd)
+   (setf-move QI tmpd))
+)
+
+(dni-c-HI
+ orcwr "Or constant word to register"
+ "or.w ${sconst16}],${Rd}"
+ (+ Rd MODE_AUTOINCREMENT INDIR_OR SIZE_WORD (f-source 15) sconst16)
+ (sequence
+   ((HI tmpd))
+   (set tmpd (or HI Rd sconst16))
+   (set-subreg-gr HI (regno Rd) tmpd)
+   (setf-move HI tmpd))
+)
+
+(dni-c-SI
+ orcdr "Or constant dword to register"
+ "or.d ${const32}],${Rd}"
+ (+ Rd MODE_AUTOINCREMENT INDIR_OR SIZE_DWORD (f-source 15) const32)
+ (sequence
+   ((SI tmpd))
+   (set tmpd (or SI Rd const32))
+   (set-subreg-gr SI (regno Rd) tmpd)
+   (setf-move SI tmpd))
+)
+
+; ORQ     i,Rd            [ Rd | 001101 | i ]
+(dni-cdt
+ orq "Or quick-immediate to register"
+ "orq $i,$Rd"
+ (+ Rd MODE_QUICK_IMMEDIATE Q_ORQ i)
+ (sequence
+   ((SI tmpd))
+   (set tmpd (or SI Rd i))
+   (set-subreg-gr SI (regno Rd) tmpd)
+   (setf-move SI tmpd))
+)
+
+; XOR     Rs,Rd           [ Rd | 01111011 | Rs ]
+(dni-cdt
+ xor "Xor from register to register"
+ "xor $Rs,$Rd"
+ (+ Rd MODE_REGISTER RFIX_XOR SIZE_FIXED Rs)
+ (sequence
+   ((SI tmpd))
+   (set tmpd (xor SI Rd Rs))
+   (set Rd tmpd)
+   (setf-move SI tmpd))
+)
+
+(define-pmacro (swap-r x)
+  "Perform bit-wise swap within each byte"
+  (sequence
+    SI
+    ((SI tmpr))
+    (set tmpr x)
+    (or (sll (and tmpr #x1010101) 7)
+       (or (sll (and tmpr #x2020202) 5)
+           (or (sll (and tmpr #x4040404) 3)
+               (or (sll (and tmpr #x8080808) 1)
+                   (or (srl (and tmpr #x10101010) 1)
+                       (or (srl (and tmpr #x20202020) 3)
+                           (or (srl (and tmpr #x40404040) 5)
+                               (srl (and tmpr #x80808080) 7)))))))))
+)
+
+(define-pmacro (swap-b x)
+  "Perform byte-wise swap within each word"
+  (sequence
+    SI
+    ((SI tmpb))
+    (set tmpb x)
+    (or (and (sll tmpb 8) #xff00ff00)
+       (and (srl tmpb 8) #xff00ff)))
+)
+
+(define-pmacro (swap-w x)
+  "Perform word-wise swap within each dword"
+  (sequence
+    SI
+    ((SI tmpb))
+    (set tmpb x)
+    (or (and (sll tmpb 16) #xffff0000)
+       (and (srl tmpb 16) #xffff)))
+)
+
+(define-pmacro (swap-_ x)
+  "Do nothing swap-wise"
+  (error SI "SWAP without swap modifier isn't implemented")
+)
+
+(define-pmacro (swap-n x)
+  "Perform bitwise not (that is, perform a not, not not perform)"
+  (inv x)
+)
+
+(define-pmacro (swap-br x) "Combine swap-r and swap-b" (swap-r (swap-b x)))
+(define-pmacro (swap-wr x) "Combine swap-r and swap-w" (swap-r (swap-w x)))
+(define-pmacro (swap-wb x) "Combine swap-b and swap-w" (swap-b (swap-w x)))
+(define-pmacro (swap-wbr x) "Combine swap-r and swap-wb" (swap-r (swap-wb x)))
+(define-pmacro (swap-nr x) "Combine swap-r and swap-n" (swap-r (swap-n x)))
+(define-pmacro (swap-nb x) "Combine swap-n and swap-b" (swap-b (swap-n x)))
+(define-pmacro (swap-nbr x) "Combine swap-r and swap-nb" (swap-r (swap-nb x)))
+(define-pmacro (swap-nw x) "Combine swap-n and swap-w" (swap-w (swap-n x)))
+(define-pmacro (swap-nwr x) "Combine swap-r and swap-nw" (swap-r (swap-nw x)))
+(define-pmacro (swap-nwb x) "Combine swap-b and swap-nw" (swap-b (swap-nw x)))
+(define-pmacro (swap-nwbr x) "Combine swap-r and swap-nwb" (swap-r (swap-nwb x)))
+
+(define-pmacro (cris-swap swapcode val)
+  (sequence
+    SI
+    ((SI tmpcode) (SI tmpval) (SI tmpres))
+    (set tmpcode swapcode)
+    (set tmpval val)
+    (.splice
+     cond
+     (.unsplice
+      (.map
+       (.pmacro
+       (x-swapcode x-swap)
+       ((eq tmpcode x-swapcode)
+        (set tmpres ((.sym swap- x-swap) tmpval))))
+       (.iota 16)
+       (.splice _ (.unsplice cris-swap-codes)))))
+    tmpres)
+)
+
+; NOT     Rd              alias for SWAPN Rd
+(dni-cdt-attr
+ not "Not"
+ ((MACH crisv0,crisv3))
+ "not ${Rs}"
+ (+ (f-dest 8) RFIX_SWAP MODE_REGISTER SIZE_FIXED Rd-sfield)
+ (sequence
+   ((SI tmp) (SI tmpd))
+   (set tmp Rd-sfield)
+   (set tmpd (cris-swap 8 tmp))
+   (set Rd-sfield tmpd)
+   (setf-move SI tmpd))
+)
+
+; SWAP<option>    Rd      [ N W B R | 01110111 | Rd ]
+(dni-cdt-attr
+ swap "Swap"
+ ((MACH crisv8,crisv10,crisv32))
+ "swap${swapoption} ${Rs}"
+ (+ swapoption RFIX_SWAP MODE_REGISTER SIZE_FIXED Rd-sfield)
+ (sequence
+   ((SI tmps) (SI tmpd))
+   (set tmps Rd-sfield)
+   (set tmpd (cris-swap swapoption tmps))
+   (set Rd-sfield tmpd)
+   (setf-move SI tmpd))
+)
+
+; ASR.m   Rs,Rd           [ Rd | 011110mm | Rs ]
+(dni-cdt-bwd
+ asrr "Arithmetic shift right register count"
+ "$Rs,$Rd"
+ (+ Rd MODE_REGISTER R_ASR Rs)
+ (.pmacro
+  (BWD)
+  (sequence
+    ((BWD tmpd) (SI cnt1) (SI cnt2))
+    (set cnt1 Rs)
+    (set cnt2 (if SI (ne (and cnt1 32) 0) 31 (and cnt1 31)))
+    (set tmpd (sra SI (ext SI (trunc BWD Rd)) cnt2))
+    (set-subreg-gr BWD (regno Rd) tmpd)
+    (setf-move BWD tmpd)))
+)
+
+; ASRQ    c,Rd            [ Rd | 0011101 | c ]
+(dni-cdt
+ asrq "Arithmetic shift right quick-immediate count"
+ "asrq $c,${Rd}"
+ (+ Rd Q_ASHQ MODE_QUICK_IMMEDIATE (f-b5 1) c)
+ (sequence
+   ((SI tmpd))
+   (set tmpd (sra Rd c))
+   (set Rd tmpd)
+   (setf-move SI tmpd))
+)
+
+; LSR.m   Rs,Rd           [ Rd | 011111mm | Rs ]
+(dni-cdt-bwd
+ lsrr "Logical shift right register count"
+ "$Rs,$Rd"
+ (+ Rd MODE_REGISTER R_LSR Rs)
+ (.pmacro
+  (BWD)
+  (sequence
+    ((SI tmpd) (SI cnt))
+    (set cnt (and Rs 63))
+    (set
+     tmpd
+     (if SI (ne (and cnt 32) 0)
+        0
+        (srl SI (zext SI (trunc BWD Rd)) (and cnt 31))))
+    (set-subreg-gr BWD (regno Rd) tmpd)
+    (setf-move BWD tmpd)))
+)
+
+; LSRQ    c,Rd            [ Rd | 0011111 | c ]
+(dni-cdt
+ lsrq "Logical shift right quick-immediate count"
+ "lsrq $c,${Rd}"
+ (+ Rd Q_LSHQ MODE_QUICK_IMMEDIATE (f-b5 1) c)
+ (sequence
+   ((SI tmpd))
+   (set tmpd (srl Rd c))
+   (set Rd tmpd)
+   (setf-move SI tmpd))
+)
+
+; LSL.m   Rs,Rd           [ Rd | 010011mm | Rs ]
+(dni-cdt-bwd
+ lslr "Logical shift left register count"
+ "$Rs,$Rd"
+ (+ Rd MODE_REGISTER R_LSL Rs)
+ (.pmacro
+  (BWD)
+  (sequence
+    ((SI tmpd) (SI cnt))
+    (set cnt (and Rs 63))
+    (set
+     tmpd
+     (if SI (ne (and cnt 32) 0)
+        0
+        (sll SI (zext SI (trunc BWD Rd)) (and cnt 31))))
+    (set-subreg-gr BWD (regno Rd) tmpd)
+    (setf-move BWD tmpd)))
+)
+
+; LSLQ    c,Rd            [ Rd | 0011110 | c ]
+(dni-cdt
+ lslq "Logical shift left quick-immediate count"
+ "lslq $c,${Rd}"
+ (+ Rd Q_LSHQ MODE_QUICK_IMMEDIATE (f-b5 0) c)
+ (sequence
+   ((SI tmpd))
+   (set tmpd (sll Rd c))
+   (set Rd tmpd)
+   (setf-move SI tmpd))
+)
+
+; BTST    Rs,Rd           [ Rd | 01001111 | Rs ]
+(dni-cdt
+ btst "Bit test register number"
+ "$Rs,$Rd"
+ (+ Rd MODE_REGISTER RFIX_BTST SIZE_FIXED Rs)
+ (sequence
+   ((SI tmpd) (SI cnt))
+   (set tmpd (sll Rd (sub 31 (and Rs 31))))
+   (setf-move SI tmpd))
+)
+
+; BTSTQ   c,Rd            [ Rd | 0011100 | c ]
+(dni-cdt
+ btstq "Bit test quick-immediate number"
+ "btstq $c,${Rd}"
+ (+ Rd Q_ASHQ MODE_QUICK_IMMEDIATE (f-b5 0) c)
+ (sequence
+   ((SI tmpd))
+   (set tmpd (sll Rd (sub 31 c)))
+   (setf-move SI tmpd))
+)
+
+; SETF    <list of flags> [ P U I X | 01011011 | N Z V C ]
+(dni-cdt
+ setf "Set condition code flags explicitly"
+ "setf ${list-of-flags}"
+ ; The zero-flags case gets flag operands wrong; there's a "_"
+ ; where there should have been nothing.  Also, flags are in
+ ; assembly code allowed to be specified in any order, which
+ ; doesn't match the "flagbits" settings.  Luckily we don't
+ ; use this field for assembly.
+ (+ RFIX_SETF MODE_REGISTER SIZE_FIXED list-of-flags)
+ (.splice
+  sequence
+  ((SI tmp))
+  (set tmp list-of-flags)
+  (.unsplice
+   (.map
+    (.pmacro (ccbit)
+            (if (ne (and tmp (sll 1 (.sym ccbit -bitnumber))) 0)
+                (set (.sym ccbit bit) 1)))
+    cris-flagnames))
+   (set prefix-set 0)
+   ; Unless x was specified to be set, set it to 0.
+   (if (eq (and tmp (sll 1 x-bitnumber)) 0)
+       (set xbit 0)))
+)
+
+; CLEARF  <list of flags> [ P U I X | 01011111 | N Z V C ]
+(dni-cdt
+ clearf "Clear condition code flags explicitly"
+ "clearf ${list-of-flags}"
+ ; The zero-flags case gets flag operands wrong; there's a "_"
+ ; where there should have been nothing.  Also, flags are in
+ ; assembly code allowed to be specified in any order, which
+ ; doesn't match the "flagbits" settings.  Luckily we don't
+ ; use this field for assembly.
+ (+ RFIX_CLEARF MODE_REGISTER SIZE_FIXED list-of-flags)
+ (.splice
+  sequence
+  ((SI tmp))
+  (set tmp list-of-flags)
+  (.unsplice
+   (.map
+    (.pmacro (ccbit)
+            (if (ne (and tmp (sll 1 (.sym ccbit -bitnumber))) 0)
+                (set (.sym ccbit bit) 0)))
+    cris-flagnames))
+   (reset-x-p))
+)
+
+(define-pmacro
+  (rfe-rfn-guts)
+  "Common parts of RFE and RFN"
+  (sequence
+    ((USI oldccs) (USI samebits) (USI shiftbits) (USI keepmask) (BI p1))
+    (set oldccs ccs)
+    ; Keeping U, S and I in user mode is handled by the CCS setter, so we
+    ; don't have to bother.  Actually Q and M are handled too.  The reason
+    ; to mask those out is to not have them shifted down into the second
+    ; flags level.
+    (set keepmask #xc0000000)
+    (set samebits (and oldccs keepmask))
+    ; The P bit has its own equation.
+    (set shiftbits (and (srl (and oldccs #x3ffdfc00) 10) (inv keepmask)))
+    (set p1 (ne 0 (and oldccs #x20000)))
+    (set ccs (or (or samebits shiftbits)
+                (if SI (and rbit (not p1)) 0 #x80))))
+)
+
+; RFE                     [ 0010 10010011 0000 ]
+(dni-cdt-attr
+ rfe
+ "RFE"
+ (MACH-V32)
+ "rfe"
+ (+ (f-dest 2) MODE_INDIRECT INFIX_RFE SIZE_FIXED (f-source 0))
+ (rfe-rfn-guts)
+)
+
+; SFE                     [ 0011 10010011 0000 ]
+(dni-cdt-attr
+ sfe
+ "SFE"
+ (MACH-V32)
+ "sfe"
+ (+ (f-dest 3) MODE_INDIRECT INFIX_SFE SIZE_FIXED (f-source 0))
+ (sequence
+   ((SI oldccs) (SI savemask))
+   (set savemask #xc0000000)
+   (set oldccs ccs)
+   (set ccs
+       (or (and savemask oldccs)
+           (and (inv savemask) (sll oldccs 10)))))
+)
+
+; RFG                     [ 0100 10010011 0000 ]
+(dni-cdt-attr
+ rfg
+ "RFG"
+ (MACH-V32)
+ "rfg"
+ (+ (f-dest 4) MODE_INDIRECT INFIX_RFG SIZE_FIXED (f-source 0))
+ (c-call VOID "@cpu@_rfg_handler" pc)
+)
+
+; RFN                     [ 0101 10010011 0000 ]
+(dni-cdt-attr
+ rfn
+ "RFN"
+ (MACH-V32)
+ "rfn"
+ (+ (f-dest 5) MODE_INDIRECT INFIX_RFN SIZE_FIXED (f-source 0))
+ (sequence () (rfe-rfn-guts) (set mbit 1))
+)
+
+; HALT                     [ 1111 10010011 0000 ]
+(dni-cdt-attr
+ halt
+ "HALT"
+ (MACH-V32)
+ "halt"
+ (+ (f-dest 15) MODE_INDIRECT INFIX_HALT SIZE_FIXED (f-source 0))
+ (set pc (c-call USI "@cpu@_halt_handler" pc))
+)
+
+; Bcc     o               [ cc | 0000 | o ]
+(dni
+ bcc-b "bcc byte operand"
+ ()
+ "b${cc} ${o-pcrel}"
+ (+ cc QHI_BCC MODE_QUICK_IMMEDIATE o-pcrel)
+ (sequence
+   ((BI truthval))
+   (set truthval (cris-condition cc))
+
+   ; Amazing as it may seem, there's no simpler way to find out
+   ; whether a branch is taken or not than to mark it through a kludge
+   ; like this.
+   (c-call VOID "@cpu@_branch_taken" pc o-pcrel truthval)
+
+   (reset-x-p)
+   (if truthval
+       (delay 1
+             (set pc o-pcrel))))
+ (.splice (.unsplice (simplecris-timing))
+         (crisv32 (unit u-branch) (unit u-exec)))
+)
+(dni
+ ba-b "ba byte operand"
+ ()
+ "ba ${o-pcrel}"
+ (+ (f-dest 14) QHI_BCC MODE_QUICK_IMMEDIATE o-pcrel)
+ (sequence
+   ()
+   (reset-x-p)
+   (delay 1
+         (set pc o-pcrel)))
+ ((crisv32 (unit u-jump) (unit u-exec)))
+)
+
+; Bcc     [PC+]           [ cc | 11011111 1111 ]
+; (We don't implement the generic for pre-V32 but unused variant
+; "Bcc [Rn(+)]" where n != 15.)
+(dni
+ bcc-w "bcc, word operand"
+ ()
+ "b${cc} ${o-word-pcrel}"
+ (+ cc MODE_AUTOINCREMENT INFIX_BCC_M SIZE_FIXED (f-source 15) o-word-pcrel)
+ (sequence
+   ((BI truthval))
+   (set truthval (cris-condition cc))
+
+   ; Amazing as it may seem, there's no simpler way to find out
+   ; whether a branch is taken or not than to mark it through a kludge
+   ; like this.
+   (c-call VOID "@cpu@_branch_taken" pc o-word-pcrel truthval)
+
+   (reset-x-p)
+   (if truthval
+       (delay 1
+             (set pc o-word-pcrel))))
+ (.splice
+  (.unsplice (simplecris-common-timing ((unit u-const16) (unit u-exec))))
+  (crisv32 (unit u-const16) (unit u-branch) (unit u-exec)))
+)
+(dni
+ ba-w "ba word operand"
+ ()
+ "ba ${o-word-pcrel}"
+ (+ (f-dest 14) MODE_AUTOINCREMENT INFIX_BCC_M SIZE_FIXED (f-source 15) o-word-pcrel)
+ (sequence
+   ()
+   (reset-x-p)
+   (delay 1
+         (set pc o-word-pcrel)))
+ (.splice
+  (.unsplice (simplecris-common-timing ((unit u-const16) (unit u-exec))))
+  (crisv32 (unit u-const16) (unit u-jump) (unit u-exec)))
+)
+
+; JAS     Rs,Pd           [ Pd | 10011011 | Rs ]
+(dni
+ jas-r "JAS register"
+ (MACH-V32)
+ "jas ${Rs},${Pd}"
+ (+ Pd MODE_INDIRECT INFIX_JAS_R SIZE_FIXED Rs)
+ (sequence
+   ()
+   (reset-x-p)
+   (if (andif (eq (regno Rs) 1) (eq (regno Pd) 11))
+       ; We use this as a trigger; a normally reasonably rare instruction
+       ; used in the v32 trampoline.  See comment at bdapqpc.
+       ; CGEN-FIXME: can't use (regno srp) [== (regno (reg h-sr 11))]
+       (c-call VOID "cris_flush_simulator_decode_cache" pc))
+   (delay 1
+         (sequence
+           ()
+           (set Pd (add SI pc 4))
+           (set pc Rs))))
+ ((crisv32 (unit u-jump-r) (unit u-jump) (unit u-exec)))
+)
+; Same semantics in pre-V32, except no delay-slot.
+; FIXME: Missing JIRC/JSRC/JBRC.
+(dni-cdt-attr
+ jump-r "JUMP/JSR/JIR register"
+ (MACH-PC)
+ "jump/jsr/jir ${Rs}"
+ (+ Pd MODE_INDIRECT INFIX_JUMP_R SIZE_FIXED Rs)
+ (sequence
+   ()
+   (set Pd (add SI pc 2))
+   (set pc Rs)
+   (reset-x-p))
+)
+
+; JAS     [PC+],Pd        [ Pd | 11011011 1111 ]
+(dni
+ jas-c "JAS constant"
+ (MACH-V32)
+ "jas ${const32},${Pd}"
+ (+ Pd MODE_AUTOINCREMENT INFIX_JAS_M SIZE_FIXED (f-source 15) const32)
+ (sequence
+   ()
+   (reset-x-p)
+   (delay 1
+         (sequence
+           ()
+           (set Pd (add SI pc 8))
+           (set pc const32))))
+ ((crisv32 (unit u-const32) (unit u-jump) (unit u-exec)))
+)
+
+;        JUMP/JSR/JIR  | Special r.| 1  m| 0  1  0  0| 1  1| Source    |
+(dni-cmt-attr
+ jump-m "JUMP/JSR/JIR memory"
+ (MACH-PC)
+ "jump/jsr/jir [${Rs}${inc}]"
+ (+ Pd INFIX_JUMP_M SIZE_FIXED Rs)
+ (sequence
+   ()
+   (set Pd (add SI pc 2))
+   (set pc (cris-get-mem SI Rs))
+   (reset-x-p))
+)
+(dni-c-SI-attr
+ jump-c "JUMP/JSR/JIR constant"
+ (MACH-PC)
+ "jump/jsr/jir ${const32}"
+ (+ Pd MODE_AUTOINCREMENT INFIX_JUMP_M SIZE_FIXED (f-source 15) const32)
+ (sequence
+   ()
+   (set Pd (add SI pc 6))
+   (set pc const32)
+   (reset-x-p))
+)
+
+; JUMP    Ps              [ Ps | 10011111 0000 ]
+(dni
+ jump-p "JUMP special register"
+ (MACH-V32)
+ "jump ${Ps}"
+ (+ Ps MODE_INDIRECT INFIX_JUMP_P SIZE_FIXED (f-source 0))
+ (sequence
+   ()
+   (reset-x-p)
+   (delay 1
+         (set pc Ps)))
+ ((crisv32 (unit u-jump-sr)
+          (unit u-exec)))
+)
+
+; BAS     [PC+],Pd        [ Pd | 11101011 1111 ]
+(dni
+ bas-c "BAS constant"
+ (MACH-V32)
+ "bas ${const32},${Pd}"
+ (+ Pd MODE_AUTOINCREMENT INFIX_BAS SIZE_FIXED (f-source 15) const32-pcrel)
+ (sequence
+   ()
+   (reset-x-p)
+   (delay 1
+         (sequence
+           ()
+           (set Pd (add SI pc 8))
+           (set pc const32-pcrel))))
+ ((crisv32 (unit u-const32) (unit u-jump) (unit u-exec)))
+)
+
+; JASC    Rs,Pd           [ Pd | 10110011 | Rs ]
+(dni
+ jasc-r "JASC register"
+ (MACH-V32)
+ "jasc ${Rs},${Pd}"
+ (+ Pd MODE_INDIRECT INFIX_JASC SIZE_FIXED Rs)
+ (sequence
+   ()
+   (reset-x-p)
+   (delay 1
+         (sequence
+           ()
+           (set Pd (add SI pc 8))
+           (set pc Rs))))
+ ((crisv32 (unit u-jump-r) (unit u-skip4) (unit u-jump) (unit u-exec)))
+)
+
+; JASC    [PC+],Pd        [ Pd | 11110011 1111 ]
+(dni
+ jasc-c "JASC constant"
+ (MACH-V32)
+ "jasc ${const32},${Pd}"
+ (+ Pd MODE_AUTOINCREMENT INFIX_JASC SIZE_FIXED (f-source 15) const32)
+ (sequence
+   ()
+   (reset-x-p)
+   (delay 1
+         (sequence
+           ()
+           (set Pd (add SI pc 12))
+           (set pc const32))))
+ ((crisv32 (unit u-const32) (unit u-skip4) (unit u-jump) (unit u-exec)))
+)
+
+; BASC    [PC+],Pd        [ Pd | 11101111 1111 ]
+(dni
+ basc-c "BASC constant"
+ (MACH-V32)
+ "basc ${const32},${Pd}"
+ (+ Pd MODE_AUTOINCREMENT INFIX_BASC SIZE_FIXED (f-source 15) const32-pcrel)
+ (sequence
+   ()
+   (reset-x-p)
+   (delay 1
+         (sequence
+           ()
+           (set Pd (add SI pc 12))
+           (set pc const32-pcrel))))
+ ((crisv32 (unit u-const32) (unit u-skip4) (unit u-jump) (unit u-exec)))
+)
+
+; BREAK     n             [ 1110 | 10010011 | n ]
+
+(dni-cdt
+ break "break"
+ "break $n"
+ (+ (f-operand2 #xe) MODE_INDIRECT INFIX_BREAK SIZE_FIXED n)
+ (sequence () (reset-x-p) (set pc (c-call USI "@cpu@_break_handler" n pc)))
+)
+
+; BOUND.m Rs,Rd           [ Rd | 010111mm | Rs ]
+(dni-cdt-bwd
+ bound-r "Bound register"
+ "${Rs},${Rd}"
+ (+ Rd R_BOUND MODE_REGISTER Rs)
+ (.pmacro
+  (BWD)
+  (sequence
+    ((SI tmpopd) (SI tmpops) (SI newval))
+    (set tmpops ((.sym BWD -zext) (trunc BWD Rs)))
+    (set tmpopd Rd)
+    (set newval (if SI (ltu tmpops tmpopd) tmpops tmpopd))
+    (set Rd newval)
+    (setf-move SI newval)))
+)
+
+; BOUND.m [Rs],Rd         [ Rd | 100111mm | Rs ]
+; BOUND.m [Rs+],Rd        [ Rd | 110111mm | Rs ]
+(dni-cmt-bwd-attr
+ bound-m "Bound memory"
+ (MACH-PRE-V32)
+ "[${Rs}${inc}],${Rd}"
+ (+ Rd INDIR_BOUND Rs)
+ (.pmacro
+  (BWD)
+  (sequence
+    ((SI tmpopd) (SI tmpops) (SI newval))
+    (set tmpops ((.sym BWD -zext) (cris-get-mem BWD Rs)))
+    (set tmpopd Rd)
+    (set newval (if SI (ltu tmpops tmpopd) tmpops tmpopd))
+    (if (andif prefix-set (not inc))
+       (set Rs newval)
+       (set Rd newval))
+    (setf-move SI newval)))
+)
+
+; (BOUND.m [PC+],Rd        [ Rd | 110111mm | 1111 ])
+(dni-c-QI
+ bound-cb "Bound constant byte"
+ "bound.b [PC+],${Rd}"
+ (+ Rd MODE_AUTOINCREMENT INDIR_BOUND SIZE_BYTE (f-source 15) uconst8)
+ (sequence
+   ((SI tmpopd) (SI tmpops) (SI newval))
+   (set tmpops (zext SI (trunc QI uconst8)))
+    (set tmpopd Rd)
+    (set newval (if SI (ltu tmpops tmpopd) tmpops tmpopd))
+    (set Rd newval)
+    (setf-move SI newval))
+)
+(dni-c-HI
+ bound-cw "Bound constant word"
+ "bound.w [PC+],${Rd}"
+ (+ Rd MODE_AUTOINCREMENT INDIR_BOUND SIZE_WORD (f-source 15) uconst16)
+ (sequence
+   ((SI tmpopd) (SI tmpops) (SI newval))
+   (set tmpops (zext SI uconst16))
+    (set tmpopd Rd)
+    (set newval (if SI (ltu tmpops tmpopd) tmpops tmpopd))
+    (set Rd newval)
+    (setf-move SI newval))
+)
+(dni-c-SI
+ bound-cd "Bound constant dword"
+ "bound.d [PC+],${Rd}"
+ (+ Rd MODE_AUTOINCREMENT INDIR_BOUND SIZE_DWORD (f-source 15) const32)
+ (sequence
+   ((SI tmpopd) (SI tmpops) (SI newval))
+   (set tmpops const32)
+    (set tmpopd Rd)
+    (set newval (if SI (ltu tmpops tmpopd) tmpops tmpopd))
+    (set Rd newval)
+    (setf-move SI newval))
+)
+
+; Scc     Rd              [ cc | 01010011 | Rd ]
+(dni-cdt
+ scc "scc"
+ "s${cc} ${Rd-sfield}"
+ (+ cc MODE_REGISTER RFIX_SCC SIZE_FIXED Rd-sfield)
+ (sequence
+   ((BI truthval))
+   (set truthval (cris-condition cc))
+   (set Rd-sfield (zext SI truthval))
+   (reset-x-p))
+)
+
+; LZ      Rs,Rd           [ Rd | 01110011 | Rs ]
+(dni-cdt-attr
+ lz "lz"
+ (MACH-V3-UP)
+ "lz ${Rs},${Rd}"
+ (+ Rd MODE_REGISTER RFIX_LZ SIZE_FIXED Rs)
+ (sequence
+   ((SI tmpd) (SI tmp))
+   (set tmp Rs)
+   (set tmpd 0)
+   (.splice
+    sequence
+    ()
+    (.unsplice
+     (.map
+      (.pmacro (n)
+              (if (ge tmp 0)
+                  (sequence
+                    ()
+                    (set tmp (sll tmp 1))
+                    (set tmpd (add tmpd 1)))))
+      (.iota 32))))
+   (set Rd tmpd)
+   (setf-move SI tmpd))
+)
+
+; ADDOQ   o,Rs,ACR        [ Rs | 0001 | o ]
+(dni-cdt
+ addoq "addoq"
+ "addoq $o,$Rs,ACR"
+ (+ Rs-dfield MODE_QUICK_IMMEDIATE QHI_ADDOQ o)
+ (sequence
+   ()
+   (set prefixreg (add SI Rs-dfield o))
+   (set prefix-set 1))
+)
+
+; (BDAPQ   o,PC        [ 1111 | 0001 | o ])
+; This [PC+I] prefix is used in trampolines.
+(dni-cdt-attr
+ bdapqpc "bdapq pc operand"
+ (MACH-PC UNCOND-CTI)
+ "bdapq $o,PC"
+ (+ (f-dest 15) MODE_QUICK_IMMEDIATE QHI_BDAP o)
+ (sequence
+   ()
+   (set prefixreg (add SI (add SI pc 2) o))
+   (set prefix-set 1)
+   ; When this *rare* instruction is seen, we're may be about to write
+   ; into code to be executed soon, *probably* covering addresses decoded
+   ; and executed before.  If the simulator does not implement snooping
+   ; and automatic decoder flush, it will execute old code.  This call
+   ; is a kludge for such simulators, asking it to abandon such cached
+   ; information.  Anyway, it is hopefully enough to make CGEN-sim not
+   ; hork on gcc trampolines.
+   ; We mark this insn as UNCOND-CTI so this insn will end a simulator
+   ; basic block (the atomic unit of translation).
+   (c-call VOID "cris_flush_simulator_decode_cache" pc))
+)
+
+; (BDAP.D  [PC+],PC   [ 1111 | 11010110 | 1111 ]
+; This [PC+I] prefix is used for DSO-local jumps in PIC code, together with
+; move-m-pcplus-p0: "move [pc=pc+N],p0"
+(dni-c-SI-attr
+ bdap-32-pc "bdap.d [PC+],PC"
+ (MACH-PC)
+ "bdap ${sconst32},PC"
+ (+ (f-dest 15) MODE_AUTOINCREMENT INDIR_BDAP_M SIZE_DWORD (f-source 15) const32)
+ (sequence
+   ((SI newpc) (SI oldpc) (SI offs))
+   (set offs const32)
+   (set oldpc (add SI pc 6))
+   (set newpc (add SI oldpc offs))
+   (set prefixreg newpc)
+   (set prefix-set 1))
+)
+
+; (MOVE    [PC+],P0        [ 0000 | 11100011 | 1111 ])
+; This insn is used for DSO-local jumps in PIC code.  See bdap-32-pc.
+(dni ; Must not use dni-cmt-* because we force MODE_AUTOINCREMENT.
+ move-m-pcplus-p0 "move [PC+],P0"
+ (MACH-PC)
+ "move [PC+],P0"
+ (+ (f-dest 0) MODE_AUTOINCREMENT INFIX_MOVE_M_S SIZE_FIXED (f-source 15))
+ (if prefix-set
+     (sequence
+       ((QI dummy))
+       ; We model the memory read, but throw the result away, as the
+       ; destination register is read-only.  We need to assign the result of
+       ; cris-get-mem though, as CGEN-FIXME: invalid C code will otherwise
+       ; be generated.
+       (set dummy (cris-get-mem QI pc))
+       (reset-x-p))
+     (error "move [PC+],P0 without prefix is not implemented"))
+ (cris-mem-timing)
+)
+
+; This insn is used in Linux in the form "move [$sp=$sp+16],$p8"; it's
+; similar to move-m-pcplus-p0 above.  The same comments apply here.
+(dni
+ move-m-spplus-p8 "move [SP+],P8"
+ (MACH-PC)
+ "move [SP+],P8"
+ (+ (f-dest 8) MODE_AUTOINCREMENT INFIX_MOVE_M_S SIZE_FIXED (f-source 14))
+ (if prefix-set
+     (sequence
+       ((SI dummy))
+       (set dummy (cris-get-mem SI sp))
+       (reset-x-p))
+     (error "move [SP+],P8 without prefix is not implemented"))
+ (cris-mem-timing)
+)
+
+; ADDO.m  [Rs],Rd,ACR    [ Rd | 100101mm | Rs ]
+; ADDO.m  [Rs+],Rd,ACR   [ Rd | 110101mm | Rs ]
+(dni-cmt-bwd
+ addo-m "addo.m memory"
+ "[${Rs}${inc}],$Rd,ACR"
+ (+ Rd INDIR_ADDO Rs)
+ (.pmacro
+  (BWD)
+  (sequence
+    ((BWD tmps))
+    (set tmps (cris-get-mem BWD Rs))
+    (set prefixreg (add SI Rd ((.sym BWD -ext) tmps)))
+    (set prefix-set 1)))
+)
+
+; (ADDO.m  [PC+],Rd,ACR   [ Rd | 110101mm | 1111 ]
+(dni-c-QI
+ addo-cb "addo.b const"
+ "addo.b [PC+],$Rd,ACR"
+ (+ Rd MODE_AUTOINCREMENT INDIR_ADDO SIZE_BYTE (f-source 15) sconst8)
+ (sequence
+   ()
+   (set prefixreg (add SI Rd (ext SI (trunc QI sconst8))))
+   (set prefix-set 1))
+)
+(dni-c-HI
+ addo-cw "addo.w const"
+ "addo.w [PC+],$Rd,ACR"
+ (+ Rd MODE_AUTOINCREMENT INDIR_ADDO SIZE_WORD (f-source 15) sconst16)
+ (sequence
+   ()
+   (set prefixreg (add SI Rd (ext SI (trunc HI sconst16))))
+   (set prefix-set 1))
+)
+(dni-c-SI
+ addo-cd "addo.d const"
+ "addo.d [PC+],$Rd,ACR"
+ (+ Rd MODE_AUTOINCREMENT INDIR_ADDO SIZE_DWORD (f-source 15) const32)
+ (sequence
+   ()
+   (set prefixreg (add SI Rd const32))
+   (set prefix-set 1))
+)
+
+;         DIP    []   | 0  0  0  0| 1  m| 0  1  0  1| 1  1| Source    |
+
+(dni-cmt-attr
+ dip-m "dip mem"
+ (MACH-PRE-V32)
+ "dip [${Rs}${inc}]"
+ (+ (f-dest 0) INFIX_DIP SIZE_FIXED Rs)
+ (sequence
+   ((SI tmps))
+   (set tmps (cris-get-mem SI Rs))
+   (set prefixreg tmps)
+   (set prefix-set 1))
+)
+
+;         (DIP    []   | 0  0  0  0| 1  m| 0  1  0  1| 1  1| Source    |    )
+(dni-c-SI-attr
+ dip-c "dip [PC+]"
+ (MACH-PC)
+ "dip [PC+]"
+ (+ (f-dest 0) MODE_AUTOINCREMENT INFIX_DIP SIZE_FIXED (f-source 15) const32)
+ (sequence
+   ()
+   (set prefixreg const32)
+   (set prefix-set 1))
+)
+
+; ADDI    Rs.m,Rd,ACR     [ Rs | 010101mm | Rd ]
+; a.k.a. biap
+(dni-cdt-bwd
+ addi-acr "addi prefix"
+ "${Rs-dfield}.m,${Rd-sfield},ACR"
+ (+ Rd-sfield MODE_REGISTER R_ADDI_ACR Rs-dfield)
+ (.pmacro
+  (BWD)
+  (sequence
+    ()
+    (set prefixreg (add SI Rd-sfield (mul Rs-dfield (.sym BWD -size))))
+    (set prefix-set 1)))
+)
+
+(dni-cdt-bwd-attr
+ biap-pc "biap.m ${Rs-dfield},PC"
+ (MACH-PC)
+ "${Rs-dfield}.m,PC"
+ (+ Rs-dfield MODE_REGISTER R_ADDI_ACR (f-source 15))
+ (.pmacro
+  (BWD)
+  (sequence
+    ()
+    (set prefixreg (add SI (add SI pc 4) (mul Rs-dfield (.sym BWD -size))))
+    (set prefix-set 1)))
+)
+
+; FIDXI    [Rs]            [ 0000 | 11010011 | Rs ]
+(dni-cdt-attr
+ fidxi "fidxi [Rs]"
+ (MACH-V32)
+ "fidxi [$Rs]"
+ (+ (f-dest 0) MODE_AUTOINCREMENT INFIX_FIDXI SIZE_FIXED Rs)
+ (set pc (c-call USI "@cpu@_fidxi_handler" pc Rs))
+)
+
+; FTAGI    [Rs]            [ 0001 | 11010011 | Rs ]
+(dni-cdt-attr
+ ftagi "ftagi [Rs]"
+ (MACH-V32)
+ "fidxi [$Rs]"
+ (+ (f-dest 1) MODE_AUTOINCREMENT INFIX_FTAGI SIZE_FIXED Rs)
+ (set pc (c-call USI "@cpu@_ftagi_handler" pc Rs))
+)
+
+; FIDXD    [Rs]            [ 0000 | 10101011 | Rs ]
+(dni-cdt-attr
+ fidxd "fidxd [Rs]"
+ (MACH-V32)
+ "fidxd [$Rs]"
+ (+ (f-dest 0) MODE_INDIRECT INFIX_FIDXD SIZE_FIXED Rs)
+ (set pc (c-call USI "@cpu@_fidxd_handler" pc Rs))
+)
+
+; FTAGD    [Rs]            [ 0001 | 10101011 | Rs ]
+(dni-cdt-attr
+ ftagd "ftagd [Rs]"
+ (MACH-V32)
+ "ftagd [$Rs]"
+ (+ (f-dest 1) MODE_INDIRECT INFIX_FTAGD SIZE_FIXED Rs)
+ (set pc (c-call USI "@cpu@_ftagd_handler" pc Rs))
+)

diff --git a/cpu/frv.cpu b/cpu/frv.cpu
new file mode 100644 (file)
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--- /dev/null
+++ b/cpu/frv.cpu
@@ -0,0 +1,9799 @@
+; Fujitsu FRV opcode support, for GNU Binutils.  -*- Scheme -*-
+;
+; Copyright 2000, 2001, 2003, 2004, 2007, 2009 Free Software Foundation, Inc.
+;
+; Contributed by Red Hat Inc; developed under contract from Fujitsu.
+;
+; This file is part of the GNU Binutils.
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 3 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, write to the Free Software
+; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+; MA 02110-1301, USA.
+
+(include "simplify.inc")
+
+; define-arch must appear first
+
+(define-arch
+  (name frv) ; name of cpu architecture
+  (comment "Fujitsu FRV")
+  (insn-lsb0? #t)
+  (machs frv fr550 fr500 fr450 fr400 tomcat simple)
+  (isas frv)
+)
+
+(define-isa
+  (name frv)
+  (base-insn-bitsize 32)
+  ; Initial bitnumbers to decode insns by.
+  (decode-assist (24 23 22 21 20 19 18))
+  (liw-insns 1)       ; The frv fetches  up to 1 insns at a time.
+  (parallel-insns 8)  ; The frv executes up to 8 insns at a time.
+)
+
+; Cpu family definitions.
+;
+(define-cpu
+  ; cpu names must be distinct from the architecture name and machine names.
+  ; The "b" suffix stands for "base" and is the convention.
+  ; The "f" suffix stands for "family" and is the convention.
+  (name frvbf)
+  (comment "Fujitsu FRV base family")
+  (endian big)
+  (word-bitsize 32)
+)
+\f
+; Generic FR-V machine. Supports the entire architecture
+(define-mach
+  (name frv)
+  (comment "Generic FRV cpu")
+  (cpu frvbf)
+)
+(define-model
+  (name frv) (comment "Generic FRV model") (attrs)
+  (mach frv)
+
+  (pipeline all "" () ((fetch) (decode) (execute) (writeback)))
+
+  ; `state' is a list of variables for recording model state
+  ; (state)
+
+  (unit u-exec "Execution Unit" ()
+       1 1 ; issue done
+       () ; state
+       () ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+)
+\f
+; FR550 machine
+(define-mach
+  (name fr550)
+  (comment "FR550 cpu")
+  (cpu frvbf)
+)
+(define-model
+  (name fr550) (comment "FR550 model") (attrs)
+  (mach fr550)
+
+  (pipeline all "" () ((fetch) (decode) (execute) (writeback)))
+
+  ; `state' is a list of variables for recording model state
+  (state
+   ; State items
+   ; These are all masks with each bit representing one register.
+   (prev-fr-load      DI) ; Previous use of FR  register was target of a load
+   (prev-fr-complex-1 DI) ; Previous use of FR  register has variable latency
+   (prev-fr-complex-2 DI) ; Previous use of FR  register has variable latency
+   (prev-ccr-complex  DI) ; Previous use of CCR register has variable latency
+   (prev-acc-mmac     DI) ; Previous use of ACC register was a MMAC category
+   (cur-fr-load       DI) ; Current  use of FR  register was target of a load
+   (cur-fr-complex-1  DI) ; Current  use of FR  register has variable latency
+   (cur-fr-complex-2  DI) ; Current  use of FR  register has variable latency
+   (cur-ccr-complex   SI) ; Current  use of CCR register has variable latency
+   (cur-acc-mmac      DI) ; Current  use of ACC register was a MMAC category
+  )
+  ; Basic unit for instructions with no latency penalties
+  (unit u-exec "Execution Unit" ()
+       1 1 ; issue done
+       () ; state
+       () ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Basic integer insn unit
+  (unit u-integer "Integer Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       ((GRk INT -1) (ICCi_1 INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Integer multiplication unit
+  (unit u-imul "Integer Multiplication Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       ((GRdoublek INT -1) (ICCi_1 INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Integer division unit
+  (unit u-idiv "Integer Division Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       ((GRk INT -1) (ICCi_1 INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Branch unit
+  (unit u-branch "Branch Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)
+        (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs
+       ((pc)) ; outputs
+       () ; profile action (default)
+       )
+  ; Trap unit
+  (unit u-trap "Trap Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)
+        (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Condition code check unit
+  (unit u-check "Check Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((ICCi_3 INT -1) (FCCi_3 INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Float Arithmetic unit
+  (unit u-float-arith "Float Arithmetic unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRi INT -1) (FRj INT -1) ; inputs
+        (FRdoublei INT -1) (FRdoublej INT -1)) ; inputs
+       ((FRk INT -1) (FRdoublek INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Float Dual Arithmetic unit
+  (unit u-float-dual-arith "Float Arithmetic unit" ()
+       ; This unit has a 2 cycle penalty -- see table 14-14 in the fr550 LSI
+       1 3 ; issue done
+       () ; state
+       ((FRi INT -1) (FRj INT -1) ; inputs
+        (FRdoublei INT -1) (FRdoublej INT -1)) ; inputs
+       ((FRk INT -1) (FRdoublek INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Float Div unit
+  (unit u-float-div "Float Div unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRi INT -1) (FRj INT -1)) ; inputs
+       ((FRk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Float Square Root unit
+  (unit u-float-sqrt "Float Square Root unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRj INT -1) (FRdoublej INT -1)) ; inputs
+       ((FRk INT -1) (FRdoublek INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Float Compare unit
+  (unit u-float-compare "Float Compare unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRi INT -1) (FRj INT -1)
+        (FRdoublei INT -1) (FRdoublej INT -1)) ; inputs
+       ((FCCi_2 INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Dual Float Compare unit
+  (unit u-float-dual-compare "Float Dual Compare unit" ()
+       ; This unit has a 2 cycle penalty -- see table 14-14 in the fr550 LSI
+       1 3 ; issue done
+       () ; state
+       ((FRi INT -1) (FRj INT -1)) ; inputs
+       ((FCCi_2 INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; FR Move to GR unit
+  (unit u-fr2gr "FR Move to GR Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRintk INT -1)) ; inputs
+       ((GRj INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; GR Move to FR unit
+  (unit u-gr2fr "GR Move to FR Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRj INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; SPR Move to GR unit
+  (unit u-spr2gr "SPR Move to GR Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((spr INT -1)) ; inputs
+       ((GRj INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; GR Move to SPR unit
+  (unit u-gr2spr "GR Move to SPR Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRj INT -1)) ; inputs
+       ((spr INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; GR set half unit
+  (unit u-set-hilo "GR Set Half" ()
+       1 1 ; issue done
+       () ; state
+       () ; inputs
+       ((GRkhi INT -1) (GRklo INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; GR load unit
+  (unit u-gr-load "GR Load Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       ((GRk INT -1) (GRdoublek INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; GR store unit
+  (unit u-gr-store "GR Store Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1) (GRk INT -1) (GRdoublek INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; FR load unit
+  (unit u-fr-load "FR Load Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       ((FRintk INT -1) (FRdoublek INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; FR store unit
+  (unit u-fr-store "FR Store Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Swap unit
+  (unit u-swap "Swap Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       ((GRk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; FR Move to FR unit
+  (unit u-fr2fr "FR Move to FR Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRi INT -1)) ; inputs
+       ((FRk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Clrgr unit
+  (unit u-clrgr "Clrgr Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRk INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Clrfr unit
+  (unit u-clrfr "Clrfr Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRk INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Insn cache invalidate unit
+  (unit u-ici "Insn cache invalidate unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Data cache invalidate unit
+  (unit u-dci "Data cache invalidate unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Data cache flush unit
+  (unit u-dcf "Data cache flush unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Insn cache preload unit
+  (unit u-icpl "Insn cache preload unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Data cache preload unit
+  (unit u-dcpl "Data cache preload unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Insn cache unlock unit
+  (unit u-icul "Insn cache unlock unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Data cache unlock unit
+  (unit u-dcul "Data cache unlock unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; commit unit
+  (unit u-commit "Commit Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRk INT -1) (FRk INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Float Conversion unit
+  (unit u-float-convert "Float Conversion unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRj INT -1) (FRintj INT -1) (FRdoublej INT -1)) ; inputs
+       ((FRk INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Media units
+  (unit u-media "Media unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1) (FRintj INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-quad "Media-quad unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRintieven INT -1) (FRintjeven INT -1)) ; inputs
+       ((FRintkeven INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-dual-expand "Media Dual Expand unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1)) ; inputs
+       ((FRintkeven INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-3-dual "Media-3-dual unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-3-acc "Media unit for M-3 using ACC" ()
+       1 1 ; issue done
+       () ; state
+       ((FRintj INT -1) (ACC40Si INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-3-acc-dual "Media-3-acc-dual unit" ()
+       1 1 ; issue done
+       () ; state
+       ((ACC40Si INT -1)) ; inputs
+       ((FRintkeven INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-3-wtacc "Media-3-wtacc unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1) (ACC40Sk INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-3-mclracc "Media-3-mclracc unit" ()
+       1 1 ; issue done
+       () ; state
+       () ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-set "Media set" ()
+       1 1 ; issue done
+       () ; state
+       () ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-4 "Media-4 unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1) (FRintj INT -1)) ; inputs
+       ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-4-acc "Media-4-acc unit" ()
+       1 1 ; issue done
+       () ; state
+       ((ACC40Si INT -1)) ; inputs
+       ((ACC40Sk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-4-acc-dual "Media-4-acc-dual unit" ()
+       1 1 ; issue done
+       () ; state
+       ((ACC40Si INT -1)) ; inputs
+       ((ACC40Sk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-4-add-sub "Media-4-add-sub unit" ()
+       1 1 ; issue done
+       () ; state
+       ((ACC40Si INT -1)) ; inputs
+       ((ACC40Sk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-4-add-sub-dual "Media-4-add-sub-dual unit" ()
+       1 1 ; issue done
+       () ; state
+       ((ACC40Si INT -1)) ; inputs
+       ((ACC40Sk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-4-quad "Media-4-quad unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRintieven INT -1) (FRintjeven INT -1)) ; inputs
+       ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+)
+
+; FR500 machine.
+(define-mach
+  (name fr500)
+  (comment "FR500 cpu")
+  (cpu frvbf)
+)
+(define-model
+  (name fr500) (comment "FR500 model") (attrs)
+  (mach fr500)
+
+  (pipeline all "" () ((fetch) (decode) (execute) (writeback)))
+
+  ; `state' is a list of variables for recording model state
+  (state
+   ; State items
+   ; These are all masks with each bit representing one register.
+   (prev-fpop       DI) ; Previous use of FR register was floating point insn
+   (prev-media      DI) ; Previous use of FR register was a media insn
+   (prev-cc-complex DI) ; Previous use of ICC register was not simple
+   (cur-fpop        DI) ; Current use of FR register was floating point insn
+   (cur-media       DI) ; Current use of FR register was a media insn
+   (cur-cc-complex  DI) ; Current use of ICC register was not simple
+  )
+  ; Basic unit for instructions with no latency penalties
+  (unit u-exec "Execution Unit" ()
+       1 1 ; issue done
+       () ; state
+       () ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Basic integer insn unit
+  (unit u-integer "Integer Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       ((GRk INT -1) (ICCi_1 INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Integer multiplication unit
+  (unit u-imul "Integer Multiplication Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       ((GRdoublek INT -1) (ICCi_1 INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Integer division unit
+  (unit u-idiv "Integer Division Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       ((GRk INT -1) (ICCi_1 INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Branch unit
+  (unit u-branch "Branch Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)
+        (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs
+       ((pc)) ; outputs
+       () ; profile action (default)
+       )
+  ; Trap unit
+  (unit u-trap "Trap Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)
+        (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Condition code check unit
+  (unit u-check "Check Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((ICCi_3 INT -1) (FCCi_3 INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Clrgr unit
+  (unit u-clrgr "Clrgr Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRk INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Clrfr unit
+  (unit u-clrfr "Clrfr Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRk INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; GR set half unit
+  (unit u-set-hilo "GR Set Half" ()
+       1 1 ; issue done
+       () ; state
+       () ; inputs
+       ((GRkhi INT -1) (GRklo INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; GR load unit -- TODO doesn't handle quad
+  (unit u-gr-load "GR Load Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       ((GRk INT -1) (GRdoublek INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; GR store unit -- TODO doesn't handle quad
+  (unit u-gr-store "GR Store Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1) (GRk INT -1) (GRdoublek INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; GR recovering store unit -- TODO doesn't handle quad
+  (unit u-gr-r-store "GR Recovering Store Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1) (GRk INT -1) (GRdoublek INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; FR load unit -- TODO doesn't handle quad
+  (unit u-fr-load "FR Load Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       ((FRintk INT -1) (FRdoublek INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; FR store unit -- TODO doesn't handle quad
+  (unit u-fr-store "FR Store Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; FR recovering store unit -- TODO doesn't handle quad
+  (unit u-fr-r-store "FR Recovering Store Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Swap unit
+  (unit u-swap "Swap Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       ((GRk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; FR Move to FR unit
+  (unit u-fr2fr "FR Move to FR Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRi INT -1)) ; inputs
+       ((FRk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; FR Move to GR unit
+  (unit u-fr2gr "FR Move to GR Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRintk INT -1)) ; inputs
+       ((GRj INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; SPR Move to GR unit
+  (unit u-spr2gr "SPR Move to GR Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((spr INT -1)) ; inputs
+       ((GRj INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; GR Move to FR unit
+  (unit u-gr2fr "GR Move to FR Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRj INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; GR Move to SPR unit
+  (unit u-gr2spr "GR Move to SPR Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRj INT -1)) ; inputs
+       ((spr INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Float Arithmetic unit
+  (unit u-float-arith "Float Arithmetic unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRi INT -1) (FRj INT -1) ; inputs
+        (FRdoublei INT -1) (FRdoublej INT -1)) ; inputs
+       ((FRk INT -1) (FRdoublek INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Float Dual Arithmetic unit
+  (unit u-float-dual-arith "Float Arithmetic unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRi INT -1) (FRj INT -1) ; inputs
+        (FRdoublei INT -1) (FRdoublej INT -1)) ; inputs
+       ((FRk INT -1) (FRdoublek INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Float Div unit
+  (unit u-float-div "Float Div unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRi INT -1) (FRj INT -1)) ; inputs
+       ((FRk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Float Square Root unit
+  (unit u-float-sqrt "Float Square Root unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRj INT -1) (FRdoublej INT -1)) ; inputs
+       ((FRk INT -1) (FRdoublek INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Float Dual Square Root unit
+  (unit u-float-dual-sqrt "Float Dual Square Root unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRj INT -1)) ; inputs
+       ((FRk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Float Compare unit
+  (unit u-float-compare "Float Compare unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRi INT -1) (FRj INT -1)
+        (FRdoublei INT -1) (FRdoublej INT -1)) ; inputs
+       ((FCCi_2 INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Dual Float Compare unit
+  (unit u-float-dual-compare "Float Dual Compare unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRi INT -1) (FRj INT -1)) ; inputs
+       ((FCCi_2 INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Float Conversion unit
+  (unit u-float-convert "Float Conversion unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRj INT -1) (FRintj INT -1) (FRdoublej INT -1)) ; inputs
+       ((FRk INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Dual Float Conversion unit
+  (unit u-float-dual-convert "Float Dual Conversion unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRj INT -1) (FRintj INT -1)) ; inputs
+       ((FRk INT -1) (FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Media unit
+  (unit u-media "Media unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1) (FRintj INT -1) (ACC40Si INT -1) (ACCGi INT -1)) ; inputs
+       ((FRintk INT -1) (ACC40Sk INT -1) (ACC40Uk INT -1) (ACCGk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Media Quad Arithmetic unit
+  (unit u-media-quad-arith "Media Quad Arithmetic unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1) (FRintj INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Media Dual Multiplication unit
+  (unit u-media-dual-mul "Media Dual Multiplication unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1) (FRintj INT -1)) ; inputs
+       ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Media Quad Multiplication unit
+  (unit u-media-quad-mul "Media Quad Multiplication unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1) (FRintj INT -1)) ; inputs
+       ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Media Quad Complex unit
+  (unit u-media-quad-complex "Media Quad Complex unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1) (FRintj INT -1)) ; inputs
+       ((ACC40Sk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Media Dual Expand unit
+  (unit u-media-dual-expand "Media Dual Expand unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Media Dual Unpack unit
+  (unit u-media-dual-unpack "Media Dual Unpack unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Media Dual byte to half unit
+  (unit u-media-dual-btoh "Media Byte to byte" ()
+       1 1 ; issue done
+       () ; state
+       ((FRintj INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Media Dual half to byte unit
+  (unit u-media-dual-htob "Media Half to byte" ()
+       1 1 ; issue done
+       () ; state
+       ((FRintj INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Media Dual byte to half unit extended
+  (unit u-media-dual-btohe "Media Byte to byte extended" ()
+       1 1 ; issue done
+       () ; state
+       ((FRintj INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Barrier unit
+  (unit u-barrier "Barrier unit" ()
+       1 1 ; issue done
+       () ; state
+       () ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Memory Barrier unit
+  (unit u-membar "Memory Barrier unit" ()
+       1 1 ; issue done
+       () ; state
+       () ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Insn cache invalidate unit
+  (unit u-ici "Insn cache invalidate unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Data cache invalidate unit
+  (unit u-dci "Data cache invalidate unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Data cache flush unit
+  (unit u-dcf "Data cache flush unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Insn cache preload unit
+  (unit u-icpl "Insn cache preload unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Data cache preload unit
+  (unit u-dcpl "Data cache preload unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Insn cache unlock unit
+  (unit u-icul "Insn cache unlock unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Data cache unlock unit
+  (unit u-dcul "Data cache unlock unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; commit unit
+  (unit u-commit "Commit Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRk INT -1) (FRk INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+)
+\f
+; Tomcat machine. Early version of fr500 machine
+(define-mach
+  (name tomcat)
+  (comment "Tomcat -- early version of fr500")
+  (cpu frvbf)
+)
+(define-model
+  (name tomcat) (comment "Tomcat model") (attrs)
+  (mach tomcat)
+
+  (pipeline all "" () ((fetch) (decode) (execute) (writeback)))
+
+  ; `state' is a list of variables for recording model state
+  ; (state)
+
+  (unit u-exec "Execution Unit" ()
+       1 1 ; issue done
+       () ; state
+       () ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+)
+\f
+; FR400 machine
+(define-mach
+  (name fr400)
+  (comment "FR400 cpu")
+  (cpu frvbf)
+)
+(define-model
+  (name fr400) (comment "FR400 model") (attrs)
+  (mach fr400)
+  (pipeline all "" () ((fetch) (decode) (execute) (writeback)))
+  ; `state' is a list of variables for recording model state
+  (state
+   ; State items
+   ; These are all masks with each bit representing one register.
+   (prev-fp-load    DI) ; Previous use of FR  register was floating point load
+   (prev-fr-p4      DI) ; Previous use of FR  register was media unit 4
+   (prev-fr-p6      DI) ; Previous use of FR  register was media unit 6
+   (prev-acc-p2     DI) ; Previous use of ACC register was media unit 2
+   (prev-acc-p4     DI) ; Previous use of ACC register was media unit 4
+   (cur-fp-load     DI) ; Current  use of FR  register is  floating point load
+   (cur-fr-p4       DI) ; Current  use of FR  register is  media unit 4
+   (cur-fr-p6       DI) ; Current  use of FR  register is  media unit 6
+   (cur-acc-p2      DI) ; Current  use of ACC register is  media unit 2
+   (cur-acc-p4      DI) ; Current  use of ACC register is  media unit 4
+  )
+  (unit u-exec "Execution Unit" ()
+       1 1 ; issue done
+       () ; state
+       () ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Basic integer insn unit
+  (unit u-integer "Integer Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       ((GRk INT -1) (ICCi_1 INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Integer multiplication unit
+  (unit u-imul "Integer Multiplication Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       ((GRdoublek INT -1) (ICCi_1 INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Integer division unit
+  (unit u-idiv "Integer Division Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       ((GRk INT -1) (ICCi_1 INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Branch unit
+  (unit u-branch "Branch Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)
+        (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs
+       ((pc)) ; outputs
+       () ; profile action (default)
+       )
+  ; Trap unit
+  (unit u-trap "Trap Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)
+        (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Condition code check unit
+  (unit u-check "Check Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((ICCi_3 INT -1) (FCCi_3 INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; GR set half unit
+  (unit u-set-hilo "GR Set Half" ()
+       1 1 ; issue done
+       () ; state
+       () ; inputs
+       ((GRkhi INT -1) (GRklo INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; GR load unit -- TODO doesn't handle quad
+  (unit u-gr-load "GR Load Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       ((GRk INT -1) (GRdoublek INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; GR store unit -- TODO doesn't handle quad
+  (unit u-gr-store "GR Store Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1) (GRk INT -1) (GRdoublek INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; FR load unit -- TODO doesn't handle quad
+  (unit u-fr-load "FR Load Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       ((FRintk INT -1) (FRdoublek INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; FR store unit -- TODO doesn't handle quad
+  (unit u-fr-store "FR Store Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Swap unit
+  (unit u-swap "Swap Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       ((GRk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; FR Move to GR unit
+  (unit u-fr2gr "FR Move to GR Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRintk INT -1)) ; inputs
+       ((GRj INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; SPR Move to GR unit
+  (unit u-spr2gr "SPR Move to GR Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((spr INT -1)) ; inputs
+       ((GRj INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; GR Move to FR unit
+  (unit u-gr2fr "GR Move to FR Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRj INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; GR Move to SPR unit
+  (unit u-gr2spr "GR Move to SPR Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRj INT -1)) ; inputs
+       ((spr INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Media unit M1 -- see table 13-8 in the fr400 LSI
+  (unit u-media-1 "Media-1 unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1) (FRintj INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-1-quad "Media-1-quad unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1) (FRintj INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-hilo "Media-hilo unit -- a variation of the Media-1 unit" ()
+       1 1 ; issue done
+       () ; state
+       () ; inputs
+       ((FRkhi INT -1) (FRklo INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Media unit M2 -- see table 13-8 in the fr400 LSI
+  (unit u-media-2 "Media-2 unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1) (FRintj INT -1)) ; inputs
+       ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-2-quad "Media-2-quad unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1) (FRintj INT -1)) ; inputs
+       ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-2-acc "Media-2-acc unit" ()
+       1 1 ; issue done
+       () ; state
+       ((ACC40Si INT -1)) ; inputs
+       ((ACC40Sk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-2-acc-dual "Media-2-acc-dual unit" ()
+       1 1 ; issue done
+       () ; state
+       ((ACC40Si INT -1)) ; inputs
+       ((ACC40Sk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-2-add-sub "Media-2-add-sub unit" ()
+       1 1 ; issue done
+       () ; state
+       ((ACC40Si INT -1)) ; inputs
+       ((ACC40Sk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-2-add-sub-dual "Media-2-add-sub-dual unit" ()
+       1 1 ; issue done
+       () ; state
+       ((ACC40Si INT -1)) ; inputs
+       ((ACC40Sk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Media unit M3 -- see table 13-8 in the fr400 LSI
+  (unit u-media-3 "Media-3 unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1) (FRintj INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-3-dual "Media-3-dual unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-3-quad "Media-3-quad unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1) (FRintj INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Media unit M4 -- see table 13-8 in the fr400 LSI
+  (unit u-media-4 "Media-4 unit" ()
+       1 1 ; issue done
+       () ; state
+       ((ACC40Si INT -1) (FRintj INT -1)) ; inputs
+       ((ACC40Sk INT -1) (FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-4-accg "Media-4-accg unit" ()
+       1 1 ; issue done
+       () ; state
+       ((ACCGi INT -1) (FRinti INT -1)) ; inputs
+       ((ACCGk INT -1) (FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-4-acc-dual "Media-4-acc-dual unit" ()
+       1 1 ; issue done
+       () ; state
+       ((ACC40Si INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Media unit M6 -- see table 13-8 in the fr400 LSI
+  (unit u-media-6 "Media-6 unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Media unit M7 -- see table 13-8 in the fr400 LSI
+  (unit u-media-7 "Media-1 unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1) (FRintj INT -1)) ; inputs
+       ((FCCk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Media Dual Expand unit
+  (unit u-media-dual-expand "Media Dual Expand unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Media Dual half to byte unit
+  (unit u-media-dual-htob "Media Half to byte" ()
+       1 1 ; issue done
+       () ; state
+       ((FRintj INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Barrier unit
+  (unit u-barrier "Barrier unit" ()
+       1 1 ; issue done
+       () ; state
+       () ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Memory Barrier unit
+  (unit u-membar "Memory Barrier unit" ()
+       1 1 ; issue done
+       () ; state
+       () ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Insn cache invalidate unit
+  (unit u-ici "Insn cache invalidate unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Data cache invalidate unit
+  (unit u-dci "Data cache invalidate unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Data cache flush unit
+  (unit u-dcf "Data cache flush unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Insn cache preload unit
+  (unit u-icpl "Insn cache preload unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Data cache preload unit
+  (unit u-dcpl "Data cache preload unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Insn cache unlock unit
+  (unit u-icul "Insn cache unlock unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Data cache unlock unit
+  (unit u-dcul "Data cache unlock unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+)
+\f
+; FR450 machine
+(define-mach
+  (name fr450)
+  (comment "FR450 cpu")
+  (cpu frvbf)
+)
+(define-model
+  (name fr450) (comment "FR450 model") (attrs)
+  (mach fr450)
+  (pipeline all "" () ((fetch) (decode) (execute) (writeback)))
+  ; `state' is a list of variables for recording model state
+  (state
+   ; State items
+   ; These are all masks with each bit representing one register.
+   (prev-fp-load    DI) ; Previous use of FR  register was floating point load
+   (prev-fr-p4      DI) ; Previous use of FR  register was media unit 4
+   (prev-fr-p6      DI) ; Previous use of FR  register was media unit 6
+   (prev-acc-p2     DI) ; Previous use of ACC register was media unit 2
+   (prev-acc-p4     DI) ; Previous use of ACC register was media unit 4
+   (cur-fp-load     DI) ; Current  use of FR  register is  floating point load
+   (cur-fr-p4       DI) ; Current  use of FR  register is  media unit 4
+   (cur-fr-p6       DI) ; Current  use of FR  register is  media unit 6
+   (cur-acc-p2      DI) ; Current  use of ACC register is  media unit 2
+   (cur-acc-p4      DI) ; Current  use of ACC register is  media unit 4
+  )
+  (unit u-exec "Execution Unit" ()
+       1 1 ; issue done
+       () ; state
+       () ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Basic integer insn unit
+  (unit u-integer "Integer Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       ((GRk INT -1) (ICCi_1 INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Integer multiplication unit
+  (unit u-imul "Integer Multiplication Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       ((GRdoublek INT -1) (ICCi_1 INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Integer division unit
+  (unit u-idiv "Integer Division Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       ((GRk INT -1) (ICCi_1 INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Branch unit
+  (unit u-branch "Branch Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)
+        (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs
+       ((pc)) ; outputs
+       () ; profile action (default)
+       )
+  ; Trap unit
+  (unit u-trap "Trap Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)
+        (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Condition code check unit
+  (unit u-check "Check Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((ICCi_3 INT -1) (FCCi_3 INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; GR set half unit
+  (unit u-set-hilo "GR Set Half" ()
+       1 1 ; issue done
+       () ; state
+       () ; inputs
+       ((GRkhi INT -1) (GRklo INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; GR load unit -- TODO doesn't handle quad
+  (unit u-gr-load "GR Load Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       ((GRk INT -1) (GRdoublek INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; GR store unit -- TODO doesn't handle quad
+  (unit u-gr-store "GR Store Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1) (GRk INT -1) (GRdoublek INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; FR load unit -- TODO doesn't handle quad
+  (unit u-fr-load "FR Load Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       ((FRintk INT -1) (FRdoublek INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; FR store unit -- TODO doesn't handle quad
+  (unit u-fr-store "FR Store Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Swap unit
+  (unit u-swap "Swap Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       ((GRk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; FR Move to GR unit
+  (unit u-fr2gr "FR Move to GR Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRintk INT -1)) ; inputs
+       ((GRj INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; SPR Move to GR unit
+  (unit u-spr2gr "SPR Move to GR Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((spr INT -1)) ; inputs
+       ((GRj INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; GR Move to FR unit
+  (unit u-gr2fr "GR Move to FR Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRj INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; GR Move to SPR unit
+  (unit u-gr2spr "GR Move to SPR Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRj INT -1)) ; inputs
+       ((spr INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Media unit M1 -- see table 14-8 in the fr450 LSI
+  (unit u-media-1 "Media-1 unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1) (FRintj INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-1-quad "Media-1-quad unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1) (FRintj INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-hilo "Media-hilo unit -- a variation of the Media-1 unit" ()
+       1 1 ; issue done
+       () ; state
+       () ; inputs
+       ((FRkhi INT -1) (FRklo INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Media unit M2 -- see table 14-8 in the fr450 LSI
+  (unit u-media-2 "Media-2 unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1) (FRintj INT -1)) ; inputs
+       ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-2-quad "Media-2-quad unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1) (FRintj INT -1)) ; inputs
+       ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-2-acc "Media-2-acc unit" ()
+       1 1 ; issue done
+       () ; state
+       ((ACC40Si INT -1)) ; inputs
+       ((ACC40Sk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-2-acc-dual "Media-2-acc-dual unit" ()
+       1 1 ; issue done
+       () ; state
+       ((ACC40Si INT -1)) ; inputs
+       ((ACC40Sk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-2-add-sub "Media-2-add-sub unit" ()
+       1 1 ; issue done
+       () ; state
+       ((ACC40Si INT -1)) ; inputs
+       ((ACC40Sk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-2-add-sub-dual "Media-2-add-sub-dual unit" ()
+       1 1 ; issue done
+       () ; state
+       ((ACC40Si INT -1)) ; inputs
+       ((ACC40Sk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Media unit M3 -- see table 14-8 in the fr450 LSI
+  (unit u-media-3 "Media-3 unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1) (FRintj INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-3-dual "Media-3-dual unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-3-quad "Media-3-quad unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1) (FRintj INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Media unit M4 -- see table 14-8 in the fr450 LSI
+  (unit u-media-4 "Media-4 unit" ()
+       1 1 ; issue done
+       () ; state
+       ((ACC40Si INT -1) (FRintj INT -1)) ; inputs
+       ((ACC40Sk INT -1) (FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-4-accg "Media-4-accg unit" ()
+       1 1 ; issue done
+       () ; state
+       ((ACCGi INT -1) (FRinti INT -1)) ; inputs
+       ((ACCGk INT -1) (FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-4-acc-dual "Media-4-acc-dual unit" ()
+       1 1 ; issue done
+       () ; state
+       ((ACC40Si INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-media-4-mclracca "Media-4 unit for MCLRACC with #A=1" ()
+       1 1 ; issue done
+       () ; state
+       () ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Media unit M6 -- see table 14-8 in the fr450 LSI
+  (unit u-media-6 "Media-6 unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Media unit M7 -- see table 14-8 in the fr450 LSI
+  (unit u-media-7 "Media-1 unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1) (FRintj INT -1)) ; inputs
+       ((FCCk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Media Dual Expand unit
+  (unit u-media-dual-expand "Media Dual Expand unit" ()
+       1 1 ; issue done
+       () ; state
+       ((FRinti INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Media Dual half to byte unit
+  (unit u-media-dual-htob "Media Half to byte" ()
+       1 1 ; issue done
+       () ; state
+       ((FRintj INT -1)) ; inputs
+       ((FRintk INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  ; Barrier unit
+  (unit u-barrier "Barrier unit" ()
+       1 1 ; issue done
+       () ; state
+       () ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Memory Barrier unit
+  (unit u-membar "Memory Barrier unit" ()
+       1 1 ; issue done
+       () ; state
+       () ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Insn cache invalidate unit
+  (unit u-ici "Insn cache invalidate unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Data cache invalidate unit
+  (unit u-dci "Data cache invalidate unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Data cache flush unit
+  (unit u-dcf "Data cache flush unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Insn cache preload unit
+  (unit u-icpl "Insn cache preload unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Data cache preload unit
+  (unit u-dcpl "Data cache preload unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Insn cache unlock unit
+  (unit u-icul "Insn cache unlock unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  ; Data cache unlock unit
+  (unit u-dcul "Data cache unlock unit" ()
+       1 1 ; issue done
+       () ; state
+       ((GRi INT -1) (GRj INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+)
+\f
+; Simple machine - single issue integer machine
+(define-mach
+  (name simple)
+  (comment "Simple single issue integer cpu")
+  (cpu frvbf)
+)
+(define-model
+  (name simple) (comment "Simple model") (attrs)
+  (mach simple)
+  (pipeline all "" () ((fetch) (decode) (execute) (writeback)))
+  ; `state' is a list of variables for recording model state
+  (state)
+  (unit u-exec "Execution Unit" ()
+       1 1 ; issue done
+       () ; state
+       () ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+)
+\f
+; The instruction fetch/execute cycle.
+;
+; This is how to fetch and decode an instruction.
+; Leave it out for now
+
+; (define-extract (const SI 0))
+
+; This is how to execute a decoded instruction.
+; Leave it out for now
+
+; (define-execute (const SI 0))
+\f
+; An attribute to describe which unit an insn runs in.
+(define-attr
+  (for insn)
+  (type enum)
+  (name UNIT)
+  (comment "parallel execution pipeline selection")
+  ; The order of declaration is significant. 
+  ; See the *_unit_mapping tables in frv.opc
+  ; Keep variations on the same unit together.
+  ; Keep the '01' variant immediately after the '1' variant in each unit.
+  ; Keep the 'ALL' variations immediately after the last numbered variant in each unit.
+  (values NIL
+         I0 I1 I01 I2 I3 IALL
+         FM0 FM1 FM01 FM2 FM3 FMALL FMLOW
+         B0 B1 B01
+         C
+         MULT-DIV ; multiply/division slotted differently on different machines
+         IACC     ; iacc multiply     slotted differently on different machines
+         LOAD     ; loads             slotted differently on different machines
+         STORE    ; store             slotted differently on different machines
+         SCAN     ; scan, scani       slotted differently on different machines
+         DCPL     ; dcpl              slotted differently on different machines
+         MDUALACC ; media dual acc    slotted differently on different machines
+         MDCUTSSI ; mdcutssi insn     slotted differently on different machines
+         MCLRACC-1; mclracc A==1      slotted differently on different machines
+         NUM_UNITS
+  )
+)
+; Attributes to describe major categories of insns
+(define-attr
+  (for insn)
+  (type enum)
+  (name FR400-MAJOR)
+  (comment "fr400 major insn categories")
+  ; The order of declaration is significant. Keep variations on the same major
+  ; together.
+  (values NONE
+         I-1 I-2 I-3 I-4 I-5
+         B-1 B-2 B-3 B-4 B-5 B-6
+         C-1 C-2
+         M-1 M-2
+  )
+)
+(define-attr
+  (for insn)
+  (type enum)
+  (name FR450-MAJOR)
+  (comment "fr450 major insn categories")
+  ; The order of declaration is significant. Keep variations on the same major
+  ; together.
+  (values NONE
+         I-1 I-2 I-3 I-4 I-5
+         B-1 B-2 B-3 B-4 B-5 B-6
+         C-1 C-2
+         M-1 M-2 M-3 M-4 M-5 M-6
+  )
+)
+(define-attr
+  (for insn)
+  (type enum)
+  (name FR500-MAJOR)
+  (comment "fr500 major insn categories")
+  ; The order of declaration is significant. Keep variations on the same major
+  ; together.
+  (values NONE
+         I-1 I-2 I-3 I-4 I-5 I-6
+         B-1 B-2 B-3 B-4 B-5 B-6
+         C-1 C-2
+         F-1 F-2 F-3 F-4 F-5 F-6 F-7 F-8
+         M-1 M-2 M-3 M-4 M-5 M-6 M-7 M-8
+  )
+)
+(define-attr
+  (for insn)
+  (type enum)
+  (name FR550-MAJOR)
+  (comment "fr550 major insn categories")
+  ; The order of declaration is significant. Keep variations on the same major
+  ; together.
+  (values NONE
+         I-1 I-2 I-3 I-4 I-5 I-6 I-7 I-8
+         B-1 B-2 B-3 B-4 B-5 B-6
+         C-1 C-2
+         F-1 F-2 F-3 F-4
+         M-1 M-2 M-3 M-4 M-5
+  )
+)
+; Privileged insn
+(define-attr
+  (for insn)
+  (type boolean)
+  (name PRIVILEGED)
+  (comment "insn only allowed in supervisor mode")
+)
+; Non-Excepting insn
+(define-attr
+  (for insn)
+  (type boolean)
+  (name NON-EXCEPTING)
+  (comment "non-excepting insn")
+)
+; Conditional insn
+(define-attr
+  (for insn)
+  (type boolean)
+  (name CONDITIONAL)
+  (comment "conditional insn")
+)
+; insn accesses FR registers
+(define-attr
+  (for insn)
+  (type boolean)
+  (name FR-ACCESS)
+  (comment "insn accesses FR registers")
+)
+; insn preserves MSR.OVF
+(define-attr
+  (for insn)
+  (type boolean)
+  (name PRESERVE-OVF)
+  (comment "Preserve value of MSR.OVF")
+)
+; "Audio" instruction provided by the fr405 but not the original fr400 core.
+(define-attr
+  (for insn)
+  (type boolean)
+  (name AUDIO)
+  (comment "Audio instruction added with FR405")
+)
+; null attribute -- used as a place holder for where an attribue is required.
+(define-attr
+  (for insn)
+  (type boolean)
+  (name NA)
+  (comment "placeholder attribute")
+  (attrs META) ; do not define in any generated file for now
+)
+
+; IDOC attribute for instruction documentation.
+
+(define-attr
+  (for insn)
+  (type enum)
+  (name IDOC)
+  (comment "insn kind for documentation")
+  (attrs META)
+  (values
+   (MEM - () "Memory")
+   (ALU - () "ALU")
+   (FPU - () "FPU")
+   (BR - () "Branch")
+   (PRIV - () "Priviledged")
+   (MISC - () "Miscellaneous")
+  )
+)
+\f
+; Instruction fields.
+;
+; Attributes:
+; PCREL-ADDR: pc relative value (for reloc and disassembly purposes)
+; ABS-ADDR: absolute address (for reloc and disassembly purposes?)
+; RESERVED: bits are not used to decode insn, must be all 0
+(dnf f-pack      "packing bit"                  () 31  1)
+(dnf f-op        "primary opcode"               () 24  7)
+(dnf f-ope1      "extended opcode"              () 11  6)
+(dnf f-ope2      "extended opcode"              ()  9  4)
+(dnf f-ope3      "extended opcode"              () 15  3)
+(dnf f-ope4      "extended opcode"              ()  7  2)
+
+(dnf f-GRi       "source register 1"            () 17  6)
+(dnf f-GRj       "source register 2"            ()  5  6)
+(dnf f-GRk       "destination register"         () 30  6)
+
+(dnf f-FRi       "source register 1"            () 17  6)
+(dnf f-FRj       "source register 2"            ()  5  6)
+(dnf f-FRk       "destination register"         () 30  6)
+
+(dnf f-CPRi      "source register 1"            () 17  6)
+(dnf f-CPRj      "source register 2"            ()  5  6)
+(dnf f-CPRk      "destination register"         () 30  6)
+
+(dnf f-ACCGi     "source register"              () 17  6)
+(dnf f-ACCGk     "destination register"         () 30  6)
+
+(dnf f-ACC40Si   "40 bit signed accumulator"    () 17  6)
+(dnf f-ACC40Ui   "40 bit unsigned accumulator"  () 17  6)
+(dnf f-ACC40Sk   "40 bit accumulator"           () 30  6)
+(dnf f-ACC40Uk   "40 bit accumulator"           () 30  6)
+
+(dnf f-CRi       "source      register"         () 14  3)
+(dnf f-CRj       "source      register"         ()  2  3)
+(dnf f-CRk       "destination register"         () 27  3)
+(dnf f-CCi       "condition   register"         () 11  3)
+
+(df  f-CRj_int   "target cr for ck insns"       () 26  2 UINT
+     ((value pc) (sub WI value 4))
+     ((value pc) (add WI value 4))
+)
+(dnf f-CRj_float "target cr for fck insns"      () 26  2)
+
+(dnf f-ICCi_1    "condition register"           () 11  2)
+(dnf f-ICCi_2    "condition register"           () 26  2)
+(dnf f-ICCi_3    "condition register"           ()  1  2)
+(dnf f-FCCi_1    "condition register"           () 11  2)
+(dnf f-FCCi_2    "condition register"           () 26  2)
+(dnf f-FCCi_3    "condition register"           ()  1  2)
+(dnf f-FCCk      "condition register"           () 26  2)
+(dnf f-eir       "exception insn register"      () 17  6)
+
+(df  f-s10       "10 bit sign extended"         ()  9 10  INT #f #f)
+(df  f-s12       "12 bit sign extended"         () 11 12  INT #f #f)
+(df  f-d12       "12 bit sign extended"         () 11 12  INT #f #f)
+(df  f-u16       "16 bit unsigned"              () 15 16 UINT #f #f)
+(df  f-s16       "16 bit sign extended"         () 15 16  INT #f #f)
+(df  f-s6        "6  bit   signed"              ()  5  6  INT #f #f)
+(df  f-s6_1      "6  bit   signed"              () 11  6  INT #f #f)
+(df  f-u6        "6  bit unsigned"              ()  5  6 UINT #f #f)
+(df  f-s5        "5  bit   signed"              ()  4  5  INT #f #f)
+
+(df  f-u12-h "upper 6 bits of u12"  () 17 6  INT #f #f)
+(df  f-u12-l "lower 6 bits of u12"  ()  5 6 UINT #f #f)
+(dnmf f-u12   "12 bit signed immediate" () INT
+      (f-u12-h f-u12-l)
+      (sequence () ; insert
+               (set (ifield f-u12-h) (sra SI (ifield f-u12) 6))
+               (set (ifield f-u12-l) (and (ifield f-u12) #x3f))
+               )
+      (sequence () ; extract
+               (set (ifield f-u12) (or (sll (ifield f-u12-h) 6)
+                                       (ifield f-u12-l)))
+               )
+)
+
+(dnf f-int-cc    "integer  branch conditions"   () 30  4)
+(dnf f-flt-cc    "floating branch conditions"   () 30  4)
+(df  f-cond      "conditional arithmetic"       ()  8  1 UINT #f #f)
+(df  f-ccond     "lr branch condition"          () 12  1 UINT #f #f)
+(df  f-hint      "2 bit branch prediction hint" () 17  2 UINT #f #f)
+(df  f-LI        "link indicator"               () 25  1 UINT #f #f)
+(df  f-lock      "cache lock indicator"         () 25  1 UINT #f #f)
+(df  f-debug     "debug mode indicator"         () 25  1 UINT #f #f)
+(df  f-A         "all accumulator bit"          () 17  1 UINT #f #f)
+(df  f-ae        "cache all entries indicator"  () 25  1 UINT #f #f)
+
+(dnf  f-spr-h "upper 6 bits of spr"  () 30  6)
+(dnf  f-spr-l "lower 6 bits of spr"  () 17  6)
+(dnmf f-spr   "special purpose register" () UINT
+      (f-spr-h f-spr-l)
+      (sequence () ; insert
+               (set (ifield f-spr-h) (srl (ifield f-spr) (const 6)))
+               (set (ifield f-spr-l) (and (ifield f-spr) (const #x3f)))
+               )
+      (sequence () ; extract
+               (set (ifield f-spr) (or (sll (ifield f-spr-h) (const 6))
+                                       (ifield f-spr-l)))
+               )
+)
+
+(df  f-label16    "18 bit pc relative signed offset" (PCREL-ADDR) 15 16 INT
+     ((value pc) (sra WI (sub WI value pc) (const 2)))
+     ((value pc) (add WI (sll WI value (const 2)) pc))
+)
+
+(df   f-labelH6   "upper 6  bits of label24"  () 30  6 INT #f #f)
+(dnf  f-labelL18  "lower 18 bits of label24"  () 17 18)
+(dnmf f-label24   "26 bit signed offset"     (PCREL-ADDR) INT
+      (f-labelH6 f-labelL18)
+      ; insert
+      (sequence ()
+               (set (ifield f-labelH6)
+                    (sra WI (sub (ifield f-label24) pc) (const 20)))
+               (set (ifield f-labelL18)
+                    (and (srl (sub (ifield f-label24) pc) (const 2))
+                         (const #x3ffff)))
+               )
+      ; extract
+      (sequence ()
+               (set (ifield f-label24)
+                    (add (sll (or (sll (ifield f-labelH6) (const 18))
+                                  (ifield f-labelL18))
+                              (const 2))
+                         pc)))
+)
+
+(dnf f-LRAE "Load Real Address E flag" () 5 1)
+(dnf f-LRAD "Load Real Address D flag" () 4 1)
+(dnf f-LRAS "Load Real Address S flag" () 3 1)
+
+(dnf f-TLBPRopx "TLB Probe operation number" () 28 3)
+(dnf f-TLBPRL   "TLB Probe L flag" () 25 1)
+
+(dnf f-ICCi_1-null  "null field" (RESERVED) 11  2)
+(dnf f-ICCi_2-null  "null field" (RESERVED) 26  2)
+(dnf f-ICCi_3-null  "null field" (RESERVED)  1  2)
+(dnf f-FCCi_1-null  "null field" (RESERVED) 11  2)
+(dnf f-FCCi_2-null  "null field" (RESERVED) 26  2)
+(dnf f-FCCi_3-null  "null field" (RESERVED)  1  2)
+(dnf f-rs-null      "null field" (RESERVED) 17  6)
+(dnf f-GRi-null     "null field" (RESERVED) 17  6)
+(dnf f-GRj-null     "null field" (RESERVED)  5  6)
+(dnf f-GRk-null     "null field" (RESERVED) 30  6)
+(dnf f-FRi-null     "null field" (RESERVED) 17  6)
+(dnf f-FRj-null     "null field" (RESERVED)  5  6)
+(dnf f-ACCj-null    "null field" (RESERVED)  5  6)
+(dnf f-rd-null      "null field" (RESERVED) 30  6)
+(dnf f-cond-null    "null field" (RESERVED) 30  4)
+(dnf f-ccond-null   "null field" (RESERVED) 12  1)
+(dnf f-s12-null     "null field" (RESERVED) 11 12)
+(dnf f-label16-null "null field" (RESERVED) 15 16)
+(dnf f-misc-null-1  "null field" (RESERVED) 30  5)
+(dnf f-misc-null-2  "null field" (RESERVED) 11  6)
+(dnf f-misc-null-3  "null field" (RESERVED) 11  4)
+(dnf f-misc-null-4  "null field" (RESERVED) 17  2)
+(dnf f-misc-null-5  "null field" (RESERVED) 17 16)
+(dnf f-misc-null-6  "null field" (RESERVED) 30  3)
+(dnf f-misc-null-7  "null field" (RESERVED) 17  3)
+(dnf f-misc-null-8  "null field" (RESERVED)  5  3)
+(dnf f-misc-null-9  "null field" (RESERVED)  5  4)
+(dnf f-misc-null-10 "null field" (RESERVED) 16  5)
+(dnf f-misc-null-11 "null field" (RESERVED)  5  1)
+
+(dnf f-LRA-null     "null field" (RESERVED)  2  3)
+(dnf f-TLBPR-null   "null field" (RESERVED) 30  2)
+
+(dnf f-LI-off      "null field" (RESERVED) 25  1)
+(dnf f-LI-on       "null field" (RESERVED) 25  1)
+
+; Relocation annotations.
+(dsh h-reloc-ann   "relocation annotation" () (register BI))
+(dnf f-reloc-ann   "relocation annotation" () 0 0)
+
+(define-pmacro (dann xname xcomment xmode xparse xprint)
+  (define-operand
+    (name xname)
+    (comment xcomment)
+    (type h-reloc-ann)
+    (index f-reloc-ann)
+    (mode xmode)
+    (handlers (parse xparse) (print xprint))
+    )
+  )
+
+\f
+; Enums.
+
+; insn-op:
+; FIXME: should use die macro or some such
+(define-normal-insn-enum insn-op "insn op enums" () OP_ f-op
+ (
+ "00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "0A" "0B" "0C" "0D" "0E" "0F"
+ "10" "11" "12" "13" "14" "15" "16" "17" "18" "19" "1A" "1B" "1C" "1D" "1E" "1F"
+ "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "2A" "2B" "2C" "2D" "2E" "2F"
+ "30" "31" "32" "33" "34" "35" "36" "37" "38" "39" "3A" "3B" "3C" "3D" "3E" "3F"
+ "40" "41" "42" "43" "44" "45" "46" "47" "48" "49" "4A" "4B" "4C" "4D" "4E" "4F"
+ "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "5A" "5B" "5C" "5D" "5E" "5F"
+ "60" "61" "62" "63" "64" "65" "66" "67" "68" "69" "6A" "6B" "6C" "6D" "6E" "6F"
+ "70" "71" "72" "73" "74" "75" "76" "77" "78" "79" "7A" "7B" "7C" "7D" "7E" "7F"
+ )
+)
+
+(define-normal-insn-enum insn-ope1 "insn ope enums" () OPE1_ f-ope1
+ (
+ "00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "0A" "0B" "0C" "0D" "0E" "0F"
+ "10" "11" "12" "13" "14" "15" "16" "17" "18" "19" "1A" "1B" "1C" "1D" "1E" "1F"
+ "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "2A" "2B" "2C" "2D" "2E" "2F"
+ "30" "31" "32" "33" "34" "35" "36" "37" "38" "39" "3A" "3B" "3C" "3D" "3E" "3F"
+ )
+)
+
+(define-normal-insn-enum insn-ope2 "insn ope enums" () OPE2_ f-ope2
+ (
+ "00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "0A" "0B" "0C" "0D" "0E" "0F"
+ )
+)
+
+(define-normal-insn-enum insn-ope3 "insn ope enums" () OPE3_ f-ope3
+ (
+ "00" "01" "02" "03" "04" "05" "06" "07"
+ )
+)
+
+(define-normal-insn-enum insn-ope4 "insn ope enums" () OPE4_ f-ope4
+ (
+ "0" "1" "2" "3"
+ )
+)
+
+; int-cc: integer branch conditions
+; FIXME: should use die macro or some such
+(define-normal-insn-enum int-cc "integer branch cond enums" () ICC_ f-int-cc
+  (
+   "nev" "c"  "v"  "lt" "eq" "ls" "n" "le"
+   "ra"  "nc" "nv" "ge" "ne" "hi" "p" "gt"
+  )
+)
+
+; flt-cc: floating-point/media branch conditions
+; FIXME: should use die macro or some such
+(define-normal-insn-enum flt-cc "float branch cond enums" () FCC_ f-flt-cc
+  ("nev" "u" "gt" "ug" "lt" "ul" "lg" "ne"
+   "eq" "ue" "ge" "uge" "le" "ule" "o" "ra")
+)
+\f
+; Hardware pieces.
+; These entries list the elements of the raw hardware.
+; They're also used to provide tables and other elements of the assembly
+; language.
+(dnh h-pc "program counter" (PC PROFILE) (pc) () () ())
+
+; The PSR. The individual fields are referenced more than the entire
+; register, so reference them directly. We can assemble the
+; entire register contents when necessary.
+;
+(dsh h-psr_imple "PSR.IMPLE"   () (register UQI))
+(dsh h-psr_ver   "PSR.VER"     () (register UQI))
+(dsh h-psr_ice   "PSR.ICE bit" () (register BI))
+(dsh h-psr_nem   "PSR.NEM bit" () (register BI))
+(dsh h-psr_cm    "PSR.CM  bit" () (register BI))
+(dsh h-psr_be    "PSR.BE  bit" () (register BI))
+(dsh h-psr_esr   "PSR.ESR bit" () (register BI))
+(dsh h-psr_ef    "PSR.EF  bit" () (register BI))
+(dsh h-psr_em    "PSR.EM  bit" () (register BI))
+(dsh h-psr_pil   "PSR.PIL    " () (register UQI))
+(dsh h-psr_ps    "PSR.PS  bit" () (register BI))
+(dsh h-psr_et    "PSR.ET  bit" () (register BI))
+
+; PSR.S requires special handling because the shadow registers (SR0-SR4) must
+; be switched with GR4-GR7 when changing from user to supervisor mode or
+; vice-versa.
+(define-hardware
+  (name h-psr_s)
+  (comment "PSR.S bit")
+  (attrs)
+  (type register BI)
+  (get)
+  (set (newval) (c-call VOID "@cpu@_h_psr_s_set_handler" newval))
+)
+
+; The TBR. The individual bits are referenced more than the entire
+; register, so reference them directly. We can assemble the
+; entire register contents when necessary.
+;
+(dsh h-tbr_tba "TBR.TBA" () (register UWI))
+(dsh h-tbr_tt  "TBR.TT"  () (register UQI))
+
+; The BPSR. The individual bits are referenced more than the entire
+; register, so reference them directly. We can assemble the
+; entire register contents when necessary.
+;
+(dsh h-bpsr_bs   "PSR.S   bit" () (register BI))
+(dsh h-bpsr_bet  "PSR.ET  bit" () (register BI))
+
+; General registers
+;
+(define-keyword
+  (name gr-names)
+  (print-name h-gr)
+  (prefix "")
+  (values
+   (sp 1) (fp 2)
+   (gr0   0)(gr1   1)(gr2   2)(gr3   3)(gr4   4)(gr5   5)(gr6   6)(gr7   7)
+   (gr8   8)(gr9   9)(gr10 10)(gr11 11)(gr12 12)(gr13 13)(gr14 14)(gr15 15)
+   (gr16 16)(gr17 17)(gr18 18)(gr19 19)(gr20 20)(gr21 21)(gr22 22)(gr23 23)
+   (gr24 24)(gr25 25)(gr26 26)(gr27 27)(gr28 28)(gr29 29)(gr30 30)(gr31 31)
+   (gr32 32)(gr33 33)(gr34 34)(gr35 35)(gr36 36)(gr37 37)(gr38 38)(gr39 39)
+   (gr40 40)(gr41 41)(gr42 42)(gr43 43)(gr44 44)(gr45 45)(gr46 46)(gr47 47)
+   (gr48 48)(gr49 49)(gr50 50)(gr51 51)(gr52 52)(gr53 53)(gr54 54)(gr55 55)
+   (gr56 56)(gr57 57)(gr58 58)(gr59 59)(gr60 60)(gr61 61)(gr62 62)(gr63 63)
+  )
+)
+
+(define-hardware
+  (name h-gr)
+  (comment "general registers")
+  (attrs PROFILE)
+  (type register USI (64))
+  (indices extern-keyword gr-names)
+  (get (index) (c-call WI "@cpu@_h_gr_get_handler" index))
+  (set (index newval) (c-call VOID "@cpu@_h_gr_set_handler" index newval))
+)
+
+; General Registers as double words
+; These registers are shadowed onto h-gr
+(define-hardware
+  (name h-gr_double)
+  (comment "general registers as double words")
+  (attrs PROFILE VIRTUAL)
+  (type register DI (32))
+  ; FIXME: Need constraint to prohibit odd numbers.
+  (indices extern-keyword gr-names)
+  (get (index)
+       (c-call DI "@cpu@_h_gr_double_get_handler" index))
+  (set (index newval)
+       (c-call VOID "@cpu@_h_gr_double_set_handler" index newval))
+)
+
+; General Registers as high and low half words
+; These registers are shadowed onto h-gr
+(define-hardware
+  (name h-gr_hi)
+  (comment "general registers as high half word")
+  (attrs PROFILE VIRTUAL)
+  (type register UHI (64))
+  (indices extern-keyword gr-names)
+  (get (index) (c-call UHI "@cpu@_h_gr_hi_get_handler" index))
+  (set (index newval) (c-call VOID "@cpu@_h_gr_hi_set_handler" index newval))
+)
+(define-hardware
+  (name h-gr_lo)
+  (comment "general registers as low half word")
+  (attrs PROFILE VIRTUAL)
+  (type register UHI (64))
+  (indices extern-keyword gr-names)
+  (get (index) (c-call UHI "@cpu@_h_gr_lo_get_handler" index))
+  (set (index newval) (c-call VOID "@cpu@_h_gr_lo_set_handler" index newval))
+)
+
+; Floating Point Registers
+(define-keyword
+  (name fr-names)
+  (print-name h-fr)
+  (prefix "")
+  (values
+   (fr0   0)(fr1   1)(fr2   2)(fr3   3)(fr4   4)(fr5   5)(fr6   6)(fr7   7)
+   (fr8   8)(fr9   9)(fr10 10)(fr11 11)(fr12 12)(fr13 13)(fr14 14)(fr15 15)
+   (fr16 16)(fr17 17)(fr18 18)(fr19 19)(fr20 20)(fr21 21)(fr22 22)(fr23 23)
+   (fr24 24)(fr25 25)(fr26 26)(fr27 27)(fr28 28)(fr29 29)(fr30 30)(fr31 31)
+   (fr32 32)(fr33 33)(fr34 34)(fr35 35)(fr36 36)(fr37 37)(fr38 38)(fr39 39)
+   (fr40 40)(fr41 41)(fr42 42)(fr43 43)(fr44 44)(fr45 45)(fr46 46)(fr47 47)
+   (fr48 48)(fr49 49)(fr50 50)(fr51 51)(fr52 52)(fr53 53)(fr54 54)(fr55 55)
+   (fr56 56)(fr57 57)(fr58 58)(fr59 59)(fr60 60)(fr61 61)(fr62 62)(fr63 63)
+  )
+)
+
+(define-hardware
+  (name h-fr)
+  (comment "floating point registers")
+  (attrs PROFILE)
+  (type register SF (64))
+  (indices extern-keyword fr-names)
+  (get (index) (c-call SF "@cpu@_h_fr_get_handler" index))
+  (set (index newval) (c-call VOID "@cpu@_h_fr_set_handler" index newval))
+)
+
+; Floating Point Registers as double precision
+; These registers are shadowed onto h-fr
+
+(define-hardware
+  (name h-fr_double)
+  (comment "floating point registers as double precision")
+  (attrs PROFILE VIRTUAL)
+  (type register DF (32))
+  ; FIXME: Need constraint to prohibit odd numbers.
+  (indices extern-keyword fr-names)
+  (get (index)
+       (c-call DF "@cpu@_h_fr_double_get_handler" index))
+  (set (index newval)
+       (c-call VOID "@cpu@_h_fr_double_set_handler" index newval))
+)
+
+; Floating Point Registers as integer words.
+; These registers are shadowed onto h-fr
+
+(define-hardware
+  (name h-fr_int)
+  (comment "floating point registers as integers")
+  (attrs PROFILE VIRTUAL)
+  (type register USI (64))
+  (indices extern-keyword fr-names)
+  (get (index)
+       (c-call USI "@cpu@_h_fr_int_get_handler" index))
+  (set (index newval)
+       (c-call VOID "@cpu@_h_fr_int_set_handler" index newval))
+)
+
+; Floating Point Registers as high and low half words
+; These registers are shadowed onto h-fr
+(define-hardware
+  (name h-fr_hi)
+  (comment "floating point registers as unsigned high half word")
+  (attrs PROFILE VIRTUAL)
+  (type register UHI (64))
+  (indices extern-keyword fr-names)
+  (get (regno) (srl (reg h-fr_int regno) 16))
+  (set (regno newval) (set (reg h-fr_int regno)
+                          (or (and (reg h-fr_int regno) #xffff)
+                              (sll newval 16))))
+)
+(define-hardware
+  (name h-fr_lo)
+  (comment "floating point registers as unsigned low half word")
+  (attrs PROFILE VIRTUAL)
+  (type register UHI (64))
+  (indices extern-keyword fr-names)
+  (get (regno) (and (reg h-fr_int regno) #xffff))
+  (set (regno newval) (set (reg h-fr_int regno)
+                          (or (and (reg h-fr_int regno) #xffff0000)
+                              (and newval #xffff))))
+)
+
+; Floating Point Registers as unsigned bytes
+; These registers are shadowed onto h-fr
+(define-hardware
+  (name h-fr_0)
+  (comment "floating point registers as unsigned byte 0")
+  (attrs PROFILE VIRTUAL)
+  (type register UHI (64))
+  (indices extern-keyword fr-names)
+  (get (regno) (and (reg h-fr_int regno) #xff))
+  (set (regno newval)
+       (sequence ()
+                (if (gt USI newval #xff)
+                    (set newval #xff))
+                (set (reg h-fr_int regno) (or (and (reg h-fr_int regno) #xffffff00)
+                                          newval))))
+)
+(define-hardware
+  (name h-fr_1)
+  (comment "floating point registers as unsigned byte 1")
+  (attrs PROFILE VIRTUAL)
+  (type register UHI (64))
+  (indices extern-keyword fr-names)
+  (get (regno) (and (srl (reg h-fr_int regno) 8) #xff))
+  (set (regno newval)
+       (sequence ()
+                (if (gt USI newval #xff)
+                    (set newval #xff))
+                (set (reg h-fr_int regno) (or (and (reg h-fr_int regno) #xffff00ff) 
+                                          (sll newval 8)))))
+)
+(define-hardware
+  (name h-fr_2)
+  (comment "floating point registers as unsigned byte 2")
+  (attrs PROFILE VIRTUAL)
+  (type register UHI (64))
+  (indices extern-keyword fr-names)
+  (get (regno) (and (srl (reg h-fr_int regno) 16) #xff))
+  (set (regno newval)
+       (sequence ()
+                (if (gt USI newval #xff)
+                    (set newval #xff))
+                (set (reg h-fr_int regno) (or (and (reg h-fr_int regno) #xff00ffff) 
+                                          (sll newval 16)))))
+)
+(define-hardware
+  (name h-fr_3)
+  (comment "floating point registers as unsigned byte 3")
+  (attrs PROFILE VIRTUAL)
+  (type register UHI (64))
+  (indices extern-keyword fr-names)
+  (get (regno) (and (srl (reg h-fr_int regno) 24) #xff))
+  (set (regno newval)
+       (sequence ()
+                (if (gt USI newval #xff)
+                    (set newval #xff))
+                (set (reg h-fr_int regno) (or (and (reg h-fr_int regno) #x00ffffff) 
+                                          (sll newval 24)))))
+)
+; Coprocessor Registers
+;
+(define-keyword
+  (name cpr-names)
+  (print-name h-cpr)
+  (prefix "")
+  (values
+(cpr0   0)(cpr1   1)(cpr2   2)(cpr3   3)(cpr4   4)(cpr5   5)(cpr6   6)(cpr7   7)
+(cpr8   8)(cpr9   9)(cpr10 10)(cpr11 11)(cpr12 12)(cpr13 13)(cpr14 14)(cpr15 15)
+(cpr16 16)(cpr17 17)(cpr18 18)(cpr19 19)(cpr20 20)(cpr21 21)(cpr22 22)(cpr23 23)
+(cpr24 24)(cpr25 25)(cpr26 26)(cpr27 27)(cpr28 28)(cpr29 29)(cpr30 30)(cpr31 31)
+(cpr32 32)(cpr33 33)(cpr34 34)(cpr35 35)(cpr36 36)(cpr37 37)(cpr38 38)(cpr39 39)
+(cpr40 40)(cpr41 41)(cpr42 42)(cpr43 43)(cpr44 44)(cpr45 45)(cpr46 46)(cpr47 47)
+(cpr48 48)(cpr49 49)(cpr50 50)(cpr51 51)(cpr52 52)(cpr53 53)(cpr54 54)(cpr55 55)
+(cpr56 56)(cpr57 57)(cpr58 58)(cpr59 59)(cpr60 60)(cpr61 61)(cpr62 62)(cpr63 63)
+  )
+)
+
+(define-hardware
+  (name h-cpr)
+  (comment "coprocessor registers")
+  (attrs PROFILE (MACH frv))
+  (type register WI (64))
+  (indices extern-keyword cpr-names)
+)
+
+; Coprocessor Registers as double words
+; These registers are shadowed onto h-cpr
+(define-hardware
+  (name h-cpr_double)
+  (comment "coprocessor registers as double words")
+  (attrs PROFILE VIRTUAL (MACH frv))
+  (type register DI (32))
+  ; FIXME: Need constraint to prohibit odd numbers.
+  (indices extern-keyword cpr-names)
+  (get (index)
+       (c-call DI "@cpu@_h_cpr_double_get_handler" index))
+  (set (index newval)
+       (c-call VOID "@cpu@_h_cpr_double_set_handler" index newval))
+)
+
+; Special Purpose Registers
+;
+(define-keyword
+  (name spr-names)
+  (print-name h-spr)
+  (prefix "")
+  (values
+   (psr        0) (pcsr       1) (bpcsr      2) (tbr        3) (bpsr       4)
+
+   (hsr0      16) (hsr1      17) (hsr2      18) (hsr3      19)
+   (hsr4      20) (hsr5      21) (hsr6      22) (hsr7      23)
+   (hsr8      24) (hsr9      25) (hsr10     26) (hsr11     27)
+   (hsr12     28) (hsr13     29) (hsr14     30) (hsr15     31)
+   (hsr16     32) (hsr17     33) (hsr18     34) (hsr19     35)
+   (hsr20     36) (hsr21     37) (hsr22     38) (hsr23     39)
+   (hsr24     40) (hsr25     41) (hsr26     42) (hsr27     43)
+   (hsr28     44) (hsr29     45) (hsr30     46) (hsr31     47)
+   (hsr32     48) (hsr33     49) (hsr34     50) (hsr35     51)
+   (hsr36     52) (hsr37     53) (hsr38     54) (hsr39     55)
+   (hsr40     56) (hsr41     57) (hsr42     58) (hsr43     59)
+   (hsr44     60) (hsr45     61) (hsr46     62) (hsr47     63)
+   (hsr48     64) (hsr49     65) (hsr50     66) (hsr51     67)
+   (hsr52     68) (hsr53     69) (hsr54     70) (hsr55     71)
+   (hsr56     72) (hsr57     73) (hsr58     74) (hsr59     75)
+   (hsr60     76) (hsr61     77) (hsr62     78) (hsr63     79)
+
+   (ccr      256) (cccr     263) (lr       272) (lcr      273) (iacc0h   280) (iacc0l   281) (isr      288)
+
+   (neear0   352) (neear1   353) (neear2   354) (neear3   355)
+   (neear4   356) (neear5   357) (neear6   358) (neear7   359)
+   (neear8   360) (neear9   361) (neear10  362) (neear11  363)
+   (neear12  364) (neear13  365) (neear14  366) (neear15  367)
+   (neear16  368) (neear17  369) (neear18  370) (neear19  371)
+   (neear20  372) (neear21  373) (neear22  374) (neear23  375)
+   (neear24  376) (neear25  377) (neear26  378) (neear27  379)
+   (neear28  380) (neear29  381) (neear30  382) (neear31  383)
+
+   (nesr0    384) (nesr1    385) (nesr2    386) (nesr3    387)
+   (nesr4    388) (nesr5    389) (nesr6    390) (nesr7    391)
+   (nesr8    392) (nesr9    393) (nesr10   394) (nesr11   395)
+   (nesr12   396) (nesr13   397) (nesr14   398) (nesr15   399)
+   (nesr16   400) (nesr17   401) (nesr18   402) (nesr19   403)
+   (nesr20   404) (nesr21   405) (nesr22   406) (nesr23   407)
+   (nesr24   408) (nesr25   409) (nesr26   410) (nesr27   411)
+   (nesr28   412) (nesr29   413) (nesr30   414) (nesr31   415)
+
+   (necr     416)
+
+   (gner0    432) (gner1    433)
+
+   (fner0    434) (fner1    435)
+
+   (epcr0    512) (epcr1    513) (epcr2    514) (epcr3    515)
+   (epcr4    516) (epcr5    517) (epcr6    518) (epcr7    519)
+   (epcr8    520) (epcr9    521) (epcr10   522) (epcr11   523)
+   (epcr12   524) (epcr13   525) (epcr14   526) (epcr15   527)
+   (epcr16   528) (epcr17   529) (epcr18   530) (epcr19   531)
+   (epcr20   532) (epcr21   533) (epcr22   534) (epcr23   535)
+   (epcr24   536) (epcr25   537) (epcr26   538) (epcr27   539)
+   (epcr28   540) (epcr29   541) (epcr30   542) (epcr31   543)
+   (epcr32   544) (epcr33   545) (epcr34   546) (epcr35   547)
+   (epcr36   548) (epcr37   549) (epcr38   550) (epcr39   551)
+   (epcr40   552) (epcr41   553) (epcr42   554) (epcr43   555)
+   (epcr44   556) (epcr45   557) (epcr46   558) (epcr47   559)
+   (epcr48   560) (epcr49   561) (epcr50   562) (epcr51   563)
+   (epcr52   564) (epcr53   565) (epcr54   566) (epcr55   567)
+   (epcr56   568) (epcr57   569) (epcr58   570) (epcr59   571)
+   (epcr60   572) (epcr61   573) (epcr62   574) (epcr63   575)
+
+   (esr0     576) (esr1     577) (esr2     578) (esr3     579)
+   (esr4     580) (esr5     581) (esr6     582) (esr7     583)
+   (esr8     584) (esr9     585) (esr10    586) (esr11    587)
+   (esr12    588) (esr13    589) (esr14    590) (esr15    591)
+   (esr16    592) (esr17    593) (esr18    594) (esr19    595)
+   (esr20    596) (esr21    597) (esr22    598) (esr23    599)
+   (esr24    600) (esr25    601) (esr26    602) (esr27    603)
+   (esr28    604) (esr29    605) (esr30    606) (esr31    607)
+   (esr32    608) (esr33    609) (esr34    610) (esr35    611)
+   (esr36    612) (esr37    613) (esr38    614) (esr39    615)
+   (esr40    616) (esr41    617) (esr42    618) (esr43    619)
+   (esr44    620) (esr45    621) (esr46    622) (esr47    623)
+   (esr48    624) (esr49    625) (esr50    626) (esr51    627)
+   (esr52    628) (esr53    629) (esr54    630) (esr55    631)
+   (esr56    632) (esr57    633) (esr58    634) (esr59    635)
+   (esr60    636) (esr61    637) (esr62    638) (esr63    639)
+
+   (eir0     640) (eir1     641) (eir2     642) (eir3     643)
+   (eir4     644) (eir5     645) (eir6     646) (eir7     647)
+   (eir8     648) (eir9     649) (eir10    650) (eir11    651)
+   (eir12    652) (eir13    653) (eir14    654) (eir15    655)
+   (eir16    656) (eir17    657) (eir18    658) (eir19    659)
+   (eir20    660) (eir21    661) (eir22    662) (eir23    663)
+   (eir24    664) (eir25    665) (eir26    666) (eir27    667)
+   (eir28    668) (eir29    669) (eir30    670) (eir31    671)
+
+   (esfr0    672) (esfr1    673)
+
+   (sr0      768) (sr1      769) (sr2      770) (sr3      771) 
+
+   (scr0     832) (scr1     833) (scr2     834) (scr3     835)
+
+   (fsr0    1024) (fsr1    1025) (fsr2    1026) (fsr3    1027)
+   (fsr4    1028) (fsr5    1029) (fsr6    1030) (fsr7    1031)
+   (fsr8    1032) (fsr9    1033) (fsr10   1034) (fsr11   1035)
+   (fsr12   1036) (fsr13   1037) (fsr14   1038) (fsr15   1039)
+   (fsr16   1040) (fsr17   1041) (fsr18   1042) (fsr19   1043)
+   (fsr20   1044) (fsr21   1045) (fsr22   1046) (fsr23   1047)
+   (fsr24   1048) (fsr25   1049) (fsr26   1050) (fsr27   1051)
+   (fsr28   1052) (fsr29   1053) (fsr30   1054) (fsr31   1055)
+   (fsr32   1056) (fsr33   1057) (fsr34   1058) (fsr35   1059)
+   (fsr36   1060) (fsr37   1061) (fsr38   1062) (fsr39   1063)
+   (fsr40   1064) (fsr41   1065) (fsr42   1066) (fsr43   1067)
+   (fsr44   1068) (fsr45   1069) (fsr46   1070) (fsr47   1071)
+   (fsr48   1072) (fsr49   1073) (fsr50   1074) (fsr51   1075)
+   (fsr52   1076) (fsr53   1077) (fsr54   1078) (fsr55   1079)
+   (fsr56   1080) (fsr57   1081) (fsr58   1082) (fsr59   1083)
+   (fsr60   1084) (fsr61   1085) (fsr62   1086) (fsr63   1087)
+
+   ; FQ0-FQ31 are 64 bit registers.
+   ; These names allow access to the upper 32 bits of the FQ registers.
+   (fqop0   1088) (fqop1   1090) (fqop2   1092) (fqop3   1094) 
+   (fqop4   1096) (fqop5   1098) (fqop6   1100) (fqop7   1102) 
+   (fqop8   1104) (fqop9   1106) (fqop10  1108) (fqop11  1110) 
+   (fqop12  1112) (fqop13  1114) (fqop14  1116) (fqop15  1118) 
+   (fqop16  1120) (fqop17  1122) (fqop18  1124) (fqop19  1126) 
+   (fqop20  1128) (fqop21  1130) (fqop22  1132) (fqop23  1134) 
+   (fqop24  1136) (fqop25  1138) (fqop26  1140) (fqop27  1142) 
+   (fqop28  1144) (fqop29  1146) (fqop30  1148) (fqop31  1150) 
+   ; These names allow access to the lower 32 bits of the FQ registers.
+   (fqst0   1089) (fqst1   1091) (fqst2   1093) (fqst3   1095) 
+   (fqst4   1097) (fqst5   1099) (fqst6   1101) (fqst7   1103) 
+   (fqst8   1105) (fqst9   1107) (fqst10  1109) (fqst11  1111) 
+   (fqst12  1113) (fqst13  1115) (fqst14  1117) (fqst15  1119) 
+   (fqst16  1121) (fqst17  1123) (fqst18  1125) (fqst19  1127) 
+   (fqst20  1129) (fqst21  1131) (fqst22  1133) (fqst23  1135) 
+   (fqst24  1137) (fqst25  1139) (fqst26  1141) (fqst27  1143) 
+   (fqst28  1145) (fqst29  1147) (fqst30  1149) (fqst31  1151) 
+   ; These also access the lower 32 bits of the FQ registers.
+   ; These are not accessible as spr registers (see LSI appendix - section 13.4)
+;  (fq0     1089) (fq1     1091) (fq2     1093) (fq3     1095) 
+;  (fq4     1097) (fq5     1099) (fq6     1101) (fq7     1103) 
+;  (fq8     1105) (fq9     1107) (fq10    1109) (fq11    1111) 
+;  (fq12    1113) (fq13    1115) (fq14    1117) (fq15    1119) 
+;  (fq16    1121) (fq17    1123) (fq18    1125) (fq19    1127) 
+;  (fq20    1129) (fq21    1131) (fq22    1133) (fq23    1135) 
+;  (fq24    1137) (fq25    1139) (fq26    1141) (fq27    1143) 
+;  (fq28    1145) (fq29    1147) (fq30    1149) (fq31    1151) 
+
+   (mcilr0  1272) (mcilr1  1273)
+
+   (msr0    1280) (msr1    1281) (msr2    1282) (msr3    1283)
+   (msr4    1284) (msr5    1285) (msr6    1286) (msr7    1287)
+   (msr8    1288) (msr9    1289) (msr10   1290) (msr11   1291)
+   (msr12   1292) (msr13   1293) (msr14   1294) (msr15   1295)
+   (msr16   1296) (msr17   1297) (msr18   1298) (msr19   1299)
+   (msr20   1300) (msr21   1301) (msr22   1302) (msr23   1303)
+   (msr24   1304) (msr25   1305) (msr26   1306) (msr27   1307)
+   (msr28   1308) (msr29   1309) (msr30   1310) (msr31   1311)
+   (msr32   1312) (msr33   1313) (msr34   1314) (msr35   1315)
+   (msr36   1316) (msr37   1317) (msr38   1318) (msr39   1319)
+   (msr40   1320) (msr41   1321) (msr42   1322) (msr43   1323)
+   (msr44   1324) (msr45   1325) (msr46   1326) (msr47   1327)
+   (msr48   1328) (msr49   1329) (msr50   1330) (msr51   1331)
+   (msr52   1332) (msr53   1333) (msr54   1334) (msr55   1335)
+   (msr56   1336) (msr57   1337) (msr58   1338) (msr59   1339)
+   (msr60   1340) (msr61   1341) (msr62   1342) (msr63   1343)
+
+   ; MQ0-MQ31 are 64 bit registers.
+   ; These names allow access to the upper 32 bits of the MQ registers.
+   (mqop0   1344) (mqop1   1346) (mqop2   1348) (mqop3   1350) 
+   (mqop4   1352) (mqop5   1354) (mqop6   1356) (mqop7   1358) 
+   (mqop8   1360) (mqop9   1362) (mqop10  1364) (mqop11  1366) 
+   (mqop12  1368) (mqop13  1370) (mqop14  1372) (mqop15  1374) 
+   (mqop16  1376) (mqop17  1378) (mqop18  1380) (mqop19  1382) 
+   (mqop20  1384) (mqop21  1386) (mqop22  1388) (mqop23  1390) 
+   (mqop24  1392) (mqop25  1394) (mqop26  1396) (mqop27  1398) 
+   (mqop28  1400) (mqop29  1402) (mqop30  1404) (mqop31  1406) 
+   ; These names allow access to the lower 32 bits of the MQ registers.
+   (mqst0   1345) (mqst1   1347) (mqst2   1349) (mqst3   1351) 
+   (mqst4   1353) (mqst5   1355) (mqst6   1357) (mqst7   1359) 
+   (mqst8   1361) (mqst9   1363) (mqst10  1365) (mqst11  1367) 
+   (mqst12  1369) (mqst13  1371) (mqst14  1373) (mqst15  1375) 
+   (mqst16  1377) (mqst17  1379) (mqst18  1381) (mqst19  1383) 
+   (mqst20  1385) (mqst21  1387) (mqst22  1389) (mqst23  1391) 
+   (mqst24  1393) (mqst25  1395) (mqst26  1397) (mqst27  1399) 
+   (mqst28  1401) (mqst29  1403) (mqst30  1405) (mqst31  1407) 
+   ; These also access the lower 32 bits of the MQ registers.
+   ; These are not accessible as spr registers (see LSI appendix - section 13.4)
+;  (mq0     1345) (mq1     1347) (mq2     1349) (mq3     1351) 
+;  (mq4     1353) (mq5     1355) (mq6     1357) (mq7     1359) 
+;  (mq8     1361) (mq9     1363) (mq10    1365) (mq11    1367) 
+;  (mq12    1369) (mq13    1371) (mq14    1373) (mq15    1375) 
+;  (mq16    1377) (mq17    1379) (mq18    1381) (mq19    1383) 
+;  (mq20    1385) (mq21    1387) (mq22    1389) (mq23    1391) 
+;  (mq24    1393) (mq25    1395) (mq26    1397) (mq27    1399) 
+;  (mq28    1401) (mq29    1403) (mq30    1405) (mq31    1407) 
+
+   ; These are not accessible as spr registers (see LSI appendix - section 13.4)
+;  (acc0    1408) (acc1    1409) (acc2    1410) (acc3    1411)
+;  (acc4    1412) (acc5    1413) (acc6    1414) (acc7    1415)
+;  (acc8    1416) (acc9    1417) (acc10   1418) (acc11   1419)
+;  (acc12   1420) (acc13   1421) (acc14   1422) (acc15   1423)
+;  (acc16   1424) (acc17   1425) (acc18   1426) (acc19   1427)
+;  (acc20   1428) (acc21   1429) (acc22   1430) (acc23   1431)
+;  (acc24   1432) (acc25   1433) (acc26   1434) (acc27   1435)
+;  (acc28   1436) (acc29   1437) (acc30   1438) (acc31   1439)
+;  (acc32   1440) (acc33   1441) (acc34   1442) (acc35   1443)
+;  (acc36   1444) (acc37   1445) (acc38   1446) (acc39   1447)
+;  (acc40   1448) (acc41   1449) (acc42   1450) (acc43   1451)
+;  (acc44   1452) (acc45   1453) (acc46   1454) (acc47   1455)
+;  (acc48   1456) (acc49   1457) (acc50   1458) (acc51   1459)
+;  (acc52   1460) (acc53   1461) (acc54   1462) (acc55   1463)
+;  (acc56   1464) (acc57   1465) (acc58   1466) (acc59   1467)
+;  (acc60   1468) (acc61   1469) (acc62   1470) (acc63   1471)
+
+;  (accg0   1472) (accg1   1473) (accg2   1474) (accg3   1475)
+;  (accg4   1476) (accg5   1477) (accg6   1478) (accg7   1479)
+;  (accg8   1480) (accg9   1481) (accg10  1482) (accg11  1483)
+;  (accg12  1484) (accg13  1485) (accg14  1486) (accg15  1487)
+;  (accg16  1488) (accg17  1489) (accg18  1490) (accg19  1491)
+;  (accg20  1492) (accg21  1493) (accg22  1494) (accg23  1495)
+;  (accg24  1496) (accg25  1497) (accg26  1498) (accg27  1499)
+;  (accg28  1500) (accg29  1501) (accg30  1502) (accg31  1503)
+;  (accg32  1504) (accg33  1505) (accg34  1506) (accg35  1507)
+;  (accg36  1508) (accg37  1509) (accg38  1510) (accg39  1511)
+;  (accg40  1512) (accg41  1513) (accg42  1514) (accg43  1515)
+;  (accg44  1516) (accg45  1517) (accg46  1518) (accg47  1519)
+;  (accg48  1520) (accg49  1521) (accg50  1522) (accg51  1523)
+;  (accg52  1524) (accg53  1525) (accg54  1526) (accg55  1527)
+;  (accg56  1528) (accg57  1529) (accg58  1530) (accg59  1531)
+;  (accg60  1532) (accg61  1533) (accg62  1534) (accg63  1535)
+
+   (ear0    1536) (ear1    1537) (ear2    1538) (ear3    1539)
+   (ear4    1540) (ear5    1541) (ear6    1542) (ear7    1543)
+   (ear8    1544) (ear9    1545) (ear10   1546) (ear11   1547)
+   (ear12   1548) (ear13   1549) (ear14   1550) (ear15   1551)
+   (ear16   1552) (ear17   1553) (ear18   1554) (ear19   1555)
+   (ear20   1556) (ear21   1557) (ear22   1558) (ear23   1559)
+   (ear24   1560) (ear25   1561) (ear26   1562) (ear27   1563)
+   (ear28   1564) (ear29   1565) (ear30   1566) (ear31   1567)
+   (ear32   1568) (ear33   1569) (ear34   1570) (ear35   1571)
+   (ear36   1572) (ear37   1573) (ear38   1574) (ear39   1575)
+   (ear40   1576) (ear41   1577) (ear42   1578) (ear43   1579)
+   (ear44   1580) (ear45   1581) (ear46   1582) (ear47   1583)
+   (ear48   1584) (ear49   1585) (ear50   1586) (ear51   1587)
+   (ear52   1588) (ear53   1589) (ear54   1590) (ear55   1591)
+   (ear56   1592) (ear57   1593) (ear58   1594) (ear59   1595)
+   (ear60   1596) (ear61   1597) (ear62   1598) (ear63   1599)
+
+   (edr0    1600) (edr1    1601) (edr2    1602) (edr3    1603)
+   (edr4    1604) (edr5    1605) (edr6    1606) (edr7    1607)
+   (edr8    1608) (edr9    1609) (edr10   1610) (edr11   1611)
+   (edr12   1612) (edr13   1613) (edr14   1614) (edr15   1615)
+   (edr16   1616) (edr17   1617) (edr18   1618) (edr19   1619)
+   (edr20   1620) (edr21   1621) (edr22   1622) (edr23   1623)
+   (edr24   1624) (edr25   1625) (edr26   1626) (edr27   1627)
+   (edr28   1628) (edr29   1629) (edr30   1630) (edr31   1631)
+   (edr32   1632) (edr33   1636) (edr34   1634) (edr35   1635)
+   (edr36   1636) (edr37   1637) (edr38   1638) (edr39   1639)
+   (edr40   1640) (edr41   1641) (edr42   1642) (edr43   1643)
+   (edr44   1644) (edr45   1645) (edr46   1646) (edr47   1647)
+   (edr48   1648) (edr49   1649) (edr50   1650) (edr51   1651)
+   (edr52   1652) (edr53   1653) (edr54   1654) (edr55   1655)
+   (edr56   1656) (edr57   1657) (edr58   1658) (edr59   1659)
+   (edr60   1660) (edr61   1661) (edr62   1662) (edr63   1663)
+
+   (iamlr0  1664) (iamlr1  1665) (iamlr2  1666) (iamlr3  1667)
+   (iamlr4  1668) (iamlr5  1669) (iamlr6  1670) (iamlr7  1671)
+   (iamlr8  1672) (iamlr9  1673) (iamlr10 1674) (iamlr11 1675)
+   (iamlr12 1676) (iamlr13 1677) (iamlr14 1678) (iamlr15 1679)
+   (iamlr16 1680) (iamlr17 1681) (iamlr18 1682) (iamlr19 1683)
+   (iamlr20 1684) (iamlr21 1685) (iamlr22 1686) (iamlr23 1687)
+   (iamlr24 1688) (iamlr25 1689) (iamlr26 1690) (iamlr27 1691)
+   (iamlr28 1692) (iamlr29 1693) (iamlr30 1694) (iamlr31 1695)
+   (iamlr32 1696) (iamlr33 1697) (iamlr34 1698) (iamlr35 1699)
+   (iamlr36 1700) (iamlr37 1701) (iamlr38 1702) (iamlr39 1703)
+   (iamlr40 1704) (iamlr41 1705) (iamlr42 1706) (iamlr43 1707)
+   (iamlr44 1708) (iamlr45 1709) (iamlr46 1710) (iamlr47 1711)
+   (iamlr48 1712) (iamlr49 1713) (iamlr50 1714) (iamlr51 1715)
+   (iamlr52 1716) (iamlr53 1717) (iamlr54 1718) (iamlr55 1719)
+   (iamlr56 1720) (iamlr57 1721) (iamlr58 1722) (iamlr59 1723)
+   (iamlr60 1724) (iamlr61 1725) (iamlr62 1726) (iamlr63 1727)
+
+   (iampr0  1728) (iampr1  1729) (iampr2  1730) (iampr3  1731)
+   (iampr4  1732) (iampr5  1733) (iampr6  1734) (iampr7  1735)
+   (iampr8  1736) (iampr9  1737) (iampr10 1738) (iampr11 1739)
+   (iampr12 1740) (iampr13 1741) (iampr14 1742) (iampr15 1743)
+   (iampr16 1744) (iampr17 1745) (iampr18 1746) (iampr19 1747)
+   (iampr20 1748) (iampr21 1749) (iampr22 1750) (iampr23 1751)
+   (iampr24 1752) (iampr25 1753) (iampr26 1754) (iampr27 1755)
+   (iampr28 1756) (iampr29 1757) (iampr30 1758) (iampr31 1759)
+   (iampr32 1760) (iampr33 1761) (iampr34 1762) (iampr35 1763)
+   (iampr36 1764) (iampr37 1765) (iampr38 1766) (iampr39 1767)
+   (iampr40 1768) (iampr41 1769) (iampr42 1770) (iampr43 1771)
+   (iampr44 1772) (iampr45 1773) (iampr46 1774) (iampr47 1775)
+   (iampr48 1776) (iampr49 1777) (iampr50 1778) (iampr51 1779)
+   (iampr52 1780) (iampr53 1781) (iampr54 1782) (iampr55 1783)
+   (iampr56 1784) (iampr57 1785) (iampr58 1786) (iampr59 1787)
+   (iampr60 1788) (iampr61 1789) (iampr62 1790) (iampr63 1791)
+
+   (damlr0  1792) (damlr1  1793) (damlr2  1794) (damlr3  1795)
+   (damlr4  1796) (damlr5  1797) (damlr6  1798) (damlr7  1799)
+   (damlr8  1800) (damlr9  1801) (damlr10 1802) (damlr11 1803)
+   (damlr12 1804) (damlr13 1805) (damlr14 1806) (damlr15 1807)
+   (damlr16 1808) (damlr17 1809) (damlr18 1810) (damlr19 1811)
+   (damlr20 1812) (damlr21 1813) (damlr22 1814) (damlr23 1815)
+   (damlr24 1816) (damlr25 1817) (damlr26 1818) (damlr27 1819)
+   (damlr28 1820) (damlr29 1821) (damlr30 1822) (damlr31 1823)
+   (damlr32 1824) (damlr33 1825) (damlr34 1826) (damlr35 1827)
+   (damlr36 1828) (damlr37 1829) (damlr38 1830) (damlr39 1831)
+   (damlr40 1832) (damlr41 1833) (damlr42 1834) (damlr43 1835)
+   (damlr44 1836) (damlr45 1837) (damlr46 1838) (damlr47 1839)
+   (damlr48 1840) (damlr49 1841) (damlr50 1842) (damlr51 1843)
+   (damlr52 1844) (damlr53 1845) (damlr54 1846) (damlr55 1847)
+   (damlr56 1848) (damlr57 1849) (damlr58 1850) (damlr59 1851)
+   (damlr60 1852) (damlr61 1853) (damlr62 1854) (damlr63 1855)
+
+   (dampr0  1856) (dampr1  1857) (dampr2  1858) (dampr3  1859)
+   (dampr4  1860) (dampr5  1861) (dampr6  1862) (dampr7  1863)
+   (dampr8  1864) (dampr9  1865) (dampr10 1866) (dampr11 1867)
+   (dampr12 1868) (dampr13 1869) (dampr14 1870) (dampr15 1871)
+   (dampr16 1872) (dampr17 1873) (dampr18 1874) (dampr19 1875)
+   (dampr20 1876) (dampr21 1877) (dampr22 1878) (dampr23 1879)
+   (dampr24 1880) (dampr25 1881) (dampr26 1882) (dampr27 1883)
+   (dampr28 1884) (dampr29 1885) (dampr30 1886) (dampr31 1887)
+   (dampr32 1888) (dampr33 1889) (dampr34 1890) (dampr35 1891)
+   (dampr36 1892) (dampr37 1893) (dampr38 1894) (dampr39 1895)
+   (dampr40 1896) (dampr41 1897) (dampr42 1898) (dampr43 1899)
+   (dampr44 1900) (dampr45 1901) (dampr46 1902) (dampr47 1903)
+   (dampr48 1904) (dampr49 1905) (dampr50 1906) (dampr51 1907)
+   (dampr52 1908) (dampr53 1909) (dampr54 1910) (dampr55 1911)
+   (dampr56 1912) (dampr57 1913) (dampr58 1914) (dampr59 1915)
+   (dampr60 1916) (dampr61 1917) (dampr62 1918) (dampr63 1919)
+
+   (amcr    1920) (stbar   1921) (mmcr    1922)
+   (iamvr1  1925) (damvr1  1927)
+   (cxnr    1936) (ttbr    1937) (tplr    1938) (tppr    1939)
+   (tpxr    1940)
+   (timerh  1952) (timerl  1953) (timerd  1954)
+   (dcr     2048) (brr     2049) (nmar    2050) (btbr    2051)
+
+   (ibar0   2052) (ibar1   2053) (ibar2   2054) (ibar3   2055)
+   (dbar0   2056) (dbar1   2057) (dbar2   2058) (dbar3   2059)
+
+   (dbdr00  2060) (dbdr01  2061) (dbdr02  2062) (dbdr03  2063)
+   (dbdr10  2064) (dbdr11  2065) (dbdr12  2066) (dbdr13  2067)
+   (dbdr20  2068) (dbdr21  2069) (dbdr22  2070) (dbdr23  2071)
+   (dbdr30  2072) (dbdr31  2073) (dbdr32  2074) (dbdr33  2075)
+
+   (dbmr00  2076) (dbmr01  2077) (dbmr02  2078) (dbmr03  2079)
+   (dbmr10  2080) (dbmr11  2081) (dbmr12  2082) (dbmr13  2083)
+   (dbmr20  2084) (dbmr21  2085) (dbmr22  2086) (dbmr23  2087)
+   (dbmr30  2088) (dbmr31  2089) (dbmr32  2090) (dbmr33  2091)
+
+   (cpcfr   2304) (cpcr    2305) (cpsr    2306) (cptr    2307)
+   (cphsr0  2308) (cphsr1  2309) (cpesr0  2320) (cpesr1  2321)
+   (cpemr0  2322) (cpemr1  2323) 
+
+   (iperr0  2324) (iperr1  2325) (ipjsr   2326) (ipjrr   2327)
+   (ipcsr0  2336) (ipcsr1  2337) (ipcwer0 2338) (ipcwer1 2339)
+   (ipcwr   2340)
+
+   (mbhsr   2352) (mbssr   2353) (mbrsr   2354) (mbsdr   2355)
+   (mbrdr   2356) (mbsmr   2357) (mbstr0  2359) (mbstr1  2360)
+
+   (slpr    2368) (sldr    2369) (slhsr   2370) (sltr    2371)
+   (slwr    2372)
+
+   (ihsr8   3848) (ihsr9   3849) (ihsr10  3850)
+  )
+)
+
+(define-hardware
+  (name h-spr)
+  (comment "special purpose registers")
+  (attrs PROFILE)
+  (type register UWI (4096))
+  (indices extern-keyword spr-names)
+  (get (index) (c-call UWI "@cpu@_h_spr_get_handler" index))
+  (set (index newval) (c-call VOID "@cpu@_h_spr_set_handler" index newval))
+)
+
+(define-pmacro (spr-pcsr)  (reg h-spr   1))
+(define-pmacro (spr-bpcsr) (reg h-spr   2))
+(define-pmacro (spr-lr)    (reg h-spr 272))
+(define-pmacro (spr-lcr)   (reg h-spr 273))
+(define-pmacro (spr-iacc0h) (reg h-spr 280))
+(define-pmacro (spr-iacc0l) (reg h-spr 281))
+(define-pmacro (spr-sr0)   (reg h-spr 768))
+(define-pmacro (spr-sr1)   (reg h-spr 769))
+(define-pmacro (spr-sr2)   (reg h-spr 770))
+(define-pmacro (spr-sr3)   (reg h-spr 771))
+
+; Accumulator guard. Actually a subset of the SPR registers, but those SPRs
+; are read-only in most insns. This hardware element is used by those insns
+; which have direct access (mwtaccg, mrdaccg).
+(define-keyword
+  (name accg-names)
+  (print-name h-accg)
+  (prefix "")
+  (values
+   (accg0   0)(accg1   1)(accg2   2)(accg3   3)
+   (accg4   4)(accg5   5)(accg6   6)(accg7   7)
+   (accg8   8)(accg9   9)(accg10 10)(accg11 11)
+   (accg12 12)(accg13 13)(accg14 14)(accg15 15)
+   (accg16 16)(accg17 17)(accg18 18)(accg19 19)
+   (accg20 20)(accg21 21)(accg22 22)(accg23 23)
+   (accg24 24)(accg25 25)(accg26 26)(accg27 27)
+   (accg28 28)(accg29 29)(accg30 30)(accg31 31)
+   (accg32 32)(accg33 33)(accg34 34)(accg35 35)
+   (accg36 36)(accg37 37)(accg38 38)(accg39 39)
+   (accg40 40)(accg41 41)(accg42 42)(accg43 43)
+   (accg44 44)(accg45 45)(accg46 46)(accg47 47)
+   (accg48 48)(accg49 49)(accg50 50)(accg51 51)
+   (accg52 52)(accg53 53)(accg54 54)(accg55 55)
+   (accg56 56)(accg57 57)(accg58 58)(accg59 59)
+   (accg60 60)(accg61 61)(accg62 62)(accg63 63)
+  )
+)
+
+(define-hardware
+  (name h-accg)
+  (comment "accumulator guard")
+  (attrs PROFILE VIRTUAL)
+  (type register UWI (64))
+  (indices extern-keyword accg-names)
+  (get (index)
+       (and (reg h-spr (add index 1472)) #xff))
+  (set (index newval)
+       (set (raw-reg UWI h-spr (add index 1472)) (and newval #xff)))
+)
+
+; 40 bit accumulator. Composed of ACCG and ACC registers concatenated, but
+; referenced more often as the composed 40 bits.
+(define-keyword
+  (name acc-names)
+  (print-name h-acc40)
+  (prefix "")
+  (values
+(acc0   0)(acc1   1)(acc2   2)(acc3   3)(acc4   4)(acc5   5)(acc6   6)(acc7   7)
+(acc8   8)(acc9   9)(acc10 10)(acc11 11)(acc12 12)(acc13 13)(acc14 14)(acc15 15)
+(acc16 16)(acc17 17)(acc18 18)(acc19 19)(acc20 20)(acc21 21)(acc22 22)(acc23 23)
+(acc24 24)(acc25 25)(acc26 26)(acc27 27)(acc28 28)(acc29 29)(acc30 30)(acc31 31)
+(acc32 32)(acc33 33)(acc34 34)(acc35 35)(acc36 36)(acc37 37)(acc38 38)(acc39 39)
+(acc40 40)(acc41 41)(acc42 42)(acc43 43)(acc44 44)(acc45 45)(acc46 46)(acc47 47)
+(acc48 48)(acc49 49)(acc50 50)(acc51 51)(acc52 52)(acc53 53)(acc54 54)(acc55 55)
+(acc56 56)(acc57 57)(acc58 58)(acc59 59)(acc60 60)(acc61 61)(acc62 62)(acc63 63)
+  )
+)
+
+(define-hardware
+  (name h-acc40S)
+  (comment "40 bit signed accumulator")
+  (attrs PROFILE VIRTUAL)
+  (type register DI (64))
+  (indices extern-keyword acc-names)
+  ; The accumlator is made up of two 32 bit registers, accgi/acci.
+  ; We want to extract this as a combined 40 signed bits
+  (get (index)
+       (or DI
+          (sll  DI (ext DI (trunc QI (reg h-spr (add index 1472))))
+                32)
+          (zext DI (reg h-spr (add index 1408)))))
+  ; Bits 40-63 are not written. raw-reg is used to bypass read-only restrictions
+  ; on ACC and ACCG registers
+  (set (index newval)
+       (sequence ()
+                (c-call VOID "frv_check_spr_write_access" (add index 1408))
+                (set (raw-reg UWI h-spr
+                              (add index 1472)) (and (srl newval 32) #xff))
+                (set (raw-reg UWI h-spr
+                              (add index 1408)) (trunc USI newval))))
+)
+
+(define-hardware
+  (name h-acc40U)
+  (comment "40 bit unsigned accumulator")
+  (attrs PROFILE VIRTUAL)
+  (type register UDI (64))
+  (indices extern-keyword acc-names)
+  ; The accumlator is made up of two 32 bit registers, accgi/acci.
+  ; We want to extract this as a combined 40 unsigned bits
+  (get (index)
+       (or DI
+          (sll  DI (zext DI (reg h-spr (add index 1472))) 32)
+          (zext DI (reg h-spr (add index 1408)))))
+  ; Bits 40-63 are not written. raw-reg is used to bypass read-only restrictions
+  ; on ACC and ACCG registers
+  (set (index newval)
+       (sequence ()
+                (c-call VOID "frv_check_spr_write_access" (add index 1408))
+                (set (raw-reg UWI h-spr
+                              (add index 1472)) (and (srl newval 32) #xff))
+                (set (raw-reg UWI h-spr
+                              (add index 1408)) (trunc USI newval))))
+)
+; 64-bit signed accumulator.  Composed of iacc0h and iacc0l registers
+; concatenated, but referenced more often as the composed 64 bits.
+(define-keyword
+  ; This is totally hokey -- I have to have an index!
+  (name iacc0-names)
+  (print-name h-iacc0)
+  (prefix "")
+  (values (iacc0 0))
+)
+
+(define-hardware
+  (name h-iacc0)
+  (comment "64 bit signed accumulator")
+  (attrs PROFILE VIRTUAL (MACH fr400,fr450))
+  (type register DI (1))
+  (indices extern-keyword iacc0-names)
+  ; The single 64-bit integer accumulator is made up of two 32 bit
+  ; registers, iacc0h and iacc0l.  We want to extract this as a
+  ; combined 64 signed bits.
+  (get (idx) (or DI (sll DI (ext DI (spr-iacc0h)) 32) (zext DI (spr-iacc0l))))
+  (set (idx newval)
+       (sequence ()
+                (set (spr-iacc0h) (trunc SI (srl newval 32)))
+                (set (spr-iacc0l) (trunc SI newval))))
+)
+
+; Integer condition code registers (CCR)
+;
+; The individual sub registers bits of the CCR are referenced more often than
+; the entire register so set them directly. We can assemble the
+; entire register when necessary.
+;
+(define-keyword
+  (name iccr-names)
+  (print-name h-iccr)
+  (prefix "")
+  (values (icc0 0) (icc1 1) (icc2 2) (icc3 3))
+)
+
+(define-hardware
+  (name h-iccr)
+  (comment "Integer condition code registers")
+  (attrs PROFILE)
+  (type register UQI (4))
+  (indices extern-keyword iccr-names)
+)
+
+; Floating point condition code registers (CCR)
+;
+; The individual sub registers bits of the CCR are referenced more often than
+; the entire register so set them directly. We can assemble the
+; entire register when necessary.
+;
+(define-keyword
+  (name fccr-names)
+  (print-name h-fccr)
+  (prefix "")
+  (values (fcc0 0) (fcc1 1) (fcc2 2) (fcc3 3))
+)
+
+(define-hardware
+  (name h-fccr)
+  (comment "Floating point condition code registers")
+  (attrs PROFILE)
+  (type register UQI (4))
+  (indices extern-keyword fccr-names)
+)
+
+; C condition code registers (CCCR)
+;
+(define-keyword
+  (name cccr-names)
+  (print-name h-cccr)
+  (prefix "")
+  (values (cc0 0) (cc1 1) (cc2 2) (cc3 3) (cc4 4) (cc5 5) (cc6 6) (cc7 7))
+)
+
+(define-hardware
+  (name h-cccr)
+  (comment "Condition code registers")
+  (attrs PROFILE)
+  (type register UQI (8))
+  (indices extern-keyword cccr-names)
+)
+\f
+; Dummy hardware used to define packing bit on insns
+;
+(define-hardware
+  (name h-pack)
+  (comment "Packing bit dummy hardware")
+  (type immediate (UINT 1))
+  (values keyword "" (("" 1) (".p" 0) (".P" 0)))
+)
+; Dummy hardware used to define hint field for branches always taken
+;
+(define-hardware
+  (name h-hint-taken)
+  (comment "Branch taken hint dummy hardware")
+  (type immediate (UINT 1))
+  ; The order of these is important. We want '2' to get written by default,
+  ; but we also want the docoder/disassembler to allow the values '0', '1' and
+  ; '3'.
+  (values keyword "" (("" 2) ("" 0) ("" 1) ("" 3)))
+)
+; Dummy hardware used to define hint field for branches never taken
+;
+(define-hardware
+  (name h-hint-not-taken)
+  (comment "Branch not taken hint dummy hardware")
+  (type immediate (UINT 1))
+  ; The order of these is important. We want '0' to get written by default,
+  ; but we also want the docoder/disassembler to allow the values '1', '2' and
+  ; '3'.
+  (values keyword "" (("" 0) ("" 1) ("" 2) ("" 3)))
+)
+\f
+; Instruction Operands.
+; These entries provide a layer between the assembler and the raw hardware
+; description, and are used to refer to hardware elements in the semantic
+; code.  Usually there's a bit of over-specification, but in more complicated
+; instruction sets there isn't.
+
+; FRV specific operand attributes:
+
+(define-attr
+  (for operand)
+  (type boolean)
+  (name HASH-PREFIX)
+  (comment "immediates have an optional '#' prefix")
+)
+
+; ??? Convention says this should be o-sr, but then the insn definitions
+; should refer to o-sr which is clumsy.  The "o-" could be implicit, but
+; then it should be implicit for all the symbols here, but then there would
+; be confusion between (f-)simm8 and (h-)simm8.
+; So for now the rule is exactly as it appears here.
+
+; dnmop: define-normal-mode-operand: temporary, pending potential removal
+; of modes from h/w.
+(define-pmacro (dnmop xname xcomment xattrs xtype xindex xmode)
+  (define-operand
+    (name xname)
+    (comment xcomment)
+    (.splice attrs (.unsplice xattrs))
+    (type xtype)
+    (index xindex)
+    (mode xmode)
+    )
+)
+
+; dnpmop: define-normal-parsed-mode-operand: Normal mode operand with parse handler
+(define-pmacro (dnpmop xname xcomment xattrs xtype xindex xmode xparse)
+  (define-operand
+    (name xname)
+    (comment xcomment)
+    (.splice attrs (.unsplice xattrs))
+    (type xtype)
+    (index xindex)
+    (mode xmode)
+    (handlers (parse xparse))
+    )
+)
+
+(dnop  pack "packing bit" () h-pack f-pack)
+
+(dnmop GRi        "source register 1"      () h-gr        f-GRi  SI)
+(dnmop GRj        "source register 2"      () h-gr        f-GRj  SI)
+(dnmop GRk        "destination register"   () h-gr        f-GRk  SI)
+(dnmop GRkhi      "destination register"   () h-gr_hi     f-GRk  UHI)
+(dnmop GRklo      "destination register"   () h-gr_lo     f-GRk  UHI)
+(dnpmop GRdoublek "destination register"   () h-gr_double f-GRk  DI "even_register")
+(dnmop ACC40Si    "signed accumulator"     () h-acc40S    f-ACC40Si DI)
+(dnmop ACC40Ui    "unsigned accumulator"   () h-acc40U    f-ACC40Ui UDI)
+(dnmop ACC40Sk    "target accumulator"     () h-acc40S    f-ACC40Sk DI)
+(dnmop ACC40Uk    "target accumulator"     () h-acc40U    f-ACC40Uk UDI)
+(dnmop ACCGi      "source register"        () h-accg      f-ACCGi   UWI)
+(dnmop ACCGk      "target register"        () h-accg      f-ACCGk   UWI)
+
+(dnmop CPRi       "source register"        ((MACH frv)) h-cpr        f-CPRi SI)
+(dnmop CPRj       "source register"        ((MACH frv)) h-cpr        f-CPRj SI)
+(dnmop CPRk       "destination register"   ((MACH frv)) h-cpr        f-CPRk SI)
+(dnpmop CPRdoublek "destination register"  ((MACH frv)) h-cpr_double f-CPRk DI "even_register")
+
+; floating point operands
+(dnmop FRinti    "source register 1"      () h-fr_int    f-FRi SI)
+(dnmop FRintj    "source register 2"      () h-fr_int    f-FRj SI)
+(dnmop FRintk    "target register"        () h-fr_int    f-FRk SI)
+(dnmop FRi       "source register 1"      () h-fr        f-FRi SF)
+(dnmop FRj       "source register 2"      () h-fr        f-FRj SF)
+(dnmop FRk       "destination register"   () h-fr        f-FRk SF)
+(dnmop FRkhi     "destination register"   () h-fr_hi     f-FRk UHI)
+(dnmop FRklo     "destination register"   () h-fr_lo     f-FRk UHI)
+(dnpmop FRdoublei "source register 1"     () h-fr_double f-FRi DF "even_register")
+(dnpmop FRdoublej "source register 2"     () h-fr_double f-FRj DF "even_register")
+(dnpmop FRdoublek "target register"       () h-fr_double f-FRk DF "even_register")
+
+(dnop CRi       "source register 1"       () h-cccr f-CRi)
+(dnop CRj       "source register 2"       () h-cccr f-CRj)
+(dnop CRj_int   "destination register"    () h-cccr f-CRj_int)
+(dnop CRj_float "destination register"    () h-cccr f-CRj_float)
+(dnop CRk       "destination register"    () h-cccr f-CRk)
+(dnop CCi       "condition   register"    () h-cccr f-CCi)
+
+(dnop ICCi_1  "condition   register"      () h-iccr f-ICCi_1)
+(dnop ICCi_2  "condition   register"      () h-iccr f-ICCi_2)
+(dnop ICCi_3  "condition   register"      () h-iccr f-ICCi_3)
+(dnop FCCi_1  "condition   register"      () h-fccr f-FCCi_1)
+(dnop FCCi_2  "condition   register"      () h-fccr f-FCCi_2)
+(dnop FCCi_3  "condition   register"      () h-fccr f-FCCi_3)
+(dnop FCCk    "condition   register"      () h-fccr f-FCCk)
+
+(dnop eir     "exception insn reg"        () h-uint f-eir)
+(dnop s10     "10 bit signed immediate"   (HASH-PREFIX) h-sint f-s10)
+(dnop u16     "16 bit unsigned immediate" (HASH-PREFIX) h-uint f-u16)
+(dnop s16     "16 bit signed   immediate" (HASH-PREFIX) h-sint f-s16)
+(dnop s6      "6  bit signed   immediate" (HASH-PREFIX) h-sint f-s6)
+(dnop s6_1    "6  bit signed   immediate" (HASH-PREFIX) h-sint f-s6_1)
+(dnop u6      "6  bit unsigned immediate" (HASH-PREFIX) h-uint f-u6)
+(dnop s5      "5  bit signed   immediate" (HASH-PREFIX) h-sint f-s5)
+(dnop cond    "conditional arithmetic"    (HASH-PREFIX) h-uint f-cond)
+(dnop ccond   "lr branch condition"       (HASH-PREFIX) h-uint f-ccond)
+(dnop hint    "2 bit branch predictor"    (HASH-PREFIX) h-uint f-hint)
+(dnop hint_taken "2 bit branch predictor"     () h-hint-taken     f-hint)
+(dnop hint_not_taken "2 bit branch predictor" () h-hint-not-taken f-hint)
+
+(dnop LI      "link indicator"            () h-uint f-LI)
+(dnop lock    "cache lock indicator"      (HASH-PREFIX) h-uint f-lock)
+(dnop debug   "debug mode indicator"      (HASH-PREFIX) h-uint f-debug)
+(dnop ae      "all entries indicator"     (HASH-PREFIX) h-uint f-ae)
+
+(dnop label16  "18 bit pc relative address" () h-iaddr f-label16)
+
+(dnop LRAE "Load Real Address E flag" () h-uint f-LRAE)
+(dnop LRAD "Load Real Address D flag" () h-uint f-LRAD)
+(dnop LRAS "Load Real Address S flag" () h-uint f-LRAS)
+
+(dnop TLBPRopx "TLB Probe operation number" () h-uint f-TLBPRopx)
+(dnop TLBPRL   "TLB Probe L flag"           () h-uint f-TLBPRL)
+
+(define-operand
+  (name A0)
+  (comment "A==0 operand of mclracc")
+  (attrs)
+  (type h-uint)
+  (index f-A)
+  (mode USI)
+  (handlers (parse "A0"))
+)
+
+(define-operand
+  (name A1)
+  (comment "A==1 operand of mclracc")
+  (attrs)
+  (type h-uint)
+  (index f-A)
+  (mode USI)
+  (handlers (parse "A1"))
+)
+
+(define-operand
+  (name FRintieven)
+  (comment "(even) source register 1")
+  (attrs)
+  (type h-fr_int)
+  (index f-FRi)
+  (mode SI)
+  (handlers (parse "even_register"))
+)
+
+(define-operand
+  (name FRintjeven)
+  (comment "(even) source register 2")
+  (attrs)
+  (type h-fr_int)
+  (index f-FRj)
+  (mode SI)
+  (handlers (parse "even_register"))
+)
+
+(define-operand
+  (name FRintkeven)
+  (comment "(even) target register")
+  (attrs)
+  (type h-fr_int)
+  (index f-FRk)
+  (mode SI)
+  (handlers (parse "even_register"))
+)
+
+(define-operand
+  (name d12)
+  (comment "12 bit signed immediate")
+  (attrs)
+  (type h-sint)
+  (index f-d12)
+  (handlers (parse "d12"))
+)
+
+(define-operand
+  (name s12)
+  (comment "12 bit signed immediate")
+  (attrs HASH-PREFIX)
+  (type h-sint)
+  (index f-d12)
+  (handlers (parse "s12"))
+)
+
+(define-operand
+  (name u12)
+  (comment "12 bit signed immediate")
+  (attrs HASH-PREFIX)
+  (type h-sint)
+  (index f-u12)
+  (handlers (parse "u12"))
+)
+
+(define-operand 
+  (name spr)
+  (comment "special purpose register")
+  (attrs)
+  (type  h-spr)
+  (index f-spr)
+  (handlers (parse "spr") (print "spr"))
+)
+
+(define-operand
+  (name ulo16)
+  (comment "16 bit unsigned immediate, for #lo()")
+  (attrs)
+  (type h-uint)
+  (index f-u16)
+  (handlers (parse "ulo16") (print "lo"))
+)
+
+(define-operand
+  (name slo16)
+  (comment "16 bit unsigned immediate, for #lo()")
+  (attrs)
+  (type h-sint)
+  (index f-s16)
+  (handlers (parse "uslo16") (print "lo"))
+)
+
+(define-operand
+  (name uhi16)
+  (comment "16 bit unsigned immediate, for #hi()")
+  (attrs)
+  (type h-uint)
+  (index f-u16)
+  (handlers (parse "uhi16") (print "hi"))
+)
+
+(define-operand
+  (name label24)
+  (comment "26 bit pc relative address")
+  (attrs)
+  (type h-iaddr)
+  (index f-label24)
+  (mode SI)
+  (handlers (parse "call_label"))
+)
+
+; operands representing hardware
+;
+(dnop psr_esr "PSR.ESR bit" (SEM-ONLY) h-psr_esr f-nil)
+(dnop psr_s   "PSR.S   bit" (SEM-ONLY) h-psr_s   f-nil)
+(dnop psr_ps  "PSR.PS  bit" (SEM-ONLY) h-psr_ps  f-nil)
+(dnop psr_et  "PSR.ET  bit" (SEM-ONLY) h-psr_et  f-nil)
+
+(dnop bpsr_bs  "BPSR.BS  bit" (SEM-ONLY) h-bpsr_bs  f-nil)
+(dnop bpsr_bet "BPSR.BET bit" (SEM-ONLY) h-bpsr_bet f-nil)
+
+(dnop tbr_tba "TBR.TBA" (SEM-ONLY) h-tbr_tba f-nil)
+(dnop tbr_tt  "TBR.TT"  (SEM-ONLY) h-tbr_tt  f-nil)
+
+; Null operands
+;
+(define-pmacro (ICCi_1-null)  (f-ICCi_1-null 0))
+(define-pmacro (ICCi_2-null)  (f-ICCi_2-null 0))
+(define-pmacro (ICCi_3-null)  (f-ICCi_3-null 0))
+(define-pmacro (FCCi_1-null)  (f-FCCi_1-null 0))
+(define-pmacro (FCCi_2-null)  (f-FCCi_2-null 0))
+(define-pmacro (FCCi_3-null)  (f-FCCi_3-null 0))
+(define-pmacro (rs-null)      (f-rs-null     0))
+(define-pmacro (GRi-null)     (f-GRi-null    0))
+(define-pmacro (GRj-null)     (f-GRj-null    0))
+(define-pmacro (GRk-null)     (f-GRk-null    0))
+(define-pmacro (FRi-null)     (f-FRi-null    0))
+(define-pmacro (FRj-null)     (f-FRj-null    0))
+(define-pmacro (ACCj-null)    (f-ACCj-null   0))
+(define-pmacro (rd-null)      (f-rd-null     0))
+(define-pmacro (cond-null)    (f-cond-null   0))
+(define-pmacro (ccond-null)   (f-ccond-null  0))
+(define-pmacro (s12-null)     (f-s12-null    0))
+(define-pmacro (label16-null) (f-label16-null 0))
+(define-pmacro (misc-null-1)  (f-misc-null-1 0))
+(define-pmacro (misc-null-2)  (f-misc-null-2 0))
+(define-pmacro (misc-null-3)  (f-misc-null-3 0))
+(define-pmacro (misc-null-4)  (f-misc-null-4 0))
+(define-pmacro (misc-null-5)  (f-misc-null-5 0))
+(define-pmacro (misc-null-6)  (f-misc-null-6 0))
+(define-pmacro (misc-null-7)  (f-misc-null-7 0))
+(define-pmacro (misc-null-8)  (f-misc-null-8 0))
+(define-pmacro (misc-null-9)  (f-misc-null-9 0))
+(define-pmacro (misc-null-10) (f-misc-null-10 0))
+(define-pmacro (misc-null-11) (f-misc-null-11 0))
+
+(define-pmacro (LRA-null)     (f-LRA-null 0))
+(define-pmacro (TLBPR-null)   (f-TLBPR-null 0))
+
+(define-pmacro (LI-on)       (f-LI-on  1))
+(define-pmacro (LI-off)      (f-LI-off 0))
+\f
+; Instruction definitions.
+;
+; Notes:
+; - dni is short for "define-normal-instruction"
+; - Macros are used to represent each insn format. These should be used as much
+;   as possible unless an insn has exceptional behaviour
+;
+
+; Commonly used Macros
+;
+; Specific registers
+;
+
+; Integer condition code manipulation
+;
+(define-pmacro (set-z-and-n icc x)
+  (if (eq x 0)
+      (set icc (or (and icc #x7) #x4))
+      (if (lt x 0)
+         (set icc (or (and icc #xb) #x8))
+         (set icc (and icc #x3))))
+)
+
+(define-pmacro (set-n icc val)
+  (if (eq val 0)
+      (set icc (and icc #x7))
+      (set icc (or  icc #x8)))
+)
+
+(define-pmacro (set-z icc val)
+  (if (eq val 0)
+      (set icc (and icc #xb))
+      (set icc (or  icc #x4)))
+)
+
+(define-pmacro (set-v icc val)
+  (if (eq val 0)
+      (set icc (and icc #xd))
+      (set icc (or  icc #x2)))
+)
+
+(define-pmacro (set-c icc val)
+  (if (eq val 0)
+      (set icc (and icc #xe))
+      (set icc (or  icc #x1)))
+)
+
+(define-pmacro (nbit icc)
+  (trunc BI (srl (and icc #x8) 3))
+)
+
+(define-pmacro (zbit icc)
+  (trunc BI (srl (and icc #x4) 2))
+)
+
+(define-pmacro (vbit icc)
+  (trunc BI (srl (and icc #x2) 1))
+)
+
+(define-pmacro (cbit icc)
+  (trunc BI (and icc #x1))
+)
+
+(define-pmacro (ebit icc)
+  (trunc BI (srl (and icc #x8) 3))
+)
+
+(define-pmacro (lbit icc)
+  (trunc BI (srl (and icc #x4) 2))
+)
+
+(define-pmacro (gbit icc)
+  (trunc BI (srl (and icc #x2) 1))
+)
+
+(define-pmacro (ubit icc)
+  (trunc BI (and icc #x1))
+)
+
+; FRV insns
+;
+;
+; Format: INT, Logic, Shift r-r
+;
+(define-pmacro (int-logic-r-r name operation op ope comment)
+  (dni name
+       (comment)
+       ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+       (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+       (.str name "$pack $GRi,$GRj,$GRk")
+       (+ pack GRk op GRi (ICCi_1-null) ope GRj)
+       (set GRk (operation GRi GRj))
+       ((fr400 (unit u-integer)) (fr450 (unit u-integer))
+       (fr500 (unit u-integer)) (fr550 (unit u-integer)))
+  )
+)
+
+(int-logic-r-r add  add   OP_00 OPE2_00 "add reg/reg")
+(int-logic-r-r sub  sub   OP_00 OPE2_04 "sub reg/reg")
+(int-logic-r-r and  and   OP_01 OPE2_00 "and reg/reg")
+(int-logic-r-r or   or    OP_01 OPE2_02 "or  reg/reg")
+(int-logic-r-r xor  xor   OP_01 OPE2_04 "xor reg/reg")
+
+(dni not
+     ("not")
+     ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+      (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+     ("not$pack $GRj,$GRk")
+     (+ pack GRk OP_01 (rs-null) (ICCi_1-null) OPE2_06 GRj)
+     (set GRk (inv GRj))
+     ((fr400 (unit u-integer)) (fr450 (unit u-integer))
+      (fr500 (unit u-integer)) (fr550 (unit u-integer)))
+)
+
+(dni sdiv
+     "signed division"
+     ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
+      (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+     "sdiv$pack $GRi,$GRj,$GRk"
+     (+ pack GRk OP_00 GRi (ICCi_1-null) OPE2_0E GRj)
+     (sequence ()
+              (c-call VOID "@cpu@_signed_integer_divide"
+                      GRi GRj (index-of GRk) 0)
+              (clobber GRk))
+     ((fr400 (unit u-idiv)) (fr450 (unit u-idiv))
+      (fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
+)
+
+(dni nsdiv
+     "non excepting signed division"
+     ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) NON-EXCEPTING
+      (MACH simple,tomcat,fr500,fr550,frv))
+     "nsdiv$pack $GRi,$GRj,$GRk"
+     (+ pack GRk OP_01 GRi (ICCi_1-null) OPE2_0E GRj)
+     (sequence ()
+              (c-call VOID "@cpu@_signed_integer_divide"
+                      GRi GRj (index-of GRk) 1)
+              (clobber GRk))
+     ((fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
+)
+
+(dni udiv
+     "unsigned division reg/reg"
+     ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
+      (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+     "udiv$pack $GRi,$GRj,$GRk"
+     (+ pack GRk OP_00 GRi (ICCi_1-null) OPE2_0F GRj)
+     (sequence ()
+              (c-call VOID "@cpu@_unsigned_integer_divide"
+                      GRi GRj (index-of GRk) 0)
+              (clobber GRk))
+     ((fr400 (unit u-idiv)) (fr450 (unit u-idiv))
+      (fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
+)
+
+(dni nudiv
+     "non excepting unsigned division"
+     ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) NON-EXCEPTING
+      (MACH simple,tomcat,fr500,fr550,frv))
+     "nudiv$pack $GRi,$GRj,$GRk"
+     (+ pack GRk OP_01 GRi (ICCi_1-null) OPE2_0F GRj)
+     (sequence ()
+              (c-call VOID "@cpu@_unsigned_integer_divide"
+                      GRi GRj (index-of GRk) 1)
+              (clobber GRk))
+     ((fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
+)
+
+; Multiplication
+;
+(define-pmacro (multiply-r-r name signop op ope comment)
+  (dni name
+       (comment)
+       ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
+       (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+       (.str name "$pack $GRi,$GRj,$GRdoublek")
+       (+ pack GRdoublek op GRi (ICCi_1-null) ope GRj) 
+       (set GRdoublek (mul DI (signop DI GRi) (signop DI GRj)))
+       ((fr400 (unit u-imul)) (fr450 (unit u-imul))
+       (fr500 (unit u-imul)) (fr550 (unit u-imul)))
+  )
+)
+
+(multiply-r-r smul ext  OP_00 OPE2_08 "signed   multiply reg/reg")
+(multiply-r-r umul zext OP_00 OPE2_0A "unsigned multiply reg/reg")
+
+; Multiplication with integer accumulator IACC
+;
+
+(define-pmacro (iacc-set value) 
+  (set (reg h-iacc0 0) value))
+
+(define-pmacro (iacc-add value) 
+  (set (reg h-iacc0 0)
+       (cond DI
+            ((andif (andif (gt value 0) (gt (reg h-iacc0 0) 0))
+                    (lt (sub DI #x7fffffffffffffff value) (reg h-iacc0 0)))
+             ; Positive overflow
+             (const DI #x7fffffffffffffff))
+            ((andif (andif (lt value 0) (lt (reg h-iacc0 0) 0))
+                    (gt (sub DI #x8000000000000000 value) (reg h-iacc0 0)))
+             ; Negative overflow
+             (const DI #x8000000000000000))
+            (else
+             (add DI (reg h-iacc0 0) value))))
+)
+
+(define-pmacro (iacc-sub value) 
+  (set (reg h-iacc0 0)
+       (cond DI
+            ((andif (andif (lt value 0) (gt (reg h-iacc0 0) 0))
+                    (lt (add DI #x7fffffffffffffff value) (reg h-iacc0 0)))
+             ; Positive overflow
+             (const DI #x7fffffffffffffff))
+            ((andif (andif (gt value 0) (lt (reg h-iacc0 0) 0))
+                    (gt (add DI #x8000000000000000 value) (reg h-iacc0 0)))
+             ; Negative overflow
+             (const DI #x8000000000000000))
+            (else
+             (sub DI (reg h-iacc0 0) value))))
+)
+
+(define-pmacro (iacc-multiply-r-r name operation op ope comment)
+  (dni name
+       (comment)
+       ((UNIT IACC) (MACH fr400,fr450)
+       (FR400-MAJOR I-1) (FR450-MAJOR I-1) AUDIO)
+       (.str name "$pack $GRi,$GRj")
+       (+ pack (rd-null) op GRi ope GRj)
+       ((.sym iacc- operation) (mul DI (ext DI GRi) (ext DI GRj)))
+       ((fr400 (unit u-integer)) (fr450 (unit u-integer)))
+  )
+)
+
+(iacc-multiply-r-r smu   set OP_46 OPE1_05 "Signed multiply     reg/reg/iacc")
+(iacc-multiply-r-r smass add OP_46 OPE1_06 "Signed multiply/add reg/reg/iacc")
+(iacc-multiply-r-r smsss sub OP_46 OPE1_07 "Signed multiply/sub reg/reg/iacc")
+
+(define-pmacro (int-shift-r-r name op ope comment)
+  (dni name
+       (comment)
+       ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+       (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+       (.str name "$pack $GRi,$GRj,$GRk")
+       (+ pack GRk op GRi (ICCi_1-null) ope GRj)
+       (set GRk (name GRi (and GRj #x1f)))
+       ((fr400 (unit u-integer)) (fr450 (unit u-integer))
+       (fr500 (unit u-integer)) (fr550 (unit u-integer)))
+  )
+)
+
+(int-shift-r-r sll OP_01 OPE2_08 "shift left  logical reg/reg")
+(int-shift-r-r srl OP_01 OPE2_0A "shift right logical reg/reg")
+(int-shift-r-r sra OP_01 OPE2_0C "shift right arith   reg/reg")
+
+(dni slass
+     "shift left arith reg/reg with saturation"
+     ((UNIT IALL) (MACH fr400,fr450)
+      (FR400-MAJOR I-1) (FR450-MAJOR I-1) AUDIO)
+     "slass$pack $GRi,$GRj,$GRk"
+     (+ pack GRk OP_46 GRi OPE1_02 GRj)
+     (set GRk (c-call SI "@cpu@_shift_left_arith_saturate" GRi GRj))
+     ()
+)
+
+(dni scutss
+     "Integer accumulator cut with saturation"
+     ((UNIT I0) (MACH fr400,fr450)
+      (FR400-MAJOR I-1) (FR450-MAJOR I-1) AUDIO)
+     "scutss$pack $GRj,$GRk"
+     (+ pack GRk OP_46 (rs-null) OPE1_04 GRj)
+     (set GRk (c-call SI "@cpu@_iacc_cut" (reg h-iacc0 0) GRj))
+     ()
+)
+
+(define-pmacro (scan-semantics arg1 arg2 targ)
+  (sequence ((WI tmp1) (WI tmp2))
+           (set tmp1 arg1)
+           (set tmp2 (sra arg2 1))
+           (set targ (c-call WI "@cpu@_scan_result" (xor tmp1 tmp2))))
+)
+
+(dni scan
+     "scan"
+     ((UNIT SCAN) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+      (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+     "scan$pack $GRi,$GRj,$GRk"
+     (+ pack GRk OP_0B GRi (ICCi_1-null) OPE2_00 GRj)
+     (scan-semantics GRi GRj GRk)
+     ((fr400 (unit u-integer)) (fr450 (unit u-integer))
+      (fr500 (unit u-integer)) (fr550 (unit u-integer)))
+)
+
+; Format: conditional INT, Logic, Shift r-r
+;
+(define-pmacro (conditional-int-logic name operation op ope comment)
+  (dni name
+       (comment)
+       ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+       (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
+       (.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond")
+       (+ pack GRk op GRi CCi cond ope GRj)
+       (if (eq CCi (or cond 2))
+          (set GRk (operation GRi GRj)))
+       ((fr400 (unit u-integer)) (fr450 (unit u-integer))
+       (fr500 (unit u-integer)) (fr550 (unit u-integer)))
+  )
+)
+
+(conditional-int-logic cadd  add  OP_58 OPE4_0 "conditional add")
+(conditional-int-logic csub  sub  OP_58 OPE4_1 "conditional sub")
+(conditional-int-logic cand  and  OP_5A OPE4_0 "conditional and")
+(conditional-int-logic cor   or   OP_5A OPE4_1 "conditional or")
+(conditional-int-logic cxor  xor  OP_5A OPE4_2 "conditional xor")
+
+(dni cnot
+     "conditional not"
+     ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+      (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
+     "cnot$pack $GRj,$GRk,$CCi,$cond"
+     (+ pack GRk OP_5A (rs-null) CCi cond OPE4_3 GRj)
+     (if (eq CCi (or cond 2))
+        (set GRk (inv GRj)))
+     ((fr400 (unit u-integer)) (fr450 (unit u-integer))
+      (fr500 (unit u-integer)) (fr550 (unit u-integer)))
+)
+
+(dni csmul
+     "conditional signed multiply"
+     ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
+      (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
+     "csmul$pack $GRi,$GRj,$GRdoublek,$CCi,$cond"
+     (+ pack GRdoublek OP_58 GRi CCi cond OPE4_2 GRj)
+     (if (eq CCi (or cond 2))
+        (set GRdoublek (mul DI (ext DI GRi) (ext DI GRj))))
+     ((fr400 (unit u-imul)) (fr450 (unit u-imul))
+      (fr500 (unit u-imul)) (fr550 (unit u-imul)))
+)
+
+(dni csdiv
+     "conditional signed division"
+     ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
+      (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
+     "csdiv$pack $GRi,$GRj,$GRk,$CCi,$cond"
+     (+ pack GRk OP_58 GRi CCi cond OPE4_3 GRj)
+     (if (eq CCi (or cond 2))
+        (sequence ()
+                  (c-call VOID "@cpu@_signed_integer_divide"
+                          GRi GRj (index-of GRk) 0)
+                  (clobber GRk)))
+     ((fr400 (unit u-idiv)) (fr450 (unit u-idiv))
+      (fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
+)
+
+(dni cudiv
+     "conditional unsigned division"
+     ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
+      (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
+     "cudiv$pack $GRi,$GRj,$GRk,$CCi,$cond"
+     (+ pack GRk OP_59 GRi CCi cond OPE4_3 GRj)
+     (if (eq CCi (or cond 2))
+        (sequence ()
+                  (c-call VOID "@cpu@_unsigned_integer_divide"
+                          GRi GRj (index-of GRk) 0)
+                  (clobber GRk)))
+     ((fr400 (unit u-idiv)) (fr450 (unit u-idiv))
+      (fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
+)
+
+(define-pmacro (conditional-shift name operation op ope comment)
+  (dni name
+       (comment)
+       ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+       (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
+       (.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond")
+       (+ pack GRk op GRi CCi cond ope GRj)
+       (if (eq CCi (or cond 2))
+          (set GRk (operation GRi (and GRj #x1f))))
+       ((fr400 (unit u-integer)) (fr450 (unit u-integer))
+       (fr500 (unit u-integer)) (fr550 (unit u-integer)))
+  )
+)
+
+(conditional-shift csll sll OP_5C OPE4_0 "conditional shift left  logical")
+(conditional-shift csrl srl OP_5C OPE4_1 "conditional shift right logical")
+(conditional-shift csra sra OP_5C OPE4_2 "conditional shift right arith")
+
+(dni cscan
+     "conditional scan"
+     ((UNIT SCAN) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+      (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
+     "cscan$pack $GRi,$GRj,$GRk,$CCi,$cond"
+     (+ pack GRk OP_65 GRi CCi cond OPE4_3 GRj)
+     (if (eq CCi (or cond 2))
+        (scan-semantics GRi GRj GRk))
+     ((fr400 (unit u-integer)) (fr450 (unit u-integer))
+      (fr500 (unit u-integer)) (fr550 (unit u-integer)))
+)
+
+; Format: INT, Logic, Shift, cc r-r
+;
+(define-pmacro (int-arith-cc-semantics operation icc)
+  (sequence ((BI tmp) (QI cc) (SI result))
+           (set cc icc)
+           (set tmp ((.sym operation -oflag) GRi GRj (const 0)))
+           (set-v cc tmp)
+           (set tmp ((.sym operation -cflag) GRi GRj (const 0)))
+           (set-c cc tmp)
+           (set result (operation GRi GRj))
+           (set-z-and-n cc result)
+           (set GRk result)
+           (set icc cc))
+)
+
+(define-pmacro (int-arith-cc-r-r name operation op ope comment)
+  (dni name
+       (comment)
+       ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+       (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+       (.str name "$pack $GRi,$GRj,$GRk,$ICCi_1")
+       (+ pack GRk op GRi ICCi_1 ope GRj)
+       (int-arith-cc-semantics operation ICCi_1)
+       ((fr400 (unit u-integer)) (fr450 (unit u-integer))
+       (fr500 (unit u-integer)) (fr550 (unit u-integer)))
+  )
+)
+
+(int-arith-cc-r-r addcc add OP_00 OPE2_01 "add reg/reg, set icc")
+(int-arith-cc-r-r subcc sub OP_00 OPE2_05 "sub reg/reg, set icc")
+
+(define-pmacro (int-logic-cc-semantics op icc)
+  (sequence ((SI tmp))
+           (set tmp (op GRi GRj))
+           (set GRk tmp)
+           (set-z-and-n icc tmp))
+)
+
+(define-pmacro (int-logic-cc-r-r name op ope comment)
+  (dni (.sym name cc)
+       (comment)
+       ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+       (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+       (.str (.sym name cc) "$pack $GRi,$GRj,$GRk,$ICCi_1")
+       (+ pack GRk op GRi ICCi_1 ope GRj)
+       (int-logic-cc-semantics name ICCi_1)
+       ((fr400 (unit u-integer)) (fr450 (unit u-integer))
+       (fr500 (unit u-integer)) (fr550 (unit u-integer)))
+  )
+)
+
+(int-logic-cc-r-r and OP_01 OPE2_01 "and reg/reg, set icc")
+(int-logic-cc-r-r or  OP_01 OPE2_03 "or  reg/reg, set icc")
+(int-logic-cc-r-r xor OP_01 OPE2_05 "xor reg/reg, set icc")
+
+(define-pmacro (int-shift-cc-semantics op l-r icc)
+  (sequence ((WI shift) (SI tmp) (QI cc))
+           (set shift (and GRj #x1f))
+           (set cc (c-call QI (.str "@cpu@_set_icc_for_shift_" l-r)
+                           GRi shift icc))
+           (set tmp (op GRi shift))
+           (set GRk tmp)
+           (set-z-and-n cc tmp)
+           (set icc cc))
+)
+
+(define-pmacro (int-shift-cc-r-r name l-r op ope comment)
+  (dni (.sym name cc)
+       (comment)
+       ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+       (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+       (.str (.sym name cc) "$pack $GRi,$GRj,$GRk,$ICCi_1")
+       (+ pack GRk op GRi ICCi_1 ope GRj)
+       (int-shift-cc-semantics name l-r ICCi_1)
+       ((fr400 (unit u-integer)) (fr450 (unit u-integer))
+       (fr500 (unit u-integer)) (fr550 (unit u-integer)))
+  )
+)
+
+(int-shift-cc-r-r sll left  OP_01 OPE2_09 "shift left  logical reg/reg,set icc")
+(int-shift-cc-r-r srl right OP_01 OPE2_0B "shift right logical reg/reg,set icc")
+(int-shift-cc-r-r sra right OP_01 OPE2_0D "shift right arith   reg/reg,set icc")
+
+(define-pmacro (multiply-cc-semantics signop arg1 arg2 targ icc)
+  (sequence ((DI tmp) (QI cc))
+           (set cc icc)
+           (set tmp (mul DI (signop DI arg1) (signop DI arg2)))
+           (set-n cc (srl DI tmp 63))
+           (set-z cc (eq tmp 0))
+           (set targ tmp)
+           (set icc cc))
+)
+
+(define-pmacro (multiply-cc-r-r name signop op ope comment)
+  (dni name
+       (comment)
+       ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
+       (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+       (.str name "$pack $GRi,$GRj,$GRdoublek,$ICCi_1")
+       (+ pack GRdoublek op GRi ICCi_1 ope GRj)
+       (multiply-cc-semantics signop GRi GRj GRdoublek ICCi_1)
+       ((fr400 (unit u-imul)) (fr450 (unit u-imul))
+       (fr500 (unit u-imul)) (fr550 (unit u-imul)))
+  )
+)
+
+(multiply-cc-r-r smulcc ext  OP_00 OPE2_09 "signed   multiply reg/reg")
+(multiply-cc-r-r umulcc zext OP_00 OPE2_0B "unsigned multiply reg/reg")
+
+
+; Format: conditional INT, Logic, Shift, cc r-r
+;
+(define-pmacro (conditional-int-arith-cc name operation op ope comment)
+  (dni name
+       (comment)
+       ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+       (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
+       (.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond")
+       (+ pack GRk op GRi CCi cond ope GRj)
+       (if (eq CCi (or cond 2))
+          (int-arith-cc-semantics operation
+                                  (reg h-iccr (and (index-of CCi) 3))))
+       ((fr400 (unit u-integer)) (fr450 (unit u-integer))
+       (fr500 (unit u-integer)) (fr550 (unit u-integer)))
+  )
+)
+
+(conditional-int-arith-cc caddcc add OP_59 OPE4_0 "add, set icc")
+(conditional-int-arith-cc csubcc sub OP_59 OPE4_1 "sub, set icc")
+
+(dni csmulcc
+     "conditional signed multiply and set condition code"
+     ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
+      (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
+     "csmulcc$pack $GRi,$GRj,$GRdoublek,$CCi,$cond"
+     (+ pack GRdoublek OP_59 GRi CCi cond OPE4_2 GRj)
+     (if (eq CCi (or cond 2))
+        (multiply-cc-semantics ext GRi GRj GRdoublek
+                               (reg h-iccr (and (index-of CCi) 3))))
+     ((fr400 (unit u-imul)) (fr450 (unit u-imul))
+      (fr500 (unit u-imul)) (fr550 (unit u-imul)))
+)
+
+(define-pmacro (conditional-int-logic-cc name operation op ope comment)
+  (dni name
+       (comment)
+       ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+       (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
+       (.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond")
+       (+ pack GRk op GRi CCi cond ope GRj)
+       (if (eq CCi (or cond 2))
+          (int-logic-cc-semantics operation
+                                  (reg h-iccr (and (index-of CCi) 3))))
+       ((fr400 (unit u-integer)) (fr450 (unit u-integer))
+       (fr500 (unit u-integer)) (fr550 (unit u-integer)))
+  )
+)
+
+(conditional-int-logic-cc candcc and OP_5B OPE4_0 "conditional and, set icc")
+(conditional-int-logic-cc corcc  or  OP_5B OPE4_1 "conditional or , set icc")
+(conditional-int-logic-cc cxorcc xor OP_5B OPE4_2 "conditional xor, set icc")
+
+(define-pmacro (conditional-int-shift-cc name l-r op ope comment)
+  (dni (.sym c name cc)
+       (comment)
+       ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+       (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
+       (.str (.sym c name cc) "$pack $GRi,$GRj,$GRk,$CCi,$cond")
+       (+ pack GRk op GRi CCi cond ope GRj)
+       (if (eq CCi (or cond 2))
+          (int-shift-cc-semantics name l-r
+                                  (reg h-iccr (and (index-of CCi) 3))))
+       ((fr400 (unit u-integer)) (fr450 (unit u-integer))
+       (fr500 (unit u-integer)) (fr550 (unit u-integer)))
+  )
+)
+
+(conditional-int-shift-cc sll left  OP_5D OPE4_0 "shift left  logical, set icc")
+(conditional-int-shift-cc srl right OP_5D OPE4_1 "shift right logical, set icc")
+(conditional-int-shift-cc sra right OP_5D OPE4_2 "shift right arith  , set icc")
+
+; Add and subtract with carry
+;
+(define-pmacro (int-arith-x-r-r name operation op ope comment)
+  (dni name
+       (comment)
+       ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+       (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+       (.str name "$pack $GRi,$GRj,$GRk,$ICCi_1")
+       (+ pack GRk op GRi ICCi_1 ope GRj)
+       (set GRk ((.sym operation c) GRi GRj (cbit ICCi_1)))
+       ((fr400 (unit u-integer)) (fr450 (unit u-integer))
+       (fr500 (unit u-integer)) (fr550 (unit u-integer)))
+  )
+)
+
+(int-arith-x-r-r addx add OP_00 OPE2_02 "Add reg/reg, with carry")
+(int-arith-x-r-r subx sub OP_00 OPE2_06 "Sub reg/reg, with carry")
+
+(define-pmacro (int-arith-x-cc-r-r name operation op ope comment)
+  (dni name
+       (comment)
+       ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+       (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+       (.str name "$pack $GRi,$GRj,$GRk,$ICCi_1")
+       (+ pack GRk op GRi ICCi_1 ope GRj)
+       (sequence ((WI tmp) (QI cc))
+                (set cc ICCi_1)
+                (set tmp ((.sym operation c) GRi GRj (cbit cc)))
+                (set-v cc ((.sym operation -oflag) GRi GRj (cbit cc)))
+                (set-c cc ((.sym operation -cflag) GRi GRj (cbit cc)))
+                (set-z-and-n cc tmp)
+                (set GRk tmp)
+                (set ICCi_1 cc))
+       ((fr400 (unit u-integer)) (fr450 (unit u-integer))
+       (fr500 (unit u-integer)) (fr550 (unit u-integer)))
+  )
+)
+
+(int-arith-x-cc-r-r addxcc add OP_00 OPE2_03 "Add reg/reg, use/set carry")
+(int-arith-x-cc-r-r subxcc sub OP_00 OPE2_07 "Sub reg/reg, use/set carry")
+; Add and subtract with saturation
+;
+(define-pmacro (int-arith-ss-r-r name operation op ope comment)
+  (dni name
+       (comment)
+       ((UNIT IALL) (MACH fr400,fr450)
+       (FR400-MAJOR I-1) (FR450-MAJOR I-1) AUDIO)
+       (.str name "$pack $GRi,$GRj,$GRk")
+       (+ pack GRk op GRi ope GRj)
+       (sequence ()
+                (set GRk (operation GRi GRj))
+                (if ((.sym operation -oflag) GRi GRj (const 0))
+                                       ; Overflow, saturate.
+                                       ; Sign of result will be
+                                       ; same as sign of first operand.
+                    (set GRk
+                         (cond SI
+                               ((gt GRi 0) (const #x7fffffff))
+                               ((lt GRi 0) (const #x80000000))
+                               (else (const 0)))))
+       )
+       ((fr400 (unit u-integer)) (fr450 (unit u-integer)))
+  )
+)
+
+(int-arith-ss-r-r addss add OP_46 OPE1_00 "add reg/reg, with saturation")
+(int-arith-ss-r-r subss sub OP_46 OPE1_01 "sub reg/reg, with saturation")
+
+; Format: INT, Logic, Shift r-simm
+;
+(define-pmacro (int-logic-r-simm name operation op comment)
+  (dni name
+       (comment)
+       ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+       (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+       (.str name "$pack $GRi,$s12,$GRk")
+       (+ pack GRk op GRi s12)
+       (set GRk (operation GRi s12))
+       ((fr400 (unit u-integer)) (fr450 (unit u-integer))
+       (fr500 (unit u-integer)) (fr550 (unit u-integer)))
+  )
+)
+
+(int-logic-r-simm addi  add   OP_10 "add reg/immed")
+(int-logic-r-simm subi  sub   OP_14 "sub reg/immed")
+(int-logic-r-simm andi  and   OP_20 "and reg/immed")
+(int-logic-r-simm ori   or    OP_22 "or  reg/immed")
+(int-logic-r-simm xori  xor   OP_24 "xor reg/immed")
+
+(dni sdivi
+     "signed division reg/immed"
+     ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
+      (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+     "sdivi$pack $GRi,$s12,$GRk"
+     (+ pack GRk OP_1E GRi s12)
+     (sequence ()
+              (c-call VOID "@cpu@_signed_integer_divide"
+                      GRi s12 (index-of GRk) 0)
+              (clobber GRk))
+     ((fr400 (unit u-idiv)) (fr450 (unit u-idiv))
+      (fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
+)
+
+(dni nsdivi
+     "non excepting signed division reg/immed"
+     ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) NON-EXCEPTING
+      (MACH simple,tomcat,fr500,fr550,frv))
+     "nsdivi$pack $GRi,$s12,$GRk"
+     (+ pack GRk OP_2E GRi s12)
+     (sequence ()
+              (c-call VOID "@cpu@_signed_integer_divide"
+                      GRi s12 (index-of GRk) 1)
+              (clobber GRk))
+     ((fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
+)
+
+(dni udivi
+     "unsigned division reg/immed"
+     ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
+      (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+     "udivi$pack $GRi,$s12,$GRk"
+     (+ pack GRk OP_1F GRi s12)
+     (sequence ()
+              (c-call VOID "@cpu@_unsigned_integer_divide"
+                      GRi s12 (index-of GRk) 0)
+              (clobber GRk))
+     ((fr400 (unit u-idiv)) (fr450 (unit u-idiv))
+      (fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
+)
+
+(dni nudivi
+     "non excepting unsigned division reg/immed"
+     ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) NON-EXCEPTING
+      (MACH simple,tomcat,fr500,fr550,frv))
+     "nudivi$pack $GRi,$s12,$GRk"
+     (+ pack GRk OP_2F GRi s12)
+     (sequence ()
+              (c-call VOID "@cpu@_unsigned_integer_divide"
+                      GRi s12 (index-of GRk) 1)
+              (clobber GRk))
+     ((fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
+)
+
+(define-pmacro (multiply-r-simm name signop op comment)
+  (dni name
+       (comment)
+       ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
+       (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+       (.str name "$pack $GRi,$s12,$GRdoublek")
+       (+ pack GRdoublek op GRi s12)
+       (set GRdoublek (mul DI (signop DI GRi) (signop DI s12)))
+       ((fr400 (unit u-imul)) (fr450 (unit u-imul))
+       (fr500 (unit u-imul)) (fr550 (unit u-imul)))
+  )
+)
+
+(multiply-r-simm smuli ext  OP_18 "signed   multiply reg/immed")
+(multiply-r-simm umuli zext OP_1A "unsigned multiply reg/immed")
+
+(define-pmacro (int-shift-r-simm name op comment)
+  (dni (.sym name i)
+       (comment)
+       ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+       (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+       (.str (.sym name i) "$pack $GRi,$s12,$GRk")
+       (+ pack GRk op GRi s12)
+       (set GRk (name GRi (and s12 #x1f)))
+       ((fr400 (unit u-integer)) (fr450 (unit u-integer))
+       (fr500 (unit u-integer)) (fr550 (unit u-integer)))
+  )
+)
+
+(int-shift-r-simm sll OP_28 "shift left  logical reg/immed")
+(int-shift-r-simm srl OP_2A "shift right logical reg/immed")
+(int-shift-r-simm sra OP_2C "shift right arith   reg/immed")
+
+(dni scani
+     "scan immediate"
+     ((UNIT SCAN) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+      (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+     "scani$pack $GRi,$s12,$GRk"
+     (+ pack GRk OP_47 GRi s12)
+     (scan-semantics GRi s12 GRk)
+     ((fr400 (unit u-integer)) (fr450 (unit u-integer))
+      (fr500 (unit u-integer)) (fr550 (unit u-integer)))
+)
+
+; Format: INT, Logic, Shift cc r-simm
+;
+(define-pmacro (int-arith-cc-r-simm name operation op comment)
+  (dni name
+       (comment)
+       ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+       (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+       (.str name "$pack $GRi,$s10,$GRk,$ICCi_1")
+       (+ pack GRk op GRi ICCi_1 s10)
+       (sequence ((BI tmp) (QI cc) (SI result))
+                (set cc ICCi_1)
+                (set tmp ((.sym operation -oflag) GRi s10 (const 0)))
+                (set-v cc tmp)
+                (set tmp ((.sym operation -cflag) GRi s10 (const 0)))
+                (set-c cc tmp)
+                (set result (operation GRi s10))
+                (set-z-and-n cc result)
+                (set GRk result)
+                (set ICCi_1 cc))
+       ((fr400 (unit u-integer)) (fr450 (unit u-integer))
+       (fr500 (unit u-integer)) (fr550 (unit u-integer)))
+  )
+)
+
+(int-arith-cc-r-simm addicc add OP_11 "add reg/immed, set icc")
+(int-arith-cc-r-simm subicc sub OP_15 "sub reg/immed, set icc")
+
+(define-pmacro (int-logic-cc-r-simm name op comment)
+  (dni (.sym name icc)
+       (comment)
+       ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+       (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+       (.str (.sym name icc) "$pack $GRi,$s10,$GRk,$ICCi_1")
+       (+ pack GRk op GRi ICCi_1 s10)
+       (sequence ((SI tmp))
+                (set tmp (name GRi s10))
+                (set GRk tmp)
+                (set-z-and-n ICCi_1 tmp))
+       ((fr400 (unit u-integer)) (fr450 (unit u-integer))
+       (fr500 (unit u-integer)) (fr550 (unit u-integer)))
+  )
+)
+
+(int-logic-cc-r-simm and  OP_21 "and reg/immed, set icc")
+(int-logic-cc-r-simm or   OP_23 "or  reg/immed, set icc")
+(int-logic-cc-r-simm xor  OP_25 "xor reg/immed, set icc")
+
+(define-pmacro (multiply-cc-r-simm name signop op comment)
+  (dni name
+       (comment)
+       ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
+       (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+       (.str name "$pack $GRi,$s10,$GRdoublek,$ICCi_1")
+       (+ pack GRdoublek op GRi ICCi_1 s10)
+       (multiply-cc-semantics signop GRi s10 GRdoublek ICCi_1)
+       ((fr400 (unit u-imul)) (fr450 (unit u-imul))
+       (fr500 (unit u-imul)) (fr550 (unit u-imul)))
+  )
+)
+
+(multiply-cc-r-simm smulicc ext  OP_19 "signed   multiply reg/immed")
+(multiply-cc-r-simm umulicc zext OP_1B "unsigned multiply reg/immed")
+
+(define-pmacro (int-shift-cc-r-simm name l-r op comment)
+  (dni (.sym name icc)
+       (comment)
+       ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+       (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+       (.str (.sym name icc) "$pack $GRi,$s10,$GRk,$ICCi_1")
+       (+ pack GRk op GRi ICCi_1 s10)
+       (sequence ((WI shift) (SI tmp) (QI cc))
+                (set shift (and s10 #x1f))
+                (set cc (c-call QI (.str "@cpu@_set_icc_for_shift_" l-r)
+                                GRi shift ICCi_1))
+                (set tmp (name GRi shift))
+                (set GRk tmp)
+                (set-z-and-n cc tmp)
+                (set ICCi_1 cc))
+       ((fr400 (unit u-integer)) (fr450 (unit u-integer))
+       (fr500 (unit u-integer)) (fr550 (unit u-integer)))
+  )
+)
+
+(int-shift-cc-r-simm sll left  OP_29 "shift left  logical reg/immed, set icc")
+(int-shift-cc-r-simm srl right OP_2B "shift right logical reg/immed, set icc")
+(int-shift-cc-r-simm sra right OP_2D "shift right arith   reg/immed, set icc")
+
+(define-pmacro (int-arith-x-r-simm name operation op comment)
+  (dni name
+       (comment)
+       ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+       (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+       (.str name "$pack $GRi,$s10,$GRk,$ICCi_1")
+       (+ pack GRk op GRi ICCi_1 s10)
+       (set GRk ((.sym operation c) GRi s10 (cbit ICCi_1)))
+       ((fr400 (unit u-integer)) (fr450 (unit u-integer))
+       (fr500 (unit u-integer)) (fr550 (unit u-integer)))
+  )
+)
+
+(int-arith-x-r-simm addxi add OP_12 "Add reg/immed, with carry")
+(int-arith-x-r-simm subxi sub OP_16 "Sub reg/immed, with carry")
+
+(define-pmacro (int-arith-x-cc-r-simm name operation op comment)
+  (dni name
+       (comment)
+       ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+       (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+       (.str name "$pack $GRi,$s10,$GRk,$ICCi_1")
+       (+ pack GRk op GRi ICCi_1 s10)
+       (sequence ((WI tmp) (QI cc))
+                (set cc ICCi_1)
+                (set tmp ((.sym operation c) GRi s10 (cbit cc)))
+                (set-v cc ((.sym operation -oflag) GRi s10 (cbit cc)))
+                (set-c cc ((.sym operation -cflag) GRi s10 (cbit cc)))
+                (set-z-and-n cc tmp)
+                (set GRk tmp)
+                (set ICCi_1 cc))
+       ((fr400 (unit u-integer)) (fr450 (unit u-integer))
+       (fr500 (unit u-integer)) (fr550 (unit u-integer)))
+  )
+)
+
+(int-arith-x-cc-r-simm addxicc add OP_13 "Add reg/immed, with carry")
+(int-arith-x-cc-r-simm subxicc sub OP_17 "Sub reg/immed, with carry")
+
+; Byte compare insns
+
+(dni cmpb
+     "Compare bytes"
+     ((UNIT IALL) (MACH fr400,fr450,fr550) (FR550-MAJOR I-1)
+      (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+     "cmpb$pack $GRi,$GRj,$ICCi_1"
+     (+ pack (GRk-null) OP_00 GRi ICCi_1 OPE2_0C GRj)
+     (sequence ((QI cc))
+              (set-n cc (eq (and GRi #xff000000) (and GRj #xff000000)))
+              (set-z cc (eq (and GRi #x00ff0000) (and GRj #x00ff0000)))
+              (set-v cc (eq (and GRi #x0000ff00) (and GRj #x0000ff00)))
+              (set-c cc (eq (and GRi #x000000ff) (and GRj #x000000ff)))
+              (set ICCi_1 cc))
+     ((fr400 (unit u-integer)) (fr450 (unit u-integer))
+      (fr550 (unit u-integer)))
+)
+
+(dni cmpba
+     "OR of Compare bytes"
+     ((UNIT IALL) (MACH fr400,fr450,fr550) (FR550-MAJOR I-1)
+      (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+     "cmpba$pack $GRi,$GRj,$ICCi_1"
+     (+ pack (GRk-null) OP_00 GRi ICCi_1 OPE2_0D GRj)
+     (sequence ((QI cc))
+              (set cc 0)
+              (set-c cc
+                     (orif (eq (and GRi #xff000000) (and GRj #xff000000))
+                           (orif (eq (and GRi #x00ff0000) (and GRj #x00ff0000))
+                                 (orif (eq (and GRi #x0000ff00)
+                                           (and GRj #x0000ff00))
+                                        (eq (and GRi #x000000ff)
+                                           (and GRj #x000000ff))))))
+              (set ICCi_1 cc))
+     ((fr400 (unit u-integer)) (fr450 (unit u-integer))
+      (fr550 (unit u-integer)))
+)
+
+; Format: Load immediate
+;
+(dni setlo
+     "set low order bits"
+     ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+      (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+     "setlo$pack $ulo16,$GRklo"
+     (+ pack GRk OP_3D (misc-null-4) u16)
+     (set GRklo u16)
+     ((fr400 (unit u-set-hilo)) (fr450 (unit u-set-hilo))
+      (fr500 (unit u-set-hilo)) (fr550 (unit u-set-hilo)))
+)
+
+(dni sethi
+     "set high order bits"
+     ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+      (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+     "sethi$pack $uhi16,$GRkhi"
+     (+ pack GRkhi OP_3E (misc-null-4) u16)
+     (set GRkhi u16)
+     ((fr400 (unit u-set-hilo)) (fr450 (unit u-set-hilo))
+      (fr500 (unit u-set-hilo)) (fr550 (unit u-set-hilo)))
+)
+
+(dni setlos
+     "set low order bits and extend sign"
+     ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+      (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+     "setlos$pack $slo16,$GRk"
+     (+ pack GRk OP_3F (misc-null-4) s16)
+     (set GRk s16)
+     ((fr400 (unit u-integer)) (fr450 (unit u-integer))
+      (fr500 (unit u-integer)) (fr550 (unit u-integer)))
+)
+
+(define-pmacro (load-gr-r name mode op ope comment ann)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2)
+       (FR400-MAJOR I-2) (FR450-MAJOR I-2))
+       (.str name "$pack " ann "($GRi,$GRj),$GRk")
+       (+ pack GRk op GRi ope GRj)
+       (set GRk (c-call mode (.str "@cpu@_read_mem_" mode) pc (add GRi GRj)))
+       ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+       (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+  )
+)
+
+(dann ldann "ld annotation" SI "ld_annotation" "at")
+
+(load-gr-r ldsb   QI OP_02 OPE1_00 "Load   signed byte" "@")
+(load-gr-r ldub  UQI OP_02 OPE1_01 "Load unsigned byte" "@")
+(load-gr-r ldsh   HI OP_02 OPE1_02 "Load   signed half" "@")
+(load-gr-r lduh  UHI OP_02 OPE1_03 "Load unsigned half" "@")
+(load-gr-r ld     SI OP_02 OPE1_04 "Load          word" "$ldann")
+
+(define-pmacro (load-fr-r name mode op ope comment)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2)
+       (FR400-MAJOR I-2) (FR450-MAJOR I-2) FR-ACCESS)
+       (.str name "$pack @($GRi,$GRj),$FRintk")
+       (+ pack FRintk op GRi ope GRj)
+       (set FRintk (c-call mode (.str "@cpu@_read_mem_" mode) pc (add GRi GRj)))
+       ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load))
+       (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
+  )
+)
+
+(load-fr-r ldbf UQI OP_02 OPE1_08 "Load byte   float")
+(load-fr-r ldhf UHI OP_02 OPE1_09 "Load half   float")
+(load-fr-r ldf   SI OP_02 OPE1_0A "Load word   float")
+
+(define-pmacro (load-cpr-r name mode op ope reg attr comment)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR500-MAJOR I-2) attr)
+       (.str name "$pack @($GRi,$GRj),$" reg "k")
+       (+ pack (.sym reg k) op GRi ope GRj)
+       (set (.sym reg k)
+           (c-call mode (.str "@cpu@_read_mem_" mode) pc (add GRi GRj)))
+       ()
+  )
+)
+
+(load-cpr-r ldc SI OP_02 OPE1_0D CPR (MACH frv) "Load coprocessor word")
+
+; These correspond to enumerators in frv-sim.h
+(define-pmacro (ne-UQI-size) 0)
+(define-pmacro (ne-QI-size)  1)
+(define-pmacro (ne-UHI-size) 2)
+(define-pmacro (ne-HI-size)  3)
+(define-pmacro (ne-SI-size)  4)
+(define-pmacro (ne-DI-size)  5)
+(define-pmacro (ne-XI-size)  6)
+
+(define-pmacro (ne-load-semantics base dispix targ idisp size is_float action)
+  (sequence ((BI do_op))
+           (set do_op
+                (c-call BI "@cpu@_check_non_excepting_load"
+                         (index-of base) dispix (index-of targ)
+                         idisp size is_float))
+           (if do_op action))
+)
+
+(define-pmacro (ne-load-gr-r name mode op ope size comment)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING
+       (MACH simple,tomcat,fr500,fr550,frv))
+       (.str name "$pack @($GRi,$GRj),$GRk")
+       (+ pack GRk op GRi ope GRj)
+       (ne-load-semantics GRi (index-of GRj) GRk 0 size 0
+                         (set GRk
+                              (c-call mode (.str "@cpu@_read_mem_" mode)
+                                      pc (add GRi GRj))))
+       ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+  )
+)
+
+(ne-load-gr-r nldsb  QI OP_02 OPE1_20 (ne-QI-size)  "Load   signed byte")
+(ne-load-gr-r nldub UQI OP_02 OPE1_21 (ne-UQI-size) "Load unsigned byte")
+(ne-load-gr-r nldsh  HI OP_02 OPE1_22 (ne-HI-size)  "Load   signed half")
+(ne-load-gr-r nlduh UHI OP_02 OPE1_23 (ne-UHI-size) "Load unsigned half")
+(ne-load-gr-r nld    SI OP_02 OPE1_24 (ne-SI-size)  "Load          word")
+
+(define-pmacro (ne-load-fr-r name mode op ope size comment)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING FR-ACCESS
+       (MACH simple,tomcat,fr500,fr550,frv))
+       (.str name "$pack @($GRi,$GRj),$FRintk")
+       (+ pack FRintk op GRi ope GRj)
+       (ne-load-semantics GRi (index-of GRj) FRintk 0 size 1
+                         (set FRintk
+                              (c-call mode (.str "@cpu@_read_mem_" mode)
+                                      pc (add GRi GRj))))
+       ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
+  )
+)
+
+(ne-load-fr-r nldbf UQI OP_02 OPE1_28 (ne-UQI-size) "Load byte float")
+(ne-load-fr-r nldhf UHI OP_02 OPE1_29 (ne-UHI-size) "Load half float")
+(ne-load-fr-r nldf   SI OP_02 OPE1_2A (ne-SI-size)  "Load word float")
+
+; Semantics for a load-double insn
+;
+(define-pmacro (load-double-semantics not_gr mode regtype address arg)
+  (if (orif not_gr (ne (index-of (.sym regtype doublek)) 0))
+      (sequence ()
+               (set address (add GRi arg))
+               (set (.sym regtype doublek)
+                    (c-call mode (.str "@cpu@_read_mem_" mode) pc address))))
+)
+
+(define-pmacro (load-double-r-r
+               name not_gr mode op ope regtype attr profile comment ann)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2)
+       (FR400-MAJOR I-2) (FR450-MAJOR I-2) attr)
+       (.str name "$pack " ann "($GRi,$GRj),$" regtype "doublek")
+       (+ pack (.sym regtype doublek) op GRi ope GRj)
+       (sequence ((WI address))
+                (load-double-semantics not_gr mode regtype address GRj))
+       profile
+  )
+)
+
+(dann lddann "ldd annotation" SI "ldd_annotation" "at")
+
+(load-double-r-r ldd  0 DI OP_02 OPE1_05 GR  NA
+                ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) 
+                 (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+                "Load double word" "$lddann")
+(load-double-r-r lddf 1 DF OP_02 OPE1_0B FR  FR-ACCESS
+                ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load))
+                 (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
+                "Load double float" "@")
+(load-double-r-r lddc 1 DI OP_02 OPE1_0E CPR (MACH frv) ()
+                "Load coprocessor double" "@")
+
+(define-pmacro (ne-load-double-r-r
+               name not_gr mode op ope regtype size is_float attr profile
+               comment)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING attr
+       (MACH simple,tomcat,fr500,fr550,frv))
+       (.str name "$pack @($GRi,$GRj),$" regtype "doublek")
+       (+ pack (.sym regtype doublek) op GRi ope GRj)
+       (sequence ((WI address))
+                (ne-load-semantics GRi (index-of GRj) (.sym regtype doublek)
+                                   0 size is_float
+                                   (load-double-semantics not_gr mode
+                                                          regtype
+                                                          address GRj)))
+       profile
+  )
+)
+
+(ne-load-double-r-r nldd  0 DI OP_02 OPE1_25 GR (ne-DI-size) 0 NA
+                   ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load double   word")
+(ne-load-double-r-r nlddf 1 DF OP_02 OPE1_2B FR (ne-DI-size) 1 FR-ACCESS
+                   ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load double float")
+
+; Semantics for a load-quad insn
+;
+(define-pmacro (load-quad-semantics regtype address arg)
+  (sequence ()
+           (set address (add GRi arg))
+           (c-call VOID (.str "@cpu@_load_quad_" regtype)
+                   pc address (index-of (.sym regtype k))))
+)
+
+(define-pmacro (load-quad-r-r name op ope regtype attr profile comment)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) attr)
+       (.str name "$pack @($GRi,$GRj),$" regtype "k")
+       (+ pack (.sym regtype k) op GRi ope GRj)
+       (sequence ((WI address))
+                (load-quad-semantics regtype address GRj))
+       ; TODO regtype-k not referenced for profiling
+       profile
+  )
+)
+
+(load-quad-r-r ldq  OP_02 OPE1_06 GR    NA        ((fr500 (unit u-gr-load)))
+              "Load quad word")
+(load-quad-r-r ldqf OP_02 OPE1_0C FRint FR-ACCESS ((fr500 (unit u-fr-load)))
+              "Load quad float")
+(load-quad-r-r ldqc OP_02 OPE1_0F CPR   NA        () "Load coprocessor quad")
+
+(define-pmacro (ne-load-quad-r-r
+               name op ope regtype size is_float attr profile comment)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) NON-EXCEPTING attr)
+       (.str name "$pack @($GRi,$GRj),$" regtype "k")
+       (+ pack (.sym regtype k) op GRi ope GRj)
+       (sequence ((WI address))
+                (ne-load-semantics GRi (index-of GRj) (.sym regtype k)
+                                   0 size is_float
+                                   (load-quad-semantics regtype address GRj)))
+       ; TODO regtype-k not referenced for profiling
+       profile
+  )
+)
+
+(ne-load-quad-r-r nldq  OP_02 OPE1_26 GR    (ne-XI-size) 0 NA
+                 ((fr500 (unit u-gr-load))) "Load quad word")
+(ne-load-quad-r-r nldqf OP_02 OPE1_2C FRint (ne-XI-size) 1 FR-ACCESS
+                 ((fr500 (unit u-fr-load))) "Load quad float")
+
+(define-pmacro (load-gr-u-semantics mode)
+  (sequence ((UWI address))
+           (set address (add GRi GRj))
+           (set GRk (c-call mode (.str "@cpu@_read_mem_" mode) pc address))
+           (if (ne (index-of GRi) (index-of GRk))
+               (sequence ()
+                         (set GRi address)
+                         (c-call VOID "@cpu@_force_update"))))
+)
+
+(define-pmacro (load-gr-u name mode op ope comment)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2)
+       (FR400-MAJOR I-2) (FR450-MAJOR I-2))
+       (.str name "$pack @($GRi,$GRj),$GRk")
+       (+ pack GRk op GRi ope GRj)
+       (load-gr-u-semantics mode)
+       ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+       (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+  )
+)
+
+(load-gr-u ldsbu   QI OP_02 OPE1_10 "Load   signed byte, update index")
+(load-gr-u ldubu  UQI OP_02 OPE1_11 "Load unsigned byte, update index")
+(load-gr-u ldshu   HI OP_02 OPE1_12 "Load   signed half, update index")
+(load-gr-u lduhu  UHI OP_02 OPE1_13 "Load unsigned half, update index")
+(load-gr-u ldu     SI OP_02 OPE1_14 "Load          word, update index")
+
+(define-pmacro (ne-load-gr-u name mode op ope size comment)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING
+       (MACH simple,tomcat,fr500,fr550,frv))
+       (.str name "$pack @($GRi,$GRj),$GRk")
+       (+ pack GRk op GRi ope GRj)
+       (ne-load-semantics GRi (index-of GRj) GRk 0 size 0 (load-gr-u-semantics mode))
+       ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+  )
+)
+
+(ne-load-gr-u nldsbu  QI OP_02 OPE1_30 (ne-QI-size)  "Load   signed byte, update index")
+(ne-load-gr-u nldubu UQI OP_02 OPE1_31 (ne-UQI-size) "Load unsigned byte, update index")
+(ne-load-gr-u nldshu  HI OP_02 OPE1_32 (ne-HI-size)  "Load   signed half, update index")
+(ne-load-gr-u nlduhu UHI OP_02 OPE1_33 (ne-UHI-size) "Load unsigned half, update index")
+(ne-load-gr-u nldu    SI OP_02 OPE1_34 (ne-SI-size)  "Load          word, update index")
+
+(define-pmacro (load-non-gr-u-semantics mode regtype)
+  (sequence ((UWI address))
+           (set address (add GRi GRj))
+           (set (.sym regtype k)
+                (c-call mode (.str "@cpu@_read_mem_" mode) pc address))
+           (set GRi address)
+           (c-call VOID "@cpu@_force_update"))
+)
+
+(define-pmacro (load-fr-u name mode op ope comment)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2)
+       (FR400-MAJOR I-2) (FR450-MAJOR I-2) FR-ACCESS)
+       (.str name "$pack @($GRi,$GRj),$FRintk")
+       (+ pack FRintk op GRi ope GRj)
+       (load-non-gr-u-semantics mode FRint)
+       ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load))
+       (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
+  )
+)
+
+(load-fr-u ldbfu  UQI OP_02 OPE1_18 "Load byte float, update index")
+(load-fr-u ldhfu  UHI OP_02 OPE1_19 "Load half float, update index")
+(load-fr-u ldfu    SI OP_02 OPE1_1A "Load word float, update index")
+
+(define-pmacro (load-cpr-u name mode op ope comment)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv))
+       (.str name "$pack @($GRi,$GRj),$CPRk")
+       (+ pack CPRk op GRi ope GRj)
+       (load-non-gr-u-semantics mode CPR)
+       ()
+  )
+)
+
+(load-cpr-u ldcu SI OP_02 OPE1_1D "Load coprocessor word float,update index")
+
+(define-pmacro (ne-load-non-gr-u name mode op ope regtype size comment)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING FR-ACCESS
+       (MACH simple,tomcat,fr500,fr550,frv))
+       (.str name "$pack @($GRi,$GRj),$" regtype "k")
+       (+ pack (.sym regtype k) op GRi ope GRj)
+       (ne-load-semantics GRi (index-of GRj) (.sym regtype k) 0 size 1
+                         (load-non-gr-u-semantics mode regtype))
+       ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
+  )
+)
+
+(ne-load-non-gr-u nldbfu UQI OP_02 OPE1_38 FRint (ne-UQI-size) "Load byte float, update index")
+(ne-load-non-gr-u nldhfu UHI OP_02 OPE1_39 FRint (ne-UHI-size) "Load half float, update index")
+(ne-load-non-gr-u nldfu   SI OP_02 OPE1_3A FRint (ne-SI-size)  "Load word float, update index")
+
+(define-pmacro (load-double-gr-u-semantics)
+  (sequence ((WI address))
+           (load-double-semantics 0 DI GR address GRj)
+           (if (ne (index-of GRi) (index-of GRdoublek))
+               (sequence ()
+                         (set GRi address)
+                         (c-call VOID "@cpu@_force_update"))))
+)
+
+(define-pmacro (load-double-gr-u name op ope comment)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2)
+       (FR400-MAJOR I-2) (FR450-MAJOR I-2))
+       (.str name "$pack @($GRi,$GRj),$GRdoublek")
+       (+ pack GRdoublek op GRi ope GRj)
+       (load-double-gr-u-semantics)
+       ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+       (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+  )
+)
+
+(load-double-gr-u lddu  OP_02 OPE1_15 "Load double word, update index")
+
+(define-pmacro (ne-load-double-gr-u name op ope size comment)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING
+       (MACH simple,tomcat,fr500,fr550,frv))
+       (.str name "$pack @($GRi,$GRj),$GRdoublek")
+       (+ pack GRdoublek op GRi ope GRj)
+       (ne-load-semantics GRi (index-of GRj) GRdoublek 0 size 0
+                         (load-double-gr-u-semantics))
+       ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+
+  )
+)
+
+(ne-load-double-gr-u nlddu OP_02 OPE1_35 (ne-DI-size) "Load double word, update index")
+
+(define-pmacro (load-double-non-gr-u-semantics mode regtype)
+  (sequence ((WI address))
+           (load-double-semantics 1 mode regtype address GRj)
+           (set GRi address)
+           (c-call VOID "@cpu@_force_update"))
+)
+
+(define-pmacro (load-double-non-gr-u
+               name mode op ope regtype attr profile comment)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2)
+       (FR400-MAJOR I-2) (FR450-MAJOR I-2) attr)
+       (.str name "$pack @($GRi,$GRj),$" regtype "doublek")
+       (+ pack (.sym regtype doublek) op GRi ope GRj)
+       (load-double-non-gr-u-semantics mode regtype)
+       profile
+  )
+)
+
+(load-double-non-gr-u lddfu DF OP_02 OPE1_1B FR  FR-ACCESS
+                     ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load))
+                      (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
+                     "Load double float, update index")
+(load-double-non-gr-u lddcu DI OP_02 OPE1_1E CPR (MACH frv)
+                     () "Load coprocessor double float, update index")
+
+(define-pmacro (ne-load-double-non-gr-u name mode op ope regtype size comment)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING FR-ACCESS
+       (MACH simple,tomcat,fr500,fr550,frv))
+       (.str name "$pack @($GRi,$GRj),$" regtype "doublek")
+       (+ pack (.sym regtype doublek) op GRi ope GRj)
+       (ne-load-semantics GRi (index-of GRj) (.sym regtype doublek) 0 size 1
+                         (load-double-non-gr-u-semantics mode regtype))
+       ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
+  )
+)
+
+(ne-load-double-non-gr-u nlddfu DF OP_02 OPE1_3B FR (ne-DI-size) "Load double float, update index")
+
+(define-pmacro (load-quad-gr-u-semantics)
+  (sequence ((WI address))
+           (load-quad-semantics GR address GRj)
+           (if (ne (index-of GRi) (index-of GRk))
+               (sequence ()
+                         (set GRi address)
+                         (c-call VOID "@cpu@_force_update"))))
+)
+
+(define-pmacro (load-quad-gr-u name op ope comment)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv))
+       (.str name "$pack @($GRi,$GRj),$GRk")
+       (+ pack GRk op GRi ope GRj)
+       (load-quad-gr-u-semantics)
+       ; TODO - GRk not referenced here for profiling
+       ((fr500 (unit u-gr-load)))
+  )
+)
+
+(load-quad-gr-u ldqu  OP_02 OPE1_16 "Load quad word, update index")
+
+(define-pmacro (ne-load-quad-gr-u name op ope size comment)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) NON-EXCEPTING)
+       (.str name "$pack @($GRi,$GRj),$GRk")
+       (+ pack GRk op GRi ope GRj)
+       (ne-load-semantics GRi (index-of GRj) GRk 0 size 0
+                         (load-quad-gr-u-semantics))
+       ; TODO - GRk not referenced here for profiling
+       ((fr500 (unit u-gr-load)))
+  )
+)
+
+(ne-load-quad-gr-u nldqu OP_02 OPE1_36 (ne-XI-size) "Load quad word, update index")
+
+(define-pmacro (load-quad-non-gr-u-semantics regtype)
+  (sequence ((WI address))
+           (load-quad-semantics regtype address GRj)
+           (set GRi address)
+           (c-call VOID "@cpu@_force_update"))
+)
+
+(define-pmacro (load-quad-non-gr-u name op ope regtype attr profile comment)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) attr)
+       (.str name "$pack @($GRi,$GRj),$" regtype "k")
+       (+ pack (.sym regtype k) op GRi ope GRj)
+       (load-quad-non-gr-u-semantics regtype)
+       profile
+  )
+)
+
+(load-quad-non-gr-u ldqfu OP_02 OPE1_1C FRint FR-ACCESS
+                   ((fr500 (unit u-fr-load))) "Load quad float, update index")
+(load-quad-non-gr-u ldqcu OP_02 OPE1_1F CPR   NA
+                   () "Load coprocessor quad word, update index")
+
+(define-pmacro (ne-load-quad-non-gr-u name op ope regtype size comment)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) NON-EXCEPTING FR-ACCESS)
+       (.str name "$pack @($GRi,$GRj),$" regtype "k")
+       (+ pack (.sym regtype k) op GRi ope GRj)
+       (ne-load-semantics GRi (index-of GRj) (.sym regtype k) 0 size 1
+                         (load-quad-non-gr-u-semantics regtype))
+       ((fr500 (unit u-fr-load)))
+  )
+)
+
+(ne-load-quad-non-gr-u nldqfu OP_02 OPE1_3C FRint (ne-XI-size) "Load quad float,update index")
+
+(define-pmacro (load-r-simm name mode op regtype attr profile comment)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2)
+       (FR400-MAJOR I-2) (FR450-MAJOR I-2) attr)
+       (.str name "$pack @($GRi,$d12),$" regtype "k")
+       (+ pack (.sym regtype k) op GRi d12)
+       (set (.sym regtype k)
+           (c-call mode (.str "@cpu@_read_mem_" mode) pc (add GRi d12)))
+       profile
+  )
+)
+
+(load-r-simm ldsbi  QI OP_30 GR NA
+            ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+             (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+            "Load   signed byte")
+(load-r-simm ldshi  HI OP_31 GR NA
+            ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+             (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+            "Load   signed half")
+(load-r-simm ldi    SI OP_32 GR NA
+            ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+             (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+            "Load          word")
+(load-r-simm ldubi UQI OP_35 GR NA
+            ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+             (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+            "Load unsigned byte")
+(load-r-simm lduhi UHI OP_36 GR NA
+            ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+             (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+            "Load unsigned half")
+
+(load-r-simm ldbfi UQI OP_38 FRint FR-ACCESS
+            ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load))
+             (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
+            "Load byte float")
+(load-r-simm ldhfi UHI OP_39 FRint FR-ACCESS
+            ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load))
+             (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
+            "Load half float")
+(load-r-simm ldfi   SI OP_3A FRint FR-ACCESS
+            ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load))
+             (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
+            "Load word float")
+
+(define-pmacro (ne-load-r-simm
+               name mode op regtype size is_float attr profile comment)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING attr
+       (MACH simple,tomcat,fr500,fr550,frv))
+       (.str name "$pack @($GRi,$d12),$" regtype "k")
+       (+ pack (.sym regtype k) op GRi d12)
+       (ne-load-semantics GRi -1 (.sym regtype k) d12 size is_float
+                         (set (.sym regtype k)
+                              (c-call mode (.str "@cpu@_read_mem_" mode)
+                                      pc (add GRi d12))))
+       profile
+  )
+)
+
+(ne-load-r-simm nldsbi  QI OP_40 GR (ne-QI-size)  0 NA
+               ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load   signed byte")
+(ne-load-r-simm nldubi UQI OP_41 GR (ne-UQI-size) 0 NA
+               ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load unsigned byte")
+(ne-load-r-simm nldshi  HI OP_42 GR (ne-HI-size)  0 NA
+               ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load   signed half")
+(ne-load-r-simm nlduhi UHI OP_43 GR (ne-UHI-size) 0 NA
+               ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load unsigned half")
+(ne-load-r-simm nldi    SI OP_44 GR (ne-SI-size)  0 NA
+               ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load          word")
+
+(ne-load-r-simm nldbfi UQI OP_48 FRint (ne-UQI-size) 1 FR-ACCESS
+               ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load byte float")
+(ne-load-r-simm nldhfi UHI OP_49 FRint (ne-UHI-size) 1 FR-ACCESS
+               ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load half float")
+(ne-load-r-simm nldfi   SI OP_4A FRint (ne-SI-size)  1 FR-ACCESS
+               ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load word float")
+
+(define-pmacro (load-double-r-simm
+               name not_gr mode op regtype attr profile comment)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2)
+       (FR400-MAJOR I-2) (FR450-MAJOR I-2) attr)
+       (.str name "$pack @($GRi,$d12),$" regtype "doublek")
+       (+ pack (.sym regtype doublek) op GRi d12)
+       (sequence ((WI address))
+                (load-double-semantics not_gr mode regtype address d12))
+       profile
+  )
+)
+
+(load-double-r-simm lddi  0 DI OP_33 GR NA
+                   ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+                    (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+                   "Load double word")
+(load-double-r-simm lddfi 1 DF OP_3B FR FR-ACCESS
+                   ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load))
+                    (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
+                   "Load double float")
+
+(define-pmacro (ne-load-double-r-simm
+               name not_gr mode op regtype size is_float attr profile comment)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING attr
+       (MACH simple,tomcat,fr500,fr550,frv))
+       (.str name "$pack @($GRi,$d12),$" regtype "doublek")
+       (+ pack (.sym regtype doublek) op GRi d12)
+       (sequence ((WI address))
+                (ne-load-semantics GRi -1 (.sym regtype doublek)
+                                   d12 size is_float
+                                   (load-double-semantics not_gr mode
+                                                          regtype
+                                                          address d12)))
+       profile
+  )
+)
+
+(ne-load-double-r-simm nlddi  0 DI OP_45 GR (ne-DI-size) 0 NA
+                      ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load double word")
+(ne-load-double-r-simm nlddfi 1 DF OP_4B FR (ne-DI-size) 1 FR-ACCESS
+                      ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load double float")
+
+(define-pmacro (load-quad-r-simm name op regtype attr profile comment)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) attr)
+       (.str name "$pack @($GRi,$d12),$" regtype "k")
+       (+ pack (.sym regtype k) op GRi d12)
+       (sequence ((WI address))
+                (load-quad-semantics regtype address d12))
+       profile
+  )
+)
+
+(load-quad-r-simm ldqi  OP_34 GR    NA
+                 ((fr500 (unit u-gr-load))) "Load quad word")
+(load-quad-r-simm ldqfi OP_3C FRint FR-ACCESS
+                 ((fr500 (unit u-fr-load))) "Load quad float")
+
+(define-pmacro (ne-load-quad-r-simm
+               name op regtype size is_float attr profile comment)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) NON-EXCEPTING attr)
+       (.str name "$pack @($GRi,$d12),$" regtype "k")
+       (+ pack (.sym regtype k) op GRi d12)
+       (sequence ((WI address))
+                (ne-load-semantics GRi -1 (.sym regtype k) d12 size is_float
+                                   (load-quad-semantics regtype address d12)))
+       profile
+  )
+)
+
+(ne-load-quad-r-simm nldqfi OP_4C FRint (ne-XI-size) 1 FR-ACCESS
+                    ((fr500 (unit u-fr-load))) "Load quad float")
+
+(define-pmacro (store-r-r name mode op ope reg attr profile comment)
+  (dni name
+       (comment)
+       ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3)
+       (FR400-MAJOR I-3) (FR450-MAJOR I-3) attr)
+       (.str name "$pack $" reg "k,@($GRi,$GRj)")
+       (+ pack (.sym reg k) op GRi ope GRj)
+       (c-call VOID (.str "@cpu@_write_mem_" mode)
+              pc (add GRi GRj) (.sym reg k))
+       profile
+  )
+)
+
+(store-r-r stb   QI OP_03 OPE1_00 GR NA
+          ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+           (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+          "Store unsigned byte")
+(store-r-r sth   HI OP_03 OPE1_01 GR NA
+          ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+           (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+          "Store unsigned half")
+(store-r-r st    SI OP_03 OPE1_02 GR NA
+          ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+           (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+          "Store          word")
+
+(store-r-r stbf  QI OP_03 OPE1_08 FRint FR-ACCESS
+          ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+           (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+          "Store byte float")
+(store-r-r sthf  HI OP_03 OPE1_09 FRint FR-ACCESS
+          ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+           (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+          "Store half float")
+(store-r-r stf   SI OP_03 OPE1_0A FRint FR-ACCESS
+          ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+           (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+          "Store word float")
+
+(store-r-r stc   SI OP_03 OPE1_25 CPR (MACH frv) () "Store coprocessor word")
+
+; Semantics for a store-double insn
+;
+(define-pmacro (store-double-semantics mode regtype address arg)
+  (sequence ()
+           (set address (add GRi arg))
+           (c-call VOID (.str "@cpu@_write_mem_" mode)
+                   pc address (.sym regtype doublek)))
+)
+
+(define-pmacro (store-double-r-r name mode op ope regtype attr profile comment)
+  (dni name
+       (comment)
+       ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3)
+       (FR400-MAJOR I-3) (FR450-MAJOR I-3) attr)
+       (.str name "$pack $" regtype "doublek,@($GRi,$GRj)")
+       (+ pack (.sym regtype doublek) op GRi ope GRj)
+       (sequence ((WI address))
+                (store-double-semantics mode regtype address GRj))
+       profile
+  )
+)
+
+(store-double-r-r std  DI OP_03 OPE1_03 GR  NA
+                 ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+                  (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+                 "Store double word")
+(store-double-r-r stdf DF OP_03 OPE1_0B FR  FR-ACCESS
+                 ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+                  (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+                 "Store double float")
+
+(store-double-r-r stdc DI OP_03 OPE1_26 CPR (MACH frv)
+                 () "Store coprocessor double word")
+
+; Semantics for a store-quad insn
+;
+(define-pmacro (store-quad-semantics regtype address arg)
+  (sequence ()
+           (set address (add GRi arg))
+           (c-call VOID (.str "@cpu@_store_quad_" regtype)
+                    pc address (index-of (.sym regtype k))))
+)
+
+(define-pmacro (store-quad-r-r name op ope regtype attr profile comment)
+  (dni name
+       (comment)
+       ((UNIT STORE) (FR500-MAJOR I-3) (MACH frv) attr)
+       (.str name "$pack $" regtype "k,@($GRi,$GRj)")
+       (+ pack (.sym regtype k) op GRi ope GRj)
+       (sequence ((WI address))
+                (store-quad-semantics regtype address GRj))
+       profile
+  )
+)
+
+(store-quad-r-r stq   OP_03 OPE1_04 GR    NA
+               ((fr500 (unit u-gr-store))) "Store quad word")
+(store-quad-r-r stqf  OP_03 OPE1_0C FRint FR-ACCESS
+               ((fr500 (unit u-fr-store)))
+               "Store quad float")
+(store-quad-r-r stqc  OP_03 OPE1_27 CPR   NA
+               () "Store coprocessor quad word")
+
+(define-pmacro (store-r-r-u name mode op ope regtype attr profile comment)
+  (dni name
+       (comment)
+       ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3)
+       (FR400-MAJOR I-3) (FR450-MAJOR I-3) attr)
+       (.str name "$pack $" regtype "k,@($GRi,$GRj)")
+       (+ pack (.sym regtype k) op GRi ope GRj)
+       (sequence ((UWI address))
+                (set address (add GRi GRj))
+                (c-call VOID (.str "@cpu@_write_mem_" mode)
+                        pc address (.sym regtype k))
+                (set GRi address))
+       profile
+  )
+)
+
+(store-r-r-u stbu  QI OP_03 OPE1_10 GR NA
+            ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+             (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+            "Store unsigned byte, update index")
+(store-r-r-u sthu  HI OP_03 OPE1_11 GR NA
+            ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+             (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+            "Store unsigned half, update index")
+(store-r-r-u stu   WI OP_03 OPE1_12 GR NA
+            ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+             (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+            "Store          word, update index")
+
+(store-r-r-u stbfu QI OP_03 OPE1_18 FRint FR-ACCESS
+            ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+             (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+            "Store byte float, update index")
+(store-r-r-u sthfu HI OP_03 OPE1_19 FRint FR-ACCESS
+            ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+             (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+            "Store half float, update index")
+(store-r-r-u stfu  SI OP_03 OPE1_1A FRint FR-ACCESS
+            ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+             (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+            "Store word float, update index")
+
+(store-r-r-u stcu  SI OP_03 OPE1_2D CPR (MACH frv) ()
+            "Store coprocessor word, update index")
+
+(define-pmacro (store-double-r-r-u
+               name mode op ope regtype attr profile comment)
+  (dni name
+       (comment)
+       ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3)
+       (FR400-MAJOR I-3) (FR450-MAJOR I-3) attr)
+       (.str name "$pack $" regtype "doublek,@($GRi,$GRj)")
+       (+ pack (.sym regtype doublek) op GRi ope GRj)
+       (sequence ((WI address))
+                (store-double-semantics mode regtype address GRj)
+                (set GRi address))
+       profile
+  )
+)
+
+(store-double-r-r-u stdu  DI OP_03 OPE1_13 GR  NA
+                   ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+                    (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+                   "Store double word, update index")
+(store-double-r-r-u stdfu DF OP_03 OPE1_1B FR  FR-ACCESS
+                   ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+                    (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+                   "Store double float,update index")
+(store-double-r-r-u stdcu DI OP_03 OPE1_2E CPR (MACH frv) ()
+                   "Store coprocessor double word, update index")
+
+(define-pmacro (store-quad-r-r-u name op ope regtype attr profile comment)
+  (dni name
+       (comment)
+       ((UNIT STORE) (FR500-MAJOR I-3) (MACH frv) attr)
+       (.str name "$pack $" regtype "k,@($GRi,$GRj)")
+       (+ pack (.sym regtype k) op GRi ope GRj)
+       (sequence ((WI address))
+                (store-quad-semantics regtype address GRj)
+                (set GRi address))
+       profile
+  )
+)
+
+(store-quad-r-r-u stqu  OP_03 OPE1_14 GR    NA
+                 ((fr500 (unit u-gr-store)))
+                 "Store quad word, update index")
+(store-quad-r-r-u stqfu OP_03 OPE1_1C FRint FR-ACCESS
+                 ((fr500 (unit u-fr-store)))
+                 "Store quad float, update index")
+(store-quad-r-r-u stqcu OP_03 OPE1_2F CPR   NA ()
+                 "Store coprocessor quad   word, update index")
+
+(define-pmacro (conditional-load name mode op ope regtype profile comment)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2)
+       (FR400-MAJOR I-2) (FR450-MAJOR I-2) CONDITIONAL)
+       (.str name "$pack @($GRi,$GRj),$" regtype "k,$CCi,$cond")
+       (+ pack (.sym regtype k) op GRi CCi  cond ope GRj)
+       (if (eq CCi (or cond 2))
+          (set (.sym regtype k)
+               (c-call mode (.str "@cpu@_read_mem_" mode) pc (add GRi GRj))))
+       profile
+  )
+)
+
+(conditional-load cldsb  QI OP_5E OPE4_0 GR
+                 ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+                  (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+                 "Load   signed byte")
+(conditional-load cldub UQI OP_5E OPE4_1 GR
+                 ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+                  (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+                 "Load unsigned byte")
+(conditional-load cldsh  HI OP_5E OPE4_2 GR
+                 ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+                  (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+                 "Load   signed half")
+(conditional-load clduh UHI OP_5E OPE4_3 GR
+                 ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+                  (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+                 "Load unsigned half")
+(conditional-load cld    SI OP_5F OPE4_0 GR
+                 ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+                  (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+                 "Load          word")
+
+(conditional-load cldbf UQI OP_60 OPE4_0 FRint
+                 ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load))
+                  (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
+                 "Load byte float")
+(conditional-load cldhf UHI OP_60 OPE4_1 FRint
+                 ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load))
+                  (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
+                 "Load half float")
+(conditional-load cldf   SI OP_60 OPE4_2 FRint
+                 ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load))
+                  (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
+                 "Load word float")
+
+(define-pmacro (conditional-load-double
+               name not_gr mode op ope regtype attr profile comment)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2)
+       (FR400-MAJOR I-2) (FR450-MAJOR I-2) CONDITIONAL attr)
+       (.str name "$pack @($GRi,$GRj),$" regtype "doublek,$CCi,$cond")
+       (+ pack (.sym regtype doublek) op GRi CCi  cond ope GRj)
+       (if (eq CCi (or cond 2))
+          (sequence ((WI address))
+                    (load-double-semantics not_gr mode regtype address GRj)))
+       profile
+  )
+)
+
+(conditional-load-double cldd  0 DI OP_5F OPE4_1 GR NA
+                        ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+                         (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+                        "Load double word")
+(conditional-load-double clddf 1 DF OP_60 OPE4_3 FR FR-ACCESS
+                        ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+                         (fr500 (unit u-gr-load)) (fr550 (unit u-fr-load)))
+                        "Load double float")
+
+(dni cldq
+     "conditional load quad integer"
+     ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) CONDITIONAL)
+     "cldq$pack @($GRi,$GRj),$GRk,$CCi,$cond"
+     (+ pack GRk OP_5F GRi CCi cond OPE4_2 GRj)
+     (if (eq CCi (or cond 2))
+        (sequence ((WI address))
+                  (load-quad-semantics GR address GRj)))
+     ((fr500 (unit u-gr-load)))
+)
+
+(define-pmacro (conditional-load-gr-u name mode op ope comment)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2)
+       (FR400-MAJOR I-2) (FR450-MAJOR I-2) CONDITIONAL)
+       (.str name "$pack @($GRi,$GRj),$GRk,$CCi,$cond")
+       (+ pack GRk op GRi CCi  cond ope GRj)
+       (if (eq CCi (or cond 2))
+          (sequence ((WI address))
+                    (set address (add GRi GRj))
+                    (set GRk
+                         (c-call mode (.str "@cpu@_read_mem_" mode)
+                                 pc address))
+                    (if (ne (index-of GRi) (index-of GRk))
+                        (set GRi address))))
+       ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+       (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+  )
+)
+
+(conditional-load-gr-u cldsbu  QI OP_61 OPE4_0 "Load   signed byte, update")
+(conditional-load-gr-u cldubu UQI OP_61 OPE4_1 "Load unsigned byte, update")
+(conditional-load-gr-u cldshu  HI OP_61 OPE4_2 "Load   signed half, update")
+(conditional-load-gr-u clduhu UHI OP_61 OPE4_3 "Load unsigned half, update")
+(conditional-load-gr-u cldu    SI OP_62 OPE4_0 "Load          word, update")
+
+(define-pmacro (conditional-load-non-gr-u name mode op ope regtype comment)
+  (dni name
+       (comment)
+       ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2)
+       (FR400-MAJOR I-2) (FR450-MAJOR I-2) CONDITIONAL FR-ACCESS)
+       (.str name "$pack @($GRi,$GRj),$" regtype "k,$CCi,$cond")
+       (+ pack (.sym regtype k) op GRi CCi  cond ope GRj)
+       (if (eq CCi (or cond 2))
+          (sequence ((WI address))
+                    (set address (add GRi GRj))
+                    (set (.sym regtype k)
+                         (c-call mode (.str "@cpu@_read_mem_" mode)
+                                 pc address))
+                    (set GRi address)))
+       ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load))
+       (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
+  )
+)
+
+(conditional-load-non-gr-u cldbfu UQI OP_63 OPE4_0 FRint "Load byte float, update")
+(conditional-load-non-gr-u cldhfu UHI OP_63 OPE4_1 FRint "Load half float, update")
+(conditional-load-non-gr-u cldfu   SI OP_63 OPE4_2 FRint "Load word float, update")
+
+
+(dni clddu
+     "Load double word,  update"
+     ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2)
+      (FR400-MAJOR I-2) (FR450-MAJOR I-2) CONDITIONAL)
+     "clddu$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond"
+     (+ pack GRdoublek OP_62 GRi CCi cond OPE4_1 GRj)
+     (if (eq CCi (or cond 2))
+        (sequence ((WI address))
+                  (load-double-semantics 0 DI GR address GRj)
+                  (if (ne (index-of GRi) (index-of GRdoublek))
+                      (set GRi address))))
+     ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+      (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+)
+
+(dni clddfu
+     "Load double float, update"
+     ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2)
+      (FR400-MAJOR I-2) (FR450-MAJOR I-2) CONDITIONAL FR-ACCESS)
+     "clddfu$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond"
+     (+ pack FRdoublek OP_63 GRi CCi cond OPE4_3 GRj)
+     (if (eq CCi (or cond 2))
+        (sequence ((WI address))
+                  (load-double-semantics 1 DF FR address GRj)
+                  (set GRi address)))
+     ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load))
+      (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
+)
+
+(dni cldqu
+     "conditional load quad integer and update index"
+     ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) CONDITIONAL)
+     "cldqu$pack @($GRi,$GRj),$GRk,$CCi,$cond"
+     (+ pack GRk OP_62 GRi CCi cond OPE4_2 GRj)
+     (if (eq CCi (or cond 2))
+        (sequence ((WI address))
+                  (load-quad-semantics GR address GRj)
+                  (if (ne (index-of GRi) (index-of GRk))
+                      (set GRi address))))
+     ((fr500 (unit u-gr-load)))
+)
+
+(define-pmacro (conditional-store name mode op ope regtype profile comment)
+  (dni name
+       (comment)
+       ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3)
+       (FR400-MAJOR I-3) (FR450-MAJOR I-3) CONDITIONAL)
+       (.str name "$pack $" regtype "k,@($GRi,$GRj),$CCi,$cond")
+       (+ pack (.sym regtype k) op GRi CCi cond ope GRj)
+       (if (eq CCi (or cond 2))
+          (c-call VOID (.str "@cpu@_write_mem_" mode)
+                  pc (add GRi GRj) (.sym regtype k)))
+       profile
+  )
+)
+
+(conditional-store cstb  QI OP_64 OPE4_0 GR
+                  ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+                   (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+                  "Store unsigned byte")
+(conditional-store csth  HI OP_64 OPE4_1 GR
+                  ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+                   (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+                  "Store unsigned half")
+(conditional-store cst   SI OP_64 OPE4_2 GR
+                  ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+                   (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+                  "Store          word")
+
+(conditional-store cstbf QI OP_66 OPE4_0 FRint
+                  ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+                   (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+                  "Store byte float")
+(conditional-store csthf HI OP_66 OPE4_1 FRint
+                  ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+                   (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+                  "Store half float")
+(conditional-store cstf  SI OP_66 OPE4_2 FRint
+                  ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+                   (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+                  "Store word float")
+
+(define-pmacro (conditional-store-double
+               name mode op ope regtype attr profile comment)
+  (dni name
+       (comment)
+       ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3)
+       (FR400-MAJOR I-3) (FR450-MAJOR I-3) CONDITIONAL attr)
+       (.str name "$pack $" regtype "doublek,@($GRi,$GRj),$CCi,$cond")
+       (+ pack (.sym regtype doublek) op GRi CCi  cond ope GRj)
+       (if (eq CCi (or cond 2))
+          (sequence ((WI address))
+                    (store-double-semantics mode regtype address GRj)))
+       profile
+  )
+)
+
+(conditional-store-double cstd  DI OP_64 OPE4_3 GR NA
+                         ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+                          (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+                         "Store double word")
+(conditional-store-double cstdf DF OP_66 OPE4_3 FR FR-ACCESS
+                         ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+                          (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+                         "Store double float")
+
+(dni cstq
+     "conditionally store quad word"
+     ((UNIT STORE) (FR500-MAJOR I-3) (MACH frv) CONDITIONAL)
+     "cstq$pack $GRk,@($GRi,$GRj),$CCi,$cond"
+     (+ pack GRk OP_65 GRi CCi cond OPE4_0 GRj)
+     (if (eq CCi (or cond 2))
+        (sequence ((WI address))
+                  (store-quad-semantics GR address GRj)))
+     ((fr500 (unit u-gr-store)))
+)
+
+(define-pmacro (conditional-store-u
+               name mode op ope regtype attr profile comment)
+  (dni name
+       (comment)
+       ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3)
+       (FR400-MAJOR I-3) (FR450-MAJOR I-3) CONDITIONAL attr)
+       (.str name "$pack $" regtype "k,@($GRi,$GRj),$CCi,$cond")
+       (+ pack (.sym regtype k) op GRi CCi  cond ope GRj)
+       (if (eq CCi (or cond 2))
+          (sequence ((WI address))
+                    (set address (add GRi GRj))
+                    (c-call VOID (.str "@cpu@_write_mem_" mode)
+                            pc address (.sym regtype k))
+                    (set GRi address)))
+       profile
+  )
+)
+
+(conditional-store-u cstbu QI OP_67 OPE4_0 GR NA
+                    ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+                     (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+                    "Store unsigned byte, update index")
+(conditional-store-u csthu HI OP_67 OPE4_1 GR NA
+                    ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+                     (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+                    "Store unsigned half, update index")
+(conditional-store-u cstu  SI OP_67 OPE4_2 GR NA
+                    ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+                     (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+                    "Store          word, update index")
+
+(conditional-store-u cstbfu QI OP_68 OPE4_0 FRint FR-ACCESS
+                    ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+                     (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+                    "Store byte float, update index")
+(conditional-store-u csthfu HI OP_68 OPE4_1 FRint FR-ACCESS
+                    ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+                     (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+                    "Store half float, update index")
+(conditional-store-u cstfu  SI OP_68 OPE4_2 FRint FR-ACCESS
+                    ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+                     (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+                    "Store word float, update index")
+
+(define-pmacro (conditional-store-double-u
+               name mode op ope regtype attr profile comment)
+  (dni name
+       (comment)
+       ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3)
+       (FR400-MAJOR I-3) (FR450-MAJOR I-3) CONDITIONAL attr)
+       (.str name "$pack $" regtype "doublek,@($GRi,$GRj),$CCi,$cond")
+       (+ pack (.sym regtype doublek) op GRi CCi  cond ope GRj)
+       (if (eq CCi (or cond 2))
+          (sequence ((WI address))
+                    (store-double-semantics mode regtype address GRj)
+                    (set GRi address)))
+       profile
+  )
+)
+
+(conditional-store-double-u cstdu  DI OP_67 OPE4_3 GR NA
+                           ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+                            (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+                           "Store double word, update index")
+(conditional-store-double-u cstdfu DF OP_68 OPE4_3 FR FR-ACCESS
+                           ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+                            (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+                           "Store double float, update index")
+
+(define-pmacro (store-r-simm name mode op regtype attr profile comment)
+  (dni name
+       (comment)
+       ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3)
+       (FR400-MAJOR I-3) (FR450-MAJOR I-3) attr)
+       (.str name "$pack $" regtype "k,@($GRi,$d12)")
+       (+ pack (.sym regtype k) op GRi d12)
+       (c-call VOID (.str "@cpu@_write_mem_" mode)
+              pc (add GRi d12) (.sym regtype k))
+       profile
+  )
+)
+
+(store-r-simm stbi QI OP_50 GR NA
+             ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+              (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+             "Store unsigned byte")
+(store-r-simm sthi HI OP_51 GR NA
+             ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+              (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+             "Store unsigned half")
+(store-r-simm sti  SI OP_52 GR NA
+             ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+              (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+             "Store          word")
+
+(store-r-simm stbfi QI OP_4E FRint FR-ACCESS
+             ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+              (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+             "Store byte float")
+(store-r-simm sthfi HI OP_4F FRint FR-ACCESS
+             ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+              (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+             "Store half float")
+(store-r-simm stfi  SI OP_55 FRint FR-ACCESS
+             ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+              (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+             "Store word float")
+
+(define-pmacro (store-double-r-simm name mode op regtype attr profile comment)
+  (dni name
+       (comment)
+       ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3)
+       (FR400-MAJOR I-3) (FR450-MAJOR I-3) attr)
+       (.str name "$pack $" regtype "doublek,@($GRi,$d12)")
+       (+ pack (.sym regtype doublek) op GRi d12)
+       (sequence ((WI address))
+                (store-double-semantics mode regtype address d12))
+       profile
+  )
+)
+
+(store-double-r-simm stdi  DI OP_53 GR NA
+                    ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+                     (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+                    "Store double word")
+(store-double-r-simm stdfi DF OP_56 FR FR-ACCESS
+                    ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+                     (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+                    "Store double float")
+
+(define-pmacro (store-quad-r-simm name op regtype attr profile comment)
+  (dni name
+       (comment)
+       ((UNIT STORE) (FR500-MAJOR I-3) (MACH frv) attr)
+       (.str name "$pack $" regtype "k,@($GRi,$d12)")
+       (+ pack (.sym regtype k) op GRi d12)
+       (sequence ((WI address))
+                (store-quad-semantics regtype address d12))
+       profile
+  )
+)
+
+(store-quad-r-simm stqi  OP_54 GR    NA ((fr500 (unit u-gr-store)))
+                  "Store quad word")
+(store-quad-r-simm stqfi OP_57 FRint FR-ACCESS ()
+                  "Store quad float")
+
+(define-pmacro (swap-semantics base offset arg)
+  (sequence ((WI tmp) (WI address))
+           (set tmp arg)
+           (set address (add base offset))
+           (c-call VOID "@cpu@_check_swap_address" address)
+           (set arg (c-call WI "@cpu@_read_mem_WI" pc address))
+           (c-call VOID "@cpu@_write_mem_WI" pc address tmp))
+)
+
+(dni swap
+     "Swap contents of memory with GR"
+     ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2)
+      (FR400-MAJOR C-2) (FR450-MAJOR C-2))
+     "swap$pack @($GRi,$GRj),$GRk"
+     (+ pack GRk OP_03 GRi OPE1_05 GRj)
+     (swap-semantics GRi GRj GRk)
+     ((fr400 (unit u-swap)) (fr450 (unit u-swap))
+      (fr500 (unit u-swap)) (fr550 (unit u-swap)))
+)
+
+(dni "swapi"
+     "Swap contents of memory with GR"
+     ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2)
+      (FR400-MAJOR C-2) (FR450-MAJOR C-2))
+     ("swapi$pack @($GRi,$d12),$GRk")
+     (+ pack GRk OP_4D GRi d12)
+     (swap-semantics GRi d12 GRk)
+     ((fr400 (unit u-swap)) (fr450 (unit u-swap))
+      (fr500 (unit u-swap)) (fr550 (unit u-swap)))
+)
+
+(dni cswap
+     "Conditionally swap contents of memory with GR"
+     ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2)
+      (FR400-MAJOR C-2) (FR450-MAJOR C-2) CONDITIONAL)
+     "cswap$pack @($GRi,$GRj),$GRk,$CCi,$cond"
+     (+ pack GRk OP_65 GRi CCi cond OPE4_2 GRj)
+     (if (eq CCi (or cond 2))
+        (swap-semantics GRi GRj GRk))
+     ((fr400 (unit u-swap)) (fr450 (unit u-swap))
+      (fr500 (unit u-swap)) (fr550 (unit u-swap)))
+)
+
+(define-pmacro (register-transfer
+               name op ope reg_src reg_targ pipe attrs profile comment)
+  (dni name
+       (comment)
+       (.splice (UNIT pipe) (.unsplice attrs))
+       (.str name "$pack $" reg_src ",$" reg_targ)
+       (+ pack reg_targ op (rs-null) ope reg_src)
+       (set reg_targ reg_src)
+       profile
+  )
+)
+
+(register-transfer movgf OP_03 OPE1_15
+                  GRj FRintk I0
+                  ((FR500-MAJOR I-4) (FR550-MAJOR I-5)
+                   (FR400-MAJOR I-4) (FR450-MAJOR I-4) FR-ACCESS)
+                  ((fr400 (unit u-gr2fr)) (fr450 (unit u-gr2fr))
+                   (fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr)))
+                  "transfer gr to fr")
+(register-transfer movfg OP_03 OPE1_0D
+                  FRintk GRj I0
+                  ((FR500-MAJOR I-4) (FR550-MAJOR I-5)
+                   (FR400-MAJOR I-4) (FR450-MAJOR I-4) FR-ACCESS)
+                  ((fr400 (unit u-fr2gr)) (fr450 (unit u-fr2gr))
+                   (fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr)))
+                  "transfer fr to gr")
+
+(define-pmacro (nextreg hw r offset) (reg hw (add (index-of r) offset)))
+
+(define-pmacro (register-transfer-double-from-gr-semantics cond)
+  (if cond
+      (if (eq (index-of GRj) 0)
+         (sequence ()
+                   (set FRintk 0)
+                   (set (nextreg h-fr_int FRintk 1) 0))
+         (sequence ()
+                   (set FRintk GRj)
+                   (set (nextreg h-fr_int FRintk 1) (nextreg h-gr GRj 1)))))
+)
+
+(dni movgfd
+     "move GR for FR double"
+     ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5)
+      (FR400-MAJOR I-4) (FR450-MAJOR I-4) FR-ACCESS)
+     "movgfd$pack $GRj,$FRintk"
+     (+ pack FRintk OP_03 (rs-null) OPE1_16 GRj)
+     (register-transfer-double-from-gr-semantics 1)
+     ; TODO -- doesn't handle second register in the pair
+     ((fr400 (unit u-gr2fr)) (fr450 (unit u-gr2fr))
+      (fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr)))
+)
+
+(define-pmacro (register-transfer-double-to-gr-semantics cond)
+  (if (andif (ne (index-of GRj) 0) cond)
+      (sequence ()
+               (set GRj FRintk)
+               (set (nextreg h-gr GRj 1) (nextreg h-fr_int FRintk 1))))
+)
+
+(dni movfgd
+     "move FR for GR double"
+     ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5)
+      (FR400-MAJOR I-4) (FR450-MAJOR I-4) FR-ACCESS)
+     "movfgd$pack $FRintk,$GRj"
+     (+ pack FRintk OP_03 (rs-null) OPE1_0E GRj)
+     (register-transfer-double-to-gr-semantics 1)
+     ; TODO -- doesn't handle second register in the pair
+     ((fr400 (unit u-fr2gr)) (fr450 (unit u-fr2gr))
+      (fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr)))
+)
+
+(dni movgfq
+     "move GR for FR quad"
+     ((UNIT I0) (FR500-MAJOR I-4) (MACH frv) FR-ACCESS)
+     "movgfq$pack $GRj,$FRintk"
+     (+ pack FRintk OP_03 (rs-null) OPE1_17 GRj)
+     (if (eq (index-of GRj) 0)
+        (sequence ()
+                  (set FRintk 0)
+                  (set (reg h-fr_int (add (index-of FRintk) 1)) 0)
+                  (set (reg h-fr_int (add (index-of FRintk) 2)) 0)
+                  (set (reg h-fr_int (add (index-of FRintk) 3)) 0))
+        (sequence ()
+                  (set FRintk GRj)
+                  (set (reg h-fr_int (add (index-of FRintk) 1))
+                       (reg h-gr (add (index-of GRj)    1)))
+                  (set (reg h-fr_int (add (index-of FRintk) 2))
+                       (reg h-gr (add (index-of GRj)    2)))
+                  (set (reg h-fr_int (add (index-of FRintk) 3))
+                       (reg h-gr (add (index-of GRj)    3)))))
+     ()
+)
+
+(dni movfgq
+     "move FR for GR quad"
+     ((UNIT I0) (FR500-MAJOR I-4) (MACH frv) FR-ACCESS)
+     "movfgq$pack $FRintk,$GRj"
+     (+ pack FRintk OP_03 (rs-null) OPE1_0F GRj)
+     (if (ne (index-of GRj) 0)
+        (sequence ()
+                  (set GRj FRintk)
+                  (set (reg h-gr (add (index-of GRj)    1))
+                       (reg h-fr_int (add (index-of FRintk) 1)))
+                  (set (reg h-gr (add (index-of GRj)    2))
+                       (reg h-fr_int (add (index-of FRintk) 2)))
+                  (set (reg h-gr (add (index-of GRj)    3))
+                       (reg h-fr_int (add (index-of FRintk) 3)))))
+     ()
+)
+
+(define-pmacro (conditional-register-transfer
+               name op ope reg_src reg_targ pipe attrs profile comment)
+  (dni name
+       (comment)
+       (.splice (UNIT pipe) CONDITIONAL FR-ACCESS (.unsplice attrs))
+       (.str name "$pack $" reg_src ",$" reg_targ ",$CCi,$cond")
+       (+ pack reg_targ op (rs-null) CCi cond ope reg_src)
+       (if (eq CCi (or cond 2))
+          (set reg_targ reg_src))
+       profile
+  )
+)
+
+(conditional-register-transfer cmovgf OP_69 OPE4_0 GRj FRintk I0
+                              ((FR500-MAJOR I-4) (FR550-MAJOR I-5)
+                               (FR400-MAJOR I-4) (FR450-MAJOR I-4))
+                              ((fr400 (unit u-gr2fr)) (fr450 (unit u-gr2fr))
+                               (fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr)))
+                              "transfer gr to fr")
+(conditional-register-transfer cmovfg OP_69 OPE4_2 FRintk GRj I0
+                              ((FR500-MAJOR I-4) (FR550-MAJOR I-5)
+                               (FR400-MAJOR I-4) (FR450-MAJOR I-4))
+                              ((fr400 (unit u-fr2gr)) (fr450 (unit u-fr2gr))
+                               (fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr)))
+                              "transfer fr to gr")
+
+
+(dni cmovgfd
+     "Conditional move GR to FR double"
+     ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5)
+      (FR400-MAJOR I-4) (FR450-MAJOR I-4) CONDITIONAL FR-ACCESS)
+     "cmovgfd$pack $GRj,$FRintk,$CCi,$cond"
+     (+ pack FRintk OP_69 (rs-null) CCi cond OPE4_1 GRj)
+     (register-transfer-double-from-gr-semantics (eq CCi (or cond 2)))
+     ; TODO -- doesn't handle extra registers in double
+     ((fr400 (unit u-gr2fr)) (fr450 (unit u-gr2fr))
+      (fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr)))
+)
+
+(dni cmovfgd
+     "Conditional move FR to GR double"
+     ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5)
+      (FR400-MAJOR I-4) (FR450-MAJOR I-4) CONDITIONAL FR-ACCESS)
+     "cmovfgd$pack $FRintk,$GRj,$CCi,$cond"
+     (+ pack FRintk OP_69 (rs-null) CCi cond OPE4_3 GRj)
+     (register-transfer-double-to-gr-semantics (eq CCi (or cond 2)))
+     ; TODO -- doesn't handle second register in the pair
+     ((fr400 (unit u-fr2gr)) (fr450 (unit u-fr2gr))
+      (fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr)))
+)
+
+(define-pmacro (register-transfer-spr
+               name op ope reg_src reg_targ unitname comment)
+  (dni name
+       (comment)
+       ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2)
+       (FR400-MAJOR C-2) (FR450-MAJOR C-2))
+       (.str name "$pack $" reg_src ",$" reg_targ)
+       (+ pack reg_targ op ope reg_src)
+       (set reg_targ reg_src)
+       ((fr400 (unit unitname)) (fr450 (unit unitname))
+       (fr500 (unit unitname)) (fr550 (unit unitname)))
+  )
+)
+
+(register-transfer-spr movgs OP_03 OPE1_06 GRj spr u-gr2spr "transfer gr->spr")
+(register-transfer-spr movsg OP_03 OPE1_07 spr GRj u-spr2gr "transfer spr->gr")
+
+; Integer Branch Conditions
+(define-pmacro (Inev cc) (const BI 0))
+(define-pmacro (Ira  cc) (const BI 1))
+(define-pmacro (Ieq  cc) (     zbit cc))
+(define-pmacro (Ine  cc) (not (zbit cc)))
+(define-pmacro (Ile  cc) (     orif (zbit cc) (xor (nbit cc) (vbit cc))))
+(define-pmacro (Igt  cc) (not (orif (zbit cc) (xor (nbit cc) (vbit cc)))))
+(define-pmacro (Ilt  cc) (     xor  (nbit cc) (vbit cc)))
+(define-pmacro (Ige  cc) (not (xor  (nbit cc) (vbit cc))))
+(define-pmacro (Ils  cc) (     orif (cbit cc) (zbit cc)))
+(define-pmacro (Ihi  cc) (not (orif (cbit cc) (zbit cc))))
+(define-pmacro (Ic   cc) (     cbit cc))
+(define-pmacro (Inc  cc) (not (cbit cc)))
+(define-pmacro (In   cc) (     nbit cc))
+(define-pmacro (Ip   cc) (not (nbit cc)))
+(define-pmacro (Iv   cc) (     vbit cc))
+(define-pmacro (Inv  cc) (not (vbit cc)))
+
+; Float Branch Conditions
+(define-pmacro (Fnev cc) (const BI 0))
+(define-pmacro (Fra  cc) (const BI 1))
+(define-pmacro (Fne  cc) (orif (lbit cc) (orif (gbit cc) (ubit cc))))
+(define-pmacro (Feq  cc) (ebit cc))
+(define-pmacro (Flg  cc) (orif (lbit cc) (gbit cc)))
+(define-pmacro (Fue  cc) (orif (ebit cc) (ubit cc)))
+(define-pmacro (Ful  cc) (orif (lbit cc) (ubit cc)))
+(define-pmacro (Fge  cc) (orif (ebit cc) (gbit cc)))
+(define-pmacro (Flt  cc) (lbit cc))
+(define-pmacro (Fuge cc) (orif (ebit cc) (orif (gbit cc) (ubit cc))))
+(define-pmacro (Fug  cc) (orif (gbit cc) (ubit cc)))
+(define-pmacro (Fle  cc) (orif (ebit cc) (lbit cc)))
+(define-pmacro (Fgt  cc) (gbit cc))
+(define-pmacro (Fule cc) (orif (ebit cc) (orif (lbit cc) (ubit cc))))
+(define-pmacro (Fu   cc) (ubit cc))
+(define-pmacro (Fo   cc) (orif (ebit cc) (orif (lbit cc) (gbit cc))))
+
+(define-pmacro (conditional-branch-i prefix cc op cond comment)
+  (dni (.sym prefix cc)
+       (comment)
+       ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1)
+       (FR400-MAJOR B-1) (FR450-MAJOR B-1))
+       (.str (.sym prefix cc) "$pack $ICCi_2,$hint,$label16")
+       (+ pack (.sym ICC_ cc) ICCi_2 op hint label16)
+       (sequence ()
+                (c-call VOID "@cpu@_model_branch" label16 hint)
+                (if (cond ICCi_2)
+                    (set pc label16)))
+       ((fr400 (unit u-branch)) (fr450 (unit u-branch))
+       (fr500 (unit u-branch)) (fr550 (unit u-branch)))
+  )
+)
+
+(dni bra
+     "integer branch equal"
+      ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1)
+       (FR400-MAJOR B-1) (FR450-MAJOR B-1))
+      "bra$pack $hint_taken$label16"
+      (+ pack ICC_ra (ICCi_2-null) OP_06 hint_taken label16)
+      (sequence ()
+               (c-call VOID "@cpu@_model_branch" label16 hint_taken)
+               (set pc label16))
+      ((fr400 (unit u-branch)) (fr450 (unit u-branch))
+       (fr500 (unit u-branch)) (fr550 (unit u-branch)))
+)
+
+(dni bno
+     "integer branch never"
+      ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1)
+       (FR400-MAJOR B-1) (FR450-MAJOR B-1))
+      "bno$pack$hint_not_taken"
+      (+ pack ICC_nev (ICCi_2-null) OP_06 hint_not_taken (label16-null))
+      (c-call VOID "@cpu@_model_branch" label16 hint_not_taken)
+      ((fr400 (unit u-branch)) (fr450 (unit u-branch))
+       (fr500 (unit u-branch)) (fr550 (unit u-branch)))
+)
+
+(conditional-branch-i b eq  OP_06 Ieq  "integer branch equal")
+(conditional-branch-i b ne  OP_06 Ine  "integer branch not equal")
+(conditional-branch-i b le  OP_06 Ile  "integer branch less or equal")
+(conditional-branch-i b gt  OP_06 Igt  "integer branch greater")
+(conditional-branch-i b lt  OP_06 Ilt  "integer branch less")
+(conditional-branch-i b ge  OP_06 Ige  "integer branch greater or equal")
+(conditional-branch-i b ls  OP_06 Ils  "integer branch less or equal unsigned")
+(conditional-branch-i b hi  OP_06 Ihi  "integer branch greater unsigned")
+(conditional-branch-i b c   OP_06 Ic   "integer branch carry set")
+(conditional-branch-i b nc  OP_06 Inc  "integer branch carry clear")
+(conditional-branch-i b n   OP_06 In   "integer branch negative")
+(conditional-branch-i b p   OP_06 Ip   "integer branch positive")
+(conditional-branch-i b v   OP_06 Iv   "integer branch overflow set")
+(conditional-branch-i b nv  OP_06 Inv  "integer branch overflow clear")
+
+(define-pmacro (conditional-branch-f prefix cc op cond comment)
+  (dni (.sym prefix cc)
+       (comment)
+       ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1)
+       (FR400-MAJOR B-1) (FR450-MAJOR B-1) FR-ACCESS)
+       (.str (.sym prefix cc) "$pack $FCCi_2,$hint,$label16")
+       (+ pack (.sym FCC_ cc) FCCi_2 op hint label16)
+       (sequence ()
+                (c-call VOID "@cpu@_model_branch" label16 hint)
+                (if (cond FCCi_2) (set pc label16)))
+       ((fr400 (unit u-branch)) (fr450 (unit u-branch))
+       (fr500 (unit u-branch)) (fr550 (unit u-branch)))
+  )
+)
+
+(dni fbra
+     "float branch equal"
+      ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1)
+       (FR400-MAJOR B-1) (FR450-MAJOR B-1) FR-ACCESS)
+      "fbra$pack $hint_taken$label16"
+      (+ pack FCC_ra (FCCi_2-null) OP_07 hint_taken label16)
+      (sequence ()
+               (c-call VOID "@cpu@_model_branch" label16 hint_taken)
+               (set pc label16))
+      ((fr400 (unit u-branch)) (fr450 (unit u-branch))
+       (fr500 (unit u-branch)) (fr550 (unit u-branch)))
+)
+
+(dni fbno
+     "float branch never"
+      ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1)
+       (FR400-MAJOR B-1) (FR450-MAJOR B-1) FR-ACCESS)
+      "fbno$pack$hint_not_taken"
+      (+ pack FCC_nev (FCCi_2-null) OP_07 hint_not_taken (label16-null))
+      (c-call VOID "@cpu@_model_branch" label16 hint_not_taken)
+      ((fr400 (unit u-branch)) (fr450 (unit u-branch))
+       (fr500 (unit u-branch)) (fr550 (unit u-branch)))
+)
+
+(conditional-branch-f fb ne  OP_07 Fne  "float branch not equal")
+(conditional-branch-f fb eq  OP_07 Feq  "float branch equal")
+(conditional-branch-f fb lg  OP_07 Flg  "float branch less or greater")
+(conditional-branch-f fb ue  OP_07 Fue  "float branch unordered or equal")
+(conditional-branch-f fb ul  OP_07 Ful  "float branch unordered or less")
+(conditional-branch-f fb ge  OP_07 Fge  "float branch greater or equal")
+(conditional-branch-f fb lt  OP_07 Flt  "float branch less")
+(conditional-branch-f fb uge OP_07 Fuge "float branch unordered, greater,equal")
+(conditional-branch-f fb ug  OP_07 Fug  "float branch unordered or greater")
+(conditional-branch-f fb le  OP_07 Fle  "float branch less or equal")
+(conditional-branch-f fb gt  OP_07 Fgt  "float branch greater")
+(conditional-branch-f fb ule OP_07 Fule "float branch unordered, less or equal")
+(conditional-branch-f fb u   OP_07 Fu   "float branch unordered")
+(conditional-branch-f fb o   OP_07 Fo   "float branch ordered")
+
+(define-pmacro (ctrlr-branch-semantics cond ccond)
+  (sequence ((SI tmp))
+           (set tmp (sub (spr-lcr) 1))
+           (set (spr-lcr) tmp)
+           (if cond
+               (if (eq ccond 0)
+                   (if (ne tmp 0)
+                       (set pc (spr-lr)))
+                   (if (eq tmp 0)
+                       (set pc (spr-lr))))))
+)
+
+(dni bctrlr
+     "LCR conditional branch to lr"
+     ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2)
+      (FR400-MAJOR B-2) (FR450-MAJOR B-2))
+     ("bctrlr$pack $ccond,$hint")
+     (+ pack (cond-null) (ICCi_2-null) OP_0E hint OPE3_01 ccond (s12-null))
+     (sequence ()
+              (c-call VOID "@cpu@_model_branch" (spr-lr) hint)
+              (ctrlr-branch-semantics (const BI 1) ccond))
+     ((fr400 (unit u-branch)) (fr450 (unit u-branch))
+      (fr500 (unit u-branch)) (fr550 (unit u-branch)))
+)
+
+(define-pmacro (conditional-branch-cclr prefix cc i-f op ope cond attr comment)
+  (dni (.sym prefix cc lr)
+       (comment)
+       ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3)
+       (FR400-MAJOR B-3) (FR450-MAJOR B-3) attr)
+       (.str (.sym prefix cc lr) "$pack $" i-f "CCi_2,$hint")
+       (+ pack (.sym i-f CC_ cc) (.sym i-f CCi_2) op hint ope
+         (ccond-null) (s12-null))
+       (sequence ()
+                (c-call VOID "@cpu@_model_branch" (spr-lr) hint)
+                (if (cond (.sym i-f CCi_2)) (set pc (spr-lr))))
+       ((fr400 (unit u-branch)) (fr450 (unit u-branch))
+       (fr500 (unit u-branch)) (fr550 (unit u-branch)))
+  )
+)
+
+(dni bralr
+     "integer cclr branch always"
+     ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3)
+      (FR400-MAJOR B-3) (FR450-MAJOR B-3))
+     "bralr$pack$hint_taken"
+     (+ pack ICC_ra (ICCi_2-null) OP_0E hint_taken OPE3_02 (ccond-null) (s12-null))
+     (sequence ()
+              (c-call VOID "@cpu@_model_branch" (spr-lr) hint_taken)
+              (set pc (spr-lr)))
+     ((fr400 (unit u-branch)) (fr450 (unit u-branch))
+      (fr500 (unit u-branch)) (fr550 (unit u-branch)))
+)
+
+(dni bnolr
+     "integer cclr branch never"
+     ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3)
+      (FR400-MAJOR B-3) (FR450-MAJOR B-3))
+     "bnolr$pack$hint_not_taken"
+     (+ pack ICC_nev (ICCi_2-null) OP_0E hint_not_taken OPE3_02 (ccond-null) (s12-null))
+     (c-call VOID "@cpu@_model_branch" (spr-lr) hint_not_taken)
+     ((fr400 (unit u-branch)) (fr450 (unit u-branch))
+      (fr500 (unit u-branch)) (fr550 (unit u-branch)))
+)
+
+(conditional-branch-cclr b eq  I OP_0E OPE3_02 Ieq  NA "integer cclr branch equal")
+(conditional-branch-cclr b ne  I OP_0E OPE3_02 Ine  NA "integer cclr branch not equal")
+(conditional-branch-cclr b le  I OP_0E OPE3_02 Ile  NA "integer cclr branch less or equal")
+(conditional-branch-cclr b gt  I OP_0E OPE3_02 Igt  NA "integer cclr branch greater")
+(conditional-branch-cclr b lt  I OP_0E OPE3_02 Ilt  NA "integer cclr branch less")
+(conditional-branch-cclr b ge  I OP_0E OPE3_02 Ige  NA "integer cclr branch greater or equal")
+(conditional-branch-cclr b ls  I OP_0E OPE3_02 Ils  NA "integer cclr branch less or equal unsigned")
+(conditional-branch-cclr b hi  I OP_0E OPE3_02 Ihi  NA "integer cclr branch greater unsigned")
+(conditional-branch-cclr b c   I OP_0E OPE3_02 Ic   NA "integer cclr branch carry set")
+(conditional-branch-cclr b nc  I OP_0E OPE3_02 Inc  NA "integer cclr branch carry clear")
+(conditional-branch-cclr b n   I OP_0E OPE3_02 In   NA "integer cclr branch negative")
+(conditional-branch-cclr b p   I OP_0E OPE3_02 Ip   NA "integer cclr branch positive")
+(conditional-branch-cclr b v   I OP_0E OPE3_02 Iv   NA "integer cclr branch overflow set")
+(conditional-branch-cclr b nv  I OP_0E OPE3_02 Inv  NA "integer cclr branch overflow clear")
+
+(dni fbralr
+     "float cclr branch always"
+     ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3)
+      (FR400-MAJOR B-3) (FR450-MAJOR B-3) FR-ACCESS)
+     "fbralr$pack$hint_taken"
+     (+ pack FCC_ra (FCCi_2-null) OP_0E hint_taken OPE3_06 (ccond-null) (s12-null))
+     (sequence ()
+              (c-call VOID "@cpu@_model_branch" (spr-lr) hint_taken)
+              (set pc (spr-lr)))
+     ((fr400 (unit u-branch)) (fr450 (unit u-branch))
+      (fr500 (unit u-branch)) (fr550 (unit u-branch)))
+)
+
+(dni fbnolr
+     "float cclr branch never"
+     ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3)
+      (FR400-MAJOR B-3) (FR450-MAJOR B-3) FR-ACCESS)
+     "fbnolr$pack$hint_not_taken"
+     (+ pack FCC_nev (FCCi_2-null) OP_0E hint_not_taken OPE3_06 (ccond-null) (s12-null))
+     (c-call VOID "@cpu@_model_branch" (spr-lr) hint_not_taken)
+     ((fr400 (unit u-branch)) (fr450 (unit u-branch))
+      (fr500 (unit u-branch)) (fr550 (unit u-branch)))
+)
+
+(conditional-branch-cclr fb eq  F OP_0E OPE3_06 Feq  FR-ACCESS "float cclr branch equal")
+(conditional-branch-cclr fb ne  F OP_0E OPE3_06 Fne  FR-ACCESS "float cclr branch not equal")
+(conditional-branch-cclr fb lg  F OP_0E OPE3_06 Flg  FR-ACCESS "float branch less or greater")
+(conditional-branch-cclr fb ue  F OP_0E OPE3_06 Fue  FR-ACCESS "float branch unordered or equal")
+(conditional-branch-cclr fb ul  F OP_0E OPE3_06 Ful  FR-ACCESS "float branch unordered or less")
+(conditional-branch-cclr fb ge  F OP_0E OPE3_06 Fge  FR-ACCESS "float branch greater or equal")
+(conditional-branch-cclr fb lt  F OP_0E OPE3_06 Flt  FR-ACCESS "float branch less")
+(conditional-branch-cclr fb uge F OP_0E OPE3_06 Fuge FR-ACCESS "float branch unordered, greater, equal")
+(conditional-branch-cclr fb ug  F OP_0E OPE3_06 Fug  FR-ACCESS "float branch unordered or greater")
+(conditional-branch-cclr fb le  F OP_0E OPE3_06 Fle  FR-ACCESS "float branch less or equal")
+(conditional-branch-cclr fb gt  F OP_0E OPE3_06 Fgt  FR-ACCESS "float branch greater")
+(conditional-branch-cclr fb ule F OP_0E OPE3_06 Fule FR-ACCESS "float branch unordered, less or equal")
+(conditional-branch-cclr fb u   F OP_0E OPE3_06 Fu   FR-ACCESS "float branch unordered")
+(conditional-branch-cclr fb o   F OP_0E OPE3_06 Fo   FR-ACCESS "float branch ordered")
+
+(define-pmacro (conditional-branch-ctrlr prefix cc i-f op ope cond attr comment)
+  (dni (.sym prefix cc lr)
+       (comment)
+       ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2)
+       (FR400-MAJOR B-2) (FR450-MAJOR B-2) attr)
+       (.str (.sym prefix cc lr) "$pack $" i-f "CCi_2,$ccond,$hint")
+       (+ pack (.sym i-f CC_ cc) (.sym i-f CCi_2) op hint ope ccond (s12-null))
+       (sequence ()
+                (c-call VOID "@cpu@_model_branch" (spr-lr) hint)
+                (ctrlr-branch-semantics (cond (.sym i-f CCi_2)) ccond))
+       ((fr400 (unit u-branch)) (fr450 (unit u-branch))
+       (fr500 (unit u-branch)) (fr550 (unit u-branch)))
+  )
+)
+
+(dni bcralr
+     "integer ctrlr branch always"
+     ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2)
+      (FR400-MAJOR B-2) (FR450-MAJOR B-2))
+     "bcralr$pack $ccond$hint_taken"
+     (+ pack ICC_ra (ICCi_2-null) OP_0E hint_taken OPE3_03 ccond (s12-null))
+     (sequence ()
+              (c-call VOID "@cpu@_model_branch" (spr-lr) hint_taken)
+              (ctrlr-branch-semantics (const BI 1) ccond))
+     ((fr400 (unit u-branch)) (fr450 (unit u-branch))
+      (fr500 (unit u-branch)) (fr550 (unit u-branch)))
+)
+
+(dni bcnolr
+     "integer ctrlr branch never"
+     ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2)
+      (FR400-MAJOR B-2) (FR450-MAJOR B-2))
+     "bcnolr$pack$hint_not_taken"
+     (+ pack ICC_nev (ICCi_2-null) OP_0E hint_not_taken OPE3_03 (ccond-null) (s12-null))
+     (sequence ()
+              (c-call VOID "@cpu@_model_branch" (spr-lr) hint_not_taken)
+              (ctrlr-branch-semantics (const BI 0) ccond))
+     ((fr400 (unit u-branch)) (fr450 (unit u-branch))
+      (fr500 (unit u-branch)) (fr550 (unit u-branch)))
+)
+
+(conditional-branch-ctrlr bc eq  I OP_0E OPE3_03 Ieq  NA "integer ctrlr branch equal")
+(conditional-branch-ctrlr bc ne  I OP_0E OPE3_03 Ine  NA "integer ctrlr branch not equal")
+(conditional-branch-ctrlr bc le  I OP_0E OPE3_03 Ile  NA "integer ctrlr branch less equal")
+(conditional-branch-ctrlr bc gt  I OP_0E OPE3_03 Igt  NA "integer ctrlr branch greater")
+(conditional-branch-ctrlr bc lt  I OP_0E OPE3_03 Ilt  NA "integer ctrlr branch less")
+(conditional-branch-ctrlr bc ge  I OP_0E OPE3_03 Ige  NA "integer ctrlr branch greater equal")
+(conditional-branch-ctrlr bc ls  I OP_0E OPE3_03 Ils  NA "integer ctrlr branch less equal unsigned")
+(conditional-branch-ctrlr bc hi  I OP_0E OPE3_03 Ihi  NA "integer ctrlr branch greater unsigned")
+(conditional-branch-ctrlr bc c   I OP_0E OPE3_03 Ic   NA "integer ctrlr branch carry set")
+(conditional-branch-ctrlr bc nc  I OP_0E OPE3_03 Inc  NA "integer ctrlr branch carry clear")
+(conditional-branch-ctrlr bc n   I OP_0E OPE3_03 In   NA "integer ctrlr branch negative")
+(conditional-branch-ctrlr bc p   I OP_0E OPE3_03 Ip   NA "integer ctrlr branch positive")
+(conditional-branch-ctrlr bc v   I OP_0E OPE3_03 Iv   NA "integer ctrlr branch overflow set")
+(conditional-branch-ctrlr bc nv  I OP_0E OPE3_03 Inv  NA "integer ctrlr branch overflow clear")
+
+(dni fcbralr
+     "float ctrlr branch always"
+     ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2)
+      (FR400-MAJOR B-2) (FR450-MAJOR B-2) FR-ACCESS)
+     "fcbralr$pack $ccond$hint_taken"
+     (+ pack FCC_ra (FCCi_2-null) OP_0E hint_taken OPE3_07 ccond (s12-null))
+     (sequence ()
+              (c-call VOID "@cpu@_model_branch" (spr-lr) hint_taken)
+              (ctrlr-branch-semantics (const BI 1) ccond))
+     ((fr400 (unit u-branch)) (fr450 (unit u-branch))
+      (fr500 (unit u-branch)) (fr550 (unit u-branch)))
+)
+
+(dni fcbnolr
+     "float ctrlr branch never"
+     ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2)
+      (FR400-MAJOR B-2) (FR450-MAJOR B-2) FR-ACCESS)
+     "fcbnolr$pack$hint_not_taken"
+     (+ pack FCC_nev (FCCi_2-null) OP_0E hint_not_taken OPE3_07 (ccond-null) (s12-null))
+     (sequence ()
+              (c-call VOID "@cpu@_model_branch" (spr-lr) hint_not_taken)
+              (ctrlr-branch-semantics (const BI 0) ccond))
+     ((fr400 (unit u-branch)) (fr450 (unit u-branch))
+      (fr500 (unit u-branch)) (fr550 (unit u-branch)))
+)
+
+(conditional-branch-ctrlr fcb eq  F OP_0E OPE3_07 Feq  FR-ACCESS "float cclr branch equal")
+(conditional-branch-ctrlr fcb ne  F OP_0E OPE3_07 Fne  FR-ACCESS "float cclr branch not equal")
+(conditional-branch-ctrlr fcb lg  F OP_0E OPE3_07 Flg  FR-ACCESS "float branch less or greater")
+(conditional-branch-ctrlr fcb ue  F OP_0E OPE3_07 Fue  FR-ACCESS "float branch unordered or equal")
+(conditional-branch-ctrlr fcb ul  F OP_0E OPE3_07 Ful  FR-ACCESS "float branch unordered or less")
+(conditional-branch-ctrlr fcb ge  F OP_0E OPE3_07 Fge  FR-ACCESS "float branch greater or equal")
+(conditional-branch-ctrlr fcb lt  F OP_0E OPE3_07 Flt  FR-ACCESS "float branch less")
+(conditional-branch-ctrlr fcb uge F OP_0E OPE3_07 Fuge FR-ACCESS "float branch unordered, greater, equal")
+(conditional-branch-ctrlr fcb ug  F OP_0E OPE3_07 Fug  FR-ACCESS "float branch unordered or greater")
+(conditional-branch-ctrlr fcb le  F OP_0E OPE3_07 Fle  FR-ACCESS "float branch less or equal")
+(conditional-branch-ctrlr fcb gt  F OP_0E OPE3_07 Fgt  FR-ACCESS "float branch greater")
+(conditional-branch-ctrlr fcb ule F OP_0E OPE3_07 Fule FR-ACCESS "float branch unordered, less or equal")
+(conditional-branch-ctrlr fcb u   F OP_0E OPE3_07 Fu   FR-ACCESS "float branch unordered")
+(conditional-branch-ctrlr fcb o   F OP_0E OPE3_07 Fo   FR-ACCESS "float branch ordered")
+
+(define-pmacro (jump-and-link-semantics base offset LI)
+  (sequence ()
+           (if (eq LI 1)
+               (c-call VOID "@cpu@_set_write_next_vliw_addr_to_LR" 1))
+           ; Target address gets aligned here
+           (set pc (and (add base offset) #xfffffffc))
+           (c-call VOID "@cpu@_model_branch" pc #x2)) ; hint branch taken
+)
+
+(dni jmpl
+     "jump and link"
+     ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6)
+      (FR400-MAJOR I-5) (FR450-MAJOR I-5))
+     "jmpl$pack @($GRi,$GRj)"
+     (+ pack (misc-null-1) (LI-off) OP_0C GRi (misc-null-2) GRj)
+     (jump-and-link-semantics GRi GRj LI)
+     ((fr400 (unit u-branch)) (fr450 (unit u-branch))
+      (fr500 (unit u-branch)) (fr550 (unit u-branch)))
+)
+
+(dann callann "call annotation" SI "call_annotation" "at")
+
+(dni calll
+     "call and link"
+     ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6)
+      (FR400-MAJOR I-5) (FR450-MAJOR I-5))
+     "calll$pack $callann($GRi,$GRj)"
+     (+ pack (misc-null-1) (LI-on) OP_0C GRi (misc-null-2) GRj)
+     (jump-and-link-semantics GRi GRj LI)
+     ((fr400 (unit u-branch)) (fr450 (unit u-branch))
+      (fr500 (unit u-branch)) (fr550 (unit u-branch)))
+)
+
+(dni jmpil
+     "jump immediate and link"
+     ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6)
+      (FR400-MAJOR I-5) (FR450-MAJOR I-5))
+     "jmpil$pack @($GRi,$s12)"
+     (+ pack (misc-null-1) (LI-off) OP_0D GRi s12)
+     (jump-and-link-semantics GRi s12 LI)
+     ((fr400 (unit u-branch)) (fr450 (unit u-branch))
+      (fr500 (unit u-branch)) (fr550 (unit u-branch)))
+)
+
+(dni callil
+     "call immediate and link"
+     ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6)
+      (FR400-MAJOR I-5) (FR450-MAJOR I-5))
+     "callil$pack @($GRi,$s12)"
+     (+ pack (misc-null-1) (LI-on) OP_0D GRi s12)
+     (jump-and-link-semantics GRi s12 LI)
+     ((fr400 (unit u-branch)) (fr450 (unit u-branch))
+      (fr500 (unit u-branch)) (fr550 (unit u-branch)))
+)
+
+(dni call
+     "call and link"
+     ((UNIT B0) (FR500-MAJOR B-4) (FR550-MAJOR B-4)
+      (FR400-MAJOR B-4) (FR450-MAJOR B-4))
+     "call$pack $label24"
+     (+ pack OP_0F label24)
+     (sequence ()
+              (c-call VOID "@cpu@_set_write_next_vliw_addr_to_LR" 1)
+              (set pc label24)
+              (c-call VOID "@cpu@_model_branch" pc #x2)) ; hint branch taken
+     ((fr400 (unit u-branch)) (fr450 (unit u-branch))
+      (fr500 (unit u-branch)) (fr550 (unit u-branch)))
+)
+
+(dni rett
+    "return from trap"
+    ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2)
+     (FR400-MAJOR C-2) (FR450-MAJOR C-2) PRIVILEGED)
+    "rett$pack $debug"
+    (+ pack (misc-null-1) debug OP_05 (rs-null) (s12-null))
+    ; frv_rett handles operating vs user mode
+    (sequence ()
+             (set pc (c-call UWI "frv_rett" pc debug))
+             (c-call VOID "@cpu@_model_branch" pc #x2)) ; hint branch taken
+    ()
+)
+
+(dni rei
+     "run exception instruction"
+     ((UNIT C) (FR500-MAJOR C-1) (MACH frv) PRIVILEGED)
+     "rei$pack $eir"
+     (+ pack (rd-null) OP_37 eir (s12-null))
+     (nop) ; for now
+     ()
+)
+
+(define-pmacro (trap-semantics cond base offset)
+  (if cond
+      (sequence ()
+               ; This is defered to frv_itrap because for the breakpoint
+               ; case we want to change as little of the machine state as
+               ; possible.
+               ;
+               ; PCSR=PC
+               ; PSR.PS=PSR.S
+               ; PSR.ET=0
+               ; if PSR.ESR==1
+               ;   SR0 through SR3=GR4 through GR7
+               ; TBR.TT=0x80 + ((GRi + s12) & 0x7f)
+               ; PC=TBR
+               ; We still should indicate what is modified by this insn.
+               (clobber (spr-pcsr))
+               (clobber psr_ps)
+               (clobber psr_et)
+               (clobber tbr_tt)
+               (if (ne psr_esr (const 0))
+                   (sequence ()
+                             (clobber (spr-sr0))
+                             (clobber (spr-sr1))
+                             (clobber (spr-sr2))
+                             (clobber (spr-sr3))))
+               ; frv_itrap handles operating vs user mode
+               (c-call VOID "frv_itrap" pc base offset)))
+)
+
+(define-pmacro (trap-r prefix cc i-f op ope cond attr comment)
+  (dni (.sym prefix cc)
+       (comment)
+       ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1)
+       (FR400-MAJOR C-1) (FR450-MAJOR C-1) attr)
+       (.str (.sym prefix cc) "$pack $" i-f "CCi_2,$GRi,$GRj")
+       (+ pack (.sym i-f CC_ cc) (.sym i-f CCi_2) op GRi (misc-null-3) ope GRj)
+       (trap-semantics (cond (.sym i-f CCi_2)) GRi GRj)
+       ((fr400 (unit u-trap)) (fr450 (unit u-trap))
+       (fr500 (unit u-trap)) (fr550 (unit u-trap)))
+  )
+)
+
+(dni tra
+     "integer trap always"
+     ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1)
+      (FR400-MAJOR C-1) (FR450-MAJOR C-1))
+     "tra$pack $GRi,$GRj"
+     (+ pack ICC_ra (ICCi_2-null) OP_04 GRi (misc-null-3) OPE4_0 GRj)
+     (trap-semantics (const BI 1) GRi GRj)
+     ((fr400 (unit u-trap)) (fr450 (unit u-trap))
+      (fr500 (unit u-trap)) (fr550 (unit u-trap)))
+)
+
+(dni tno
+     "integer trap never"
+     ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1)
+      (FR400-MAJOR C-1) (FR450-MAJOR C-1))
+     "tno$pack"
+     (+ pack ICC_nev (ICCi_2-null) OP_04 (GRi-null) (misc-null-3) OPE4_0 (GRj-null))
+     (trap-semantics (const BI 0) GRi GRj)
+     ((fr400 (unit u-trap)) (fr450 (unit u-trap))
+      (fr500 (unit u-trap)) (fr550 (unit u-trap)))
+)
+
+(trap-r t eq  I OP_04 OPE4_0 Ieq  NA "integer trap equal")
+(trap-r t ne  I OP_04 OPE4_0 Ine  NA "integer trap not equal")
+(trap-r t le  I OP_04 OPE4_0 Ile  NA "integer trap less or equal")
+(trap-r t gt  I OP_04 OPE4_0 Igt  NA "integer trap greater")
+(trap-r t lt  I OP_04 OPE4_0 Ilt  NA "integer trap less")
+(trap-r t ge  I OP_04 OPE4_0 Ige  NA "integer trap greater or equal")
+(trap-r t ls  I OP_04 OPE4_0 Ils  NA "integer trap less or equal unsigned")
+(trap-r t hi  I OP_04 OPE4_0 Ihi  NA "integer trap greater unsigned")
+(trap-r t c   I OP_04 OPE4_0 Ic   NA "integer trap carry set")
+(trap-r t nc  I OP_04 OPE4_0 Inc  NA "integer trap carry clear")
+(trap-r t n   I OP_04 OPE4_0 In   NA "integer trap negative")
+(trap-r t p   I OP_04 OPE4_0 Ip   NA "integer trap positive")
+(trap-r t v   I OP_04 OPE4_0 Iv   NA "integer trap overflow set")
+(trap-r t nv  I OP_04 OPE4_0 Inv  NA "integer trap overflow clear")
+
+(dni ftra
+     "float trap always"
+     ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1)
+      (FR400-MAJOR C-1) (FR450-MAJOR C-1) FR-ACCESS)
+     "ftra$pack $GRi,$GRj"
+     (+ pack FCC_ra (FCCi_2-null) OP_04 GRi (misc-null-3) OPE4_1 GRj)
+     (trap-semantics (const BI 1) GRi GRj)
+     ((fr400 (unit u-trap)) (fr450 (unit u-trap))
+      (fr500 (unit u-trap)) (fr550 (unit u-trap)))
+)
+
+(dni ftno
+     "flost trap never"
+     ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1)
+      (FR400-MAJOR C-1) (FR450-MAJOR C-1) FR-ACCESS)
+     "ftno$pack"
+     (+ pack FCC_nev (FCCi_2-null) OP_04 (GRi-null) (misc-null-3) OPE4_1 (GRj-null))
+     (trap-semantics (const BI 0) GRi GRj)
+     ((fr400 (unit u-trap)) (fr450 (unit u-trap))
+      (fr500 (unit u-trap)) (fr550 (unit u-trap)))
+)
+
+(trap-r ft ne  F OP_04 OPE4_1 Fne  FR-ACCESS "float trap not equal")
+(trap-r ft eq  F OP_04 OPE4_1 Feq  FR-ACCESS "float trap equal")
+(trap-r ft lg  F OP_04 OPE4_1 Flg  FR-ACCESS "float trap greater or less")
+(trap-r ft ue  F OP_04 OPE4_1 Fue  FR-ACCESS "float trap unordered or equal")
+(trap-r ft ul  F OP_04 OPE4_1 Ful  FR-ACCESS "float trap unordered or less")
+(trap-r ft ge  F OP_04 OPE4_1 Fge  FR-ACCESS "float trap greater or equal")
+(trap-r ft lt  F OP_04 OPE4_1 Flt  FR-ACCESS "float trap less")
+(trap-r ft uge F OP_04 OPE4_1 Fuge FR-ACCESS "float trap unordered greater or equal")
+(trap-r ft ug  F OP_04 OPE4_1 Fug  FR-ACCESS "float trap unordered or greater")
+(trap-r ft le  F OP_04 OPE4_1 Fle  FR-ACCESS "float trap less or equal")
+(trap-r ft gt  F OP_04 OPE4_1 Fgt  FR-ACCESS "float trap greater")
+(trap-r ft ule F OP_04 OPE4_1 Fule FR-ACCESS "float trap unordered less or equal")
+(trap-r ft u   F OP_04 OPE4_1 Fu   FR-ACCESS "float trap unordered")
+(trap-r ft o   F OP_04 OPE4_1 Fo   FR-ACCESS "float trap ordered")
+
+(define-pmacro (trap-immed prefix cc i-f op cond attr comment)
+  (dni (.sym prefix cc)
+       (comment)
+       ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1)
+       (FR400-MAJOR C-1) (FR450-MAJOR C-1) attr)
+       (.str (.sym prefix cc) "$pack $" i-f "CCi_2,$GRi,$s12")
+       (+ pack (.sym i-f CC_ cc) (.sym i-f CCi_2) op GRi s12)
+       (trap-semantics (cond (.sym i-f CCi_2)) GRi s12)
+       ((fr400 (unit u-trap)) (fr450 (unit u-trap))
+       (fr500 (unit u-trap)) (fr550 (unit u-trap)))
+  )
+)
+
+(dni tira
+     "integer trap always"
+     ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1)
+      (FR400-MAJOR C-1) (FR450-MAJOR C-1))
+     "tira$pack $GRi,$s12"
+     (+ pack ICC_ra (ICCi_2-null) OP_1C GRi s12)
+     (trap-semantics (const BI 1) GRi s12)
+     ((fr400 (unit u-trap)) (fr450 (unit u-trap))
+      (fr500 (unit u-trap)) (fr550 (unit u-trap)))
+)
+
+(dni tino
+     "integer trap never"
+     ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1)
+      (FR400-MAJOR C-1) (FR450-MAJOR C-1))
+     "tino$pack"
+     (+ pack ICC_nev (ICCi_2-null) OP_1C (GRi-null) (s12-null))
+     (trap-semantics (const BI 0) GRi s12)
+     ((fr400 (unit u-trap)) (fr450 (unit u-trap))
+      (fr500 (unit u-trap)) (fr550 (unit u-trap)))
+)
+
+(trap-immed ti eq  I OP_1C Ieq  NA "integer trap equal")
+(trap-immed ti ne  I OP_1C Ine  NA "integer trap not equal")
+(trap-immed ti le  I OP_1C Ile  NA "integer trap less or equal")
+(trap-immed ti gt  I OP_1C Igt  NA "integer trap greater")
+(trap-immed ti lt  I OP_1C Ilt  NA "integer trap less")
+(trap-immed ti ge  I OP_1C Ige  NA "integer trap greater or equal")
+(trap-immed ti ls  I OP_1C Ils  NA "integer trap less or equal unsigned")
+(trap-immed ti hi  I OP_1C Ihi  NA "integer trap greater unsigned")
+(trap-immed ti c   I OP_1C Ic   NA "integer trap carry set")
+(trap-immed ti nc  I OP_1C Inc  NA "integer trap carry clear")
+(trap-immed ti n   I OP_1C In   NA "integer trap negative")
+(trap-immed ti p   I OP_1C Ip   NA "integer trap positive")
+(trap-immed ti v   I OP_1C Iv   NA "integer trap overflow set")
+(trap-immed ti nv  I OP_1C Inv  NA "integer trap overflow clear")
+
+(dni ftira
+     "float trap always"
+     ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1)
+      (FR400-MAJOR C-1) (FR450-MAJOR C-1) FR-ACCESS)
+     "ftira$pack $GRi,$s12"
+     (+ pack FCC_ra (ICCi_2-null) OP_1D GRi s12)
+     (trap-semantics (const BI 1) GRi s12)
+     ((fr400 (unit u-trap))
+      (fr500 (unit u-trap)) (fr550 (unit u-trap)))
+)
+
+(dni ftino
+     "float trap never"
+     ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1)
+      (FR400-MAJOR C-1) (FR450-MAJOR C-1) FR-ACCESS)
+     "ftino$pack"
+     (+ pack FCC_nev (FCCi_2-null) OP_1D (GRi-null) (s12-null))
+     (trap-semantics (const BI 0) GRi s12)
+     ((fr400 (unit u-trap)) (fr450 (unit u-trap))
+      (fr500 (unit u-trap)) (fr550 (unit u-trap)))
+)
+
+(trap-immed fti ne  F OP_1D Fne  FR-ACCESS "float trap not equal")
+(trap-immed fti eq  F OP_1D Feq  FR-ACCESS "float trap equal")
+(trap-immed fti lg  F OP_1D Flg  FR-ACCESS "float trap greater or less")
+(trap-immed fti ue  F OP_1D Fue  FR-ACCESS "float trap unordered or equal")
+(trap-immed fti ul  F OP_1D Ful  FR-ACCESS "float trap unordered or less")
+(trap-immed fti ge  F OP_1D Fge  FR-ACCESS "float trap greater or equal")
+(trap-immed fti lt  F OP_1D Flt  FR-ACCESS "float trap less")
+(trap-immed fti uge F OP_1D Fuge FR-ACCESS "float trap unordered greater or equal")
+(trap-immed fti ug  F OP_1D Fug  FR-ACCESS "float trap unordered or greater")
+(trap-immed fti le  F OP_1D Fle  FR-ACCESS "float trap less or equal")
+(trap-immed fti gt  F OP_1D Fgt  FR-ACCESS "float trap greater")
+(trap-immed fti ule F OP_1D Fule FR-ACCESS "float trap unordered less or equal")
+(trap-immed fti u   F OP_1D Fu   FR-ACCESS "float trap unordered")
+(trap-immed fti o   F OP_1D Fo   FR-ACCESS "float trap ordered")
+
+(dni break
+     "break trap"
+     ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1)
+      (FR400-MAJOR C-1) (FR450-MAJOR C-1))
+     "break$pack"
+     (+ pack (rd-null) OP_04 (rs-null) (misc-null-3) OPE4_3 (GRj-null))
+     (sequence ()
+              ; This is defered to frv_break because for the breakpoint
+              ; case we want to change as little of the machine state as
+              ; possible.
+              ;
+              ; BPCSR=PC
+              ; BPSR.BS=PSR.S
+              ; BPSR.BET=PSR.ET
+              ; PSR.S=1
+              ; PSR.ET=0
+              ; TBR.TT=0xff
+              ; PC=TBR
+              ; We still should indicate what is modified by this insn.
+              (clobber (spr-bpcsr))
+              (clobber bpsr_bs)
+              (clobber bpsr_bet)
+              (clobber psr_s)
+              (clobber psr_et)
+              (clobber tbr_tt)
+              (c-call VOID "frv_break"))
+     ()
+)
+
+(dni mtrap
+     "media trap"
+     ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1)
+      (FR400-MAJOR C-1) (FR450-MAJOR C-1) FR-ACCESS)
+     "mtrap$pack"
+     (+ pack (rd-null) OP_04 (rs-null) (misc-null-3) OPE4_2 (GRj-null))
+     (c-call VOID "frv_mtrap")
+     ()
+)
+
+(define-pmacro (condition-code-logic name operation ope comment)
+  (dni name
+       (comment)
+       ((UNIT B01) (FR500-MAJOR B-6) (FR550-MAJOR B-6)
+       (FR400-MAJOR B-6) (FR450-MAJOR B-6))
+       (.str name "$pack $CRi,$CRj,$CRk")
+       (+ pack (misc-null-6) CRk OP_0A (misc-null-7) CRi ope (misc-null-8) CRj)
+       (set CRk (c-call UQI "@cpu@_cr_logic" operation CRi CRj))
+       ()
+  )
+)
+(define-pmacro (op-andcr)   0)
+(define-pmacro (op-orcr)    1)
+(define-pmacro (op-xorcr)   2)
+(define-pmacro (op-nandcr)  3)
+(define-pmacro (op-norcr)   4)
+(define-pmacro (op-andncr)  5)
+(define-pmacro (op-orncr)   6)
+(define-pmacro (op-nandncr) 7)
+(define-pmacro (op-norncr)  8)
+
+(define-pmacro (cr-true)  3)
+(define-pmacro (cr-false) 2)
+(define-pmacro (cr-undefined) 0)
+
+(condition-code-logic andcr   (op-andcr)   OPE1_08 "and   condition code regs")
+(condition-code-logic orcr    (op-orcr)    OPE1_09 "or    condition code regs")
+(condition-code-logic xorcr   (op-xorcr)   OPE1_0A "xor   condition code regs")
+(condition-code-logic nandcr  (op-nandcr)  OPE1_0C "nand  condition code regs")
+(condition-code-logic norcr   (op-norcr)   OPE1_0D "nor   condition code regs")
+(condition-code-logic andncr  (op-andncr)  OPE1_10 "andn  condition code regs")
+(condition-code-logic orncr   (op-orncr)   OPE1_11 "orn   condition code regs")
+(condition-code-logic nandncr (op-nandncr) OPE1_14 "nandn condition code regs")
+(condition-code-logic norncr  (op-norncr)  OPE1_15 "norn  condition code regs")
+
+(dni notcr
+     ("not cccr register")
+     ((UNIT B01) (FR500-MAJOR B-6) (FR550-MAJOR B-6)
+      (FR400-MAJOR B-6) (FR450-MAJOR B-6))
+     (.str notcr "$pack $CRj,$CRk")
+     (+ pack (misc-null-6) CRk OP_0A (rs-null) OPE1_0B (misc-null-8) CRj)
+     (set CRk (xor CRj 1))
+     ()
+)
+
+(define-pmacro (check-semantics cond cr)
+  (if cond (set cr (cr-true)) (set cr (cr-false)))
+)
+
+(define-pmacro (check-int-condition-code prefix cc op cond comment)
+  (dni (.sym prefix cc)
+       (comment)
+       ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5)
+       (FR400-MAJOR B-5) (FR450-MAJOR B-5))
+       (.str (.sym prefix cc) "$pack $ICCi_3,$CRj_int")
+       (+ pack (.sym ICC_ cc) CRj_int op (misc-null-5) ICCi_3)
+       (check-semantics (cond ICCi_3) CRj_int)
+       ((fr400 (unit u-check)) (fr450 (unit u-check))
+       (fr500 (unit u-check)) (fr550 (unit u-check)))
+  )
+)
+
+(dni ckra
+     "check integer cc always"
+     ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5)
+      (FR400-MAJOR B-5) (FR450-MAJOR B-5))
+     "ckra$pack $CRj_int"
+     (+ pack ICC_ra CRj_int OP_08 (misc-null-5) (ICCi_3-null))
+     (check-semantics (const BI 1) CRj_int)
+     ((fr400 (unit u-check)) (fr450 (unit u-check))
+      (fr500 (unit u-check)) (fr550 (unit u-check)))
+)
+
+(dni ckno
+     "check integer cc never"
+     ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5)
+      (FR400-MAJOR B-5) (FR450-MAJOR B-5))
+     "ckno$pack $CRj_int"
+     (+ pack ICC_nev CRj_int OP_08 (misc-null-5) (ICCi_3-null))
+     (check-semantics (const BI 0) CRj_int)
+     ((fr400 (unit u-check)) (fr450 (unit u-check))
+      (fr500 (unit u-check)) (fr550 (unit u-check)))
+)
+
+(check-int-condition-code ck eq  OP_08 Ieq  "check integer cc equal")
+(check-int-condition-code ck ne  OP_08 Ine  "check integer cc not equal")
+(check-int-condition-code ck le  OP_08 Ile  "check integer cc less or equal")
+(check-int-condition-code ck gt  OP_08 Igt  "check integer cc greater")
+(check-int-condition-code ck lt  OP_08 Ilt  "check integer cc less")
+(check-int-condition-code ck ge  OP_08 Ige  "check integer cc greater or equal")
+(check-int-condition-code ck ls  OP_08 Ils  "check integer cc less or equal unsigned")
+(check-int-condition-code ck hi  OP_08 Ihi  "check integer cc greater unsigned")
+(check-int-condition-code ck c   OP_08 Ic   "check integer cc carry set")
+(check-int-condition-code ck nc  OP_08 Inc  "check integer cc carry clear")
+(check-int-condition-code ck n   OP_08 In   "check integer cc negative")
+(check-int-condition-code ck p   OP_08 Ip   "check integer cc positive")
+(check-int-condition-code ck v   OP_08 Iv   "check integer cc overflow set")
+(check-int-condition-code ck nv  OP_08 Inv  "check integer cc overflow clear")
+
+(define-pmacro (check-float-condition-code prefix cc op cond comment)
+  (dni (.sym prefix cc)
+       (comment)
+       ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5)
+       (FR400-MAJOR B-5) (FR450-MAJOR B-5) FR-ACCESS)
+       (.str (.sym prefix cc) "$pack $FCCi_3,$CRj_float")
+       (+ pack (.sym FCC_ cc) CRj_float op (misc-null-5) FCCi_3)
+       (check-semantics (cond FCCi_3) CRj_float)
+       ((fr400 (unit u-check)) (fr450 (unit u-check))
+       (fr500 (unit u-check)) (fr550 (unit u-check)))
+  )
+)
+
+(dni fckra
+     "check float cc always"
+     ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5)
+      (FR400-MAJOR B-5) (FR450-MAJOR B-5) FR-ACCESS)
+     "fckra$pack $CRj_float"
+     (+ pack FCC_ra CRj_float OP_09 (misc-null-5) FCCi_3)
+     (check-semantics (const BI 1) CRj_float)
+     ((fr400 (unit u-check)) (fr450 (unit u-check))
+      (fr500 (unit u-check)) (fr550 (unit u-check)))
+)
+
+(dni fckno
+     "check float cc never"
+     ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5)
+      (FR400-MAJOR B-5) (FR450-MAJOR B-5) FR-ACCESS)
+     "fckno$pack $CRj_float"
+     (+ pack FCC_nev CRj_float OP_09 (misc-null-5) FCCi_3)
+     (check-semantics (const BI 0) CRj_float)
+     ((fr400 (unit u-check)) (fr450 (unit u-check))
+      (fr500 (unit u-check)) (fr550 (unit u-check)))
+)
+
+(check-float-condition-code fck ne  OP_09 Fne  "check float cc not equal")
+(check-float-condition-code fck eq  OP_09 Feq  "check float cc equal")
+(check-float-condition-code fck lg  OP_09 Flg  "check float cc greater or less")
+(check-float-condition-code fck ue  OP_09 Fue  "check float cc unordered or equal")
+(check-float-condition-code fck ul  OP_09 Ful  "check float cc unordered or less")
+(check-float-condition-code fck ge  OP_09 Fge  "check float cc greater or equal")
+(check-float-condition-code fck lt  OP_09 Flt  "check float cc less")
+(check-float-condition-code fck uge OP_09 Fuge "check float cc unordered greater or equal")
+(check-float-condition-code fck ug  OP_09 Fug  "check float cc unordered or greater")
+(check-float-condition-code fck le  OP_09 Fle  "check float cc less or equal")
+(check-float-condition-code fck gt  OP_09 Fgt  "check float cc greater")
+(check-float-condition-code fck ule OP_09 Fule "check float cc unordered less or equal")
+(check-float-condition-code fck u   OP_09 Fu   "check float cc unordered")
+(check-float-condition-code fck o   OP_09 Fo   "check float cc ordered")
+
+(define-pmacro (conditional-check-int-condition-code prefix cc op ope test comment)
+  (dni (.sym prefix cc)
+       (comment)
+       ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5)
+       (FR400-MAJOR B-5) (FR450-MAJOR B-5) CONDITIONAL)
+       (.str (.sym prefix cc) "$pack $ICCi_3,$CRj_int,$CCi,$cond")
+       (+ pack (.sym ICC_ cc) CRj_int op (rs-null) CCi cond ope
+         (misc-null-9) ICCi_3)
+       (if (eq CCi (or cond 2))
+          (check-semantics (test ICCi_3) CRj_int)
+          (set CRj_int (cr-undefined)))
+       ((fr400 (unit u-check)) (fr450 (unit u-check))
+       (fr500 (unit u-check)) (fr550 (unit u-check)))
+  )
+)
+
+(dni cckra
+     "conditional check integer cc always"
+     ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5)
+      (FR400-MAJOR B-5) (FR450-MAJOR B-5) CONDITIONAL)
+     "cckra$pack $CRj_int,$CCi,$cond"
+     (+ pack ICC_ra CRj_int OP_6A (rs-null) CCi cond OPE4_0
+       (misc-null-9) (ICCi_3-null))
+     (if (eq CCi (or cond 2))
+        (check-semantics (const BI 1) CRj_int)
+        (set CRj_int (cr-undefined)))
+     ((fr400 (unit u-check)) (fr450 (unit u-check))
+      (fr500 (unit u-check)) (fr550 (unit u-check)))
+)
+
+(dni cckno
+     "conditional check integer cc never"
+     ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5)
+      (FR400-MAJOR B-5) (FR450-MAJOR B-5) CONDITIONAL)
+     "cckno$pack $CRj_int,$CCi,$cond"
+     (+ pack ICC_nev CRj_int OP_6A (rs-null) CCi cond OPE4_0
+       (misc-null-9) (ICCi_3-null))
+     (if (eq CCi (or cond 2))
+        (check-semantics (const BI 0) CRj_int)
+        (set CRj_int (cr-undefined)))
+     ((fr400 (unit u-check)) (fr450 (unit u-check))
+      (fr500 (unit u-check)) (fr550 (unit u-check)))
+)
+
+(conditional-check-int-condition-code cck eq  OP_6A OPE4_0 Ieq  "check integer cc equal")
+(conditional-check-int-condition-code cck ne  OP_6A OPE4_0 Ine  "check integer cc not equal")
+(conditional-check-int-condition-code cck le  OP_6A OPE4_0 Ile  "check integer cc less or equal")
+(conditional-check-int-condition-code cck gt  OP_6A OPE4_0 Igt  "check integer cc greater")
+(conditional-check-int-condition-code cck lt  OP_6A OPE4_0 Ilt  "check integer cc less")
+(conditional-check-int-condition-code cck ge  OP_6A OPE4_0 Ige  "check integer cc greater or equal")
+(conditional-check-int-condition-code cck ls  OP_6A OPE4_0 Ils  "check integer cc less or equal unsigned")
+(conditional-check-int-condition-code cck hi  OP_6A OPE4_0 Ihi  "check integer cc greater unsigned")
+(conditional-check-int-condition-code cck c   OP_6A OPE4_0 Ic   "check integer cc carry set")
+(conditional-check-int-condition-code cck nc  OP_6A OPE4_0 Inc  "check integer cc carry clear")
+(conditional-check-int-condition-code cck n   OP_6A OPE4_0 In   "check integer cc negative")
+(conditional-check-int-condition-code cck p   OP_6A OPE4_0 Ip   "check integer cc positive")
+(conditional-check-int-condition-code cck v   OP_6A OPE4_0 Iv   "check integer cc overflow set")
+(conditional-check-int-condition-code cck nv  OP_6A OPE4_0 Inv  "check integer cc overflow clear")
+
+(define-pmacro (conditional-check-float-condition-code prefix cc op ope test comment)
+  (dni (.sym prefix cc)
+       (comment)
+       ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5)
+       (FR400-MAJOR B-5) (FR450-MAJOR B-5) CONDITIONAL FR-ACCESS)
+       (.str (.sym prefix cc) "$pack $FCCi_3,$CRj_float,$CCi,$cond")
+       (+ pack (.sym FCC_ cc) CRj_float op (rs-null) CCi cond ope
+         (misc-null-9) FCCi_3)
+       (if (eq CCi (or cond 2))
+          (check-semantics (test FCCi_3) CRj_float)
+          (set CRj_float (cr-undefined)))
+       ((fr400 (unit u-check)) (fr450 (unit u-check))
+       (fr500 (unit u-check)) (fr550 (unit u-check)))
+  )
+)
+
+(dni cfckra
+     "conditional check float cc always"
+     ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5)
+      (FR400-MAJOR B-5) (FR450-MAJOR B-5) CONDITIONAL FR-ACCESS)
+     "cfckra$pack $CRj_float,$CCi,$cond"
+     (+ pack FCC_ra CRj_float OP_6A (rs-null) CCi cond OPE4_1
+       (misc-null-9) (FCCi_3-null))
+     (if (eq CCi (or cond 2))
+        (check-semantics (const BI 1) CRj_float)
+        (set CRj_float (cr-undefined)))
+     ((fr400 (unit u-check)) (fr450 (unit u-check))
+      (fr500 (unit u-check)) (fr550 (unit u-check)))
+)
+
+(dni cfckno
+     "conditional check float cc never"
+     ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5)
+      (FR400-MAJOR B-5) (FR450-MAJOR B-5) CONDITIONAL FR-ACCESS)
+     "cfckno$pack $CRj_float,$CCi,$cond"
+     (+ pack FCC_nev CRj_float OP_6A (rs-null) CCi cond OPE4_1
+       (misc-null-9) (FCCi_3-null))
+     (if (eq CCi (or cond 2))
+        (check-semantics (const BI 0) CRj_float)
+        (set CRj_float (cr-undefined)))
+     ((fr400 (unit u-check)) (fr450 (unit u-check))
+      (fr500 (unit u-check)) (fr550 (unit u-check)))
+)
+
+(conditional-check-float-condition-code cfck ne  OP_6A OPE4_1 Fne  "check float cc not equal")
+(conditional-check-float-condition-code cfck eq  OP_6A OPE4_1 Feq  "check float cc equal")
+(conditional-check-float-condition-code cfck lg  OP_6A OPE4_1 Flg  "check float cc greater or less")
+(conditional-check-float-condition-code cfck ue  OP_6A OPE4_1 Fue  "check float cc unordered or equal")
+(conditional-check-float-condition-code cfck ul  OP_6A OPE4_1 Ful  "check float cc unordered or less")
+(conditional-check-float-condition-code cfck ge  OP_6A OPE4_1 Fge  "check float cc greater or equal")
+(conditional-check-float-condition-code cfck lt  OP_6A OPE4_1 Flt  "check float cc less")
+(conditional-check-float-condition-code cfck uge OP_6A OPE4_1 Fuge "check float cc unordered greater or equal")
+(conditional-check-float-condition-code cfck ug  OP_6A OPE4_1 Fug  "check float cc unordered or greater")
+(conditional-check-float-condition-code cfck le  OP_6A OPE4_1 Fle  "check float cc less or equal")
+(conditional-check-float-condition-code cfck gt  OP_6A OPE4_1 Fgt  "check float cc greater")
+(conditional-check-float-condition-code cfck ule OP_6A OPE4_1 Fule "check float cc unordered less or equal")
+(conditional-check-float-condition-code cfck u   OP_6A OPE4_1 Fu   "check float cc unordered")
+(conditional-check-float-condition-code cfck o   OP_6A OPE4_1 Fo   "check float cc ordered")
+
+(dni cjmpl
+     "conditional jump and link"
+     ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6)
+      (FR400-MAJOR I-5) (FR450-MAJOR I-5) CONDITIONAL)
+     "cjmpl$pack @($GRi,$GRj),$CCi,$cond"
+     (+ pack (misc-null-1) (LI-off) OP_6A GRi CCi cond OPE4_2 GRj)
+     (if (eq CCi (or cond 2))
+        (jump-and-link-semantics GRi GRj LI))
+     ((fr400 (unit u-branch)) (fr450 (unit u-branch))
+      (fr500 (unit u-branch)) (fr550 (unit u-branch)))
+)
+
+(dni ccalll
+     "conditional call and link"
+     ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6)
+      (FR400-MAJOR I-5) (FR450-MAJOR I-5) CONDITIONAL)
+     "ccalll$pack @($GRi,$GRj),$CCi,$cond"
+     (+ pack (misc-null-1) (LI-on) OP_6A GRi CCi cond OPE4_2 GRj)
+     (if (eq CCi (or cond 2))
+        (jump-and-link-semantics GRi GRj LI))
+     ((fr400 (unit u-branch)) (fr450 (unit u-branch))
+      (fr500 (unit u-branch)) (fr550 (unit u-branch)))
+)
+
+(define-pmacro (cache-invalidate name cache all op ope profile comment)
+  (dni name
+       (comment)
+       ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2)
+       (FR400-MAJOR C-2) (FR450-MAJOR C-2))
+       (.str name "$pack @($GRi,$GRj)")
+       (+ pack (rd-null) op GRi ope GRj)
+       (c-call VOID (.str "@cpu@_" cache "_cache_invalidate") (add GRi GRj) all)
+       profile
+  )
+)
+
+(cache-invalidate ici insn 0 OP_03 OPE1_38
+                 ((fr400 (unit u-ici)) (fr450 (unit u-ici))
+                  (fr500 (unit u-ici)) (fr550 (unit u-ici)))
+                 "invalidate insn cache")
+(cache-invalidate dci data 0 OP_03 OPE1_3C
+                 ((fr400 (unit u-dci)) (fr450 (unit u-dci))
+                  (fr500 (unit u-dci)) (fr550 (unit u-dci)))
+                 "invalidate data cache")
+
+(define-pmacro (cache-invalidate-entry name cache op ope profile comment)
+  (dni name
+       (comment)
+       ((UNIT C) (MACH fr400,fr450,fr550) (FR550-MAJOR C-2)
+       (FR400-MAJOR C-2) (FR450-MAJOR C-2))
+       (.str name "$pack @($GRi,$GRj),$ae")
+       (+ pack (misc-null-1) ae op GRi ope GRj)
+       (if (eq ae 0)
+          (c-call VOID (.str "@cpu@_" cache "_cache_invalidate") (add GRi GRj) -1) ; Invalid ae setting for this insn
+          (c-call VOID (.str "@cpu@_" cache "_cache_invalidate") (add GRi GRj) ae))
+       profile
+  )
+)
+
+(cache-invalidate-entry icei insn OP_03 OPE1_39
+                       ((fr400 (unit u-ici)) (fr450 (unit u-ici))
+                        (fr550 (unit u-ici)))
+                       "invalidate insn cache entry")
+(cache-invalidate-entry dcei data OP_03 OPE1_3A
+                       ((fr400 (unit u-dci)) (fr450 (unit u-dci))
+                        (fr550 (unit u-dci)))
+                       "invalidate data cache entry")
+
+(dni dcf
+     "Data cache flush"
+     ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2)
+      (FR400-MAJOR C-2) (FR450-MAJOR C-2))
+     "dcf$pack @($GRi,$GRj)"
+     (+ pack (rd-null) OP_03 GRi OPE1_3D GRj)
+     (c-call VOID "@cpu@_data_cache_flush" (add GRi GRj) 0)
+     ((fr400 (unit u-dcf)) (fr450 (unit u-dcf))
+      (fr500 (unit u-dcf)) (fr550 (unit u-dcf)))
+)
+
+(dni dcef
+     "Data cache entry flush"
+     ((UNIT C) (MACH fr400,fr450,fr550) (FR550-MAJOR C-2)
+      (FR400-MAJOR C-2) (FR450-MAJOR C-2))
+     "dcef$pack @($GRi,$GRj),$ae"
+     (+ pack (misc-null-1) ae OP_03 GRi OPE1_3B GRj)
+     (if (eq ae 0)
+        (c-call VOID "@cpu@_data_cache_flush" (add GRi GRj) -1)
+        (c-call VOID "@cpu@_data_cache_flush" (add GRi GRj) ae))
+     ((fr400 (unit u-dcf)) (fr450 (unit u-dcf)) (fr550 (unit u-dcf)))
+)
+
+(define-pmacro (write-TLB name insn op ope comment)
+  (dni name
+       (comment)
+       ((UNIT C) (FR500-MAJOR C-2) (MACH frv) PRIVILEGED)
+       (.str insn "$pack $GRk,@($GRi,$GRj)")
+       (+ pack GRk op GRi ope GRj)
+       (nop) ; for now
+       ()
+  )
+)
+
+(write-TLB witlb witlb OP_03 OPE1_32 "write for insn TLB")
+(write-TLB wdtlb wdtlb OP_03 OPE1_36 "write for data TLB")
+
+(define-pmacro (invalidate-TLB name insn op ope comment)
+  (dni name
+       (comment)
+       ((UNIT C) (FR500-MAJOR C-2) (MACH frv) PRIVILEGED)
+       (.str insn "$pack @($GRi,$GRj)")
+       (+ pack (rd-null) op GRi ope GRj)
+       (nop) ; for now
+       ()
+  )
+)
+
+(invalidate-TLB itlbi itlbi OP_03 OPE1_33 "invalidate insn TLB")
+(invalidate-TLB dtlbi dtlbi OP_03 OPE1_37 "invalidate data TLB")
+
+(define-pmacro (cache-preload name cache pipe attrs op ope profile comment)
+  (dni name
+       (comment)
+       (.splice (UNIT pipe) (FR500-MAJOR C-2)
+               (FR400-MAJOR C-2) (.unsplice attrs))
+       (.str name "$pack $GRi,$GRj,$lock")
+       (+ pack (misc-null-1) lock op GRi ope GRj)
+       (c-call VOID (.str "@cpu@_" cache "_cache_preload") GRi GRj lock)
+       profile
+  )
+)
+
+(cache-preload icpl insn C ((FR550-MAJOR C-2) (FR450-MAJOR C-2)) OP_03 OPE1_30
+              ((fr400 (unit u-icpl)) (fr450 (unit u-icpl)) 
+               (fr500 (unit u-icpl)) (fr550 (unit u-icpl)))
+              "preload insn cache")
+(cache-preload dcpl data DCPL ((FR550-MAJOR I-8) (FR450-MAJOR I-2)) OP_03 OPE1_34
+              ((fr400 (unit u-dcpl)) (fr450 (unit u-dcpl))
+               (fr500 (unit u-dcpl)) (fr550 (unit u-dcpl)))
+              "preload data cache")
+
+(define-pmacro (cache-unlock name cache op ope profile comment)
+  (dni name
+       (comment)
+       ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2)
+       (FR400-MAJOR C-2) (FR450-MAJOR C-2))
+       (.str name "$pack $GRi")
+       (+ pack (rd-null) op GRi ope (GRj-null))
+       (c-call VOID (.str "@cpu@_" cache "_cache_unlock") GRi)
+       profile
+  )
+)
+
+(cache-unlock icul insn OP_03 OPE1_31
+             ((fr400 (unit u-icul)) (fr450 (unit u-icul))
+              (fr500 (unit u-icul)) (fr550 (unit u-icul)))
+             "unlock insn cache")
+(cache-unlock dcul data OP_03 OPE1_35
+             ((fr400 (unit u-dcul)) (fr450 (unit u-dcul))
+              (fr500 (unit u-dcul)) (fr550 (unit u-dcul)))
+             "unlock data cache")
+
+(define-pmacro (barrier name insn op ope profile comment)
+  (dni name
+       (comment)
+       ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2)
+       (FR400-MAJOR C-2) (FR450-MAJOR C-2))
+       (.str insn "$pack")
+       (+ pack (rd-null) op (rs-null) ope (GRj-null))
+       (nop) ; sufficient implementation
+       profile
+  )
+)
+
+(barrier bar    bar    OP_03 OPE1_3E
+        ((fr400 (unit u-barrier)) (fr450 (unit u-barrier))
+         (fr500 (unit u-barrier)))
+        "barrier")
+(barrier membar membar OP_03 OPE1_3F
+        ((fr400 (unit u-membar)) (fr450 (unit u-membar))
+         (fr500 (unit u-membar)))
+        "memory barrier")
+
+; Load real address instructions
+(define-pmacro (load-real-address name insn what op ope)
+  (dni name
+       (.str "Load real address of " what)
+       ((UNIT C) (FR450-MAJOR C-2) (MACH fr450))
+       (.str insn "$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS")
+       (+ pack GRk op GRi ope LRAE LRAD LRAS (LRA-null))
+       (nop) ; not simulated
+       ()
+  )
+)
+
+(load-real-address lrai "lrai" "instruction" OP_03 OPE1_20)
+(load-real-address lrad "lrad" "data" OP_03 OPE1_21)
+
+(dni tlbpr
+     "TLB Probe"
+     ((UNIT C) (FR450-MAJOR C-2) (MACH fr450))
+     "tlbpr$pack $GRi,$GRj,$TLBPRopx,$TLBPRL"
+     (+ pack (TLBPR-null) TLBPRopx TLBPRL OP_03 GRi OPE1_24 GRj)
+     (nop) ; not simulated
+     ()
+)
+
+; Coprocessor operations
+(define-pmacro (cop-op num op)
+  (dni (.sym cop num)
+       "Coprocessor operation"
+       ((UNIT C) (FR500-MAJOR C-2) (MACH frv))
+       (.str "cop" num "$pack $s6_1,$CPRi,$CPRj,$CPRk")
+       (+ pack CPRk op CPRi s6_1 CPRj)
+       (nop) ; sufficient implementation
+       ()
+  )
+)
+
+(cop-op 1 OP_7E)
+(cop-op 2 OP_7F)
+
+(define-pmacro (clear-ne-flag-semantics target_index is_float)
+  (c-call VOID "@cpu@_clear_ne_flags" target_index is_float)
+)
+
+(define-pmacro (clear-ne-flag-r name op ope reg is_float attr profile comment)
+  (dni name
+       (comment)
+       ((UNIT I01) (FR500-MAJOR I-6) (FR550-MAJOR I-7) (MACH simple,tomcat,fr500,fr550,frv) attr)
+       (.str name "$pack $" reg "k")
+       (+ pack (.sym reg k) op (rs-null) ope (GRj-null))
+       (sequence ()
+                ; hack to get this referenced for profiling
+                (c-raw-call VOID "frv_ref_SI" (.sym reg k))
+                (clear-ne-flag-semantics (index-of (.sym reg k)) is_float))
+       profile
+  )
+)
+
+(clear-ne-flag-r clrgr OP_0A OPE1_00 GR 0 NA
+                ((fr500 (unit u-clrgr)) (fr550 (unit u-clrgr)))
+                "Clear GR NE flag")
+(clear-ne-flag-r clrfr OP_0A OPE1_02 FR 1 FR-ACCESS
+                ((fr500 (unit u-clrfr)) (fr550 (unit u-clrfr)))
+                "Clear FR NE flag")
+
+(define-pmacro (clear-ne-flag-all name op ope is_float attr profile comment)
+  (dni name
+       (comment)
+       ((UNIT I01) (FR500-MAJOR I-6) (FR550-MAJOR I-7) (MACH simple,tomcat,fr500,fr550,frv) attr)
+       (.str name "$pack")
+       (+ pack (rd-null) op (rs-null) ope (GRj-null))
+       (clear-ne-flag-semantics -1 is_float)
+       profile
+  )
+)
+
+(clear-ne-flag-all clrga OP_0A OPE1_01 0 NA
+                ((fr500 (unit u-clrgr)) (fr550 (unit u-clrgr)))
+                  "Clear GR NE flag ALL")
+(clear-ne-flag-all clrfa OP_0A OPE1_03 1 FR-ACCESS
+                ((fr500 (unit u-clrfr)) (fr550 (unit u-clrfr)))
+                  "Clear FR NE flag ALL")
+
+(define-pmacro (commit-semantics target_index is_float)
+  (c-call VOID "@cpu@_commit" target_index is_float)
+)
+
+(define-pmacro (commit-r name op ope reg is_float attr comment)
+  (dni name
+       (comment)
+       ((UNIT I01) (FR500-MAJOR I-6) (FR550-MAJOR I-7) (MACH frv,fr500,fr550) attr)
+       (.str name "$pack $" reg "k")
+       (+ pack (.sym reg k) op (rs-null) ope (GRj-null))
+       (commit-semantics (index-of (.sym reg k)) is_float)
+       ((fr500 (unit u-commit)) (fr550 (unit u-commit)))
+  )
+)
+
+(commit-r commitgr OP_0A OPE1_04 GR 0 NA        "commit exceptions, specific GR")
+(commit-r commitfr OP_0A OPE1_06 FR 1 FR-ACCESS "commit exceptions, specific FR")
+
+(define-pmacro (commit name op ope is_float attr comment)
+  (dni name
+       (comment)
+       ((UNIT I01) (FR500-MAJOR I-6) (FR550-MAJOR I-7) (MACH frv,fr500,fr550) attr)
+       (.str name "$pack")
+       (+ pack (rd-null) op (rs-null) ope (GRj-null))
+       (commit-semantics -1 is_float)
+       ((fr500 (unit u-commit)) (fr550 (unit u-commit)))
+  )
+)
+
+(commit commitga OP_0A OPE1_05 0 NA        "commit exceptions, any GR")
+(commit commitfa OP_0A OPE1_07 1 FR-ACCESS "commit exceptions, any FR")
+
+(define-pmacro (floating-point-conversion
+               name op ope conv mode src targ attr comment)
+  (dni name
+       (comment)
+       (.splice (UNIT FMALL) (FR500-MAJOR F-1) (.unsplice attr))
+       (.str name "$pack $" src ",$" targ)
+       (+ pack targ op (rs-null) ope src)
+       (set targ (conv mode src))
+       ((fr500 (unit u-float-convert)) (fr550 (unit u-float-convert)))
+  )
+)
+
+(floating-point-conversion fitos OP_79 OPE1_00 float SF FRintj FRk
+                          ((FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv))
+                          "Convert Integer to Single")
+(floating-point-conversion fstoi OP_79 OPE1_01 fix   SI FRj FRintk
+                          ((FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv))
+                          "Convert Single  to Integer")
+(floating-point-conversion fitod OP_7A OPE1_00 float DF FRintj FRdoublek
+                          ((MACH frv))
+                          "Convert Integer to Double")
+(floating-point-conversion fdtoi OP_7A OPE1_01 fix   SI FRdoublej FRintk
+                          ((MACH frv))
+                          "Convert Double to Integer")
+
+(define-pmacro (floating-point-dual-conversion
+               name op ope conv mode src src_hw targ targ_hw attr comment)
+  (dni name
+       (comment)
+       ((MACH frv) (UNIT FMALL) (FR500-MAJOR F-1) attr)
+       (.str name "$pack $" src ",$" targ)
+       (+ pack targ op (rs-null) ope src)
+       (sequence ()
+                (set targ (conv mode src))
+                (set (nextreg targ_hw targ 1)
+                     (conv mode (nextreg src_hw src 1))))
+       ((fr500 (unit u-float-dual-convert)))
+  )
+)
+
+(floating-point-dual-conversion fditos OP_79 OPE1_10 float SF FRintj h-fr_int FRk h-fr NA "Dual Convert Integer to Single")
+(floating-point-dual-conversion fdstoi OP_79 OPE1_11 fix   SI FRj h-fr FRintk h-fr_int NA "Dual Convert Single  to Integer")
+
+(define-pmacro (ne-floating-point-dual-conversion
+               name op ope conv mode src src_hw targ targ_hw attr comment)
+  (dni name
+       (comment)
+       ((MACH frv) (UNIT FMALL) (FR500-MAJOR F-1) NON-EXCEPTING attr)
+       (.str name "$pack $" src ",$" targ)
+       (+ pack targ op (rs-null) ope src)
+       (sequence ()
+                (c-call VOID "@cpu@_set_ne_index" (index-of targ))
+                (set targ (conv mode src))
+                (c-call VOID "@cpu@_set_ne_index" (add (index-of targ) 1))
+                (set (nextreg targ_hw targ 1)
+                     (conv mode (nextreg src_hw src 1))))
+       ((fr500 (unit u-float-dual-convert)))
+  )
+)
+
+(ne-floating-point-dual-conversion nfditos OP_79 OPE1_30 float SF FRintj h-fr_int FRk h-fr NA "Non excepting dual Convert Integer to Single")
+(ne-floating-point-dual-conversion nfdstoi OP_79 OPE1_31 fix   SI FRj h-fr FRintk h-fr_int NA "Non excepting dual Convert Single  to Integer")
+
+(define-pmacro (conditional-floating-point-conversion
+               name op ope conv mode src targ comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (FR500-MAJOR F-1) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv))
+       (.str name "$pack $" src ",$" targ ",$CCi,$cond")
+       (+ pack targ op (rs-null) CCi cond ope src)
+       (if (eq CCi (or cond 2))
+          (set targ (conv mode src)))
+       ((fr500 (unit u-float-convert)) (fr550 (unit u-float-convert)))
+  )
+)
+
+(conditional-floating-point-conversion cfitos OP_6B OPE4_0 float SF FRintj FRk "Conditional convert Integer to Single")
+(conditional-floating-point-conversion cfstoi OP_6B OPE4_1 fix   SI FRj FRintk "Conditional convert Single to Integer")
+
+(define-pmacro (ne-floating-point-conversion 
+               name op ope conv mode src targ comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (FR500-MAJOR F-1) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv))
+       (.str name "$pack $" src ",$" targ)
+       (+ pack targ op (rs-null) ope src)
+       (sequence ()
+                (c-call VOID "@cpu@_set_ne_index" (index-of targ))
+                (set targ (conv mode src)))
+       ((fr500 (unit u-float-convert)) (fr550 (unit u-float-convert)))
+  )
+)
+
+(ne-floating-point-conversion nfitos OP_79 OPE1_20 float SF FRintj FRk "NE convert Integer to Single")
+(ne-floating-point-conversion nfstoi OP_79 OPE1_21 fix   SI FRj FRintk "NE convert Single to Integer")
+
+(register-transfer fmovs OP_79 OPE1_02
+                  FRj FRk FMALL
+                  ((FR500-MAJOR F-1) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv))
+                  ((fr500 (unit u-fr2fr)))
+                  "Move Single Float")
+(register-transfer fmovd OP_7A OPE1_02
+                  ; TODO -- unit doesn't handle extra register
+                  FRdoublej FRdoublek FM01
+                  ((FR500-MAJOR F-1) (MACH frv))
+                  ((fr500 (unit u-fr2fr)) (fr550 (unit u-fr2fr)))
+                  "Move Double Float")
+
+(dni fdmovs
+     "Dual move single float"
+     ((MACH frv) (UNIT FMALL) (FR500-MAJOR F-1))
+     "fdmovs$pack $FRj,$FRk"
+     (+ pack FRk OP_79 (rs-null) OPE1_12 FRj)
+     (sequence ()
+              (set FRk FRj)
+              (set (nextreg h-fr FRk 1) (nextreg h-fr FRj 1)))
+     ; TODO -- unit doesn't handle extra register
+     ((fr500 (unit u-fr2fr)))
+)
+
+(conditional-register-transfer cfmovs OP_6C OPE4_0 FRj FRk FMALL
+                              ((FR500-MAJOR F-1) (FR550-MAJOR F-2)
+                               (MACH simple,tomcat,fr500,fr550,frv))
+                              ((fr500 (unit u-fr2fr)) (fr550 (unit u-fr2fr)))
+                              "Conditional move Single Float")
+
+(define-pmacro (floating-point-neg name src targ op ope attr comment)
+  (dni name
+       (comment)
+       (.splice (UNIT FMALL) (FR500-MAJOR F-1) (.unsplice attr))
+       (.str name "$pack $" src ",$" targ)
+       (+ pack src op (rs-null) ope targ)
+       (set targ (neg src))
+       ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith)))
+  )
+)
+
+(floating-point-neg fnegs FRj FRk OP_79 OPE1_03 ((FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) "Floating point negate, single")
+(floating-point-neg fnegd FRdoublej FRdoublek OP_7A OPE1_03 ((MACH frv)) "Floating point negate, double")
+
+(dni fdnegs
+     "Floating point dual negate, single"
+     ((MACH frv) (UNIT FMALL) (FR500-MAJOR F-1))
+     "fdnegs$pack $FRj,$FRk"
+     (+ pack FRk OP_79 (rs-null) OPE1_13 FRj)
+     (sequence ()
+              (set FRk (neg FRj))
+              (set (nextreg h-fr FRk 1) (neg (nextreg h-fr FRj 1))))
+     ((fr500 (unit u-float-dual-arith)))
+)
+
+(dni cfnegs
+     "Conditional floating point negate, single"
+     ((UNIT FMALL) (FR500-MAJOR F-1) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv))
+     "cfnegs$pack $FRj,$FRk,$CCi,$cond"
+     (+ pack FRj OP_6C (rs-null) CCi cond OPE4_1 FRk)
+     (if (eq CCi (or cond 2))
+        (set FRk (neg FRj)))
+     ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith)))
+)
+
+(define-pmacro (float-abs name src targ op ope attr comment)
+  (dni name
+       (comment)
+       (.splice (UNIT FMALL) (FR500-MAJOR F-1) (.unsplice attr))
+       (.str name "$pack $" src ",$" targ )
+       (+ pack targ op (rs-null) ope src)
+       (set targ (abs src))
+       ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith)))
+  )
+)
+
+(float-abs fabss FRj FRk OP_79 OPE1_04 ((FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) "Float absolute value, single")
+(float-abs fabsd FRdoublej FRdoublek OP_7A OPE1_04 ((MACH frv)) "Float absolute value, double")
+
+(dni fdabss
+     "Floating point dual absolute value, single"
+     ((MACH frv) (UNIT FMALL) (FR500-MAJOR F-1))
+     "fdabss$pack $FRj,$FRk"
+     (+ pack FRk OP_79 (rs-null) OPE1_14 FRj)
+     (sequence ()
+              (set FRk (abs FRj))
+              (set (nextreg h-fr FRk 1) (abs (nextreg h-fr FRj 1))))
+     ((fr500 (unit u-float-dual-arith)))
+)
+
+(dni cfabss
+     "Conditional floating point absolute value, single"
+     ((UNIT FMALL) (FR500-MAJOR F-1) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv))
+     "cfabss$pack $FRj,$FRk,$CCi,$cond"
+     (+ pack FRj OP_6C (rs-null) CCi cond OPE4_2 FRk)
+     (if (eq CCi (or cond 2))
+        (set FRk (abs FRj)))
+     ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith)))
+)
+
+(dni fsqrts
+     "Square root single"
+     ((UNIT FM01) (FR500-MAJOR F-4) (FR550-MAJOR F-3) (MACH simple,tomcat,fr500,fr550,frv))
+     "fsqrts$pack $FRj,$FRk"
+     (+ pack FRk OP_79 (rs-null) OPE1_05 FRj)
+     (set FRk (sqrt SF FRj))
+     ((fr500 (unit u-float-sqrt)) (fr550 (unit u-float-sqrt)))
+)
+
+(dni fdsqrts
+     "Dual square root single"
+     ((MACH frv) (UNIT FM01) (FR500-MAJOR F-4))
+     "fdsqrts$pack $FRj,$FRk"
+     (+ pack FRk OP_79 (rs-null) OPE1_15 FRj)
+     (sequence ()
+              (set FRk (sqrt SF FRj))
+              (set (nextreg h-fr FRk 1) (sqrt (nextreg h-fr FRj 1))))
+     ((fr500 (unit u-float-dual-sqrt)))
+)
+
+(dni nfdsqrts
+     "Non excepting Dual square root single"
+     ((MACH frv) (UNIT FM01) (FR500-MAJOR F-4) NON-EXCEPTING)
+     "nfdsqrts$pack $FRj,$FRk"
+     (+ pack FRk OP_79 (rs-null) OPE1_35 FRj)
+     (sequence ()
+              (c-call VOID "@cpu@_set_ne_index" (index-of FRk))
+              (set FRk (sqrt SF FRj))
+              (c-call VOID "@cpu@_set_ne_index" (add (index-of FRk) 1))
+              (set (nextreg h-fr FRk 1) (sqrt (nextreg h-fr FRj 1))))
+     ((fr500 (unit u-float-dual-sqrt)))
+)
+
+(dni fsqrtd
+     "Square root double"
+     ((UNIT FM01) (FR500-MAJOR F-4) (MACH frv))
+     "fsqrtd$pack $FRdoublej,$FRdoublek"
+     (+ pack FRdoublek OP_7A (rs-null) OPE1_05 FRdoublej)
+     (set FRdoublek (sqrt DF FRdoublej))
+     ((fr500 (unit u-float-sqrt)))
+)
+
+(dni cfsqrts
+     "Conditional square root single"
+     ((UNIT FM01) (FR500-MAJOR F-4) (FR550-MAJOR F-3) (MACH simple,tomcat,fr500,fr550,frv))
+     "cfsqrts$pack $FRj,$FRk,$CCi,$cond"
+     (+ pack FRk OP_6E (rs-null) CCi cond OPE4_2 FRj)
+     (if (eq CCi (or cond 2))
+        (set FRk (sqrt SF FRj)))
+     ((fr500 (unit u-float-sqrt)) (fr550 (unit u-float-sqrt)))
+)
+
+(dni nfsqrts
+     "Non exception square root, single"
+     ((UNIT FM01) (FR500-MAJOR F-4) (FR550-MAJOR F-3) (MACH simple,tomcat,fr500,fr550,frv))
+     "nfsqrts$pack $FRj,$FRk"
+     (+ pack FRk OP_79 (rs-null) OPE1_25 FRj)
+     (sequence ()
+              (c-call VOID "@cpu@_set_ne_index" (index-of FRk))
+              (set FRk (sqrt SF FRj)))
+     ((fr500 (unit u-float-sqrt)) (fr550 (unit u-float-sqrt)))
+)
+
+(define-pmacro (float-binary-op-s name pipe attr operation op ope comment)
+  (dni name
+       (comment)
+       (.splice (UNIT pipe) (MACH simple,tomcat,fr500,fr550,frv) (.unsplice attr))
+       (.str name "$pack $FRi,$FRj,$FRk")
+       (+ pack FRk op FRi ope FRj)
+       (set FRk (operation FRi FRj))
+       ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith)))
+  )
+)
+
+(float-binary-op-s fadds FMALL ((FR500-MAJOR F-2) (FR550-MAJOR F-2)) add OP_79 OPE1_06 "add single float")
+(float-binary-op-s fsubs FMALL ((FR500-MAJOR F-2) (FR550-MAJOR F-2)) sub OP_79 OPE1_07 "sub single float")
+(float-binary-op-s fmuls FM01  ((FR500-MAJOR F-3) (FR550-MAJOR F-3)) mul OP_79 OPE1_08 "mul single float")
+
+(dni fdivs
+     "div single float"
+     ((UNIT FM01) (FR500-MAJOR F-4) (FR550-MAJOR F-3) (MACH simple,tomcat,fr500,fr550,frv))
+     "fdivs$pack $FRi,$FRj,$FRk"
+     (+ pack FRk OP_79 FRi OPE1_09 FRj)
+     (set FRk (div FRi FRj))
+     ((fr500 (unit u-float-div))
+      (fr550 (unit u-float-div)))
+)
+
+(define-pmacro (float-binary-op-d name operation op ope major comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (FR500-MAJOR major) (MACH frv))
+       (.str name "$pack $FRdoublei,$FRdoublej,$FRdoublek")
+       (+ pack FRdoublek op FRdoublei ope FRdoublej)
+       (set FRdoublek (operation FRdoublei FRdoublej))
+       ((fr500 (unit u-float-arith)))
+  )
+)
+
+(float-binary-op-d faddd add OP_7A OPE1_06 F-2 "add double float")
+(float-binary-op-d fsubd sub OP_7A OPE1_07 F-2 "sub double float")
+(float-binary-op-d fmuld mul OP_7A OPE1_08 F-3 "mul double float")
+(float-binary-op-d fdivd div OP_7A OPE1_09 F-4 "div double float")
+
+(define-pmacro (conditional-float-binary-op name pipe attr operation op ope profile comment)
+  (dni name
+       (comment)
+       (.splice (UNIT pipe) (MACH simple,tomcat,fr500,fr550,frv)
+               (.unsplice attr))
+       (.str name "$pack $FRi,$FRj,$FRk,$CCi,$cond")
+       (+ pack FRk op FRi CCi cond ope FRj)
+       (if (eq CCi (or cond 2))
+          (set FRk (operation FRi FRj)))
+       profile
+  )
+)
+
+(conditional-float-binary-op cfadds FMALL ((FR500-MAJOR F-2) (FR550-MAJOR F-2)) add OP_6D OPE4_0
+                            ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith)))
+                            "cond add single")
+(conditional-float-binary-op cfsubs FMALL ((FR500-MAJOR F-2) (FR550-MAJOR F-2)) sub OP_6D OPE4_1
+                            ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith)))
+                            "cond sub single")
+(conditional-float-binary-op cfmuls FM01  ((FR500-MAJOR F-3) (FR550-MAJOR F-3)) mul OP_6E OPE4_0
+                            ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith)))
+                            "cond mul single")
+(conditional-float-binary-op cfdivs FM01  ((FR500-MAJOR F-4) (FR550-MAJOR F-3)) div OP_6E OPE4_1
+                            ((fr500 (unit u-float-div)) (fr550 (unit u-float-div)))
+                            "cond div single")
+
+(define-pmacro (ne-float-binary-op name pipe attr operation op ope profile comment)
+  (dni name
+       (comment)
+       (.splice (UNIT pipe) (MACH simple,tomcat,fr500,fr550,frv)
+               (.unsplice attr))
+       (.str name "$pack $FRi,$FRj,$FRk")
+       (+ pack FRk op FRi ope FRj)
+       (sequence ()
+                (c-call VOID "@cpu@_set_ne_index" (index-of FRk))
+                (set FRk (operation FRi FRj)))
+       profile
+  )
+)
+
+(ne-float-binary-op nfadds FMALL ((FR500-MAJOR F-2) (FR550-MAJOR F-2)) add OP_79 OPE1_26
+                   ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith)))
+                   "ne add single")
+(ne-float-binary-op nfsubs FMALL ((FR500-MAJOR F-2) (FR550-MAJOR F-2)) sub OP_79 OPE1_27
+                   ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith)))
+                   "ne sub single")
+(ne-float-binary-op nfmuls FM01  ((FR500-MAJOR F-3) (FR550-MAJOR F-3)) mul OP_79 OPE1_28
+                   ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith)))
+                   "ne mul single")
+(ne-float-binary-op nfdivs FM01  ((FR500-MAJOR F-4) (FR550-MAJOR F-3)) div OP_79 OPE1_29
+                   ((fr500 (unit u-float-div)) (fr550 (unit u-float-div)))
+                   "ne div single")
+
+(define-pmacro (fcc-eq) 8)
+(define-pmacro (fcc-lt) 4)
+(define-pmacro (fcc-gt) 2)
+(define-pmacro (fcc-uo) 1)
+
+(define-pmacro (compare-and-set-fcc arg1 arg2 fcc)
+  (if (gt arg1 arg2)
+      (set fcc (fcc-gt))
+      (if (eq arg1 arg2)
+         (set fcc (fcc-eq))
+         (if (lt arg1 arg2)
+             (set fcc (fcc-lt))
+             (set fcc (fcc-uo)))))
+)
+
+(dni fcmps
+     "compare single float"
+     ((UNIT FMALL) (FR500-MAJOR F-2) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv))
+     "fcmps$pack $FRi,$FRj,$FCCi_2"
+     (+ pack (cond-null) FCCi_2 OP_79 FRi OPE1_0A FRj)
+     (compare-and-set-fcc FRi FRj FCCi_2)
+     ((fr500 (unit u-float-compare)) (fr550 (unit u-float-compare)))
+)
+
+(dni fcmpd
+     "compare double float"
+     ((UNIT FMALL) (FR500-MAJOR F-2) (MACH frv))
+     "fcmpd$pack $FRdoublei,$FRdoublej,$FCCi_2"
+     (+ pack (cond-null) FCCi_2 OP_7A FRdoublei OPE1_0A FRdoublej)
+     (compare-and-set-fcc FRdoublei FRdoublej FCCi_2)
+     ((fr500 (unit u-float-compare)))
+)
+
+(dni cfcmps
+     "Conditional compare single, float"
+     ((UNIT FMALL) (FR500-MAJOR F-2) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv))
+     "cfcmps$pack $FRi,$FRj,$FCCi_2,$CCi,$cond"
+     (+ pack (cond-null) FCCi_2 OP_6D FRi CCi cond OPE4_2 FRj)
+     (if (eq CCi (or cond 2))
+        (compare-and-set-fcc FRi FRj FCCi_2))
+     ((fr500 (unit u-float-compare)) (fr550 (unit u-float-compare)))
+)
+
+(dni fdcmps
+     "float dual compare single"
+     ((UNIT FMALL) (FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv))
+     "fdcmps$pack $FRi,$FRj,$FCCi_2"
+     (+ pack (cond-null) FCCi_2 OP_79 FRi OPE1_1A FRj)
+     (sequence ()
+              (compare-and-set-fcc FRi FRj FCCi_2)
+              (compare-and-set-fcc (nextreg h-fr FRi 1) (nextreg h-fr FRj 1)
+                                   (nextreg h-fccr FCCi_2 1)))
+     ((fr500 (unit u-float-dual-compare)) (fr550 (unit u-float-dual-compare)))
+)
+
+(define-pmacro (float-mul-with-add name add_sub arg1 arg2 targ op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (FR500-MAJOR F-5) (MACH frv))
+       (.str name "$pack $" arg1 ",$" arg2 ",$" targ)
+       (+ pack targ op arg1 ope arg2)
+       (set targ (add_sub (mul arg1 arg2) targ))
+       ((fr500 (unit u-float-dual-arith)))
+  )
+)
+
+(float-mul-with-add fmadds add FRi FRj FRk OP_79 OPE1_0B "mul with add, single")
+(float-mul-with-add fmsubs sub FRi FRj FRk OP_79 OPE1_0C "mul with sub, single")
+
+(float-mul-with-add fmaddd add FRdoublei FRdoublej FRdoublek OP_7A OPE1_0B "mul with add, double")
+(float-mul-with-add fmsubd sub FRdoublei FRdoublej FRdoublek OP_7A OPE1_0C "mul with sub, double")
+
+(dni fdmadds
+     "Float dual multiply with add"
+     ((UNIT FMALL) (FR500-MAJOR F-5) (MACH frv))
+     "fdmadds$pack $FRi,$FRj,$FRk"
+     (+ pack FRk OP_79 FRi OPE1_1B FRj)
+     (sequence ()
+              (set FRk (add (mul FRi FRj) FRk))
+              (set (nextreg h-fr FRk 1)
+                   (add (mul (nextreg h-fr FRi 1) (nextreg h-fr FRj 1))
+                        (nextreg h-fr FRk 1))))
+     ; TODO dual registers not referenced for profiling
+     ((fr500 (unit u-float-dual-arith)))
+)
+
+(dni nfdmadds
+     "Non excepting float dual multiply with add"
+     ((UNIT FMALL) (FR500-MAJOR F-5) (MACH frv))
+     "nfdmadds$pack $FRi,$FRj,$FRk"
+     (+ pack FRk OP_79 FRi OPE1_3B FRj)
+     (sequence ()
+              (c-call VOID "@cpu@_set_ne_index" (index-of FRk))
+              (set FRk (add (mul FRi FRj) FRk))
+              (c-call VOID "@cpu@_set_ne_index" (add (index-of FRk) 1))
+              (set (nextreg h-fr FRk 1)
+                   (add (mul (nextreg h-fr FRi 1) (nextreg h-fr FRj 1))
+                        (nextreg h-fr FRk 1))))
+     ; TODO dual registers not referenced for profiling
+     ((fr500 (unit u-float-dual-arith)))
+)
+
+(define-pmacro (conditional-float-mul-with-add
+               name add_sub arg1 arg2 targ op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (FR500-MAJOR F-5) (MACH frv) CONDITIONAL)
+       (.str name "$pack $FRi,$FRj,$FRk,$CCi,$cond")
+       (+ pack FRk op FRi CCi cond ope FRj)
+       (if (eq CCi (or cond 2))
+          (set targ (add_sub (mul arg1 arg2) targ)))
+       ((fr500 (unit u-float-dual-arith)))
+  )
+)
+
+(conditional-float-mul-with-add cfmadds add FRi FRj FRk OP_6F OPE4_0 "conditional mul with add, single")
+(conditional-float-mul-with-add cfmsubs sub FRi FRj FRk OP_6F OPE4_1 "conditional mul with sub, single")
+
+(define-pmacro (ne-float-mul-with-add name add_sub arg1 arg2 targ op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (FR500-MAJOR F-5) (MACH frv) NON-EXCEPTING)
+       (.str name "$pack $" arg1 ",$" arg2 ",$" targ)
+       (+ pack targ op arg1 ope arg2)
+       (sequence ()
+                (c-call VOID "@cpu@_set_ne_index" (index-of targ))
+                (set targ (add_sub (mul arg1 arg2) targ)))
+       ((fr500 (unit u-float-dual-arith)))
+  )
+)
+
+(ne-float-mul-with-add nfmadds add FRi FRj FRk OP_79 OPE1_2B "non excepting mul with add, single")
+(ne-float-mul-with-add nfmsubs sub FRi FRj FRk OP_79 OPE1_2C "non excepting mul with sub, single")
+
+(define-pmacro (float-parallel-mul-add-semantics cond add_sub arg1 arg2 targ)
+  (if cond
+      (sequence ()
+               (set targ (mul arg1 arg2))
+               (set (nextreg h-fr targ 1)
+                    (add_sub (nextreg h-fr arg1 1) (nextreg h-fr arg2 1)))))
+)
+
+(define-pmacro (float-parallel-mul-add
+               name add_sub arg1 arg2 targ op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FM01) (FR500-MAJOR F-5) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv))
+       (.str name "$pack $" arg1 ",$" arg2 ",$" targ)
+       (+ pack targ op arg1 ope arg2)
+       (float-parallel-mul-add-semantics 1 add_sub arg1 arg2 targ)
+       ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith)))
+  )
+)
+
+(float-parallel-mul-add fmas add FRi FRj FRk OP_79 OPE1_0E "parallel mul/add, single")
+(float-parallel-mul-add fmss sub FRi FRj FRk OP_79 OPE1_0F "parallel mul/sub, single")
+
+(define-pmacro (float-dual-parallel-mul-add-semantics add_sub arg1 arg2 targ)
+  (sequence ()
+           (set targ (mul arg1 arg2))
+           (set (nextreg h-fr targ 1)
+                (add_sub (nextreg h-fr arg1 1) (nextreg h-fr arg2 1)))
+           (set (nextreg h-fr targ 2)
+                (mul (nextreg h-fr arg1 2)     (nextreg h-fr arg2 2)))
+           (set (nextreg h-fr targ 3)
+                (add_sub (nextreg h-fr arg1 3) (nextreg h-fr arg2 3))))
+)
+
+(define-pmacro (float-dual-parallel-mul-add
+               name add_sub arg1 arg2 targ op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FM01) (FR500-MAJOR F-5) (MACH frv))
+       (.str name "$pack $" arg1 ",$" arg2 ",$" targ)
+       (+ pack targ op arg1 ope arg2)
+       (float-dual-parallel-mul-add-semantics add_sub arg1 arg2 targ)
+       ()
+  )
+)
+
+(float-dual-parallel-mul-add fdmas add FRi FRj FRk OP_79 OPE1_1C "dual parallel mul/add, single")
+(float-dual-parallel-mul-add fdmss sub FRi FRj FRk OP_79 OPE1_1D "dual parallel mul/sub, single")
+
+(define-pmacro (ne-float-dual-parallel-mul-add-semantics add_sub arg1 arg2 targ)
+  (sequence ()
+           (c-call VOID "@cpu@_set_ne_index" (index-of targ))
+           (c-call VOID "@cpu@_set_ne_index" (add (index-of targ) 1))
+           (c-call VOID "@cpu@_set_ne_index" (add (index-of targ) 2))
+           (c-call VOID "@cpu@_set_ne_index" (add (index-of targ) 3))
+           (set targ (mul arg1 arg2))
+           (set (nextreg h-fr targ 1)
+                (add_sub (nextreg h-fr arg1 1) (nextreg h-fr arg2 1)))
+           (set (nextreg h-fr targ 2)
+                (mul (nextreg h-fr arg1 2)     (nextreg h-fr arg2 2)))
+           (set (nextreg h-fr targ 3)
+                (add_sub (nextreg h-fr arg1 3) (nextreg h-fr arg2 3))))
+)
+
+(define-pmacro (ne-float-dual-parallel-mul-add
+               name add_sub arg1 arg2 targ op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FM01) (FR500-MAJOR F-5) (MACH frv))
+       (.str name "$pack $" arg1 ",$" arg2 ",$" targ)
+       (+ pack targ op arg1 ope arg2)
+       (ne-float-dual-parallel-mul-add-semantics add_sub arg1 arg2 targ)
+       ()
+  )
+)
+
+(ne-float-dual-parallel-mul-add nfdmas add FRi FRj FRk OP_79 OPE1_3C "non excepting dual parallel mul/add, single")
+(ne-float-dual-parallel-mul-add nfdmss sub FRi FRj FRk OP_79 OPE1_3D "non excepting dual parallel mul/sub, single")
+
+(define-pmacro (conditional-float-parallel-mul-add name add_sub op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FM01) (FR500-MAJOR F-5) (FR550-MAJOR F-4) CONDITIONAL (MACH simple,tomcat,fr500,fr550,frv))
+       (.str name "$pack $FRi,$FRj,$FRk,$CCi,$cond")
+       (+ pack FRk op FRi CCi cond ope FRj)
+       (float-parallel-mul-add-semantics (eq CCi (or cond 2))
+                                        add_sub FRi FRj FRk)
+       ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith)))
+  )
+)
+
+(conditional-float-parallel-mul-add cfmas add OP_6F OPE4_2 "conditional parallel mul/add, single")
+(conditional-float-parallel-mul-add cfmss sub OP_6F OPE4_3 "conditional parallel mul/sub, single")
+
+(define-pmacro (float-parallel-mul-add-double-semantics add_sub arg1 arg2 targ)
+  (sequence ()
+           (set targ (ftrunc SF (mul DF (fext DF arg1) (fext DF arg2))))
+           (set (nextreg h-fr targ 1)
+                (ftrunc SF (add_sub DF
+                                    (fext DF (nextreg h-fr arg1 1))
+                                    (fext DF (nextreg h-fr arg2 1))))))
+)
+
+(define-pmacro (float-parallel-mul-add-double
+               name add_sub arg1 arg2 targ op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FM01) (FR500-MAJOR F-5) (MACH frv))
+       (.str name "$pack $" arg1 ",$" arg2 ",$" targ)
+       (+ pack targ op arg1 ope arg2)
+       (float-parallel-mul-add-double-semantics add_sub arg1 arg2 targ)
+       ()
+  )
+)
+
+(float-parallel-mul-add-double fmad add FRi FRj FRk OP_7A OPE1_0E "parallel mul/add, double")
+(float-parallel-mul-add-double fmsd sub FRi FRj FRk OP_7A OPE1_0F "parallel mul/sub, double")
+
+(define-pmacro (ne-float-parallel-mul-add name add_sub op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FM01) (FR500-MAJOR F-5) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv))
+       (.str name "$pack $FRi,$FRj,$FRk")
+       (+ pack FRk op FRi ope FRj)
+       (sequence ()
+                (c-call VOID "@cpu@_set_ne_index" (index-of FRk))
+                (set FRk (mul FRi FRj))
+                (c-call VOID "@cpu@_set_ne_index" (add (index-of FRk) 1))
+                (set (nextreg h-fr FRk 1)
+                     (add_sub (nextreg h-fr FRi 1) (nextreg h-fr FRj 1))))
+       ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith)))
+  )
+)
+
+(ne-float-parallel-mul-add nfmas add OP_79 OPE1_2E "ne parallel mul/add,single")
+(ne-float-parallel-mul-add nfmss sub OP_79 OPE1_2F "ne parallel mul/sub,single")
+
+(define-pmacro (float-dual-arith name attr oper1 oper2 op ope comment)
+  (dni name
+       (comment)
+       (.splice (UNIT FM01) (.unsplice attr))
+       (.str name "$pack $FRi,$FRj,$FRk")
+       (+ pack FRk op FRi ope FRj)
+       (sequence ()
+                (set FRk (oper1 FRi FRj))
+                (set (nextreg h-fr FRk 1)
+                     (oper2 (nextreg h-fr FRi 1) (nextreg h-fr FRj 1))))
+       ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith)))
+  )
+)
+
+(float-dual-arith fdadds ((FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) add add OP_79 OPE1_16 "dual add, single")
+(float-dual-arith fdsubs ((FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) sub sub OP_79 OPE1_17 "dual sub, single")
+(float-dual-arith fdmuls ((FR500-MAJOR F-7) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) mul mul OP_79 OPE1_18 "dual mul, single")
+(float-dual-arith fddivs ((FR500-MAJOR F-7) (MACH frv))                           div div OP_79 OPE1_19 "dual div,single")
+(float-dual-arith fdsads ((FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) add sub OP_79 OPE1_1E "dual add/sub, single")
+
+(dni fdmulcs
+     "Float dual cross multiply single"
+     ((UNIT FM01) (FR500-MAJOR F-7) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv))
+     "fdmulcs$pack $FRi,$FRj,$FRk"
+     (+ pack FRk OP_79 FRi OPE1_1F FRj)
+     (sequence ()
+              (set FRk (mul FRi (nextreg h-fr FRj 1)))
+              (set (nextreg h-fr FRk 1) (mul (nextreg h-fr FRi 1) FRj)))
+     ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith)))
+)
+
+(dni nfdmulcs
+     "NE float dual cross multiply single"
+     ((UNIT FM01) (FR500-MAJOR F-7) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv))
+     "nfdmulcs$pack $FRi,$FRj,$FRk"
+     (+ pack FRk OP_79 FRi OPE1_3F FRj)
+     (sequence ()
+              (c-call VOID "@cpu@_set_ne_index" (index-of FRk))
+              (set FRk (mul FRi (nextreg h-fr FRj 1)))
+              (c-call VOID "@cpu@_set_ne_index" (add (index-of FRk) 1))
+              (set (nextreg h-fr FRk 1) (mul (nextreg h-fr FRi 1) FRj)))
+     ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith)))
+)
+
+(define-pmacro (ne-float-dual-arith name attr oper1 oper2 op ope comment)
+  (dni name
+       (comment)
+       (.splice (UNIT FM01) (.unsplice attr))
+       (.str name "$pack $FRi,$FRj,$FRk")
+       (+ pack FRk op FRi ope FRj)
+       (sequence ()
+                (c-call VOID "@cpu@_set_ne_index" (index-of FRk))
+                (set FRk (oper1 FRi FRj))
+                (c-call VOID "@cpu@_set_ne_index" (add (index-of FRk) 1))
+                (set (nextreg h-fr FRk 1)
+                     (oper2 (nextreg h-fr FRi 1) (nextreg h-fr FRj 1))))
+       ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith)))
+  )
+)
+
+(ne-float-dual-arith nfdadds ((FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) add add OP_79 OPE1_36 "ne dual add, single")
+(ne-float-dual-arith nfdsubs ((FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) sub sub OP_79 OPE1_37 "ne dual sub, single")
+(ne-float-dual-arith nfdmuls ((FR500-MAJOR F-7) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) mul mul OP_79 OPE1_38 "ne dual mul, single")
+(ne-float-dual-arith nfddivs ((FR500-MAJOR F-7) (MACH frv))                           div div OP_79 OPE1_39 "ne dual div,single")
+(ne-float-dual-arith nfdsads ((FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) add sub OP_79 OPE1_3E "ne dual add/sub, single")
+
+(dni nfdcmps
+     "non-excepting dual float compare"
+     ((UNIT FM01) (FR500-MAJOR F-6) (MACH simple,tomcat,frv))
+     "nfdcmps$pack $FRi,$FRj,$FCCi_2"
+     (+ pack (cond-null) FCCi_2 OP_79 FRi OPE1_3A FRj)
+     (sequence ()
+              (c-call VOID "@cpu@_set_ne_index" (index-of FRk))
+              (compare-and-set-fcc FRi FRj FCCi_2)
+              (c-call VOID "@cpu@_set_ne_index" (add (index-of FRk) 1))
+              (compare-and-set-fcc (nextreg h-fr FRi 1) (nextreg h-fr FRj 1)
+                                   (nextreg h-fccr FCCi_2 1)))
+     ((fr500 (unit u-float-dual-compare)))
+)
+
+; Media Instructions
+;
+(define-pmacro (halfword hilo arg offset)
+  (reg (.sym h-fr_ hilo) (add (index-of arg) offset)))
+
+(dni mhsetlos
+     "Media set lower signed 12 bits"
+     ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-5)
+      (FR400-MAJOR M-1) (FR450-MAJOR M-1))
+     "mhsetlos$pack $u12,$FRklo"
+     (+ pack FRklo OP_78 OPE1_20 u12)
+     (set FRklo u12)
+     ((fr400 (unit u-media-hilo)) (fr450 (unit u-media-hilo))
+      (fr550 (unit u-media-set (out FRintk FRklo))))
+)
+
+(dni mhsethis
+     "Media set upper signed 12 bits"
+     ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-5)
+      (FR400-MAJOR M-1) (FR450-MAJOR M-1))
+     "mhsethis$pack $u12,$FRkhi"
+     (+ pack FRkhi OP_78 OPE1_22 u12)
+     (set FRkhi u12)
+     ((fr400 (unit u-media-hilo)) (fr450 (unit u-media-hilo))
+      (fr550 (unit u-media-set (out FRintk FRkhi))))
+)
+
+(dni mhdsets
+     "Media dual set halfword signed 12 bits"
+     ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-5)
+      (FR400-MAJOR M-1) (FR450-MAJOR M-1))
+     "mhdsets$pack $u12,$FRintk"
+     (+ pack FRintk OP_78 OPE1_24 u12)
+     (sequence ()
+              ; hack to get FRintk passed to modelling functions
+              (set FRintk (c-raw-call SI "frv_ref_SI" FRintk))
+              (set (halfword hi FRintk 0) u12)
+              (set (halfword lo FRintk 0) u12))
+     ((fr400 (unit u-media-1)) (fr450 (unit u-media-1))
+      (fr550 (unit u-media-set)))
+)
+
+(define-pmacro (set-5-semantics target value)
+  (sequence ((HI tmp))
+           (set tmp target)
+           (set tmp (and tmp #x07ff))
+           (set tmp (or tmp (sll (and s5 #x1f) 11)))
+           (set target tmp))
+)
+
+(define-pmacro (media-set-5 name hilo op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-5)
+       (FR400-MAJOR M-1) (FR450-MAJOR M-1))
+       (.str name "$pack $s5,$FRk" hilo)
+       (+ pack (.sym FRk hilo) op (FRi-null) ope (misc-null-11) s5)
+       (set-5-semantics (.sym FRk hilo) s5)
+       ((fr400 (unit u-media-hilo)) (fr450 (unit u-media-hilo))
+       (fr550 (unit u-media-set (out FRintk (.sym FRk hilo)))))
+  )
+)
+
+(media-set-5 mhsetloh lo OP_78 OPE1_21 "Media set upper 5 bits lo")
+(media-set-5 mhsethih hi OP_78 OPE1_23 "Media set upper 5 bits hi")
+
+(dni mhdseth
+     "Media dual set halfword upper 5 bits"
+     ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-5)
+      (FR400-MAJOR M-1) (FR450-MAJOR M-1))
+     "mhdseth$pack $s5,$FRintk"
+     (+ pack FRintk OP_78 (FRi-null) OPE1_25 (misc-null-11) s5)
+     (sequence ()
+              ; hack to get FRintk passed to modelling functions
+              (set FRintk (c-raw-call SI "frv_ref_SI" FRintk))
+              (set-5-semantics (halfword hi FRintk 0) s5)
+              (set-5-semantics (halfword lo FRintk 0) s5))
+     ((fr400 (unit u-media-1)) (fr450 (unit u-media-1))
+      (fr550 (unit u-media-set)))
+)
+
+(define-pmacro (media-logic-r-r name operation op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2)
+       (FR400-MAJOR M-1) (FR450-MAJOR M-1))
+       (.str name "$pack $FRinti,$FRintj,$FRintk")
+       (+ pack FRintk op FRinti ope FRintj)
+       (set FRintk (operation FRinti FRintj))
+       ((fr400 (unit u-media-1)) (fr450 (unit u-media-1))
+       (fr500 (unit u-media)) (fr550 (unit u-media)))
+  )
+)
+
+(media-logic-r-r mand and OP_7B OPE1_00 "and reg/reg")
+(media-logic-r-r mor  or  OP_7B OPE1_01 "or  reg/reg")
+(media-logic-r-r mxor xor OP_7B OPE1_02 "xor reg/reg")
+
+(define-pmacro (conditional-media-logic name operation op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2)
+       (FR400-MAJOR M-1) (FR450-MAJOR M-1) CONDITIONAL)
+       (.str name "$pack $FRinti,$FRintj,$FRintk,$CCi,$cond")
+       (+ pack FRintk op FRinti CCi cond ope FRintj)
+       (if (eq CCi (or cond 2))
+          (set FRintk (operation FRinti FRintj)))
+       ((fr400 (unit u-media-1)) (fr450 (unit u-media-1))
+       (fr500 (unit u-media)) (fr550 (unit u-media)))
+  )
+)
+
+(conditional-media-logic cmand and OP_70 OPE4_0 "conditional and reg/reg")
+(conditional-media-logic cmor  or  OP_70 OPE4_1 "conditional or  reg/reg")
+(conditional-media-logic cmxor xor OP_70 OPE4_2 "conditional xor reg/reg")
+
+(dni mnot
+     ("mnot")
+     ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2)
+      (FR400-MAJOR M-1) (FR450-MAJOR M-1))
+     ("mnot$pack $FRintj,$FRintk")
+     (+ pack FRintk OP_7B (rs-null) OPE1_03 FRintj)
+     (set FRintk (inv FRintj))
+     ((fr400 (unit u-media-1)) (fr450 (unit u-media-1))
+      (fr500 (unit u-media)) (fr550 (unit u-media)))
+)
+
+(dni cmnot
+     ("cmnot")
+     ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2)
+      (FR400-MAJOR M-1) (FR450-MAJOR M-1) CONDITIONAL)
+     ("cmnot$pack $FRintj,$FRintk,$CCi,$cond")
+     (+ pack FRintk OP_70 (rs-null) CCi cond OPE4_3 FRintj)
+     (if (eq CCi (or cond 2))
+        (set FRintk (inv FRintj)))
+     ((fr400 (unit u-media-1)) (fr450 (unit u-media-1))
+      (fr500 (unit u-media)) (fr550 (unit u-media)))
+)
+
+(define-pmacro (media-rotate-r-r name operation op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+       (FR400-MAJOR M-1) (FR450-MAJOR M-1))
+       (.str name "$pack $FRinti,$u6,$FRintk")
+       (+ pack FRintk op FRinti ope u6)
+       (set FRintk (operation FRinti (and u6 #x1f)))
+       ((fr400 (unit u-media-3)) (fr450 (unit u-media-3))
+       (fr500 (unit u-media)) (fr550 (unit u-media)))
+  )
+)
+
+(media-rotate-r-r mrotli rol OP_7B OPE1_04 "rotate left reg/reg")
+(media-rotate-r-r mrotri ror OP_7B OPE1_05 "rotate right reg/reg")
+
+(define-pmacro (media-cut-r-r name arg op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+       (FR400-MAJOR M-2) (FR450-MAJOR M-2))
+       (.str name "$pack $FRinti,$" arg ",$FRintk")
+       (+ pack FRintk op FRinti ope arg)
+       (set FRintk (c-call SI "@cpu@_cut" FRinti (nextreg h-fr_int FRinti 1) arg))
+       ((fr400 (unit u-media-3)) (fr450 (unit u-media-3))
+       (fr500 (unit u-media)) (fr550 (unit u-media)))
+  )
+)
+
+(media-cut-r-r mwcut  FRintj OP_7B OPE1_06 "media cut")
+(media-cut-r-r mwcuti u6     OP_7B OPE1_07 "media cut")
+
+(define-pmacro (media-cut-acc name arg op ope fr450-major comment)
+  (dni name
+       (comment)
+       ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+       (FR400-MAJOR M-1) (FR450-MAJOR fr450-major))
+       (.str name "$pack $ACC40Si,$" arg ",$FRintk")
+       (+ pack FRintk op ACC40Si ope arg)
+       (set FRintk (c-call SI "@cpu@_media_cut" ACC40Si arg))
+       ((fr400 (unit u-media-4)) (fr450 (unit u-media-4))
+       (fr500 (unit u-media)) (fr550 (unit u-media-3-acc)))
+  )
+)
+
+(media-cut-acc mcut  FRintj OP_7B OPE1_2C M-1 "media accumulator cut reg")
+(media-cut-acc mcuti s6     OP_7B OPE1_2E M-5 "media accumulator cut immed")
+
+(define-pmacro (media-cut-acc-ss name arg op ope fr450-major comment)
+  (dni name
+       (comment)
+       ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+       (FR400-MAJOR M-1) (FR450-MAJOR fr450-major))
+       (.str name "$pack $ACC40Si,$" arg ",$FRintk")
+       (+ pack FRintk op ACC40Si ope arg)
+       (set FRintk (c-call SI "@cpu@_media_cut_ss" ACC40Si arg))
+       ((fr400 (unit u-media-4)) (fr450 (unit u-media-4))
+       (fr500 (unit u-media)) (fr550 (unit u-media-3-acc)))
+  )
+)
+
+(media-cut-acc-ss mcutss  FRintj OP_7B OPE1_2D M-1 "media accumulator cut reg with saturation")
+(media-cut-acc-ss mcutssi s6     OP_7B OPE1_2F M-5 "media accumulator cut immed with saturation")
+
+; Dual Media Instructions
+;
+(define-pmacro (register-unaligned register alignment)
+  (and (index-of register) (sub alignment 1))
+)
+
+(dni mdcutssi
+     "Media dual cut with signed saturation"
+     ((UNIT MDCUTSSI) (MACH fr400,fr450,fr550) (FR550-MAJOR M-3)
+      (FR400-MAJOR M-2) (FR450-MAJOR M-6))
+     "mdcutssi$pack $ACC40Si,$s6,$FRintkeven"
+     (+ pack FRintkeven OP_78 ACC40Si OPE1_0E s6)
+     (if (register-unaligned ACC40Si 2)
+        (c-call VOID "@cpu@_media_acc_not_aligned")
+        (if (register-unaligned FRintkeven 2)
+            (c-call VOID "@cpu@_media_register_not_aligned")
+            (sequence ()
+                      (set FRintkeven (c-call SI "@cpu@_media_cut_ss" ACC40Si s6))
+                      (set (nextreg h-fr_int FRintkeven 1)
+                           (c-call SI "@cpu@_media_cut_ss"
+                                   (nextreg h-acc40S ACC40Si 1) s6)))))
+     ((fr400 (unit u-media-4-acc-dual
+                  (out FRintk FRintkeven)))
+      (fr450 (unit u-media-4-acc-dual
+                  (out FRintk FRintkeven)))
+      (fr550 (unit u-media-3-acc-dual)))
+)
+
+; The (add (xxxx) (mul arg 0)) is a hack to get a reference to arg generated
+; so it will be passed to the unit modelers.   YUCK!!!!!
+(define-pmacro (extract-hilo reg1 off1 reg2 off2 arg1hi arg1lo arg2hi arg2lo)
+  (sequence ()
+           (set arg1hi (add (halfword hi reg1 off1) (mul reg1 0)))
+           (set arg1lo (add (halfword lo reg1 off1) (mul reg1 0)))
+           (set arg2hi (add (halfword hi reg2 off2) (mul reg2 0)))
+           (set arg2lo (add (halfword lo reg2 off2) (mul reg2 0))))
+)
+
+(dni maveh
+     "Media dual average"
+     ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2)
+      (FR400-MAJOR M-1) (FR450-MAJOR M-1))
+     "maveh$pack $FRinti,$FRintj,$FRintk"
+     (+ pack FRintk OP_7B FRinti OPE1_08 FRintj)
+     (set FRintk (c-call SI "@cpu@_media_average" FRinti FRintj))
+     ((fr400 (unit u-media-1)) (fr450 (unit u-media-1))
+      (fr500 (unit u-media)) (fr550 (unit u-media)))
+)
+
+(define-pmacro (media-dual-shift name operation op ope profile comment)
+  (dni name
+       (comment)
+       ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+       (FR400-MAJOR M-1) (FR450-MAJOR M-1))
+       (.str name "$pack $FRinti,$u6,$FRintk")
+       (+ pack FRintk op FRinti ope u6)
+       (sequence ()
+                ; hack to get these referenced for profiling
+                (set FRinti (c-raw-call SI "frv_ref_SI" FRinti))
+                (set FRintk (c-raw-call SI "frv_ref_SI" FRintk))
+                (set (halfword hi FRintk 0)
+                     (operation (halfword hi FRinti 0) (and u6 #xf)))
+                (set (halfword lo FRintk 0)
+                     (operation (halfword lo FRinti 0) (and u6 #xf))))
+       profile
+  )
+)
+
+(media-dual-shift msllhi sll OP_7B OPE1_09
+                 ((fr400 (unit u-media-3)) (fr450 (unit u-media-3))
+                  (fr500 (unit u-media)) (fr550 (unit u-media)))
+                 "Media dual shift left  logical")
+(media-dual-shift msrlhi srl OP_7B OPE1_0A
+                 ((fr400 (unit u-media-3)) (fr450 (unit u-media-3))
+                  (fr500 (unit u-media)) (fr550 (unit u-media)))
+                 "Media dual shift right logical")
+(media-dual-shift msrahi sra OP_7B OPE1_0B
+                 ((fr400 (unit u-media-6)) (fr450 (unit u-media-6))
+                  (fr500 (unit u-media)) (fr550 (unit u-media)))
+                 "Media dual shift right arithmetic")
+
+(define-pmacro (media-dual-word-rotate-r-r name operation op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FMLOW) (MACH fr400,fr450,fr550) (FR550-MAJOR M-3)
+       (FR400-MAJOR M-2) (FR450-MAJOR M-2))
+       (.str name "$pack $FRintieven,$s6,$FRintkeven")
+       (+ pack FRintkeven op FRintieven ope s6)
+       (if (orif (register-unaligned FRintieven 2)
+                (register-unaligned FRintkeven 2))
+          (c-call VOID "@cpu@_media_register_not_aligned")
+          (sequence ()
+                    (set FRintkeven (operation FRintieven (and s6 #x1f)))
+                    (set (nextreg h-fr_int FRintkeven 1)
+                         (operation (nextreg h-fr_int FRintieven 1)
+                                    (and s6 #x1f)))))
+       ((fr400 (unit u-media-3-quad
+                    (in  FRinti FRintieven)
+                    (out FRintk FRintkeven))) 
+       (fr450 (unit u-media-3-quad
+                    (in  FRinti FRintieven)
+                    (out FRintk FRintkeven)))
+       (fr550 (unit u-media-quad)))
+  )
+)
+
+(media-dual-word-rotate-r-r mdrotli rol OP_78 OPE1_0B "rotate left reg/reg")
+
+(dni mcplhi
+     "Media bit concatenate, halfword"
+     ((UNIT FMLOW) (MACH fr400,fr450,fr550) (FR550-MAJOR M-3)
+      (FR400-MAJOR M-2) (FR450-MAJOR M-2))
+     "mcplhi$pack $FRinti,$u6,$FRintk"
+     (+ pack FRintk OP_78 FRinti OPE1_0C u6)
+     (sequence ((HI arg1) (HI arg2) (HI shift))
+              (set FRinti (c-raw-call SI "frv_ref_SI" FRinti))
+              (set FRintk (c-raw-call SI "frv_ref_SI" FRintk))
+              (set shift (and u6 #xf))
+              (set arg1 (sll (halfword hi FRinti 0) shift))
+              (if (ne shift 0)
+                  (sequence ()
+                            (set arg2 (halfword hi FRinti 1))
+                            (set arg2 (srl HI (sll HI arg2 (sub 15 shift))
+                                           (sub 15 shift)))
+                            (set arg1 (or HI arg1 arg2))))
+              (set (halfword hi FRintk 0) arg1))
+     ((fr400 (unit u-media-3-dual)) (fr450 (unit u-media-3-dual))
+      (fr550 (unit u-media-3-dual)))
+)
+
+(dni mcpli
+     "Media bit concatenate, word"
+     ((UNIT FMLOW) (MACH fr400,fr450,fr550) (FR550-MAJOR M-3)
+      (FR400-MAJOR M-2) (FR450-MAJOR M-2))
+     "mcpli$pack $FRinti,$u6,$FRintk"
+     (+ pack FRintk OP_78 FRinti OPE1_0D u6)
+     (sequence ((SI tmp) (SI shift))
+              (set shift (and u6 #x1f))
+              (set tmp (sll FRinti shift))
+              (if (ne shift 0)
+                  (sequence ((SI tmp1))
+                            (set tmp1 (srl (sll (nextreg h-fr_int FRinti 1)
+                                                (sub 31 shift))
+                                           (sub 31 shift)))
+                            (set tmp (or tmp tmp1))))
+              (set FRintk tmp))
+     ((fr400 (unit u-media-3-dual)) (fr450 (unit u-media-3-dual))
+      (fr550 (unit u-media-3-dual)))
+)
+
+(define-pmacro (saturate arg max min result)
+  (if (gt arg max)
+      (set result max)
+      (if (lt arg min)
+         (set result min)
+         (set result arg)))
+)
+
+(dni msaths
+     "Media dual saturation signed"
+     ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2)
+      (FR400-MAJOR M-1) (FR450-MAJOR M-1))
+     "msaths$pack $FRinti,$FRintj,$FRintk"
+     (+ pack FRintk OP_7B FRinti OPE1_0C FRintj)
+     (sequence ((HI argihi) (HI argilo) (HI argjhi) (HI argjlo))
+              (extract-hilo FRinti 0 FRintj 0 argihi argilo argjhi argjlo)
+              (saturate argihi argjhi (inv argjhi) (halfword hi FRintk 0))
+              (saturate argilo argjlo (inv argjlo) (halfword lo FRintk 0)))
+     ((fr400 (unit u-media-1)) (fr450 (unit u-media-1))
+      (fr500 (unit u-media)) (fr550 (unit u-media)))
+)
+
+(dni mqsaths
+     "Media quad saturation signed"
+     ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-2)
+      (FR400-MAJOR M-2) (FR450-MAJOR M-2))
+     "mqsaths$pack $FRintieven,$FRintjeven,$FRintkeven"
+     (+ pack FRintkeven OP_78 FRintieven OPE1_0F FRintjeven)
+     (if (orif (register-unaligned FRintieven 2)
+              (orif (register-unaligned FRintjeven 2)
+                    (register-unaligned FRintkeven 2)))
+        (c-call VOID "@cpu@_media_register_not_aligned")
+        (sequence ((HI argihi) (HI argilo) (HI argjhi) (HI argjlo))
+                  ; hack to get FRintkeven referenced as a target for profiling
+                  (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven))
+                  (extract-hilo FRintieven 0 FRintjeven 0 argihi argilo argjhi argjlo)
+                  (saturate argihi argjhi (inv argjhi) (halfword hi FRintkeven 0))
+                  (saturate argilo argjlo (inv argjlo) (halfword lo FRintkeven 0))
+                  (extract-hilo FRintieven 1 FRintjeven 1 argihi argilo argjhi argjlo)
+                  (saturate argihi argjhi (inv argjhi) (halfword hi FRintkeven 1))
+                  (saturate argilo argjlo (inv argjlo) (halfword lo FRintkeven 1))))
+     ((fr400 (unit u-media-1-quad
+                  (in  FRinti FRintieven)
+                  (in  FRintj FRintjeven)
+                  (out FRintk FRintkeven)))
+      (fr450 (unit u-media-1-quad
+                  (in  FRinti FRintieven)
+                  (in  FRintj FRintjeven)
+                  (out FRintk FRintkeven)))
+      (fr550 (unit u-media-quad)))
+)
+
+(define-pmacro (saturate-unsigned arg max result)
+  (if (gt arg max)
+      (set result max)
+      (set result arg))
+)
+
+(dni msathu
+     "Media dual saturation unsigned"
+     ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2)
+      (FR400-MAJOR M-1) (FR450-MAJOR M-1))
+     "msathu$pack $FRinti,$FRintj,$FRintk"
+     (+ pack FRintk OP_7B FRinti OPE1_0D FRintj)
+     (sequence ((UHI argihi) (UHI argilo) (UHI argjhi) (UHI argjlo))
+              (extract-hilo FRinti 0 FRintj 0 argihi argilo argjhi argjlo)
+              (saturate-unsigned argihi argjhi (halfword hi FRintk 0))
+              (saturate-unsigned argilo argjlo (halfword lo FRintk 0)))
+     ((fr400 (unit u-media-1)) (fr450 (unit u-media-1))
+      (fr500 (unit u-media)) (fr550 (unit u-media)))
+)
+
+(define-pmacro (media-dual-compare name mode op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2)
+       (FR400-MAJOR M-1) (FR450-MAJOR M-1))
+       (.str name "$pack $FRinti,$FRintj,$FCCk")
+       (+ pack (cond-null) FCCk op FRinti ope FRintj)
+       (if (register-unaligned FCCk 2)
+          (c-call VOID "@cpu@_media_cr_not_aligned")
+          (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo))
+                    (extract-hilo FRinti 0 FRintj 0
+                                  argihi argilo argjhi argjlo)
+                    (compare-and-set-fcc argihi argjhi FCCk)
+                    (compare-and-set-fcc argilo argjlo (nextreg h-fccr FCCk 1))))
+       ; TODO - doesn't handle second FCC
+       ((fr400 (unit u-media-7)) (fr450 (unit u-media-7))
+       (fr500 (unit u-media)) (fr550 (unit u-media)))
+  )
+)
+
+(media-dual-compare mcmpsh HI  OP_7B OPE1_0E "Media dual compare signed")
+(media-dual-compare mcmpuh UHI OP_7B OPE1_0F "Media dual compare unsigned")
+
+; Bits for the MSR.SIE field
+(define-pmacro (msr-sie-nil)      0)
+(define-pmacro (msr-sie-fri-hi)   8)
+(define-pmacro (msr-sie-fri-lo)   4)
+(define-pmacro (msr-sie-fri-1-hi) 2)
+(define-pmacro (msr-sie-fri-1-lo) 1)
+(define-pmacro (msr-sie-acci)     8)
+(define-pmacro (msr-sie-acci-1)   4)
+(define-pmacro (msr-sie-acci-2)   2)
+(define-pmacro (msr-sie-acci-3)   1)
+
+(define-pmacro (saturate-v arg max min sie result)
+  (if (gt DI arg max)
+      (sequence ()
+               (set result max)
+               (c-call VOID "@cpu@_media_overflow" sie))
+      (if (lt DI arg min)
+         (sequence ()
+                   (set result min)
+                   (c-call VOID "@cpu@_media_overflow" sie))
+         (set result arg)))
+)
+
+(dni mabshs
+     "Media dual absolute value, halfword"
+     ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-2)
+      (FR400-MAJOR M-1) (FR450-MAJOR M-1))
+     "mabshs$pack $FRintj,$FRintk"
+     (+ pack FRintk OP_78 (FRi-null) OPE1_0A FRintj)
+     (sequence ((HI arghi) (HI arglo))
+              (set FRintj (c-raw-call SI "frv_ref_SI" FRintj))
+              (set FRintk (c-raw-call SI "frv_ref_SI" FRintk))
+              (set arghi (halfword hi FRintj 0))
+              (set arglo (halfword lo FRintj 0))
+              ; We extend the argument before the abs operation so we can
+              ; notice -32768 overflowing as 32768.
+              (saturate-v (abs (ext DI arghi)) 32767 -32768 (msr-sie-fri-hi)
+                          (halfword hi FRintk 0))
+              (saturate-v (abs (ext DI arglo)) 32767 -32768 (msr-sie-fri-lo)
+                          (halfword lo FRintk 0)))
+     ((fr400 (unit u-media-1)) (fr450 (unit u-media-1))
+      (fr550 (unit u-media)))
+)
+
+; How to extend from a mode to get the intended signedness.
+(define-pmacro (DI-ext-HI x) (ext DI x))
+(define-pmacro (DI-ext-UHI x) (zext DI x))
+(define-pmacro (DI-ext-DI x) x)
+
+(define-pmacro (media-arith-sat-semantics
+               operation arg1 arg2 res mode max min sie)
+  (sequence ((DI tmp))
+           ; Make sure we saturate at max/min against a value that is
+           ; sign- or zero-extended appropriately from "mode".
+           (set tmp (operation DI
+                     ((.sym DI-ext- mode) arg1) ((.sym DI-ext- mode) arg2)))
+           (saturate-v tmp max min sie res))
+)
+
+(define-pmacro (media-dual-arith-sat-semantics operation mode max min)
+  (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo))
+           (extract-hilo FRinti 0 FRintj 0 argihi argilo argjhi argjlo)
+           (media-arith-sat-semantics operation argihi argjhi
+                                      (halfword hi FRintk 0) mode max min
+                                      (msr-sie-fri-hi))
+           (media-arith-sat-semantics operation argilo argjlo
+                                      (halfword lo FRintk 0) mode max min
+                                      (msr-sie-fri-lo)))
+)
+
+(define-pmacro (media-dual-arith-sat name operation mode max min op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2)
+       (FR400-MAJOR M-1) (FR450-MAJOR M-1))
+       (.str name "$pack $FRinti,$FRintj,$FRintk")
+       (+ pack FRintk op FRinti ope FRintj)
+       (media-dual-arith-sat-semantics operation mode max min)
+       ((fr400 (unit u-media-1)) (fr450 (unit u-media-1))
+       (fr500 (unit u-media)) (fr550 (unit u-media)))
+  )
+)
+
+(media-dual-arith-sat maddhss add  HI 32767 -32768 OP_7B OPE1_10 "Media dual add signed with saturation")
+(media-dual-arith-sat maddhus add UHI 65535      0 OP_7B OPE1_11 "Media dual add unsigned with saturation")
+
+(media-dual-arith-sat msubhss sub  HI 32767 -32768 OP_7B OPE1_12 "Media dual sub signed with saturation")
+(media-dual-arith-sat msubhus sub UHI 65535      0 OP_7B OPE1_13 "Media dual sub unsigned with saturation")
+
+(define-pmacro (conditional-media-dual-arith-sat
+               name operation mode max min op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2)
+       (FR400-MAJOR M-1) (FR450-MAJOR M-1) CONDITIONAL)
+       (.str name "$pack $FRinti,$FRintj,$FRintk,$CCi,$cond")
+       (+ pack FRintk op FRinti CCi cond ope FRintj)
+       (if (eq CCi (or cond 2))
+          (media-dual-arith-sat-semantics operation mode max min))
+       ((fr400 (unit u-media-1)) (fr450 (unit u-media-1))
+       (fr500 (unit u-media)) (fr550 (unit u-media)))
+  )
+)
+
+(conditional-media-dual-arith-sat cmaddhss add  HI 32767 -32768 OP_71 OPE4_0 "Conditional Media dual add signed with saturation")
+(conditional-media-dual-arith-sat cmaddhus add UHI 65535      0 OP_71 OPE4_1 "Conditional Media dual add unsigned with saturation")
+
+(conditional-media-dual-arith-sat cmsubhss sub  HI 32767 -32768 OP_71 OPE4_2 "Conditional Media dual sub signed with saturation")
+(conditional-media-dual-arith-sat cmsubhus sub UHI 65535      0 OP_71 OPE4_3 "Conditional Media dual sub unsigned with saturation")
+
+(define-pmacro (media-quad-arith-sat-semantics cond operation mode max min)
+  (if (orif (register-unaligned FRintieven 2)
+           (orif (register-unaligned FRintjeven 2)
+                 (register-unaligned FRintkeven 2)))
+      (c-call VOID "@cpu@_media_register_not_aligned")
+      (if cond
+         (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo))
+                   ; hack to get FRintkeven referenced as a target for profiling
+                   (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven))
+                   (extract-hilo FRintieven 0 FRintjeven 0
+                                 argihi argilo argjhi argjlo)
+                   (media-arith-sat-semantics operation argihi argjhi
+                                              (halfword hi FRintkeven 0) mode
+                                              max min (msr-sie-fri-hi))
+                   (media-arith-sat-semantics operation argilo argjlo
+                                              (halfword lo FRintkeven 0) mode
+                                              max min (msr-sie-fri-lo))
+                   (extract-hilo FRintieven 1 FRintjeven 1
+                                 argihi argilo argjhi argjlo)
+                   (media-arith-sat-semantics operation argihi argjhi
+                                              (halfword hi FRintkeven 1) mode
+                                              max min  (msr-sie-fri-1-hi))
+                   (media-arith-sat-semantics operation argilo argjlo
+                                              (halfword lo FRintkeven 1) mode
+                                              max min (msr-sie-fri-1-lo)))))
+)
+
+(define-pmacro (media-quad-arith-sat name operation mode max min op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2)
+       (FR400-MAJOR M-2) (FR450-MAJOR M-2))
+       (.str name "$pack $FRintieven,$FRintjeven,$FRintkeven")
+       (+ pack FRintkeven op FRintieven ope FRintjeven)
+       (media-quad-arith-sat-semantics 1 operation mode max min)
+       ((fr400 (unit u-media-1-quad
+                    (in  FRinti FRintieven)
+                    (in  FRintj FRintjeven)
+                    (out FRintk FRintkeven)))
+       (fr450 (unit u-media-1-quad
+                    (in  FRinti FRintieven)
+                    (in  FRintj FRintjeven)
+                    (out FRintk FRintkeven)))
+       (fr500 (unit u-media-quad-arith
+                    (in  FRinti FRintieven)
+                    (in  FRintj FRintjeven)
+                    (out FRintk FRintkeven))) (fr550 (unit u-media-quad)))
+  )
+)
+
+(media-quad-arith-sat mqaddhss add  HI 32767 -32768 OP_7B OPE1_18 "Media quad add signed with saturation")
+(media-quad-arith-sat mqaddhus add UHI 65535      0 OP_7B OPE1_19 "Media quad add unsigned with saturation")
+
+(media-quad-arith-sat mqsubhss sub  HI 32767 -32768 OP_7B OPE1_1A "Media quad sub signed with saturation")
+(media-quad-arith-sat mqsubhus sub UHI 65535      0 OP_7B OPE1_1B "Media quad sub unsigned with saturation")
+
+(define-pmacro (conditional-media-quad-arith-sat
+               name operation mode max min op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2)
+       (FR400-MAJOR M-2) (FR450-MAJOR M-2) CONDITIONAL)
+       (.str name "$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond")
+       (+ pack FRintkeven op FRintieven CCi cond ope FRintjeven)
+       (media-quad-arith-sat-semantics (eq CCi (or cond 2))
+                                      operation mode max min)
+       ((fr400 (unit u-media-1-quad
+                    (in  FRinti FRintieven)
+                    (in  FRintj FRintjeven)
+                    (out FRintk FRintkeven)))
+       (fr450 (unit u-media-1-quad
+                    (in  FRinti FRintieven)
+                    (in  FRintj FRintjeven)
+                    (out FRintk FRintkeven)))
+       (fr500 (unit u-media-quad-arith
+                    (in  FRinti FRintieven)
+                    (in  FRintj FRintjeven)
+                    (out FRintk FRintkeven))) (fr550 (unit u-media-quad)))
+  )
+)
+
+(conditional-media-quad-arith-sat cmqaddhss add  HI 32767 -32768 OP_73 OPE4_0 "Conditional Media quad add signed with saturation")
+(conditional-media-quad-arith-sat cmqaddhus add UHI 65535      0 OP_73 OPE4_1 "Conditional Media quad add unsigned with saturation")
+
+(conditional-media-quad-arith-sat cmqsubhss sub  HI 32767 -32768 OP_73 OPE4_2 "Conditional Media quad sub signed with saturation")
+(conditional-media-quad-arith-sat cmqsubhus sub UHI 65535      0 OP_73 OPE4_3 "Conditional Media quad sub unsigned with saturation")
+
+;; Return A if |A| > |B| and B is positive.  Return -A if |A| > |B| and
+;; B is negative, saturating 0x8000 as 0x7fff.  Return 0 otherwise.
+(define-pmacro (media-low-clear-semantics a b)
+  (cond HI
+       ((le UHI (abs a) (abs b)) 0)
+       ((le HI 0 b) a)
+       ((eq HI a -32768) 32767)
+       (else (neg a))))
+
+;; Return A if -|B| < A < |B|.  Return -B if A <= -|B|, saturating 0x8000
+;; as 0x7fff.  Return B if A >= |B|.
+(define-pmacro (media-scope-limit-semantics a b)
+  (cond HI
+       ((andif (gt HI b -32768)
+               (ge HI a (abs b))) b)
+       ((gt HI a (neg (abs b))) a)
+       ((eq HI b -32768) 32767)
+       (else (neg b))))
+
+(define-pmacro (media-quad-limit name operation op ope comment)
+  (dni name
+       comment
+       ((UNIT FM0) (MACH fr450) (FR450-MAJOR M-2))
+       (.str name "$pack $FRintieven,$FRintjeven,$FRintkeven")
+       (+ pack FRintkeven op FRintieven ope FRintjeven)
+       (if (orif (register-unaligned FRintieven 2)
+                (orif (register-unaligned FRintjeven 2)
+                      (register-unaligned FRintkeven 2)))
+          (c-call VOID "@cpu@_media_register_not_aligned")
+          (sequence ((HI a1) (HI a2) (HI a3) (HI a4)
+                     (HI b1) (HI b2) (HI b3) (HI b4))
+                    ; hack to get FRintkeven referenced as a target
+                    ; for profiling
+                    (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven))
+                    (extract-hilo FRintieven 0 FRintjeven 0 a1 a2 b1 b2)
+                    (extract-hilo FRintieven 1 FRintjeven 1 a3 a4 b3 b4)
+                    (set (halfword hi FRintkeven 0) (operation a1 b1))
+                    (set (halfword lo FRintkeven 0) (operation a2 b2))
+                    (set (halfword hi FRintkeven 1) (operation a3 b3))
+                    (set (halfword lo FRintkeven 1) (operation a4 b4))))
+       ((fr450 (unit u-media-1-quad
+                    (in  FRinti FRintieven)
+                    (in  FRintj FRintjeven)
+                    (out FRintk FRintkeven))))
+  )
+)
+
+(media-quad-limit mqlclrhs media-low-clear-semantics OP_78 OPE1_10
+                 "Media quad low clear")
+(media-quad-limit mqlmths media-scope-limit-semantics OP_78 OPE1_14
+                 "Media quad scope limitation")
+
+(define-pmacro (media-quad-shift name operation op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FM0) (MACH fr450) (FR450-MAJOR M-2))
+       (.str name "$pack $FRintieven,$u6,$FRintkeven")
+       (+ pack FRintkeven op FRintieven ope u6)
+       (if (orif (register-unaligned FRintieven 2)
+                (register-unaligned FRintkeven 2))
+          (c-call VOID "@cpu@_media_register_not_aligned")
+          (sequence ()
+                    ; hack to get these referenced for profiling
+                    (set FRintieven (c-raw-call SI "frv_ref_SI" FRintieven))
+                    (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven))
+                    (set (halfword hi FRintkeven 0)
+                         (operation HI (halfword hi FRintieven 0)
+                                       (and u6 #xf)))
+                    (set (halfword lo FRintkeven 0)
+                         (operation HI (halfword lo FRintieven 0)
+                                       (and u6 #xf)))
+                    (set (halfword hi FRintkeven 1)
+                         (operation HI (halfword hi FRintieven 1)
+                                       (and u6 #xf)))
+                    (set (halfword lo FRintkeven 1)
+                         (operation HI (halfword lo FRintieven 1)
+                                       (and u6 #xf)))))
+       ((fr450 (unit u-media-3-quad
+                    (in  FRinti FRintieven)
+                    (in  FRintj FRintieven)
+                    (out FRintk FRintkeven))))
+  )
+)
+
+(media-quad-shift mqsllhi sll OP_78 OPE1_11 "Media quad left shift")
+(media-quad-shift mqsrahi sra OP_78 OPE1_13 "Media quad right shift")
+
+(define-pmacro (media-acc-arith-sat name operation mode max min op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4)
+       (FR400-MAJOR M-1) (FR450-MAJOR M-3))
+       (.str name "$pack $ACC40Si,$ACC40Sk")
+       (+ pack ACC40Sk op ACC40Si ope (ACCj-null))
+       (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Si))
+          (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk))
+              (if (register-unaligned ACC40Si 2)
+                  (c-call VOID "@cpu@_media_acc_not_aligned")
+                  (media-arith-sat-semantics operation ACC40Si
+                                             (nextreg h-acc40S ACC40Si 1)
+                                             ACC40Sk mode max min (msr-sie-acci)))))
+       ((fr400 (unit u-media-2-acc)) (fr450 (unit u-media-2-acc))
+       (fr550 (unit u-media-4-acc)))
+  )
+)
+
+(media-acc-arith-sat maddaccs add DI #x7fffffffff (inv DI #x7fffffffff)
+                    OP_78 OPE1_04 "Media accumulator addition")
+(media-acc-arith-sat msubaccs sub DI #x7fffffffff (inv DI #x7fffffffff)
+                    OP_78 OPE1_05 "Media accumulator subtraction")
+
+(define-pmacro (media-dual-acc-arith-sat name operation mode max min op ope
+                                        comment)
+  (dni name
+       (comment)
+       ((UNIT MDUALACC) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4)
+       (FR400-MAJOR M-2) (FR450-MAJOR M-4))
+       (.str name "$pack $ACC40Si,$ACC40Sk")
+       (+ pack ACC40Sk op ACC40Si ope (ACCj-null))
+       (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Si))
+          (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk))
+              (if (register-unaligned ACC40Si 4)
+                  (c-call VOID "@cpu@_media_acc_not_aligned")
+                  (if (register-unaligned ACC40Sk 2)
+                      (c-call VOID "@cpu@_media_acc_not_aligned")
+                      (sequence ()
+                                (media-arith-sat-semantics operation ACC40Si
+                                                           (nextreg h-acc40S ACC40Si 1)
+                                                           ACC40Sk mode max min
+                                                           (msr-sie-acci))
+                                (media-arith-sat-semantics operation
+                                                           (nextreg h-acc40S ACC40Si 2)
+                                                           (nextreg h-acc40S ACC40Si 3)
+                                                           (nextreg h-acc40S ACC40Sk 1)
+                                                           mode max min
+                                                           (msr-sie-acci-1)))))))
+       ((fr400 (unit u-media-2-acc-dual)) (fr450 (unit u-media-2-acc-dual))
+       (fr550 (unit u-media-4-acc-dual)))
+  )
+)
+
+(media-dual-acc-arith-sat mdaddaccs add DI #x7fffffffff (inv DI #x7fffffffff)
+                         OP_78 OPE1_06 "Media accumulator addition")
+(media-dual-acc-arith-sat mdsubaccs sub DI #x7fffffffff (inv DI #x7fffffffff)
+                         OP_78 OPE1_07 "Media accumulator subtraction")
+
+(dni masaccs
+     "Media add and subtract signed accumulator with saturation"
+       ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4)
+       (FR400-MAJOR M-1) (FR450-MAJOR M-3))
+       "masaccs$pack $ACC40Si,$ACC40Sk"
+       (+ pack ACC40Sk OP_78 ACC40Si OPE1_08 (ACCj-null))
+       (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Si))
+          (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk))
+              (if (register-unaligned ACC40Si 2)
+                  (c-call VOID "@cpu@_media_acc_not_aligned")
+                  (if (register-unaligned ACC40Sk 2)
+                      (c-call VOID "@cpu@_media_acc_not_aligned")
+                      (sequence ()
+                                (media-arith-sat-semantics add ACC40Si
+                                                           (nextreg h-acc40S ACC40Si 1)
+                                                           ACC40Sk DI
+                                                           #x7fffffffff
+                                                           (inv DI #x7fffffffff)
+                                                           (msr-sie-acci))
+                                (media-arith-sat-semantics sub ACC40Si
+                                                           (nextreg h-acc40S ACC40Si 1)
+                                                           (nextreg h-acc40S ACC40Sk 1)
+                                                           DI
+                                                           #x7fffffffff
+                                                           (inv DI #x7fffffffff)
+                                                           (msr-sie-acci-1)))))))
+       ((fr400 (unit u-media-2-add-sub)) (fr450 (unit u-media-2-add-sub))
+       (fr550 (unit u-media-4-add-sub)))
+  )
+
+(dni mdasaccs
+     "Media add and subtract signed accumulator with saturation"
+       ((UNIT MDUALACC) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4)
+       (FR400-MAJOR M-2) (FR450-MAJOR M-4))
+       "mdasaccs$pack $ACC40Si,$ACC40Sk"
+       (+ pack ACC40Sk OP_78 ACC40Si OPE1_09 (ACCj-null))
+       (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Si))
+          (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk))
+              (if (register-unaligned ACC40Si 4)
+                  (c-call VOID "@cpu@_media_acc_not_aligned")
+                  (if (register-unaligned ACC40Sk 4)
+                      (c-call VOID "@cpu@_media_acc_not_aligned")
+                      (sequence ()
+                                (media-arith-sat-semantics add ACC40Si
+                                                           (nextreg h-acc40S ACC40Si 1)
+                                                           ACC40Sk DI
+                                                           #x7fffffffff
+                                                           (inv DI #x7fffffffff)
+                                                           (msr-sie-acci))
+                                (media-arith-sat-semantics sub ACC40Si
+                                                           (nextreg h-acc40S ACC40Si 1)
+                                                           (nextreg h-acc40S ACC40Sk 1)
+                                                           DI
+                                                           #x7fffffffff
+                                                           (inv DI #x7fffffffff)
+                                                           (msr-sie-acci-1))
+                                (media-arith-sat-semantics add
+                                                           (nextreg h-acc40S ACC40Si 2)
+                                                           (nextreg h-acc40S ACC40Si 3)
+                                                           (nextreg h-acc40S ACC40Sk 2)
+                                                           DI
+                                                           #x7fffffffff
+                                                           (inv DI #x7fffffffff)
+                                                           (msr-sie-acci-2))
+                                (media-arith-sat-semantics sub
+                                                           (nextreg h-acc40S ACC40Si 2)
+                                                           (nextreg h-acc40S ACC40Si 3)
+                                                           (nextreg h-acc40S ACC40Sk 3)
+                                                           DI
+                                                           #x7fffffffff
+                                                           (inv DI #x7fffffffff)
+                                                           (msr-sie-acci-3)))))))
+       ((fr400 (unit u-media-2-add-sub-dual))
+       (fr450 (unit u-media-2-add-sub-dual))
+       (fr550 (unit u-media-4-add-sub-dual)))
+  )
+
+(define-pmacro (media-multiply-semantics conv arg1 arg2 res)
+  (set res (mul DI (conv DI arg1) (conv DI arg2)))
+)
+
+(define-pmacro (media-dual-multiply-semantics cond mode conv rhs1 rhs2)
+  (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk))
+      (if (register-unaligned ACC40Sk 2)
+         (c-call VOID "@cpu@_media_acc_not_aligned")
+         (if cond
+             (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo))
+                       (extract-hilo FRinti 0 FRintj 0
+                                     argihi argilo argjhi argjlo)
+                       (media-multiply-semantics conv argihi rhs1 ACC40Sk)
+                       (media-multiply-semantics conv argilo rhs2
+                                                 (nextreg h-acc40S ACC40Sk 1))))))
+)
+
+(define-pmacro (media-dual-multiply name mode conv rhs1 rhs2 op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4)
+       (FR400-MAJOR M-1) (FR450-MAJOR M-3) PRESERVE-OVF)
+       (.str name "$pack $FRinti,$FRintj,$ACC40Sk")
+       (+ pack ACC40Sk op FRinti ope FRintj)
+       (media-dual-multiply-semantics 1 mode conv rhs1 rhs2)
+       ((fr400 (unit u-media-2)) (fr450 (unit u-media-2))
+       (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4)))
+  )
+)
+
+(media-dual-multiply mmulhs  HI ext  argjhi argjlo OP_7B OPE1_14 "Media dual multiply signed")
+(media-dual-multiply mmulhu UHI zext argjhi argjlo OP_7B OPE1_15 "Media dual multiply unsigned")
+
+(media-dual-multiply mmulxhs  HI ext  argjlo argjhi OP_7B OPE1_28 "Media dual cross multiply signed")
+(media-dual-multiply mmulxhu UHI zext argjlo argjhi OP_7B OPE1_29 "Media dual cross multiply unsigned")
+
+(define-pmacro (conditional-media-dual-multiply
+               name mode conv rhs1 rhs2 op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4)
+       (FR400-MAJOR M-1) (FR450-MAJOR M-3)
+       PRESERVE-OVF CONDITIONAL)
+       (.str name "$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond")
+       (+ pack ACC40Sk op FRinti CCi cond ope FRintj)
+       (media-dual-multiply-semantics (eq CCi (or cond 2)) mode conv rhs1 rhs2)
+       ((fr400 (unit u-media-2)) (fr450 (unit u-media-2))
+       (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4)))
+  )
+)
+
+(conditional-media-dual-multiply cmmulhs  HI ext  argjhi argjlo OP_72 OPE4_0 "Conditional Media dual multiply signed")
+(conditional-media-dual-multiply cmmulhu UHI zext argjhi argjlo OP_72 OPE4_1 "Conditional Media dual multiply unsigned")
+
+(define-pmacro (media-quad-multiply-semantics cond mode conv rhs1 rhs2)
+  (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk))
+      (if (register-unaligned ACC40Sk 4)
+         (c-call VOID "@cpu@_media_acc_not_aligned")
+         (if (orif (register-unaligned FRintieven 2)
+                   (register-unaligned FRintjeven 2))
+             (c-call VOID "@cpu@_media_register_not_aligned")
+             (if cond
+                 (sequence ((mode argihi) (mode argilo)
+                            (mode argjhi) (mode argjlo))
+                           (extract-hilo FRintieven 0 FRintjeven 0
+                                         argihi argilo argjhi argjlo)
+                           (media-multiply-semantics conv argihi rhs1 ACC40Sk)
+                           (media-multiply-semantics conv argilo rhs2
+                                                     (nextreg h-acc40S ACC40Sk 1))
+                           (extract-hilo FRintieven 1 FRintjeven 1
+                                         argihi argilo argjhi argjlo)
+                           (media-multiply-semantics conv argihi rhs1
+                                                     (nextreg h-acc40S ACC40Sk 2))
+                           (media-multiply-semantics conv argilo rhs2
+                                                     (nextreg h-acc40S ACC40Sk 3)))))))
+)
+
+(define-pmacro (media-quad-multiply name mode conv rhs1 rhs2 op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4)
+       (FR400-MAJOR M-2) (FR450-MAJOR M-4) PRESERVE-OVF)
+       (.str name "$pack $FRintieven,$FRintjeven,$ACC40Sk")
+       (+ pack ACC40Sk op FRintieven ope FRintjeven)
+       (media-quad-multiply-semantics 1 mode conv rhs1 rhs2) 
+       ((fr400 (unit u-media-2-quad
+                    (in  FRinti FRintieven)
+                    (in  FRintj FRintjeven)))
+       (fr450 (unit u-media-2-quad
+                    (in  FRinti FRintieven)
+                    (in  FRintj FRintjeven)))
+       (fr500 (unit u-media-quad-mul
+                    (in  FRinti FRintieven)
+                    (in  FRintj FRintjeven))) (fr550 (unit u-media-4-quad)))
+  )
+)
+
+(media-quad-multiply mqmulhs  HI ext  argjhi argjlo OP_7B OPE1_1C "Media quad multiply signed")
+(media-quad-multiply mqmulhu UHI zext argjhi argjlo OP_7B OPE1_1D "Media quad multiply unsigned")
+
+(media-quad-multiply mqmulxhs  HI ext  argjlo argjhi OP_7B OPE1_2A "Media quad cross multiply signed")
+(media-quad-multiply mqmulxhu UHI zext argjlo argjhi OP_7B OPE1_2B "Media quad cross multiply unsigned")
+
+(define-pmacro (conditional-media-quad-multiply
+               name mode conv rhs1 rhs2 op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4)
+       (FR400-MAJOR M-2) (FR450-MAJOR M-4)
+       PRESERVE-OVF CONDITIONAL)
+       (.str name "$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond")
+       (+ pack ACC40Sk op FRintieven CCi cond ope FRintjeven)
+       (media-quad-multiply-semantics (eq CCi (or cond 2)) mode conv rhs1 rhs2)
+       ((fr400 (unit u-media-2-quad
+                    (in  FRinti FRintieven)
+                    (in  FRintj FRintjeven)))
+       (fr450 (unit u-media-2-quad
+                    (in  FRinti FRintieven)
+                    (in  FRintj FRintjeven)))
+       (fr500 (unit u-media-quad-mul
+                    (in  FRinti FRintieven)
+                    (in  FRintj FRintjeven))) (fr550 (unit u-media-4-quad)))
+  )
+)
+
+(conditional-media-quad-multiply cmqmulhs  HI ext  argjhi argjlo OP_74 OPE4_0 "Conditional Media quad multiply signed")
+(conditional-media-quad-multiply cmqmulhu UHI zext argjhi argjlo OP_74 OPE4_1 "Conditional Media quad multiply unsigned")
+
+(define-pmacro (media-multiply-acc-semantics 
+               conv arg1 addop arg2 res max min sie)
+  (sequence ((DI tmp))
+           (set tmp (addop res (mul DI (conv DI arg1) (conv DI arg2))))
+           (saturate-v tmp max min sie res))
+)
+
+(define-pmacro (media-dual-multiply-acc-semantics
+               cond mode conv addop rhw res max min)
+  (if (c-call SI "@cpu@_check_acc_range" (index-of res))
+      (if (register-unaligned res 2)
+         (c-call VOID "@cpu@_media_acc_not_aligned")
+         (if cond
+             (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo))
+                       (extract-hilo FRinti 0 FRintj 0
+                                     argihi argilo argjhi argjlo)
+                       (media-multiply-acc-semantics conv argihi addop argjhi
+                                                     res
+                                                     max min (msr-sie-acci))
+                       (media-multiply-acc-semantics conv argilo addop argjlo
+                                                     (nextreg rhw res 1)
+                                                     max min (msr-sie-acci-1))))))
+)
+
+(define-pmacro (media-dual-multiply-acc
+               name mode conv addop rhw res max min op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4)
+       (FR400-MAJOR M-1) (FR450-MAJOR M-3))
+       (.str name "$pack $FRinti,$FRintj,$" res)
+       (+ pack res op FRinti ope FRintj)
+       (media-dual-multiply-acc-semantics 1 mode conv addop rhw res max min)
+       ((fr400 (unit u-media-2)) (fr450 (unit u-media-2))
+       (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4)))
+  )
+)
+
+(media-dual-multiply-acc mmachs HI ext add h-acc40S ACC40Sk
+                        (const DI #x7fffffffff) (const DI #xffffff8000000000)
+                        OP_7B OPE1_16
+                        "Media dual multiply and accumulate signed")
+
+(media-dual-multiply-acc mmachu UHI zext add h-acc40U ACC40Uk
+                        (const DI #xffffffffff) (const DI 0)
+                        OP_7B OPE1_17
+                        "Media dual multiply and accumulate unsigned")
+
+(media-dual-multiply-acc mmrdhs HI ext sub h-acc40S ACC40Sk
+                        (const DI #x7fffffffff) (const DI #xffffff8000000000)
+                        OP_7B OPE1_30
+                        "Media dual multiply and reduce signed")
+
+(media-dual-multiply-acc mmrdhu UHI zext sub h-acc40U ACC40Uk
+                        (const DI #xffffffffff) (const DI 0)
+                        OP_7B OPE1_31
+                        "Media dual multiply and reduce unsigned")
+
+(define-pmacro (conditional-media-dual-multiply-acc
+               name mode conv addop rhw res max min op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4)
+       (FR400-MAJOR M-1) (FR450-MAJOR M-3) CONDITIONAL)
+       (.str name "$pack $FRinti,$FRintj,$" res ",$CCi,$cond")
+       (+ pack res op FRinti CCi cond ope FRintj)
+       (media-dual-multiply-acc-semantics (eq CCi (or cond 2))
+                                         mode conv addop rhw res max min)
+       ((fr400 (unit u-media-2)) (fr450 (unit u-media-2))
+       (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4)))
+  )
+)
+
+(conditional-media-dual-multiply-acc cmmachs HI ext add h-acc40S ACC40Sk
+                        (const DI #x7fffffffff) (const DI #xffffff8000000000)
+                        OP_72 OPE4_2
+                        "Conditional Media dual multiply and accumulate signed")
+
+(conditional-media-dual-multiply-acc cmmachu UHI zext add  h-acc40U ACC40Uk
+                        (const DI #xffffffffff) (const DI 0)
+                        OP_72 OPE4_3
+                        "Conditional Media dual multiply and accumulate unsigned")
+
+(define-pmacro (media-quad-multiply-acc-semantics
+               cond mode conv addop rhw res max min)
+  (if (c-call SI "@cpu@_check_acc_range" (index-of res))
+      (if (register-unaligned res 4)
+         (c-call VOID "@cpu@_media_acc_not_aligned")
+         (if (orif (register-unaligned FRintieven 2)
+                   (register-unaligned FRintjeven 2))
+             (c-call VOID "@cpu@_media_register_not_aligned")
+             (if cond
+                 (sequence ((mode argihi) (mode argilo)
+                            (mode argjhi) (mode argjlo))
+                           (extract-hilo FRintieven 0 FRintjeven 0
+                                         argihi argilo argjhi argjlo)
+                           (media-multiply-acc-semantics conv argihi addop argjhi
+                                                         res
+                                                         max min (msr-sie-acci))
+                           (media-multiply-acc-semantics conv argilo addop argjlo
+                                                         (nextreg rhw res 1)
+                                                         max min (msr-sie-acci-1))
+                           (extract-hilo FRintieven 1 FRintjeven 1
+                                         argihi argilo argjhi argjlo)
+                           (media-multiply-acc-semantics conv argihi addop argjhi
+                                                         (nextreg rhw res 2)
+                                                         max min (msr-sie-acci-2))
+                           (media-multiply-acc-semantics conv argilo addop argjlo
+                                                         (nextreg rhw res 3)
+                                                         max min
+                                                         (msr-sie-acci-3)))))))
+)
+
+(define-pmacro (media-quad-multiply-acc
+               name mode conv addop rhw res max min op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4)
+       (FR400-MAJOR M-2) (FR450-MAJOR M-4))
+       (.str name "$pack $FRintieven,$FRintjeven,$" res)
+       (+ pack res op FRintieven ope FRintjeven)
+       (media-quad-multiply-acc-semantics 1 mode conv addop rhw res max min)
+       ((fr400 (unit u-media-2-quad
+                    (in  FRinti FRintieven)
+                    (in  FRintj FRintjeven)))
+       (fr450 (unit u-media-2-quad
+                    (in  FRinti FRintieven)
+                    (in  FRintj FRintjeven)))
+       (fr500 (unit u-media-quad-mul
+                    (in  FRinti FRintieven)
+                    (in  FRintj FRintjeven))) (fr550 (unit u-media-4-quad)))
+  )
+)
+
+(media-quad-multiply-acc mqmachs HI ext add h-acc40S ACC40Sk
+                        (const DI #x7fffffffff) (const DI #xffffff8000000000)
+                        OP_7B OPE1_1E
+                        "Media quad multiply and accumulate signed")
+
+(media-quad-multiply-acc mqmachu UHI zext add h-acc40U ACC40Uk
+                        (const DI #xffffffffff) (const DI 0)
+                        OP_7B OPE1_1F
+                        "Media quad multiply and accumulate unsigned")
+
+(define-pmacro (conditional-media-quad-multiply-acc
+               name mode conv addop rhw res max min op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4)
+       (FR400-MAJOR M-2) (FR450-MAJOR M-4) CONDITIONAL)
+       (.str name "$pack $FRintieven,$FRintjeven,$" res ",$CCi,$cond")
+       (+ pack res op FRintieven CCi cond ope FRintjeven)
+       (media-quad-multiply-acc-semantics (eq CCi (or cond 2))
+                                         mode conv addop rhw res max min)
+       ((fr400 (unit u-media-2-quad
+                    (in  FRinti FRintieven)
+                    (in  FRintj FRintjeven)))
+       (fr450 (unit u-media-2-quad
+                    (in  FRinti FRintieven)
+                    (in  FRintj FRintjeven)))
+       (fr500 (unit u-media-quad-mul
+                    (in  FRinti FRintieven)
+                    (in  FRintj FRintjeven))) (fr550 (unit u-media-4-quad)))
+  )
+)
+
+(conditional-media-quad-multiply-acc cmqmachs HI ext add h-acc40S ACC40Sk
+                        (const DI #x7fffffffff) (const DI #xffffff8000000000)
+                        OP_74 OPE4_2
+                        "Conditional Media quad multiply and accumulate signed")
+
+(conditional-media-quad-multiply-acc cmqmachu UHI zext add h-acc40U ACC40Uk
+                        (const DI #xffffffffff) (const DI 0)
+                        OP_74 OPE4_3
+                        "Conditional media quad multiply and accumulate unsigned")
+
+(define-pmacro (media-quad-multiply-cross-acc-semantics
+               cond mode conv addop rhw res max min)
+  (if (c-call SI "@cpu@_check_acc_range" (index-of res))
+      (if (register-unaligned res 4)
+         (c-call VOID "@cpu@_media_acc_not_aligned")
+         (if (orif (register-unaligned FRintieven 2)
+                   (register-unaligned FRintjeven 2))
+             (c-call VOID "@cpu@_media_register_not_aligned")
+             (if cond
+                 (sequence ((mode argihi) (mode argilo)
+                            (mode argjhi) (mode argjlo))
+                           (extract-hilo FRintieven 0 FRintjeven 0
+                                         argihi argilo argjhi argjlo)
+                           (media-multiply-acc-semantics conv argihi addop argjhi
+                                                         (nextreg rhw res 2)
+                                                         max min (msr-sie-acci-2))
+                           (media-multiply-acc-semantics conv argilo addop argjlo
+                                                         (nextreg rhw res 3)
+                                                         max min (msr-sie-acci-3))
+                           (extract-hilo FRintieven 1 FRintjeven 1
+                                         argihi argilo argjhi argjlo)
+                           (media-multiply-acc-semantics conv argihi addop argjhi
+                                                         res
+                                                         max min (msr-sie-acci))
+                           (media-multiply-acc-semantics conv argilo addop argjlo
+                                                         (nextreg rhw res 1)
+                                                         max min
+                                                         (msr-sie-acci-1)))))))
+)
+
+(define-pmacro (media-quad-multiply-cross-acc
+               name mode conv addop rhw res max min op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4)
+       (FR400-MAJOR M-2) (FR450-MAJOR M-4))
+       (.str name "$pack $FRintieven,$FRintjeven,$" res)
+       (+ pack res op FRintieven ope FRintjeven)
+       (media-quad-multiply-cross-acc-semantics 1 mode conv addop rhw res
+                                               max min)
+       ((fr400 (unit u-media-2-quad
+                    (in  FRinti FRintieven)
+                    (in  FRintj FRintjeven)))
+       (fr450 (unit u-media-2-quad
+                    (in  FRinti FRintieven)
+                    (in  FRintj FRintjeven)))
+       (fr550 (unit u-media-4-quad)))
+  )
+)
+
+(media-quad-multiply-cross-acc mqxmachs HI ext add h-acc40S ACC40Sk
+                        (const DI #x7fffffffff) (const DI #xffffff8000000000)
+                        OP_78 OPE1_00
+                        "Media quad multiply and cross accumulate signed")
+
+(define-pmacro (media-quad-cross-multiply-cross-acc-semantics
+               cond mode conv addop rhw res max min)
+  (if (c-call SI "@cpu@_check_acc_range" (index-of res))
+      (if (register-unaligned res 4)
+         (c-call VOID "@cpu@_media_acc_not_aligned")
+         (if (orif (register-unaligned FRintieven 2)
+                   (register-unaligned FRintjeven 2))
+             (c-call VOID "@cpu@_media_register_not_aligned")
+             (if cond
+                 (sequence ((mode argihi) (mode argilo)
+                            (mode argjhi) (mode argjlo))
+                           (extract-hilo FRintieven 0 FRintjeven 0
+                                         argihi argilo argjhi argjlo)
+                           (media-multiply-acc-semantics conv argihi addop argjlo
+                                                         (nextreg rhw res 2)
+                                                         max min (msr-sie-acci-2))
+                           (media-multiply-acc-semantics conv argilo addop argjhi
+                                                         (nextreg rhw res 3)
+                                                         max min (msr-sie-acci-3))
+                           (extract-hilo FRintieven 1 FRintjeven 1
+                                         argihi argilo argjhi argjlo)
+                           (media-multiply-acc-semantics conv argihi addop argjlo
+                                                         res
+                                                         max min (msr-sie-acci))
+                           (media-multiply-acc-semantics conv argilo addop argjhi
+                                                         (nextreg rhw res 1)
+                                                         max min
+                                                         (msr-sie-acci-1)))))))
+)
+
+(define-pmacro (media-quad-cross-multiply-cross-acc
+               name mode conv addop rhw res max min op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4)
+       (FR400-MAJOR M-2) (FR450-MAJOR M-4))
+       (.str name "$pack $FRintieven,$FRintjeven,$" res)
+       (+ pack res op FRintieven ope FRintjeven)
+       (media-quad-cross-multiply-cross-acc-semantics 1 mode conv addop rhw res
+                                                     max min)
+       ((fr400 (unit u-media-2-quad
+                    (in  FRinti FRintieven)
+                    (in  FRintj FRintjeven)))
+       (fr450 (unit u-media-2-quad
+                    (in  FRinti FRintieven)
+                    (in  FRintj FRintjeven)))
+       (fr550 (unit u-media-4-quad)))
+  )
+)
+
+(media-quad-cross-multiply-cross-acc mqxmacxhs HI ext add h-acc40S ACC40Sk
+                       (const DI #x7fffffffff) (const DI #xffffff8000000000)
+                       OP_78 OPE1_01
+                       "Media quad cross multiply and cross accumulate signed")
+
+(define-pmacro (media-quad-cross-multiply-acc-semantics
+               cond mode conv addop rhw res max min)
+  (if (c-call SI "@cpu@_check_acc_range" (index-of res))
+      (if (register-unaligned res 4)
+         (c-call VOID "@cpu@_media_acc_not_aligned")
+         (if (orif (register-unaligned FRintieven 2)
+                   (register-unaligned FRintjeven 2))
+             (c-call VOID "@cpu@_media_register_not_aligned")
+             (if cond
+                 (sequence ((mode argihi) (mode argilo)
+                            (mode argjhi) (mode argjlo))
+                           (extract-hilo FRintieven 0 FRintjeven 0
+                                         argihi argilo argjhi argjlo)
+                           (media-multiply-acc-semantics conv argihi addop argjlo
+                                                         res
+                                                         max min (msr-sie-acci))
+                           (media-multiply-acc-semantics conv argilo addop argjhi
+                                                         (nextreg rhw res 1)
+                                                         max min (msr-sie-acci-1))
+                           (extract-hilo FRintieven 1 FRintjeven 1
+                                         argihi argilo argjhi argjlo)
+                           (media-multiply-acc-semantics conv argihi addop argjlo
+                                                         (nextreg rhw res 2)
+                                                         max min (msr-sie-acci-2))
+                           (media-multiply-acc-semantics conv argilo addop argjhi
+                                                         (nextreg rhw res 3)
+                                                         max min
+                                                         (msr-sie-acci-3)))))))
+)
+
+(define-pmacro (media-quad-cross-multiply-acc
+               name mode conv addop rhw res max min op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4)
+       (FR400-MAJOR M-2) (FR450-MAJOR M-4))
+       (.str name "$pack $FRintieven,$FRintjeven,$" res)
+       (+ pack res op FRintieven ope FRintjeven)
+       (media-quad-cross-multiply-acc-semantics 1 mode conv addop rhw res
+                                               max min)
+       ((fr400 (unit u-media-2-quad
+                    (in FRinti FRintieven)
+                    (in FRintj FRintjeven)))
+       (fr450 (unit u-media-2-quad
+                    (in FRinti FRintieven)
+                    (in FRintj FRintjeven)))
+       (fr550 (unit u-media-4-quad)))
+  )
+)
+
+(media-quad-cross-multiply-acc mqmacxhs HI ext add h-acc40S ACC40Sk
+                       (const DI #x7fffffffff) (const DI #xffffff8000000000)
+                       OP_78 OPE1_02
+                       "Media quad cross multiply and accumulate signed")
+
+(define-pmacro (media-complex-semantics
+               conv lhs1 rhs1 lhs2 rhs2 res max min sie)
+  (sequence ((DI tmp1) (DI tmp2))
+           (media-multiply-semantics conv lhs1 rhs1 tmp1)
+           (media-multiply-semantics conv lhs2 rhs2 tmp2)
+           (set tmp1 (sub tmp1 tmp2))
+           (saturate-v tmp1 max min sie res))
+)
+
+(define-pmacro (media-complex-semantics-i
+               conv lhs1 rhs1 lhs2 rhs2 res max min sie)
+  (sequence ((DI tmp1) (DI tmp2))
+           (media-multiply-semantics conv lhs1 rhs1 tmp1)
+           (media-multiply-semantics conv lhs2 rhs2 tmp2)
+           (set tmp1 (add tmp1 tmp2))
+           (saturate-v tmp1 max min sie res))
+)
+
+(define-pmacro (media-dual-complex-semantics mode conv rhs1 rhs2 max min)
+  (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk))
+      (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo))
+               (extract-hilo FRinti 0 FRintj 0 argihi argilo argjhi argjlo)
+               (media-complex-semantics conv argihi rhs1 argilo rhs2 ACC40Sk
+                                        max min (msr-sie-acci))))
+)
+
+(define-pmacro (media-dual-complex-semantics-i mode conv rhs1 rhs2 max min)
+  (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk))
+      (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo))
+               (extract-hilo FRinti 0 FRintj 0 argihi argilo argjhi argjlo)
+               (media-complex-semantics-i conv argihi rhs1 argilo rhs2 ACC40Sk
+                                          max min (msr-sie-acci))))
+)
+
+(define-pmacro (media-dual-complex
+               name mode conv rhs1 rhs2 max min op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4)
+       (FR400-MAJOR M-1) (FR450-MAJOR M-3))
+       (.str name "$pack $FRinti,$FRintj,$ACC40Sk")
+       (+ pack ACC40Sk op FRinti ope FRintj)
+       (media-dual-complex-semantics mode conv rhs1 rhs2 max min)
+       ((fr400 (unit u-media-2)) (fr450 (unit u-media-2))
+       (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4)))
+  )
+)
+
+(define-pmacro (media-dual-complex-i
+               name mode conv rhs1 rhs2 max min op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4)
+       (FR400-MAJOR M-1) (FR450-MAJOR M-3))
+       (.str name "$pack $FRinti,$FRintj,$ACC40Sk")
+       (+ pack ACC40Sk op FRinti ope FRintj)
+       (media-dual-complex-semantics-i mode conv rhs1 rhs2 max min)
+       ((fr400 (unit u-media-2)) (fr450 (unit u-media-2))
+       (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4)))
+  )
+)
+
+(media-dual-complex mcpxrs HI ext argjhi argjlo
+                   (const DI #x7fffffffff) (const DI #xffffff8000000000)
+                   OP_7B OPE1_20
+                   "Media dual complex real signed with saturation")
+
+(media-dual-complex mcpxru UHI zext argjhi argjlo
+                   (const DI #xffffffffff) (const DI 0)
+                   OP_7B OPE1_21
+                   "Media dual complex real unsigned with saturation")
+
+(media-dual-complex-i mcpxis HI ext argjlo argjhi
+                   (const DI #x7fffffffff) (const DI #xffffff8000000000)
+                   OP_7B OPE1_22
+                   "Media dual complex imaginary signed with saturation")
+
+(media-dual-complex-i mcpxiu UHI zext argjlo argjhi
+                   (const DI #xffffffffff) (const DI 0)
+                   OP_7B OPE1_23
+                   "Media dual complex imaginary unsigned with saturation")
+
+(define-pmacro (conditional-media-dual-complex
+               name mode conv rhs1 rhs2 max min op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4)
+       (FR400-MAJOR M-1) (FR450-MAJOR M-3) CONDITIONAL)
+       (.str name "$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond")
+       (+ pack ACC40Sk op FRinti CCi cond ope FRintj)
+       (if (eq CCi (or cond 2))
+          (media-dual-complex-semantics mode conv rhs1 rhs2 max min))
+       ((fr400 (unit u-media-2)) (fr450 (unit u-media-2))
+       (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4)))
+  )
+)
+
+(define-pmacro (conditional-media-dual-complex-i
+               name mode conv rhs1 rhs2 max min op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4)
+       (FR400-MAJOR M-1) (FR450-MAJOR M-3) CONDITIONAL)
+       (.str name "$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond")
+       (+ pack ACC40Sk op FRinti CCi cond ope FRintj)
+       (if (eq CCi (or cond 2))
+          (media-dual-complex-semantics-i mode conv rhs1 rhs2 max min))
+       ((fr400 (unit u-media-2)) (fr450 (unit u-media-2))
+       (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4)))
+  )
+)
+
+(conditional-media-dual-complex cmcpxrs HI ext argjhi argjlo
+                   (const DI #x7fffffffff) (const DI #xffffff8000000000)
+                   OP_75 OPE4_0
+                   "Conditional Media dual complex real signed with saturation")
+
+(conditional-media-dual-complex cmcpxru UHI zext argjhi argjlo
+                   (const DI #xffffffffff) (const DI 0)
+                   OP_75 OPE4_1
+                   "Conditional Media dual complex real unsigned with saturation")
+
+(conditional-media-dual-complex-i cmcpxis HI ext argjlo argjhi
+                   (const DI #x7fffffffff) (const DI #xffffff8000000000)
+                   OP_75 OPE4_2
+                   "Conditional Media dual complex imaginary signed with saturation")
+
+(conditional-media-dual-complex-i cmcpxiu UHI zext argjlo argjhi
+                   (const DI #xffffffffff) (const DI 0)
+                   OP_75 OPE4_3
+                   "Conditional Media dual complex imaginary unsigned with saturation")
+
+(define-pmacro (media-quad-complex
+               name mode conv rhs1 rhs2 max min op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4)
+       (FR400-MAJOR M-2) (FR450-MAJOR M-4))
+       (.str name "$pack $FRintieven,$FRintjeven,$ACC40Sk")
+       (+ pack ACC40Sk op FRintieven ope FRintjeven)
+       (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk))
+          (if (register-unaligned ACC40Sk 2)
+              (c-call VOID "@cpu@_media_acc_not_aligned")
+              (if (orif (register-unaligned FRintieven 2)
+                        (register-unaligned FRintjeven 2))
+                  (c-call VOID "@cpu@_media_register_not_aligned")
+                  (sequence ((mode argihi) (mode argilo)
+                             (mode argjhi) (mode argjlo))
+                            (extract-hilo FRintieven 0 FRintjeven 0
+                                          argihi argilo argjhi argjlo)
+                            (media-complex-semantics conv argihi rhs1 argilo rhs2
+                                                     ACC40Sk
+                                                     max min (msr-sie-acci))
+                            (extract-hilo FRintieven 1 FRintjeven 1
+                                          argihi argilo argjhi argjlo)
+                            (media-complex-semantics conv argihi rhs1 argilo rhs2
+                                                     (nextreg h-acc40S ACC40Sk 1)
+                                                     max min (msr-sie-acci-1))))))
+       ((fr400 (unit u-media-2-quad
+                    (in FRinti FRintieven)
+                    (in FRintj FRintjeven)))
+       (fr450 (unit u-media-2-quad
+                    (in FRinti FRintieven)
+                    (in FRintj FRintjeven)))
+       (fr500 (unit u-media-quad-complex
+                    (in FRinti FRintieven)
+                    (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad)))
+  )
+)
+
+(define-pmacro (media-quad-complex-i
+               name mode conv rhs1 rhs2 max min op ope comment)
+  (dni name
+       (comment)
+       ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4)
+       (FR400-MAJOR M-2) (FR450-MAJOR M-4))
+       (.str name "$pack $FRintieven,$FRintjeven,$ACC40Sk")
+       (+ pack ACC40Sk op FRintieven ope FRintjeven)
+       (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk))
+          (if (register-unaligned ACC40Sk 2)
+              (c-call VOID "@cpu@_media_acc_not_aligned")
+              (if (orif (register-unaligned FRintieven 2)
+                        (register-unaligned FRintjeven 2))
+                  (c-call VOID "@cpu@_media_register_not_aligned")
+                  (sequence ((mode argihi) (mode argilo)
+                             (mode argjhi) (mode argjlo))
+                            (extract-hilo FRintieven 0 FRintjeven 0
+                                          argihi argilo argjhi argjlo)
+                            (media-complex-semantics-i conv argihi rhs1 argilo rhs2
+                                                       ACC40Sk
+                                                       max min (msr-sie-acci))
+                            (extract-hilo FRintieven 1 FRintjeven 1
+                                          argihi argilo argjhi argjlo)
+                            (media-complex-semantics-i conv argihi rhs1 argilo rhs2
+                                                       (nextreg h-acc40S ACC40Sk 1)
+                                                       max min (msr-sie-acci-1))))))
+       ((fr400 (unit u-media-2-quad
+                    (in FRinti FRintieven)
+                    (in FRintj FRintjeven)))
+       (fr450 (unit u-media-2-quad
+                    (in FRinti FRintieven)
+                    (in FRintj FRintjeven)))
+       (fr500 (unit u-media-quad-complex
+                    (in FRinti FRintieven)
+                    (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad)))
+  )
+)
+
+(media-quad-complex mqcpxrs HI ext argjhi argjlo
+                   (const DI #x7fffffffff) (const DI #xffffff8000000000)
+                   OP_7B OPE1_24
+                   "Media quad complex real signed with saturation")
+
+(media-quad-complex mqcpxru UHI zext argjhi argjlo
+                   (const DI #xffffffffff) (const DI 0)
+                   OP_7B OPE1_25
+                   "Media quad complex real unsigned with saturation")
+
+(media-quad-complex-i mqcpxis HI ext argjlo argjhi
+                   (const DI #x7fffffffff) (const DI #xffffff8000000000)
+                   OP_7B OPE1_26
+                   "Media quad complex imaginary signed with saturation")
+
+(media-quad-complex-i mqcpxiu UHI zext argjlo argjhi
+                   (const DI #xffffffffff) (const DI 0)
+                   OP_7B OPE1_27
+                   "Media quad complex imaginary unsigned with saturation")
+
+(define-pmacro (media-pack src1 src2 targ offset)
+  (sequence ()
+           (set (halfword hi targ offset) (halfword lo src1 offset))
+           (set (halfword lo targ offset) (halfword lo src2 offset)))
+)
+
+(define-pmacro (media-expand-halfword-to-word-semantics cond)
+  (if cond
+      (sequence ((UHI tmp))
+               (if (and u6 1)
+                   (set tmp (halfword lo FRinti 0))
+                   (set tmp (halfword hi FRinti 0)))
+               (set (halfword hi FRintk 0) tmp)
+               (set (halfword lo FRintk 0) tmp)))
+)
+
+(dni mexpdhw
+     "Media expand halfword to word"
+     ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+      (FR400-MAJOR M-1) (FR450-MAJOR M-1))
+     "mexpdhw$pack $FRinti,$u6,$FRintk"
+     (+ pack FRintk OP_7B FRinti OPE1_32 u6)
+     (media-expand-halfword-to-word-semantics 1)
+     ((fr400 (unit u-media-3)) (fr450 (unit u-media-3))
+      (fr500 (unit u-media)) (fr550 (unit u-media)))
+)
+
+(dni cmexpdhw
+     "Conditional media expand halfword to word"
+     ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+      (FR400-MAJOR M-1) (FR450-MAJOR M-1) CONDITIONAL)
+     "cmexpdhw$pack $FRinti,$u6,$FRintk,$CCi,$cond"
+     (+ pack FRintk OP_76 FRinti CCi cond OPE4_2 u6)
+     (media-expand-halfword-to-word-semantics (eq CCi (or cond 2)))
+     ((fr400 (unit u-media-3)) (fr450 (unit u-media-3))
+      (fr500 (unit u-media)) (fr550 (unit u-media)))
+)
+
+(define-pmacro (media-expand-halfword-to-double-semantics cond)
+  (if (register-unaligned FRintkeven 2)
+      (c-call VOID "@cpu@_media_register_not_aligned")
+      (if cond
+         (sequence ((UHI tmp))
+                   ; a hack to get FRintkeven referenced for profiling
+                   (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven))
+                   (if (and u6 1)
+                       (set tmp (halfword lo FRinti 0))
+                       (set tmp (halfword hi FRinti 0)))
+                   (set (halfword hi FRintkeven 0) tmp)
+                   (set (halfword lo FRintkeven 0) tmp)
+                   (set (halfword hi FRintkeven 1) tmp)
+                   (set (halfword lo FRintkeven 1) tmp))))
+)
+
+(dni mexpdhd
+     "Media expand halfword to double"
+     ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+      (FR400-MAJOR M-2) (FR450-MAJOR M-2))
+     "mexpdhd$pack $FRinti,$u6,$FRintkeven"
+     (+ pack FRintkeven OP_7B FRinti OPE1_33 u6)
+     (media-expand-halfword-to-double-semantics 1)
+     ((fr400 (unit u-media-dual-expand
+                  (out FRintk FRintkeven)))
+      (fr450 (unit u-media-dual-expand
+                  (out FRintk FRintkeven)))
+      (fr500 (unit u-media-dual-expand
+                  (out FRintk FRintkeven)))
+      (fr550 (unit u-media-dual-expand)))
+)
+
+(dni cmexpdhd
+     "Conditional media expand halfword to double"
+     ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+      (FR400-MAJOR M-2) (FR450-MAJOR M-2) CONDITIONAL)
+     "cmexpdhd$pack $FRinti,$u6,$FRintkeven,$CCi,$cond"
+     (+ pack FRintkeven OP_76 FRinti CCi cond OPE4_3 u6)
+     (media-expand-halfword-to-double-semantics (eq CCi (or cond 2)))
+     ((fr400 (unit u-media-dual-expand
+                  (out FRintk FRintkeven)))
+      (fr450 (unit u-media-dual-expand
+                  (out FRintk FRintkeven)))
+      (fr500 (unit u-media-dual-expand
+                  (out FRintk FRintkeven)))
+      (fr550 (unit u-media-dual-expand)))
+)
+
+(dni mpackh
+     "Media halfword pack"
+     ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+      (FR400-MAJOR M-1) (FR450-MAJOR M-1))
+     "mpackh$pack $FRinti,$FRintj,$FRintk"
+     (+ pack FRintk OP_7B FRinti OPE1_34 FRintj)
+     (media-pack FRinti FRintj FRintk 0)
+     ((fr400 (unit u-media-3)) (fr450 (unit u-media-3))
+      (fr500 (unit u-media)) (fr550 (unit u-media)))
+)
+
+(dni mdpackh
+     "Media dual pack"
+     ((UNIT FM01) (FR500-MAJOR M-5) (FR550-MAJOR M-3)
+      (FR400-MAJOR M-2) (FR450-MAJOR M-2))
+     "mdpackh$pack $FRintieven,$FRintjeven,$FRintkeven"
+     (+ pack FRintkeven OP_7B FRintieven OPE1_36 FRintjeven)
+     (if (orif (register-unaligned FRintieven 2)
+              (orif (register-unaligned FRintjeven 2)
+                    (register-unaligned FRintkeven 2)))
+        (c-call VOID "@cpu@_media_register_not_aligned")
+        (sequence ()
+                  ; hack to get these referenced for profiling
+                  (set FRintieven (c-raw-call SI "frv_ref_SI" FRintieven))
+                  (set FRintjeven (c-raw-call SI "frv_ref_SI" FRintjeven))
+                  (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven))
+                  (media-pack FRintieven FRintjeven FRintkeven 0)
+                  (media-pack FRintieven FRintjeven FRintkeven 1)))
+     ((fr400 (unit u-media-3-quad
+                  (in  FRinti FRintieven)
+                  (in  FRintj FRintjeven)
+                  (out FRintk FRintkeven)))
+      (fr450 (unit u-media-3-quad
+                  (in  FRinti FRintieven)
+                  (in  FRintj FRintjeven)
+                  (out FRintk FRintkeven)))
+      (fr500 (unit u-media-quad-arith
+                  (in  FRinti FRintieven)
+                  (in  FRintj FRintjeven)
+                  (out FRintk FRintkeven)))
+      (fr550 (unit u-media-quad)))
+)
+
+(define-pmacro (media-unpack src soff targ toff)
+  (sequence ()
+           (set (halfword hi targ toff) (halfword hi src soff))
+           (set (halfword lo targ toff) (halfword hi src soff))
+           (set (halfword hi targ (add toff 1)) (halfword lo src soff))
+           (set (halfword lo targ (add toff 1)) (halfword lo src soff)))
+)
+
+(dni munpackh
+     "Media halfword unpack"
+     ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+      (FR400-MAJOR M-2) (FR450-MAJOR M-2))
+     "munpackh$pack $FRinti,$FRintkeven"
+     (+ pack FRintkeven OP_7B FRinti OPE1_35 (FRj-null))
+     (if (register-unaligned FRintkeven 2)
+        (c-call VOID "@cpu@_media_register_not_aligned")
+        (sequence ()
+                  ; hack to get these referenced for profiling
+                  (set FRinti (c-raw-call SI "frv_ref_SI" FRinti))
+                  (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven))
+                  (media-unpack FRinti 0 FRintkeven 0)))
+     ((fr400 (unit u-media-dual-expand
+                  (out FRintk FRintkeven)))
+      (fr450 (unit u-media-dual-expand
+                  (out FRintk FRintkeven)))
+      (fr500 (unit u-media-dual-expand
+                  (out FRintk FRintkeven)))
+      (fr550 (unit u-media-dual-expand)))
+)
+
+(dni mdunpackh
+     "Media dual unpack"
+     ((UNIT FM01) (FR500-MAJOR M-7) (MACH simple,tomcat,frv))
+     "mdunpackh$pack $FRintieven,$FRintk"
+     (+ pack FRintk OP_7B FRintieven OPE1_37 (FRj-null))
+     (if (orif (register-unaligned FRintieven 2) (register-unaligned FRintk 4))
+        (c-call VOID "@cpu@_media_register_not_aligned")
+        (sequence ()
+                  ; hack to get these referenced for profiling
+                  (set FRintieven (c-raw-call SI "frv_ref_SI" FRintieven))
+                  (set FRintk (c-raw-call SI "frv_ref_SI" FRintk))
+                  (media-unpack FRintieven 0 FRintk 0)
+                  (media-unpack FRintieven 1 FRintk 2)))
+     ((fr500 (unit u-media-dual-unpack
+                  (in FRinti FRintieven))))
+)
+
+(define-pmacro (ubyte num arg offset)
+  (reg (.sym h-fr_ num) (add (index-of arg) offset)))
+
+(define-pmacro (mbtoh-semantics cond)
+  (if (register-unaligned FRintkeven 2)
+      (c-call VOID "@cpu@_media_register_not_aligned")
+      (if cond
+         (sequence ()
+                   (set (halfword hi FRintkeven 0) (ubyte 3 FRintj 0))
+                   (set (halfword lo FRintkeven 0) (ubyte 2 FRintj 0))
+                   (set (halfword hi FRintkeven 1) (ubyte 1 FRintj 0))
+                   (set (halfword lo FRintkeven 1) (ubyte 0 FRintj 0)))))
+)
+
+(dni mbtoh
+     "Media convert byte to halfword"
+     ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+      (FR400-MAJOR M-2) (FR450-MAJOR M-2))
+     "mbtoh$pack $FRintj,$FRintkeven"
+     (+ pack FRintkeven OP_7B (FRi-null) OPE1_38 FRintj)
+     (sequence ()
+              ; hack to get these referenced for profiling
+              (set FRintj (c-raw-call SI "frv_ref_SI" FRintj))
+              (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven))
+              (mbtoh-semantics 1))
+     ((fr400 (unit u-media-dual-expand
+                  (out FRintk FRintkeven)))
+      (fr450 (unit u-media-dual-expand
+                  (out FRintk FRintkeven)))
+      (fr500 (unit u-media-dual-btoh
+                  (out FRintk FRintkeven)))
+      (fr550 (unit u-media-dual-expand)))
+)
+
+(dni cmbtoh
+     "Conditional media convert byte to halfword"
+     ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+      (FR400-MAJOR M-2) (FR450-MAJOR M-2) CONDITIONAL)
+     "cmbtoh$pack $FRintj,$FRintkeven,$CCi,$cond"
+     (+ pack FRintkeven OP_77 (FRi-null) CCi cond OPE4_0 FRintj)
+     (sequence ()
+              ; hack to get these referenced for profiling
+              (set FRintj (c-raw-call SI "frv_ref_SI" FRintj))
+              (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven))
+              (mbtoh-semantics (eq CCi (or cond 2))))
+     ((fr400 (unit u-media-dual-expand
+                  (out FRintk FRintkeven)))
+      (fr450 (unit u-media-dual-expand
+                  (out FRintk FRintkeven)))
+      (fr500 (unit u-media-dual-btoh
+                  (out FRintk FRintkeven)))
+      (fr550 (unit u-media-dual-expand
+                  (in FRinti FRintj))))
+)
+
+(define-pmacro (mhtob-semantics cond)
+  (if (register-unaligned FRintjeven 2)
+      (c-call VOID "@cpu@_media_register_not_aligned")
+      (if cond
+         (sequence ()
+                   (set (ubyte 3 FRintk 0) (halfword hi FRintjeven 0))
+                   (set (ubyte 2 FRintk 0) (halfword lo FRintjeven 0))
+                   (set (ubyte 1 FRintk 0) (halfword hi FRintjeven 1))
+                   (set (ubyte 0 FRintk 0) (halfword lo FRintjeven 1)))))
+)
+
+(dni mhtob
+     "Media convert halfword to byte"
+     ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+      (FR400-MAJOR M-2) (FR450-MAJOR M-2))
+     "mhtob$pack $FRintjeven,$FRintk"
+     (+ pack FRintk OP_7B (FRi-null) OPE1_39 FRintjeven)
+     (sequence ()
+              ; hack to get these referenced for profiling
+              (set FRintjeven (c-raw-call SI "frv_ref_SI" FRintjeven))
+              (set FRintk (c-raw-call SI "frv_ref_SI" FRintk))
+              (mhtob-semantics 1))
+     ((fr400 (unit u-media-dual-htob
+                  (in FRintj FRintjeven)))
+      (fr450 (unit u-media-dual-htob
+                  (in FRintj FRintjeven)))
+      (fr500 (unit u-media-dual-htob
+                  (in FRintj FRintjeven)))
+      (fr550 (unit u-media-3-dual
+                  (in FRinti FRintjeven))))
+)
+
+(dni cmhtob
+     "Conditional media convert halfword to byte"
+     ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+      (FR400-MAJOR M-2) (FR450-MAJOR M-2) CONDITIONAL)
+     "cmhtob$pack $FRintjeven,$FRintk,$CCi,$cond"
+     (+ pack FRintk OP_77 (FRi-null) CCi cond OPE4_1 FRintjeven)
+     (sequence ()
+              ; hack to get these referenced for profiling
+              (set FRintjeven (c-raw-call SI "frv_ref_SI" FRintjeven))
+              (set FRintk (c-raw-call SI "frv_ref_SI" FRintk))
+              (mhtob-semantics (eq CCi (or cond 2))))
+     ((fr400 (unit u-media-dual-htob
+                  (in FRintj FRintjeven)))
+      (fr450 (unit u-media-dual-htob
+                  (in FRintj FRintjeven)))
+      (fr500 (unit u-media-dual-htob
+                  (in FRintj FRintjeven)))
+      (fr550 (unit u-media-3-dual
+                  (in FRinti FRintjeven))))
+)
+
+(define-pmacro (mbtohe-semantics cond)
+  (if (register-unaligned FRintk 4)
+      (c-call VOID "@cpu@_media_register_not_aligned")
+      (if cond
+         (sequence ()
+                   (set (halfword hi FRintk 0) (ubyte 3 FRintj 0))
+                   (set (halfword lo FRintk 0) (ubyte 3 FRintj 0))
+                   (set (halfword hi FRintk 1) (ubyte 2 FRintj 0))
+                   (set (halfword lo FRintk 1) (ubyte 2 FRintj 0))
+                   (set (halfword hi FRintk 2) (ubyte 1 FRintj 0))
+                   (set (halfword lo FRintk 2) (ubyte 1 FRintj 0))
+                   (set (halfword hi FRintk 3) (ubyte 0 FRintj 0))
+                   (set (halfword lo FRintk 3) (ubyte 0 FRintj 0)))))
+)
+
+(dni mbtohe
+     "Media convert byte to halfword extended"
+     ((UNIT FM01) (FR500-MAJOR M-7) (MACH simple,tomcat,frv))
+     "mbtohe$pack $FRintj,$FRintk"
+     (+ pack FRintk OP_7B (FRi-null) OPE1_3A FRintj)
+     (sequence ()
+              ; hack to get these referenced for profiling
+              (set FRintj (c-raw-call SI "frv_ref_SI" FRintj))
+              (set FRintk (c-raw-call SI "frv_ref_SI" FRintk))
+              (mbtohe-semantics 1))
+     ((fr500 (unit u-media-dual-btohe)))
+)
+
+(dni cmbtohe
+     "Conditional media convert byte to halfword extended"
+     ((UNIT FM01) (FR500-MAJOR M-7) CONDITIONAL (MACH simple,tomcat,frv))
+     "cmbtohe$pack $FRintj,$FRintk,$CCi,$cond"
+     (+ pack FRintk OP_77 (FRi-null) CCi cond OPE4_2 FRintj)
+     (sequence ()
+              ; hack to get these referenced for profiling
+              (set FRintj (c-raw-call SI "frv_ref_SI" FRintj))
+              (set FRintk (c-raw-call SI "frv_ref_SI" FRintk))
+              (mbtohe-semantics (eq CCi (or cond 2))))
+     ((fr500 (unit u-media-dual-btohe)))
+)
+
+; Media NOP
+; A special case of mclracc
+(dni mnop "Media nop"
+     ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-1)
+      (FR400-MAJOR M-1) (FR450-MAJOR M-1))
+     "mnop$pack"
+     (+ pack (f-ACC40Sk 63) OP_7B (f-A 1) (misc-null-10) OPE1_3B (FRj-null))
+     (nop)
+     ()
+)
+
+; mclracc with #A==0
+(dni mclracc-0
+     "Media clear accumulator(s)"
+     ((UNIT FM01) (FR500-MAJOR M-3) (FR550-MAJOR M-3)
+      (FR400-MAJOR M-1) (FR450-MAJOR M-3))
+     "mclracc$pack $ACC40Sk,$A0"
+     (+ pack ACC40Sk OP_7B (f-A 0) (misc-null-10) OPE1_3B (FRj-null))
+     (c-call VOID "@cpu@_clear_accumulators" (index-of ACC40Sk) 0)
+     ((fr400 (unit u-media-4)) (fr450 (unit u-media-4))
+      (fr500 (unit u-media)) (fr550 (unit u-media-3-mclracc)))
+)
+
+; mclracc with #A==1
+(dni mclracc-1
+     "Media clear accumulator(s)"
+     ((UNIT MCLRACC-1) (FR500-MAJOR M-6) (FR550-MAJOR M-3)
+      (FR400-MAJOR M-2) (FR450-MAJOR M-4))
+     "mclracc$pack $ACC40Sk,$A1"
+     (+ pack ACC40Sk OP_7B (f-A 1) (misc-null-10) OPE1_3B (FRj-null))
+     (c-call VOID "@cpu@_clear_accumulators" (index-of ACC40Sk) 1)
+     ((fr400 (unit u-media-4)) (fr450 (unit u-media-4-mclracca))
+      (fr500 (unit u-media)) (fr550 (unit u-media-3-mclracc)))
+)
+
+(dni mrdacc
+     "Media read accumulator"
+     ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+      (FR400-MAJOR M-1) (FR450-MAJOR M-5))
+     "mrdacc$pack $ACC40Si,$FRintk"
+     (+ pack FRintk OP_7B ACC40Si OPE1_3C (FRj-null))
+     (set FRintk ACC40Si)
+     ((fr400 (unit u-media-4)) (fr450 (unit u-media-4))
+      (fr500 (unit u-media)) (fr550 (unit u-media-3-acc)))
+)
+
+(dni mrdaccg
+     "Media read accumulator guard"
+     ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+      (FR400-MAJOR M-1) (FR450-MAJOR M-5))
+     "mrdaccg$pack $ACCGi,$FRintk"
+     (+ pack FRintk OP_7B ACCGi OPE1_3E (FRj-null))
+     (set FRintk ACCGi)
+     ((fr400 (unit u-media-4-accg)) (fr450 (unit u-media-4-accg))
+      (fr500 (unit u-media)) (fr550 (unit u-media-3-acc (in ACC40Si ACCGi))))
+)
+
+(dni mwtacc
+     "Media write accumulator"
+     ((UNIT FM01) (FR500-MAJOR M-3) (FR550-MAJOR M-3)
+      (FR400-MAJOR M-1) (FR450-MAJOR M-3))
+     "mwtacc$pack $FRinti,$ACC40Sk"
+     (+ pack ACC40Sk OP_7B FRinti OPE1_3D (FRj-null))
+     (set ACC40Sk (or (and ACC40Sk (const DI #xffffffff00000000))
+                    FRinti))
+     ((fr400 (unit u-media-4)) (fr450 (unit u-media-4))
+      (fr500 (unit u-media)) (fr550 (unit u-media-3-wtacc)))
+)
+
+(dni mwtaccg
+     "Media write accumulator guard"
+     ((UNIT FM01) (FR500-MAJOR M-3) (FR550-MAJOR M-3)
+      (FR400-MAJOR M-1) (FR450-MAJOR M-3))
+     "mwtaccg$pack $FRinti,$ACCGk"
+     (+ pack ACCGk OP_7B FRinti OPE1_3F (FRj-null))
+     (sequence ()
+              ; hack to get these referenced for profiling
+              (c-raw-call VOID "frv_ref_SI" ACCGk)
+              (set ACCGk FRinti))
+     ((fr400 (unit u-media-4-accg)) (fr450 (unit u-media-4-accg))
+      (fr500 (unit u-media)) (fr550 (unit u-media-3-wtacc (in ACC40Sk ACCGk))))
+)
+
+(define-pmacro (media-cop num op)
+  (dni (.sym mcop num)
+       "Media custom instruction"
+       ((UNIT FM01) (FR500-MAJOR M-1) (MACH frv))
+       (.str "mcop" num "$pack $FRi,$FRj,$FRk")
+       (+ pack FRk op FRi OPE1_00 FRj)
+       (c-call VOID "@cpu@_media_cop" num)
+       ()
+  )
+)
+
+(media-cop 1 OP_7C)
+(media-cop 2 OP_7D)
+
+; nop
+; A nop is defined to be a "ori gr0,0,gr0"
+; This needn't be a macro-insn, but making it one greatly simplifies decode.c
+; On the other hand spending a little time in the decoder is often worth it.
+;
+(dnmi nop "nop"
+     ((UNIT IALL) (FR500-MAJOR I-1) (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+     "nop$pack"
+     (emit ori pack (GRi 0) (s12 0) (GRk 0))
+)
+
+; Floating point NOP
+(dni fnop
+     "Floating point nop"
+     ((UNIT FMALL) (FR500-MAJOR F-8) (FR550-MAJOR F-1) (MACH simple,tomcat,fr500,fr550,frv))
+     "fnop$pack"
+     (+ pack (rd-null) OP_79 (FRi-null) OPE1_0D (FRj-null))
+     (nop)
+     ()
+)
+
+; A return instruction
+(dnmi ret "return"
+      (NO-DIS (UNIT B01) (FR500-MAJOR B-3)
+             (FR400-MAJOR B-3) (FR450-MAJOR B-3))
+      "ret$pack"
+      (emit bralr pack (hint_taken 2))
+)
+
+(dnmi cmp "compare"
+      (NO-DIS (UNIT IALL) (FR500-MAJOR I-1)
+             (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+      "cmp$pack $GRi,$GRj,$ICCi_1"
+      (emit subcc pack GRi GRj (GRk 0) ICCi_1)
+)
+
+(dnmi cmpi "compare immediate"
+      (NO-DIS (UNIT IALL) (FR500-MAJOR I-1)
+             (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+      "cmpi$pack $GRi,$s10,$ICCi_1"
+      (emit subicc pack GRi s10 (GRk 0) ICCi_1)
+)
+
+(dnmi ccmp "conditional compare"
+      (NO-DIS (UNIT IALL) (FR500-MAJOR I-1)
+             (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
+      "ccmp$pack $GRi,$GRj,$CCi,$cond"
+      (emit csubcc pack GRi GRj (GRk 0) CCi cond)
+)
+
+(dnmi mov "move"
+      (NO-DIS (UNIT IALL) (FR500-MAJOR I-1)
+             (FR400-MAJOR I-1) (FR450-MAJOR I-1))
+      "mov$pack $GRi,$GRk"
+      (emit ori pack GRi (s12 0) GRk)
+)   
+
+(dnmi cmov "conditional move"
+      (NO-DIS (UNIT IALL) (FR500-MAJOR I-1)
+             (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
+      "cmov$pack $GRi,$GRk,$CCi,$cond"
+      (emit cor pack GRi (GRj 0) GRk CCi cond)
+)   

diff --git a/cpu/frv.opc b/cpu/frv.opc
new file mode 100644 (file)
index 0000000..0b9c93c
--- /dev/null
+++ b/cpu/frv.opc
@@ -0,0 +1,1918 @@
+/* Fujitsu FRV opcode support, for GNU Binutils.  -*- C -*-
+
+   Copyright 2000, 2001, 2003, 2004, 2005, 2007, 2009
+   Free Software Foundation, Inc.
+
+   Contributed by Red Hat Inc; developed under contract from Fujitsu.
+
+   This file is part of the GNU Binutils.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+
+/* This file is an addendum to frv.cpu.  Heavy use of C code isn't
+   appropriate in .cpu files, so it resides here.  This especially applies
+   to assembly/disassembly where parsing/printing can be quite involved.
+   Such things aren't really part of the specification of the cpu, per se,
+   so .cpu files provide the general framework and .opc files handle the
+   nitty-gritty details as necessary.
+
+   Each section is delimited with start and end markers.
+
+   <arch>-opc.h additions use: "-- opc.h"
+   <arch>-opc.c additions use: "-- opc.c"
+   <arch>-asm.c additions use: "-- asm.c"
+   <arch>-dis.c additions use: "-- dis.c"
+   <arch>-ibd.h additions use: "-- ibd.h".  */
+\f
+/* -- opc.h */
+
+#undef  CGEN_DIS_HASH_SIZE
+#define CGEN_DIS_HASH_SIZE 128
+#undef  CGEN_DIS_HASH
+#define CGEN_DIS_HASH(buffer, value) (((value) >> 18) & 127)
+
+/* Allows reason codes to be output when assembler errors occur.  */
+#define CGEN_VERBOSE_ASSEMBLER_ERRORS
+
+/* Vliw support.  */
+#define FRV_VLIW_SIZE 8 /* fr550 has largest vliw size of 8.  */
+#define PAD_VLIW_COMBO ,UNIT_NIL,UNIT_NIL,UNIT_NIL,UNIT_NIL
+
+typedef CGEN_ATTR_VALUE_ENUM_TYPE VLIW_COMBO[FRV_VLIW_SIZE];
+
+typedef struct
+{
+  int                    next_slot;
+  int                    constraint_violation;
+  unsigned long          mach;
+  unsigned long          elf_flags;
+  CGEN_ATTR_VALUE_ENUM_TYPE * unit_mapping;
+  VLIW_COMBO *           current_vliw;
+  CGEN_ATTR_VALUE_ENUM_TYPE   major[FRV_VLIW_SIZE];
+  const CGEN_INSN *      insn[FRV_VLIW_SIZE];
+} FRV_VLIW;
+
+int frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
+int frv_is_float_major  (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
+int frv_is_media_major  (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
+int frv_is_branch_insn  (const CGEN_INSN *);
+int frv_is_float_insn   (const CGEN_INSN *);
+int frv_is_media_insn   (const CGEN_INSN *);
+void frv_vliw_reset     (FRV_VLIW *, unsigned long, unsigned long);
+int frv_vliw_add_insn   (FRV_VLIW *, const CGEN_INSN *);
+int spr_valid           (long);
+/* -- */
+\f
+/* -- opc.c */
+#include "elf/frv.h"
+#include <stdio.h>
+
+/* Returns TRUE if {MAJOR,MACH} is a major branch of the FRV
+   development tree.  */
+
+bfd_boolean
+frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach)
+{
+  switch (mach)
+    {
+    case bfd_mach_fr400:
+      if (major >= FR400_MAJOR_B_1 && major <= FR400_MAJOR_B_6)
+       return TRUE;
+      break;
+    case bfd_mach_fr450:
+      if (major >= FR450_MAJOR_B_1 && major <= FR450_MAJOR_B_6)
+       return TRUE;
+      break;
+    default:
+      if (major >= FR500_MAJOR_B_1 && major <= FR500_MAJOR_B_6)
+       return TRUE;
+      break;
+    }
+
+  return FALSE;
+}
+
+/* Returns TRUE if {MAJOR,MACH} supports floating point insns.  */
+
+bfd_boolean
+frv_is_float_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach)
+{
+  switch (mach)
+    {
+    case bfd_mach_fr400:
+    case bfd_mach_fr450:
+      return FALSE;
+    default:
+      if (major >= FR500_MAJOR_F_1 && major <= FR500_MAJOR_F_8)
+       return TRUE;
+      break;
+    }
+
+  return FALSE;
+}
+
+/* Returns TRUE if {MAJOR,MACH} supports media insns.  */
+
+bfd_boolean
+frv_is_media_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach)
+{
+  switch (mach)
+    {
+    case bfd_mach_fr400:
+      if (major >= FR400_MAJOR_M_1 && major <= FR400_MAJOR_M_2)
+       return TRUE;
+      break;
+    case bfd_mach_fr450:
+      if (major >= FR450_MAJOR_M_1 && major <= FR450_MAJOR_M_6)
+       return TRUE;
+      break;
+    default:
+      if (major >= FR500_MAJOR_M_1 && major <= FR500_MAJOR_M_8)
+       return TRUE;
+      break;
+    }
+
+  return FALSE;
+}
+
+bfd_boolean
+frv_is_branch_insn (const CGEN_INSN *insn)
+{
+  if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
+                          bfd_mach_fr400))
+    return TRUE;
+  if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR),
+                          bfd_mach_fr450))
+    return TRUE;
+  if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
+                          bfd_mach_fr500))
+    return TRUE;
+
+  return FALSE;
+}
+
+bfd_boolean
+frv_is_float_insn (const CGEN_INSN *insn)
+{
+  if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
+                         bfd_mach_fr400))
+    return TRUE;
+  if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR),
+                         bfd_mach_fr450))
+    return TRUE;
+  if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
+                         bfd_mach_fr500))
+    return TRUE;
+
+  return FALSE;
+}
+
+bfd_boolean
+frv_is_media_insn (const CGEN_INSN *insn)
+{
+  if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
+                         bfd_mach_fr400))
+    return TRUE;
+  if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR),
+                         bfd_mach_fr450))
+    return TRUE;
+  if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
+                         bfd_mach_fr500))
+    return TRUE;
+
+  return FALSE;
+}
+
+/* This table represents the allowable packing for vliw insns for the fr400.
+   The fr400 has only 2 vliw slots. Represent this by not allowing any insns
+   in the extra slots.
+   Subsets of any given row are also allowed.  */
+static VLIW_COMBO fr400_allowed_vliw[] =
+{
+  /*  slot0       slot1       slot2       slot3    */
+  {  UNIT_I0,    UNIT_I1,    UNIT_NIL,   UNIT_NIL  PAD_VLIW_COMBO },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_NIL,   UNIT_NIL  PAD_VLIW_COMBO },
+  {  UNIT_I0,    UNIT_B0,    UNIT_NIL,   UNIT_NIL  PAD_VLIW_COMBO },
+  {  UNIT_FM0,   UNIT_FM1,   UNIT_NIL,   UNIT_NIL  PAD_VLIW_COMBO },
+  {  UNIT_FM0,   UNIT_B0,    UNIT_NIL,   UNIT_NIL  PAD_VLIW_COMBO },
+  {  UNIT_B0,    UNIT_NIL,   UNIT_NIL,   UNIT_NIL  PAD_VLIW_COMBO },
+  {  UNIT_C,     UNIT_NIL,   UNIT_NIL,   UNIT_NIL  PAD_VLIW_COMBO },
+  {  UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL  PAD_VLIW_COMBO }
+};
+
+/* This table represents the allowable packing for vliw insns for the fr500.
+   The fr500 has only 4 vliw slots. Represent this by not allowing any insns
+   in the extra slots.
+   Subsets of any given row are also allowed.  */
+static VLIW_COMBO fr500_allowed_vliw[] =
+{
+  /*  slot0       slot1       slot2       slot3    */
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_FM1  PAD_VLIW_COMBO },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_B0   PAD_VLIW_COMBO },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_FM1,   UNIT_B0   PAD_VLIW_COMBO },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_B0,    UNIT_B1   PAD_VLIW_COMBO },
+  {  UNIT_I0,    UNIT_I1,    UNIT_B0,    UNIT_B1   PAD_VLIW_COMBO },
+  {  UNIT_I0,    UNIT_B0,    UNIT_B1,    UNIT_NIL  PAD_VLIW_COMBO },
+  {  UNIT_FM0,   UNIT_FM1,   UNIT_B0,    UNIT_B1   PAD_VLIW_COMBO },
+  {  UNIT_FM0,   UNIT_B0,    UNIT_B1,    UNIT_NIL  PAD_VLIW_COMBO },
+  {  UNIT_B0,    UNIT_B1,    UNIT_NIL,   UNIT_NIL  PAD_VLIW_COMBO },
+  {  UNIT_C,     UNIT_NIL,   UNIT_NIL,   UNIT_NIL  PAD_VLIW_COMBO },
+  {  UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL  PAD_VLIW_COMBO }
+};
+
+/* This table represents the allowable packing for vliw insns for the fr550.
+   Subsets of any given row are also allowed.  */
+static VLIW_COMBO fr550_allowed_vliw[] =
+{
+  /*  slot0       slot1       slot2       slot3       slot4       slot5       slot6       slot7   */
+  {  UNIT_I0,    UNIT_I1,    UNIT_I2,    UNIT_I3,    UNIT_B0,    UNIT_B1 ,   UNIT_NIL,   UNIT_NIL },
+  {  UNIT_I0,    UNIT_I1,    UNIT_I2,    UNIT_B0,    UNIT_B1 ,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL },
+  {  UNIT_I0,    UNIT_I1,    UNIT_B0,    UNIT_B1 ,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL },
+  {  UNIT_I0,    UNIT_B0,    UNIT_B1 ,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_FM1,   UNIT_I2,    UNIT_FM2,   UNIT_I3,    UNIT_FM3 },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_FM1,   UNIT_I2,    UNIT_FM2,   UNIT_I3,    UNIT_B0  },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_FM1,   UNIT_I2,    UNIT_FM2,   UNIT_FM3,   UNIT_B0  },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_FM1,   UNIT_I2,    UNIT_FM2,   UNIT_B0,    UNIT_B1  },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_FM1,   UNIT_I2,    UNIT_I3,    UNIT_B0,    UNIT_B1  },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_FM1,   UNIT_I2,    UNIT_B0,    UNIT_B1,    UNIT_NIL },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_FM1,   UNIT_FM2,   UNIT_FM3,   UNIT_B0,    UNIT_B1  },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_FM1,   UNIT_FM2,   UNIT_FM3,   UNIT_B0,    UNIT_B1  },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_FM1,   UNIT_FM2,   UNIT_B0,    UNIT_B1,    UNIT_NIL },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_FM1,   UNIT_B0,    UNIT_B1,    UNIT_NIL,   UNIT_NIL },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_I2,    UNIT_I3,    UNIT_B0,    UNIT_B1,    UNIT_NIL },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_I2,    UNIT_B0,    UNIT_B1,    UNIT_NIL,   UNIT_NIL },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_B0,    UNIT_B1,    UNIT_NIL,   UNIT_NIL,   UNIT_NIL },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_FM1,   UNIT_FM2,   UNIT_FM3,   UNIT_B0,    UNIT_B1,    UNIT_NIL },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_FM1,   UNIT_FM2,   UNIT_B0,    UNIT_B1,    UNIT_NIL,   UNIT_NIL },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_FM1,   UNIT_B0,    UNIT_B1,    UNIT_NIL,   UNIT_NIL,   UNIT_NIL },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_B0,    UNIT_B1,    UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL },
+  {  UNIT_B0,    UNIT_B1,    UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL },
+  {  UNIT_C,     UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL },
+  {  UNIT_FM0,   UNIT_FM1,   UNIT_FM2,   UNIT_FM3,   UNIT_B0,    UNIT_B1,    UNIT_NIL,   UNIT_NIL },
+  {  UNIT_FM0,   UNIT_FM1,   UNIT_FM2,   UNIT_B0,    UNIT_B1,    UNIT_NIL,   UNIT_NIL,   UNIT_NIL },
+  {  UNIT_FM0,   UNIT_FM1,   UNIT_B0,    UNIT_B1,    UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL },
+  {  UNIT_FM0,   UNIT_B0,    UNIT_B1,    UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL },
+  {  UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL }
+};
+
+/* Some insns are assigned specialized implementation units which map to
+   different actual implementation units on different machines.  These
+   tables perform that mapping.  */
+static CGEN_ATTR_VALUE_ENUM_TYPE fr400_unit_mapping[] =
+{
+/* unit in insn    actual unit */
+/* NIL      */     UNIT_NIL,
+/* I0       */     UNIT_I0,
+/* I1       */     UNIT_I1,
+/* I01      */     UNIT_I01, 
+/* I2       */     UNIT_NIL, /* no I2 or I3 unit */
+/* I3       */     UNIT_NIL,
+/* IALL     */     UNIT_I01, /* only I0 and I1 units */
+/* FM0      */     UNIT_FM0,
+/* FM1      */     UNIT_FM1,
+/* FM01     */     UNIT_FM01,
+/* FM2      */     UNIT_NIL, /* no F2 or M2 units */
+/* FM3      */     UNIT_NIL, /* no F3 or M3 units */
+/* FMALL    */     UNIT_FM01,/* Only F0,F1,M0,M1 units */
+/* FMLOW    */     UNIT_FM0, /* Only F0,M0 units */
+/* B0       */     UNIT_B0,  /* branches only in B0 unit.  */
+/* B1       */     UNIT_B0,
+/* B01      */     UNIT_B0,
+/* C        */     UNIT_C,
+/* MULT-DIV */     UNIT_I0,  /* multiply and divide only in I0  unit.  */
+/* IACC     */     UNIT_I01, /* iacc multiply       in I0 or I1 unit.  */
+/* LOAD     */     UNIT_I0,  /* load                only in I0  unit.  */
+/* STORE    */     UNIT_I0,  /* store               only in I0  unit.  */
+/* SCAN     */     UNIT_I0,  /* scan                only in I0  unit.  */
+/* DCPL     */     UNIT_C,   /* dcpl                only in C   unit.  */
+/* MDUALACC */     UNIT_FM0, /* media dual acc insn only in FM0 unit.  */
+/* MDCUTSSI */     UNIT_FM0, /* mdcutssi            only in FM0 unit.  */
+/* MCLRACC-1*/     UNIT_FM0  /* mclracc,A==1   insn only in FM0 unit.  */
+};
+
+/* Some insns are assigned specialized implementation units which map to
+   different actual implementation units on different machines.  These
+   tables perform that mapping.  */
+static CGEN_ATTR_VALUE_ENUM_TYPE fr450_unit_mapping[] =
+{
+/* unit in insn    actual unit */
+/* NIL      */     UNIT_NIL,
+/* I0       */     UNIT_I0,
+/* I1       */     UNIT_I1,
+/* I01      */     UNIT_I01, 
+/* I2       */     UNIT_NIL, /* no I2 or I3 unit */
+/* I3       */     UNIT_NIL,
+/* IALL     */     UNIT_I01, /* only I0 and I1 units */
+/* FM0      */     UNIT_FM0,
+/* FM1      */     UNIT_FM1,
+/* FM01     */     UNIT_FM01,
+/* FM2      */     UNIT_NIL, /* no F2 or M2 units */
+/* FM3      */     UNIT_NIL, /* no F3 or M3 units */
+/* FMALL    */     UNIT_FM01,/* Only F0,F1,M0,M1 units */
+/* FMLOW    */     UNIT_FM0, /* Only F0,M0 units */
+/* B0       */     UNIT_B0,  /* branches only in B0 unit.  */
+/* B1       */     UNIT_B0,
+/* B01      */     UNIT_B0,
+/* C        */     UNIT_C,
+/* MULT-DIV */     UNIT_I0,  /* multiply and divide only in I0  unit.  */
+/* IACC     */     UNIT_I01, /* iacc multiply       in I0 or I1 unit.  */
+/* LOAD     */     UNIT_I0,  /* load                only in I0  unit.  */
+/* STORE    */     UNIT_I0,  /* store               only in I0  unit.  */
+/* SCAN     */     UNIT_I0,  /* scan                only in I0  unit.  */
+/* DCPL     */     UNIT_I0,  /* dcpl                only in I0  unit.  */
+/* MDUALACC */     UNIT_FM0, /* media dual acc insn only in FM0 unit.  */
+/* MDCUTSSI */     UNIT_FM01, /* mdcutssi           in FM0 or FM1.  */
+/* MCLRACC-1*/     UNIT_FM0  /* mclracc,A==1   insn only in FM0 unit.  */
+};
+
+static CGEN_ATTR_VALUE_ENUM_TYPE fr500_unit_mapping[] =
+{
+/* unit in insn    actual unit */
+/* NIL      */     UNIT_NIL,
+/* I0       */     UNIT_I0,
+/* I1       */     UNIT_I1,
+/* I01      */     UNIT_I01, 
+/* I2       */     UNIT_NIL, /* no I2 or I3 unit */
+/* I3       */     UNIT_NIL,
+/* IALL     */     UNIT_I01, /* only I0 and I1 units */
+/* FM0      */     UNIT_FM0,
+/* FM1      */     UNIT_FM1,
+/* FM01     */     UNIT_FM01,
+/* FM2      */     UNIT_NIL, /* no F2 or M2 units */
+/* FM3      */     UNIT_NIL, /* no F3 or M2 units */
+/* FMALL    */     UNIT_FM01,/* Only F0,F1,M0,M1 units */
+/* FMLOW    */     UNIT_FM0, /* Only F0,M0 units */
+/* B0       */     UNIT_B0,
+/* B1       */     UNIT_B1,
+/* B01      */     UNIT_B01,
+/* C        */     UNIT_C,
+/* MULT-DIV */     UNIT_I01, /* multiply and divide in I0 or I1 unit.  */
+/* IACC     */     UNIT_NIL, /* iacc multiply       not implemented */
+/* LOAD     */     UNIT_I01, /* load                in I0 or I1 unit.  */
+/* STORE    */     UNIT_I0,  /* store               only in I0 unit.  */
+/* SCAN     */     UNIT_I01, /* scan                in I0 or I1 unit.  */
+/* DCPL     */     UNIT_C,   /* dcpl                only in C unit.  */
+/* MDUALACC */     UNIT_FM0, /* media dual acc insn only in FM0 unit.  */
+/* MDCUTSSI */     UNIT_FM0, /* mdcutssi            only in FM0 unit.  */
+/* MCLRACC-1*/     UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit.  */
+};
+
+static CGEN_ATTR_VALUE_ENUM_TYPE fr550_unit_mapping[] =
+{
+/* unit in insn    actual unit */
+/* NIL      */     UNIT_NIL,
+/* I0       */     UNIT_I0,
+/* I1       */     UNIT_I1,
+/* I01      */     UNIT_I01, 
+/* I2       */     UNIT_I2,
+/* I3       */     UNIT_I3,
+/* IALL     */     UNIT_IALL, 
+/* FM0      */     UNIT_FM0,
+/* FM1      */     UNIT_FM1,
+/* FM01     */     UNIT_FM01,
+/* FM2      */     UNIT_FM2,
+/* FM3      */     UNIT_FM3,
+/* FMALL    */     UNIT_FMALL,
+/* FMLOW    */     UNIT_FM01, /* Only F0,F1,M0,M1 units */
+/* B0       */     UNIT_B0,
+/* B1       */     UNIT_B1,
+/* B01      */     UNIT_B01,
+/* C        */     UNIT_C,
+/* MULT-DIV */     UNIT_I01,  /* multiply and divide in I0 or I1 unit.    */
+/* IACC     */     UNIT_NIL,  /* iacc multiply       not implemented.     */
+/* LOAD     */     UNIT_I01,  /* load                in I0 or I1 unit.    */
+/* STORE    */     UNIT_I01,  /* store               in I0 or I1 unit.    */
+/* SCAN     */     UNIT_IALL, /* scan                in any integer unit. */
+/* DCPL     */     UNIT_I0,   /* dcpl                only in I0 unit.     */
+/* MDUALACC */     UNIT_FMALL,/* media dual acc insn in all media units   */
+/* MDCUTSSI */     UNIT_FM01, /* mdcutssi            in FM0 or FM1 unit.  */
+/* MCLRACC-1*/     UNIT_FM01  /* mclracc,A==1 in FM0 or FM1 unit.         */
+};
+
+void
+frv_vliw_reset (FRV_VLIW *vliw, unsigned long mach, unsigned long elf_flags)
+{
+  vliw->next_slot = 0;
+  vliw->constraint_violation = 0;
+  vliw->mach = mach;
+  vliw->elf_flags = elf_flags;
+
+  switch (mach)
+    {
+    case bfd_mach_fr400:
+      vliw->current_vliw = fr400_allowed_vliw;
+      vliw->unit_mapping = fr400_unit_mapping;
+      break;
+    case bfd_mach_fr450:
+      vliw->current_vliw = fr400_allowed_vliw;
+      vliw->unit_mapping = fr450_unit_mapping;
+      break;
+    case bfd_mach_fr550:
+      vliw->current_vliw = fr550_allowed_vliw;
+      vliw->unit_mapping = fr550_unit_mapping;
+      break;
+    default:
+      vliw->current_vliw = fr500_allowed_vliw;
+      vliw->unit_mapping = fr500_unit_mapping;
+      break;
+    }
+}
+
+/* Return TRUE if unit1 is a match for unit2.
+   Unit1 comes from the insn's UNIT attribute. unit2 comes from one of the
+   *_allowed_vliw tables above.  */
+static bfd_boolean
+match_unit (FRV_VLIW *vliw,
+           CGEN_ATTR_VALUE_ENUM_TYPE unit1, CGEN_ATTR_VALUE_ENUM_TYPE unit2)
+{
+  /* Map any specialized implementation units to actual ones.  */
+  unit1 = vliw->unit_mapping[unit1];
+
+  if (unit1 == unit2)
+    return TRUE;
+  if (unit1 < unit2)
+    return FALSE;
+
+  switch (unit1)
+    {
+    case UNIT_I01:
+    case UNIT_FM01:
+    case UNIT_B01:
+      /* The 01 versions of these units are within 2 enums of the 0 or 1
+        versions.  */
+      if (unit1 - unit2 <= 2)
+       return TRUE;
+      break;
+    case UNIT_IALL:
+    case UNIT_FMALL:
+      /* The ALL versions of these units are within 5 enums of the 0, 1, 2 or 3
+        versions.  */
+      if (unit1 - unit2 <= 5)
+       return TRUE;
+      break;
+    default:
+      break;
+    }
+
+  return FALSE;
+}
+
+/* Return TRUE if the vliws match, FALSE otherwise.  */
+
+static bfd_boolean
+match_vliw (VLIW_COMBO *vliw1, VLIW_COMBO *vliw2, int vliw_size)
+{
+  int i;
+
+  for (i = 0; i < vliw_size; ++i)
+    if ((*vliw1)[i] != (*vliw2)[i])
+      return FALSE;
+
+  return TRUE;
+}
+
+/* Find the next vliw vliw in the table that can accomodate the new insn.
+   If one is found then return it. Otherwise return NULL.  */
+
+static VLIW_COMBO *
+add_next_to_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE unit)
+{
+  int           next    = vliw->next_slot;
+  VLIW_COMBO    *current = vliw->current_vliw;
+  VLIW_COMBO    *potential;
+
+  if (next <= 0)
+    {
+      fprintf (stderr, "frv-opc.c line %d: bad vliw->next_slot value.\n",
+              __LINE__);
+      abort (); /* Should never happen.  */
+    }
+
+  /* The table is sorted by units allowed within slots, so vliws with
+     identical starting sequences are together.  */
+  potential = current;
+  do
+    {
+      if (match_unit (vliw, unit, (*potential)[next]))
+       return potential;
+      ++potential;
+    }
+  while (match_vliw (potential, current, next));
+
+  return NULL;
+}
+
+/* Look for the given major insn type in the given vliw.
+   Returns TRUE if found, FALSE otherwise.  */
+
+static bfd_boolean
+find_major_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major)
+{
+  int i;
+
+  for (i = 0; i < vliw->next_slot; ++i)
+    if (vliw->major[i] == major)
+      return TRUE;
+
+  return FALSE;
+}
+
+/* Check for constraints between the insns in the vliw due to major insn
+   types.  */
+
+static bfd_boolean
+fr400_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major)
+{
+  /* In the cpu file, all media insns are represented as being allowed in
+     both media units. This makes it easier since this is the case for fr500.
+     Catch the invalid combinations here.  Insns of major class FR400_MAJOR_M_2
+     cannot coexist with any other media insn in a vliw.  */
+  switch (major)
+    {
+    case FR400_MAJOR_M_2:
+      return ! find_major_in_vliw (vliw, FR400_MAJOR_M_1)
+       &&   ! find_major_in_vliw (vliw, FR400_MAJOR_M_2);
+    case FR400_MAJOR_M_1:
+      return ! find_major_in_vliw (vliw, FR400_MAJOR_M_2);
+    default:
+      break;
+    }
+  return TRUE;
+}
+
+static bfd_boolean
+fr450_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major)
+{
+  CGEN_ATTR_VALUE_ENUM_TYPE other_major;
+
+  /* Our caller guarantees there's at least one other instruction.  */
+  other_major = CGEN_INSN_ATTR_VALUE (vliw->insn[0], CGEN_INSN_FR450_MAJOR);
+
+  /* (M4, M5) and (M4, M6) are allowed.  */
+  if (other_major == FR450_MAJOR_M_4)
+    if (major == FR450_MAJOR_M_5 || major == FR450_MAJOR_M_6)
+      return TRUE;
+
+  /* Otherwise, instructions in even-numbered media categories cannot be
+     executed in parallel with other media instructions.  */
+  switch (major)
+    {
+    case FR450_MAJOR_M_2:
+    case FR450_MAJOR_M_4:
+    case FR450_MAJOR_M_6:
+      return !(other_major >= FR450_MAJOR_M_1
+              && other_major <= FR450_MAJOR_M_6);
+
+    case FR450_MAJOR_M_1:
+    case FR450_MAJOR_M_3:
+    case FR450_MAJOR_M_5:
+      return !(other_major == FR450_MAJOR_M_2
+              || other_major == FR450_MAJOR_M_4
+              || other_major == FR450_MAJOR_M_6);
+
+    default:
+      return TRUE;
+    }
+}
+
+static bfd_boolean
+find_unit_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE unit)
+{
+  int i;
+
+  for (i = 0; i < vliw->next_slot; ++i)
+    if (CGEN_INSN_ATTR_VALUE (vliw->insn[i], CGEN_INSN_UNIT) == unit)
+      return TRUE;
+
+  return FALSE; /* Not found.  */
+}
+
+static bfd_boolean
+find_major_in_slot (FRV_VLIW *vliw,
+                   CGEN_ATTR_VALUE_ENUM_TYPE major,
+                   CGEN_ATTR_VALUE_ENUM_TYPE slot)
+{
+  int i;
+
+  for (i = 0; i < vliw->next_slot; ++i)
+    if (vliw->major[i] == major && (*vliw->current_vliw)[i] == slot)
+      return TRUE;
+
+  return FALSE;
+}
+
+static bfd_boolean
+fr550_find_media_in_vliw (FRV_VLIW *vliw)
+{
+  int i;
+
+  for (i = 0; i < vliw->next_slot; ++i)
+    {
+      if (vliw->major[i] < FR550_MAJOR_M_1 || vliw->major[i] > FR550_MAJOR_M_5)
+       continue;
+
+      /* Found a media insn, however, MNOP and MCLRACC don't count.  */
+      if (CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_MNOP
+         || CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_MCLRACC_0
+         || CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_MCLRACC_1)
+       continue;
+
+      return TRUE; /* Found one.  */
+    }
+
+  return FALSE;
+}
+
+static bfd_boolean
+fr550_find_float_in_vliw (FRV_VLIW *vliw)
+{
+  int i;
+
+  for (i = 0; i < vliw->next_slot; ++i)
+    {
+      if (vliw->major[i] < FR550_MAJOR_F_1 || vliw->major[i] > FR550_MAJOR_F_4)
+       continue;
+
+      /* Found a floating point insn, however, FNOP doesn't count.  */
+      if (CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_FNOP)
+       continue;
+
+      return TRUE; /* Found one.  */
+    }
+
+  return FALSE;
+}
+
+static bfd_boolean
+fr550_check_insn_major_constraints (FRV_VLIW *vliw,
+                                   CGEN_ATTR_VALUE_ENUM_TYPE major,
+                                   const CGEN_INSN *insn)
+{
+  CGEN_ATTR_VALUE_ENUM_TYPE unit;
+  CGEN_ATTR_VALUE_ENUM_TYPE slot = (*vliw->current_vliw)[vliw->next_slot];
+  switch (slot)
+    {
+    case UNIT_I2:
+      /* If it's a store, then there must be another store in I1 */
+      unit = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_UNIT);
+      if (unit == UNIT_STORE)
+       return find_unit_in_vliw (vliw, UNIT_STORE);
+      break;
+    case UNIT_FM2:
+    case UNIT_FM3:
+      /* Floating point insns other than FNOP in slot f2 or f3 cannot coexist
+        with media insns.  */
+      if (major >= FR550_MAJOR_F_1 && major <= FR550_MAJOR_F_4
+         && CGEN_INSN_NUM (insn) != FRV_INSN_FNOP)
+       return ! fr550_find_media_in_vliw (vliw);
+      /* Media insns other than MNOP in slot m2 or m3 cannot coexist with
+        floating point insns.  */
+      if (major >= FR550_MAJOR_M_1 && major <= FR550_MAJOR_M_5
+         && CGEN_INSN_NUM (insn) != FRV_INSN_MNOP)
+       return ! fr550_find_float_in_vliw (vliw);
+      /* F-2 in slot f2 or f3 cannot coexist with F-2 or F-4 in slot f1 or f2
+        respectively.  */
+      if (major == FR550_MAJOR_F_2)
+       return ! find_major_in_slot (vliw, FR550_MAJOR_F_2,
+                                    slot - (UNIT_FM2 - UNIT_FM0))
+         &&   ! find_major_in_slot (vliw, FR550_MAJOR_F_4,
+                                    slot - (UNIT_FM2 - UNIT_FM0));
+      /* M-2 or M-5 in slot m2 or m3 cannot coexist with M-2 in slot m1 or m2
+        respectively.  */
+      if (major == FR550_MAJOR_M_2 || major == FR550_MAJOR_M_5)
+       return ! find_major_in_slot (vliw, FR550_MAJOR_M_2,
+                                    slot - (UNIT_FM2 - UNIT_FM0));
+      /* M-4 in slot m2 or m3 cannot coexist with M-4 in slot m1 or m2
+        respectively.  */
+      if (major == FR550_MAJOR_M_4)
+       return ! find_major_in_slot (vliw, FR550_MAJOR_M_4,
+                                    slot - (UNIT_FM2 - UNIT_FM0));
+      break;
+    default:
+      break;
+    }
+  return TRUE; /* All OK.  */
+}
+
+static bfd_boolean
+fr500_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major)
+{
+  /* TODO: A table might be faster for some of the more complex instances
+     here.  */
+  switch (major)
+    {
+    case FR500_MAJOR_I_1:
+    case FR500_MAJOR_I_4:
+    case FR500_MAJOR_I_5:
+    case FR500_MAJOR_I_6:
+    case FR500_MAJOR_B_1:
+    case FR500_MAJOR_B_2:
+    case FR500_MAJOR_B_3:
+    case FR500_MAJOR_B_4:
+    case FR500_MAJOR_B_5:
+    case FR500_MAJOR_B_6:
+    case FR500_MAJOR_F_4:
+    case FR500_MAJOR_F_8:
+    case FR500_MAJOR_M_8:
+      return TRUE; /* OK */
+    case FR500_MAJOR_I_2:
+      /* Cannot coexist with I-3 insn.  */
+      return ! find_major_in_vliw (vliw, FR500_MAJOR_I_3);
+    case FR500_MAJOR_I_3:
+      /* Cannot coexist with I-2 insn.  */
+      return ! find_major_in_vliw (vliw, FR500_MAJOR_I_2);
+    case FR500_MAJOR_F_1:
+    case FR500_MAJOR_F_2:
+      /* Cannot coexist with F-5, F-6, or M-7 insn.  */
+      return ! find_major_in_vliw (vliw, FR500_MAJOR_F_5)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_6)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_7);
+    case FR500_MAJOR_F_3:
+      /* Cannot coexist with F-7, or M-7 insn.  */
+      return ! find_major_in_vliw (vliw, FR500_MAJOR_F_7)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_7);
+    case FR500_MAJOR_F_5:
+      /* Cannot coexist with F-1, F-2, F-6, F-7, or M-7 insn.  */
+      return ! find_major_in_vliw (vliw, FR500_MAJOR_F_1)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_2)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_6)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_7)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_7);
+    case FR500_MAJOR_F_6:
+      /* Cannot coexist with F-1, F-2, F-5, F-6, or M-7 insn.  */
+      return ! find_major_in_vliw (vliw, FR500_MAJOR_F_1)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_2)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_5)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_6)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_7);
+    case FR500_MAJOR_F_7:
+      /* Cannot coexist with F-3, F-5, F-7, or M-7 insn.  */
+      return ! find_major_in_vliw (vliw, FR500_MAJOR_F_3)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_5)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_7)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_7);
+    case FR500_MAJOR_M_1:
+      /* Cannot coexist with M-7 insn.  */
+      return ! find_major_in_vliw (vliw, FR500_MAJOR_M_7);
+    case FR500_MAJOR_M_2:
+    case FR500_MAJOR_M_3:
+      /* Cannot coexist with M-5, M-6 or M-7 insn.  */
+      return ! find_major_in_vliw (vliw, FR500_MAJOR_M_5)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_6)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_7);
+    case FR500_MAJOR_M_4:
+      /* Cannot coexist with M-6 insn.  */
+      return ! find_major_in_vliw (vliw, FR500_MAJOR_M_6);
+    case FR500_MAJOR_M_5:
+      /* Cannot coexist with M-2, M-3, M-5, M-6  or M-7 insn.  */
+      return ! find_major_in_vliw (vliw, FR500_MAJOR_M_2)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_3)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_5)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_6)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_7);
+    case FR500_MAJOR_M_6:
+      /* Cannot coexist with M-2, M-3, M-4, M-5, M-6  or M-7 insn.  */
+      return ! find_major_in_vliw (vliw, FR500_MAJOR_M_2)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_3)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_4)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_5)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_6)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_7);
+    case FR500_MAJOR_M_7:
+      /* Cannot coexist with M-1, M-2, M-3, M-5, M-6  or M-7 insn.  */
+      return ! find_major_in_vliw (vliw, FR500_MAJOR_M_1)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_2)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_3)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_5)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_6)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_7)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_1)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_2)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_3)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_5)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_6)
+       &&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_7);
+    default:
+      fprintf (stderr, "frv-opc.c, line %d: bad major code, aborting.\n",
+              __LINE__);
+      abort ();
+      break;
+    }
+  return TRUE;
+}
+
+static bfd_boolean
+check_insn_major_constraints (FRV_VLIW *vliw,
+                             CGEN_ATTR_VALUE_ENUM_TYPE major,
+                             const CGEN_INSN *insn)
+{
+  switch (vliw->mach)
+    {
+    case bfd_mach_fr400:
+      return fr400_check_insn_major_constraints (vliw, major);
+
+    case bfd_mach_fr450:
+      return fr450_check_insn_major_constraints (vliw, major);
+
+    case bfd_mach_fr550:
+      return fr550_check_insn_major_constraints (vliw, major, insn);
+
+    default:
+      return fr500_check_insn_major_constraints (vliw, major);
+    }
+}
+
+/* Add in insn to the VLIW vliw if possible.
+   Return 0 if successful, non-zero otherwise.  */
+
+int
+frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn)
+{
+  int index;
+  CGEN_ATTR_VALUE_ENUM_TYPE major;
+  CGEN_ATTR_VALUE_ENUM_TYPE unit;
+  VLIW_COMBO *new_vliw;
+
+  if (vliw->constraint_violation || CGEN_INSN_INVALID_P (insn))
+    return 1;
+
+  index = vliw->next_slot;
+  if (index >= FRV_VLIW_SIZE)
+    return 1;
+
+  unit = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_UNIT);
+  if (unit == UNIT_NIL)
+    {
+      fprintf (stderr, "frv-opc.c line %d: bad insn unit.\n",
+              __LINE__);
+      abort (); /* No UNIT specified for this insn in frv.cpu.  */
+    }
+
+  switch (vliw->mach)
+    {
+    case bfd_mach_fr400:
+      major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR);
+      break;
+    case bfd_mach_fr450:
+      major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR);
+      break;
+    case bfd_mach_fr550:
+      major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR550_MAJOR);
+      break;
+    default:
+      major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR);
+      break;
+    }
+
+  if (index <= 0)
+    {
+      /* Any insn can be added to slot 0.  */
+      while (! match_unit (vliw, unit, (*vliw->current_vliw)[0]))
+       ++vliw->current_vliw;
+      vliw->major[0] = major;
+      vliw->insn[0] = insn;
+      vliw->next_slot = 1;
+      return 0;
+    }
+
+  /* If there are already insns in the vliw(s) check to see that
+     this one can be added.  Do this by finding an allowable vliw
+     combination that can accept the new insn.  */
+  if (! (vliw->elf_flags & EF_FRV_NOPACK))
+    {
+      new_vliw = add_next_to_vliw (vliw, unit);
+      if (new_vliw && check_insn_major_constraints (vliw, major, insn))
+       {
+         vliw->current_vliw = new_vliw;
+         vliw->major[index] = major;
+         vliw->insn[index] = insn;
+         vliw->next_slot++;
+         return 0;
+       }
+
+      /* The frv machine supports all packing conbinations.  If we fail,
+        to add the insn, then it could not be handled as if it was the fr500.
+        Just return as if it was handled ok.  */
+      if (vliw->mach == bfd_mach_frv)
+       return 0;
+    }
+
+  vliw->constraint_violation = 1;
+  return 1;
+}
+
+bfd_boolean
+spr_valid (long regno)
+{
+  if (regno < 0)     return FALSE;
+  if (regno <= 4095) return TRUE;
+  return FALSE;
+}
+/* -- */
+\f
+/* -- asm.c */
+inline static const char *
+parse_symbolic_address (CGEN_CPU_DESC cd,
+                       const char **strp,
+                       int opindex,
+                       int opinfo,
+                       enum cgen_parse_operand_result *resultp,
+                       bfd_vma *valuep)
+{
+  enum cgen_parse_operand_result result_type;
+  const char *errmsg = (* cd->parse_operand_fn)
+    (cd, CGEN_PARSE_OPERAND_SYMBOLIC, strp, opindex, opinfo,
+     &result_type, valuep);
+
+  if (errmsg == NULL
+      && result_type != CGEN_PARSE_OPERAND_RESULT_QUEUED)
+    return "symbolic expression required";
+
+  if (resultp)
+    *resultp = result_type;
+
+  return errmsg;
+}
+
+static const char *
+parse_ldd_annotation (CGEN_CPU_DESC cd,
+                     const char **strp,
+                     int opindex,
+                     unsigned long *valuep)
+{
+  const char *errmsg;
+  enum cgen_parse_operand_result result_type;
+  bfd_vma value;
+
+  if (**strp == '#' || **strp == '%')
+    {
+      if (strncasecmp (*strp + 1, "tlsdesc(", 8) == 0)
+       {
+         *strp += 9;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_TLSDESC_RELAX,
+                                          &result_type, &value);
+         if (**strp != ')')
+           return "missing ')'";
+         if (valuep)
+           *valuep = value;
+         ++*strp;
+         if (errmsg)
+           return errmsg;
+       }
+    }
+  
+  while (**strp == ' ' || **strp == '\t')
+    ++*strp;
+  
+  if (**strp != '@')
+    return "missing `@'";
+
+  ++*strp;
+
+  return NULL;
+}
+
+static const char *
+parse_call_annotation (CGEN_CPU_DESC cd,
+                      const char **strp,
+                      int opindex,
+                      unsigned long *valuep)
+{
+  const char *errmsg;
+  enum cgen_parse_operand_result result_type;
+  bfd_vma value;
+
+  if (**strp == '#' || **strp == '%')
+    {
+      if (strncasecmp (*strp + 1, "gettlsoff(", 10) == 0)
+       {
+         *strp += 11;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_GETTLSOFF_RELAX,
+                                          &result_type, &value);
+         if (**strp != ')')
+           return "missing ')'";
+         if (valuep)
+           *valuep = value;
+         ++*strp;
+         if (errmsg)
+           return errmsg;
+       }
+    }
+  
+  while (**strp == ' ' || **strp == '\t')
+    ++*strp;
+  
+  if (**strp != '@')
+    return "missing `@'";
+
+  ++*strp;
+
+  return NULL;
+}
+
+static const char *
+parse_ld_annotation (CGEN_CPU_DESC cd,
+                    const char **strp,
+                    int opindex,
+                    unsigned long *valuep)
+{
+  const char *errmsg;
+  enum cgen_parse_operand_result result_type;
+  bfd_vma value;
+
+  if (**strp == '#' || **strp == '%')
+    {
+      if (strncasecmp (*strp + 1, "tlsoff(", 7) == 0)
+       {
+         *strp += 8;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_TLSOFF_RELAX,
+                                          &result_type, &value);
+         if (**strp != ')')
+           return "missing ')'";
+         if (valuep)
+           *valuep = value;
+         ++*strp;
+         if (errmsg)
+           return errmsg;
+       }
+    }
+  
+  while (**strp == ' ' || **strp == '\t')
+    ++*strp;
+  
+  if (**strp != '@')
+    return "missing `@'";
+
+  ++*strp;
+
+  return NULL;
+}
+
+static const char *
+parse_ulo16 (CGEN_CPU_DESC cd,
+            const char **strp,
+            int opindex,
+            unsigned long *valuep)
+{
+  const char *errmsg;
+  enum cgen_parse_operand_result result_type;
+  bfd_vma value;
+ 
+  if (**strp == '#' || **strp == '%')
+    {
+      if (strncasecmp (*strp + 1, "lo(", 3) == 0)
+       {
+         *strp += 4;
+         errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_LO16,
+                                      & result_type, & value);
+         if (**strp != ')')
+           return "missing `)'";
+         ++*strp;
+         if (errmsg == NULL
+             && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+           value &= 0xffff;
+         *valuep = value;
+         return errmsg;
+       }
+      if (strncasecmp (*strp + 1, "gprello(", 8) == 0)
+       {
+         *strp += 9;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_GPRELLO,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "gotlo(", 6) == 0)
+       {
+         *strp += 7;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_GOTLO,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "gotfuncdesclo(", 14) == 0)
+       {
+         *strp += 15;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_FUNCDESC_GOTLO,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "gotofflo(", 9) == 0)
+       {
+         *strp += 10;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_GOTOFFLO,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "gotofffuncdesclo(", 17) == 0)
+       {
+         *strp += 18;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_FUNCDESC_GOTOFFLO,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "gottlsdesclo(", 13) == 0)
+       {
+         *strp += 14;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_GOTTLSDESCLO,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "tlsmofflo(", 10) == 0)
+       {
+         *strp += 11;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_TLSMOFFLO,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "gottlsofflo(", 12) == 0)
+       {
+         *strp += 13;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_GOTTLSOFFLO,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+    }
+  return cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
+}
+
+static const char *
+parse_uslo16 (CGEN_CPU_DESC cd,
+             const char **strp,
+             int opindex,
+             signed long *valuep)
+{
+  const char *errmsg;
+  enum cgen_parse_operand_result result_type;
+  bfd_vma value;
+ 
+  if (**strp == '#' || **strp == '%')
+    {
+      if (strncasecmp (*strp + 1, "lo(", 3) == 0)
+       {
+         *strp += 4;
+         errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_LO16,
+                                      & result_type, & value);
+         if (**strp != ')')
+           return "missing `)'";
+         ++*strp;
+         if (errmsg == NULL
+             && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+           value &= 0xffff;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "gprello(", 8) == 0)
+       {
+         *strp += 9;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_GPRELLO,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "gotlo(", 6) == 0)
+       {
+         *strp += 7;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_GOTLO,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "gotfuncdesclo(", 14) == 0)
+       {
+         *strp += 15;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_FUNCDESC_GOTLO,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "gotofflo(", 9) == 0)
+       {
+         *strp += 10;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_GOTOFFLO,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "gotofffuncdesclo(", 17) == 0)
+       {
+         *strp += 18;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_FUNCDESC_GOTOFFLO,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "gottlsdesclo(", 13) == 0)
+       {
+         *strp += 14;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_GOTTLSDESCLO,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "tlsmofflo(", 10) == 0)
+       {
+         *strp += 11;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_TLSMOFFLO,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "gottlsofflo(", 12) == 0)
+       {
+         *strp += 13;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_GOTTLSOFFLO,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+    }
+  return cgen_parse_signed_integer (cd, strp, opindex, valuep);
+}
+
+static const char *
+parse_uhi16 (CGEN_CPU_DESC cd,
+            const char **strp,
+            int opindex,
+            unsigned long *valuep)
+{
+  const char *errmsg;
+  enum cgen_parse_operand_result result_type;
+  bfd_vma value;
+ 
+  if (**strp == '#' || **strp == '%')
+    {
+      if (strncasecmp (*strp + 1, "hi(", 3) == 0)
+       {
+         *strp += 4;
+         errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_HI16,
+                                      & result_type, & value);
+         if (**strp != ')')
+           return "missing `)'";
+         ++*strp;
+         if (errmsg == NULL
+             && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+           {
+             /* If bfd_vma is wider than 32 bits, but we have a sign-
+                or zero-extension, truncate it.  */
+             if (value >= - ((bfd_vma)1 << 31)
+                 || value <= ((bfd_vma)1 << 31) - (bfd_vma)1)
+               value &= (((bfd_vma)1 << 16) << 16) - 1;
+             value >>= 16;
+           }
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "gprelhi(", 8) == 0)
+       {
+         *strp += 9;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_GPRELHI,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "gothi(", 6) == 0)
+       {
+         *strp += 7;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_GOTHI,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "gotfuncdeschi(", 14) == 0)
+       {
+         *strp += 15;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_FUNCDESC_GOTHI,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "gotoffhi(", 9) == 0)
+       {
+         *strp += 10;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_GOTOFFHI,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "gotofffuncdeschi(", 17) == 0)
+       {
+         *strp += 18;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_FUNCDESC_GOTOFFHI,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "gottlsdeschi(", 13) == 0)
+       {
+         *strp += 14;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_GOTTLSDESCHI,
+                                          &result_type, &value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "tlsmoffhi(", 10) == 0)
+       {
+         *strp += 11;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_TLSMOFFHI,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "gottlsoffhi(", 12) == 0)
+       {
+         *strp += 13;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_GOTTLSOFFHI,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+    }
+  return cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
+}
+
+static long
+parse_register_number (const char **strp)
+{
+  int regno;
+
+  if (**strp < '0' || **strp > '9')
+    return -1; /* error */
+
+  regno = **strp - '0';
+  for (++*strp; **strp >= '0' && **strp <= '9'; ++*strp)
+    regno = regno * 10 + (**strp - '0');
+
+  return regno;
+}
+
+static const char *
+parse_spr (CGEN_CPU_DESC cd,
+          const char **strp,
+          CGEN_KEYWORD * table,
+          long *valuep)
+{
+  const char *save_strp;
+  long regno;
+
+  /* Check for spr index notation.  */
+  if (strncasecmp (*strp, "spr[", 4) == 0)
+    {
+      *strp += 4;
+      regno = parse_register_number (strp);
+      if (**strp != ']')
+        return _("missing `]'");
+      ++*strp;
+      if (! spr_valid (regno))
+       return _("Special purpose register number is out of range");
+      *valuep = regno;
+      return NULL;
+    }
+
+  save_strp = *strp;
+  regno = parse_register_number (strp);
+  if (regno != -1)
+    {
+      if (! spr_valid (regno))
+       return _("Special purpose register number is out of range");
+      *valuep = regno;
+      return NULL;
+    }
+
+  *strp = save_strp;
+  return cgen_parse_keyword (cd, strp, table, valuep);
+}
+
+static const char *
+parse_d12 (CGEN_CPU_DESC cd,
+          const char **strp,
+          int opindex,
+          long *valuep)
+{
+  const char *errmsg;
+  enum cgen_parse_operand_result result_type;
+  bfd_vma value;
+ 
+  /* Check for small data reference.  */
+  if (**strp == '#' || **strp == '%')
+    {
+      if (strncasecmp (*strp + 1, "gprel12(", 8) == 0)
+        {
+          *strp += 9;
+          errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_GPREL12,
+                                          & result_type, & value);
+          if (**strp != ')')
+            return "missing `)'";
+          ++*strp;
+          *valuep = value;
+          return errmsg;
+        }
+      else if (strncasecmp (*strp + 1, "got12(", 6) == 0)
+       {
+         *strp += 7;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_GOT12,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "gotfuncdesc12(", 14) == 0)
+       {
+         *strp += 15;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_FUNCDESC_GOT12,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "gotoff12(", 9) == 0)
+       {
+         *strp += 10;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_GOTOFF12,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "gotofffuncdesc12(", 17) == 0)
+       {
+         *strp += 18;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_FUNCDESC_GOTOFF12,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "gottlsdesc12(", 13) == 0)
+       {
+         *strp += 14;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_GOTTLSDESC12,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "tlsmoff12(", 10) == 0)
+       {
+         *strp += 11;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_TLSMOFF12,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "gottlsoff12(", 12) == 0)
+       {
+         *strp += 13;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_GOTTLSOFF12,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+    }
+  return cgen_parse_signed_integer (cd, strp, opindex, valuep);
+}
+
+static const char *
+parse_s12 (CGEN_CPU_DESC cd,
+          const char **strp,
+          int opindex,
+          long *valuep)
+{
+  const char *errmsg;
+  enum cgen_parse_operand_result result_type;
+  bfd_vma value;
+ 
+  /* Check for small data reference.  */
+  if (**strp == '#' || **strp == '%')
+    {
+      if (strncasecmp (*strp + 1, "gprel12(", 8) == 0)
+       {
+         *strp += 9;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_GPREL12,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing `)'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "got12(", 6) == 0)
+       {
+         *strp += 7;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_GOT12,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "gotfuncdesc12(", 14) == 0)
+       {
+         *strp += 15;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_FUNCDESC_GOT12,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "gotoff12(", 9) == 0)
+       {
+         *strp += 10;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_GOTOFF12,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "gotofffuncdesc12(", 17) == 0)
+       {
+         *strp += 18;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_FUNCDESC_GOTOFF12,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "gottlsdesc12(", 13) == 0)
+       {
+         *strp += 14;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_GOTTLSDESC12,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "tlsmoff12(", 10) == 0)
+       {
+         *strp += 11;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_TLSMOFF12,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+      else if (strncasecmp (*strp + 1, "gottlsoff12(", 12) == 0)
+       {
+         *strp += 13;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_GOTTLSOFF12,
+                                          & result_type, & value);
+         if (**strp != ')')
+           return "missing ')'";
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+    }
+
+  if (**strp == '#')
+    ++*strp;
+  return cgen_parse_signed_integer (cd, strp, opindex, valuep);
+}
+
+static const char *
+parse_u12 (CGEN_CPU_DESC cd,
+          const char **strp,
+          int opindex,
+          long *valuep)
+{
+  const char *errmsg;
+  enum cgen_parse_operand_result result_type;
+  bfd_vma value;
+ 
+  /* Check for small data reference.  */
+  if ((**strp == '#' || **strp == '%')
+      && strncasecmp (*strp + 1, "gprel12(", 8) == 0)
+    {
+      *strp += 9;
+      errmsg = parse_symbolic_address (cd, strp, opindex,
+                                      BFD_RELOC_FRV_GPRELU12,
+                                      & result_type, & value);
+      if (**strp != ')')
+        return "missing `)'";
+      ++*strp;
+      *valuep = value;
+      return errmsg;
+    }
+  else
+    {
+      if (**strp == '#')
+        ++*strp;
+      return cgen_parse_signed_integer (cd, strp, opindex, valuep);
+    }
+}
+
+static const char *
+parse_A (CGEN_CPU_DESC cd,
+        const char **strp,
+        int opindex,
+        unsigned long *valuep,
+        unsigned long A)
+{
+  const char *errmsg;
+ 
+  if (**strp == '#')
+    ++*strp;
+
+  errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
+  if (errmsg)
+    return errmsg;
+
+  if (*valuep != A)
+    return _("Value of A operand must be 0 or 1");
+
+  return NULL;
+}
+
+static const char *
+parse_A0 (CGEN_CPU_DESC cd,
+         const char **strp,
+         int opindex,
+         unsigned long *valuep)
+{
+  return parse_A (cd, strp, opindex, valuep, 0);
+}
+
+static const char *
+parse_A1 (CGEN_CPU_DESC cd,
+         const char **strp,
+         int opindex,
+         unsigned long *valuep)
+{
+  return parse_A (cd, strp, opindex, valuep, 1);
+}
+
+static const char *
+parse_even_register (CGEN_CPU_DESC  cd,
+                    const char **  strP,
+                    CGEN_KEYWORD * tableP,
+                    long *         valueP)
+{
+  const char * errmsg;
+  const char * saved_star_strP = * strP;
+
+  errmsg = cgen_parse_keyword (cd, strP, tableP, valueP);
+
+  if (errmsg == NULL && ((* valueP) & 1))
+    {
+      errmsg = _("register number must be even");
+      * strP = saved_star_strP;
+    }
+
+  return errmsg;
+}
+
+static const char *
+parse_call_label (CGEN_CPU_DESC cd,
+                 const char **strp,
+                 int opindex,
+                 int opinfo,
+                 enum cgen_parse_operand_result *resultp,
+                 bfd_vma *valuep)
+{
+  const char *errmsg;
+  bfd_vma value;
+ 
+  /* Check for small data reference.  */
+  if (opinfo == 0 && (**strp == '#' || **strp == '%'))
+    {
+      if (strncasecmp (*strp + 1, "gettlsoff(", 10) == 0)
+       {
+         *strp += 11;
+         errmsg = parse_symbolic_address (cd, strp, opindex,
+                                          BFD_RELOC_FRV_GETTLSOFF,
+                                          resultp, &value);
+         if (**strp != ')')
+           return _("missing `)'");
+         ++*strp;
+         *valuep = value;
+         return errmsg;
+       }
+    }
+
+  return cgen_parse_address (cd, strp, opindex, opinfo, resultp, valuep);
+}
+
+/* -- */
+\f
+/* -- dis.c */
+static void
+print_at (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+         void * dis_info,
+         long reloc_ann ATTRIBUTE_UNUSED,
+         long value ATTRIBUTE_UNUSED,
+         bfd_vma pc ATTRIBUTE_UNUSED,
+         int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+
+  (*info->fprintf_func) (info->stream, "@");
+}  
+
+static void
+print_spr (CGEN_CPU_DESC cd,
+          void * dis_info,
+          CGEN_KEYWORD *names,
+          long regno,
+          unsigned int attrs)
+{
+  /* Use the register index format for any unnamed registers.  */
+  if (cgen_keyword_lookup_value (names, regno) == NULL)
+    {
+      disassemble_info *info = (disassemble_info *) dis_info;
+      (*info->fprintf_func) (info->stream, "spr[%ld]", regno);
+    }
+  else
+    print_keyword (cd, dis_info, names, regno, attrs);
+}
+
+static void
+print_hi (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+         void * dis_info,
+         long value,
+         unsigned int attrs ATTRIBUTE_UNUSED,
+         bfd_vma pc ATTRIBUTE_UNUSED,
+         int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+
+  (*info->fprintf_func) (info->stream, value ? "0x%lx" : "hi(0x%lx)", value);
+}
+
+static void
+print_lo (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+         void * dis_info,
+         long value,
+         unsigned int attrs ATTRIBUTE_UNUSED,
+         bfd_vma pc ATTRIBUTE_UNUSED,
+         int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+  if (value)
+    (*info->fprintf_func) (info->stream, "0x%lx", value);
+  else
+    (*info->fprintf_func) (info->stream, "lo(0x%lx)", value);
+}
+
+/* -- */

diff --git a/cpu/iq10.cpu b/cpu/iq10.cpu
new file mode 100644 (file)
index 0000000..252cf53
--- /dev/null
+++ b/cpu/iq10.cpu
@@ -0,0 +1,1112 @@
+; IQ10-only CPU description. -*- Scheme -*-
+;
+; Copyright 2001, 2002, 2007, 2009 Free Software Foundation, Inc.
+;
+; Contributed by Red Hat Inc; developed under contract from Vitesse.
+;
+; This file is part of the GNU Binutils.
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 3 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, write to the Free Software
+; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+; MA 02110-1301, USA.
+
+
+; Instructions.
+
+(dni andoui-q10 "iq10 and upper ones immediate" (MACH10 USES-RS USES-RT)
+     "andoui $rt,$rs,$hi16"
+     (+ OP10_ANDOUI rs rt hi16)
+     (set rt (and rs (or (sll hi16 16) #xFFFF)))
+     ())
+
+(dni andoui2-q10 "iq10 and upper ones immediate" (ALIAS NO-DIS MACH10 USES-RS USES-RT)
+     "andoui ${rt-rs},$hi16"
+     (+ OP10_ANDOUI rt-rs hi16)
+     (set rt-rs (and rt-rs (or (sll hi16 16) #xFFFF)))
+     ())
+
+(dni orui-q10 "or upper immediate" (MACH10 USES-RS USES-RT)
+     "orui $rt,$rs,$hi16"
+     (+ OP10_ORUI rs rt hi16)
+     (set rt (or rs (sll hi16 16)))
+     ())
+
+(dni orui2-q10 "or upper immediate" (ALIAS NO-DIS MACH10 USES-RS USES-RT)
+     "orui ${rt-rs},$hi16"
+     (+ OP10_ORUI rt-rs hi16)
+     (set rt-rs (or rt-rs (sll hi16 16)))
+     ())
+
+(dni mrgbq10 "merge bytes" (MACH10 USES-RD USES-RS USES-RT)
+     "mrgb $rd,$rs,$rt,$maskq10"
+     (+ OP_SPECIAL rs rt rd maskq10 FUNC_MRGB)
+     (sequence ((SI temp))
+              (if (bitclear? mask 0)
+                  (set temp (and rs #xFF))
+                  (set temp (and rt #xFF)))
+              (if (bitclear? mask 1)
+                  (set temp (or temp (and rs #xFF00)))
+                  (set temp (or temp (and rt #xFF00))))
+              (if (bitclear? mask 2)
+                  (set temp (or temp (and rs #xFF0000)))
+                  (set temp (or temp (and rt #xFF0000))))
+              (if (bitclear? mask 3)
+                  (set temp (or temp (and rs #xFF000000)))
+                  (set temp (or temp (and rt #xFF000000))))
+              (set rd temp))
+     ())
+
+(dni mrgbq102 "merge bytes" (ALIAS NO-DIS MACH10 USES-RD USES-RS USES-RT)
+     "mrgb ${rd-rs},$rt,$maskq10"
+     (+ OP_SPECIAL rt rd-rs maskq10 FUNC_MRGB)
+     (sequence ((SI temp))
+              (if (bitclear? mask 0)
+                  (set temp (and rd-rs #xFF))
+                  (set temp (and rt #xFF)))
+              (if (bitclear? mask 1)
+                  (set temp (or temp (and rd-rs #xFF00)))
+                  (set temp (or temp (and rt #xFF00))))
+              (if (bitclear? mask 2)
+                  (set temp (or temp (and rd-rs #xFF0000)))
+                  (set temp (or temp (and rt #xFF0000))))
+              (if (bitclear? mask 3)
+                  (set temp (or temp (and rd-rs #xFF000000)))
+                  (set temp (or temp (and rt #xFF000000))))
+              (set rd-rs temp))
+     ())
+
+; In the future, we'll want the j & jal to use the 21 bit target, with 
+; the upper five bits shifted up.  For now, give 'em the 16 bit target.
+
+(dni jq10 "jump" (MACH10)
+     "j $jmptarg"
+     (+ OP_J (f-rs 0) (f-rt 0) jmptarg)
+;     "j $jmptargq10"
+;     (+ OP_J upper-5-jmptargq10 (f-rt 0) lower-16-jmptargq10)
+     (delay 1 (set pc jmptarg))
+     ())
+
+(dni jalq10 "jump and link" (MACH10 USES-RT)
+     "jal $rt,$jmptarg"
+     (+ OP_JAL (f-rs 0) rt jmptarg)
+;     "jal $rt,$jmptargq10"
+;     (+ OP_JAL upper-5-jmptargq10 rt lower-16-jmptargq10)
+     (delay 1
+           (sequence ()
+                     (set rt (add pc 8))
+                     (set pc jmptarg)))
+     ())
+
+(dni jalq10-2 "jump and link, implied r31" (MACH10 USES-RT)
+     "jal $jmptarg"
+     (+ OP_JAL (f-rs 0) (f-rt 31) jmptarg)
+     (delay 1
+           (sequence ()
+                     (set rt (add pc 8))
+                     (set pc jmptarg)))
+     ())
+\f
+; Branch instructions.
+
+(dni bbil "branch bit immediate likely" (MACH10 USES-RS)
+     "bbil $rs($bitnum),$offset"
+     (+ OP10_BBIL rs bitnum offset)
+     (if (bitset? rs bitnum)
+        (delay 1 (set pc offset))
+        (skip 1))
+     ())
+
+(dni bbinl "branch bit immediate negated likely" (MACH10 USES-RS)
+     "bbinl $rs($bitnum),$offset"
+     (+ OP10_BBINL rs bitnum offset)
+     (if (bitclear? rs bitnum)
+        (delay 1 (set pc offset))
+        (skip 1))
+     ())
+
+(dni bbvl "branch bit variable likely" (MACH10 USES-RS USES-RT)
+     "bbvl $rs,$rt,$offset"
+     (+ OP10_BBVL rs rt offset)
+     (if (bitset? rs (and rt #x1F))
+        (delay 1 (set pc offset))
+        (skip 1))
+     ())
+
+(dni bbvnl "branch bit variable negated likely" (MACH10 USES-RS USES-RT)
+     "bbvnl $rs,$rt,$offset"
+     (+ OP10_BBVNL rs rt offset)
+     (if (bitclear? rs (and rt #x1F))
+        (delay 1 (set pc offset))
+        (skip 1))
+     ())
+
+(dni bgtzal "branch if greater than zero and link" (MACH10 USES-RS USES-R31)
+     "bgtzal $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BGTZAL offset)
+     (if (gt rs 0)
+        (sequence ()
+                  (set (reg h-gr 31) (add pc 8))
+                  (delay 1 (set pc offset))))
+     ())
+
+(dni bgtzall
+     "branch if greater than zero and link likely" (MACH10 USES-RS USES-R31)
+     "bgtzall $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BGTZALL offset)
+     (if (gt rs 0)
+        (sequence ()
+                  (set (reg h-gr 31) (add pc 8))
+                  (delay 1 (set pc offset)))
+        (skip 1))
+     ())
+
+(dni blezal "branch if less than or equal to zero and link" (MACH10 USES-RS USES-R31)
+     "blezal $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BLEZAL offset)
+     (if (le rs 0)
+        (sequence ()
+                  (set (reg h-gr 31) (add pc 8))
+                  (delay 1 (set pc offset))))
+     ())
+
+(dni blezall
+     "branch if less than or equal to zero and link likely" (MACH10 USES-RS USES-R31)
+     "blezall $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BLEZALL offset)
+     (if (le rs 0)
+        (sequence ()
+                  (set (reg h-gr 31) (add pc 8))
+                  (delay 1 (set pc offset)))
+        (skip 1))
+     ())
+
+(dni bgtz-q10 "branch if greater than zero" (MACH10 USES-RS)
+     "bgtz $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BGTZ offset)
+     (if (gt rs 0)
+        (delay 1 (set pc offset)))
+     ())
+
+(dni bgtzl-q10 "branch if greater than zero likely" (MACH10 USES-RS)
+     "bgtzl $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BGTZL offset)
+     (if (gt rs 0)
+        (delay 1 (set pc offset))
+        (skip 1))
+     ())
+
+
+(dni blez-q10 "branch if less than or equal to zero" (MACH10 USES-RS)
+     "blez $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BLEZ offset)
+     (if (le rs 0)
+        (delay 1 (set pc offset)))
+     ())
+
+(dni blezl-q10 "branch if less than or equal to zero likely" (MACH10 USES-RS)
+     "blezl $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BLEZL offset)
+     (if (le rs 0)
+        (delay 1 (set pc offset))
+        (skip 1))
+     ())
+
+(dni bmb-q10 "branch if matching byte-lane" (MACH10 USES-RS USES-RT)
+     "bmb $rs,$rt,$offset"
+     (+ OP10_BMB rs rt offset)
+     (sequence ((BI branch?))
+              (set branch? 0)
+              (if (eq (and rs #xFF) (and rt #xFF))
+                  (set branch? 1))
+              (if (eq (and rs #xFF00) (and rt #xFF00))
+                  (set branch? 1))
+              (if (eq (and rs #xFF0000) (and rt #xFF0000))
+                  (set branch? 1))
+              (if (eq (and rs #xFF000000) (and rt #xFF000000))
+                  (set branch? 1))
+              (if branch?
+                  (delay 1 (set pc offset))))
+     ())
+
+(dni bmbl "branch if matching byte-lane likely" (MACH10 USES-RS USES-RT)
+     "bmbl $rs,$rt,$offset"
+     (+ OP10_BMBL rs rt offset)
+     (sequence ((BI branch?))
+              (set branch? 0)
+              (if (eq (and rs #xFF) (and rt #xFF))
+                  (set branch? 1))
+              (if (eq (and rs #xFF00) (and rt #xFF00))
+                  (set branch? 1))
+              (if (eq (and rs #xFF0000) (and rt #xFF0000))
+                  (set branch? 1))
+              (if (eq (and rs #xFF000000) (and rt #xFF000000))
+                  (set branch? 1))
+              (if branch?
+                  (delay 1 (set pc offset))
+                  (skip 1)))
+     ())
+
+(dni bri "branch if register invalid" (MACH10 USES-RS)
+     "bri $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BRI offset)
+     (if (gt rs 0)
+        (delay 1 (set pc offset))
+        (skip 1))
+     ())
+
+(dni brv "branch if register invalid" (MACH10 USES-RS)
+     "brv $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BRV offset)
+     (if (gt rs 0)
+        (delay 1 (set pc offset))
+        (skip 1))
+     ())
+
+; debug instructions
+
+(dni bctx "branch if the current context == instruction[21]" (MACH10 USES-RS)
+     "bctx $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BCTX offset)
+     (delay 1 (set pc offset))
+     ())
+
+(dni yield "unconditional yield to the other context" (MACH10)
+     "yield"
+     (+ OP_SPECIAL (f-rs 0) (f-rt 0) (f-rd 0) (f-shamt 0) FUNC10_YIELD)
+     (unimp yield)
+     ())
+
+; Special instructions.
+
+(dni crc32 "CRC, 32 bit input" (MACH10 USES-RD USES-RS USES-RT)
+     "crc32 $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_CRC32)
+     (unimp crc32)
+     ())
+
+(dni crc32b "CRC, 8 bit input" (MACH10 USES-RD USES-RS USES-RT)
+     "crc32b $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_CRC32B)
+     (unimp crc32b)
+     ())
+
+(dni cnt1s "Count ones" (MACH10 USES-RD USES-RS)
+     "cnt1s $rd,$rs"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC10_CNT1S)
+     (unimp crcp)
+     ())
+
+\f
+; Special Instructions
+
+(dni avail "Mark Header Buffer Available" (MACH10 USES-RD)
+     "avail $rd"
+     (+ OP_COP3 (f-rs 0) (f-rt 0) rd (f-shamt 0) FUNC10_AVAIL)
+     (unimp avail)
+     ())
+
+(dni free "Mark Header Buffer Free" (MACH10 USES-RS USES-RD)
+     "free $rd,$rs"
+     (+ OP_COP3 rs (f-rt 0) rd (f-shamt 0) FUNC10_FREE)
+     (unimp free)
+     ())
+
+(dni tstod "Test Header Buffer Order Dependency" (MACH10 USES-RS USES-RD)
+     "tstod $rd,$rs"
+     (+ OP_COP3 rs (f-rt 0) rd (f-shamt 0) FUNC10_TSTOD)
+     (unimp tstod)
+     ())
+
+(dni cmphdr "Get a Complete Header" (MACH10 USES-RD)
+     "cmphdr $rd"
+     (+ OP_COP3 (f-rs 0) (f-rt 0) rd (f-shamt 0) FUNC10_CMPHDR)
+     (unimp cmphdr)
+     ())
+
+(dni mcid "Allocate a Multicast ID" (MACH10 USES-RD USES-RT)
+     "mcid $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_MCID)
+     (unimp mcid)
+     ())
+
+(dni dba "Allocate a Data Buffer Pointer" (MACH10 USES-RD)
+     "dba $rd"
+     (+ OP_COP3 (f-rs 0) (f-rt 0) rd (f-shamt 0) FUNC10_DBA)
+     (unimp dba)
+     ())
+
+(dni dbd "Deallocate a Data Buffer Pointer" (MACH10 USES-RS USES-RT USES-RD)
+     "dbd $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_DBD)
+     (unimp dbd)
+     ())
+
+(dni dpwt "DSTN_PORT Write" (MACH10 USES-RS USES-RD)
+     "dpwt $rd,$rs"
+     (+ OP_COP3 rs (f-rt 0) rd (f-shamt 0) FUNC10_DPWT)
+     (unimp dpwt)
+     ())
+
+; Architectural and coprocessor instructions.
+
+(dni chkhdrq10 "" (MACH10 USES-RS USES-RD)
+     "chkhdr $rd,$rs"
+     (+ OP_COP3 rs (f-rt 0) rd (f-shamt 0) FUNC10_CHKHDR)
+     (unimp chkhdr)
+     ())
+
+; Coprocessor DMA Instructions (IQ10)
+
+(dni rba "Read Bytes Absolute" (MACH10 USES-RS USES-RT USES-RD)
+     "rba $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_RBA)
+     (unimp rba)
+     ())
+
+(dni rbal "Read Bytes Absolute and Lock" (MACH10 USES-RS USES-RT USES-RD)
+     "rbal $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_RBAL)
+     (unimp rbal)
+     ())
+
+(dni rbar "Read Bytes Absolute and Release" (MACH10 USES-RS USES-RT USES-RD)
+     "rbar $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_RBAR)
+     (unimp rbar)
+     ())
+
+(dni wba "Write Bytes Absolute" (MACH10 USES-RS USES-RT USES-RD)
+     "wba $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_WBA)
+     (unimp wba)
+     ())
+
+(dni wbau "Write Bytes Absolute and Unlock" (MACH10 USES-RS USES-RT USES-RD)
+     "wbau $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_WBAU)
+     (unimp wbau)
+     ())
+
+(dni wbac "Write Bytes Absolute Cacheable" (MACH10 USES-RS USES-RT USES-RD)
+     "wbac $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_WBAC)
+     (unimp wbac)
+     ())
+
+(dni rbi "Read Bytes Immediate" (MACH10 USES-RD USES-RS USES-RT)
+     "rbi $rd,$rs,$rt,$bytecount"
+     (+ OP_COP3 rs rt rd FUNC10_RBI bytecount)
+     (unimp rbi)
+     ())
+
+(dni rbil "Read Bytes Immediate and Lock" (MACH10 USES-RD USES-RS USES-RT)
+     "rbil $rd,$rs,$rt,$bytecount"
+     (+ OP_COP3 rs rt rd FUNC10_RBIL bytecount)
+     (unimp rbil)
+     ())
+
+(dni rbir "Read Bytes Immediate and Release" (MACH10 USES-RD USES-RS USES-RT)
+     "rbir $rd,$rs,$rt,$bytecount"
+     (+ OP_COP3 rs rt rd FUNC10_RBIR bytecount)
+     (unimp rbir)
+     ())
+
+(dni wbi "Write Bytes Immediate" (MACH10 USES-RD USES-RS USES-RT)
+     "wbi $rd,$rs,$rt,$bytecount"
+     (+ OP_COP3 rs rt rd FUNC10_WBI bytecount)
+     (unimp wbi)
+     ())
+
+(dni wbic "Write Bytes Immediate Cacheable" (MACH10 USES-RD USES-RS USES-RT)
+     "wbic $rd,$rs,$rt,$bytecount"
+     (+ OP_COP3 rs rt rd FUNC10_WBIC bytecount)
+     (unimp wbic)
+     ())
+
+(dni wbiu "Write Bytes Immediate" (MACH10 USES-RD USES-RS USES-RT)
+     "wbiu $rd,$rs,$rt,$bytecount"
+     (+ OP_COP3 rs rt rd FUNC10_WBIU bytecount)
+     (unimp wbiu)
+     ())
+
+(dni pkrli "Packet Release Immediate" (MACH10 USES-RD USES-RS USES-RT)
+     "pkrli $rd,$rs,$rt,$bytecount"
+     (+ OP_COP2 rs rt rd FUNC10_PKRLI bytecount)
+     (unimp pkrli)
+     ())
+
+(dni pkrlih "Packet Release Immediate and Hold" (MACH10 USES-RD USES-RS USES-RT)
+     "pkrlih $rd,$rs,$rt,$bytecount"
+     (+ OP_COP2 rs rt rd FUNC10_PKRLIH bytecount)
+     (unimp pkrlih)
+     ())
+
+(dni pkrliu "Packet Release Immediate Unconditional" (MACH10 USES-RD USES-RS USES-RT)
+     "pkrliu $rd,$rs,$rt,$bytecount"
+     (+ OP_COP2 rs rt rd FUNC10_PKRLIU bytecount)
+     (unimp pkrliu)
+     ())
+
+(dni pkrlic "Packet Release Immediate Continue" (MACH10 USES-RD USES-RS USES-RT)
+     "pkrlic $rd,$rs,$rt,$bytecount"
+     (+ OP_COP2 rs rt rd FUNC10_PKRLIC bytecount)
+     (unimp pkrlic)
+     ())
+
+(dni pkrla "Packet Release Absolute" (MACH10 USES-RS USES-RT USES-RD)
+     "pkrla $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_PKRLA)
+     (unimp pkrla)
+     ())
+
+(dni pkrlau "Packet Release Absolute Unconditional" (MACH10 USES-RS USES-RT USES-RD)
+     "pkrlau $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_PKRLAU)
+     (unimp pkrlau)
+     ())
+
+(dni pkrlah "Packet Release Absolute and Hold" (MACH10 USES-RS USES-RT USES-RD)
+     "pkrlah $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_PKRLAH)
+     (unimp pkrlah)
+     ())
+
+(dni pkrlac "Packet Release Absolute Continue" (MACH10 USES-RS USES-RT USES-RD)
+     "pkrlac $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_PKRLAC)
+     (unimp pkrlac)
+     ())
+
+; Main Memory Access Instructions
+
+(dni lock "lock memory" (MACH10 USES-RD USES-RT)
+     "lock $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_LOCK)
+     (unimp lock)
+     ())
+
+(dni unlk "unlock memory" (MACH10 USES-RT USES-RD)
+     "unlk $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_UNLK)
+     (unimp unlk)
+     ())
+     
+(dni swrd "Single Word Read" (MACH10 USES-RT USES-RD)
+     "swrd $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_SWRD)
+     (unimp swrd)
+     ())
+
+(dni swrdl "Single Word Read and Lock" (MACH10 USES-RT USES-RD)
+     "swrdl $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_SWRDL)
+     (unimp swrdl)
+     ())
+
+(dni swwr "Single Word Write" (MACH10 USES-RS USES-RT USES-RD)
+     "swwr $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_SWWR)
+     (unimp swwr)
+     ())
+
+(dni swwru "Single Word Write and Unlock" (MACH10 USES-RS USES-RT USES-RD)
+     "swwru $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_SWWRU)
+     (unimp swwru)
+     ())
+
+(dni dwrd "Double Word Read" (MACH10 EVEN-REG-NUM USES-RT USES-RD)
+     "dwrd $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_DWRD)
+     (unimp dwrd)
+     ())
+
+(dni dwrdl "Double Word Read and Lock" (MACH10 EVEN-REG-NUM USES-RT USES-RD)
+     "dwrdl $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_DWRDL)
+     (unimp dwrdl)
+     ())
+
+; CAM access instructions (IQ10)
+
+(dni cam36 "CAM Access in 36-bit Mode" (MACH10 USES-RT USES-RD)
+     "cam36 $rd,$rt,${cam-z},${cam-y}"
+     (+ OP_COP3 (f-rs 0) rt rd FUNC10_CAM36 cam-z cam-y)
+     (unimp cam36)
+     ())
+
+(dni cam72 "CAM Access in 72-bit Mode" (MACH10 USES-RT USES-RD)
+     "cam72 $rd,$rt,${cam-y},${cam-z}"
+     (+ OP_COP3 (f-rs 0) rt rd FUNC10_CAM72 cam-z cam-y)
+     (unimp cam72)
+     ())
+
+(dni cam144 "CAM Access in 144-bit Mode" (MACH10 USES-RT USES-RD)
+     "cam144 $rd,$rt,${cam-y},${cam-z}"
+     (+ OP_COP3 (f-rs 0) rt rd FUNC10_CAM144 cam-z cam-y)
+     (unimp cam144)
+     ())
+
+(dni cam288 "CAM Access in 288-bit Mode" (MACH10 USES-RT USES-RD)
+     "cam288 $rd,$rt,${cam-y},${cam-z}"
+     (+ OP_COP3 (f-rs 0) rt rd FUNC10_CAM288 cam-z cam-y)
+     (unimp cam288)
+     ())
+
+; Counter manager instructions (IQ10)
+
+(dni cm32and "Counter Manager And" (MACH10 USES-RS USES-RT USES-RD)
+     "cm32and $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32AND)
+     (unimp cm32and)
+     ())
+
+(dni cm32andn "Counter Manager And With Inverse" (MACH10 USES-RS USES-RT USES-RD)
+     "cm32andn $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32ANDN)
+     (unimp cm32andn)
+     ())
+
+(dni cm32or "Counter Manager Or" (MACH10 USES-RS USES-RT USES-RD)
+     "cm32or $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32OR)
+     (unimp cm32or)
+     ())
+
+(dni cm32ra "Counter Manager 32-bit Rolling Add" (MACH10 USES-RS USES-RT USES-RD)
+     "cm32ra $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 2) FUNC10_CM32RA)
+     (unimp cm32ra)
+     ())
+
+(dni cm32rd "Counter Manager 32-bit Rolling Decrement" (MACH10 USES-RT USES-RD)
+     "cm32rd $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32RD)
+     (unimp cm32rd)
+     ())
+
+(dni cm32ri "Counter Manager 32-bit Rolling Increment" (MACH10 USES-RT USES-RD)
+     "cm32ri $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32RI)
+     (unimp cm32ri)
+     ())
+
+(dni cm32rs "Counter Manager 32-bit Rolling Subtract" (MACH10 USES-RS USES-RT USES-RD)
+     "cm32rs $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 2) FUNC10_CM32RS)
+     (unimp cm32rs)
+     ())
+
+(dni cm32sa "Counter Manager 32-bit Saturating Add" (MACH10 USES-RS USES-RT USES-RD)
+     "cm32sa $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32SA)
+     (unimp cm32sa)
+     ())
+
+(dni cm32sd "Counter Manager 32-bit Saturating Decrement" (MACH10 USES-RT USES-RD)
+     "cm32sd $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32SD)
+     (unimp cm32sd)
+     ())
+
+(dni cm32si "Counter Manager 32-bit Saturating Increment" (MACH10 USES-RT USES-RD)
+     "cm32si $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32SI)
+     (unimp cm32si)
+     ())
+
+(dni cm32ss "Counter Manager 32-bit Saturating Subtract" (MACH10 USES-RS USES-RT USES-RD)
+     "cm32ss $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32SS)
+     (unimp cm32ss)
+     ())
+
+(dni cm32xor "Counter Manager Xor" (MACH10 USES-RS USES-RT USES-RD)
+     "cm32xor $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32XOR)
+     (unimp cm32xor)
+     ())
+
+(dni cm64clr "Counter Manager Clear" (MACH10 EVEN-REG-NUM USES-RT USES-RD)
+     "cm64clr $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64CLR)
+     (unimp cm64clr)
+     ())
+
+(dni cm64ra "Counter Manager 64-bit Rolling Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD)
+     "cm64ra $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64RA)
+     (unimp cm64ra)
+     ())
+
+(dni cm64rd "Counter Manager 64-bit Rolling Decrement" (MACH10 EVEN-REG-NUM USES-RT USES-RD)
+     "cm64rd $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64RD)
+     (unimp cm64rd)
+     ())
+
+(dni cm64ri "Counter Manager 32-bit Rolling Increment" (MACH10 EVEN-REG-NUM USES-RT USES-RD)
+     "cm64ri $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64RI)
+     (unimp cm64ri)
+     ())
+
+(dni cm64ria2 "Counter Manager 32/32 Rolling Increment/Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD)
+     "cm64ria2 $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64RIA2)
+     (unimp cm64ria2)
+     ())
+
+(dni cm64rs "Counter Manager 64-bit Rolling Subtract" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD)
+     "cm64rs $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64RS)
+     (unimp cm64rs)
+     ())
+
+(dni cm64sa "Counter Manager 64-bit Saturating Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD)
+     "cm64sa $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64SA)
+     (unimp cm64sa)
+     ())
+
+(dni cm64sd "Counter Manager 64-bit Saturating Decrement" (MACH10 EVEN-REG-NUM USES-RT USES-RD)
+     "cm64sd $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64SD)
+     (unimp cm64sd)
+     ())
+
+(dni cm64si "Counter Manager 64-bit Saturating Increment" (MACH10 EVEN-REG-NUM USES-RT USES-RD)
+     "cm64si $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64SI)
+     (unimp cm64si)
+     ())
+
+(dni cm64sia2 "Counter Manager 32/32 Saturating Increment/Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD)
+     "cm64sia2 $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64SIA2)
+     (unimp cm64sia2)
+     ())
+
+(dni cm64ss "Counter Manager 64-bit Saturating Subtract" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD)
+     "cm64ss $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64SS)
+     (unimp cm64ss)
+     ())
+
+(dni cm128ria2 "Counter Manager 128-bit 64/64 Rolling Increment/Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD)
+     "cm128ria2 $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128RIA2)
+     (unimp cm128ria2)
+     ())
+
+(dni cm128ria3 "Counter Manager 128-bit 32/32/64 Rolling Increment/Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD)
+     "cm128ria3 $rd,$rs,$rt,${cm-3z}"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128RIA3 cm-3z)
+     (unimp cm128ria3)
+     ())
+
+(dni cm128ria4 "Counter Manager 128-bit 32/32/32/32 Rolling Inc/Add" (MACH10 USES-RS USES-RT USES-RD)
+     "cm128ria4 $rd,$rs,$rt,${cm-4z}"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128RIA4 cm-4z)
+     (unimp cm128ria4)
+     ())
+
+(dni cm128sia2 "Counter Manager 128-bit 64/64 Saturating Inc/Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD)
+     "cm128sia2 $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128SIA2)
+     (unimp cm128sia2)
+     ())
+
+(dni cm128sia3 "Counter Manager 128-bit 32/32/64 Saturating Inc/Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD)
+     "cm128sia3 $rd,$rs,$rt,${cm-3z}"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128SIA3 cm-3z)
+     (unimp cm128sia3)
+     ())
+
+(dni cm128sia4 "Counter Manager 128-bit 32/32/32/32 Saturating Inc/Add" (MACH10 USES-RS USES-RT USES-RD)
+     "cm128sia4 $rd,$rs,$rt,${cm-4z}"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128SIA4 cm-4z)
+     (unimp cm128sia4)
+     ())
+
+(dni cm128vsa "Counter Manager Continuous State Dual Leaky Token Bucket Policing" (MACH10 USES-RS USES-RT USES-RD)
+     "cm128vsa $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128VSA)
+     (unimp cm128vsa)
+     ())
+
+; Coprocessor Data Movement Instructions
+
+; Note that we don't set the USES-RD or USES-RT attributes for many of the following 
+; instructions, as it's the COP register that's being specified.
+
+; ??? Is YIELD-INSN the right attribute for IQ10?  The IQ2000 used the attribute to warn about 
+; yielding instructions in a delay slot, but that's not relevant in IQ10.  What *is* relevant 
+; (and unique to IQ10) is instructions that yield if the destination register is accessed 
+; before the value is there, causing a yield.
+
+(dni cfc "copy from coprocessor control register" (MACH10 LOAD-DELAY USES-RD YIELD-INSN)
+     "cfc $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_CFC)
+     (unimp cfc)
+     ())
+
+(dni ctc "copy to coprocessor control register" (MACH10 USES-RS)
+     "ctc $rs,$rt"
+     (+ OP_COP3 rs rt (f-rd 0) (f-shamt 0) FUNC10_CTC)
+     (unimp ctc)
+     ())
+
+; Macros
+
+(dnmi m-avail "Mark Header Buffer Available" (MACH10 NO-DIS)
+     "avail"
+     (emit avail (f-rd 0))
+)
+
+(dnmi m-cam36 "CAM Access in 36-bit Mode" (MACH10 USES-RT USES-RD NO-DIS)
+     "cam36 $rd,$rt,${cam-z}"
+     (emit cam36 rd rt cam-z (f-cam-y 0))
+)
+
+(dnmi m-cam72 "CAM Access in 72-bit Mode" (MACH10 USES-RT USES-RD NO-DIS)
+     "cam72 $rd,$rt,${cam-z}"
+     (emit cam72 rd rt cam-z (f-cam-y 0))
+)
+
+(dnmi m-cam144 "CAM Access in 144-bit Mode" (MACH10 USES-RT USES-RD NO-DIS)
+     "cam144 $rd,$rt,${cam-z}"
+     (emit cam144 rd rt cam-z (f-cam-y 0))
+)
+
+(dnmi m-cam288 "CAM Access in 288-bit Mode" (MACH10 USES-RT USES-RD NO-DIS)
+     "cam288 $rd,$rt,${cam-z}"
+     (emit cam288 rd rt cam-z (f-cam-y 0))
+)
+
+(dnmi m-cm32read "Counter Manager 32-bit Rolling Add R0" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm32read $rd,$rt"
+     (emit cm32ra rd (f-rs 0) rt)
+)
+
+(dnmi m-cm64read "Counter Manager 64-bit Rolling Add R0" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm64read $rd,$rt"
+     (emit cm64ra rd (f-rs 0) rt)
+)
+
+(dnmi m-cm32mlog "Counter Manager 32-bit or R0" (MACH10 USES-RS USES-RT NO-DIS)
+     "cm32mlog $rs,$rt"
+     (emit cm32or (f-rd 0) rs rt)
+)
+
+(dnmi m-cm32and "Counter Manager And" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm32and $rs,$rt"
+     (emit cm32and (f-rd 0) rs rt)
+)
+
+(dnmi m-cm32andn "Counter Manager And With Inverse" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm32andn $rs,$rt"
+     (emit cm32andn (f-rd 0) rs rt)
+)
+
+(dnmi m-cm32or "Counter Manager Or" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm32or $rs,$rt"
+     (emit cm32or (f-rd 0) rs rt)
+)
+
+(dnmi m-cm32ra "Counter Manager 32-bit Rolling Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm32ra $rs,$rt"
+     (emit cm32ra (f-rd 0) rs rt)
+)
+
+(dnmi m-cm32rd "Counter Manager 32-bit Rolling Decrement" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm32rd $rt"
+     (emit cm32rd (f-rd 0) rt)
+)
+
+(dnmi m-cm32ri "Counter Manager 32-bit Rolling Increment" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm32ri $rt"
+     (emit cm32ri (f-rd 0) rt)
+)
+
+(dnmi m-cm32rs "Counter Manager 32-bit Rolling Subtract" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm32rs $rs,$rt"
+     (emit cm32rs (f-rd 0) rs rt)
+)
+
+(dnmi m-cm32sa "Counter Manager 32-bit Saturating Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm32sa $rs,$rt"
+     (emit cm32sa (f-rd 0) rs rt)
+)
+
+(dnmi m-cm32sd "Counter Manager 32-bit Saturating Decrement" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm32sd $rt"
+     (emit cm32sd (f-rd 0) rt)
+)
+
+(dnmi m-cm32si "Counter Manager 32-bit Saturating Increment" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm32si $rt"
+     (emit cm32si (f-rd 0) rt)
+)
+
+(dnmi m-cm32ss "Counter Manager 32-bit Saturating Subtract" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm32ss $rs,$rt"
+     (emit cm32ss (f-rd 0) rs rt)
+)
+
+(dnmi m-cm32xor "Counter Manager Xor" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm32xor $rs,$rt"
+     (emit cm32xor (f-rd 0) rs rt)
+)
+
+(dnmi m-cm64clr "Counter Manager Clear" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm64clr $rt"
+     (emit cm64clr (f-rd 0) rt)
+)
+
+(dnmi m-cm64ra "Counter Manager 64-bit Rolling Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm64ra $rs,$rt"
+     (emit cm64ra (f-rd 0) rs rt)
+)
+
+(dnmi m-cm64rd "Counter Manager 64-bit Rolling Decrement" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm64rd $rt"
+     (emit cm64rd (f-rd 0) rt)
+)
+
+(dnmi m-cm64ri "Counter Manager 32-bit Rolling Increment" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm64ri $rt"
+     (emit cm64ri (f-rd 0) rt)
+)
+
+(dnmi m-cm64ria2 "Counter Manager 32/32 Rolling Increment/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm64ria2 $rs,$rt"
+     (emit cm64ria2 (f-rd 0) rs rt)
+)
+
+(dnmi m-cm64rs "Counter Manager 64-bit Rolling Subtract" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm64rs $rs,$rt"
+     (emit cm64rs (f-rd 0) rs rt)
+)
+
+(dnmi m-cm64sa "Counter Manager 64-bit Saturating Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm64sa $rs,$rt"
+     (emit cm64sa (f-rd 0) rs rt)
+)
+
+(dnmi m-cm64sd "Counter Manager 64-bit Saturating Decrement" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm64sd $rt"
+     (emit cm64sd (f-rd 0) rt)
+)
+
+(dnmi m-cm64si "Counter Manager 64-bit Saturating Increment" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm64si $rt"
+     (emit cm64si (f-rd 0) rt)
+)
+
+(dnmi m-cm64sia2 "Counter Manager 32/32 Saturating Increment/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm64sia2 $rs,$rt"
+     (emit cm64sia2 (f-rd 0) rs rt)
+)
+
+(dnmi m-cm64ss "Counter Manager 64-bit Saturating Subtract" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm64ss $rs,$rt"
+     (emit cm64ss (f-rd 0) rs rt)
+)
+
+(dnmi m-cm128ria2 "Counter Manager 128-bit 64/64 Rolling Increment/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm128ria2 $rs,$rt"
+     (emit cm128ria2 (f-rd 0) rs rt)
+)
+
+(dnmi m-cm128ria3 "Counter Manager 128-bit 32/32/64 Rolling Increment/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm128ria3 $rs,$rt,${cm-3z}"
+     (emit cm128ria3 (f-rd 0) rs rt cm-3z)
+)
+
+(dnmi m-cm128ria4 "Counter Manager 128-bit 32/32/32/32 Rolling Inc/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm128ria4 $rs,$rt,${cm-4z}"
+     (emit cm128ria4 (f-rd 0) rs rt cm-4z)
+)
+
+(dnmi m-cm128sia2 "Counter Manager 128-bit 64/64 Saturating Inc/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm128sia2 $rs,$rt"
+     (emit cm128sia2 (f-rd 0) rs rt)
+)
+
+(dnmi m-cm128sia3 "Counter Manager 128-bit 32/32/64 Saturating Inc/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm128sia3 $rs,$rt,${cm-3z}"
+     (emit cm128sia3 (f-rd 0) rs rt cm-3z)
+)
+
+(dnmi m-cm128sia4 "Counter Manager 128-bit 32/32/32/32 Saturating Inc/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm128sia4 $rs,$rt,${cm-4z}"
+     (emit cm128sia4 (f-rd 0) rs rt cm-4z)
+)
+
+(dnmi m-cmphdr "Get a Complete Header" (MACH10 NO-DIS)
+     "cmphdr"
+     (emit cmphdr (f-rd 0))
+)
+
+(dnmi m-dbd "Deallocate a Data Buffer Pointer" (MACH10 USES-RD USES-RT NO-DIS)
+     "dbd $rd,$rt"
+     (emit dbd rd (f-rs 0) rt)
+)
+
+(dnmi m2-dbd "Deallocate a Data Buffer Pointer" (MACH10 USES-RT NO-DIS)
+     "dbd $rt"
+     (emit dbd (f-rd 0) (f-rs 0) rt)
+)
+
+(dnmi m-dpwt "DSTN_PORT Write" (MACH10 USES-RS NO-DIS)
+     "dpwt $rs"
+     (emit dpwt (f-rd 0) rs)
+)
+
+(dnmi m-free "" (MACH10 USES-RS USES-RD NO-DIS)
+     "free $rs"
+     (emit free (f-rd 0) rs)
+)
+
+;(dnmi m-jal "jump and link, implied r31" (MACH10 USES-RT NO-DIS)
+;     "jal $jmptarg"
+;     (emit jal (f-rt 31) jmptarg)
+;)
+
+(dnmi m-lock "lock memory" (MACH10 USES-RT NO-DIS)
+     "lock $rt"
+     (emit lock (f-rd 0) rt)
+)
+
+(dnmi m-pkrla "Packet Release Absolute" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "pkrla $rs,$rt"
+     (emit pkrla (f-rd 0) rs rt)
+)
+
+(dnmi m-pkrlac "Packet Release Absolute Continue" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "pkrlac $rs,$rt"
+     (emit pkrlac (f-rd 0) rs rt)
+)
+
+(dnmi m-pkrlah "Packet Release Absolute and Hold" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "pkrlah $rs,$rt"
+     (emit pkrlah (f-rd 0) rs rt)
+)
+
+(dnmi m-pkrlau "Packet Release Absolute Unconditional" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "pkrlau $rs,$rt"
+     (emit pkrlau (f-rd 0) rs rt)
+)
+
+(dnmi m-pkrli "Packet Release Immediate" (MACH10 USES-RD USES-RS USES-RT NO-DIS)
+     "pkrli $rs,$rt,$bytecount"
+     (emit pkrli (f-rd 0) rs rt bytecount)
+)
+
+(dnmi m-pkrlic "Packet Release Immediate Continue" (MACH10 USES-RS USES-RT NO-DIS)
+     "pkrlic $rs,$rt,$bytecount"
+     (emit pkrlic (f-rd 0) rs rt bytecount)
+)
+
+(dnmi m-pkrlih "Packet Release Immediate and Hold" (MACH10 USES-RD USES-RS USES-RT NO-DIS)
+     "pkrlih $rs,$rt,$bytecount"
+     (emit pkrlih (f-rd 0) rs rt bytecount)
+)
+
+(dnmi m-pkrliu "Packet Release Immediate Unconditional" (MACH10 USES-RD USES-RS USES-RT NO-DIS)
+     "pkrliu $rs,$rt,$bytecount"
+     (emit pkrliu (f-rd 0) rs rt bytecount)
+)
+
+(dnmi m-rba "Read Bytes Absolute" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "rba $rs,$rt"
+     (emit rba (f-rd 0) rs rt)
+)
+
+(dnmi m-rbal "Read Bytes Absolute and Lock" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "rbal $rs,$rt"
+     (emit rbal (f-rd 0) rs rt)
+)
+
+(dnmi m-rbar "Read Bytes Absolute and Release" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "rbar $rs,$rt"
+     (emit rbar (f-rd 0) rs rt)
+)
+
+(dnmi m-rbi "Read Bytes Immediate" (MACH10 USES-RS USES-RT NO-DIS)
+     "rbi $rs,$rt,$bytecount"
+     (emit rbi (f-rd 0) rs rt bytecount)
+)
+
+(dnmi m-rbil "Read Bytes Immediate and Lock" (MACH10 USES-RS USES-RT NO-DIS)
+     "rbil $rs,$rt,$bytecount"
+     (emit rbil (f-rd 0) rs rt bytecount)
+)
+
+(dnmi m-rbir "Read Bytes Immediate and Release" (MACH10 USES-RS USES-RT NO-DIS)
+     "rbir $rs,$rt,$bytecount"
+     (emit rbir (f-rd 0) rs rt bytecount)
+)
+
+(dnmi m-swwr "Single Word Write" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "swwr $rs,$rt"
+     (emit swwr (f-rd 0) rs rt)
+)
+
+(dnmi m-swwru "Single Word Write and Unlock" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "swwru $rs,$rt"
+     (emit swwru (f-rd 0) rs rt)
+)
+
+(dnmi m-tstod "Test Header Buffer Order Dependency" (MACH10 USES-RS USES-RD NO-DIS)
+     "tstod $rs"
+     (emit tstod (f-rd 0) rs)
+)
+
+(dnmi m-unlk "" (MACH10 USES-RT USES-RD NO-DIS)
+     "unlk $rt"
+     (emit unlk (f-rd 0) rt)
+)
+     
+(dnmi m-wba "Write Bytes Absolute" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "wba $rs,$rt"
+     (emit wba (f-rd 0) rs rt)
+)
+
+(dnmi m-wbac "Write Bytes Absolute Cacheable" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "wbac $rs,$rt"
+     (emit wbac (f-rd 0) rs rt)
+)
+
+(dnmi m-wbau "Write Bytes Absolute and Unlock" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "wbau $rs,$rt"
+     (emit wbau (f-rd 0) rs rt)
+)
+
+(dnmi m-wbi "Write Bytes Immediate" (MACH10 USES-RD USES-RS USES-RT NO-DIS)
+     "wbi $rs,$rt,$bytecount"
+     (emit wbi (f-rd 0) rs rt bytecount)
+)
+
+(dnmi m-wbic "Write Bytes Immediate Cacheable" (MACH10 USES-RD USES-RS USES-RT NO-DIS)
+     "wbic $rs,$rt,$bytecount"
+     (emit wbic (f-rd 0) rs rt bytecount)
+)
+
+(dnmi m-wbiu "Write Bytes Immediate" (MACH10 USES-RD USES-RS USES-RT NO-DIS)
+     "wbiu $rs,$rt,$bytecount"
+     (emit wbiu (f-rd 0) rs rt bytecount)
+)
+\f

diff --git a/cpu/iq2000.cpu b/cpu/iq2000.cpu
new file mode 100644 (file)
index 0000000..e25ba69
--- /dev/null
+++ b/cpu/iq2000.cpu
@@ -0,0 +1,1196 @@
+; IQ2000/IQ10 Common CPU description. -*- Scheme -*-
+; Copyright 2001, 2002, 2007, 2009 Free Software Foundation, Inc.
+;
+; Contributed by Red Hat Inc; developed under contract from Fujitsu.
+;
+; This file is part of the GNU Binutils.
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 3 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, write to the Free Software
+; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+; MA 02110-1301, USA.
+
+(include "simplify.inc")
+
+(define-arch
+  (name iq2000)
+  (comment "IQ2000 architecture")
+  (insn-lsb0? #t)
+  (machs iq2000 iq10)
+  (isas iq2000)
+)
+
+(define-isa
+  (name iq2000)
+  (comment "Basic IQ2000 instruction set")
+  (default-insn-word-bitsize 32)
+  (default-insn-bitsize 32)
+  (base-insn-bitsize 32)
+  (decode-assist (31 30 29 28 27 26))
+)
+
+(define-cpu
+  (name iq2000bf)
+  (comment "IQ2000 family")
+  (endian big)
+  (word-bitsize 32)
+  (file-transform "")
+)
+
+(define-cpu
+  (name iq10bf)
+  (comment "IQ10 coprocessor family")
+  (endian big)
+  (word-bitsize 32)
+  (file-transform "")
+
+)
+
+(define-mach
+  (name iq2000)
+  (comment "IQ2000 packet processing engine")
+  (cpu iq2000bf)
+  (isas iq2000)
+)
+
+(define-mach
+  (name iq10)
+  (comment "IQ10 coprocessor")
+  (cpu iq10bf)
+  (isas iq2000)
+)
+
+(define-model
+  (name iq2000)
+  (comment "IQ2000 microprocessor")
+  (mach iq2000)
+  (unit u-exec "Execution Unit" ()
+       1 1 ; issue done
+       () () () ())
+)
+
+(define-model
+  (name iq10)
+  (comment "IQ10 coprocessor")
+  (mach iq10)
+  (unit u-exec "Execution Unit" ()
+       1 1 ; issue done
+       () () () ())
+)
+
+; Macros to simplify MACH attribute specification.
+
+(define-pmacro MACH2000 (MACH iq2000))
+(define-pmacro MACH10 (MACH iq10))
+
+\f
+; Hardware elements.
+
+(define-hardware
+  (name h-pc)
+  (comment "program counter")
+  (attrs PC PROFILE (ISA iq2000))
+  (type pc)
+  (get () (c-call USI "get_h_pc"))
+  (set (newval) (c-call VOID "set_h_pc" newval))
+)
+; FIXME: it would be nice if the hardwired zero in R0 could be
+; specified as a virtual hardware element, with one less register in
+; the register file proper.
+
+(define-keyword
+  (name gr-names)
+  (print-name h-gr)
+  (values (r0 0)   (%0 0)   (r1 1)   (%1 1)   (r2 2)   (%2 2)   (r3 3)   (%3 3)  
+          (r4 4)   (%4 4)   (r5 5)   (%5 5)   (r6 6)   (%6 6)   (r7 7)   (%7 7)
+          (r8 8)   (%8 8)   (r9 9)   (%9 9)   (r10 10) (%10 10) (r11 11) (%11 11)
+          (r12 12) (%12 12) (r13 13) (%13 13) (r14 14) (%14 14) (r15 15) (%15 15) 
+          (r16 16) (%16 16) (r17 17) (%17 17) (r18 18) (%18 18) (r19 19) (%19 19) 
+          (r20 20) (%20 20) (r21 21) (%21 21) (r22 22) (%22 22) (r23 23) (%23 23)
+          (r24 24) (%24 24) (r25 25) (%25 25) (r26 26) (%26 26) (r27 27) (%27 27) 
+          (r28 28) (%28 28) (r29 29) (%29 29) (r30 30) (%30 30) (r31 31) (%31 31))
+)
+
+(define-hardware 
+  (name h-gr)
+  (comment "General purpose registers")
+;  (attrs (ISA iq2000) CACHE-ADDR)
+  (type register SI (32))
+  (indices extern-keyword gr-names)
+  (get (idx)
+       (cond SI
+            ((eq idx 0) (const 0))
+            (else (raw-reg h-gr idx))))
+  (set (idx newval)
+       (cond VOID
+            ((eq idx 0) (nop))
+            (else (set (raw-reg h-gr idx) newval))))
+)
+
+\f
+; Instruction fields.
+
+(dnf f-opcode   "opcode field"                  ()  31  6)
+(dnf f-rs       "register field Rs"             ()  25  5)
+(dnf f-rt       "register field Rt"             ()  20  5)
+(dnf f-rd       "register field Rd"             ()  15  5)
+(dnf f-shamt    "shift amount field"            ()  10  5)
+(dnf f-cp-op    "coprocessor op field"         ()  10  3)
+(dnf f-cp-op-10 "coprocessor op field for CAM"  ()  10  5)
+(dnf f-cp-grp   "coprocessor group field"      ()   7  2)
+(dnf f-func     "function field"                ()   5  6)
+(dnf f-imm      "immediate field"               ()  15 16)
+
+(define-multi-ifield
+  (name f-rd-rs)
+  (comment "register Rd implied from Rs")
+  (attrs)
+  (mode UINT)
+  (subfields f-rd f-rs)
+  (insert (sequence ()
+                   (set (ifield f-rd) (ifield f-rd-rs))
+                   (set (ifield f-rs) (ifield f-rd-rs))
+                    ))
+  (extract (sequence ()
+                     (set (ifield f-rd-rs) (ifield f-rs))
+                     ))
+)
+
+(define-multi-ifield
+  (name f-rd-rt)
+  (comment "register Rd implied from Rt")
+  (attrs)
+  (mode UINT)
+  (subfields f-rd f-rt)
+  (insert (sequence ()
+                   (set (ifield f-rd) (ifield f-rd-rt))
+                   (set (ifield f-rt) (ifield f-rd-rt))
+                    ))
+  (extract (sequence ()
+                     (set (ifield f-rd-rt) (ifield f-rt))
+                     ))
+)
+
+(define-multi-ifield
+  (name f-rt-rs)
+  (comment "register Rt implied from Rs")
+  (attrs)
+  (mode UINT)
+  (subfields f-rt f-rs)
+  (insert (sequence ()
+                   (set (ifield f-rt) (ifield f-rt-rs))
+                   (set (ifield f-rs) (ifield f-rt-rs))
+                    ))
+  (extract (sequence ()
+                     (set (ifield f-rd-rs) (ifield f-rs))
+                     ))
+)
+
+(df  f-jtarg "jump target field"               (ABS-ADDR) 15 16 UINT
+     ((value pc) (srl USI (and USI value #x03FFFF) 2))
+     ((value pc) (or USI (and USI pc #xF0000000) (sll USI value 2))))
+
+(df  f-jtargq10 "iq10 jump target field"       (ABS-ADDR) 20 21 UINT
+     ((value pc) (srl SI (and SI value #x7FFFFF) 2))
+     ((value pc) (or SI (and SI pc #xF0000000) (sll SI value 2))))
+
+(df  f-offset "pc offset field"                (PCREL-ADDR) 15 16 INT
+     ; Actually, this is relative to the address of the delay slot.
+     ((value pc) (sra SI (sub SI value pc) 2))
+     ((value pc) (add SI (sll SI value 2) (add pc 4))))
+
+; Instruction fields that scarcely appear in instructions.
+
+(dnf f-count   "count field"        ()   15  7)
+(dnf f-bytecount "byte count field" ()    7  8)
+(dnf f-index   "index field"        ()    8  9)
+(dnf f-mask    "mask field"         ()    9  4)
+(dnf f-maskq10 "iq10 mask field"    ()   10  5)
+(dnf f-maskl   "mask left field"    ()    4  5)
+(dnf f-excode  "execcode field"     ()   25 20)
+(dnf f-rsrvd   "reserved field"     ()   25 10)
+(dnf f-10-11   "bits 10:0"          ()   10 11)
+(dnf f-24-19   "bits 24:6"          ()   24 19)
+(dnf f-5       "bit 5"              ()    5  1)
+(dnf f-10      "bit 10"             ()   10  1)
+(dnf f-25      "bit 25"             ()   25  1)
+(dnf f-cam-z   "cam global mask z"  ()    5  3)
+(dnf f-cam-y   "cam operation y"    ()    2  3)
+(dnf f-cm-3func "CM 3 bit fn field" ()    5  3)
+(dnf f-cm-4func "CM 4 bit fn field" ()    5  4)
+(dnf f-cm-3z   "CM 3Z field"        ()    1  2)
+(dnf f-cm-4z   "CM 4Z field"        ()    2  3)
+
+\f
+; Enumerations.
+
+(define-normal-insn-enum
+  opcodes "primary opcodes" () OP_ f-opcode
+  (("SPECIAL" 0) ("REGIMM" 1) ("J"     2) ("JAL"    3) ("BEQ"    4) ("BNE"   5) ("BLEZ"   6) ("BGTZ"    7) 
+   ("ADDI"    8) ("ADDIU"  9) ("SLTI" 10) ("SLTIU" 11) ("ANDI"  12) ("ORI"  13) ("XORI"  14) ("LUI"    15)
+   ("COP0"   16) ("COP1"  17) ("COP2" 18) ("COP3"  19) ("BEQL"  20) ("BNEL" 21) ("BLEZL" 22) ("BGTZL"  23) 
+   ("BMB0"   24) ("BMB1"  25) ("BMB2" 26) ("BMB3"  27) ("BBI"   28) ("BBV"  29) ("BBIN"  30) ("BBVN"   31) 
+   ("LB"     32) ("LH"    33)             ("LW"    35) ("LBU"   36) ("LHU"  37)              ("RAM"    39)  
+   ("SB"     40) ("SH"    41)             ("SW"    43) ("ANDOI" 44) ("BMB"  45)              ("ORUI"   47) 
+   ("LDW"    48) 
+   ("SDW"    56)                                                                             ("ANDOUI" 63))
+)
+
+(define-normal-insn-enum
+  q10_opcodes "iq10-only primary opcodes" () OP10_ f-opcode
+  (("BMB" 6) ("ORUI" 15) ("BMBL" 22) ("ANDOUI" 47) ("BBIL" 60) ("BBVL" 61) ("BBINL" 62) ("BBVNL" 63))
+)
+
+(define-normal-insn-enum
+  regimm-functions "branch sub-opcodes" () FUNC_ f-rt
+  (("BLTZ"    0) ("BGEZ"    1) ("BLTZL"    2) ("BGEZL"    3) ("BLEZ"    4) ("BGTZ"    5) ("BLEZL"    6) ("BGTZL"    7) 
+   ("BRI"     8) ("BRV"     9)                               ("BCTX"   12) 
+   ("BLTZAL" 16) ("BGEZAL" 17) ("BLTZALL" 18) ("BGEZALL" 19) ("BLEZAL" 20) ("BGTZAL" 21) ("BLEZALL" 22) ("BGTZALL" 23))
+)
+
+(define-normal-insn-enum
+  functions "function sub-opcodes" () FUNC_ f-func
+  (("SLL"  0) ("SLMV"   1) ("SRL"  2) ("SRA"   3) ("SLLV"     4) ("SRMV"   5) ("SRLV"   6) ("SRAV" 7) 
+   ("JR"   8) ("JALR"   9) ("JCR" 10)             ("SYSCALL" 12) ("BREAK" 13) ("SLEEP" 14)
+   ("ADD" 32) ("ADDU"  33) ("SUB" 34) ("SUBU" 35) ("AND"     36) ("OR"    37) ("XOR"   38) ("NOR" 39) 
+              ("ADO16" 41) ("SLT" 42) ("SLTU" 43)                ("MRGB"  45))
+)
+
+; iq10 special function sub-opcodes
+(define-normal-insn-enum
+  q10s_functions "iq10-only special function sub-opcodes" () FUNC10_ f-func
+  (("YIELD" 14) ("CNT1S" 46))
+)
+
+; coprocessor opcodes in concert with f-cp-grp
+(define-normal-insn-enum
+  cop_functions "iq10 function sub-opcodes" () FUNC10_ f-func
+  (("CFC"    0) ("LOCK"    1) ("CTC"     2) ("UNLK"    3) ("SWRD"    4) ("SWRDL"   5) ("SWWR"    6) ("SWWRU"  7) 
+   ("RBA"    8) ("RBAL"    9) ("RBAR"   10)               ("DWRD"   12) ("DWRDL"  13) 
+   ("WBA"   16) ("WBAU"   17) ("WBAC"   18)               ("CRC32"  20) ("CRC32B" 21) 
+   ("MCID"  32) ("DBD"    33) ("DBA"    34) ("DPWT"   35) ("AVAIL"  36) ("FREE"   37) ("CHKHDR" 38) ("TSTOD" 39)
+   ("PKRLA" 40) ("PKRLAU" 41) ("PKRLAH" 42) ("PKRLAC" 43) ("CMPHDR" 44) 
+
+   ("CM64RS"  0) ("CM64RD"  1)                                ("CM64RI"    4) ("CM64CLR"    5)
+   ("CM64SS"  8) ("CM64SD"  9)                                ("CM64SI"   12) 
+   ("CM64RA" 16)                                              ("CM64RIA2" 20) ("CM128RIA2" 21)
+   ("CM64SA" 24)                                              ("CM64SIA2" 28) ("CM128SIA2" 29)
+   ("CM32RS" 32) ("CM32RD" 33) ("CM32XOR" 34) ("CM32ANDN" 35) ("CM32RI"   36)                  ("CM128VSA" 38)
+   ("CM32SS" 40) ("CM32SD" 41) ("CM32OR"  42) ("CM32AND"  43) ("CM32SI"   44) 
+   ("CM32RA" 48)  
+   ("CM32SA" 56) )
+)
+
+; coprocessor opcodes in concert with f-cp-grp
+(define-normal-insn-enum
+  cop_cm128_4functions "iq10 function sub-opcodes" () FUNC10_ f-cm-4func
+  (("CM128RIA3" 4) ("CM128SIA3" 6))
+)
+
+(define-normal-insn-enum
+  cop_cm128_3functions "iq10 function sub-opcodes" () FUNC10_ f-cm-3func
+  (("CM128RIA4" 6) ("CM128SIA4" 7))
+)
+
+(define-normal-insn-enum
+   cop2_functions "iq10 coprocessor sub-opcodes" () FUNC10_ f-cp-op
+   (("PKRLI" 0) ("PKRLIU" 1) ("PKRLIH" 2) ("PKRLIC" 3) ("RBIR" 1) ("RBI" 2) ("RBIL" 3) ("WBIC" 5) ("WBI" 6) ("WBIU" 7))
+)
+
+(define-normal-insn-enum
+   cop3_cam_functions "iq10 coprocessor cam sub-opcodes" () FUNC10_ f-cp-op-10
+   (("CAM36" 16) ("CAM72" 17) ("CAM144" 18) ("CAM288" 19))
+)
+
+\f
+; Attributes.
+
+(define-attr
+  (for insn)
+  (type boolean)
+  (name YIELD-INSN)
+  (comment "insn generates a context yield")
+)
+
+(define-attr
+  (for insn)
+  (type boolean)
+  (name LOAD-DELAY)
+  (comment "insn has a load delay")
+)
+
+(define-attr
+  (for insn)
+  (type boolean)
+  (name EVEN-REG-NUM)
+  (comment "insn requires an even numbered register in rt(2000) or rd(10)")
+)
+
+(define-attr
+  (for insn)
+  (type boolean)
+  (name UNSUPPORTED)
+  (comment "insn is unsupported")
+)
+
+(define-pmacro (define-reg-use-attr regfield)
+  (define-attr
+    (for insn)
+    (type boolean)
+    (name (.sym USES- (.upcase regfield)))
+    (comment ("insn accesses register operand " regfield))))
+
+(define-reg-use-attr "rd")
+(define-reg-use-attr "rs")
+(define-reg-use-attr "rt")
+(define-reg-use-attr "r31")
+
+\f
+; Operands.
+
+(dnop rs       "register Rs"             () h-gr    f-rs)
+(dnop rt       "register Rt"             () h-gr    f-rt)
+(dnop rd       "register Rd"             () h-gr    f-rd)
+(dnop rd-rs    "register Rd from Rs"     () h-gr    f-rd-rs)
+(dnop rd-rt    "register Rd from Rt"     () h-gr    f-rd-rt)
+(dnop rt-rs    "register Rt from Rs"     () h-gr    f-rt-rs)
+(dnop shamt    "shift amount"            () h-uint  f-shamt)
+(define-operand (name imm) (comment "immediate") (attrs)
+   (type h-uint) (index f-imm) (handlers (parse "imm")))
+(dnop offset   "pc-relative offset"      () h-iaddr f-offset)
+(dnop baseoff  "base register offset"    () h-iaddr f-imm)
+(dnop jmptarg  "jump target"             () h-iaddr f-jtarg)
+(dnop mask     "mask"                    () h-uint  f-mask)
+(dnop maskq10  "iq10 mask"               () h-uint  f-maskq10)
+(dnop maskl    "mask left"               () h-uint  f-maskl)
+(dnop count    "count"                   () h-uint  f-count)
+(dnop _index   "index"                   () h-uint  f-index)
+(dnop execode  "execcode"                () h-uint  f-excode)
+(dnop bytecount "byte count"             () h-uint  f-bytecount)
+(dnop cam-y     "cam global opn y"       () h-uint  f-cam-y)
+(dnop cam-z     "cam global mask z"      () h-uint  f-cam-z)
+(dnop cm-3func  "CM 3 bit fn field"      () h-uint  f-cm-3func)
+(dnop cm-4func  "CM 4 bit fn field"      () h-uint  f-cm-4func)
+(dnop cm-3z     "CM 3 bit Z field"       () h-uint  f-cm-3z)
+(dnop cm-4z     "CM 4 bit Z field"       () h-uint  f-cm-4z)
+
+; Aliases for the rs and rt operands. This just makes the load/store
+; insns easier to compare with the instruction set documentation.
+
+(dnop base    "base register"                  () h-gr   f-rs)
+(dnop maskr   "mask right"                     () h-uint f-rs)
+(dnop bitnum  "bit number"                     () h-uint f-rt)
+
+; For high(foo).
+(define-operand
+  (name hi16)
+  (comment "high 16 bit immediate")
+  (attrs)
+  (type h-uint)
+  (index f-imm)
+  (handlers (parse "hi16"))
+)
+
+; For low(foo).
+(define-operand
+  (name lo16)
+  (comment "16 bit signed immediate, for low")
+  (attrs)
+  (type h-uint)
+  (index f-imm)
+  (handlers (parse "lo16"))
+)
+
+; For negated imm.
+(define-operand
+  (name mlo16)
+  (comment "negated 16 bit signed immediate")
+  (attrs)
+  (type h-uint)
+  (index f-imm)
+  (handlers (parse "mlo16"))
+)
+
+; For iq10 jmps
+; In the future, we'll want the j & jal to use the 21 bit target, with 
+; the upper five bits shifted up.  For now, don't use this.
+(define-operand
+  (name jmptargq10)
+  (comment "iq10 21-bit jump offset")
+  (attrs)
+  (type h-iaddr)
+  (index f-jtargq10)
+  (handlers (parse "jtargq10"))
+)
+
+\f
+; Instructions.
+
+; A pmacro for use in semantic bodies of unimplemented insns.
+(define-pmacro (unimp mnemonic) (nop))
+
+(define-pmacro (bitset? value bit-num)
+  (and value (sll 1 bit-num)))
+
+(define-pmacro (bitclear? value bit-num)
+  (not (bitset? value bit-num)))
+
+; Arithmetic/logic instructions.
+
+(dni add2 "add registers" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "add ${rd-rs},$rt"
+     (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_ADD)
+     (set rd-rs (add rt rd-rs))
+     ())
+
+(dni add "add registers" (USES-RD USES-RS USES-RT)
+     "add $rd,$rs,$rt"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_ADD)
+     (set rd (add rs rt))
+     ())
+
+
+(dni addi2 "add immediate" (ALIAS NO-DIS USES-RS USES-RT)
+     "addi ${rt-rs},$lo16"
+     (+ OP_ADDI rt-rs lo16)
+     (set rt-rs (add rt-rs (ext SI (trunc HI lo16))))
+     ())
+
+(dni addi "add immediate" (USES-RS USES-RT)
+     "addi $rt,$rs,$lo16"
+     (+ OP_ADDI rs rt lo16)
+     (set rt (add rs (ext SI (trunc HI lo16))))
+     ())
+
+(dni addiu2 "add immediate unsigned" (ALIAS NO-DIS USES-RS USES-RT)
+     "addiu ${rt-rs},$lo16"
+     (+ OP_ADDIU rt-rs lo16)
+     (set rt-rs (add rt-rs (ext SI (trunc HI lo16))))
+     ())
+
+(dni addiu "add immediate unsigned" (USES-RS USES-RT)
+     "addiu $rt,$rs,$lo16"
+     (+ OP_ADDIU rs rt lo16)
+     (set rt (add rs (ext SI (trunc HI lo16))))
+     ())
+
+(dni addu2 "add unsigned" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "addu ${rd-rs},$rt"
+     (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_ADDU)
+     (set rd-rs (add rd-rs rt))
+     ())
+
+(dni addu "add unsigned" (USES-RD USES-RS USES-RT)
+     "addu $rd,$rs,$rt"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_ADDU)
+     (set rd (add rs rt))
+     ())
+
+(dni ado162 "add 16, ones complement" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "ado16 ${rd-rs},$rt"
+     (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_ADO16)
+     (sequence ((HI high) (HI low))
+              (set low (add HI (and HI rd-rs #xFFFF) (and HI rt #xFFFF)))
+              (set high (add HI (srl rd-rs 16) (srl rt 16)))
+              (set rd-rs (or SI (sll SI high 16) low)))
+     ())
+
+(dni ado16 "add 16, ones complement" (USES-RD USES-RS USES-RT)
+     "ado16 $rd,$rs,$rt"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_ADO16)
+     (sequence ((HI high) (HI low))
+              (set low (add HI (and HI rs #xFFFF) (and HI rt #xFFFF)))
+              (set high (add HI (srl rs 16) (srl rt 16)))
+              (set rd (or SI (sll SI high 16) low)))
+     ())
+
+(dni and2 "and register" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "and ${rd-rs},$rt"
+     (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_AND)
+     (set rd-rs (and rd-rs rt))
+     ())
+
+(dni and "and register" (USES-RD USES-RS USES-RT)
+     "and $rd,$rs,$rt"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_AND)
+     (set rd (and rs rt))
+     ())
+
+(dni andi2 "and immediate" (ALIAS NO-DIS USES-RS USES-RT)
+     "andi ${rt-rs},$lo16"
+     (+ OP_ANDI rt-rs lo16)
+     (set rt-rs (and rt-rs (zext SI lo16)))
+     ())
+
+(dni andi "and immediate" (USES-RS USES-RT)
+     "andi $rt,$rs,$lo16"
+     (+ OP_ANDI rs rt lo16)
+     (set rt (and rs (zext SI lo16)))
+     ())
+
+(dni andoi2 "and ones immediate" (ALIAS NO-DIS USES-RS USES-RT)
+     "andoi ${rt-rs},$lo16"
+     (+ OP_ANDOI rt-rs lo16)
+     (set rt-rs (and rt-rs (or #xFFFF0000 (ext SI (trunc HI lo16)))))
+     ())
+
+(dni andoi "and ones immediate" (USES-RS USES-RT)
+     "andoi $rt,$rs,$lo16"
+     (+ OP_ANDOI rs rt lo16)
+     (set rt (and rs (or #xFFFF0000 (ext SI (trunc HI lo16)))))
+     ())
+
+(dni nor2 "nor" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "nor ${rd-rs},$rt"
+     (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_NOR)
+     (set rd-rs (inv (or rd-rs rt)))
+     ())
+
+(dni nor "nor" (USES-RD USES-RS USES-RT)
+     "nor $rd,$rs,$rt"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_NOR)
+     (set rd (inv (or rs rt)))
+     ())
+
+(dni or2 "or" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "or ${rd-rs},$rt"
+     (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_OR)
+     (set rd-rs (or rd-rs rt))
+     ())
+
+(dni or "or" (USES-RD USES-RS USES-RT)
+     "or $rd,$rs,$rt"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_OR)
+     (set rd (or rs rt))
+     ())
+
+(dni ori2 "or immediate" (ALIAS NO-DIS USES-RS USES-RT)
+     "ori ${rt-rs},$lo16"
+     (+ OP_ORI rt-rs lo16)
+     (set rt-rs (or rt-rs (zext SI lo16)))
+     ())
+
+(dni ori "or immediate" (USES-RS USES-RT)
+     "ori $rt,$rs,$lo16"
+     (+ OP_ORI rs rt lo16)
+     (set rt (or rs (zext SI lo16)))
+     ())
+
+(dni ram "rotate and mask" (USES-RD USES-RT)
+     "ram $rd,$rt,$shamt,$maskl,$maskr"
+     (+ OP_RAM maskr rt rd shamt (f-5 0) maskl)
+     (sequence ()
+              (set rd (ror rt shamt))
+              (set rd (and rd (srl #xFFFFFFFF maskl)))
+              (set rd (and rd (sll #xFFFFFFFF maskr))))
+     ())
+
+(dni sll "shift left logical" (USES-RD USES-RT)
+     "sll $rd,$rt,$shamt"
+     (+ OP_SPECIAL (f-rs 0) rt rd shamt (f-func 0))
+     (set rd (sll rt shamt))
+     ())
+
+(dni sllv2 "shift left logical variable" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "sllv ${rd-rt},$rs"
+     (+ OP_SPECIAL rs rd-rt (f-shamt 0) FUNC_SLLV)
+     (set rd-rt (sll rd-rt (and rs #x1F)))
+     ())
+
+(dni sllv "shift left logical variable" (USES-RD USES-RS USES-RT)
+     "sllv $rd,$rt,$rs"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SLLV)
+     (set rd (sll rt (and rs #x1F)))
+     ())
+
+(dni slmv2 "shift left and mask variable" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "slmv ${rd-rt},$rs,$shamt"
+     (+ OP_SPECIAL rs rd-rt shamt FUNC_SLMV)
+     (set rd-rt (and (sll rd-rt shamt) (srl #xFFFFFFFF rs)))
+     ())
+
+(dni slmv "shift left and mask variable" (USES-RD USES-RS USES-RT)
+     "slmv $rd,$rt,$rs,$shamt"
+     (+ OP_SPECIAL rs rt rd shamt FUNC_SLMV)
+     (set rd (and (sll rt shamt) (srl #xFFFFFFFF rs)))
+     ())
+
+(dni slt2 "set if less than" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "slt ${rd-rs},$rt"
+     (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_SLT)
+     (if (lt rd-rs rt)
+        (set rd-rs 1)
+        (set rd-rs 0))
+     ())
+
+(dni slt "set if less than" (USES-RD USES-RS USES-RT)
+     "slt $rd,$rs,$rt"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SLT)
+     (if (lt rs rt)
+        (set rd 1)
+        (set rd 0))
+     ())
+
+(dni slti2 "set if less than immediate" (ALIAS NO-DIS USES-RS USES-RT)
+     "slti ${rt-rs},$imm"
+     (+ OP_SLTI rt-rs imm)
+     (if (lt rt-rs (ext SI (trunc HI imm)))
+        (set rt-rs 1)
+        (set rt-rs 0))
+     ())
+
+(dni slti "set if less than immediate" (USES-RS USES-RT)
+     "slti $rt,$rs,$imm"
+     (+ OP_SLTI rs rt imm)
+     (if (lt rs (ext SI (trunc HI imm)))
+        (set rt 1)
+        (set rt 0))
+     ())
+
+(dni sltiu2 "set if less than immediate unsigned" (ALIAS NO-DIS USES-RS USES-RT)
+     "sltiu ${rt-rs},$imm"
+     (+ OP_SLTIU rt-rs imm)
+     (if (ltu rt-rs (ext SI (trunc HI imm)))
+        (set rt-rs 1)
+        (set rt-rs 0))
+     ())
+
+(dni sltiu "set if less than immediate unsigned" (USES-RS USES-RT)
+     "sltiu $rt,$rs,$imm"
+     (+ OP_SLTIU rs rt imm)
+     (if (ltu rs (ext SI (trunc HI imm)))
+        (set rt 1)
+        (set rt 0))
+     ())
+
+(dni sltu2 "set if less than unsigned" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "sltu ${rd-rs},$rt"
+     (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_SLTU)
+     (if (ltu rd-rs rt)
+        (set rd-rs 1)
+        (set rd-rs 0))
+     ())
+
+(dni sltu "set if less than unsigned" (USES-RD USES-RS USES-RT)
+     "sltu $rd,$rs,$rt"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SLTU)
+     (if (ltu rs rt)
+        (set rd 1)
+        (set rd 0))
+     ())
+
+(dni sra2 "shift right arithmetic" (ALIAS NO-DIS USES-RD USES-RT)
+     "sra ${rd-rt},$shamt"
+     (+ OP_SPECIAL (f-rs 0) rd-rt shamt FUNC_SRA)
+     (set rd-rt (sra rd-rt shamt))
+     ())
+
+(dni sra "shift right arithmetic" (USES-RD USES-RT)
+     "sra $rd,$rt,$shamt"
+     (+ OP_SPECIAL (f-rs 0) rt rd shamt FUNC_SRA)
+     (set rd (sra rt shamt))
+     ())
+
+(dni srav2 "shift right arithmetic variable" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "srav ${rd-rt},$rs"
+     (+ OP_SPECIAL rs rd-rt (f-shamt 0) FUNC_SRAV)
+     (set rd-rt (sra rd-rt (and rs #x1F)))
+     ())
+
+(dni srav "shift right arithmetic variable" (USES-RD USES-RS USES-RT)
+     "srav $rd,$rt,$rs"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SRAV)
+     (set rd (sra rt (and rs #x1F)))
+     ())
+
+(dni srl "shift right logical" (USES-RD USES-RT)
+     "srl $rd,$rt,$shamt"
+     (+ OP_SPECIAL (f-rs 0) rt rd shamt FUNC_SRL)
+     (set rd (srl rt shamt))
+     ())
+
+(dni srlv2 "shift right logical variable" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "srlv ${rd-rt},$rs"
+     (+ OP_SPECIAL rs rd-rt (f-shamt 0) FUNC_SRLV)
+     (set rd-rt (srl rd-rt (and rs #x1F)))
+     ())
+
+(dni srlv "shift right logical variable" (USES-RD USES-RS USES-RT)
+     "srlv $rd,$rt,$rs"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SRLV)
+     (set rd (srl rt (and rs #x1F)))
+     ())
+
+(dni srmv2 "shift right and mask variable" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "srmv ${rd-rt},$rs,$shamt"
+     (+ OP_SPECIAL rs rd-rt shamt FUNC_SRMV)
+     (set rd-rt (and (srl rd-rt shamt) (sll #xFFFFFFFF rs)))
+     ())
+
+(dni srmv "shift right and mask variable" (USES-RD USES-RS USES-RT)
+     "srmv $rd,$rt,$rs,$shamt"
+     (+ OP_SPECIAL rs rt rd shamt FUNC_SRMV)
+     (set rd (and (srl rt shamt) (sll #xFFFFFFFF rs)))
+     ())
+
+(dni sub2 "subtract" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "sub ${rd-rs},$rt"
+     (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_SUB)
+     (set rd-rs (sub rd-rs rt))
+     ())
+
+(dni sub "subtract" (USES-RD USES-RS USES-RT)
+     "sub $rd,$rs,$rt"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SUB)
+     (set rd (sub rs rt))
+     ())
+
+(dni subu2 "subtract unsigned" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "subu ${rd-rs},$rt"
+     (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_SUBU)
+     (set rd-rs (sub rd-rs rt))
+     ())
+
+(dni subu "subtract unsigned" (USES-RD USES-RS USES-RT)
+     "subu $rd,$rs,$rt"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SUBU)
+     (set rd (sub rs rt))
+     ())
+
+(dni xor2 "exclusive or" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "xor ${rd-rs},$rt"
+     (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_XOR)
+     (set rd-rs (xor rd-rs rt))
+     ())
+
+(dni xor "exclusive or" (USES-RD USES-RS USES-RT)
+     "xor $rd,$rs,$rt"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_XOR)
+     (set rd (xor rs rt))
+     ())
+
+(dni xori2 "exclusive or immediate" (ALIAS NO-DIS USES-RS USES-RT)
+     "xori ${rt-rs},$lo16"
+     (+ OP_XORI rt-rs lo16)
+     (set rt-rs (xor rt-rs (zext SI lo16)))
+     ())
+
+(dni xori "exclusive or immediate" (USES-RS USES-RT)
+     "xori $rt,$rs,$lo16"
+     (+ OP_XORI rs rt lo16)
+     (set rt (xor rs (zext SI lo16)))
+     ())
+
+\f
+; Branch instructions.
+
+(dni bbi "branch bit immediate" (USES-RS)
+     "bbi $rs($bitnum),$offset"
+     (+ OP_BBI rs bitnum offset)
+     (if (bitset? rs bitnum)
+        (delay 1 (set pc offset)))
+     ())
+
+(dni bbin "branch bit immediate negated" (USES-RS)
+     "bbin $rs($bitnum),$offset"
+     (+ OP_BBIN rs bitnum offset)
+     (if (bitclear? rs bitnum)
+        (delay 1 (set pc offset)))
+     ())
+
+(dni bbv "branch bit variable" (USES-RS USES-RT)
+     "bbv $rs,$rt,$offset"
+     (+ OP_BBV rs rt offset)
+     (if (bitset? rs (and rt #x1F))
+        (delay 1 (set pc offset)))
+     ())
+
+(dni bbvn "branch bit variable negated" (USES-RS USES-RT)
+     "bbvn $rs,$rt,$offset"
+     (+ OP_BBVN rs rt offset)
+     (if (bitclear? rs (and rt #x1F))
+        (delay 1 (set pc offset)))
+     ())
+
+(dni beq "branch if equal" (USES-RS USES-RT)
+     "beq $rs,$rt,$offset"
+     (+ OP_BEQ rs rt offset)
+     (if (eq rs rt)
+        (delay 1 (set pc offset)))
+     ())
+
+(dni beql "branch if equal likely" (USES-RS USES-RT)
+     "beql $rs,$rt,$offset"
+     (+ OP_BEQL rs rt offset)
+     (if (eq rs rt)
+        (delay 1 (set pc offset))
+        (skip 1))
+     ())
+
+(dni bgez "branch if greater than or equal to zero" (USES-RS)
+     "bgez $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BGEZ offset)
+     (if (ge rs 0)
+        (delay 1 (set pc offset)))
+     ())
+
+(dni bgezal "branch if greater than or equal to zero and link" (USES-RS USES-R31)
+     "bgezal $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BGEZAL offset)
+     (if (ge rs 0)
+        (sequence ()
+                  (set (reg h-gr 31) (add pc 8))
+                  (delay 1 (set pc offset))))
+     ())
+
+(dni bgezall
+     "branch if greater than equal to zero and link likely" (USES-RS USES-R31)
+     "bgezall $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BGEZALL offset)
+     (if (ge rs 0)
+        (sequence ()
+                  (set (reg h-gr 31) (add pc 8))
+                  (delay 1 (set pc offset)))
+        (skip 1))
+     ())
+
+(dni bgezl "branch if greater or equal to zero likely" (USES-RS)
+     "bgezl $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BGEZL offset)
+     (if (ge rs 0)
+        (delay 1 (set pc offset))
+        (skip 1))
+     ())
+
+(dni bltz "branch if less than zero" (USES-RS)
+     "bltz $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BLTZ offset)
+     (if (lt rs 0)
+        (delay 1 (set pc offset)))
+     ())
+
+(dni bltzl "branch if less than zero likely" (USES-RS)
+     "bltzl $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BLTZL offset)
+     (if (lt rs 0)
+        (delay 1 (set pc offset))
+        (skip 1))
+     ())
+
+(dni bltzal "branch if less than zero and link" (USES-RS USES-R31)
+     "bltzal $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BLTZAL offset)
+     (if (lt rs 0)
+        (sequence ()
+                  (set (reg h-gr 31) (add pc 8))
+                  (delay 1 (set pc offset))))
+     ())
+
+(dni bltzall "branch if less than zero and link likely" (USES-RS USES-R31)
+     "bltzall $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BLTZALL offset)
+     (if (lt rs 0)
+        (sequence ()
+                  (set (reg h-gr 31) (add pc 8))
+                  (delay 1 (set pc offset)))
+        (skip 1))
+     ())
+
+(dni bmb0 "branch if matching byte-lane 0" (USES-RS USES-RT)
+     "bmb0 $rs,$rt,$offset"
+     (+ OP_BMB0 rs rt offset)
+     (if (eq (and rs #xFF) (and rt #xFF))
+        (delay 1 (set pc offset)))
+     ())
+
+(dni bmb1 "branch if matching byte-lane 1" (USES-RS USES-RT)
+     "bmb1 $rs,$rt,$offset"
+     (+ OP_BMB1 rs rt offset)
+     (if (eq (and rs #xFF00) (and rt #xFF00))
+        (delay 1 (set pc offset)))
+     ())
+
+(dni bmb2 "branch if matching byte-lane 2" (USES-RS USES-RT)
+     "bmb2 $rs,$rt,$offset"
+     (+ OP_BMB2 rs rt offset)
+     (if (eq (and rs #xFF0000) (and rt #xFF0000))
+        (delay 1 (set pc offset)))
+     ())
+
+(dni bmb3 "branch if matching byte-lane 3" (USES-RS USES-RT)
+     "bmb3 $rs,$rt,$offset"
+     (+ OP_BMB3 rs rt offset)
+     (if (eq (and rs #xFF000000) (and rt #xFF000000))
+        (delay 1 (set pc offset)))
+     ())
+
+(dni bne "branch if not equal" (USES-RS USES-RT)
+     "bne $rs,$rt,$offset"
+     (+ OP_BNE rs rt offset)
+     (if (ne rs rt)
+        (delay 1 (set pc offset)))
+     ())
+
+(dni bnel "branch if not equal likely" (USES-RS USES-RT)
+     "bnel $rs,$rt,$offset"
+     (+ OP_BNEL rs rt offset)
+     (if (ne rs rt)
+        (delay 1 (set pc offset))
+        (skip 1))
+     ())
+
+\f
+
+\f
+; Jump instructions.
+; Might as well jump!
+
+(dni jalr "jump and link register" (USES-RD USES-RS)
+     "jalr $rd,$rs"
+     (+ OP_SPECIAL rs (f-rt 0) rd (f-shamt 0) FUNC_JALR)
+     (delay 1
+           (sequence ()
+                     (set rd (add pc 8))
+                     (set pc rs)))
+     ())
+
+(dni jr "jump register" (USES-RS)
+     "jr $rs"
+     (+ OP_SPECIAL rs (f-rt 0) (f-rd 0) (f-shamt 0) FUNC_JR)
+     (delay 1 (set pc rs))
+     ())
+
+\f
+; Load instructions.
+
+(dni lb "load byte" (LOAD-DELAY USES-RS USES-RT)
+     "lb $rt,$lo16($base)"
+     (+ OP_LB base rt lo16)
+     (set rt (ext WI (mem QI (add base (ext SI (trunc HI lo16))))))
+;     (sequence ((SI addr) (SI word))
+;             (set addr (add base lo16))
+;             (set word (mem SI (and addr (inv 3))))
+;             (set word (srl word (sll (and addr 2) 3)))
+;             (set rt (ext SI word)))
+     ())
+
+(dni lbu "load byte unsigned" (LOAD-DELAY USES-RS USES-RT)
+     "lbu $rt,$lo16($base)"
+     (+ OP_LBU base rt lo16)
+     (set rt (zext WI (mem QI (add base (ext SI (trunc HI lo16))))))
+;     (sequence ((SI addr) (SI word))
+;             (set addr (add base lo16))
+;             (set word (mem SI (and addr (inv 3))))
+;             (set rt (srl word (sll (and addr 2) 3))))
+     ())
+
+(dni lh "load half word" (LOAD-DELAY USES-RS USES-RT)
+     "lh $rt,$lo16($base)"
+     (+ OP_LH base rt lo16)
+     (set rt (ext WI (mem HI (add base (ext SI (trunc HI lo16))))))
+;     (sequence ((SI addr) (HI word))
+;             (set addr (add base lo16))
+;             (set word (mem SI (and addr (inv 3))))
+;             (set word (srl word (sll (and addr 1) 4)))
+;             (set rt (ext SI word)))
+     ())
+
+(dni lhu "load half word unsigned" (LOAD-DELAY USES-RS USES-RT)
+     "lhu $rt,$lo16($base)"
+     (+ OP_LHU base rt lo16)
+     (set rt (zext WI (mem HI (add base (ext SI (trunc HI lo16))))))
+;     (sequence ((SI addr) (SI word))
+;             (set addr (add base lo16))
+;             (set word (mem SI (and addr (inv 3))))
+;             (set rt (srl word (sll (and addr 1) 4))))
+     ())
+
+(dni lui "load upper immediate" (USES-RT)
+     "lui $rt,$hi16"
+     (+ OP_LUI (f-rs 0) rt hi16)
+     (set rt (sll hi16 16))
+     ())
+
+(dni lw "load word" (LOAD-DELAY USES-RS USES-RT)
+    "lw $rt,$lo16($base)"
+    (+ OP_LW base rt lo16)
+    (set rt (mem SI (add base (ext SI (trunc HI lo16)))))
+    ())
+
+\f
+; Store instructions.
+
+(dni sb "store byte" (USES-RS USES-RT)
+     "sb $rt,$lo16($base)"
+     (+ OP_SB base rt lo16)
+     (set (mem QI (add base (ext SI (trunc HI lo16)))) (and QI rt #xFF))
+     ())
+
+(dni sh "store half word" (USES-RS USES-RT)
+     "sh $rt,$lo16($base)"
+     (+ OP_SH base rt lo16)
+     (set (mem HI (add base (ext SI (trunc HI lo16)))) (and HI rt #xFFFF))
+     ())
+
+(dni sw "store word" (USES-RS USES-RT)
+     "sw $rt,$lo16($base)"
+     (+ OP_SW base rt lo16)
+     (set (mem SI (add base (ext SI (trunc HI lo16)))) rt)
+     ())
+
+\f
+; Special instructions for simulation/debugging
+(dni break "breakpoint" ()
+     "break"
+     (+ OP_SPECIAL (f-rs 0) (f-rt 0) (f-rd 0) (f-shamt 0) FUNC_BREAK)
+     (c-call VOID "do_break" pc)
+     ())
+
+(dni syscall "system call" (YIELD-INSN)
+     "syscall"
+     (+ OP_SPECIAL execode (f-func 12))
+     (c-call VOID "do_syscall")
+     ())
+
+; Macro instructions, common to iq10 & iq2000
+
+(dnmi nop "nop" ()
+      "nop"
+      (emit sll (rd 0) (rt 0) (shamt 0))
+)
+
+(dnmi li "load immediate" (USES-RS NO-DIS)
+      "li $rs,$imm"
+      (emit ori (rt 0) rs imm)
+)
+
+(dnmi move "move" (USES-RD USES-RT NO-DIS)
+      "move $rd,$rt"
+      (emit or rd (rs 0) rt)
+)
+
+(dnmi lb-base-0 "load byte - implied base 0" (USES-RT NO-DIS)
+      "lb $rt,$lo16"
+      (emit lb rt lo16 (base 0))
+)
+
+(dnmi lbu-base-0 "load byte unsigned - implied base 0" (USES-RT NO-DIS)
+      "lbu $rt,$lo16"
+      (emit lbu rt lo16 (base 0))
+)
+
+(dnmi lh-base-0 "load half - implied base 0" (USES-RT NO-DIS)
+      "lh $rt,$lo16"
+      (emit lh rt lo16 (base 0))
+)
+
+(dnmi lw-base-0 "load word - implied base 0" (USES-RT NO-DIS)
+      "lw $rt,$lo16"
+      (emit lw rt lo16 (base 0))
+)
+
+(dnmi m-add "add immediate" (USES-RS USES-RT NO-DIS)
+      "add $rt,$rs,$lo16"
+      (emit addi rt rs lo16))
+
+(dnmi m-addu "add immediate unsigned" (USES-RS USES-RT NO-DIS)
+      "addu $rt,$rs,$lo16"
+      (emit addiu rt rs lo16)
+)
+
+(dnmi m-and "and immediate" (USES-RS USES-RT NO-DIS)
+      "and $rt,$rs,$lo16"
+      (emit andi rt rs lo16)
+)
+
+(dnmi m-j "jump register" (USES-RS NO-DIS)
+      "j $rs"
+      (emit jr rs)
+)
+
+(dnmi m-or "or immediate" (USES-RS USES-RT NO-DIS)
+      "or $rt,$rs,$lo16"
+      (emit ori rt rs lo16)
+)
+
+(dnmi m-sll "shift left logical" (USES-RD USES-RT USES-RS NO-DIS)
+      "sll $rd,$rt,$rs"
+      (emit sllv rd rt rs)
+)
+
+(dnmi m-slt "slt immediate" (USES-RS USES-RT NO-DIS)
+      "slt $rt,$rs,$imm"
+      (emit slti rt rs imm)
+)
+
+(dnmi m-sltu "sltu immediate" (USES-RS USES-RT NO-DIS)
+      "sltu $rt,$rs,$imm"
+      (emit sltiu rt rs imm)
+)
+
+(dnmi m-sra "shift right arithmetic" (USES-RD USES-RT USES-RS NO-DIS)
+      "sra $rd,$rt,$rs"
+      (emit srav rd rt rs)
+)
+
+(dnmi m-srl "shift right logical" (USES-RD USES-RT USES-RS NO-DIS)
+      "srl $rd,$rt,$rs"
+      (emit srlv rd rt rs)
+)
+
+(dnmi not "not" (USES-RD USES-RT NO-DIS)
+      "not $rd,$rt"
+      (emit nor rd (rs 0) rt)
+)
+
+(dnmi subi "sub immediate" (USES-RS USES-RT NO-DIS)
+      "subi $rt,$rs,$mlo16"
+      (emit addiu rt rs mlo16)
+)      
+
+(dnmi m-sub "subtract immediate" (USES-RS USES-RT NO-DIS)
+      "sub $rt,$rs,$mlo16"
+      (emit addiu rt rs mlo16)
+)
+
+(dnmi m-subu "subtract unsigned" (USES-RS USES-RT NO-DIS)
+      "subu $rt,$rs,$mlo16"
+      (emit addiu rt rs mlo16)
+)
+
+(dnmi sb-base-0 "store byte - implied base 0" (USES-RT NO-DIS)
+      "sb $rt,$lo16"
+      (emit sb rt lo16 (base 0))
+)
+
+(dnmi sh-base-0 "store half - implied base 0" (USES-RT NO-DIS)
+      "sh $rt,$lo16"
+      (emit sh rt lo16 (base 0))
+)
+
+(dnmi sw-base-0 "store word - implied base 0" (USES-RT NO-DIS)
+      "sw $rt,$lo16"
+      (emit sw rt lo16 (base 0))
+)
+
+(dnmi m-xor "xor immediate" (USES-RS USES-RT NO-DIS)
+      "xor $rt,$rs,$lo16"
+      (emit xori rt rs lo16)
+)
+
+
+(if (keep-mach? (iq2000))
+(include "iq2000m.cpu"))
+
+(if (keep-mach? (iq10))
+(include "iq10.cpu"))

diff --git a/cpu/iq2000.opc b/cpu/iq2000.opc
new file mode 100644 (file)
index 0000000..f180373
--- /dev/null
+++ b/cpu/iq2000.opc
@@ -0,0 +1,320 @@
+/* IQ2000 opcode support.  -*- C -*-
+
+   Copyright 2000, 2001, 2002, 2005, 2007, 2009 Free Software Foundation, Inc.
+
+   Contributed by Red Hat Inc; developed under contract from Fujitsu.
+
+   This file is part of the GNU Binutils.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* This file is an addendum to iq2000.cpu.  Heavy use of C code isn't
+   appropriate in .cpu files, so it resides here.  This especially applies
+   to assembly/disassembly where parsing/printing can be quite involved.
+   Such things aren't really part of the specification of the cpu, per se,
+   so .cpu files provide the general framework and .opc files handle the
+   nitty-gritty details as necessary.
+
+   Each section is delimited with start and end markers.
+
+   <arch>-opc.h additions use: "-- opc.h"
+   <arch>-opc.c additions use: "-- opc.c"
+   <arch>-asm.c additions use: "-- asm.c"
+   <arch>-dis.c additions use: "-- dis.c"
+   <arch>-ibd.h additions use: "-- ibd.h".  */
+\f
+/* -- opc.h */
+
+/* Allows reason codes to be output when assembler errors occur.  */
+#define CGEN_VERBOSE_ASSEMBLER_ERRORS
+
+/* Override disassembly hashing - there are variable bits in the top
+   byte of these instructions.  */
+#define CGEN_DIS_HASH_SIZE 8
+#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 6) % CGEN_DIS_HASH_SIZE)
+
+/* following activates check beyond hashing since some iq2000 and iq10
+   instructions have same mnemonics but different functionality. */
+#define CGEN_VALIDATE_INSN_SUPPORTED
+
+extern int iq2000_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
+
+/* -- asm.c */
+
+#include "safe-ctype.h"
+
+static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'");
+
+/* Special check to ensure that instruction exists for given machine.  */
+
+int
+iq2000_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
+{
+  int machs = cd->machs;
+
+  return (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH) & machs) != 0;
+}
+
+static int
+iq2000_cgen_isa_register (const char **strp)
+{
+  int len;
+  int ch1, ch2;
+
+  if (**strp == 'r' || **strp == 'R') 
+    {
+      len = strlen (*strp);
+      if (len == 2) 
+        {
+          ch1 = (*strp)[1];
+          if ('0' <= ch1 && ch1 <= '9')
+            return 1;
+        } 
+      else if (len == 3) 
+        {
+         ch1 = (*strp)[1];
+          ch2 = (*strp)[2];
+          if (('1' <= ch1 && ch1 <= '2') && ('0' <= ch2 && ch2 <= '9'))
+            return 1;
+          if ('3' == ch1 && (ch2 == '0' || ch2 == '1'))
+            return 1;
+        }
+    }
+  if (**strp == '%'
+      && TOLOWER ((*strp)[1]) != 'l'
+      && TOLOWER ((*strp)[1]) != 'h')
+    return 1;
+  return 0;
+}
+
+/* Handle negated literal.  */
+
+static const char *
+parse_mimm (CGEN_CPU_DESC cd,
+           const char **strp,
+           int opindex,
+           unsigned long *valuep)
+{
+  const char *errmsg;
+
+  /* Verify this isn't a register.  */
+  if (iq2000_cgen_isa_register (strp))
+    errmsg = _("immediate value cannot be register");
+  else
+    {
+      long value;
+      
+      errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
+      if (errmsg == NULL)
+       {
+         long x = (-value) & 0xFFFF0000;
+
+         if (x != 0 && x != (long) 0xFFFF0000)
+           errmsg = _("immediate value out of range");
+         else
+           *valuep = (-value & 0xFFFF);
+       }
+    }
+  return errmsg;
+}
+
+/* Handle signed/unsigned literal.  */
+
+static const char *
+parse_imm (CGEN_CPU_DESC cd,
+          const char **strp,
+          int opindex,
+          unsigned long *valuep)
+{
+  const char *errmsg;
+
+  if (iq2000_cgen_isa_register (strp))
+    errmsg = _("immediate value cannot be register");
+  else
+    {
+      long value;
+
+      errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
+      if (errmsg == NULL)
+       {
+         long x = value & 0xFFFF0000;
+
+         if (x != 0 && x != (long) 0xFFFF0000)
+           errmsg = _("immediate value out of range");
+         else
+           *valuep = (value & 0xFFFF);
+       }
+    }
+  return errmsg;
+}
+
+/* Handle iq10 21-bit jmp offset.  */
+
+static const char *
+parse_jtargq10 (CGEN_CPU_DESC cd,
+               const char **strp,
+               int opindex,
+               int reloc ATTRIBUTE_UNUSED,
+               enum cgen_parse_operand_result *type_addr ATTRIBUTE_UNUSED,
+               bfd_vma *valuep)
+{
+  const char *errmsg;
+  bfd_vma value;
+  enum cgen_parse_operand_result result_type = CGEN_PARSE_OPERAND_RESULT_NUMBER;
+
+  errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_OFFSET_21,
+                              & result_type, & value);
+  if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+    {
+      /* Check value is within 23-bits
+        (remembering that 2-bit shift right will occur).  */
+      if (value > 0x7fffff)
+        return _("21-bit offset out of range");
+    }
+  *valuep = (value & 0x7FFFFF);
+  return errmsg;
+}
+
+/* Handle high().  */
+
+static const char *
+parse_hi16 (CGEN_CPU_DESC cd,
+           const char **strp,
+           int opindex,
+           unsigned long *valuep)
+{
+  if (strncasecmp (*strp, "%hi(", 4) == 0)
+    {
+      enum cgen_parse_operand_result result_type;
+      bfd_vma value;
+      const char *errmsg;
+
+      *strp += 4;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16,
+                                  & result_type, & value);
+      if (**strp != ')')
+       return MISSING_CLOSING_PARENTHESIS;
+
+      ++*strp;
+      if (errmsg == NULL
+         && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+       {
+         /* If value has top-bit of %lo on, then it will
+            sign-propagate and so we compensate by adding
+            1 to the resultant %hi value.  */
+         if (value & 0x8000)
+           value += 0x10000;
+         value >>= 16;
+         value &= 0xffff;
+       }
+      *valuep = value;
+
+      return errmsg;
+    }
+
+  /* We add %uhi in case a user just wants the high 16-bits or is using
+     an insn like ori for %lo which does not sign-propagate.  */
+  if (strncasecmp (*strp, "%uhi(", 5) == 0)
+    {
+      enum cgen_parse_operand_result result_type;
+      bfd_vma value;
+      const char *errmsg;
+
+      *strp += 5;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_UHI16,
+                                  & result_type, & value);
+      if (**strp != ')')
+       return MISSING_CLOSING_PARENTHESIS;
+
+      ++*strp;
+      if (errmsg == NULL
+         && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+       value >>= 16;
+
+      value &= 0xffff;
+      *valuep = value;
+
+      return errmsg;
+    }
+
+  return parse_imm (cd, strp, opindex, valuep);
+}
+
+/* Handle %lo in a signed context.
+   The signedness of the value doesn't matter to %lo(), but this also
+   handles the case where %lo() isn't present.  */
+
+static const char *
+parse_lo16 (CGEN_CPU_DESC cd,
+           const char **strp,
+           int opindex,
+           unsigned long *valuep)
+{
+  if (strncasecmp (*strp, "%lo(", 4) == 0)
+    {
+      const char *errmsg;
+      enum cgen_parse_operand_result result_type;
+      bfd_vma value;
+
+      *strp += 4;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
+                                  & result_type, & value);
+      if (**strp != ')')
+       return MISSING_CLOSING_PARENTHESIS;
+      ++*strp;
+      if (errmsg == NULL
+         && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+       value &= 0xffff;
+      *valuep = value;
+      return errmsg;
+    }
+
+  return parse_imm (cd, strp, opindex, valuep);
+}
+
+/* Handle %lo in a negated signed context.
+   The signedness of the value doesn't matter to %lo(), but this also
+   handles the case where %lo() isn't present.  */
+
+static const char *
+parse_mlo16 (CGEN_CPU_DESC cd,
+            const char **strp,
+            int opindex,
+            unsigned long *valuep)
+{
+  if (strncasecmp (*strp, "%lo(", 4) == 0)
+    {
+      const char *errmsg;
+      enum cgen_parse_operand_result result_type;
+      bfd_vma value;
+
+      *strp += 4;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
+                                  & result_type, & value);
+      if (**strp != ')')
+       return MISSING_CLOSING_PARENTHESIS;
+      ++*strp;
+      if (errmsg == NULL
+         && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+       value = (-value) & 0xffff;
+      *valuep = value;
+      return errmsg;
+    }
+
+  return parse_mimm (cd, strp, opindex, valuep);
+}
+
+/* -- */

diff --git a/cpu/iq2000m.cpu b/cpu/iq2000m.cpu
new file mode 100644 (file)
index 0000000..5942241
--- /dev/null
+++ b/cpu/iq2000m.cpu
@@ -0,0 +1,631 @@
+; IQ2000-only CPU description. -*- Scheme -*-
+;
+; Copyright 2000, 2001, 2002, 2004, 2007, 2009 Free Software Foundation, Inc.
+;
+; Contributed by Red Hat Inc; developed under contract from Vitesse.
+;
+; This file is part of the GNU Binutils.
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 3 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, write to the Free Software
+; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+; MA 02110-1301, USA.
+
+(dni andoui "and upper ones immediate" (MACH2000 USES-RS USES-RT)
+     "andoui $rt,$rs,$hi16"
+     (+ OP_ANDOUI rs rt hi16)
+     (set rt (and rs (or (sll hi16 16) #xFFFF)))
+     ())
+
+(dni andoui2 "and upper ones immediate" (ALIAS NO-DIS MACH2000 USES-RS USES-RT)
+     "andoui ${rt-rs},$hi16"
+     (+ OP_ANDOUI rt-rs hi16)
+     (set rt-rs (and rt-rs (or (sll hi16 16) #xFFFF)))
+     ())
+
+(dni orui2 "or upper immediate" (ALIAS NO-DIS MACH2000 USES-RS USES-RT)
+     "orui ${rt-rs},$hi16"
+     (+ OP_ORUI rt-rs hi16)
+     (set rt-rs (or rt-rs (sll hi16 16)))
+     ())
+
+(dni orui "or upper immediate" (MACH2000 USES-RS USES-RT)
+     "orui $rt,$rs,$hi16"
+     (+ OP_ORUI rs rt hi16)
+     (set rt (or rs (sll hi16 16)))
+     ())
+
+(dni bgtz "branch if greater than zero" (MACH2000 USES-RS)
+     "bgtz $rs,$offset"
+     (+ OP_BGTZ rs (f-rt 0) offset)
+     (if (gt rs 0)
+        (delay 1 (set pc offset)))
+     ())
+
+
+(dni bgtzl "branch if greater than zero likely" (MACH2000 USES-RS)
+     "bgtzl $rs,$offset"
+     (+ OP_BGTZL rs (f-rt 0) offset)
+     (if (gt rs 0)
+        (delay 1 (set pc offset))
+        (skip 1))
+     ())
+
+(dni blez "branch if less than or equal to zero" (MACH2000 USES-RS)
+     "blez $rs,$offset"
+     (+ OP_BLEZ rs (f-rt 0) offset)
+     (if (le rs 0)
+        (delay 1 (set pc offset)))
+     ())
+
+(dni blezl "branch if less than or equal to zero likely" (MACH2000 USES-RS)
+     "blezl $rs,$offset"
+     (+ OP_BLEZL rs (f-rt 0) offset)
+     (if (le rs 0)
+        (delay 1 (set pc offset))
+        (skip 1))
+     ())
+
+
+(dni mrgb "merge bytes" (MACH2000 USES-RD USES-RS USES-RT)
+     "mrgb $rd,$rs,$rt,$mask"
+     (+ OP_SPECIAL rs rt rd (f-10 0) mask FUNC_MRGB)
+     (sequence ((SI temp))
+              (if (bitclear? mask 0)
+                  (set temp (and rs #xFF))
+                  (set temp (and rt #xFF)))
+              (if (bitclear? mask 1)
+                  (set temp (or temp (and rs #xFF00)))
+                  (set temp (or temp (and rt #xFF00))))
+              (if (bitclear? mask 2)
+                  (set temp (or temp (and rs #xFF0000)))
+                  (set temp (or temp (and rt #xFF0000))))
+              (if (bitclear? mask 3)
+                  (set temp (or temp (and rs #xFF000000)))
+                  (set temp (or temp (and rt #xFF000000))))
+              (set rd temp))
+     ())
+
+(dni mrgb2 "merge bytes" (ALIAS NO-DIS MACH2000 USES-RD USES-RS USES-RT)
+     "mrgb ${rd-rs},$rt,$mask"
+     (+ OP_SPECIAL rt rd-rs (f-10 0) mask FUNC_MRGB)
+     (sequence ((SI temp))
+              (if (bitclear? mask 0)
+                  (set temp (and rd-rs #xFF))
+                  (set temp (and rt #xFF)))
+              (if (bitclear? mask 1)
+                  (set temp (or temp (and rd-rs #xFF00)))
+                  (set temp (or temp (and rt #xFF00))))
+              (if (bitclear? mask 2)
+                  (set temp (or temp (and rd-rs #xFF0000)))
+                  (set temp (or temp (and rt #xFF0000))))
+              (if (bitclear? mask 3)
+                  (set temp (or temp (and rd-rs #xFF000000)))
+                  (set temp (or temp (and rt #xFF000000))))
+              (set rd-rs temp))
+     ())
+
+; NOTE: None of these instructions' semantics are specified, so they
+; will not work in a simulator.
+;
+; Architectural and coprocessor instructions.
+; BREAK and SYSCALL are implemented with escape hatches to the C
+; code.  These are used by the test suite to indicate pass/failures.
+
+(dni bctxt "branch and switch context" (MACH2000 DELAY-SLOT COND-CTI USES-RS)
+     "bctxt $rs,$offset"
+     (+ OP_REGIMM rs (f-rt 6) offset)
+     (unimp bctxt)
+     ())
+
+(dni bc0f "branch if copro 0 condition false" (MACH2000 DELAY-SLOT COND-CTI)
+     "bc0f $offset"
+     (+ OP_COP0 (f-rs 8) (f-rt 0) offset)
+     (unimp bc0f)
+     ())
+
+(dni bc0fl "branch if copro 0 condition false likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI)
+     "bc0fl $offset"
+     (+ OP_COP0 (f-rs 8) (f-rt 2) offset)
+     (unimp bc0fl)
+     ())
+
+(dni bc3f "branch if copro 3 condition false" (MACH2000 DELAY-SLOT COND-CTI)
+     "bc3f $offset"
+     (+ OP_COP3 (f-rs 8) (f-rt 0) offset)
+     (unimp bc3f)
+     ())
+
+(dni bc3fl "branch if copro 3 condition false likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI)
+     "bc3fl $offset"
+     (+ OP_COP3 (f-rs 8) (f-rt 2) offset)
+     (unimp bc3fl)
+     ())
+
+(dni bc0t "branch if copro 0 condition true" (MACH2000 DELAY-SLOT COND-CTI)
+     "bc0t $offset"
+     (+ OP_COP0 (f-rs 8) (f-rt 1) offset)
+     (unimp bc0t)
+     ())
+
+(dni bc0tl "branch if copro 0 condition true likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI)
+     "bc0tl $offset"
+     (+ OP_COP0 (f-rs 8) (f-rt 3) offset)
+     (unimp bc0tl)
+     ())
+
+(dni bc3t "branch if copro 3 condition true" (MACH2000 DELAY-SLOT COND-CTI)
+     "bc3t $offset"
+     (+ OP_COP3 (f-rs 8) (f-rt 1) offset)
+     (unimp bc3t)
+     ())
+
+(dni bc3tl "branch if copro 3 condition true likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI)
+     "bc3tl $offset"
+     (+ OP_COP3 (f-rs 8) (f-rt 3) offset)
+     (unimp bc3tl)
+     ())
+
+; Note that we don't set the USES-RD or USES-RT attributes for many of the following 
+; instructions, as it's the COP register that's being specified.
+
+(dni cfc0 "control from coprocessor 0" (MACH2000 LOAD-DELAY USES-RT)
+     "cfc0 $rt,$rd"
+     (+ OP_COP0 (f-rs 2) rt rd (f-10-11 0))
+     (unimp cfc0)
+     ())
+
+(dni cfc1 "control from coprocessor 1" (MACH2000 LOAD-DELAY USES-RT)
+     "cfc1 $rt,$rd"
+     (+ OP_COP1 (f-rs 2) rt rd (f-10-11 0))
+     (unimp cfc1)
+     ())
+
+(dni cfc2 "control from coprocessor 2" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN)
+     "cfc2 $rt,$rd"
+     (+ OP_COP2 (f-rs 2) rt rd (f-10-11 0))
+     (unimp cfc2)
+     ())
+
+(dni cfc3 "control from coprocessor 3" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN)
+     "cfc3 $rt,$rd"
+     (+ OP_COP3 (f-rs 2) rt rd (f-10-11 0))
+     (unimp cfc3)
+     ())
+
+; COPz instructions are an instruction form, not real instructions
+; with associated assembly mnemonics.  Therefore, they are omitted
+; from the ISA description.
+
+(dni chkhdr "check header" (MACH2000 LOAD-DELAY USES-RD YIELD-INSN)
+     "chkhdr $rd,$rt"
+     (+ OP_COP3 (f-rs 9) rt rd (f-shamt 0) (f-func 0))
+     (unimp chkhdr)
+     ())
+
+(dni ctc0 "control to coprocessor 0" (MACH2000 USES-RT)
+     "ctc0 $rt,$rd"
+     (+ OP_COP0 (f-rs 6) rt rd (f-10-11 0))
+     (unimp ctc0)
+     ())
+
+(dni ctc1 "control to coprocessor 1" (MACH2000 USES-RT)
+     "ctc1 $rt,$rd"
+     (+ OP_COP1 (f-rs 6) rt rd (f-10-11 0))
+     (unimp ctc1)
+     ())
+
+(dni ctc2 "control to coprocessor 2" (MACH2000 USES-RT)
+     "ctc2 $rt,$rd"
+     (+ OP_COP2 (f-rs 6) rt rd (f-10-11 0))
+     (unimp ctc2)
+     ())
+
+(dni ctc3 "control to coprocessor 3" (MACH2000 USES-RT)
+     "ctc3 $rt,$rd"
+     (+ OP_COP3 (f-rs 6) rt rd (f-10-11 0))
+     (unimp ctc3)
+     ())
+
+(dni jcr "jump context register" (MACH2000 DELAY-SLOT UNCOND-CTI USES-RS)
+     "jcr $rs"
+     (+ OP_SPECIAL rs (f-rt 0) (f-rd 0) (f-shamt 0) FUNC_JCR)
+     (unimp jcr)
+     ())
+
+(dni luc32 "lookup chain 32 bits" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "luc32 $rt,$rd"
+     (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 3))
+     (unimp luc32)
+     ())
+
+(dni luc32l "lookup chain 32 bits and lock" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "luc32l $rt,$rd"
+     (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 7))
+     (unimp luc32l)
+     ())
+
+(dni luc64 "lookup chain 64 bits" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "luc64 $rt,$rd"
+     (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 11))
+     (unimp luc64)
+     ())
+
+(dni luc64l "lookup chain 64 bits and lock" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "luc64l $rt,$rd"
+     (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 15))
+     (unimp luc64l)
+     ())
+
+(dni luk "lookup key" (MACH2000 USES-RD USES-RT)
+     "luk $rt,$rd"
+     (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 8))
+     (unimp luk)
+     ())
+
+(dni lulck "lookup lock" (MACH2000 USES-RT YIELD-INSN)
+     "lulck $rt"
+     (+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 4))
+     (unimp lulck)
+     ())
+
+(dni lum32 "lookup match 32 bits" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "lum32 $rt,$rd"
+     (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 2))
+     (unimp lum32)
+     ())
+
+(dni lum32l "lookup match 32 bits and lock" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "lum32l $rt,$rd"
+     (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 6))
+     (unimp lum32l)
+     ())
+
+(dni lum64 "lookup match 64 bits" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "lum64 $rt,$rd"
+     (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 10))
+     (unimp lum64)
+     ())
+
+(dni lum64l "lookup match 64 bits and lock" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "lum64l $rt,$rd"
+     (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 14))
+     (unimp lum64l)
+     ())
+
+(dni lur "lookup read" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "lur $rt,$rd"
+     (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 1))
+     (unimp lur)
+     ())
+
+(dni lurl "lookup read and lock" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "lurl $rt,$rd"
+     (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 5))
+     (unimp lurl)
+     ())
+
+(dni luulck "lookup unlock" (MACH2000 USES-RT YIELD-INSN)
+     "luulck $rt"
+     (+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 0))
+     (unimp luulck)
+     ())
+
+(dni mfc0 "move from coprocessor 0" (MACH2000 LOAD-DELAY USES-RT)
+     "mfc0 $rt,$rd"
+     (+ OP_COP0 (f-rs 0) rt rd (f-10-11 0))
+     (unimp mfc0)
+     ())
+
+(dni mfc1 "move from coprocessor 1" (MACH2000 LOAD-DELAY USES-RT)
+     "mfc1 $rt,$rd"
+     (+ OP_COP1 (f-rs 0) rt rd (f-10-11 0))
+     (unimp mfc1)
+     ())
+
+(dni mfc2 "move from coprocessor 2" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN)
+     "mfc2 $rt,$rd"
+     (+ OP_COP2 (f-rs 0) rt rd (f-10-11 0))
+     (unimp mfc2)
+     ())
+
+(dni mfc3 "move from coprocessor 3" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN)
+     "mfc3 $rt,$rd"
+     (+ OP_COP3 (f-rs 0) rt rd (f-10-11 0))
+     (unimp mfc3)
+     ())
+
+(dni mtc0 "move to coprocessor 0" (MACH2000 USES-RT)
+     "mtc0 $rt,$rd"
+     (+ OP_COP0 (f-rs 4) rt rd (f-10-11 0))
+     (unimp mtc0)
+     ())
+
+(dni mtc1 "move to coprocessor 1" (MACH2000 USES-RT)
+     "mtc1 $rt,$rd"
+     (+ OP_COP1 (f-rs 4) rt rd (f-10-11 0))
+     (unimp mtc1)
+     ())
+
+(dni mtc2 "move to coprocessor 2" (MACH2000 USES-RT)
+     "mtc2 $rt,$rd"
+     (+ OP_COP2 (f-rs 4) rt rd (f-10-11 0))
+     (unimp mtc2)
+     ())
+
+(dni mtc3 "move to coprocessor 3" (MACH2000 USES-RT)
+     "mtc3 $rt,$rd"
+     (+ OP_COP3 (f-rs 4) rt rd (f-10-11 0))
+     (unimp mtc3)
+     ())
+
+(dni pkrl "pkrl" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "pkrl $rd,$rt"
+     (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 7))
+     (unimp pkrl)
+     ())
+
+(dni pkrlr1 "pkrlr1" (MACH2000 USES-RT YIELD-INSN)
+     "pkrlr1 $rt,$_index,$count"
+     (+ OP_COP3 (f-rs 29) rt count _index)
+     (unimp pkrlr1)
+     ())
+
+(dni pkrlr30 "pkrlr30" (MACH2000 USES-RT YIELD-INSN)
+     "pkrlr30 $rt,$_index,$count"
+     (+ OP_COP3 (f-rs 31) rt count _index)
+     (unimp pkrlr30)
+     ())
+
+(dni rb "dma read bytes" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "rb $rd,$rt"
+     (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 4))
+     (unimp rb)
+     ())
+
+(dni rbr1 "dma read bytes using r1" (MACH2000 USES-RT YIELD-INSN)
+     "rbr1 $rt,$_index,$count"
+     (+ OP_COP3 (f-rs 24) rt count _index)
+     (unimp rbr1)
+     ())
+
+(dni rbr30 "dma read bytes using r30" (MACH2000 USES-RT YIELD-INSN)
+     "rbr30 $rt,$_index,$count"
+     (+ OP_COP3 (f-rs 26) rt count _index)
+     (unimp rbr30)
+     ())
+
+(dni rfe "restore from exception" (MACH2000)
+     "rfe"
+     (+ OP_COP0 (f-25 1) (f-24-19 0) (f-func 16))
+     (unimp rfe)
+     ())
+
+(dni rx "dma read word64s" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "rx $rd,$rt"
+     (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 6))
+     (unimp rx)
+     ())
+
+(dni rxr1 "dma read word64s using r1" (MACH2000 USES-RT YIELD-INSN)
+     "rxr1 $rt,$_index,$count"
+     (+ OP_COP3 (f-rs 28) rt count _index)
+     (unimp rxr1)
+     ())
+
+(dni rxr30 "dma read word 64s using r30" (MACH2000 USES-RT YIELD-INSN)
+     "rxr30 $rt,$_index,$count"
+     (+ OP_COP3 (f-rs 30) rt count _index)
+     (unimp rxr30)
+     ())
+
+(dni sleep "sleep" (MACH2000 YIELD-INSN)
+     "sleep"
+     (+ OP_SPECIAL execode FUNC_SLEEP)
+     (unimp sleep)
+     ())
+
+(dni srrd "sram read" (MACH2000 USES-RT YIELD-INSN)
+     "srrd $rt"
+     (+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 16))
+     (unimp srrd)
+     ())
+
+(dni srrdl "sram read and lock" (MACH2000 USES-RT YIELD-INSN)
+     "srrdl $rt"
+     (+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 20))
+     (unimp srrdl)
+     ())
+
+(dni srulck "sram unlock" (MACH2000 USES-RT YIELD-INSN)
+     "srulck $rt"
+     (+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 22))
+     (unimp srulck)
+     ())
+
+(dni srwr "sram write" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "srwr $rt,$rd"
+     (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 17))
+     (unimp srwr)
+     ())
+
+(dni srwru "sram write and unlock" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "srwru $rt,$rd"
+     (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 21))
+     (unimp srwru)
+     ())
+
+(dni trapqfl "yield if dma queue full" (MACH2000 YIELD-INSN)
+     "trapqfl"
+     (+ OP_COP3 (f-rs 1) (f-rt 0) (f-rd 0) (f-shamt 0) (f-func 8))
+     (unimp trapqfl)
+     ())
+
+(dni trapqne "yield if dma queue not empty" (MACH2000 YIELD-INSN)
+     "trapqne"
+     (+ OP_COP3 (f-rs 1) (f-rt 0) (f-rd 0) (f-shamt 0) (f-func 9))
+     (unimp trapqne)
+     ())
+
+(dni traprel "traprel" (MACH2000 USES-RT YIELD-INSN)
+     "traprel $rt"
+     (+ OP_COP3 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 10))
+     (unimp traprel)
+     ())
+
+(dni wb "dma write bytes" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "wb $rd,$rt"
+     (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 0))
+     (unimp wb)
+     ())
+
+(dni wbu "dma write bytes and unlock" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "wbu $rd,$rt"
+     (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 1))
+     (unimp wbu)
+     ())
+
+(dni wbr1 "dma write bytes using r1" (MACH2000 USES-RT YIELD-INSN)
+     "wbr1 $rt,$_index,$count"
+     (+ OP_COP3 (f-rs 16) rt count _index)
+     (unimp wbr1)
+     ())
+
+(dni wbr1u "dma write bytes using r1 and unlock" (MACH2000 USES-RT YIELD-INSN)
+     "wbr1u $rt,$_index,$count"
+     (+ OP_COP3 (f-rs 17) rt count _index)
+     (unimp wbr1u)
+     ())
+
+(dni wbr30 "dma write bytes using r30" (MACH2000 USES-RT YIELD-INSN)
+     "wbr30 $rt,$_index,$count"
+     (+ OP_COP3 (f-rs 18) rt count _index)
+     (unimp wbr30)
+     ())
+
+(dni wbr30u "dma write bytes using r30 and unlock" (MACH2000 USES-RT YIELD-INSN)
+     "wbr30u $rt,$_index,$count"
+     (+ OP_COP3 (f-rs 19) rt count _index)
+     (unimp wbr30u)
+     ())
+
+(dni wx "dma write word64s" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "wx $rd,$rt"
+     (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 2))
+     (unimp wx)
+     ())
+
+(dni wxu "dma write word64s and unlock" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "wxu $rd,$rt"
+     (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 3))
+     (unimp wxu)
+     ())
+
+(dni wxr1 "dma write word64s using r1" (MACH2000 USES-RT YIELD-INSN)
+     "wxr1 $rt,$_index,$count"
+     (+ OP_COP3 (f-rs 20) rt count _index)
+     (unimp wxr1)
+     ())
+
+(dni wxr1u "dma write word64s using r1 and unlock" (MACH2000 USES-RT YIELD-INSN)
+     "wxr1u $rt,$_index,$count"
+     (+ OP_COP3 (f-rs 21) rt count _index)
+     (unimp wxr1u)
+     ())
+
+(dni wxr30 "dma write word64s using r30" (MACH2000 USES-RT YIELD-INSN)
+     "wxr30 $rt,$_index,$count"
+     (+ OP_COP3 (f-rs 22) rt count _index)
+     (unimp wxr30)
+     ())
+
+(dni wxr30u "dma write word64s using r30 and unlock" (MACH2000 USES-RT YIELD-INSN)
+     "wxr30u $rt,$_index,$count"
+     (+ OP_COP3 (f-rs 23) rt count _index)
+     (unimp wxr30u)
+     ())
+
+
+; Load/Store instructions.
+
+(dni ldw "load double word" (MACH2000 EVEN-REG-NUM LOAD-DELAY USES-RT)
+     "ldw $rt,$lo16($base)"
+     (+ OP_LDW base rt lo16)
+     (sequence ((SI addr))
+              (set addr (and (add base lo16) (inv 3)))
+              (set (reg h-gr (add (ifield f-rt) 1)) (mem SI addr))
+              (set rt (mem SI (add addr 4))))
+     ())
+
+(dni sdw "store double word" (MACH2000 EVEN-REG-NUM USES-RT)
+     "sdw $rt,$lo16($base)"
+     (+ OP_SDW base rt lo16)
+     (sequence ((SI addr))
+              (set addr (and (add base lo16) (inv 3)))
+              (set (mem SI (add addr 4)) rt)
+              (set (mem SI addr) (reg h-gr (add (ifield f-rt) 1))))
+     ())
+
+
+; Jump instructions
+
+(dni j "jump" (MACH2000)
+     "j $jmptarg"
+     (+ OP_J (f-rsrvd 0) jmptarg)
+     (delay 1 (set pc jmptarg))
+     ())
+
+(dni jal "jump and link" (MACH2000 USES-R31)
+     "jal $jmptarg"
+     (+ OP_JAL (f-rsrvd 0) jmptarg)
+     (delay 1
+           (sequence ()
+                     (set (reg h-gr 31) (add pc 8))
+                     (set pc jmptarg)))
+     ())
+
+(dni bmb "branch if matching byte-lane" (MACH2000 USES-RS USES-RT)
+     "bmb $rs,$rt,$offset"
+     (+ OP_BMB rs rt offset)
+     (sequence ((BI branch?))
+              (set branch? 0)
+              (if (eq (and rs #xFF) (and rt #xFF))
+                  (set branch? 1))
+              (if (eq (and rs #xFF00) (and rt #xFF00))
+                  (set branch? 1))
+              (if (eq (and rs #xFF0000) (and rt #xFF0000))
+                  (set branch? 1))
+              (if (eq (and rs #xFF000000) (and rt #xFF000000))
+                  (set branch? 1))
+              (if branch?
+                  (delay 1 (set pc offset))))
+     ())
+
+
+; Macros
+
+(dnmi ldw-base-0 "load double word - implied base 0" (MACH2000 EVEN-REG-NUM LOAD-DELAY USES-RT USES-RS NO-DIS)
+      "ldw $rt,$lo16"
+      (emit ldw rt lo16 (base 0))
+)
+
+(dnmi sdw-base-0 "store double word - implied base 0" (MACH2000 EVEN-REG-NUM USES-RT NO-DIS)
+      "sdw $rt,$lo16"
+      (emit sdw rt lo16 (base 0))
+)
+
+
+
+
+
+

diff --git a/cpu/lm32.cpu b/cpu/lm32.cpu
new file mode 100644 (file)
index 0000000..31b943d
--- /dev/null
+++ b/cpu/lm32.cpu
@@ -0,0 +1,932 @@
+; Lattice Mico32 CPU description.  -*- Scheme -*-
+; Copyright 2008, 2009  Free Software Foundation, Inc.
+; Contributed by Jon Beniston <jon@beniston.com>
+;
+; This file is part of the GNU Binutils.
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 3 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, write to the Free Software
+; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+; MA 02110-1301, USA.
+
+(include "simplify.inc")
+
+(define-arch
+  (name lm32) ; name of cpu family
+  (comment "Lattice Mico32")
+  (default-alignment aligned)
+  (insn-lsb0? #t)
+  (machs lm32)
+  (isas lm32)
+)
+
+\f
+; Instruction sets.
+
+(define-isa
+  (name lm32)
+  (comment "Lattice Mico32 ISA")
+  (default-insn-word-bitsize 32)
+  (default-insn-bitsize 32)
+  (base-insn-bitsize 32)
+  (decode-assist (31 30 29 28 27 26))
+)
+
+\f
+; Cpu family definitions.
+
+(define-cpu
+  ; cpu names must be distinct from the architecture name and machine name
+  (name lm32bf)
+  (comment "Lattice Mico32 CPU")
+  (endian big)
+  (word-bitsize 32)
+)
+
+(define-mach
+  (name lm32)
+  (comment "Lattice Mico32 MACH")
+  (cpu lm32bf)
+)
+
+(define-model
+  (name lm32)
+  (comment "Lattice Mico32 reference implementation")
+  (mach lm32)
+  (unit u-exec "Execution unit" ()
+    1 1 () () () ())
+) 
+
+\f
+; Hardware elements.
+
+(dnh h-pc "Program counter" (PC) (pc) () () ())
+
+(dnh h-gr "General purpose registers"
+  ()
+  (register SI (32))
+  (keyword "" ( 
+               (gp 26) (fp 27) (sp 28) (ra 29) (ea 30) (ba 31)
+               (r0 0) (r1 1) (r2 2) (r3 3)
+               (r4 4) (r5 5) (r6 6) (r7 7)
+               (r8 8) (r9 9) (r10 10) (r11 11)
+               (r12 12) (r13 13) (r14 14) (r15 15)
+               (r16 16) (r17 17) (r18 18) (r19 19)
+               (r20 20) (r21 21) (r22 22) (r23 23)
+               (r24 24) (r25 25) (r26 26) (r27 27)
+               (r28 28) (r29 29) (r30 30) (r31 31)                
+              )
+  )
+  () ()
+)
+  
+(dnh h-csr "Control and status registers"
+  ()
+  (register SI (32))
+  (keyword "" (
+               (IE 0) (IM 1) (IP 2) 
+               (ICC 3) (DCC 4)
+               (CC 5)
+               (CFG 6)
+               (EBA 7)
+               (DC 8)
+               (DEBA 9)
+               (JTX 14) (JRX 15)          
+               (BP0 16) (BP1 17) (BP2 18) (BP3 19)
+               (WP0 24) (WP1 25) (WP2 26) (WP3 27)     
+              )
+  )
+  () ()
+)              
+  
+\f
+; Instruction fields.
+
+(dnf f-opcode   "opcode field"                () 31  6)
+(dnf f-r0       "register index 0 field"      () 25  5)
+(dnf f-r1       "register index 1 field"      () 20  5)
+(dnf f-r2       "register index 2 field"      () 15  5)
+(dnf f-resv0    "reserved"                    (RESERVED) 10 11)
+(dnf f-shift    "shift amount field"          ()  4  5)
+(df  f-imm      "signed immediate field"      () 15 16 INT #f #f)
+(dnf f-uimm     "unsigned immediate field"    () 15 16)
+(dnf f-csr      "csr field"                   () 25  5)
+(dnf f-user     "user defined field"          () 10 11)
+(dnf f-exception "exception field"            () 25 26)
+
+(df f-branch "branch offset field" (PCREL-ADDR) 15 16 INT
+        ((value pc) (sra SI (sub SI value pc) 2))
+        ((value pc) (add SI pc (sra SI (sll SI value 16) 14)))
+)
+(df f-call "call offset field" (PCREL-ADDR) 25 26 INT 
+        ((value pc) (sra SI (sub SI value pc) 2))
+        ((value pc) (add SI pc (sra SI (sll SI value 6) 4)))
+)
+
+\f
+; Operands.
+
+(dnop r0        "register 0"            () h-gr         f-r0)
+(dnop r1        "register 1"            () h-gr         f-r1)
+(dnop r2        "register 2"            () h-gr         f-r2)
+(dnop shift     "shift amout"           () h-uint       f-shift)
+(dnop imm       "signed immediate"      () h-sint       f-imm)
+(dnop uimm      "unsigned immediate"    () h-uint       f-uimm)
+(dnop branch    "branch offset"         () h-iaddr      f-branch)
+(dnop call      "call offset"           () h-iaddr      f-call)
+(dnop csr       "csr"                   () h-csr        f-csr)
+(dnop user      "user"                  () h-uint       f-user)
+(dnop exception "exception"             () h-uint       f-exception)
+            
+(define-operand
+  (name hi16)
+  (comment "high 16-bit immediate")
+  (attrs)
+  (type h-uint)
+  (index f-uimm)
+  (handlers (parse "hi16"))
+)
+
+(define-operand
+  (name lo16)
+  (comment "low 16-bit immediate")
+  (attrs)
+  (type h-uint)
+  (index f-uimm)
+  (handlers (parse "lo16"))
+)
+
+(define-operand
+  (name gp16)
+  (comment "gp relative 16-bit immediate")
+  (attrs)
+  (type h-sint)
+  (index f-imm)
+  (handlers (parse "gp16"))
+)
+
+(define-operand
+  (name got16)
+  (comment "got 16-bit immediate")
+  (attrs)
+  (type h-sint)
+  (index f-imm)
+  (handlers (parse "got16"))
+)
+
+(define-operand
+  (name gotoffhi16)
+  (comment "got offset high 16-bit immediate")
+  (attrs)
+  (type h-sint)
+  (index f-imm)
+  (handlers (parse "gotoff_hi16"))
+)
+
+(define-operand
+  (name gotofflo16)
+  (comment "got offset low 16-bit immediate")
+  (attrs)
+  (type h-sint)
+  (index f-imm)
+  (handlers (parse "gotoff_lo16"))
+)
+
+\f
+; Enumerations.
+
+(define-normal-insn-enum
+  opcodes "opcodes" () OP_ f-opcode
+  (("ADD"       45)      
+   ("ADDI"      13)      
+   ("AND"       40)
+   ("ANDI"      8)
+   ("ANDHI"     24)
+   ("B"         48)
+   ("BI"        56)
+   ("BE"        17)
+   ("BG"        18)
+   ("BGE"       19)
+   ("BGEU"      20)
+   ("BGU"       21)
+   ("BNE"       23)
+   ("CALL"      54)
+   ("CALLI"     62)
+   ("CMPE"      57)
+   ("CMPEI"     25)
+   ("CMPG"      58)
+   ("CMPGI"     26)
+   ("CMPGE"     59)
+   ("CMPGEI"    27)
+   ("CMPGEU"    60)
+   ("CMPGEUI"   28)
+   ("CMPGU"     61)
+   ("CMPGUI"    29)
+   ("CMPNE"     63)
+   ("CMPNEI"    31)
+   ("DIVU"      35)
+   ("LB"        4)
+   ("LBU"       16)
+   ("LH"        7)
+   ("LHU"       11)
+   ("LW"        10)
+   ("MODU"      49)
+   ("MUL"       34)
+   ("MULI"      2)
+   ("NOR"       33)
+   ("NORI"      1)
+   ("OR"        46)
+   ("ORI"       14)
+   ("ORHI"      30)
+   ("RAISE"     43)
+   ("RCSR"      36)
+   ("SB"        12)
+   ("SEXTB"     44)
+   ("SEXTH"     55)
+   ("SH"        3)
+   ("SL"        47)
+   ("SLI"       15)
+   ("SR"        37)
+   ("SRI"       5)
+   ("SRU"       32)
+   ("SRUI"      0)
+   ("SUB"       50)
+   ("SW"        22)
+   ("USER"      51)
+   ("WCSR"      52)
+   ("XNOR"      41)
+   ("XNORI"     9)
+   ("XOR"       38)
+   ("XORI"      6)
+  )
+)
+ 
+\f
+; Instructions. Note: Reg-reg must come before reg-imm.
+
+(dni add "add" ()
+        "add $r2,$r0,$r1"
+        (+ OP_ADD r0 r1 r2 (f-resv0 0))
+        (set r2 (add r0 r1))
+        ()
+)
+
+(dni addi "add immediate" ()
+        "addi $r1,$r0,$imm"  
+        (+ OP_ADDI r0 r1 imm)
+        (set r1 (add r0 (ext SI (trunc HI imm))))
+        ()
+)
+
+(dni and "and" ()
+        "and $r2,$r0,$r1"
+        (+ OP_AND r0 r1 r2 (f-resv0 0))
+        (set r2 (and r0 r1))
+        ()
+)
+
+(dni andi "and immediate" ()
+        "andi $r1,$r0,$uimm"  
+        (+ OP_ANDI r0 r1 uimm)
+        (set r1 (and r0 (zext SI uimm)))
+        ()
+)
+
+(dni andhii "and high immediate" ()
+        "andhi $r1,$r0,$hi16"  
+        (+ OP_ANDHI r0 r1 hi16)
+        (set r1 (and r0 (sll SI hi16 16)))
+        ()
+)
+
+(dni b "branch" ()
+        "b $r0"
+        (+ OP_B r0 (f-r1 0) (f-r2 0) (f-resv0 0))
+        (set pc (c-call USI "@cpu@_b_insn" r0 f-r0))
+        ()
+)
+
+(dni bi "branch immediate" ()
+        "bi $call"
+        (+ OP_BI call)
+        (set pc (ext SI call))
+        ()
+)
+
+(dni be "branch equal" ()
+        "be $r0,$r1,$branch"
+        (+ OP_BE r0 r1 branch)
+        (if (eq r0 r1)
+            (set pc branch)
+        )
+        ()
+)
+
+(dni bg "branch greater" ()
+        "bg $r0,$r1,$branch"
+        (+ OP_BG r0 r1 branch)
+        (if (gt r0 r1)
+            (set pc branch)
+        )
+        ()
+)
+
+(dni bge "branch greater or equal" ()
+        "bge $r0,$r1,$branch"
+        (+ OP_BGE r0 r1 branch)
+        (if (ge r0 r1)
+            (set pc branch)
+        )
+        ()
+)
+
+(dni bgeu "branch greater or equal unsigned" ()
+        "bgeu $r0,$r1,$branch"
+        (+ OP_BGEU r0 r1 branch)
+        (if (geu r0 r1)
+            (set pc branch)
+        )
+        ()
+)
+
+(dni bgu "branch greater unsigned" ()
+        "bgu $r0,$r1,$branch"
+        (+ OP_BGU r0 r1 branch)
+        (if (gtu r0 r1)
+            (set pc branch)
+        )
+        ()
+)
+
+(dni bne "branch not equal" ()
+        "bne $r0,$r1,$branch"
+        (+ OP_BNE r0 r1 branch)
+        (if (ne r0 r1)
+            (set pc branch)
+        )
+        ()
+)
+
+(dni call "call" ()
+        "call $r0"
+        (+ OP_CALL r0 (f-r1 0) (f-r2 0) (f-resv0 0))
+        (sequence ()
+                (set (reg h-gr 29) (add pc 4))
+                (set pc r0) 
+        )
+        ()
+)
+
+(dni calli "call immediate" ()
+        "calli $call"
+        (+ OP_CALLI call)
+        (sequence ()
+                (set (reg h-gr 29) (add pc 4))
+                (set pc (ext SI call)) 
+        )
+        ()
+)
+
+(dni cmpe "compare equal" ()
+        "cmpe $r2,$r0,$r1"  
+        (+ OP_CMPE r0 r1 r2 (f-resv0 0))
+        (set r2 (eq SI r0 r1))
+        ()
+)
+
+(dni cmpei "compare equal immediate" ()
+        "cmpei $r1,$r0,$imm"  
+        (+ OP_CMPEI r0 r1 imm)
+        (set r1 (eq SI r0 (ext SI (trunc HI imm))))
+        ()
+)
+
+(dni cmpg "compare greater than" ()
+        "cmpg $r2,$r0,$r1"  
+        (+ OP_CMPG r0 r1 r2 (f-resv0 0))
+        (set r2 (gt SI r0 r1))
+        ()
+)
+
+(dni cmpgi "compare greater than immediate" ()
+        "cmpgi $r1,$r0,$imm"  
+        (+ OP_CMPGI r0 r1 imm)
+        (set r1 (gt SI r0 (ext SI (trunc HI imm))))
+        ()
+)
+
+(dni cmpge "compare greater or equal" ()
+        "cmpge $r2,$r0,$r1"  
+        (+ OP_CMPGE r0 r1 r2 (f-resv0 0))
+        (set r2 (ge SI r0 r1))
+        ()
+)
+
+(dni cmpgei "compare greater or equal immediate" ()
+        "cmpgei $r1,$r0,$imm"  
+        (+ OP_CMPGEI r0 r1 imm)
+        (set r1 (ge SI r0 (ext SI (trunc HI imm))))
+        ()
+)
+
+(dni cmpgeu "compare greater or equal unsigned" ()
+        "cmpgeu $r2,$r0,$r1"  
+        (+ OP_CMPGEU r0 r1 r2 (f-resv0 0))
+        (set r2 (geu SI r0 r1))
+        ()
+)
+
+(dni cmpgeui "compare greater or equal unsigned immediate" ()
+        "cmpgeui $r1,$r0,$uimm"  
+        (+ OP_CMPGEUI r0 r1 uimm)
+        (set r1 (geu SI r0 (zext SI uimm)))
+        ()
+)
+
+(dni cmpgu "compare greater than unsigned" ()
+        "cmpgu $r2,$r0,$r1"  
+        (+ OP_CMPGU r0 r1 r2 (f-resv0 0))
+        (set r2 (gtu SI r0 r1))
+        ()
+)
+
+(dni cmpgui "compare greater than unsigned immediate" ()
+        "cmpgui $r1,$r0,$uimm"  
+        (+ OP_CMPGUI r0 r1 uimm)
+        (set r1 (gtu SI r0 (zext SI uimm)))
+        ()
+)
+
+(dni cmpne "compare not equal" ()
+        "cmpne $r2,$r0,$r1"  
+        (+ OP_CMPNE r0 r1 r2 (f-resv0 0))
+        (set r2 (ne SI r0 r1))
+        ()
+)
+
+(dni cmpnei "compare not equal immediate" ()
+        "cmpnei $r1,$r0,$imm"  
+        (+ OP_CMPNEI r0 r1 imm)
+        (set r1 (ne SI r0 (ext SI (trunc HI imm))))
+        ()
+)
+
+(dni divu "unsigned divide" ()
+        "divu $r2,$r0,$r1"
+        (+ OP_DIVU r0 r1 r2 (f-resv0 0))
+        (set pc (c-call USI "@cpu@_divu_insn" pc f-r0 f-r1 f-r2))
+        ()
+)
+
+(dni lb "load byte" ()
+        "lb $r1,($r0+$imm)"
+        (+ OP_LB r0 r1 imm)
+        (set r1 (ext SI (mem QI (add r0 (ext SI (trunc HI imm))))))
+        ()
+)
+
+(dni lbu "load byte unsigned" ()
+        "lbu $r1,($r0+$imm)"
+        (+ OP_LBU r0 r1 imm)
+        (set r1 (zext SI (mem QI (add r0 (ext SI (trunc HI imm))))))
+        ()
+)
+
+(dni lh "load halfword" ()
+        "lh $r1,($r0+$imm)"
+        (+ OP_LH r0 r1 imm)
+        (set r1 (ext SI (mem HI (add r0 (ext SI (trunc HI imm))))))
+        ()
+)
+
+(dni lhu "load halfword unsigned" ()
+        "lhu $r1,($r0+$imm)"
+        (+ OP_LHU r0 r1 imm)
+        (set r1 (zext SI (mem HI (add r0 (ext SI (trunc HI imm))))))
+        ()
+)
+
+(dni lw "load word" ()
+        "lw $r1,($r0+$imm)"
+        (+ OP_LW r0 r1 imm)
+        (set r1 (mem SI (add r0 (ext SI (trunc HI imm)))))
+        ()
+)
+
+(dni modu "unsigned modulus" ()
+        "modu $r2,$r0,$r1"
+        (+ OP_MODU r0 r1 r2 (f-resv0 0))
+        (set pc (c-call USI "@cpu@_modu_insn" pc f-r0 f-r1 f-r2))
+        ()
+)
+
+(dni mul "mulitply" ()
+        "mul $r2,$r0,$r1"
+        (+ OP_MUL r0 r1 r2 (f-resv0 0))
+        (set r2 (mul r0 r1))
+        ()
+)
+
+(dni muli "multiply immediate" ()
+        "muli $r1,$r0,$imm"  
+        (+ OP_MULI r0 r1 imm)
+        (set r1 (mul r0 (ext SI (trunc HI imm))))
+        ()
+)
+
+(dni nor "nor" ()
+        "nor $r2,$r0,$r1"
+        (+ OP_NOR r0 r1 r2 (f-resv0 0))
+        (set r2 (inv (or r0 r1)))
+        ()
+)
+
+(dni nori "nor immediate" ()
+        "nori $r1,$r0,$uimm"  
+        (+ OP_NORI r0 r1 uimm)
+        (set r1 (inv (or r0 (zext SI uimm))))
+        ()
+)
+
+(dni or "or" ()
+        "or $r2,$r0,$r1"
+        (+ OP_OR r0 r1 r2 (f-resv0 0))
+        (set r2 (or r0 r1))
+        ()
+)
+
+(dni ori "or immediate" ()
+        "ori $r1,$r0,$lo16"  
+        (+ OP_ORI r0 r1 lo16)
+        (set r1 (or r0 (zext SI lo16)))
+        ()
+)
+
+(dni orhii "or high immediate" ()
+        "orhi $r1,$r0,$hi16"  
+        (+ OP_ORHI r0 r1 hi16)
+        (set r1 (or r0 (sll SI hi16 16)))
+        ()
+)
+
+(dni rcsr "read control or status register" ()
+        "rcsr $r2,$csr"
+        (+ OP_RCSR csr (f-r1 0) r2 (f-resv0 0))
+        (set r2 csr) 
+        ()
+)
+
+(dni sb "store byte" ()
+        "sb ($r0+$imm),$r1"
+        (+ OP_SB r0 r1 imm)
+        (set (mem QI (add r0 (ext SI (trunc HI imm)))) r1)
+        ()
+)
+
+(dni sextb "sign extend byte" ()
+        "sextb $r2,$r0"
+        (+ OP_SEXTB r0 (f-r1 0) r2 (f-resv0 0))
+        (set r2 (ext SI (trunc QI r0)))
+        ()
+)
+
+(dni sexth "sign extend half-word" ()
+        "sexth $r2,$r0"
+        (+ OP_SEXTH r0 (f-r1 0) r2 (f-resv0 0))
+        (set r2 (ext SI (trunc HI r0)))
+        ()
+)
+
+(dni sh "store halfword" ()
+        "sh ($r0+$imm),$r1"
+        (+ OP_SH r0 r1 imm)
+        (set (mem HI (add r0 (ext SI (trunc HI imm)))) r1)
+        ()
+)
+
+(dni sl "shift left" ()
+        "sl $r2,$r0,$r1"
+        (+ OP_SL r0 r1 r2 (f-resv0 0))
+        (set r2 (sll SI r0 r1))
+        ()
+)
+
+(dni sli "shift left immediate" ()
+        "sli $r1,$r0,$imm"  
+        (+ OP_SLI r0 r1 imm)
+        (set r1 (sll SI r0 imm))
+        ()
+)
+
+(dni sr "shift right" ()
+        "sr $r2,$r0,$r1"
+        (+ OP_SR r0 r1 r2 (f-resv0 0))
+        (set r2 (sra SI r0 r1))
+        ()
+)
+
+(dni sri "shift right immediate" ()
+        "sri $r1,$r0,$imm"  
+        (+ OP_SRI r0 r1 imm)
+        (set r1 (sra SI r0 imm))
+        ()
+)
+
+(dni sru "shift right unsigned" ()
+        "sru $r2,$r0,$r1"
+        (+ OP_SRU r0 r1 r2 (f-resv0 0))
+        (set r2 (srl SI r0 r1))
+        ()
+)
+
+(dni srui "shift right unsigned immediate" ()
+        "srui $r1,$r0,$imm"  
+        (+ OP_SRUI r0 r1 imm)
+        (set r1 (srl SI r0 imm))
+        ()
+)
+
+(dni sub "subtract" ()
+        "sub $r2,$r0,$r1"
+        (+ OP_SUB r0 r1 r2 (f-resv0 0))
+        (set r2 (sub r0 r1))
+        ()
+)
+
+(dni sw "store word" ()
+        "sw ($r0+$imm),$r1"
+        (+ OP_SW r0 r1 imm)
+        (set (mem SI (add r0 (ext SI (trunc HI imm)))) r1)
+        ()
+)
+
+(dni user "user defined instruction" ()
+        "user $r2,$r0,$r1,$user"
+        (+ OP_USER r0 r1 r2 user)
+        (set r2 (c-call SI "@cpu@_user_insn" r0 r1 user))
+        ()
+)
+
+(dni wcsr "write control or status register" ()
+        "wcsr $csr,$r1"
+        (+ OP_WCSR csr r1 (f-r2 0) (f-resv0 0))
+        (c-call VOID "@cpu@_wcsr_insn" f-csr r1) 
+        ()
+)
+    
+(dni xor "xor" ()
+        "xor $r2,$r0,$r1"
+        (+ OP_XOR r0 r1 r2 (f-resv0 0))
+        (set r2 (xor r0 r1))
+        ()
+)
+
+(dni xori "xor immediate" ()
+        "xori $r1,$r0,$uimm"  
+        (+ OP_XORI r0 r1 uimm)
+        (set r1 (xor r0 (zext SI uimm)))
+        ()
+)
+
+(dni xnor "xnor" ()
+        "xnor $r2,$r0,$r1"
+        (+ OP_XNOR r0 r1 r2 (f-resv0 0))
+        (set r2 (inv (xor r0 r1)))
+        ()
+)
+
+(dni xnori "xnor immediate" ()
+        "xnori $r1,$r0,$uimm"  
+        (+ OP_XNORI r0 r1 uimm)
+        (set r1 (inv (xor r0 (zext SI uimm))))
+        ()
+)
+
+; Pseudo instructions
+
+(dni break "breakpoint" ()
+        "break"
+        (+ OP_RAISE (f-exception 2))
+        (set pc (c-call USI "@cpu@_break_insn" pc))
+        ()
+)
+
+(dni scall "system call" ()
+        "scall"
+        (+ OP_RAISE (f-exception 7))
+        (set pc (c-call USI "@cpu@_scall_insn" pc))
+        ()
+)
+
+(dni bret "return from breakpoint" (ALIAS)
+        "bret"
+        (+ OP_B (f-r0 31) (f-r1 0) (f-r2 0) (f-resv0 0))
+        (set pc (c-call USI "@cpu@_bret_insn" r0))
+        ()
+)
+
+(dni eret "return from exception" (ALIAS)
+        "eret"
+        (+ OP_B (f-r0 30) (f-r1 0) (f-r2 0) (f-resv0 0))
+        (set pc (c-call USI "@cpu@_eret_insn" r0))
+        ()
+)
+    
+(dni ret "return" (ALIAS)
+        "ret"
+        (+ OP_B (f-r0 29) (f-r1 0) (f-r2 0) (f-resv0 0))
+        (set pc r0)
+        ()
+)
+
+(dni mv "move" (ALIAS)
+        "mv $r2,$r0"
+        (+ OP_OR r0 (f-r1 0) r2 (f-resv0 0))
+        (set r2 r0)
+        ()
+)
+
+(dni mvi "move immediate" (ALIAS)
+        "mvi $r1,$imm"
+        (+ OP_ADDI (f-r0 0) r1 imm)
+        (set r1 (add r0 (ext SI (trunc HI imm))))
+        ()
+)
+
+(dni mvui "move unsigned immediate" (ALIAS)
+        "mvu $r1,$lo16"
+        (+ OP_ORI (f-r0 0) r1 lo16)
+        (set r1 (zext SI lo16))
+        ()
+)
+
+(dni mvhi "move high immediate" (ALIAS)
+        "mvhi $r1,$hi16"
+        (+ OP_ORHI (f-r0 0) r1 hi16)
+        (set r1 (or r0 (sll SI hi16 16)))
+        ()
+)
+
+(dni mva "move address" (ALIAS)
+        "mva $r1,$gp16"
+        (+ OP_ADDI (f-r0 26) r1 gp16)
+        (set r1 (add r0 (ext SI (trunc HI gp16))))
+        ()
+)
+
+(dni not "not" (ALIAS)
+        "not $r2,$r0"
+        (+ OP_XNOR r0 (f-r1 0) r2 (f-resv0 0))
+        (set r2 (inv r0))
+        ()
+)
+
+(dni nop "nop" (ALIAS)
+        "nop"
+        (+ OP_ADDI (f-r0 0) (f-r1 0) (f-imm 0))
+        (set r0 r0)
+        ()
+)
+
+(dni lbgprel "load byte gp relative" (ALIAS)
+        "lb $r1,$gp16"
+        (+ OP_LB (f-r0 26) r1 gp16)
+        (set r1 (ext SI (mem QI (add r0 (ext SI (trunc HI gp16))))))
+        ()
+)
+
+(dni lbugprel "load byte unsigned gp relative" (ALIAS)
+        "lbu $r1,$gp16"
+        (+ OP_LBU (f-r0 26) r1 gp16)
+        (set r1 (zext SI (mem QI (add r0 (ext SI (trunc HI gp16))))))
+        ()
+)
+
+(dni lhgprel "load halfword gp relative" (ALIAS)
+        "lh $r1,$gp16"
+        (+ OP_LH (f-r0 26) r1 gp16)
+        (set r1 (ext SI (mem HI (add r0 (ext SI (trunc HI gp16))))))
+        ()
+)
+
+(dni lhugprel "load halfword unsigned gp relative" (ALIAS)
+        "lhu $r1,$gp16"
+        (+ OP_LHU (f-r0 26) r1 gp16)
+        (set r1 (zext SI (mem HI (add r0 (ext SI (trunc HI gp16))))))
+        ()
+)
+
+(dni lwgprel "load word gp relative" (ALIAS)
+        "lw $r1,$gp16"
+        (+ OP_LW (f-r0 26) r1 gp16)
+        (set r1 (mem SI (add r0 (ext SI (trunc HI gp16)))))
+        ()
+)
+
+(dni sbgprel "store byte gp relative" (ALIAS)
+        "sb $gp16,$r1"
+        (+ OP_SB (f-r0 26) r1 gp16)
+        (set (mem QI (add r0 (ext SI (trunc HI gp16)))) r1)
+        ()
+)
+
+(dni shgprel "store halfword gp relative" (ALIAS)
+        "sh $gp16,$r1"
+        (+ OP_SH (f-r0 26) r1 gp16)
+        (set (mem HI (add r0 (ext SI (trunc HI gp16)))) r1)
+        ()
+)
+
+(dni swgprel "store word gp relative" (ALIAS)
+        "sw $gp16,$r1"
+        (+ OP_SW (f-r0 26) r1 gp16)
+        (set (mem SI (add r0 (ext SI (trunc HI gp16)))) r1)
+        ()
+)
+
+(dni lwgotrel "load word got relative" (ALIAS)
+        "lw $r1,(gp+$got16)"
+        (+ OP_LW (f-r0 26) r1 got16)
+        (set r1 (mem SI (add r0 (ext SI (trunc HI got16)))))
+        ()
+)
+
+(dni orhigotoffi "or high got offset immediate" (ALIAS)
+        "orhi $r1,$r0,$gotoffhi16"  
+        (+ OP_ORHI r0 r1 gotoffhi16)
+        (set r1 (or r0 (sll SI gotoffhi16 16)))
+        ()
+)
+
+(dni addgotoff "add got offset" (ALIAS)
+        "addi $r1,$r0,$gotofflo16"  
+        (+ OP_ADDI r0 r1 gotofflo16)
+        (set r1 (add r0 (ext SI (trunc HI gotofflo16))))
+        ()
+)
+
+(dni swgotoff "store word got offset" (ALIAS)
+        "sw ($r0+$gotofflo16),$r1"
+        (+ OP_SW r0 r1 gotofflo16)
+        (set (mem SI (add r0 (ext SI (trunc HI gotofflo16)))) r1)
+        ()
+)
+
+(dni lwgotoff "load word got offset" (ALIAS)
+        "lw $r1,($r0+$gotofflo16)"
+        (+ OP_LW r0 r1 gotofflo16)
+        (set r1 (mem SI (add r0 (ext SI (trunc HI gotofflo16)))))
+        ()
+)
+
+(dni shgotoff "store half word got offset" (ALIAS)
+        "sh ($r0+$gotofflo16),$r1"
+        (+ OP_SH r0 r1 gotofflo16)
+        (set (mem HI (add r0 (ext SI (trunc HI gotofflo16)))) r1)
+        ()
+)
+
+(dni lhgotoff "load half word got offset" (ALIAS)
+        "lh $r1,($r0+$gotofflo16)"
+        (+ OP_LH r0 r1 gotofflo16)
+        (set r1 (ext SI (mem HI (add r0 (ext SI (trunc HI gotofflo16))))))
+        ()
+)
+
+(dni lhugotoff "load half word got offset unsigned" (ALIAS)
+        "lhu $r1,($r0+$gotofflo16)"
+        (+ OP_LHU r0 r1 gotofflo16)
+        (set r1 (zext SI (mem HI (add r0 (ext SI (trunc HI gotofflo16))))))
+        ()
+)
+
+(dni sbgotoff "store byte got offset" (ALIAS)
+        "sb ($r0+$gotofflo16),$r1"
+        (+ OP_SB r0 r1 gotofflo16)
+        (set (mem QI (add r0 (ext SI (trunc HI gotofflo16)))) r1)
+        ()
+)
+
+(dni lbgotoff "load byte got offset" (ALIAS)
+        "lb $r1,($r0+$gotofflo16)"
+        (+ OP_LB r0 r1 gotofflo16)
+        (set r1 (ext SI (mem QI (add r0 (ext SI (trunc HI gotofflo16))))))
+        ()
+)
+
+(dni lbugotoff "load byte got offset unsigned" (ALIAS)
+        "lbu $r1,($r0+$gotofflo16)"
+        (+ OP_LBU r0 r1 gotofflo16)
+        (set r1 (zext SI (mem QI (add r0 (ext SI (trunc HI gotofflo16))))))
+        ()
+)

diff --git a/cpu/lm32.opc b/cpu/lm32.opc
new file mode 100644 (file)
index 0000000..3a814c2
--- /dev/null
+++ b/cpu/lm32.opc
@@ -0,0 +1,235 @@
+/* Lattice Mico32 opcode support.  -*- C -*-
+   Copyright 2008, 2009  Free Software Foundation, Inc.
+   Contributed by Jon Beniston <jon@beniston.com>
+
+   This file is part of the GNU Binutils.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* -- opc.h */
+
+/* Allows reason codes to be output when assembler errors occur.  */
+#define CGEN_VERBOSE_ASSEMBLER_ERRORS
+
+#define CGEN_DIS_HASH_SIZE 64
+#define CGEN_DIS_HASH(buf,value) ((value >> 26) & 0x3f) 
+
+/* -- asm.c */
+
+/* Handle signed/unsigned literal.  */
+
+static const char *
+parse_imm (CGEN_CPU_DESC cd,
+          const char **strp,
+          int opindex,
+          unsigned long *valuep)
+{
+  const char *errmsg;
+  signed long value;
+
+  errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
+  if (errmsg == NULL)
+    {
+      unsigned long x = value & 0xFFFF0000;
+      if (x != 0 && x != 0xFFFF0000)
+        errmsg = _("immediate value out of range");
+      else
+        *valuep = (value & 0xFFFF);
+    }
+  return errmsg;
+}
+
+/* Handle hi() */
+
+static const char *
+parse_hi16 (CGEN_CPU_DESC cd,
+           const char **strp,
+           int opindex,
+           unsigned long *valuep)
+{
+  if (strncasecmp (*strp, "hi(", 3) == 0)
+    {
+      enum cgen_parse_operand_result result_type;
+      bfd_vma value;
+      const char *errmsg;
+
+      *strp += 3;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16,
+                                   &result_type, &value);
+      if (**strp != ')')
+        return _("missing `)'");
+
+      ++*strp;
+      if (errmsg == NULL
+          && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+        value = (value >> 16) & 0xffff;
+      *valuep = value;
+
+      return errmsg;
+    }
+
+  return parse_imm (cd, strp, opindex, valuep);
+}
+
+/* Handle lo() */
+
+static const char *
+parse_lo16 (CGEN_CPU_DESC cd,
+           const char **strp,
+           int opindex,
+           unsigned long *valuep)
+{
+  if (strncasecmp (*strp, "lo(", 3) == 0)
+    {
+      const char *errmsg;
+      enum cgen_parse_operand_result result_type;
+      bfd_vma value;
+
+      *strp += 3;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
+                                   &result_type, &value);
+      if (**strp != ')')
+        return _("missing `)'");
+      ++*strp;
+      if (errmsg == NULL
+          && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+        value &= 0xffff;
+      *valuep = value;
+      return errmsg;
+    }
+
+  return parse_imm (cd, strp, opindex, valuep);
+}
+
+/* Handle gp() */
+
+static const char *
+parse_gp16 (CGEN_CPU_DESC cd,
+           const char **strp,
+           int opindex,
+           long *valuep)
+{
+  if (strncasecmp (*strp, "gp(", 3) == 0)
+    {
+      const char *errmsg;
+      enum cgen_parse_operand_result result_type;
+      bfd_vma value;
+
+      *strp += 3;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_GPREL16,
+                                   & result_type, & value);
+      if (**strp != ')')
+        return _("missing `)'");
+      ++*strp;
+      if (errmsg == NULL
+          && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+        value &= 0xffff;
+      *valuep = value;
+      return errmsg;
+    }
+
+  return _("expecting gp relative address: gp(symbol)");
+}
+
+/* Handle got() */
+
+static const char *
+parse_got16 (CGEN_CPU_DESC cd,
+            const char **strp,
+            int opindex,
+            long *valuep)
+{
+  if (strncasecmp (*strp, "got(", 4) == 0)
+    {
+      const char *errmsg;
+      enum cgen_parse_operand_result result_type;
+      bfd_vma value;
+
+      *strp += 4;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LM32_16_GOT,
+                                   & result_type, & value);
+      if (**strp != ')')
+        return _("missing `)'");
+      ++*strp;
+      if (errmsg == NULL
+          && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+        value &= 0xffff;
+      *valuep = value;
+      return errmsg;
+    }
+
+  return _("expecting got relative address: got(symbol)");
+}
+
+/* Handle gotoffhi16() */
+
+static const char *
+parse_gotoff_hi16 (CGEN_CPU_DESC cd,
+                  const char **strp,
+                  int opindex,
+                  long *valuep)
+{
+  if (strncasecmp (*strp, "gotoffhi16(", 11) == 0)
+    {
+      const char *errmsg;
+      enum cgen_parse_operand_result result_type;
+      bfd_vma value;
+
+      *strp += 11;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LM32_GOTOFF_HI16,
+                                   & result_type, & value);
+      if (**strp != ')')
+        return _("missing `)'");
+      ++*strp;
+      if (errmsg == NULL
+          && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+        value &= 0xffff;
+      *valuep = value;
+      return errmsg;
+    }
+
+  return _("expecting got relative address: gotoffhi16(symbol)");
+}
+
+/* Handle gotofflo16() */
+
+static const char *
+parse_gotoff_lo16 (CGEN_CPU_DESC cd,
+                  const char **strp,
+                  int opindex,
+                  long *valuep)
+{
+  if (strncasecmp (*strp, "gotofflo16(", 11) == 0)
+    {
+      const char *errmsg;
+      enum cgen_parse_operand_result result_type;
+      bfd_vma value;
+
+      *strp += 11;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LM32_GOTOFF_LO16,
+                                   &result_type, &value);
+      if (**strp != ')')
+        return _("missing `)'");
+      ++*strp;
+      if (errmsg == NULL
+          && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+        value &= 0xffff;
+      *valuep = value;
+      return errmsg;
+    }
+
+  return _("expecting got relative address: gotofflo16(symbol)");
+}

diff --git a/cpu/m32c.cpu b/cpu/m32c.cpu
new file mode 100644 (file)
index 0000000..127da49
--- /dev/null
+++ b/cpu/m32c.cpu
@@ -0,0 +1,10520 @@
+; Renesas M32C CPU description.  -*- Scheme -*-
+;
+; Copyright 2005, 2006, 2007, 2009 Free Software Foundation, Inc.
+;
+; Contributed by Red Hat Inc; developed under contract from Renesas.
+;
+; This file is part of the GNU Binutils.
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 3 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, write to the Free Software
+; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+; MA 02110-1301, USA.
+
+(include "simplify.inc")
+
+(define-arch
+  (name m32c)
+  (comment "Renesas M32C")
+  (default-alignment forced)
+  (insn-lsb0? #f)
+  (machs m16c m32c)
+  (isas m16c m32c)
+)
+
+(define-isa
+  (name m16c)
+ 
+  (default-insn-bitsize 32)
+ 
+  ; Number of bytes of insn we can initially fetch.
+  (base-insn-bitsize 32)
+ 
+  ; Used in computing bit numbers.
+  (default-insn-word-bitsize 32)
+ 
+  (decode-assist (0 1 2 3 4 5 6 7)) ; Initial bitnumbers to decode insns by.
+
+  ; fetches 1 insn at a time.
+  (liw-insns 1)       
+
+  ; executes 1 insn at a time.
+  (parallel-insns 1)  
+  )
+
+(define-isa
+  (name m32c)
+ 
+  (default-insn-bitsize 32)
+ 
+  ; Number of bytes of insn we can initially fetch.
+  (base-insn-bitsize 32)
+ 
+  ; Used in computing bit numbers.
+  (default-insn-word-bitsize 32)
+ 
+  (decode-assist (0 1 2 3 4 5 6 7)) ; Initial bitnumbers to decode insns by.
+
+  ; fetches 1 insn at a time.
+  (liw-insns 1)       
+
+  ; executes 1 insn at a time.
+  (parallel-insns 1)  
+  )
+
+(define-cpu
+  ; cpu names must be distinct from the architecture name and machine names.
+  ; The "b" suffix stands for "base" and is the convention.
+  ; The "f" suffix stands for "family" and is the convention.
+  (name m16cbf)
+  (comment "Renesas M16C base family")
+  (insn-endian big)
+  (data-endian little)
+  (word-bitsize 16)
+)
+
+(define-cpu
+  ; cpu names must be distinct from the architecture name and machine names.
+  ; The "b" suffix stands for "base" and is the convention.
+  ; The "f" suffix stands for "family" and is the convention.
+  (name m32cbf)
+  (comment "Renesas M32C base family")
+  (insn-endian big)
+  (data-endian little)
+  (word-bitsize 16)
+)
+
+(define-mach
+  (name m16c)
+  (comment "Generic M16C cpu")
+  (cpu m32cbf)
+)
+
+(define-mach
+  (name m32c)
+  (comment "Generic M32C cpu")
+  (cpu m32cbf)
+)
+
+; Model descriptions.
+
+(define-model
+  (name m16c)
+  (comment "m16c") (attrs)
+  (mach m16c)
+
+  ; `state' is a list of variables for recording model state
+  ; (state)
+  (unit u-exec "Execution Unit" ()
+       1 1 ; issue done
+       () ; state
+       () ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+)
+
+(define-model
+  (name m32c)
+  (comment "m32c") (attrs)
+  (mach m32c)
+
+  ; `state' is a list of variables for recording model state
+  ; (state)
+  (unit u-exec "Execution Unit" ()
+       1 1 ; issue done
+       () ; state
+       () ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+)
+
+(define-attr
+  (type enum)
+  (name RL_TYPE)
+  (values NONE JUMP 1ADDR 2ADDR)
+  (default NONE)
+  )
+
+; Macros to simplify MACH attribute specification.
+
+(define-pmacro all-isas () (ISA m16c,m32c))
+(define-pmacro m16c-isa () (ISA m16c))
+(define-pmacro m32c-isa () (ISA m32c))
+
+(define-pmacro MACH16 (MACH m16c))
+(define-pmacro MACH32 (MACH m32c))
+
+(define-pmacro (machine size)
+  (MACH (.sym m size c)) (ISA (.sym m size c)))
+
+(define-pmacro RL_JUMP  (RL_TYPE JUMP))
+(define-pmacro RL_1ADDR (RL_TYPE 1ADDR))
+(define-pmacro RL_2ADDR (RL_TYPE 2ADDR))
+
+\f
+;=============================================================
+; Fields
+;-------------------------------------------------------------
+; Main opcodes
+;
+(dnf f-0-1  "opcode"                      (all-isas)   0 1)
+(dnf f-0-2  "opcode"                      (all-isas)   0 2)
+(dnf f-0-3  "opcode"                      (all-isas)   0 3)
+(dnf f-0-4  "opcode"                      (all-isas)   0 4)
+(dnf f-1-3  "opcode"                      (all-isas)   1 3)
+(dnf f-2-2  "opcode"                      (all-isas)   2 2)
+(dnf f-3-4  "opcode"                      (all-isas)   3 4)
+(dnf f-3-1  "opcode"                      (all-isas)   3 1)
+(dnf f-4-1  "opcode"                      (all-isas)   4 1)
+(dnf f-4-3  "opcode"                      (all-isas)   4 3)
+(dnf f-4-4  "opcode"                      (all-isas)   4 4)
+(dnf f-4-6  "opcode"                      (all-isas)   4 6)
+(dnf f-5-1  "opcode"                      (all-isas)   5 1)
+(dnf f-5-3  "opcode"                      (all-isas)   5 3)
+(dnf f-6-2  "opcode"                      (all-isas)   6 2)
+(dnf f-7-1  "opcode"                      (all-isas)   7 1)
+(dnf f-8-1  "opcode"                      (all-isas)   8 1)
+(dnf f-8-2  "opcode"                      (all-isas)   8 2)
+(dnf f-8-3  "opcode"                      (all-isas)   8 3)
+(dnf f-8-4  "opcode"                      (all-isas)   8 4)
+(dnf f-8-8  "opcode"                      (all-isas)   8 8)
+(dnf f-9-3  "opcode"                      (all-isas)   9 3)
+(dnf f-9-1  "opcode"                      (all-isas)   9 1)
+(dnf f-10-1 "opcode"                      (all-isas)  10 1)
+(dnf f-10-2 "opcode"                      (all-isas)  10 2)
+(dnf f-10-3 "opcode"                      (all-isas)  10 3)
+(dnf f-11-1 "opcode"                      (all-isas)  11 1)
+(dnf f-12-1 "opcode"                      (all-isas)  12 1)
+(dnf f-12-2 "opcode"                      (all-isas)  12 2)
+(dnf f-12-3 "opcode"                      (all-isas)  12 3)
+(dnf f-12-4 "opcode"                      (all-isas)  12 4)
+(dnf f-12-6 "opcode"                      (all-isas)  12 6)
+(dnf f-13-3 "opcode"                      (all-isas)  13 3)
+(dnf f-14-1 "opcode"                      (all-isas)  14 1)
+(dnf f-14-2 "opcode"                      (all-isas)  14 2)
+(dnf f-15-1 "opcode"                      (all-isas)  15 1)
+(dnf f-16-1 "opcode"                      (all-isas)  16 1)
+(dnf f-16-2 "opcode"                      (all-isas)  16 2)
+(dnf f-16-4 "opcode"                      (all-isas)  16 4)
+(dnf f-16-8 "opcode"                      (all-isas)  16 8)
+(dnf f-18-1 "opcode"                      (all-isas)  18 1)
+(dnf f-18-2 "opcode"                      (all-isas)  18 2)
+(dnf f-18-3 "opcode"                      (all-isas)  18 3)
+(dnf f-20-1 "opcode"                      (all-isas)  20 1)
+(dnf f-20-3 "opcode"                      (all-isas)  20 3)
+(dnf f-20-2 "opcode"                      (all-isas)  20 2)
+(dnf f-20-4 "opcode"                      (all-isas)  20 4)
+(dnf f-21-3 "opcode"                      (all-isas)  21 3)
+(dnf f-24-2 "opcode"                      (all-isas)  24 2)
+(dnf f-24-8 "opcode"                      (all-isas)  24 8)
+(dnf f-32-16 "opcode"                     (all-isas)  32 16)
+
+;-------------------------------------------------------------
+; Registers
+;-------------------------------------------------------------
+
+(dnf f-src16-rn "source Rn for m16c" (MACH16 m16c-isa) 10 2)
+(dnf f-src16-an "source An for m16c" (MACH16 m16c-isa) 11 1)
+
+(dnf f-src32-an-unprefixed "destination An for m32c" (MACH32 m32c-isa) 11 1)
+(dnf f-src32-an-prefixed   "destination An for m32c" (MACH32 m32c-isa) 19 1)
+
+; QI mode gr encoding for m32c is different than for m16c. The hardware
+; is indexed using the m16c encoding, so perform the transformation here.
+;  register  m16c    m32c
+;  ----------------------
+;   r0l      00'b    10'b
+;   r0h      01'b    00'b
+;   r1l      10'b    11'b
+;   r1h      11'b    01'b
+(df  f-src32-rn-unprefixed-QI "source Rn QI for m32c" (MACH32 m32c-isa) 10 2 UINT
+     ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert
+     ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract
+)
+; QI mode gr encoding for m32c is different than for m16c. The hardware
+; is indexed using the m16c encoding, so perform the transformation here.
+;  register  m16c    m32c
+;  ----------------------
+;   r0l      00'b    10'b
+;   r0h      01'b    00'b
+;   r1l      10'b    11'b
+;   r1h      11'b    01'b
+(df  f-src32-rn-prefixed-QI "source Rn QI for m32c" (MACH32 m32c-isa) 18 2 UINT
+     ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert
+     ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract
+)
+; HI mode gr encoding for m32c is different than for m16c. The hardware
+; is indexed using the m16c encoding, so perform the transformation here.
+;  register  m16c    m32c
+;  ----------------------
+;   r0       00'b    10'b
+;   r1       01'b    11'b
+;   r2       10'b    00'b
+;   r3       11'b    01'b
+(df  f-src32-rn-unprefixed-HI "source Rn HI for m32c" (MACH32 m32c-isa) 10 2 UINT
+     ((value pc) (mod USI (add value 2) 4)) ; insert
+     ((value pc) (mod USI (add value 2) 4)) ; extract
+)
+
+; HI mode gr encoding for m32c is different than for m16c. The hardware
+; is indexed using the m16c encoding, so perform the transformation here.
+;  register  m16c    m32c
+;  ----------------------
+;   r0       00'b    10'b
+;   r1       01'b    11'b
+;   r2       10'b    00'b
+;   r3       11'b    01'b
+(df  f-src32-rn-prefixed-HI "source Rn HI for m32c" (MACH32 m32c-isa) 18 2 UINT
+     ((value pc) (mod USI (add value 2) 4)) ; insert
+     ((value pc) (mod USI (add value 2) 4)) ; extract
+)
+
+; SI mode gr encoding for m32c is as follows:
+;  register  encoding  index
+;  -------------------------
+;   r2r0       10'b     0
+;   r3r1       11'b     1
+(df  f-src32-rn-unprefixed-SI "source Rn SI for m32c" (MACH32 m32c-isa) 10 2 UINT
+     ((value pc) (add USI value 2)) ; insert
+     ((value pc) (sub USI value 2)) ; extract
+)
+(df  f-src32-rn-prefixed-SI "source Rn SI for m32c" (MACH32 m32c-isa) 18 2 UINT
+     ((value pc) (add USI value 2)) ; insert
+     ((value pc) (sub USI value 2)) ; extract
+)
+
+(dnf f-dst32-rn-ext-unprefixed "destination Rn for m32c" (MACH32 m32c-isa) 9 1)
+
+(dnf f-dst16-rn      "destination Rn for m16c" (MACH16 m16c-isa) 14 2)
+(dnf f-dst16-rn-ext  "destination Rn for m16c" (MACH16 m16c-isa) 14 1)
+(dnf f-dst16-rn-QI-s "destination Rn for m16c" (MACH16 m16c-isa)  5 1)
+
+(dnf f-dst16-an   "destination An for m16c" (MACH16 m16c-isa) 15 1)
+(dnf f-dst16-an-s "destination An for m16c" (MACH16 m16c-isa)  4 1)
+
+(dnf f-dst32-an-unprefixed "destination An for m32c" (MACH32 m32c-isa)  9 1)
+(dnf f-dst32-an-prefixed   "destination An for m32c" (MACH32 m32c-isa) 17 1)
+
+; QI mode gr encoding for m32c is different than for m16c. The hardware
+; is indexed using the m16c encoding, so perform the transformation here.
+;  register  m16c    m32c
+;  ----------------------
+;   r0l      00'b    10'b
+;   r0h      01'b    00'b
+;   r1l      10'b    11'b
+;   r1h      11'b    01'b
+(df  f-dst32-rn-unprefixed-QI "destination Rn QI for m32c" (MACH32 m32c-isa) 8 2 UINT
+     ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert
+     ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract
+)
+(df  f-dst32-rn-prefixed-QI "destination Rn QI for m32c" (MACH32 m32c-isa) 16 2 UINT
+     ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert
+     ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract
+)
+; HI mode gr encoding for m32c is different than for m16c. The hardware
+; is indexed using the m16c encoding, so perform the transformation here.
+;  register  m16c    m32c
+;  ----------------------
+;   r0       00'b    10'b
+;   r1       01'b    11'b
+;   r2       10'b    00'b
+;   r3       11'b    01'b
+(df  f-dst32-rn-unprefixed-HI "destination Rn HI for m32c" (MACH32 m32c-isa) 8 2 UINT
+     ((value pc) (mod USI (add value 2) 4)) ; insert
+     ((value pc) (mod USI (add value 2) 4)) ; extract
+)
+(df  f-dst32-rn-prefixed-HI "destination Rn HI for m32c" (MACH32 m32c-isa) 16 2 UINT
+     ((value pc) (mod USI (add value 2) 4)) ; insert
+     ((value pc) (mod USI (add value 2) 4)) ; extract
+)
+; SI mode gr encoding for m32c is as follows:
+;  register  encoding  index
+;  -------------------------
+;   r2r0       10'b     0
+;   r3r1       11'b     1
+(df  f-dst32-rn-unprefixed-SI "destination Rn SI for m32c" (MACH32 m32c-isa) 8 2 UINT
+     ((value pc) (add USI value 2)) ; insert
+     ((value pc) (sub USI value 2)) ; extract
+)
+(df  f-dst32-rn-prefixed-SI "destination Rn SI for m32c" (MACH32 m32c-isa) 16 2 UINT
+     ((value pc) (add USI value 2)) ; insert
+     ((value pc) (sub USI value 2)) ; extract
+)
+
+(dnf f-dst16-1-S "destination R0[hl] for m16c" (MACH16 m16c-isa) 5 1)
+
+;-------------------------------------------------------------
+; Immediates embedded in the base insn
+;-------------------------------------------------------------
+
+(df f-imm-8-s4   "4  bit   signed" (all-isas)  8  4  INT #f #f)
+(df f-imm-12-s4  "4  bit   signed" (all-isas) 12  4  INT #f #f)
+(df f-imm-13-u3  "3  bit unsigned" (all-isas) 13  3 UINT #f #f)
+(df f-imm-20-s4  "4  bit   signed" (all-isas) 20  4  INT #f #f)
+
+(df  f-imm1-S "1 bit immediate for short format binary insns" (MACH32 m32c-isa) 2 1 UINT
+     ((value pc) (sub USI value 1)) ; insert
+     ((value pc) (add USI value 1)) ; extract
+)
+
+(dnmf f-imm3-S "3 bit unsigned for short format insns" (all-isas) UINT
+      (f-2-2 f-7-1)
+      (sequence () ; insert
+               (set (ifield f-7-1) (and (sub (ifield f-imm3-S) 1) 1))
+               (set (ifield f-2-2) (and (srl (sub (ifield f-imm3-S) 1) 1) #x3))
+               )
+      (sequence () ; extract
+               (set (ifield f-imm3-S) (add (or (sll (ifield f-2-2) 1)
+                                               (ifield f-7-1))
+                                           1))
+               )
+)
+
+;-------------------------------------------------------------
+; Immediates and displacements beyond the base insn
+;-------------------------------------------------------------
+
+(df f-dsp-8-u6   "6  bit unsigned" (all-isas)  8  6 UINT #f #f)
+(df f-dsp-8-u8   "8  bit unsigned" (all-isas)  8  8 UINT #f #f)
+(df f-dsp-8-s8   "8  bit   signed" (all-isas)  8  8  INT #f #f)
+(df f-dsp-10-u6  "6  bit unsigned" (all-isas) 10  6 UINT #f #f)
+(df f-dsp-16-u8  "8  bit unsigned" (all-isas) 16  8 UINT #f #f)
+(df f-dsp-16-s8  "8  bit   signed" (all-isas) 16  8  INT #f #f)
+(df f-dsp-24-u8  "8  bit unsigned" (all-isas) 24  8 UINT #f #f)
+(df f-dsp-24-s8  "8  bit   signed" (all-isas) 24  8  INT #f #f)
+(df f-dsp-32-u8  "8  bit unsigned" (all-isas) 32  8 UINT #f #f)
+(df f-dsp-32-s8  "8  bit   signed" (all-isas) 32  8  INT #f #f)
+(df f-dsp-40-u8  "8  bit unsigned" (all-isas) 40  8 UINT #f #f)
+(df f-dsp-40-s8  "8  bit   signed" (all-isas) 40  8  INT #f #f)
+(df f-dsp-48-u8  "8  bit unsigned" (all-isas) 48  8 UINT #f #f)
+(df f-dsp-48-s8  "8  bit   signed" (all-isas) 48  8  INT #f #f)
+(df f-dsp-56-u8  "8  bit unsigned" (all-isas) 56  8 UINT #f #f)
+(df f-dsp-56-s8  "8  bit   signed" (all-isas) 56  8  INT #f #f)
+(df f-dsp-64-u8  "8  bit unsigned" (all-isas) 64  8 UINT #f #f)
+(df f-dsp-64-s8  "8  bit   signed" (all-isas) 64  8  INT #f #f)
+
+; Insn opcode endianness is big, but the immediate fields are stored
+; in little endian. Handle this here at the field level for all immediate
+; fields longer that 1 byte.
+;
+; CGEN can't handle a field which spans a 32 bit word boundary, so
+; handle those as multi ifields.
+;
+; Take care in expressions using 'srl' or 'sll' as part of some larger
+; expression meant to yield sign-extended values.  CGEN translates
+; uses of those operators into C expressions whose type is 'unsigned
+; int', which tends to make the whole expression 'unsigned int'.
+; Expressions like (set (ifield foo) X), however, just take X and
+; store it in some member of 'struct cgen_fields', all of whose
+; members are 'long'.  On machines where 'long' is larger than
+; 'unsigned int', assigning a "sign-extended" unsigned int to a long
+; just produces a very large positive value.  insert_normal will
+; range-check the field's value and produce odd error messages like
+; this:
+;
+; Error: operand out of range (4160684031 not between -2147483648 and 2147483647) `add.l #-265,-270[fb]'
+;
+; Annoyingly, the code will work fine on machines where 'long' and
+; 'unsigned int' are the same size: the assignment will produce a
+; negative number.
+;
+; Just tell yourself over and over: overflow detection is expensive,
+; and you're glad C doesn't do it, because it never happens in real
+; life.
+
+(df f-dsp-8-u16 "16 bit unsigned" (all-isas) 8 16 UINT
+     ((value pc) (or UHI
+                    (and (srl value 8) #x00ff)
+                    (and (sll value 8) #xff00))) ; insert
+     ((value pc) (or UHI
+                    (and UHI (srl UHI value 8) #x00ff)
+                    (and UHI (sll UHI value 8) #xff00))) ; extract
+)
+
+(df f-dsp-8-s16 "8 bit   signed" (all-isas) 8 16 INT
+     ((value pc) (ext INT 
+                     (trunc HI
+                            (or (and (srl value 8) #x00ff)
+                                (and (sll value 8) #xff00))))) ; insert
+     ((value pc) (ext INT
+                     (trunc HI
+                            (or (and (srl value 8) #x00ff)
+                                (and (sll value 8) #xff00))))) ; extract
+)
+
+(df f-dsp-16-u16 "16 bit unsigned" (all-isas) 16 16 UINT
+     ((value pc) (or UHI
+                    (and (srl value 8) #x00ff)
+                    (and (sll value 8) #xff00))) ; insert
+     ((value pc) (or UHI
+                    (and UHI (srl UHI value 8) #x00ff)
+                    (and UHI (sll UHI value 8) #xff00))) ; extract
+)
+
+(df f-dsp-16-s16 "16 bit   signed" (all-isas) 16 16 INT
+     ((value pc) (ext INT 
+                     (trunc HI
+                            (or (and (srl value 8) #x00ff)
+                                (and (sll value 8) #xff00))))) ; insert
+     ((value pc) (ext INT 
+                     (trunc HI
+                            (or (and (srl value 8) #x00ff)
+                                (and (sll value 8) #xff00))))) ; extract
+)
+
+(dnmf f-dsp-24-u16 "16 bit unsigned" (all-isas) UINT
+      (f-dsp-24-u8 f-dsp-32-u8)
+      (sequence () ; insert
+               (set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-u16) #xff))
+               (set (ifield f-dsp-32-u8) (and (srl (ifield f-dsp-24-u16) 8) #xff))
+               )
+      (sequence () ; extract
+               (set (ifield f-dsp-24-u16) (or (sll (ifield f-dsp-32-u8) 8)
+                                              (ifield f-dsp-24-u8)))
+               )
+)
+
+(dnmf f-dsp-24-s16 "16 bit signed" (all-isas) INT
+      (f-dsp-24-u8 f-dsp-32-u8)
+      (sequence () ; insert
+               (set (ifield f-dsp-24-u8) 
+                    (and (ifield f-dsp-24-s16) #xff))
+               (set (ifield f-dsp-32-u8) 
+                    (and (srl (ifield f-dsp-24-s16) 8) #xff))
+               )
+      (sequence () ; extract
+               (set (ifield f-dsp-24-s16)
+                    (ext INT
+                         (trunc HI (or (sll (ifield f-dsp-32-u8) 8)
+                                       (ifield f-dsp-24-u8)))))
+               )
+)
+
+(df f-dsp-32-u16 "16 bit unsigned" (all-isas) 32 16 UINT
+     ((value pc) (or UHI
+                    (and (srl value 8) #x00ff)
+                    (and (sll value 8) #xff00))) ; insert
+     ((value pc) (or UHI
+                    (and UHI (srl UHI value 8) #x00ff)
+                    (and UHI (sll UHI value 8) #xff00))) ; extract
+)
+
+(df f-dsp-32-s16 "16 bit   signed" (all-isas) 32 16 INT
+     ((value pc) (ext INT 
+                     (trunc HI
+                            (or (and (srl value 8) #x00ff)
+                                (and (sll value 8) #xff00))))) ; insert
+     ((value pc) (ext INT 
+                     (trunc HI
+                            (or (and (srl value 8) #x00ff)
+                                (and (sll value 8) #xff00))))) ; extract
+)
+
+(df f-dsp-40-u16 "16 bit unsigned" (all-isas) 40 16 UINT
+     ((value pc) (or UHI
+                    (and (srl value 8) #x00ff)
+                    (and (sll value 8) #xff00))) ; insert
+     ((value pc) (or UHI
+                    (and UHI (srl UHI value 8) #x00ff)
+                    (and UHI (sll UHI value 8) #xff00))) ; extract
+)
+
+(df f-dsp-40-s16 "16 bit   signed" (all-isas) 40 16 INT
+     ((value pc) (ext INT 
+                     (trunc HI
+                            (or (and (srl value 8) #x00ff)
+                                (and (sll value 8) #xff00))))) ; insert
+     ((value pc) (ext INT 
+                     (trunc HI
+                            (or (and (srl value 8) #x00ff)
+                                (and (sll value 8) #xff00))))) ; extract
+)
+
+(df f-dsp-48-u16 "16 bit unsigned" (all-isas) 48 16 UINT
+     ((value pc) (or UHI
+                    (and (srl value 8) #x00ff)
+                    (and (sll value 8) #xff00))) ; insert
+     ((value pc) (or UHI
+                    (and UHI (srl UHI value 8) #x00ff)
+                    (and UHI (sll UHI value 8) #xff00))) ; extract
+)
+
+(df f-dsp-48-s16 "16 bit   signed" (all-isas) 48 16 INT
+     ((value pc) (ext INT 
+                     (trunc HI
+                            (or (and (srl value 8) #x00ff)
+                                (and (sll value 8) #xff00))))) ; insert
+     ((value pc) (ext INT 
+                     (trunc HI
+                            (or (and (srl value 8) #x00ff)
+                                (and (sll value 8) #xff00))))) ; extract
+)
+
+(df f-dsp-64-u16 "16 bit unsigned" (all-isas) 64 16 UINT
+     ((value pc) (or UHI
+                    (and (srl value 8) #x00ff)
+                    (and (sll value 8) #xff00))) ; insert
+     ((value pc) (or UHI
+                    (and UHI (srl UHI value 8) #x00ff)
+                    (and UHI (sll UHI value 8) #xff00))) ; extract
+)
+(df  f-dsp-8-s24 "24 bit signed" (all-isas) 8 24 INT
+     ((value pc) (or SI
+                    (or (srl value 16) (and value #xff00))
+                    (sll (ext INT (trunc QI (and value #xff))) 16)))
+     ((value pc) (or SI
+                    (or (srl value 16) (and value #xff00))
+                    (sll (ext INT (trunc QI (and value #xff))) 16)))
+ )
+
+(df  f-dsp-8-u24 "24 bit unsigned" (all-isas) 8 24 UINT
+     ((value pc) (or SI
+                    (or (srl value 16) (and value #xff00))
+                    (sll (and value #xff) 16)))
+     ((value pc) (or SI
+                    (or (srl value 16) (and value #xff00))
+                    (sll (and value #xff) 16)))
+ )
+
+(dnmf f-dsp-16-u24 "24 bit unsigned" (all-isas) UINT
+      (f-dsp-16-u16 f-dsp-32-u8)
+      (sequence () ; insert
+               (set (ifield f-dsp-16-u16) (and (ifield f-dsp-16-u24) #xffff))
+               (set (ifield f-dsp-32-u8) (and (srl (ifield f-dsp-16-u24) 16) #xff))
+               )
+      (sequence () ; extract
+               (set (ifield f-dsp-16-u24) (or (sll (ifield f-dsp-32-u8) 16)
+                                              (ifield f-dsp-16-u16)))
+               )
+)
+
+(dnmf f-dsp-24-u24 "24 bit unsigned" (all-isas) UINT
+      (f-dsp-24-u8 f-dsp-32-u16)
+      (sequence () ; insert
+               (set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-u24) #xff))
+               (set (ifield f-dsp-32-u16) (and (srl (ifield f-dsp-24-u24) 8) #xffff))
+               )
+      (sequence () ; extract
+               (set (ifield f-dsp-24-u24) (or (sll (ifield f-dsp-32-u16) 8)
+                                              (ifield f-dsp-24-u8)))
+               )
+)
+
+(df f-dsp-32-u24 "24 bit unsigned" (all-isas) 32 24 UINT
+     ((value pc) (or USI
+                    (or USI
+                        (and (srl value 16) #x0000ff)
+                        (and value          #x00ff00))
+                    (and (sll value 16) #xff0000))) ; insert
+     ((value pc) (or USI
+                    (or USI
+                        (and USI (srl UHI value 16) #x0000ff)
+                        (and USI value              #x00ff00))
+                    (and USI (sll UHI value 16) #xff0000))) ; extract
+)
+
+(df f-dsp-40-u20 "20 bit unsigned" (all-isas) 40 20 UINT
+     ((value pc) (or USI
+                    (or USI
+                        (and (srl value 16) #x0000ff)
+                        (and value          #x00ff00))
+                    (and (sll value 16) #x0f0000))) ; insert
+     ((value pc) (or USI
+                    (or USI
+                        (and USI (srl UHI value 16) #x0000ff)
+                        (and USI value              #x00ff00))
+                    (and USI (sll UHI value 16) #x0f0000))) ; extract
+)
+(df f-dsp-40-u24 "24 bit unsigned" (all-isas) 40 24 UINT
+     ((value pc) (or USI
+                    (or USI
+                        (and (srl value 16) #x0000ff)
+                        (and value          #x00ff00))
+                    (and (sll value 16) #xff0000))) ; insert
+     ((value pc) (or USI
+                    (or USI
+                        (and USI (srl UHI value 16) #x0000ff)
+                        (and USI value              #x00ff00))
+                    (and USI (sll UHI value 16) #xff0000))) ; extract
+)
+
+(dnmf f-dsp-40-s32 "32 bit signed" (all-isas) INT
+      (f-dsp-40-u24 f-dsp-64-u8)
+      (sequence () ; insert
+               (set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-40-s32) 24) #xff))
+               (set (ifield f-dsp-40-u24) (and (ifield f-dsp-40-s32) #xffffff)) 
+               )
+      (sequence () ; extract
+               (set (ifield f-dsp-40-s32) (or (and (ifield f-dsp-40-u24) #xffffff)
+                                              (and (sll (ifield f-dsp-64-u8) 24) #xff000000)))
+               )
+)
+
+(dnmf f-dsp-48-u20 "20 bit unsigned" (all-isas) UINT
+      (f-dsp-48-u16 f-dsp-64-u8)
+      (sequence () ; insert
+               (set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-48-u20) 16) #x0f))
+               (set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u20) #xffff)) 
+               )
+      (sequence () ; extract
+               (set (ifield f-dsp-48-u20) (or (and (ifield f-dsp-48-u16) #xffff)
+                                              (and (sll (ifield f-dsp-64-u8) 16) #x0f0000)))
+               )
+)
+(dnmf f-dsp-48-u24 "24 bit unsigned" (all-isas) UINT
+      (f-dsp-48-u16 f-dsp-64-u8)
+      (sequence () ; insert
+               (set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-48-u24) 16) #xff))
+               (set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u24) #xffff)) 
+               )
+      (sequence () ; extract
+               (set (ifield f-dsp-48-u24) (or (and (ifield f-dsp-48-u16) #xffff)
+                                              (and (sll (ifield f-dsp-64-u8) 16) #xff0000)))
+               )
+)
+
+(dnmf f-dsp-16-s32 "32 bit signed" (all-isas) INT
+      (f-dsp-16-u16 f-dsp-32-u16)
+      (sequence () ; insert
+               (set (ifield f-dsp-32-u16) (and (srl (ifield f-dsp-16-s32) 16) #xffff))
+               (set (ifield f-dsp-16-u16) (and (ifield f-dsp-16-s32) #xffff)) 
+               )
+      (sequence () ; extract
+               (set (ifield f-dsp-16-s32) (or (and (ifield f-dsp-16-u16) #xffff)
+                                              (and (sll (ifield f-dsp-32-u16) 16) #xffff0000)))
+               )
+)
+
+(dnmf f-dsp-24-s32 "32 bit signed" (all-isas) INT
+      (f-dsp-24-u8 f-dsp-32-u24)
+      (sequence () ; insert
+               (set (ifield f-dsp-32-u24) (and (srl (ifield f-dsp-24-s32) 8) #xffffff))
+               (set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-s32) #xff)) 
+               )
+      (sequence () ; extract
+               (set (ifield f-dsp-24-s32) (or (and (ifield f-dsp-24-u8) #xff)
+                                              (and (sll (ifield f-dsp-32-u24) 8) #xffffff00)))
+               )
+)
+
+(df f-dsp-32-s32 "32 bit   signed" (all-isas) 32 32 INT
+     ((value pc) 
+
+      ;; insert
+      (ext INT
+          (or SI
+              (or SI
+                  (and (srl value 24) #x000000ff)
+                  (and (srl value 8)  #x0000ff00))
+              (or SI
+                  (and (sll value 8)  #x00ff0000)
+                  (and (sll value 24) #xff000000)))))
+
+     ;; extract
+     ((value pc)
+      (ext INT
+          (or SI
+              (or SI
+                  (and (srl value 24) #x000000ff)
+                  (and (srl value 8)  #x0000ff00))
+              (or SI
+                  (and (sll value 8)  #x00ff0000)
+                  (and (sll value 24) #xff000000)))))
+)
+
+(dnmf f-dsp-48-u32 "32 bit unsigned" (all-isas) UINT
+      (f-dsp-48-u16 f-dsp-64-u16)
+      (sequence () ; insert
+               (set (ifield f-dsp-64-u16) (and (srl (ifield f-dsp-48-u32) 16) #xffff))
+               (set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u32) #xffff)) 
+               )
+      (sequence () ; extract
+               (set (ifield f-dsp-48-u32) (or (and (ifield f-dsp-48-u16) #xffff)
+                                              (and (sll (ifield f-dsp-64-u16) 16) #xffff0000)))
+               )
+)
+
+(dnmf f-dsp-48-s32 "32 bit signed" (all-isas) INT
+      (f-dsp-48-u16 f-dsp-64-u16)
+      (sequence () ; insert
+               (set (ifield f-dsp-64-u16) (and (srl (ifield f-dsp-48-s32) 16) #xffff))
+               (set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-s32) #xffff)) 
+               )
+      (sequence () ; extract
+               (set (ifield f-dsp-48-s32) (or (and (ifield f-dsp-48-u16) #xffff)
+                                              (and (sll (ifield f-dsp-64-u16) 16) #xffff0000)))
+               )
+)
+
+(dnmf f-dsp-56-s16 "16 bit signed" (all-isas) INT
+      (f-dsp-56-u8 f-dsp-64-u8)
+      (sequence () ; insert
+               (set (ifield f-dsp-56-u8)
+                    (and (ifield f-dsp-56-s16) #xff))
+               (set (ifield f-dsp-64-u8)
+                    (and (srl (ifield f-dsp-56-s16) 8) #xff))
+               )
+      (sequence () ; extract
+               (set (ifield f-dsp-56-s16)
+                    (ext INT
+                         (trunc HI (or (sll (ifield f-dsp-64-u8) 8)
+                                       (ifield f-dsp-56-u8)))))
+               )
+)
+
+(df f-dsp-64-s16 " 16 bit signed" (all-isas) 64 16 INT
+     ((value pc) (ext INT 
+                     (trunc HI
+                            (or (and (srl value 8) #x00ff)
+                                (and (sll value 8) #xff00))))) ; insert
+     ((value pc) (ext INT 
+                     (trunc HI
+                            (or (and (srl value 8) #x00ff)
+                                (and (sll value 8) #xff00))))) ; extract
+)
+
+;-------------------------------------------------------------
+; Bit indices
+;-------------------------------------------------------------
+
+(dnf f-bitno16-S "bit index for m16c" (all-isas) 5 3)
+(dnf f-bitno32-prefixed "bit index for m32c" (all-isas) 21 3)
+(dnf f-bitno32-unprefixed "bit index for m32c" (all-isas) 13 3)
+
+(dnmf f-bitbase16-u11-S "unsigned bit,base:11" (all-isas) UINT
+      (f-bitno16-S f-dsp-8-u8)
+      (sequence () ; insert
+               (set (ifield f-bitno16-S) (and f-bitbase16-u11-S #x7))
+               (set (ifield f-dsp-8-u8) (and (srl (ifield f-bitbase16-u11-S) 3) #xff))
+               )
+      (sequence () ; extract
+               (set (ifield f-bitbase16-u11-S) (or (sll (ifield f-dsp-8-u8) 3)
+                                                   (ifield f-bitno16-S)))
+               )
+)
+
+(dnmf f-bitbase32-16-u11-unprefixed "unsigned bit,base:11" (all-isas) UINT
+      (f-bitno32-unprefixed f-dsp-16-u8)
+      (sequence () ; insert
+               (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-u11-unprefixed #x7))
+               (set (ifield f-dsp-16-u8) (and (srl (ifield f-bitbase32-16-u11-unprefixed) 3) #xff))
+               )
+      (sequence () ; extract
+               (set (ifield f-bitbase32-16-u11-unprefixed) (or (sll (ifield f-dsp-16-u8) 3)
+                                                             (ifield f-bitno32-unprefixed)))
+               )
+)
+(dnmf f-bitbase32-16-s11-unprefixed "signed bit,base:11" (all-isas) INT
+      (f-bitno32-unprefixed f-dsp-16-s8)
+      (sequence () ; insert
+               (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-s11-unprefixed #x7))
+               (set (ifield f-dsp-16-s8) (sra INT (ifield f-bitbase32-16-s11-unprefixed) 3))
+               )
+      (sequence () ; extract
+               (set (ifield f-bitbase32-16-s11-unprefixed) (or (sll (ifield f-dsp-16-s8) 3)
+                                                               (ifield f-bitno32-unprefixed)))
+               )
+)
+(dnmf f-bitbase32-16-u19-unprefixed "unsigned bit,base:19" (all-isas) UINT
+      (f-bitno32-unprefixed f-dsp-16-u16)
+      (sequence () ; insert
+               (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-u19-unprefixed #x7))
+               (set (ifield f-dsp-16-u16) (and (srl (ifield f-bitbase32-16-u19-unprefixed) 3) #xffff))
+               )
+      (sequence () ; extract
+               (set (ifield f-bitbase32-16-u19-unprefixed) (or (sll (ifield f-dsp-16-u16) 3)
+                                                               (ifield f-bitno32-unprefixed)))
+               )
+)
+(dnmf f-bitbase32-16-s19-unprefixed "signed bit,base:11" (all-isas) INT
+      (f-bitno32-unprefixed f-dsp-16-s16)
+      (sequence () ; insert
+               (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-s19-unprefixed #x7))
+               (set (ifield f-dsp-16-s16) (sra INT (ifield f-bitbase32-16-s19-unprefixed) 3))
+               )
+      (sequence () ; extract
+               (set (ifield f-bitbase32-16-s19-unprefixed) (or (sll (ifield f-dsp-16-s16) 3)
+                                                               (ifield f-bitno32-unprefixed)))
+               )
+)
+; SID decoder doesn't handle multi-ifield referencing another multi-ifield  :-(
+(dnmf f-bitbase32-16-u27-unprefixed "unsigned bit,base:27" (all-isas) UINT
+      (f-bitno32-unprefixed f-dsp-16-u16 f-dsp-32-u8)
+      (sequence () ; insert
+               (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-u27-unprefixed #x7))
+               (set (ifield f-dsp-16-u16) (and (srl (ifield f-bitbase32-16-u27-unprefixed) 3) #xffff))
+               (set (ifield f-dsp-32-u8) (and (srl (ifield f-bitbase32-16-u27-unprefixed) 19) #xff))
+               )
+      (sequence () ; extract
+               (set (ifield f-bitbase32-16-u27-unprefixed) (or (sll (ifield f-dsp-16-u16) 3)
+                                                             (or (sll (ifield f-dsp-32-u8) 19)
+                                                                 (ifield f-bitno32-unprefixed))))
+               )
+)
+(dnmf f-bitbase32-24-u11-prefixed "unsigned bit,base:11" (all-isas) UINT
+      (f-bitno32-prefixed f-dsp-24-u8)
+      (sequence () ; insert
+               (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-u11-prefixed #x7))
+               (set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-u11-prefixed) 3) #xff))
+               )
+      (sequence () ; extract
+               (set (ifield f-bitbase32-24-u11-prefixed) (or (sll (ifield f-dsp-24-u8) 3)
+                                                             (ifield f-bitno32-prefixed)))
+               )
+)
+(dnmf f-bitbase32-24-s11-prefixed "signed bit,base:11" (all-isas) INT
+      (f-bitno32-prefixed f-dsp-24-s8)
+      (sequence () ; insert
+               (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-s11-prefixed #x7))
+               (set (ifield f-dsp-24-s8) (sra INT (ifield f-bitbase32-24-s11-prefixed) 3))
+               )
+      (sequence () ; extract
+               (set (ifield f-bitbase32-24-s11-prefixed) (or (sll (ifield f-dsp-24-s8) 3)
+                                                             (ifield f-bitno32-prefixed)))
+               )
+)
+; SID decoder doesn't handle multi-ifield referencing another multi-ifield  :-(
+(dnmf f-bitbase32-24-u19-prefixed "unsigned bit,base:19" (all-isas) UINT
+      (f-bitno32-prefixed f-dsp-24-u8 f-dsp-32-u8)
+      (sequence () ; insert
+               (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-u19-prefixed #x7))
+               (set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-u19-prefixed)  3) #xff))
+               (set (ifield f-dsp-32-u8) (and (srl (ifield f-bitbase32-24-u19-prefixed) 11) #xff))
+               )
+      (sequence () ; extract
+               (set (ifield f-bitbase32-24-u19-prefixed) (or (sll (ifield f-dsp-24-u8) 3)
+                                                             (or (sll (ifield f-dsp-32-u8) 11)
+                                                                 (ifield f-bitno32-prefixed))))
+               )
+)
+; SID decoder doesn't handle multi-ifield referencing another multi-ifield  :-(
+(dnmf f-bitbase32-24-s19-prefixed "signed bit,base:11" (all-isas) INT
+      (f-bitno32-prefixed f-dsp-24-u8 f-dsp-32-s8)
+      (sequence () ; insert
+               (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-s19-prefixed #x7))
+               (set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-s19-prefixed) 3) #xff))
+               (set (ifield f-dsp-32-s8) (sra INT (ifield f-bitbase32-24-s19-prefixed) 11))
+               )
+      (sequence () ; extract
+               (set (ifield f-bitbase32-24-s19-prefixed) (or (sll (ifield f-dsp-24-u8) 3)
+                                                             (or (sll (ifield f-dsp-32-s8) 11)
+                                                                 (ifield f-bitno32-prefixed))))
+               )
+)
+; SID decoder doesn't handle multi-ifield referencing another multi-ifield  :-(
+(dnmf f-bitbase32-24-u27-prefixed "unsigned bit,base:27" (all-isas) UINT
+      (f-bitno32-prefixed f-dsp-24-u8 f-dsp-32-u16)
+      (sequence () ; insert
+               (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-u27-prefixed #x7))
+               (set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-u27-prefixed) 3) #xff))
+               (set (ifield f-dsp-32-u16) (and (srl (ifield f-bitbase32-24-u27-prefixed) 11) #xffff))
+               )
+      (sequence () ; extract
+               (set (ifield f-bitbase32-24-u27-prefixed) (or (sll (ifield f-dsp-24-u8) 3)
+                                                             (or (sll (ifield f-dsp-32-u16) 11)
+                                                                 (ifield f-bitno32-prefixed))))
+               )
+)
+
+;-------------------------------------------------------------
+; Labels
+;-------------------------------------------------------------
+
+(df  f-lab-5-3 "3 bit pc relative unsigned offset" (PCREL-ADDR all-isas) 5 3 UINT
+     ((value pc) (sub SI value (add SI pc 2))) ; insert
+     ((value pc) (add SI value (add SI pc 2))) ; extract
+)
+(dnmf f-lab32-jmp-s "unsigned 3 bit pc relative offset" (PCREL-ADDR all-isas) UINT
+      (f-2-2 f-7-1)
+      (sequence ((SI val)) ; insert
+               (set val (sub (sub (ifield f-lab32-jmp-s) pc) 2))
+               (set (ifield f-7-1) (and val #x1))
+               (set (ifield f-2-2) (srl val 1))
+               )
+      (sequence () ; extract
+               (set (ifield f-lab32-jmp-s) (add pc (add (or (sll (ifield f-2-2) 1)
+                                                            (ifield f-7-1))
+                                                        2)))
+               )
+)
+(df  f-lab-8-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 8 8 INT
+     ((value pc) (sub SI value (add SI pc 1))) ; insert
+     ((value pc) (add SI value (add SI pc 1))) ; extract
+)
+(df  f-lab-8-16 "16 bit pc relative signed offset" (PCREL-ADDR SIGN-OPT all-isas) 8 16 UINT
+     ((value pc) (or SI (sll (and (sub value (add pc 1)) #xff) 8)
+                    (srl (and (sub value (add pc 1)) #xffff) 8)))
+     ((value pc) (add SI (or (srl (and value #xffff) 8)
+                            (sra (sll (and value #xff) 24) 16)) (add pc 1)))
+ )
+(df  f-lab-8-24 "24 bit absolute" (all-isas ABS-ADDR) 8 24 UINT
+     ((value pc) (or SI
+                    (or (srl value 16) (and value #xff00))
+                    (sll (and value #xff) 16)))
+     ((value pc) (or SI
+                    (or (srl value 16) (and value #xff00))
+                    (sll (and value #xff) 16)))
+ )
+(df  f-lab-16-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 16 8 INT
+     ((value pc) (sub SI value (add SI pc 2))) ; insert
+     ((value pc) (add SI value (add SI pc 2))) ; extract
+)
+(df  f-lab-24-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 24 8 INT
+     ((value pc) (sub SI value (add SI pc 2))) ; insert
+     ((value pc) (add SI value (add SI pc 2))) ; extract
+)
+(df  f-lab-32-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 32 8 INT
+     ((value pc) (sub SI value (add SI pc 2))) ; insert
+     ((value pc) (add SI value (add SI pc 2))) ; extract
+)
+(df  f-lab-40-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 40 8 INT
+     ((value pc) (sub SI value (add SI pc 2))) ; insert
+     ((value pc) (add SI value (add SI pc 2))) ; extract
+)
+
+;-------------------------------------------------------------
+; Condition codes
+;-------------------------------------------------------------
+
+(dnf f-cond16    "condition code" (all-isas) 12 4)
+(dnf f-cond16j-5 "condition code" (all-isas)  5 3)
+
+(dnmf f-cond32 "condition code" (all-isas) UINT
+      (f-9-1 f-13-3)
+      (sequence () ; insert
+               (set (ifield f-9-1) (and (srl (ifield f-cond32) 3) 1))
+               (set (ifield f-13-3) (and (ifield f-cond32) #x7))
+               )
+      (sequence () ; extract
+               (set (ifield f-cond32) (or (sll (ifield f-9-1) 3)
+                                          (ifield f-13-3)))
+               )
+)
+
+(dnmf f-cond32j "condition code" (all-isas) UINT
+      (f-1-3 f-7-1)
+      (sequence () ; insert
+               (set (ifield f-1-3) (and (srl (ifield f-cond32j) 1) #x7))
+               (set (ifield f-7-1) (and (ifield f-cond32j) #x1))
+               )
+      (sequence () ; extract
+               (set (ifield f-cond32j) (or (sll (ifield f-1-3) 1)
+                                           (ifield f-7-1)))
+               )
+)
+\f
+;=============================================================
+; Hardware
+;
+(dnh h-pc "program counter" (PC all-isas) (pc USI) () () ())
+
+;-------------------------------------------------------------
+; General registers
+; The actual registers are 16 bits
+;-------------------------------------------------------------
+
+(define-hardware
+  (name h-gr)
+  (comment "general 16 bit registers")
+  (attrs all-isas CACHE-ADDR)
+  (type register HI (4))
+  (indices keyword "" (("r0" 0) ("r1" 1) ("r2" 2) ("r3" 3))))
+
+; Define different views of the grs as VIRTUAL with getter/setter specs
+;
+(define-hardware
+  (name h-gr-QI)
+  (comment "general 8 bit registers")
+  (attrs all-isas VIRTUAL)
+  (type register QI (4))
+  (indices keyword "" (("r0l" 0) ("r0h" 1) ("r1l" 2) ("r1h" 3)))
+  (get (index) (and (if SI (mod index 2)
+                       (srl (reg h-gr (div index 2)) 8)
+                       (reg h-gr (div index 2)))
+                   #xff))
+  (set (index newval) (set (reg h-gr (div index 2))
+                          (if SI (mod index 2)
+                              (or (and (reg h-gr (div index 2)) #xff)
+                                  (sll (and newval #xff) 8))
+                              (or (and (reg h-gr (div index 2)) #xff00)
+                                  (and newval #xff))))))
+
+(define-hardware
+  (name h-gr-HI)
+  (comment "general 16 bit registers")
+  (attrs all-isas VIRTUAL)
+  (type register HI (4))
+  (indices keyword "" (("r0" 0) ("r1" 1) ("r2" 2) ("r3" 3)))
+  (get (index) (reg h-gr index))
+  (set (index newval) (set (reg h-gr index) newval)))
+
+(define-hardware
+  (name h-gr-SI)
+  (comment "general 32 bit registers")
+  (attrs all-isas VIRTUAL)
+  (type register SI (2))
+  (indices keyword "" (("r2r0" 0) ("r3r1" 1)))
+  (get (index) (or SI
+                  (and (reg h-gr index) #xffff)
+                  (and (sll (reg h-gr (add index 2)) 16) #xffff0000)))
+  (set (index newval) (sequence ()
+                               (set (reg h-gr index) (and newval #xffff))
+                               (set (reg h-gr (add index 2)) (srl newval 16)))))
+
+(define-hardware
+  (name h-gr-ext-QI)
+  (comment "general 16 bit registers")
+  (attrs all-isas VIRTUAL)
+  (type register HI (2))
+  (indices keyword "" (("r0l" 0) ("r1l" 1)))
+  (get (index) (reg h-gr-QI (mul index 2)))
+  (set (index newval) (set (reg h-gr (mul index 2)) newval)))
+
+(define-hardware
+  (name h-gr-ext-HI)
+  (comment "general 16 bit registers")
+  (attrs all-isas VIRTUAL)
+  (type register SI (2))
+  (indices keyword "" (("r0" 0) ("r1" 1)))
+  (get (index) (reg h-gr (mul index 2)))
+  (set (index newval) (set (reg h-gr-SI index) newval)))
+
+(define-hardware
+  (name h-r0l)
+  (comment "r0l register")
+  (attrs all-isas VIRTUAL)
+  (type register QI)
+  (indices keyword "" (("r0l" 0)))
+  (get () (reg h-gr-QI 0))
+  (set (newval) (set (reg h-gr-QI 0) newval)))
+
+(define-hardware
+  (name h-r0h)
+  (comment "r0h register")
+  (attrs all-isas VIRTUAL)
+  (type register QI)
+  (indices keyword "" (("r0h" 0)))
+  (get () (reg h-gr-QI 1))
+  (set (newval) (set (reg h-gr-QI 1) newval)))
+
+(define-hardware
+  (name h-r1l)
+  (comment "r1l register")
+  (attrs all-isas VIRTUAL)
+  (type register QI)
+  (indices keyword "" (("r1l" 0)))
+  (get () (reg h-gr-QI 2))
+  (set (newval) (set (reg h-gr-QI 2) newval)))
+
+(define-hardware
+  (name h-r1h)
+  (comment "r1h register")
+  (attrs all-isas VIRTUAL)
+  (type register QI)
+  (indices keyword "" (("r1h" 0)))
+  (get () (reg h-gr-QI 3))
+  (set (newval) (set (reg h-gr-QI 3) newval)))
+
+(define-hardware
+  (name h-r0)
+  (comment "r0 register")
+  (attrs all-isas VIRTUAL)
+  (type register HI)
+  (indices keyword "" (("r0" 0)))
+  (get () (reg h-gr 0))
+  (set (newval) (set (reg h-gr 0) newval)))
+
+(define-hardware
+  (name h-r1)
+  (comment "r1 register")
+  (attrs all-isas VIRTUAL)
+  (type register HI)
+  (indices keyword "" (("r1" 0)))
+  (get () (reg h-gr 1))
+  (set (newval) (set (reg h-gr 1) newval)))
+
+(define-hardware
+  (name h-r2)
+  (comment "r2 register")
+  (attrs all-isas VIRTUAL)
+  (type register HI)
+  (indices keyword "" (("r2" 0)))
+  (get () (reg h-gr 2))
+  (set (newval) (set (reg h-gr 2) newval)))
+
+(define-hardware
+  (name h-r3)
+  (comment "r3 register")
+  (attrs all-isas VIRTUAL)
+  (type register HI)
+  (indices keyword "" (("r3" 0)))
+  (get () (reg h-gr 3))
+  (set (newval) (set (reg h-gr 3) newval)))
+
+(define-hardware
+  (name h-r0l-r0h)
+  (comment "r0l or r0h")
+  (attrs all-isas VIRTUAL)
+  (type register QI (2))
+  (indices keyword "" (("r0l" 0) ("r0h" 1)))
+  (get (index) (reg h-gr-QI index))
+  (set (index newval) (set (reg h-gr-QI index) newval)))
+
+(define-hardware
+  (name h-r2r0)
+  (comment "r2r0 register")
+  (attrs all-isas VIRTUAL)
+  (type register SI)
+  (indices keyword "" (("r2r0" 0)))
+  (get () (or (sll (reg h-gr 2) 16) (reg h-gr 0)))
+  (set (newval)
+       (sequence ()
+                (set (reg h-gr 0) newval)
+                (set (reg h-gr 2) (sra newval 16)))))
+
+(define-hardware
+  (name h-r3r1)
+  (comment "r3r1 register")
+  (attrs all-isas VIRTUAL)
+  (type register SI)
+  (indices keyword "" (("r3r1" 0)))
+  (get () (or (sll (reg h-gr 3) 16) (reg h-gr 1)))
+  (set (newval)
+       (sequence ()
+                (set (reg h-gr 1) newval)
+                (set (reg h-gr 3) (sra newval 16)))))
+
+(define-hardware
+  (name h-r1r2r0)
+  (comment "r1r2r0 register")
+  (attrs all-isas VIRTUAL)
+  (type register DI)
+  (indices keyword "" (("r1r2r0" 0)))
+  (get () (or DI (sll DI (reg h-gr 1) 32) (or (sll (reg h-gr 2) 16) (reg h-gr 0))))
+  (set (newval)
+       (sequence ()
+                (set (reg h-gr 0) newval)
+                (set (reg h-gr 2) (sra newval 16))
+                (set (reg h-gr 1) (sra newval 32)))))
+
+;-------------------------------------------------------------
+; Address registers
+;-------------------------------------------------------------
+
+(define-hardware
+  (name h-ar)
+  (comment "address registers")
+  (attrs all-isas)
+  (type register USI (2))
+  (indices keyword "" (("a0" 0) ("a1" 1)))
+  (get (index) (c-call USI "h_ar_get_handler" index))
+  (set (index newval) (c-call VOID "h_ar_set_handler" index newval)))
+
+; Define different views of the ars as VIRTUAL with getter/setter specs
+(define-hardware
+  (name h-ar-QI)
+  (comment "8 bit view of address register")
+  (attrs all-isas VIRTUAL)
+  (type register QI (2))
+  (indices keyword "" (("a0" 0) ("a1" 1)))
+  (get (index) (reg h-ar index))
+  (set (index newval) (set (reg h-ar index) newval)))
+
+(define-hardware
+  (name h-ar-HI)
+  (comment "16 bit view of address register")
+  (attrs all-isas VIRTUAL)
+  (type register HI (2))
+  (indices keyword "" (("a0" 0) ("a1" 1)))
+  (get (index) (reg h-ar index))
+  (set (index newval) (set (reg h-ar index) newval)))
+
+(define-hardware
+  (name h-ar-SI)
+  (comment "32 bit view of address register")
+  (attrs all-isas VIRTUAL)
+  (type register SI)
+  (indices keyword "" (("a1a0" 0)))
+  (get () (or SI (sll SI (ext SI (reg h-ar 1)) 16) (ext SI (reg h-ar 0))))
+  (set (newval) (sequence ()
+                         (set (reg h-ar 0) (and newval #xffff))
+                         (set (reg h-ar 1) (and (srl newval 16) #xffff)))))
+
+(define-hardware
+  (name h-a0)
+  (comment "16 bit view of address register")
+  (attrs all-isas VIRTUAL)
+  (type register HI)
+  (indices keyword "" (("a0" 0)))
+  (get () (reg h-ar 0))
+  (set (newval) (set (reg h-ar 0) newval)))
+
+(define-hardware
+  (name h-a1)
+  (comment "16 bit view of address register")
+  (attrs all-isas VIRTUAL)
+  (type register HI)
+  (indices keyword "" (("a1" 1)))
+  (get () (reg h-ar 1))
+  (set (newval) (set (reg h-ar 1) newval)))
+
+; SB Register
+(define-hardware
+  (name h-sb)
+  (comment "SB register")
+  (attrs all-isas)
+  (type register USI)
+  (get () (c-call USI "h_sb_get_handler"))
+  (set (newval) (c-call VOID "h_sb_set_handler" newval))
+)
+
+; FB Register
+(define-hardware
+  (name h-fb)
+  (comment "FB register")
+  (attrs all-isas)
+  (type register USI)
+  (get () (c-call USI "h_fb_get_handler"))
+  (set (newval) (c-call VOID "h_fb_set_handler" newval))
+)
+
+; SP Register
+(define-hardware
+  (name h-sp)
+  (comment "SP register")
+  (attrs all-isas)
+  (type register USI)
+  (get () (c-call USI "h_sp_get_handler"))
+  (set (newval) (c-call VOID "h_sp_set_handler" newval))
+)
+
+;-------------------------------------------------------------
+; condition-code bits
+;-------------------------------------------------------------
+
+(define-hardware
+  (name h-sbit)
+  (comment "sign bit")
+  (attrs all-isas)
+  (type register BI)
+)
+
+(define-hardware
+  (name h-zbit)
+  (comment "zero bit")
+  (attrs all-isas)
+  (type register BI)
+)
+
+(define-hardware
+  (name h-obit)
+  (comment "overflow bit")
+  (attrs all-isas)
+  (type register BI)
+)
+
+(define-hardware
+  (name h-cbit)
+  (comment "carry bit")
+  (attrs all-isas)
+  (type register BI)
+)
+
+(define-hardware
+  (name h-ubit)
+  (comment "stack pointer select bit")
+  (attrs all-isas)
+  (type register BI)
+)
+
+(define-hardware
+  (name h-ibit)
+  (comment "interrupt enable bit")
+  (attrs all-isas)
+  (type register BI)
+)
+
+(define-hardware
+  (name h-bbit)
+  (comment "register bank select bit")
+  (attrs all-isas)
+  (type register BI)
+)
+
+(define-hardware
+  (name h-dbit)
+  (comment "debug bit")
+  (attrs all-isas)
+  (type register BI)
+)
+
+(define-hardware
+  (name h-dct0)
+  (comment "dma transfer count 000")
+  (attrs all-isas)
+  (type register UHI)
+)
+(define-hardware
+  (name h-dct1)
+  (comment "dma transfer count 001")
+  (attrs all-isas)
+  (type register UHI)
+)
+(define-hardware
+  (name h-svf)
+  (comment "save flag 011")
+  (attrs all-isas)
+  (type register UHI)
+)
+(define-hardware
+  (name h-drc0)
+  (comment "dma transfer count reload 100")
+  (attrs all-isas)
+  (type register UHI)
+)
+(define-hardware
+  (name h-drc1)
+  (comment "dma transfer count reload 101")
+  (attrs all-isas)
+  (type register UHI)
+)
+(define-hardware
+  (name h-dmd0)
+  (comment "dma mode 110")
+  (attrs all-isas)
+  (type register UQI)
+)
+(define-hardware
+  (name h-dmd1)
+  (comment "dma mode 111")
+  (attrs all-isas)
+  (type register UQI)
+)
+(define-hardware
+  (name h-intb)
+  (comment "interrupt table 000")
+  (attrs all-isas)
+  (type register USI)
+)
+(define-hardware
+  (name h-svp)
+  (comment "save pc 100")
+  (attrs all-isas)
+  (type register UHI)
+)
+(define-hardware
+  (name h-vct)
+  (comment "vector 101")
+  (attrs all-isas)
+  (type register USI)
+)
+(define-hardware
+  (name h-isp)
+  (comment "interrupt stack ptr 111")
+  (attrs all-isas)
+  (type register USI)
+)
+(define-hardware
+  (name h-dma0)
+  (comment "dma mem addr 010")
+  (attrs all-isas)
+  (type register USI)
+)
+(define-hardware
+  (name h-dma1)
+  (comment "dma mem addr 011")
+  (attrs all-isas)
+  (type register USI)
+)
+(define-hardware
+  (name h-dra0)
+  (comment "dma mem addr reload 100")
+  (attrs all-isas)
+  (type register USI)
+)
+(define-hardware
+  (name h-dra1)
+  (comment "dma mem addr reload 101")
+  (attrs all-isas)
+  (type register USI)
+)
+(define-hardware
+  (name h-dsa0)
+  (comment "dma sfr addr 110")
+  (attrs all-isas)
+  (type register USI)
+)
+(define-hardware
+  (name h-dsa1)
+  (comment "dma sfr addr 111")
+  (attrs all-isas)
+  (type register USI)
+)
+
+;-------------------------------------------------------------
+; Condition code operand hardware
+;-------------------------------------------------------------
+
+(define-hardware
+  (name h-cond16)
+  (comment "condition code hardware for m16c")
+  (attrs m16c-isa MACH16)
+  (type immediate UQI)
+  (values keyword ""
+         (("geu" #x00) ("c"  #x00)
+          ("gtu" #x01)
+          ("eq"  #x02) ("z"  #x02)
+          ("n"   #x03)
+          ("le"  #x04)
+          ("o"   #x05)
+          ("ge"  #x06)
+          ("ltu" #xf8) ("nc" #xf8)
+          ("leu" #xf9)
+          ("ne"  #xfa) ("nz" #xfa)
+          ("pz"  #xfb)
+          ("gt"  #xfc)
+          ("no"  #xfd)
+          ("lt"  #xfe)
+         )
+  )
+)
+(define-hardware
+  (name h-cond16c)
+  (comment "condition code hardware for m16c")
+  (attrs m16c-isa MACH16)
+  (type immediate UQI)
+  (values keyword ""
+         (("geu" #x00) ("c"  #x00)
+          ("gtu" #x01)
+          ("eq"  #x02) ("z"  #x02)
+          ("n"   #x03)
+          ("ltu" #x04) ("nc" #x04)
+          ("leu" #x05)
+          ("ne"  #x06) ("nz" #x06)
+          ("pz"  #x07)
+          ("le"  #x08)
+          ("o"   #x09)
+          ("ge"  #x0a)
+          ("gt"  #x0c)
+          ("no"  #x0d)
+          ("lt"  #x0e)
+         )
+  )
+)
+(define-hardware
+  (name h-cond16j)
+  (comment "condition code hardware for m16c")
+  (attrs m16c-isa MACH16)
+  (type immediate UQI)
+  (values keyword ""
+         (("le"  #x08)
+          ("o"   #x09)
+          ("ge"  #x0a)
+          ("gt"  #x0c)
+          ("no"  #x0d)
+          ("lt"  #x0e)
+         )
+  )
+)
+(define-hardware
+  (name h-cond16j-5)
+  (comment "condition code hardware for m16c")
+  (attrs m16c-isa MACH16)
+  (type immediate UQI)
+  (values keyword ""
+         (("geu" #x00) ("c"  #x00)
+          ("gtu" #x01)
+          ("eq"  #x02) ("z"  #x02)
+          ("n"   #x03)
+          ("ltu" #x04) ("nc" #x04)
+          ("leu" #x05)
+          ("ne"  #x06) ("nz" #x06)
+          ("pz"  #x07)
+         )
+  )
+)
+
+(define-hardware
+  (name h-cond32)
+  (comment "condition code hardware for m32c")
+  (attrs m32c-isa MACH32)
+  (type immediate UQI)
+  (values keyword ""
+         (("ltu" #x00) ("nc" #x00)
+          ("leu" #x01)
+          ("ne"  #x02) ("nz" #x02)
+          ("pz"  #x03)
+          ("no"  #x04)
+          ("gt"  #x05)
+          ("ge"  #x06)
+          ("geu" #x08) ("c"  #x08)
+          ("gtu" #x09)
+          ("eq"  #x0a) ("z"  #x0a)
+          ("n"   #x0b)
+          ("o"   #x0c)
+          ("le"  #x0d)
+          ("lt"  #x0e)
+         )
+  )
+)
+
+(define-hardware
+  (name h-cr1-32)
+  (comment "control registers")
+  (attrs m32c-isa MACH32)
+  (type immediate UQI)
+  (values keyword "" (("dct0" 0) ("dct1" 1) ("flg" 2) ("svf" 3) ("drc0" 4)
+                       ("drc1" 5) ("dmd0" 6) ("dmd1" 7))))
+(define-hardware
+  (name h-cr2-32)
+  (comment "control registers")
+  (attrs m32c-isa MACH32)
+  (type immediate UQI)
+  (values keyword "" (("intb" 0) ("sp" 1) ("sb" 2) ("fb" 3) ("svp" 4)
+                       ("vct" 5) ("isp" 7))))
+
+(define-hardware
+  (name h-cr3-32)
+  (comment "control registers")
+  (attrs m32c-isa MACH32)
+  (type immediate UQI)
+  (values keyword "" (("dma0" 2) ("dma1" 3) ("dra0" 4)
+                       ("dra1" 5) ("dsa0" 6) ("dsa1" 7))))
+(define-hardware
+  (name h-cr-16)
+  (comment "control registers")
+  (attrs m16c-isa MACH16)
+  (type immediate UQI)
+  (values keyword "" (("intbl" 1) ("intbh" 2) ("flg" 3) ("isp" 4)
+                       ("sp" 5) ("sb" 6) ("fb" 7))))
+
+(define-hardware
+  (name h-flags)
+  (comment "flag hardware for m32c")
+  (attrs all-isas)
+  (type immediate UQI)
+  (values keyword ""
+         (("c" #x0)
+          ("d" #x1)
+          ("z"  #x2)
+          ("s"  #x3)
+          ("b"  #x4)
+          ("o"  #x5)
+          ("i"  #x6)
+          ("u"  #x7)
+         )
+  )
+)
+
+;-------------------------------------------------------------
+; Misc helper hardware
+;-------------------------------------------------------------
+
+(define-hardware
+  (name h-shimm)
+  (comment "shift immediate")
+  (attrs all-isas)
+  (type immediate (INT 4))
+  (values keyword "" (("1" 0) ("2" 1) ("3" 2) ("4" 3) ("5" 4) ("6" 5) ("7" 6)
+                      ("8" 7) ("-1" -8) ("-2" -7) ("-3" -6) ("-4" -5) ("-5" -4)
+                      ("-6" -3) ("-7" -2) ("-8" -1)
+                      )))
+(define-hardware
+  (name h-bit-index)
+  (comment "bit index for the next insn")
+  (attrs m32c-isa MACH32)
+  (type register UHI)
+)
+(define-hardware
+  (name h-src-index)
+  (comment "source index for the next insn")
+  (attrs m32c-isa MACH32)
+  (type register UHI)
+)
+(define-hardware
+  (name h-dst-index)
+  (comment "destination index for the next insn")
+  (attrs m32c-isa MACH32)
+  (type register UHI)
+)
+(define-hardware
+  (name h-src-indirect)
+  (comment "indirect src for the next insn")
+  (attrs all-isas)
+  (type register UHI)
+)
+(define-hardware
+  (name h-dst-indirect)
+  (comment "indirect dst for the next insn")
+  (attrs all-isas)
+  (type register UHI)
+)
+(define-hardware
+  (name h-none)
+  (comment "for storing unused values")
+  (attrs m32c-isa MACH32)
+  (type register SI)
+)
+\f
+;=============================================================
+; Operands
+;-------------------------------------------------------------
+; Source Registers
+;-------------------------------------------------------------
+
+(dnop Src16RnQI  "general register QI view" (MACH16 m16c-isa) h-gr-QI f-src16-rn)
+(dnop Src16RnHI  "general register QH view" (MACH16 m16c-isa) h-gr-HI f-src16-rn)
+
+(dnop Src32RnUnprefixedQI  "general register QI view" (MACH32 m32c-isa) h-gr-QI f-src32-rn-unprefixed-QI)
+(dnop Src32RnUnprefixedHI  "general register HI view" (MACH32 m32c-isa) h-gr-HI f-src32-rn-unprefixed-HI)
+(dnop Src32RnUnprefixedSI  "general register SI view" (MACH32 m32c-isa) h-gr-SI f-src32-rn-unprefixed-SI)
+
+(dnop Src32RnPrefixedQI  "general register QI view" (MACH32 m32c-isa) h-gr-QI f-src32-rn-prefixed-QI)
+(dnop Src32RnPrefixedHI  "general register HI view" (MACH32 m32c-isa) h-gr-HI f-src32-rn-prefixed-HI)
+(dnop Src32RnPrefixedSI  "general register SI view" (MACH32 m32c-isa) h-gr-SI f-src32-rn-prefixed-SI)
+
+(dnop Src16An    "address register"         (MACH16 m16c-isa) h-ar    f-src16-an)
+(dnop Src16AnQI  "address register QI view" (MACH16 m16c-isa) h-ar-QI f-src16-an)
+(dnop Src16AnHI  "address register HI view" (MACH16 m16c-isa) h-ar-HI f-src16-an)
+
+(dnop Src32AnUnprefixed    "address register"         (MACH32 m32c-isa) h-ar    f-src32-an-unprefixed)
+(dnop Src32AnUnprefixedQI  "address register QI view" (MACH32 m32c-isa) h-ar-QI f-src32-an-unprefixed)
+(dnop Src32AnUnprefixedHI  "address register HI view" (MACH32 m32c-isa) h-ar-HI f-src32-an-unprefixed)
+(dnop Src32AnUnprefixedSI  "address register SI view" (MACH32 m32c-isa) h-ar    f-src32-an-unprefixed)
+
+(dnop Src32AnPrefixed    "address register"         (MACH32 m32c-isa) h-ar    f-src32-an-prefixed)
+(dnop Src32AnPrefixedQI  "address register QI view" (MACH32 m32c-isa) h-ar-QI f-src32-an-prefixed)
+(dnop Src32AnPrefixedHI  "address register HI view" (MACH32 m32c-isa) h-ar-HI f-src32-an-prefixed)
+(dnop Src32AnPrefixedSI  "address register SI view" (MACH32 m32c-isa) h-ar    f-src32-an-prefixed)
+
+; Destination Registers
+;
+(dnop Dst16RnQI  "general register QI view" (MACH16 m16c-isa) h-gr-QI f-dst16-rn)
+(dnop Dst16RnHI  "general register HI view" (MACH16 m16c-isa) h-gr-HI f-dst16-rn)
+(dnop Dst16RnSI  "general register SI view" (MACH16 m16c-isa) h-gr-SI f-dst16-rn)
+(dnop Dst16RnExtQI "general register QI/HI view for 'ext' insns" (MACH16 m16c-isa) h-gr-ext-QI f-dst16-rn-ext)
+
+(dnop Dst32R0QI-S "general register QI view" (MACH32 m32c-isa) h-r0l f-nil)
+(dnop Dst32R0HI-S "general register HI view" (MACH32 m32c-isa) h-r0  f-nil)
+
+(dnop Dst32RnUnprefixedQI  "general register QI view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-unprefixed-QI)
+(dnop Dst32RnUnprefixedHI  "general register HI view" (MACH32 m32c-isa) h-gr-HI f-dst32-rn-unprefixed-HI)
+(dnop Dst32RnUnprefixedSI  "general register SI view" (MACH32 m32c-isa) h-gr-SI f-dst32-rn-unprefixed-SI)
+(dnop Dst32RnExtUnprefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-ext-QI f-dst32-rn-ext-unprefixed)
+(dnop Dst32RnExtUnprefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-ext-HI f-dst32-rn-ext-unprefixed)
+
+(dnop Dst32RnPrefixedQI    "general register QI view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-prefixed-QI)
+(dnop Dst32RnPrefixedHI    "general register HI view" (MACH32 m32c-isa) h-gr-HI f-dst32-rn-prefixed-HI)
+(dnop Dst32RnPrefixedSI    "general register SI view" (MACH32 m32c-isa) h-gr-SI f-dst32-rn-prefixed-SI)
+
+(dnop Dst16RnQI-S "general register QI view" (MACH16 m16c-isa) h-r0l-r0h f-dst16-rn-QI-s)
+
+(dnop Dst16AnQI-S "address register QI view" (MACH16 m16c-isa) h-ar-QI f-dst16-rn-QI-s)
+
+(dnop Bit16Rn  "general register bit view" (MACH16 m16c-isa) h-gr-HI f-dst16-rn)
+
+(dnop Bit32RnPrefixed "general register bit view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-prefixed-QI)
+(dnop Bit32RnUnprefixed "general register bit view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-unprefixed-QI)
+
+(dnop R0   "r0"   (all-isas) h-r0   f-nil)
+(dnop R1   "r1"   (all-isas) h-r1   f-nil)
+(dnop R2   "r2"   (all-isas) h-r2   f-nil)
+(dnop R3   "r3"   (all-isas) h-r3   f-nil)
+(dnop R0l  "r0l"  (all-isas) h-r0l  f-nil)
+(dnop R0h  "r0h"  (all-isas) h-r0h  f-nil)
+(dnop R2R0 "r2r0" (all-isas) h-r2r0 f-nil)
+(dnop R3R1 "r3r1" (all-isas) h-r3r1 f-nil)
+(dnop R1R2R0 "r1r2r0" (all-isas) h-r1r2r0 f-nil)
+
+(dnop Dst16An    "address register"         (MACH16 m16c-isa) h-ar    f-dst16-an)
+(dnop Dst16AnQI  "address register QI view" (MACH16 m16c-isa) h-ar-QI f-dst16-an)
+(dnop Dst16AnHI  "address register HI view" (MACH16 m16c-isa) h-ar-HI f-dst16-an)
+(dnop Dst16AnSI  "address register SI view" (MACH16 m16c-isa) h-ar-SI f-dst16-an)
+(dnop Dst16An-S  "address register HI view" (MACH16 m16c-isa) h-ar-HI f-dst16-an-s)
+
+(dnop Dst32AnUnprefixed   "address register"         (MACH32 m32c-isa) h-ar    f-dst32-an-unprefixed)
+(dnop Dst32AnUnprefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-dst32-an-unprefixed)
+(dnop Dst32AnUnprefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-dst32-an-unprefixed)
+(dnop Dst32AnUnprefixedSI "address register SI view" (MACH32 m32c-isa) h-ar    f-dst32-an-unprefixed)
+
+(dnop Dst32AnExtUnprefixed "address register"        (MACH32 m32c-isa) h-ar    f-dst32-an-unprefixed)
+
+(dnop Dst32AnPrefixed     "address register"         (MACH32 m32c-isa) h-ar    f-dst32-an-prefixed)
+(dnop Dst32AnPrefixedQI   "address register QI view" (MACH32 m32c-isa) h-ar-QI f-dst32-an-prefixed)
+(dnop Dst32AnPrefixedHI   "address register HI view" (MACH32 m32c-isa) h-ar-HI f-dst32-an-prefixed)
+(dnop Dst32AnPrefixedSI   "address register SI view" (MACH32 m32c-isa) h-ar    f-dst32-an-prefixed)
+
+(dnop Bit16An  "address register bit view" (MACH16 m16c-isa) h-ar f-dst16-an)
+
+(dnop Bit32AnPrefixed "address register bit" (MACH32 m32c-isa) h-ar f-dst32-an-prefixed)
+(dnop Bit32AnUnprefixed "address register bit" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed)
+
+(dnop A0  "a0"   (all-isas) h-a0  f-nil)
+(dnop A1  "a1"   (all-isas) h-a1  f-nil)
+
+(dnop sb  "SB register" (all-isas SEM-ONLY) h-sb f-nil)
+(dnop fb  "FB register" (all-isas SEM-ONLY) h-fb f-nil)
+(dnop sp  "SP register" (all-isas SEM-ONLY) h-sp f-nil)
+
+(define-full-operand SrcDst16-r0l-r0h-S-normal "r0l/r0h pair" (MACH16 m16c-isa)
+  h-sint DFLT f-5-1
+  ((parse "r0l_r0h") (print "r0l_r0h")) () ()
+)
+
+(define-full-operand Regsetpop "popm regset" (all-isas) h-uint
+   DFLT f-8-8 ((parse "pop_regset") (print "pop_regset")) () ())
+(define-full-operand Regsetpush "pushm regset" (all-isas) h-uint
+   DFLT f-8-8 ((parse "push_regset") (print "push_regset")) () ())
+
+(dnop Rn16-push-S "r0[lh]" (MACH16 m16c-isa) h-gr-QI f-4-1)
+(dnop An16-push-S "a[01]"  (MACH16 m16c-isa) h-ar-HI f-4-1)
+
+;-------------------------------------------------------------
+; Offsets and absolutes
+;-------------------------------------------------------------
+
+(define-full-operand Dsp-8-u6 "unsigned 6 bit displacement at offset 8 bits" (all-isas)
+  h-uint DFLT f-dsp-8-u6
+  ((parse "unsigned6")) () ()
+)
+(define-full-operand Dsp-8-u8 "unsigned 8 bit displacement at offset 8 bits" (all-isas)
+  h-uint DFLT f-dsp-8-u8
+  ((parse "unsigned8")) () ()
+)
+(define-full-operand Dsp-8-u16 "unsigned 16 bit displacement at offset 8 bits" (all-isas)
+  h-uint DFLT f-dsp-8-u16
+  ((parse "unsigned16")) () ()
+)
+(define-full-operand Dsp-8-s8 "signed 8 bit displacement at offset 8 bits" (all-isas)
+  h-sint DFLT f-dsp-8-s8
+  ((parse "signed8")) () ()
+)
+(define-full-operand Dsp-8-s24 "signed 24 bit displacement at offset 8 bits" (all-isas)
+  h-sint DFLT f-dsp-8-s24
+  ((parse "signed24")) () ()
+)
+(define-full-operand Dsp-8-u24 "unsigned 24 bit displacement at offset 8 bits" (all-isas)
+  h-uint DFLT f-dsp-8-u24
+  ((parse "unsigned24")) () ()
+)
+(define-full-operand Dsp-10-u6 "unsigned 6 bit displacement at offset 10 bits" (all-isas)
+  h-uint DFLT f-dsp-10-u6
+  ((parse "unsigned6")) () ()
+)
+(define-full-operand Dsp-16-u8 "unsigned 8 bit displacement at offset 16 bits" (all-isas)
+  h-uint DFLT f-dsp-16-u8
+  ((parse "unsigned8")) () ()
+)
+(define-full-operand Dsp-16-u16 "unsigned 16 bit displacement at offset 16 bits" (all-isas)
+  h-uint DFLT f-dsp-16-u16
+  ((parse "unsigned16")) () ()
+)
+(define-full-operand Dsp-16-u20 "unsigned 20 bit displacement at offset 16 bits" (all-isas)
+  h-uint DFLT f-dsp-16-u24
+  ((parse "unsigned20")) () ()
+)
+(define-full-operand Dsp-16-u24 "unsigned 24 bit displacement at offset 16 bits" (all-isas)
+  h-uint DFLT f-dsp-16-u24
+  ((parse "unsigned24")) () ()
+)
+(define-full-operand Dsp-16-s8 "signed 8 bit displacement at offset 16 bits" (all-isas)
+  h-sint DFLT f-dsp-16-s8
+  ((parse "signed8")) () ()
+)
+(define-full-operand Dsp-16-s16 "signed 16 bit displacement at offset 16 bits" (all-isas)
+  h-sint DFLT f-dsp-16-s16
+  ((parse "signed16")) () ()
+)
+(define-full-operand Dsp-24-u8 "unsigned 8 bit displacement at offset 24 bits" (all-isas)
+  h-uint DFLT f-dsp-24-u8
+  ((parse "unsigned8")) () ()
+)
+(define-full-operand Dsp-24-u16 "unsigned 16 bit displacement at offset 24 bits" (all-isas)
+  h-uint DFLT f-dsp-24-u16
+  ((parse "unsigned16")) () ()
+)
+(define-full-operand Dsp-24-u20 "unsigned 20 bit displacement at offset 24 bits" (all-isas)
+  h-uint DFLT f-dsp-24-u24
+  ((parse "unsigned20")) () ()
+)
+(define-full-operand Dsp-24-u24 "unsigned 24 bit displacement at offset 24 bits" (all-isas)
+  h-uint DFLT f-dsp-24-u24
+  ((parse "unsigned24")) () ()
+)
+(define-full-operand Dsp-24-s8 "signed 8 bit displacement at offset 24 bits" (all-isas)
+  h-sint DFLT f-dsp-24-s8
+  ((parse "signed8")) () ()
+)
+(define-full-operand Dsp-24-s16 "signed 16 bit displacement at offset 24 bits" (all-isas)
+  h-sint DFLT f-dsp-24-s16
+  ((parse "signed16")) () ()
+)
+(define-full-operand Dsp-32-u8 "unsigned 8 bit displacement at offset 32 bits" (all-isas)
+  h-uint DFLT f-dsp-32-u8
+  ((parse "unsigned8")) () ()
+)
+(define-full-operand Dsp-32-u16 "unsigned 16 bit displacement at offset 32 bits" (all-isas)
+  h-uint DFLT f-dsp-32-u16
+  ((parse "unsigned16")) () ()
+)
+(define-full-operand Dsp-32-u24 "unsigned 24 bit displacement at offset 32 bits" (all-isas)
+  h-uint DFLT f-dsp-32-u24
+  ((parse "unsigned24")) () ()
+)
+(define-full-operand Dsp-32-u20 "unsigned 20 bit displacement at offset 32 bits" (all-isas)
+  h-uint DFLT f-dsp-32-u24
+  ((parse "unsigned20")) () ()
+)
+(define-full-operand Dsp-32-s8 "signed 8 bit displacement at offset 32 bits" (all-isas)
+  h-sint DFLT f-dsp-32-s8
+  ((parse "signed8")) () ()
+)
+(define-full-operand Dsp-32-s16 "signed 16 bit displacement at offset 32 bits" (all-isas)
+  h-sint DFLT f-dsp-32-s16
+  ((parse "signed16")) () ()
+)
+(define-full-operand Dsp-40-u8 "unsigned 8 bit displacement at offset 40 bits" (all-isas)
+  h-uint DFLT f-dsp-40-u8
+  ((parse "unsigned8")) () ()
+)
+(define-full-operand Dsp-40-s8 "signed 8 bit displacement at offset 40 bits" (all-isas)
+  h-sint DFLT f-dsp-40-s8
+  ((parse "signed8")) () ()
+)
+(define-full-operand Dsp-40-u16 "unsigned 16 bit displacement at offset 40 bits" (all-isas)
+  h-uint DFLT f-dsp-40-u16
+  ((parse "unsigned16")) () ()
+)
+(define-full-operand Dsp-40-s16 "signed 16 bit displacement at offset 40 bits" (all-isas)
+  h-sint DFLT f-dsp-40-s16
+  ((parse "signed16")) () ()
+)
+(define-full-operand Dsp-40-u20 "unsigned 20 bit displacement at offset 40 bits" (all-isas)
+  h-uint DFLT f-dsp-40-u20
+  ((parse "unsigned20")) () ()
+)
+(define-full-operand Dsp-40-u24 "unsigned 24 bit displacement at offset 40 bits" (all-isas)
+  h-uint DFLT f-dsp-40-u24
+  ((parse "unsigned24")) () ()
+)
+(define-full-operand Dsp-48-u8 "unsigned 8 bit displacement at offset 48 bits" (all-isas)
+  h-uint DFLT f-dsp-48-u8
+  ((parse "unsigned8")) () ()
+)
+(define-full-operand Dsp-48-s8 "signed 8 bit displacement at offset 48 bits" (all-isas)
+  h-sint DFLT f-dsp-48-s8
+  ((parse "signed8")) () ()
+)
+(define-full-operand Dsp-48-u16 "unsigned 16 bit displacement at offset 48 bits" (all-isas)
+  h-uint DFLT f-dsp-48-u16
+  ((parse "unsigned16")) () ()
+)
+(define-full-operand Dsp-48-s16 "signed 16 bit displacement at offset 48 bits" (all-isas)
+  h-sint DFLT f-dsp-48-s16
+  ((parse "signed16")) () ()
+)
+(define-full-operand Dsp-48-u20 "unsigned 24 bit displacement at offset 40 bits" (all-isas)
+  h-uint DFLT f-dsp-48-u20
+  ((parse "unsigned24")) () ()
+)
+(define-full-operand Dsp-48-u24 "unsigned 24 bit displacement at offset 48 bits" (all-isas)
+  h-uint DFLT f-dsp-48-u24
+  ((parse "unsigned24")) () ()
+)
+
+(define-full-operand Imm-8-s4 "signed 4 bit immediate at offset 8 bits" (all-isas)
+  h-sint DFLT f-imm-8-s4
+  ((parse "signed4")) () ()
+)
+(define-full-operand Imm-8-s4n "negated 4 bit immediate at offset 8 bits" (all-isas)
+  h-sint DFLT f-imm-8-s4
+  ((parse "signed4n") (print "signed4n")) () ()
+)
+(define-full-operand Imm-sh-8-s4 "signed 4 bit shift immediate at offset 8 bits" (all-isas)
+  h-shimm DFLT f-imm-8-s4
+  () () ()
+)
+(define-full-operand Imm-8-QI "signed 8 bit immediate at offset 8 bits" (all-isas)
+  h-sint DFLT f-dsp-8-s8
+  ((parse "signed8")) () ()
+)
+(define-full-operand Imm-8-HI "signed 16 bit immediate at offset 8 bits" (all-isas)
+  h-sint DFLT f-dsp-8-s16
+  ((parse "signed16")) () ()
+)
+(define-full-operand Imm-12-s4 "signed 4 bit immediate at offset 12 bits" (all-isas)
+  h-sint DFLT f-imm-12-s4
+  ((parse "signed4")) () ()
+)
+(define-full-operand Imm-12-s4n "negated 4 bit immediate at offset 12 bits" (all-isas)
+  h-sint DFLT f-imm-12-s4
+  ((parse "signed4n") (print "signed4n")) () ()
+)
+(define-full-operand Imm-sh-12-s4 "signed 4 bit shift immediate at offset 12 bits" (all-isas)
+  h-shimm DFLT f-imm-12-s4
+  () () ()
+)
+(define-full-operand Imm-13-u3 "signed 3 bit immediate at offset 13 bits" (all-isas)
+  h-sint DFLT f-imm-13-u3
+  ((parse "signed4")) () ()
+)
+(define-full-operand Imm-20-s4 "signed 4 bit immediate at offset 20 bits" (all-isas)
+  h-sint DFLT f-imm-20-s4
+  ((parse "signed4")) () ()
+)
+(define-full-operand Imm-sh-20-s4 "signed 4 bit shift immediate at offset 12 bits" (all-isas)
+  h-shimm DFLT f-imm-20-s4
+  () () ()
+)
+(define-full-operand Imm-16-QI "signed 8 bit immediate at offset 16 bits" (all-isas)
+  h-sint DFLT f-dsp-16-s8
+  ((parse "signed8")) () ()
+)
+(define-full-operand Imm-16-HI "signed 16 bit immediate at offset 16 bits" (all-isas)
+  h-sint DFLT f-dsp-16-s16
+  ((parse "signed16")) () ()
+)
+(define-full-operand Imm-16-SI "signed 32 bit immediate at offset 16 bits" (all-isas)
+  h-sint DFLT f-dsp-16-s32
+  ((parse "signed32")) () ()
+)
+(define-full-operand Imm-24-QI "signed 8 bit immediate at offset 24 bits" (all-isas)
+  h-sint DFLT f-dsp-24-s8
+  ((parse "signed8")) () ()
+)
+(define-full-operand Imm-24-HI "signed 16 bit immediate at offset 24 bits" (all-isas)
+  h-sint DFLT f-dsp-24-s16
+  ((parse "signed16")) () ()
+)
+(define-full-operand Imm-24-SI "signed 32 bit immediate at offset 24 bits" (all-isas)
+  h-sint DFLT f-dsp-24-s32
+  ((parse "signed32")) () ()
+)
+(define-full-operand Imm-32-QI "signed 8 bit immediate at offset 32 bits" (all-isas)
+  h-sint DFLT f-dsp-32-s8
+  ((parse "signed8")) () ()
+)
+(define-full-operand Imm-32-SI "signed 32 bit immediate at offset 32 bits" (all-isas)
+  h-sint DFLT f-dsp-32-s32
+  ((parse "signed32")) () ()
+)
+(define-full-operand Imm-32-HI "signed 16 bit immediate at offset 32 bits" (all-isas)
+  h-sint DFLT f-dsp-32-s16
+  ((parse "signed16")) () ()
+)
+(define-full-operand Imm-40-QI "signed 8 bit immediate at offset 40 bits" (all-isas)
+  h-sint DFLT f-dsp-40-s8
+  ((parse "signed8")) () ()
+)
+(define-full-operand Imm-40-HI "signed 16 bit immediate at offset 40 bits" (all-isas)
+  h-sint DFLT f-dsp-40-s16
+  ((parse "signed16")) () ()
+)
+(define-full-operand Imm-40-SI "signed 32 bit immediate at offset 40 bits" (all-isas)
+  h-sint DFLT f-dsp-40-s32
+  ((parse "signed32")) () ()
+)
+(define-full-operand Imm-48-QI "signed 8 bit immediate at offset 48 bits" (all-isas)
+  h-sint DFLT f-dsp-48-s8
+  ((parse "signed8")) () ()
+)
+(define-full-operand Imm-48-HI "signed 16 bit immediate at offset 48 bits" (all-isas)
+  h-sint DFLT f-dsp-48-s16
+  ((parse "signed16")) () ()
+)
+(define-full-operand Imm-48-SI "signed 32 bit immediate at offset 48 bits" (all-isas)
+  h-sint DFLT f-dsp-48-s32
+  ((parse "signed32")) () ()
+)
+(define-full-operand Imm-56-QI "signed 8 bit immediate at offset 56 bits" (all-isas)
+  h-sint DFLT f-dsp-56-s8
+  ((parse "signed8")) () ()
+)
+(define-full-operand Imm-56-HI "signed 16 bit immediate at offset 56 bits" (all-isas)
+  h-sint DFLT f-dsp-56-s16
+  ((parse "signed16")) () ()
+)
+(define-full-operand Imm-64-HI "signed 16 bit immediate at offset 64 bits" (all-isas)
+  h-sint DFLT f-dsp-64-s16
+  ((parse "signed16")) () ()
+)
+(define-full-operand Imm1-S "signed 1 bit immediate for short format binary insns" (m32c-isa)
+  h-sint DFLT f-imm1-S
+  ((parse "imm1_S")) () ()
+)
+(define-full-operand Imm3-S "signed 3 bit immediate for short format binary insns" (m32c-isa)
+  h-sint DFLT f-imm3-S
+  ((parse "imm3_S")) () ()
+)
+(define-full-operand Bit3-S "3 bit bit number" (m32c-isa)
+  h-sint DFLT f-imm3-S
+  ((parse "bit3_S")) () ()
+)
+
+;-------------------------------------------------------------
+; Bit numbers
+;-------------------------------------------------------------
+
+(define-full-operand Bitno16R "bit number for indexing registers" (m16c-isa)
+  h-uint DFLT f-dsp-16-u8
+  ((parse "Bitno16R")) () ()
+)
+(dnop Bitno32Prefixed "bit number for indexing objects" (m32c-isa) h-uint f-bitno32-prefixed)
+(dnop Bitno32Unprefixed "bit number for indexing objects" (m32c-isa) h-uint f-bitno32-unprefixed)
+
+(define-full-operand BitBase16-16-u8 "unsigned bit,base:8 at offset 16for m16c" (m16c-isa)
+  h-uint DFLT f-dsp-16-u8
+  ((parse "unsigned_bitbase8") (print "unsigned_bitbase")) () ()
+)
+(define-full-operand BitBase16-16-s8 "signed bit,base:8 at offset 16for m16c" (m16c-isa)
+  h-sint DFLT f-dsp-16-s8
+  ((parse "signed_bitbase8") (print "signed_bitbase")) () ()
+)
+(define-full-operand BitBase16-16-u16 "unsigned bit,base:16 at offset 16 for m16c" (m16c-isa)
+  h-uint DFLT f-dsp-16-u16
+  ((parse "unsigned_bitbase16") (print "unsigned_bitbase")) () ()
+)
+(define-full-operand BitBase16-8-u11-S "signed bit,base:11 at offset 16 for m16c" (m16c-isa)
+  h-uint DFLT f-bitbase16-u11-S
+  ((parse "unsigned_bitbase11") (print "unsigned_bitbase")) () ()
+)
+
+(define-full-operand BitBase32-16-u11-Unprefixed "unsigned bit,base:11 at offset 16 for m32c" (m32c-isa)
+  h-uint DFLT f-bitbase32-16-u11-unprefixed
+  ((parse "unsigned_bitbase11") (print "unsigned_bitbase")) () ()
+)
+(define-full-operand BitBase32-16-s11-Unprefixed "signed bit,base:11 at offset 16 for m32c" (m32c-isa)
+  h-sint DFLT f-bitbase32-16-s11-unprefixed
+  ((parse "signed_bitbase11") (print "signed_bitbase")) () ()
+)
+(define-full-operand BitBase32-16-u19-Unprefixed "unsigned bit,base:19 at offset 16 for m32c" (m32c-isa)
+  h-uint DFLT f-bitbase32-16-u19-unprefixed
+  ((parse "unsigned_bitbase19") (print "unsigned_bitbase")) () ()
+)
+(define-full-operand BitBase32-16-s19-Unprefixed "signed bit,base:19 at offset 16 for m32c" (m32c-isa)
+  h-sint DFLT f-bitbase32-16-s19-unprefixed
+  ((parse "signed_bitbase19") (print "signed_bitbase")) () ()
+)
+(define-full-operand BitBase32-16-u27-Unprefixed "unsigned bit,base:27 at offset 16 for m32c" (m32c-isa)
+  h-uint DFLT f-bitbase32-16-u27-unprefixed
+  ((parse "unsigned_bitbase27") (print "unsigned_bitbase")) () ()
+)
+(define-full-operand BitBase32-24-u11-Prefixed "unsigned bit,base:11 at offset 24 for m32c" (m32c-isa)
+  h-uint DFLT f-bitbase32-24-u11-prefixed
+  ((parse "unsigned_bitbase11") (print "unsigned_bitbase")) () ()
+)
+(define-full-operand BitBase32-24-s11-Prefixed "signed bit,base:11 at offset 24 for m32c" (m32c-isa)
+  h-sint DFLT f-bitbase32-24-s11-prefixed
+  ((parse "signed_bitbase11") (print "signed_bitbase")) () ()
+)
+(define-full-operand BitBase32-24-u19-Prefixed "unsigned bit,base:19 at offset 24 for m32c" (m32c-isa)
+  h-uint DFLT f-bitbase32-24-u19-prefixed
+  ((parse "unsigned_bitbase19") (print "unsigned_bitbase")) () ()
+)
+(define-full-operand BitBase32-24-s19-Prefixed "signed bit,base:19 at offset 24 for m32c" (m32c-isa)
+  h-sint DFLT f-bitbase32-24-s19-prefixed
+  ((parse "signed_bitbase19") (print "signed_bitbase")) () ()
+)
+(define-full-operand BitBase32-24-u27-Prefixed "unsigned bit,base:27 at offset 24 for m32c" (m32c-isa)
+  h-uint DFLT f-bitbase32-24-u27-prefixed
+  ((parse "unsigned_bitbase27") (print "unsigned_bitbase")) () ()
+)
+;-------------------------------------------------------------
+; Labels
+;-------------------------------------------------------------
+
+(define-full-operand Lab-5-3 "3 bit label" (all-isas RELAX)
+  h-iaddr DFLT f-lab-5-3
+  ((parse "lab_5_3")) () () )
+
+(define-full-operand Lab32-jmp-s "3 bit label" (all-isas RELAX)
+  h-iaddr DFLT f-lab32-jmp-s
+  ((parse "lab_5_3")) () () )
+
+(dnop Lab-8-8     "8 bit label"  (all-isas RELAX) h-iaddr f-lab-8-8)
+(dnop Lab-8-16    "16 bit label" (all-isas RELAX) h-iaddr f-lab-8-16)
+(dnop Lab-8-24    "24 bit label" (all-isas RELAX) h-iaddr f-lab-8-24)
+(dnop Lab-16-8    "8 bit label"  (all-isas RELAX) h-iaddr f-lab-16-8)
+(dnop Lab-24-8    "8 bit label"  (all-isas RELAX) h-iaddr f-lab-24-8)
+(dnop Lab-32-8    "8 bit label"  (all-isas RELAX) h-iaddr f-lab-32-8)
+(dnop Lab-40-8    "8 bit label"  (all-isas RELAX) h-iaddr f-lab-40-8)
+
+;-------------------------------------------------------------
+; Condition code bits
+;-------------------------------------------------------------
+
+(dnop sbit "negative    bit"      (SEM-ONLY all-isas) h-sbit f-nil)
+(dnop obit "overflow    bit"      (SEM-ONLY all-isas) h-obit f-nil)
+(dnop zbit "zero        bit"      (SEM-ONLY all-isas) h-zbit f-nil)
+(dnop cbit "carry       bit"      (SEM-ONLY all-isas) h-cbit f-nil)
+(dnop ubit "stack ptr select bit" (SEM-ONLY all-isas) h-ubit f-nil)
+(dnop ibit "interrupt enable bit" (SEM-ONLY all-isas) h-ibit f-nil)
+(dnop bbit "reg bank select bit"  (SEM-ONLY all-isas) h-bbit f-nil)
+(dnop dbit "debug       bit"      (SEM-ONLY all-isas) h-dbit f-nil)
+
+;-------------------------------------------------------------
+; Condition operands
+;-------------------------------------------------------------
+
+(define-pmacro (cond-operand mach offset)
+  (dnop (.sym cond mach - offset) "condition" ((.sym m mach c-isa)) (.sym h-cond mach) (.sym f-dsp- offset -u8))
+)
+
+(cond-operand 16 16)
+(cond-operand 16 24)
+(cond-operand 16 32)
+(cond-operand 32 16)
+(cond-operand 32 24)
+(cond-operand 32 32)
+(cond-operand 32 40)
+
+(dnop cond16c  "condition" (m16c-isa) h-cond16c f-cond16)
+(dnop cond16j  "condition" (m16c-isa) h-cond16j f-cond16)
+(dnop cond16j5 "condition" (m16c-isa) h-cond16j-5 f-cond16j-5)
+(dnop cond32   "condition" (m32c-isa) h-cond32  f-cond32)
+(dnop cond32j  "condition" (m32c-isa) h-cond32  f-cond32j)
+(dnop sccond32 "scCND condition" (m32c-isa) h-cond32 f-cond16)
+(dnop flags16  "flags" (m16c-isa) h-flags f-9-3)
+(dnop flags32  "flags" (m32c-isa) h-flags f-13-3)
+(dnop cr16     "control" (m16c-isa) h-cr-16 f-9-3)
+(dnop cr1-Unprefixed-32   "control" (m32c-isa) h-cr1-32 f-13-3)
+(dnop cr1-Prefixed-32   "control" (m32c-isa) h-cr1-32 f-21-3)
+(dnop cr2-32   "control" (m32c-isa) h-cr2-32 f-13-3)
+(dnop cr3-Unprefixed-32   "control" (m32c-isa) h-cr3-32 f-13-3)
+(dnop cr3-Prefixed-32   "control" (m32c-isa) h-cr3-32 f-21-3)
+
+;-------------------------------------------------------------
+; Suffixes
+;-------------------------------------------------------------
+
+(define-full-operand Z "Suffix for zero format insns" (all-isas)
+  h-sint DFLT f-nil
+  ((parse "Z") (print "Z")) () ()
+)
+(define-full-operand S "Suffix for short format insns" (all-isas)
+  h-sint DFLT f-nil
+  ((parse "S") (print "S")) () ()
+)
+(define-full-operand Q "Suffix for quick format insns" (all-isas)
+  h-sint DFLT f-nil
+  ((parse "Q") (print "Q")) () ()
+)
+(define-full-operand G "Suffix for general format insns" (all-isas)
+  h-sint DFLT f-nil
+  ((parse "G") (print "G")) () ()
+)
+(define-full-operand X "Empty suffix" (all-isas)
+  h-sint DFLT f-nil
+  ((parse "X") (print "X")) () ()
+)
+(define-full-operand size "any size specifier" (all-isas)
+  h-sint DFLT f-nil
+  ((parse "size") (print "size")) () ()
+)
+;-------------------------------------------------------------
+; Misc
+;-------------------------------------------------------------
+
+(dnop BitIndex "Bit Index for the next insn" (SEM-ONLY MACH32 m32c-isa) h-bit-index f-nil)
+(dnop SrcIndex "Source Index for the next insn" (SEM-ONLY MACH32 m32c-isa) h-src-index f-nil)
+(dnop DstIndex "Destination Index for the next insn" (SEM-ONLY MACH32 m32c-isa) h-dst-index f-nil)
+(dnop NoRemainder "Place holder for when the remainder is not kept" (SEM-ONLY MACH32 m32c-isa) h-none f-nil)
+\f
+;=============================================================
+; Derived Operands
+
+; Memory reference macros that clip addresses appropriately.  Refer to
+; memory at ADDRESS in MODE, clipped appropriately for either the m16c
+; or m32c.
+(define-pmacro (mem16 mode address)
+  (mem mode (and #xffff address)))
+
+(define-pmacro (mem20 mode address)
+  (mem mode (and #xfffff address)))
+
+(define-pmacro (mem32 mode address)
+  (mem mode (and #xffffff address)))
+
+; Like mem16 and mem32, but takes MACH as a parameter.  MACH must be
+; either 16 or 32.
+(define-pmacro (mem-mach mach mode address)
+  ((.sym mem mach) mode address))
+
+;-------------------------------------------------------------
+; Source
+;-------------------------------------------------------------
+; Rn direct
+;-------------------------------------------------------------
+
+(define-pmacro (src16-Rn-direct-operand xmode)
+  (begin
+    (define-derived-operand
+      (name (.sym src16-Rn-direct- xmode))
+      (comment (.str "m16c Rn direct source " xmode))
+      (attrs (machine 16))
+      (mode xmode)
+      (args ((.sym Src16Rn xmode)))
+      (syntax (.str "$Src16Rn" xmode))
+      (base-ifield f-8-4)
+      (encoding (+ (f-8-2 0) (.sym Src16Rn xmode)))
+      (ifield-assertion (eq f-8-2 0))
+      (getter (trunc xmode (.sym Src16Rn xmode)))
+      (setter (set (.sym Src16Rn xmode) newval))
+    )
+  )
+)
+(src16-Rn-direct-operand QI)
+(src16-Rn-direct-operand HI)
+
+(define-pmacro (src32-Rn-direct-operand group base xmode)
+  (begin
+    (define-derived-operand
+      (name (.sym src32-Rn-direct- group - xmode))
+      (comment (.str "m32c Rn direct source " xmode))
+      (attrs (machine 32))
+      (mode xmode)
+      (args ((.sym Src32Rn group xmode)))
+      (syntax (.str "$Src32Rn" group xmode))
+      (base-ifield (.sym f- base -11))
+      (encoding (+ ((.sym f- base -3) 4) (.sym Src32Rn group xmode)))
+      (ifield-assertion (eq (.sym f- base -3) 4))
+      (getter (trunc xmode (.sym Src32Rn group xmode)))
+      (setter (set (.sym Src32Rn group xmode) newval))
+    )
+  )
+)
+
+(src32-Rn-direct-operand Unprefixed  1 QI)
+(src32-Rn-direct-operand   Prefixed  9 QI)
+(src32-Rn-direct-operand Unprefixed  1 HI)
+(src32-Rn-direct-operand   Prefixed  9 HI)
+(src32-Rn-direct-operand Unprefixed  1 SI)
+(src32-Rn-direct-operand   Prefixed  9 SI)
+
+;-------------------------------------------------------------
+; An direct
+;-------------------------------------------------------------
+
+(define-pmacro (src16-An-direct-operand xmode)
+  (begin
+    (define-derived-operand
+      (name (.sym src16-An-direct- xmode))
+      (comment (.str "m16c An direct destination " xmode))
+      (attrs (machine 16))
+      (mode xmode)
+      (args ((.sym Src16An xmode)))
+      (syntax (.str "$Src16An" xmode))
+      (base-ifield f-8-4)
+      (encoding (+ (f-8-2 1) (f-10-1 0) (.sym Src16An xmode)))
+      (ifield-assertion (andif (eq f-8-2 1) (eq f-10-1 0)))
+      (getter (trunc xmode (.sym Src16An xmode)))
+      (setter (set (.sym Src16An xmode) newval))
+    )
+  )
+)
+(src16-An-direct-operand QI)
+(src16-An-direct-operand HI)
+
+(define-pmacro (src32-An-direct-operand group base1 base2 xmode)
+  (begin
+    (define-derived-operand
+      (name (.sym src32-An-direct- group - xmode))
+      (comment (.str "m32c An direct destination " xmode))
+      (attrs (machine 32))
+      (mode xmode)
+      (args ((.sym Src32An group xmode)))
+      (syntax (.str "$Src32An" group xmode))
+      (base-ifield (.sym f- base1 -11))
+      (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 1) (.sym Src32An group xmode)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 1)))
+      (getter (trunc xmode (.sym Src32An group xmode)))
+      (setter (set (.sym Src32An group xmode) newval))
+    )
+  )
+)
+
+(src32-An-direct-operand Unprefixed 1 10 QI)
+(src32-An-direct-operand Unprefixed 1 10 HI)
+(src32-An-direct-operand Unprefixed 1 10 SI)
+(src32-An-direct-operand Prefixed   9 18 QI)
+(src32-An-direct-operand Prefixed   9 18 HI)
+(src32-An-direct-operand Prefixed   9 18 SI)
+
+;-------------------------------------------------------------
+; An indirect
+;-------------------------------------------------------------
+
+(define-pmacro (src16-An-indirect-operand xmode)
+  (begin
+    (define-derived-operand
+      (name (.sym src16-An-indirect- xmode))
+      (comment (.str "m16c An indirect destination " xmode))
+      (attrs (machine 16))
+      (mode xmode)
+      (args (Src16An))
+      (syntax "[$Src16An]")
+      (base-ifield f-8-4)
+      (encoding (+ (f-8-2 1) (f-10-1 1) Src16An))
+      (ifield-assertion (andif (eq f-8-2 1) (eq f-10-1 1)))
+      (getter (mem16 xmode Src16An))
+      (setter (set (mem16 xmode Src16An) newval))
+    )
+  )
+)
+(src16-An-indirect-operand QI)
+(src16-An-indirect-operand HI)
+
+(define-pmacro (src32-An-indirect-operand group base1 base2 xmode)
+  (begin
+    (define-derived-operand
+      (name (.sym src32-An-indirect- group - xmode))
+      (comment (.str "m32c An indirect destination " xmode))
+      (attrs (machine 32))
+      (mode xmode)
+      (args ((.sym Src32An group)))
+      (syntax (.str "[$Src32An" group "]"))
+      (base-ifield (.sym f- base1 -11))
+      (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 0) (.sym Src32An group)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 0)))
+      (getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group)
+                      (const 0)))
+      (setter (c-call DFLT (.str "operand_setter_" xmode)  newval
+                     (.sym Src32An group) (const 0)))
+;      (getter (mem32 xmode (.sym Src32An group)))
+;      (setter (set (mem32 xmode (.sym Src32An group)) newval))
+    )
+  )
+)
+
+(src32-An-indirect-operand Unprefixed 1 10 QI)
+(src32-An-indirect-operand Unprefixed 1 10 HI)
+(src32-An-indirect-operand Unprefixed 1 10 SI)
+(src32-An-indirect-operand Prefixed   9 18 QI)
+(src32-An-indirect-operand Prefixed   9 18 HI)
+(src32-An-indirect-operand Prefixed   9 18 SI)
+
+;-------------------------------------------------------------
+; dsp:d[r] relative
+;-------------------------------------------------------------
+
+(define-pmacro (src16-relative-operand xmode)
+  (begin
+    (define-derived-operand
+      (name (.sym src16-16-8-SB-relative- xmode))
+      (comment (.str "m16c dsp:8[sb] relative destination " xmode))
+      (attrs (machine 16))
+      (mode xmode)
+      (args (Dsp-16-u8))
+      (syntax "${Dsp-16-u8}[sb]")
+      (base-ifield f-8-4)
+      (encoding (+ (f-8-4 #xA) Dsp-16-u8))
+      (ifield-assertion (eq f-8-4 #xA))
+      (getter (mem16 xmode (add Dsp-16-u8 (reg h-sb))))
+      (setter (set (mem16 xmode (add Dsp-16-u8 (reg h-sb))) newval))
+    )
+    (define-derived-operand
+      (name (.sym src16-16-16-SB-relative- xmode))
+      (comment (.str "m16c dsp:16[sb] relative destination " xmode))
+      (attrs (machine 16))
+      (mode xmode)
+      (args (Dsp-16-u16))
+      (syntax "${Dsp-16-u16}[sb]")
+      (base-ifield f-8-4)
+      (encoding (+ (f-8-4 #xE) Dsp-16-u16))
+      (ifield-assertion (eq f-8-4 #xE))
+      (getter (mem16 xmode (add Dsp-16-u16 (reg h-sb))))
+      (setter (set (mem16 xmode (add Dsp-16-u16 (reg h-sb))) newval))
+    )
+    (define-derived-operand
+      (name (.sym src16-16-8-FB-relative- xmode))
+      (comment (.str "m16c dsp:8[fb] relative destination " xmode))
+      (attrs (machine 16))
+      (mode xmode)
+      (args (Dsp-16-s8))
+      (syntax "${Dsp-16-s8}[fb]")
+      (base-ifield f-8-4)
+      (encoding (+ (f-8-4 #xB) Dsp-16-s8))
+      (ifield-assertion (eq f-8-4 #xB))
+      (getter (mem16 xmode (add Dsp-16-s8 (reg h-fb))))
+      (setter (set (mem16 xmode (add Dsp-16-s8 (reg h-fb))) newval))
+    )
+    (define-derived-operand
+      (name (.sym src16-16-8-An-relative- xmode))
+      (comment (.str "m16c dsp:8[An] relative destination " xmode))
+      (attrs (machine 16))
+      (mode xmode)
+      (args (Src16An Dsp-16-u8))
+      (syntax "${Dsp-16-u8}[$Src16An]")
+      (base-ifield f-8-4)
+      (encoding (+ (f-8-2 2) (f-10-1 0) Dsp-16-u8 Src16An))
+      (ifield-assertion (andif (eq f-8-2 2) (eq f-10-1 0)))
+      (getter (mem16 xmode (add Dsp-16-u8 Src16An)))
+      (setter (set (mem16 xmode (add Dsp-16-u8 Src16An)) newval))
+    )
+    (define-derived-operand
+      (name (.sym src16-16-16-An-relative- xmode))
+      (comment (.str "m16c dsp:16[An] relative destination " xmode))
+      (attrs (machine 16))
+      (mode xmode)
+      (args (Src16An Dsp-16-u16))
+      (syntax "${Dsp-16-u16}[$Src16An]")
+      (base-ifield f-8-4)
+      (encoding (+ (f-8-2 3) (f-10-1 0) Dsp-16-u16 Src16An))
+      (ifield-assertion (andif (eq f-8-2 3) (eq f-10-1 0)))
+      (getter (mem16 xmode (add Dsp-16-u16 Src16An)))
+      (setter (set (mem16 xmode (add Dsp-16-u16 Src16An)) newval))
+    )
+    (define-derived-operand
+      (name (.sym src16-16-20-An-relative- xmode))
+      (comment (.str "m16c dsp:20[An] relative destination " xmode))
+      (attrs (machine 16))
+      (mode xmode)
+      (args (Src16An Dsp-16-u20))
+      (syntax "${Dsp-16-u20}[$Src16An]")
+      (base-ifield f-8-4)
+      (encoding (+ (f-8-2 3) (f-10-1 0) Dsp-16-u20 Src16An))
+      (ifield-assertion (andif (eq f-8-2 3) (eq f-10-1 0)))
+      (getter (mem20 xmode (add Dsp-16-u20 Src16An)))
+      (setter (set (mem20 xmode (add Dsp-16-u20 Src16An)) newval))
+    )
+  )
+)
+
+(src16-relative-operand QI)
+(src16-relative-operand HI)
+
+(define-pmacro (src32-relative-operand offset group base1 base2 xmode)
+  (begin
+    (define-derived-operand
+      (name (.sym src32- offset -8-SB-relative- group - xmode))
+      (comment (.str "m32c dsp:8[sb] relative destination " xmode))
+      (attrs (machine 32))
+      (mode xmode)
+      (args ((.sym Dsp- offset -u8)))
+      (syntax (.str "${Dsp-" offset "-u8}[sb]"))
+      (base-ifield (.sym f- base1 -11))
+      (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u8)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 2)))
+      (getter (c-call xmode (.str "operand_getter_" xmode) sb (.sym Dsp- offset -u8)))
+      (setter (c-call DFLT (.str "operand_setter_" xmode) newval sb (.sym Dsp- offset -u8)))
+;       (getter (mem32 xmode (add (.sym Dsp- offset -u8) (reg h-sb))))
+;       (setter (set (mem32 xmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval))
+    )
+    (define-derived-operand
+      (name (.sym src32- offset -16-SB-relative- group - xmode))
+      (comment (.str "m32c dsp:16[sb] relative destination " xmode))
+      (attrs (machine 32))
+      (mode xmode)
+      (args ((.sym Dsp- offset -u16)))
+      (syntax (.str "${Dsp-" offset "-u16}[sb]"))
+      (base-ifield (.sym f- base1 -11))
+      (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u16)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 2)))
+      (getter (c-call xmode (.str "operand_getter_" xmode) sb (.sym Dsp- offset -u16)))
+      (setter (c-call DFLT (.str "operand_setter_" xmode) newval sb (.sym Dsp- offset -u16)))
+;       (getter (mem32 xmode (add (.sym Dsp- offset -u16) (reg h-sb))))
+;       (setter (set (mem32 xmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval))
+    )
+    (define-derived-operand
+      (name (.sym src32- offset -8-FB-relative- group - xmode))
+      (comment (.str "m32c dsp:8[fb] relative destination " xmode))
+      (attrs (machine 32))
+      (mode xmode)
+      (args ((.sym Dsp- offset -s8)))
+      (syntax (.str "${Dsp-" offset "-s8}[fb]"))
+      (base-ifield (.sym f- base1 -11))
+      (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s8)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 3)))
+      (getter (c-call xmode (.str "operand_getter_" xmode) fb (.sym Dsp- offset -s8)))
+      (setter (c-call DFLT (.str "operand_setter_" xmode) newval fb (.sym Dsp- offset -s8)))
+;       (getter (mem32 xmode (add (.sym Dsp- offset -s8) (reg h-fb))))
+;       (setter (set (mem32 xmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval))
+    )
+    (define-derived-operand
+      (name (.sym src32- offset -16-FB-relative- group - xmode))
+      (comment (.str "m32c dsp:16[fb] relative destination " xmode))
+      (attrs (machine 32))
+      (mode xmode)
+      (args ((.sym Dsp- offset -s16)))
+      (syntax (.str "${Dsp-" offset "-s16}[fb]"))
+      (base-ifield (.sym f- base1 -11))
+      (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s16)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 3)))
+      (getter (c-call xmode (.str "operand_getter_" xmode) fb (.sym Dsp- offset -s16)))
+      (setter (c-call DFLT (.str "operand_setter_" xmode) newval fb (.sym Dsp- offset -s16)))
+;       (getter (mem32 xmode (add (.sym Dsp- offset -s16) (reg h-fb))))
+;       (setter (set (mem32 xmode (add (.sym Dsp- offset -s16) (reg h-fb))) newval))
+    )
+    (define-derived-operand
+      (name (.sym src32- offset -8-An-relative- group - xmode))
+      (comment (.str "m32c dsp:8[An] relative destination " xmode))
+      (attrs (machine 32))
+      (mode xmode)
+      (args ((.sym Src32An group) (.sym Dsp- offset -u8)))
+      (syntax (.str "${Dsp-" offset "-u8}[$Src32An" group "]"))
+      (base-ifield (.sym f- base1 -11))
+      (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u8) (.sym Src32An group)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -1) 0)))
+      (getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) (.sym Dsp- offset -u8)))
+      (setter (c-call DFLT (.str "operand_setter_" xmode) newval (.sym Src32An group) (.sym Dsp- offset -u8)))
+;       (getter (mem32 xmode (add (.sym Dsp- offset -u8) (.sym Src32An group))))
+;       (setter (set (mem32 xmode (add (.sym Dsp- offset -u8) (.sym Src32An group))) newval))
+    )
+    (define-derived-operand
+      (name (.sym src32- offset -16-An-relative- group - xmode))
+      (comment (.str "m32c dsp:16[An] relative destination " xmode))
+      (attrs (machine 32))
+      (mode xmode)
+      (args ((.sym Src32An group) (.sym Dsp- offset -u16)))
+      (syntax (.str "${Dsp-" offset "-u16}[$Src32An" group "]"))
+      (base-ifield (.sym f- base1 -11))
+      (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u16) (.sym Src32An group)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -1) 0)))
+      (getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) (.sym Dsp- offset -u16)))
+      (setter (c-call DFLT (.str "operand_setter_" xmode) newval (.sym Src32An group) (.sym Dsp- offset -u16)))
+;       (getter (mem32 xmode (add (.sym Dsp- offset -u16) (.sym Src32An group))))
+;       (setter (set (mem32 xmode (add (.sym Dsp- offset -u16) (.sym Src32An group))) newval))
+    )
+    (define-derived-operand
+      (name (.sym src32- offset -24-An-relative- group - xmode))
+      (comment (.str "m32c dsp:16[An] relative destination " xmode))
+      (attrs (machine 32))
+      (mode xmode)
+      (args ((.sym Src32An group) (.sym Dsp- offset -u24)))
+      (syntax (.str "${Dsp-" offset "-u24}[$Src32An" group "]"))
+      (base-ifield (.sym f- base1 -11))
+      (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u24) (.sym Src32An group)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -1) 0)))
+      (getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) (.sym Dsp- offset -u24) ))
+      (setter (c-call DFLT (.str "operand_setter_" xmode) newval (.sym Src32An group) (.sym Dsp- offset -u24)))
+;       (getter (mem32 xmode (add (.sym Dsp- offset -u24) (.sym Src32An group))))
+;       (setter (set (mem32 xmode (add (.sym Dsp- offset -u24) (.sym Src32An group))) newval))
+    )
+  )
+)
+
+(src32-relative-operand 16 Unprefixed 1 10 QI)
+(src32-relative-operand 16 Unprefixed 1 10 HI)
+(src32-relative-operand 16 Unprefixed 1 10 SI)
+(src32-relative-operand 24 Prefixed   9 18 QI)
+(src32-relative-operand 24 Prefixed   9 18 HI)
+(src32-relative-operand 24 Prefixed   9 18 SI)
+
+;-------------------------------------------------------------
+; Absolute address
+;-------------------------------------------------------------
+
+(define-pmacro (src16-absolute xmode)
+  (begin
+    (define-derived-operand
+      (name (.sym src16-16-16-absolute- xmode))
+      (comment (.str "m16c absolute address " xmode))
+      (attrs (machine 16))
+      (mode xmode)
+      (args (Dsp-16-u16))
+      (syntax (.str "${Dsp-16-u16}"))
+      (base-ifield f-8-4)
+      (encoding (+ (f-8-4 #xF) Dsp-16-u16))
+      (ifield-assertion (eq f-8-4 #xF))
+      (getter (mem16 xmode Dsp-16-u16))
+      (setter (set (mem16 xmode Dsp-16-u16) newval))
+    )
+  )
+)
+
+(src16-absolute QI)
+(src16-absolute HI)
+
+(define-pmacro (src32-absolute offset group base1 base2 xmode)
+  (begin
+    (define-derived-operand
+      (name (.sym src32- offset -16-absolute- group - xmode))
+      (comment (.str "m32c absolute address " xmode))
+      (attrs (machine 32))
+      (mode xmode)
+      (args ((.sym Dsp- offset -u16)))
+      (syntax (.str "${Dsp-" offset "-u16}"))
+      (base-ifield (.sym f- base1 -11))
+      (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym Dsp- offset -u16)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3)))
+      (getter (c-call xmode (.str "operand_getter_" xmode) (const 0) (.sym Dsp- offset -u16)))
+      (setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) (.sym Dsp- offset -u16)))
+;      (getter (mem32 xmode (.sym Dsp- offset -u16)))
+;      (setter (set (mem32 xmode (.sym Dsp- offset -u16)) newval))
+    )
+    (define-derived-operand
+      (name (.sym src32- offset -24-absolute- group - xmode))
+      (comment (.str "m32c absolute address " xmode))
+      (attrs (machine 32))
+      (mode xmode)
+      (args ((.sym Dsp- offset -u24)))
+      (syntax (.str "${Dsp-" offset "-u24}"))
+      (base-ifield (.sym f- base1 -11))
+      (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u24)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2)))
+      (getter (c-call xmode (.str "operand_getter_" xmode) (const 0) (.sym Dsp- offset -u24)))
+      (setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) (.sym Dsp- offset -u24)))
+;      (getter (mem32 xmode (.sym Dsp- offset -u24)))
+;      (setter (set (mem32 xmode (.sym Dsp- offset -u24)) newval))
+    )
+  )
+)
+
+(src32-absolute 16 Unprefixed 1 10 QI)
+(src32-absolute 16 Unprefixed 1 10 HI)
+(src32-absolute 16 Unprefixed 1 10 SI)
+(src32-absolute 24 Prefixed   9 18 QI)
+(src32-absolute 24 Prefixed   9 18 HI)
+(src32-absolute 24 Prefixed   9 18 SI)
+
+;-------------------------------------------------------------
+; An indirect indirect
+;
+; Double indirect addressing uses the lower 3 bytes of the value stored
+; at the address referenced by 'op' as the effective address.
+;-------------------------------------------------------------
+
+(define-pmacro (indirect-addr op) (and USI (mem32 USI op) #x00ffffff))
+
+; (define-pmacro (src-An-indirect-indirect-operand xmode)
+;   (define-derived-operand
+;     (name (.sym src32-An-indirect-indirect- xmode))
+;     (comment (.str "m32c An indirect indirect destination " xmode))
+;     (attrs (machine 32))
+;     (mode xmode)
+;     (args (Src32AnPrefixed))
+;     (syntax (.str "[[$Src32AnPrefixed]]"))
+;     (base-ifield f-9-11)
+;     (encoding (+ (f-9-3 0) (f-18-1 0) Src32AnPrefixed))
+;     (ifield-assertion (andif (eq f-9-3 0) (eq f-18-1 0)))
+;     (getter (mem32 xmode (indirect-addr Src32AnPrefixed)))
+;     (setter (set (mem32 xmode (indirect-addr Src32AnPrefixed)) newval))
+;   )
+; )
+
+; (src-An-indirect-indirect-operand QI)
+; (src-An-indirect-indirect-operand HI)
+; (src-An-indirect-indirect-operand SI)
+
+;-------------------------------------------------------------
+; Relative indirect
+;-------------------------------------------------------------
+
+(define-pmacro (src-relative-indirect-operand xmode)
+  (begin
+;     (define-derived-operand
+;       (name (.sym src32-24-8-SB-relative-indirect- xmode))
+;       (comment (.str "m32c dsp:8[sb] relative source " xmode))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (args (Dsp-24-u8))
+;       (syntax "[${Dsp-24-u8}[sb]]")
+;       (base-ifield f-9-11)
+;       (encoding (+ (f-9-3 1) (f-18-2 2) Dsp-24-u8))
+;       (ifield-assertion (andif (eq f-9-3 1) (eq f-18-2 2)))
+;       (getter (mem32 xmode (indirect-addr (add Dsp-24-u8 (reg h-sb)))))
+;       (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u8 (reg h-sb)))) newval))
+;     )
+;     (define-derived-operand
+;       (name (.sym src32-24-16-SB-relative-indirect- xmode))
+;       (comment (.str "m32c dsp:16[sb] relative source " xmode))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (args (Dsp-24-u16))
+;       (syntax "[${Dsp-24-u16}[sb]]")
+;       (base-ifield f-9-11)
+;       (encoding (+ (f-9-3 2) (f-18-2 2) Dsp-24-u16))
+;       (ifield-assertion (andif (eq f-9-3 2) (eq f-18-2 2)))
+;       (getter (mem32 xmode (indirect-addr (add Dsp-24-u16 (reg h-sb)))))
+;       (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u16 (reg h-sb)))) newval))
+;     )
+;     (define-derived-operand
+;       (name (.sym src32-24-8-FB-relative-indirect- xmode))
+;       (comment (.str "m32c dsp:8[fb] relative source " xmode))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (args (Dsp-24-s8))
+;       (syntax "[${Dsp-24-s8}[fb]]")
+;       (base-ifield f-9-11)
+;       (encoding (+ (f-9-3 1) (f-18-2 3) Dsp-24-s8))
+;       (ifield-assertion (andif (eq f-9-3 1) (eq f-18-2 3)))
+;       (getter (mem32 xmode (indirect-addr (add Dsp-24-s8 (reg h-fb)))))
+;       (setter (set (mem32 xmode (indirect-addr (add Dsp-24-s8 (reg h-fb)))) newval))
+;     )
+;     (define-derived-operand
+;       (name (.sym src32-24-16-FB-relative-indirect- xmode))
+;       (comment (.str "m32c dsp:16[fb] relative source " xmode))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (args (Dsp-24-s16))
+;       (syntax "[${Dsp-24-s16}[fb]]")
+;       (base-ifield f-9-11)
+;       (encoding (+ (f-9-3 2) (f-18-2 3) Dsp-24-s16))
+;       (ifield-assertion (andif (eq f-9-3 2) (eq f-18-2 3)))
+;       (getter (mem32 xmode (indirect-addr (add Dsp-24-s16 (reg h-fb)))))
+;       (setter (set (mem32 xmode (indirect-addr (add Dsp-24-s16 (reg h-fb)))) newval))
+;     )
+;     (define-derived-operand
+;       (name (.sym src32-24-8-An-relative-indirect- xmode))
+;       (comment (.str "m32c dsp:8[An] relative indirect source " xmode))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (args (Src32AnPrefixed Dsp-24-u8))
+;       (syntax "[${Dsp-24-u8}[$Src32AnPrefixed]]")
+;       (base-ifield f-9-11)
+;       (encoding (+ (f-9-3 1) (f-18-1 0) Dsp-24-u8 Src32AnPrefixed))
+;       (ifield-assertion (andif (eq f-9-3 1) (eq f-18-1 0)))
+;       (getter (mem32 xmode (indirect-addr (add Dsp-24-u8 Src32AnPrefixed))))
+;       (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u8 Src32AnPrefixed))) newval))
+;     )
+;     (define-derived-operand
+;       (name (.sym src32-24-16-An-relative-indirect- xmode))
+;       (comment (.str "m32c dsp:16[An] relative source " xmode))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (args (Src32AnPrefixed Dsp-24-u16))
+;       (syntax "[${Dsp-24-u16}[$Src32AnPrefixed]]")
+;       (base-ifield f-9-11)
+;       (encoding (+ (f-9-3 2) (f-18-1 0) Dsp-24-u16 Src32AnPrefixed))
+;       (ifield-assertion (andif (eq f-9-3 2) (eq f-18-1 0)))
+;       (getter (mem32 xmode (indirect-addr (add Dsp-24-u16 Src32AnPrefixed))))
+;       (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u16 Src32AnPrefixed))) newval))
+;     )
+;     (define-derived-operand
+;       (name (.sym src32-24-24-An-relative-indirect- xmode))
+;       (comment (.str "m32c dsp:24[An] relative source " xmode))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (args (Src32AnPrefixed Dsp-24-u24))
+;       (syntax "[${Dsp-24-u24}[$Src32AnPrefixed]]")
+;       (base-ifield f-9-11)
+;       (encoding (+ (f-9-3 3) (f-18-1 0) Dsp-24-u24 Src32AnPrefixed))
+;       (ifield-assertion (andif (eq f-9-3 3) (eq f-18-1 0)))
+;       (getter (mem32 xmode (indirect-addr (add Dsp-24-u24 Src32AnPrefixed))))
+;       (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u24 Src32AnPrefixed))) newval))
+;     )
+  )
+)
+
+; (src-relative-indirect-operand QI)
+; (src-relative-indirect-operand HI)
+; (src-relative-indirect-operand SI)
+
+;-------------------------------------------------------------
+; Absolute Indirect address
+;-------------------------------------------------------------
+
+(define-pmacro (src32-absolute-indirect offset base1 base2 xmode)
+  (begin
+;     (define-derived-operand
+;       (name (.sym src32- offset -16-absolute-indirect-derived- xmode))
+;       (comment (.str "m32c absolute indirect address " xmode))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (args ((.sym Dsp- offset -u16)))
+;       (syntax (.str "[${Dsp-" offset "-u16}]"))
+;       (base-ifield (.sym f- base1 -11))
+;       (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym Dsp- offset -u16)))
+;       (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3)))
+;       (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u16))))
+;       (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u16))) newval))
+;     )
+;     (define-derived-operand
+;       (name (.sym src32- offset -24-absolute-indirect-derived- xmode))
+;       (comment (.str "m32c absolute indirect address " xmode))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (args ((.sym Dsp- offset -u24)))
+;       (syntax (.str "[${Dsp-" offset "-u24}]"))
+;       (base-ifield (.sym f- base1 -11))
+;       (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u24)))
+;       (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2)))
+;       (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u24))))
+;       (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u24))) newval))
+;     )
+  )
+)
+
+(src32-absolute-indirect 24 9 18 QI)
+(src32-absolute-indirect 24 9 18 HI)
+(src32-absolute-indirect 24 9 18 SI)
+
+;-------------------------------------------------------------
+; Register relative source operands for short format insns
+;-------------------------------------------------------------
+
+(define-pmacro (src-2-S-operands mach xmode base opc1 opc2 opc3)
+  (begin
+    (define-derived-operand
+      (name (.sym src mach -2-S-8-SB-relative- xmode))
+      (comment (.str "m" mach "c SB relative address"))
+      (attrs (machine mach))
+      (mode xmode)
+      (args (Dsp-8-u8))
+      (syntax "${Dsp-8-u8}[sb]")
+      (base-ifield (.sym f- base -2))
+      (encoding (+ ((.sym f- base -2) opc1) Dsp-8-u8))
+      (ifield-assertion (eq (.sym f- base -2) opc1))
+      (getter (c-call xmode (.str "operand_getter_" xmode) sb Dsp-8-u8))
+      (setter (c-call DFLT (.str "operand_setter_" xmode) newval sb Dsp-8-u8))
+;       (getter (mem-mach mach xmode (indirect-addr (add (reg h-sb) Dsp-8-u8))))
+;       (setter (set (mem-mach mach xmode (indirect-addr (add (reg h-sb) Dsp-8-u8))) newval))
+      )
+    (define-derived-operand
+      (name (.sym src mach -2-S-8-FB-relative- xmode))
+      (comment (.str "m" mach "c FB relative address"))
+      (attrs (machine mach))
+      (mode xmode)
+      (args (Dsp-8-s8))
+      (syntax "${Dsp-8-s8}[fb]")
+      (base-ifield (.sym f- base -2))
+      (encoding (+ ((.sym f- base -2) opc2) Dsp-8-s8))
+      (ifield-assertion (eq (.sym f- base -2) opc2))
+      (getter (c-call xmode (.str "operand_getter_" xmode) fb Dsp-8-s8))
+      (setter (c-call DFLT (.str "operand_setter_" xmode) newval fb Dsp-8-s8))
+;       (getter (mem-mach mach xmode (indirect-addr (add (reg h-fb) Dsp-8-s8))))
+;       (setter (set (mem-mach mach xmode (indirect-addr (add (reg h-fb) Dsp-8-s8))) newval))
+      )
+    (define-derived-operand
+      (name (.sym src mach -2-S-16-absolute- xmode))
+      (comment (.str "m" mach "c absolute address"))
+      (attrs (machine mach))
+      (mode xmode)
+      (args (Dsp-8-u16))
+      (syntax "${Dsp-8-u16}")
+      (base-ifield (.sym f- base -2))
+      (encoding (+ ((.sym f- base -2) opc3) Dsp-8-u16))
+      (ifield-assertion (eq (.sym f- base -2) opc3))
+      (getter (c-call xmode (.str "operand_getter_" xmode) (const 0) Dsp-8-u16))
+      (setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) Dsp-8-u16))
+;      (getter (mem-mach mach xmode Dsp-8-u16))
+;      (setter (set (mem-mach mach xmode Dsp-8-u16) newval))
+      )
+  )
+)
+
+(src-2-S-operands 16 QI 6 1 2 3)
+(src-2-S-operands 32 QI 2 2 3 1)
+(src-2-S-operands 32 HI 2 2 3 1)
+
+;=============================================================
+; Derived Operands
+;-------------------------------------------------------------
+; Destination
+;-------------------------------------------------------------
+; Rn direct
+;-------------------------------------------------------------
+
+(define-pmacro (dst16-Rn-direct-operand xmode)
+  (begin
+    (define-derived-operand
+      (name (.sym dst16-Rn-direct- xmode))
+      (comment (.str "m16c Rn direct destination " xmode))
+      (attrs (machine 16))
+      (mode xmode)
+      (args ((.sym Dst16Rn xmode)))
+      (syntax (.str "$Dst16Rn" xmode))
+      (base-ifield f-12-4)
+      (encoding (+ (f-12-2 0) (.sym Dst16Rn xmode)))
+      (ifield-assertion (eq f-12-2 0))
+      (getter (trunc xmode (.sym Dst16Rn xmode)))
+      (setter (set (.sym Dst16Rn xmode) newval))
+    )
+  )
+)
+
+(dst16-Rn-direct-operand QI)
+(dst16-Rn-direct-operand HI)
+(dst16-Rn-direct-operand SI)
+
+(define-derived-operand
+  (name dst16-Rn-direct-Ext-QI)
+  (comment "m16c Rn direct destination QI")
+  (attrs (machine 16))
+  (mode HI)
+  (args (Dst16RnExtQI))
+  (syntax "$Dst16RnExtQI")
+  (base-ifield f-12-4)
+  (encoding (+ (f-12-2 0) Dst16RnExtQI (f-15-1 0)))
+  (ifield-assertion (andif (eq f-12-2 0) (eq f-15-1 0)))
+  (getter (trunc QI (.sym Dst16RnExtQI)))
+  (setter (set Dst16RnExtQI newval))
+)
+
+(define-pmacro (dst32-Rn-direct-operand group base xmode)
+  (begin
+    (define-derived-operand
+      (name (.sym dst32-Rn-direct- group - xmode))
+      (comment (.str "m32c Rn direct destination " xmode))
+      (attrs (machine 32))
+      (mode xmode)
+      (args ((.sym Dst32Rn group xmode)))
+      (syntax (.str "$Dst32Rn" group xmode))
+      (base-ifield (.sym f- base -6))
+      (encoding (+ ((.sym f- base -3) 4) (.sym Dst32Rn group xmode)))
+      (ifield-assertion (eq (.sym f- base -3) 4))
+      (getter (trunc xmode (.sym Dst32Rn group xmode)))
+      (setter (set (.sym Dst32Rn group xmode) newval))
+    )
+  )
+)
+
+(dst32-Rn-direct-operand   Unprefixed  4 QI)
+(dst32-Rn-direct-operand     Prefixed 12 QI)
+(dst32-Rn-direct-operand   Unprefixed  4 HI)
+(dst32-Rn-direct-operand     Prefixed 12 HI)
+(dst32-Rn-direct-operand   Unprefixed  4 SI)
+(dst32-Rn-direct-operand     Prefixed 12 SI)
+
+(define-pmacro (dst32-Rn-direct-Ext-operand group base1 base2 smode dmode)
+  (begin
+    (define-derived-operand
+      (name (.sym dst32-Rn-direct- group - smode))
+      (comment (.str "m32c Rn direct destination " smode))
+      (attrs (machine 32))
+      (mode dmode)
+      (args ((.sym Dst32Rn group smode)))
+      (syntax (.str "$Dst32Rn" group smode))
+      (base-ifield (.sym f- base1 -6))
+      (encoding (+ ((.sym f- base1 -3) 4) ((.sym f- base2 -1) 1) (.sym Dst32Rn group smode)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 4) (eq (.sym f- base2 -1) 1)))
+      (getter (trunc smode (.sym Dst32Rn group smode)))
+      (setter (set (.sym Dst32Rn group smode) newval))
+    )
+  )
+)
+
+(dst32-Rn-direct-Ext-operand ExtUnprefixed 4 8 QI HI)
+(dst32-Rn-direct-Ext-operand ExtUnprefixed 4 8 HI SI)
+
+(define-derived-operand
+  (name dst32-R3-direct-Unprefixed-HI)
+  (comment "m32c R3 direct HI")
+  (attrs (machine 32))
+  (mode HI)
+  (args (R3))
+  (syntax "$R3")
+  (base-ifield f-4-6)
+  (encoding (+ (f-4-3 4) (f-8-2 #x1)))
+  (ifield-assertion (andif (eq f-4-3 4) (eq f-8-2 #x1)))
+  (getter (trunc HI R3))
+  (setter (set R3 newval))
+)
+;-------------------------------------------------------------
+; An direct
+;-------------------------------------------------------------
+
+(define-pmacro (dst16-An-direct-operand xmode)
+  (begin
+    (define-derived-operand
+      (name (.sym dst16-An-direct- xmode))
+      (comment (.str "m16c An direct destination " xmode))
+      (attrs (machine 16))
+      (mode xmode)
+      (args ((.sym Dst16An xmode)))
+      (syntax (.str "$Dst16An" xmode))
+      (base-ifield f-12-4)
+      (encoding (+ (f-12-2 1) (f-14-1 0) (.sym Dst16An xmode)))
+      (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 0)))
+      (getter (trunc xmode (.sym Dst16An xmode)))
+      (setter (set (.sym Dst16An xmode) newval))
+    )
+  )
+)
+
+(dst16-An-direct-operand QI)
+(dst16-An-direct-operand HI)
+(dst16-An-direct-operand SI)
+
+(define-pmacro (dst32-An-direct-operand group base1 base2 xmode)
+  (begin
+    (define-derived-operand
+      (name (.sym dst32-An-direct- group - xmode))
+      (comment (.str "m32c An direct destination " xmode))
+      (attrs (machine 32))
+      (mode xmode)
+      (args ((.sym Dst32An group xmode)))
+      (syntax (.str "$Dst32An" group xmode))
+      (base-ifield (.sym f- base1 -6))
+      (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 1) (.sym Dst32An group xmode)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 1)))
+      (getter (trunc xmode (.sym Dst32An group xmode)))
+      (setter (set (.sym Dst32An group xmode) newval))
+    )
+  )
+)
+
+(dst32-An-direct-operand Unprefixed  4  8 QI)
+(dst32-An-direct-operand   Prefixed 12 16 QI)
+(dst32-An-direct-operand Unprefixed  4  8 HI)
+(dst32-An-direct-operand   Prefixed 12 16 HI)
+(dst32-An-direct-operand Unprefixed  4  8 SI)
+(dst32-An-direct-operand   Prefixed 12 16 SI)
+
+;-------------------------------------------------------------
+; An indirect
+;-------------------------------------------------------------
+
+(define-pmacro (dst16-An-indirect-operand xmode)
+  (begin
+    (define-derived-operand
+      (name (.sym dst16-An-indirect- xmode))
+      (comment (.str "m16c An indirect destination " xmode))
+      (attrs (machine 16))
+      (mode xmode)
+      (args (Dst16An))
+      (syntax "[$Dst16An]")
+      (base-ifield f-12-4)
+      (encoding (+ (f-12-2 1) (f-14-1 1) Dst16An))
+      (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 1)))
+      (getter (mem16 xmode Dst16An))
+      (setter (set (mem16 xmode Dst16An) newval))
+    )
+  )
+)
+
+(dst16-An-indirect-operand QI)
+(dst16-An-indirect-operand HI)
+(dst16-An-indirect-operand SI)
+
+(define-derived-operand
+  (name dst16-An-indirect-Ext-QI)
+  (comment "m16c An indirect destination QI")
+  (attrs (machine 16))
+  (mode HI)
+  (args (Dst16An))
+  (syntax "[$Dst16An]")
+  (base-ifield f-12-4)
+  (encoding (+ (f-12-2 1) (f-14-1 1) Dst16An))
+  (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 1)))
+  (getter (mem16 QI Dst16An))
+  (setter (set (mem16 HI Dst16An) newval))
+)
+
+(define-pmacro (dst32-An-indirect-operand group base1 base2 smode dmode)
+  (begin
+    (define-derived-operand
+      (name (.sym dst32-An-indirect- group - smode))
+      (comment (.str "m32c An indirect destination " smode))
+      (attrs (machine 32))
+      (mode dmode)
+      (args ((.sym Dst32An group)))
+      (syntax (.str "[$Dst32An" group "]"))
+      (base-ifield (.sym f- base1 -6))
+      (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 0) (.sym Dst32An group)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 0)))
+      (getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group)
+                      (const 0)))
+      (setter (c-call DFLT (.str "operand_setter_" dmode)  newval
+                     (.sym Dst32An group) (const 0)))
+;      (getter (mem32 smode (.sym Dst32An group)))
+;      (setter (set (mem32 dmode (.sym Dst32An group)) newval))
+    )
+  )
+)
+
+(dst32-An-indirect-operand    Unprefixed  4  8 QI QI)
+(dst32-An-indirect-operand      Prefixed 12 16 QI QI)
+(dst32-An-indirect-operand    Unprefixed  4  8 HI HI)
+(dst32-An-indirect-operand      Prefixed 12 16 HI HI)
+(dst32-An-indirect-operand    Unprefixed  4  8 SI SI)
+(dst32-An-indirect-operand      Prefixed 12 16 SI SI)
+(dst32-An-indirect-operand ExtUnprefixed  4  8 QI HI)
+(dst32-An-indirect-operand ExtUnprefixed  4  8 HI SI)
+
+;-------------------------------------------------------------
+; dsp:d[r] relative
+;-------------------------------------------------------------
+
+(define-pmacro (dst16-relative-operand offset xmode)
+  (begin
+    (define-derived-operand
+      (name (.sym dst16- offset -8-SB-relative- xmode))
+      (comment (.str "m16c dsp:8[sb] relative destination " xmode))
+      (attrs (machine 16))
+      (mode xmode)
+      (args ((.sym Dsp- offset -u8)))
+      (syntax (.str "${Dsp-" offset "-u8}[sb]"))
+      (base-ifield f-12-4)
+      (encoding (+ (f-12-4 #xA) (.sym Dsp- offset -u8)))
+      (ifield-assertion (eq f-12-4 #xA))
+      (getter (mem16 xmode (add (.sym Dsp- offset -u8) (reg h-sb))))
+      (setter (set (mem16 xmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval))
+    )
+    (define-derived-operand
+      (name (.sym dst16- offset -16-SB-relative- xmode))
+      (comment (.str "m16c dsp:16[sb] relative destination " xmode))
+      (attrs (machine 16))
+      (mode xmode)
+      (args ((.sym Dsp- offset -u16)))
+      (syntax (.str "${Dsp-" offset "-u16}[sb]"))
+      (base-ifield f-12-4)
+      (encoding (+ (f-12-4 #xE) (.sym Dsp- offset -u16)))
+      (ifield-assertion (eq f-12-4 #xE))
+      (getter (mem16 xmode (add (.sym Dsp- offset -u16) (reg h-sb))))
+      (setter (set (mem16 xmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval))
+    )
+    (define-derived-operand
+      (name (.sym dst16- offset -8-FB-relative- xmode))
+      (comment (.str "m16c dsp:8[fb] relative destination " xmode))
+      (attrs (machine 16))
+      (mode xmode)
+      (args ((.sym Dsp- offset -s8)))
+      (syntax (.str "${Dsp-" offset "-s8}[fb]"))
+      (base-ifield f-12-4)
+      (encoding (+ (f-12-4 #xB) (.sym Dsp- offset -s8)))
+      (ifield-assertion (eq f-12-4 #xB))
+      (getter (mem16 xmode (add (.sym Dsp- offset -s8) (reg h-fb))))
+      (setter (set (mem16 xmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval))
+    )
+    (define-derived-operand
+      (name (.sym dst16- offset -8-An-relative- xmode))
+      (comment (.str "m16c dsp:8[An] relative destination " xmode))
+      (attrs (machine 16))
+      (mode xmode)
+      (args (Dst16An (.sym Dsp- offset -u8)))
+      (syntax (.str "${Dsp-" offset "-u8}[$Dst16An]"))
+      (base-ifield f-12-4)
+      (encoding (+ (f-12-2 2) (f-14-1 0) (.sym Dsp- offset -u8) Dst16An))
+      (ifield-assertion (andif (eq f-12-2 2) (eq f-14-1 0)))
+      (getter (mem16 xmode (add (.sym Dsp- offset -u8) Dst16An)))
+      (setter (set (mem16 xmode (add (.sym Dsp- offset -u8) Dst16An)) newval))
+    )
+    (define-derived-operand
+      (name (.sym dst16- offset -16-An-relative- xmode))
+      (comment (.str "m16c dsp:16[An] relative destination " xmode))
+      (attrs (machine 16))
+      (mode xmode)
+      (args (Dst16An (.sym Dsp- offset -u16)))
+      (syntax (.str "${Dsp-" offset "-u16}[$Dst16An]"))
+      (base-ifield f-12-4)
+      (encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u16) Dst16An))
+      (ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0)))
+      (getter (mem16 xmode (add (.sym Dsp- offset -u16) Dst16An)))
+      (setter (set (mem16 xmode (add (.sym Dsp- offset -u16) Dst16An)) newval))
+    )
+    (define-derived-operand
+      (name (.sym dst16- offset -20-An-relative- xmode))
+      (comment (.str "m16c dsp:20[An] relative destination " xmode))
+      (attrs (machine 16))
+      (mode xmode)
+      (args (Dst16An (.sym Dsp- offset -u20)))
+      (syntax (.str "${Dsp-" offset "-u20}[$Dst16An]"))
+      (base-ifield f-12-4)
+      (encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u20) Dst16An))
+      (ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0)))
+      (getter (mem16 xmode (add (.sym Dsp- offset -u20) Dst16An)))
+      (setter (set (mem16 xmode (add (.sym Dsp- offset -u20) Dst16An)) newval))
+    )
+  )
+)
+
+(dst16-relative-operand 16 QI)
+(dst16-relative-operand 24 QI)
+(dst16-relative-operand 32 QI)
+(dst16-relative-operand 40 QI)
+(dst16-relative-operand 48 QI)
+(dst16-relative-operand 16 HI)
+(dst16-relative-operand 24 HI)
+(dst16-relative-operand 32 HI)
+(dst16-relative-operand 40 HI)
+(dst16-relative-operand 48 HI)
+(dst16-relative-operand 16 SI)
+(dst16-relative-operand 24 SI)
+(dst16-relative-operand 32 SI)
+(dst16-relative-operand 40 SI)
+(dst16-relative-operand 48 SI)
+
+(define-pmacro (dst16-relative-Ext-operand offset smode dmode)
+  (begin
+    (define-derived-operand
+      (name (.sym dst16- offset -8-SB-relative-Ext- smode))
+      (comment (.str "m16c dsp:8[sb] relative destination " smode))
+      (attrs (machine 16))
+      (mode dmode)
+      (args ((.sym Dsp- offset -u8)))
+      (syntax (.str "${Dsp-" offset "-u8}[sb]"))
+      (base-ifield f-12-4)
+      (encoding (+ (f-12-4 #xA) (.sym Dsp- offset -u8)))
+      (ifield-assertion (eq f-12-4 #xA))
+      (getter (mem16 smode (add (.sym Dsp- offset -u8) (reg h-sb))))
+      (setter (set (mem16 dmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval))
+    )
+    (define-derived-operand
+      (name (.sym dst16- offset -16-SB-relative-Ext- smode))
+      (comment (.str "m16c dsp:16[sb] relative destination " smode))
+      (attrs (machine 16))
+      (mode dmode)
+      (args ((.sym Dsp- offset -u16)))
+      (syntax (.str "${Dsp-" offset "-u16}[sb]"))
+      (base-ifield f-12-4)
+      (encoding (+ (f-12-4 #xE) (.sym Dsp- offset -u16)))
+      (ifield-assertion (eq f-12-4 #xE))
+      (getter (mem16 smode (add (.sym Dsp- offset -u16) (reg h-sb))))
+      (setter (set (mem16 dmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval))
+    )
+    (define-derived-operand
+      (name (.sym dst16- offset -8-FB-relative-Ext- smode))
+      (comment (.str "m16c dsp:8[fb] relative destination " smode))
+      (attrs (machine 16))
+      (mode dmode)
+      (args ((.sym Dsp- offset -s8)))
+      (syntax (.str "${Dsp-" offset "-s8}[fb]"))
+      (base-ifield f-12-4)
+      (encoding (+ (f-12-4 #xB) (.sym Dsp- offset -s8)))
+      (ifield-assertion (eq f-12-4 #xB))
+      (getter (mem16 smode (add (.sym Dsp- offset -s8) (reg h-fb))))
+      (setter (set (mem16 dmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval))
+    )
+    (define-derived-operand
+      (name (.sym dst16- offset -8-An-relative-Ext- smode))
+      (comment (.str "m16c dsp:8[An] relative destination " smode))
+      (attrs (machine 16))
+      (mode dmode)
+      (args (Dst16An (.sym Dsp- offset -u8)))
+      (syntax (.str "${Dsp-" offset "-u8}[$Dst16An]"))
+      (base-ifield f-12-4)
+      (encoding (+ (f-12-2 2) (f-14-1 0) (.sym Dsp- offset -u8) Dst16An))
+      (ifield-assertion (andif (eq f-12-2 2) (eq f-14-1 0)))
+      (getter (mem16 smode (add (.sym Dsp- offset -u8) Dst16An)))
+      (setter (set (mem16 dmode (add (.sym Dsp- offset -u8) Dst16An)) newval))
+    )
+    (define-derived-operand
+      (name (.sym dst16- offset -16-An-relative-Ext- smode))
+      (comment (.str "m16c dsp:16[An] relative destination " smode))
+      (attrs (machine 16))
+      (mode dmode)
+      (args (Dst16An (.sym Dsp- offset -u16)))
+      (syntax (.str "${Dsp-" offset "-u16}[$Dst16An]"))
+      (base-ifield f-12-4)
+      (encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u16) Dst16An))
+      (ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0)))
+      (getter (mem16 smode (add (.sym Dsp- offset -u16) Dst16An)))
+      (setter (set (mem16 dmode (add (.sym Dsp- offset -u16) Dst16An)) newval))
+    )
+  )
+)
+
+(dst16-relative-Ext-operand 16 QI HI)
+
+(define-pmacro (dst32-relative-operand offset group base1 base2 smode dmode)
+  (begin
+    (define-derived-operand
+      (name (.sym dst32- offset -8-SB-relative- group - smode))
+      (comment (.str "m32c dsp:8[sb] relative destination " smode))
+      (attrs (machine 32))
+      (mode dmode)
+      (args ((.sym Dsp- offset -u8)))
+      (syntax (.str "${Dsp-" offset "-u8}[sb]"))
+      (base-ifield (.sym f- base1 -6))
+      (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u8)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 2)))
+      (getter (c-call dmode (.str "operand_getter_" dmode) sb (.sym Dsp- offset -u8)))
+      (setter (c-call DFLT (.str "operand_setter_" dmode) newval sb (.sym Dsp- offset -u8)))
+;       (getter (mem32 smode (add (.sym Dsp- offset -u8) (reg h-sb))))
+;       (setter (set (mem32 dmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval))
+    )
+    (define-derived-operand
+      (name (.sym dst32- offset -16-SB-relative- group - smode))
+      (comment (.str "m32c dsp:16[sb] relative destination " smode))
+      (attrs (machine 32))
+      (mode dmode)
+      (args ((.sym Dsp- offset -u16)))
+      (syntax (.str "${Dsp-" offset "-u16}[sb]"))
+      (base-ifield (.sym f- base1 -6))
+      (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u16)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 2)))
+      (getter (c-call dmode (.str "operand_getter_" dmode) sb (.sym Dsp- offset -u16)))
+      (setter (c-call DFLT (.str "operand_setter_" dmode) newval sb (.sym Dsp- offset -u16)))
+;       (getter (mem32 smode (add (.sym Dsp- offset -u16) (reg h-sb))))
+;       (setter (set (mem32 dmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval))
+    )
+    (define-derived-operand
+      (name (.sym dst32- offset -8-FB-relative- group - smode))
+      (comment (.str "m32c dsp:8[fb] relative destination " smode))
+      (attrs (machine 32))
+      (mode dmode)
+      (args ((.sym Dsp- offset -s8)))
+      (syntax (.str "${Dsp-" offset "-s8}[fb]"))
+      (base-ifield (.sym f- base1 -6))
+      (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s8)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 3)))
+      (getter (c-call dmode (.str "operand_getter_" dmode) fb (.sym Dsp- offset -s8)))
+      (setter (c-call DFLT (.str "operand_setter_" dmode) newval fb (.sym Dsp- offset -s8)))
+;       (getter (mem32 smode (add (.sym Dsp- offset -s8) (reg h-fb))))
+;       (setter (set (mem32 dmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval))
+    )
+    (define-derived-operand
+      (name (.sym dst32- offset -16-FB-relative- group - smode))
+      (comment (.str "m32c dsp:16[fb] relative destination " smode))
+      (attrs (machine 32))
+      (mode dmode)
+      (args ((.sym Dsp- offset -s16)))
+      (syntax (.str "${Dsp-" offset "-s16}[fb]"))
+      (base-ifield (.sym f- base1 -6))
+      (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s16)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 3)))
+      (getter (c-call dmode (.str "operand_getter_" dmode) fb (.sym Dsp- offset -s16)))
+      (setter (c-call DFLT (.str "operand_setter_" dmode) newval fb (.sym Dsp- offset -s16)))
+;       (getter (mem32 smode (add (.sym Dsp- offset -s16) (reg h-fb))))
+;       (setter (set (mem32 dmode (add (.sym Dsp- offset -s16) (reg h-fb))) newval))
+    )
+    (define-derived-operand
+      (name (.sym dst32- offset -8-An-relative- group - smode))
+      (comment (.str "m32c dsp:8[An] relative destination " smode))
+      (attrs (machine 32))
+      (mode dmode)
+      (args ((.sym Dst32An group) (.sym Dsp- offset -u8)))
+      (syntax (.str "${Dsp-" offset "-u8}[$Dst32An" group "]"))
+      (base-ifield (.sym f- base1 -6))
+      (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u8) (.sym Dst32An group)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -1) 0)))
+      (getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) (.sym Dsp- offset -u8)))
+      (setter (c-call DFLT (.str "operand_setter_" dmode) newval (.sym Dst32An group) (.sym Dsp- offset -u8)))
+;       (getter (mem32 smode (add (.sym Dsp- offset -u8) (.sym Dst32An group))))
+;       (setter (set (mem32 dmode (add (.sym Dsp- offset -u8) (.sym Dst32An group))) newval))
+    )
+    (define-derived-operand
+      (name (.sym dst32- offset -16-An-relative- group - smode))
+      (comment (.str "m32c dsp:16[An] relative destination " smode))
+      (attrs (machine 32))
+      (mode dmode)
+      (args ((.sym Dst32An group) (.sym Dsp- offset -u16)))
+      (syntax (.str "${Dsp-" offset "-u16}[$Dst32An" group "]"))
+      (base-ifield (.sym f- base1 -6))
+      (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u16) (.sym Dst32An group)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -1) 0)))
+      (getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) (.sym Dsp- offset -u16)))
+      (setter (c-call DFLT (.str "operand_setter_" dmode) newval (.sym Dst32An group) (.sym Dsp- offset -u16)))
+;       (getter (mem32 smode (add (.sym Dsp- offset -u16) (.sym Dst32An group))))
+;       (setter (set (mem32 dmode (add (.sym Dsp- offset -u16) (.sym Dst32An group))) newval))
+    )
+    (define-derived-operand
+      (name (.sym dst32- offset -24-An-relative- group - smode))
+      (comment (.str "m32c dsp:16[An] relative destination " smode))
+      (attrs (machine 32))
+      (mode dmode)
+      (args ((.sym Dst32An group) (.sym Dsp- offset -u24)))
+      (syntax (.str "${Dsp-" offset "-u24}[$Dst32An" group "]"))
+      (base-ifield (.sym f- base1 -6))
+      (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u24) (.sym Dst32An group)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -1) 0)))
+      (getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) (.sym Dsp- offset -u24)))
+      (setter (c-call DFLT (.str "operand_setter_" dmode) newval (.sym Dst32An group) (.sym Dsp- offset -u24)))
+;       (getter (mem32 smode (add (.sym Dsp- offset -u24) (.sym Dst32An group))))
+;       (setter (set (mem32 dmode (add (.sym Dsp- offset -u24) (.sym Dst32An group))) newval))
+    )
+  )
+)
+
+(dst32-relative-operand 16 Unprefixed 4 8 QI QI)
+(dst32-relative-operand 24 Unprefixed 4 8 QI QI)
+(dst32-relative-operand 32 Unprefixed 4 8 QI QI)
+(dst32-relative-operand 40 Unprefixed 4 8 QI QI)
+(dst32-relative-operand 16 Unprefixed 4 8 HI HI)
+(dst32-relative-operand 24 Unprefixed 4 8 HI HI)
+(dst32-relative-operand 32 Unprefixed 4 8 HI HI)
+(dst32-relative-operand 40 Unprefixed 4 8 HI HI)
+(dst32-relative-operand 16 Unprefixed 4 8 SI SI)
+(dst32-relative-operand 24 Unprefixed 4 8 SI SI)
+(dst32-relative-operand 32 Unprefixed 4 8 SI SI)
+(dst32-relative-operand 40 Unprefixed 4 8 SI SI)
+
+(dst32-relative-operand 24 Prefixed 12 16 QI QI)
+(dst32-relative-operand 32 Prefixed 12 16 QI QI)
+(dst32-relative-operand 40 Prefixed 12 16 QI QI)
+(dst32-relative-operand 48 Prefixed 12 16 QI QI)
+(dst32-relative-operand 24 Prefixed 12 16 HI HI)
+(dst32-relative-operand 32 Prefixed 12 16 HI HI)
+(dst32-relative-operand 40 Prefixed 12 16 HI HI)
+(dst32-relative-operand 48 Prefixed 12 16 HI HI)
+(dst32-relative-operand 24 Prefixed 12 16 SI SI)
+(dst32-relative-operand 32 Prefixed 12 16 SI SI)
+(dst32-relative-operand 40 Prefixed 12 16 SI SI)
+(dst32-relative-operand 48 Prefixed 12 16 SI SI)
+
+(dst32-relative-operand 16 ExtUnprefixed 4 8 QI HI)
+(dst32-relative-operand 16 ExtUnprefixed 4 8 HI SI)
+
+;-------------------------------------------------------------
+; Absolute address
+;-------------------------------------------------------------
+
+(define-pmacro (dst16-absolute offset xmode)
+  (begin
+    (define-derived-operand
+      (name (.sym dst16- offset -16-absolute- xmode))
+      (comment (.str "m16c absolute address " xmode))
+      (attrs (machine 16))
+      (mode xmode)
+      (args ((.sym Dsp- offset -u16)))
+      (syntax (.str "${Dsp-" offset "-u16}"))
+      (base-ifield f-12-4)
+      (encoding (+ (f-12-4 #xF) (.sym Dsp- offset -u16)))
+      (ifield-assertion (eq f-12-4 #xF))
+      (getter (mem16 xmode (.sym Dsp- offset -u16)))
+      (setter (set (mem16 xmode (.sym Dsp- offset -u16)) newval))
+    )
+  )
+)
+
+(dst16-absolute 16 QI)
+(dst16-absolute 24 QI)
+(dst16-absolute 32 QI)
+(dst16-absolute 40 QI)
+(dst16-absolute 48 QI)
+(dst16-absolute 16 HI)
+(dst16-absolute 24 HI)
+(dst16-absolute 32 HI)
+(dst16-absolute 40 HI)
+(dst16-absolute 48 HI)
+(dst16-absolute 16 SI)
+(dst16-absolute 24 SI)
+(dst16-absolute 32 SI)
+(dst16-absolute 40 SI)
+(dst16-absolute 48 SI)
+
+(define-derived-operand
+  (name dst16-16-16-absolute-Ext-QI)
+  (comment "m16c absolute address QI")
+  (attrs (machine 16))
+  (mode HI)
+  (args (Dsp-16-u16))
+  (syntax "${Dsp-16-u16}")
+  (base-ifield f-12-4)
+  (encoding (+ (f-12-4 #xF) Dsp-16-u16))
+  (ifield-assertion (eq f-12-4 #xF))
+  (getter (mem16 QI Dsp-16-u16))
+  (setter (set (mem16 HI Dsp-16-u16) newval))
+)
+
+(define-pmacro (dst32-absolute offset group base1 base2 smode dmode)
+  (begin
+    (define-derived-operand
+      (name (.sym dst32- offset -16-absolute- group - smode))
+      (comment (.str "m32c absolute address " smode))
+      (attrs (machine 32))
+      (mode dmode)
+      (args ((.sym Dsp- offset -u16)))
+      (syntax (.str "${Dsp-" offset "-u16}"))
+      (base-ifield (.sym f- base1 -6))
+      (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym Dsp- offset -u16)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3)))
+      (getter (c-call smode (.str "operand_getter_" smode) (const 0) (.sym Dsp- offset -u16)))
+      (setter (c-call DFLT (.str "operand_setter_" dmode) newval (const 0) (.sym Dsp- offset -u16)))
+;      (getter (mem32 smode (.sym Dsp- offset -u16)))
+;      (setter (set (mem32 dmode (.sym Dsp- offset -u16)) newval))
+    )
+    (define-derived-operand
+      (name (.sym dst32- offset -24-absolute- group - smode))
+      (comment (.str "m32c absolute address " smode))
+      (attrs (machine 32))
+      (mode dmode)
+      (args ((.sym Dsp- offset -u24)))
+      (syntax (.str "${Dsp-" offset "-u24}"))
+      (base-ifield (.sym f- base1 -6))
+      (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u24)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2)))
+      (getter (c-call smode (.str "operand_getter_" smode) (const 0) (.sym Dsp- offset -u24)))
+      (setter (c-call DFLT (.str "operand_setter_" dmode) newval (const 0) (.sym Dsp- offset -u24)))
+;      (getter (mem32 smode (.sym Dsp- offset -u24)))
+;      (setter (set (mem32 dmode (.sym Dsp- offset -u24)) newval))
+    )
+  )
+)
+
+(dst32-absolute 16 Unprefixed 4 8 QI QI)
+(dst32-absolute 24 Unprefixed 4 8 QI QI)
+(dst32-absolute 32 Unprefixed 4 8 QI QI)
+(dst32-absolute 40 Unprefixed 4 8 QI QI)
+(dst32-absolute 16 Unprefixed 4 8 HI HI)
+(dst32-absolute 24 Unprefixed 4 8 HI HI)
+(dst32-absolute 32 Unprefixed 4 8 HI HI)
+(dst32-absolute 40 Unprefixed 4 8 HI HI)
+(dst32-absolute 16 Unprefixed 4 8 SI SI)
+(dst32-absolute 24 Unprefixed 4 8 SI SI)
+(dst32-absolute 32 Unprefixed 4 8 SI SI)
+(dst32-absolute 40 Unprefixed 4 8 SI SI)
+
+(dst32-absolute 24 Prefixed 12 16 QI QI)
+(dst32-absolute 32 Prefixed 12 16 QI QI)
+(dst32-absolute 40 Prefixed 12 16 QI QI)
+(dst32-absolute 48 Prefixed 12 16 QI QI)
+(dst32-absolute 24 Prefixed 12 16 HI HI)
+(dst32-absolute 32 Prefixed 12 16 HI HI)
+(dst32-absolute 40 Prefixed 12 16 HI HI)
+(dst32-absolute 48 Prefixed 12 16 HI HI)
+(dst32-absolute 24 Prefixed 12 16 SI SI)
+(dst32-absolute 32 Prefixed 12 16 SI SI)
+(dst32-absolute 40 Prefixed 12 16 SI SI)
+(dst32-absolute 48 Prefixed 12 16 SI SI)
+
+(dst32-absolute 16 ExtUnprefixed 4 8 QI HI)
+(dst32-absolute 16 ExtUnprefixed 4 8 HI SI)
+
+;-------------------------------------------------------------
+; An indirect indirect
+;-------------------------------------------------------------
+
+;(define-pmacro (dst-An-indirect-indirect-operand xmode)
+;   (define-derived-operand
+;     (name (.sym dst32-An-indirect-indirect- xmode))
+;     (comment (.str "m32c An indirect indirect destination " xmode))
+;     (attrs (machine 32))
+;     (mode xmode)
+;     (args (Dst32AnPrefixed))
+;     (syntax (.str "[[$Dst32AnPrefixed]]"))
+;     (base-ifield f-12-6)
+;     (encoding (+ (f-12-3 0) (f-16-1 0) Dst32AnPrefixed))
+;     (ifield-assertion (andif (eq f-12-3 0) (eq f-16-1 0)))
+;     (getter (mem32 xmode (indirect-addr Dst32AnPrefixed)))
+;     (setter (set (mem32 xmode (indirect-addr Dst32AnPrefixed)) newval))
+;   )
+;)
+
+; (dst-An-indirect-indirect-operand QI)
+; (dst-An-indirect-indirect-operand HI)
+; (dst-An-indirect-indirect-operand SI)
+
+;-------------------------------------------------------------
+; Relative indirect
+;-------------------------------------------------------------
+
+(define-pmacro (dst-relative-indirect-operand offset xmode)
+  (begin
+;     (define-derived-operand
+;       (name (.sym dst32- offset -8-SB-relative-indirect- xmode))
+;       (comment (.str "m32c dsp:8[sb] relative destination " xmode))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (args ((.sym Dsp- offset -u8)))
+;       (syntax (.str "[${Dsp-" offset "-u8}[sb]]"))
+;       (base-ifield f-12-6)
+;       (encoding (+ (f-12-3 1) (f-16-2 2) (.sym Dsp- offset -u8)))
+;       (ifield-assertion (andif (eq f-12-3 1) (eq f-16-2 2)))
+;       (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) (reg h-sb)))))
+;       (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) (reg h-sb)))) newval))
+;     )
+;     (define-derived-operand
+;       (name (.sym dst32- offset -16-SB-relative-indirect- xmode))
+;       (comment (.str "m32c dsp:16[sb] relative destination " xmode))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (args ((.sym Dsp- offset -u16)))
+;       (syntax (.str "[${Dsp-" offset "-u16}[sb]]"))
+;       (base-ifield f-12-6)
+;       (encoding (+ (f-12-3 2) (f-16-2 2) (.sym Dsp- offset -u16)))
+;       (ifield-assertion (andif (eq f-12-3 2) (eq f-16-2 2)))
+;       (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) (reg h-sb)))))
+;       (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) (reg h-sb)))) newval))
+;     )
+;     (define-derived-operand
+;       (name (.sym dst32- offset -8-FB-relative-indirect- xmode))
+;       (comment (.str "m32c dsp:8[fb] relative destination " xmode))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (args ((.sym Dsp- offset -s8)))
+;       (syntax (.str "[${Dsp-" offset "-s8}[fb]]"))
+;       (base-ifield f-12-6)
+;       (encoding (+ (f-12-3 1) (f-16-2 3) (.sym Dsp- offset -s8)))
+;       (ifield-assertion (andif (eq f-12-3 1) (eq f-16-2 3)))
+;       (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s8) (reg h-fb)))))
+;       (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s8) (reg h-fb)))) newval))
+;     )
+;     (define-derived-operand
+;       (name (.sym dst32- offset -16-FB-relative-indirect- xmode))
+;       (comment (.str "m32c dsp:16[fb] relative destination " xmode))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (args ((.sym Dsp- offset -s16)))
+;       (syntax (.str "[${Dsp-" offset "-s16}[fb]]"))
+;       (base-ifield f-12-6)
+;       (encoding (+ (f-12-3 2) (f-16-2 3) (.sym Dsp- offset -s16)))
+;       (ifield-assertion (andif (eq f-12-3 2) (eq f-16-2 3)))
+;       (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s16) (reg h-fb)))))
+;       (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s16) (reg h-fb)))) newval))
+;     )
+;     (define-derived-operand
+;       (name (.sym dst32- offset -8-An-relative-indirect- xmode))
+;       (comment (.str "m32c dsp:8[An] relative indirect destination " xmode))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (args (Dst32AnPrefixed (.sym Dsp- offset -u8)))
+;       (syntax (.str "[${Dsp-" offset "-u8}[$Dst32AnPrefixed]]"))
+;       (base-ifield f-12-6)
+;       (encoding (+ (f-12-3 1) (f-16-1 0) (.sym Dsp- offset -u8) Dst32AnPrefixed))
+;       (ifield-assertion (andif (eq f-12-3 1) (eq f-16-1 0)))
+;       (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) Dst32AnPrefixed))))
+;       (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) Dst32AnPrefixed))) newval))
+;     )
+;     (define-derived-operand
+;       (name (.sym dst32- offset -16-An-relative-indirect- xmode))
+;       (comment (.str "m32c dsp:16[An] relative destination " xmode))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (args (Dst32AnPrefixed (.sym Dsp- offset -u16)))
+;       (syntax (.str "[${Dsp-" offset "-u16}[$Dst32AnPrefixed]]"))
+;       (base-ifield f-12-6)
+;       (encoding (+ (f-12-3 2) (f-16-1 0) (.sym Dsp- offset -u16) Dst32AnPrefixed))
+;       (ifield-assertion (andif (eq f-12-3 2) (eq f-16-1 0)))
+;       (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) Dst32AnPrefixed))))
+;       (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) Dst32AnPrefixed))) newval))
+;     )
+;     (define-derived-operand
+;       (name (.sym dst32- offset -24-An-relative-indirect- xmode))
+;       (comment (.str "m32c dsp:24[An] relative destination " xmode))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (args (Dst32AnPrefixed (.sym Dsp- offset -u24)))
+;       (syntax (.str "[${Dsp-" offset "-u24}[$Dst32AnPrefixed]]"))
+;       (base-ifield f-12-6)
+;       (encoding (+ (f-12-3 3) (f-16-1 0) (.sym Dsp- offset -u24) Dst32AnPrefixed))
+;       (ifield-assertion (andif (eq f-12-3 3) (eq f-16-1 0)))
+;       (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u24) Dst32AnPrefixed))))
+;       (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u24) Dst32AnPrefixed))) newval))
+;     )
+  )
+)
+
+; (dst-relative-indirect-operand 24 QI)
+; (dst-relative-indirect-operand 32 QI)
+; (dst-relative-indirect-operand 40 QI)
+; (dst-relative-indirect-operand 48 QI)
+; (dst-relative-indirect-operand 24 HI)
+; (dst-relative-indirect-operand 32 HI)
+; (dst-relative-indirect-operand 40 HI)
+; (dst-relative-indirect-operand 48 HI)
+; (dst-relative-indirect-operand 24 SI)
+; (dst-relative-indirect-operand 32 SI)
+; (dst-relative-indirect-operand 40 SI)
+; (dst-relative-indirect-operand 48 SI)
+
+;-------------------------------------------------------------
+; Absolute indirect
+;-------------------------------------------------------------
+
+(define-pmacro (dst-absolute-indirect offset xmode)
+  (begin
+;     (define-derived-operand
+;       (name (.sym dst32- offset -16-absolute-indirect-derived- xmode))
+;       (comment (.str "m32c absolute indirect address " xmode))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (args ((.sym Dsp- offset -u16)))
+;       (syntax (.str "[${Dsp-" offset "-u16}]"))
+;       (base-ifield f-12-6)
+;       (encoding (+ (f-12-3 3) (f-16-2 3) (.sym Dsp- offset -u16)))
+;       (ifield-assertion (andif (eq f-12-3 3) (eq f-16-2 3)))
+;       (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u16))))
+;       (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u16))) newval))
+;     )
+;     (define-derived-operand
+;       (name (.sym dst32- offset -24-absolute-indirect-derived- xmode))
+;       (comment (.str "m32c absolute indirect address " xmode))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (args ((.sym Dsp- offset -u24)))
+;       (syntax (.str "[${Dsp-" offset "-u24}]"))
+;       (base-ifield f-12-6)
+;       (encoding (+ (f-12-3 3) (f-16-2 2) (.sym Dsp- offset -u24)))
+;       (ifield-assertion (andif (eq f-12-3 3) (eq f-16-2 2)))
+;       (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u24))))
+;       (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u24))) newval))
+;     )
+  )
+)
+
+(dst-absolute-indirect 24 QI)
+(dst-absolute-indirect 32 QI)
+(dst-absolute-indirect 40 QI)
+(dst-absolute-indirect 48 QI)
+(dst-absolute-indirect 24 HI)
+(dst-absolute-indirect 32 HI)
+(dst-absolute-indirect 40 HI)
+(dst-absolute-indirect 48 HI)
+(dst-absolute-indirect 24 SI)
+(dst-absolute-indirect 32 SI)
+(dst-absolute-indirect 40 SI)
+(dst-absolute-indirect 48 SI)
+
+;-------------------------------------------------------------
+; Bit operands
+;-------------------------------------------------------------
+(define-pmacro (get-register-bit reg bitno)
+  (and (srl reg bitno) 1)
+)
+           
+(define-pmacro (set-register-bit reg bitno value)
+  (set reg (or (and reg (inv (sll 1 bitno)))
+              (sll (and QI value 1) bitno)))
+)
+
+(define-pmacro (get-memory-bit mach base bitno)
+  (and (srl (mem-mach mach QI (add base (div bitno 8)))
+           (mod bitno 8))
+       1)
+)
+           
+(define-pmacro (set-memory-bit mach base bitno value)
+  (sequence ((USI addr))
+           (set addr (add base (div bitno 8)))
+           (set (mem-mach mach QI addr)
+                (or (and (mem-mach mach QI addr)
+                         (inv (sll 1 (mod bitno 8))))
+                    (sll (and QI value 1) (mod bitno 8)))))
+)
+
+;-------------------------------------------------------------
+; Rn direct
+;-------------------------------------------------------------
+
+(define-derived-operand
+  (name bit16-Rn-direct)
+  (comment "m16c Rn direct bit")
+  (attrs (machine 16))
+  (mode BI)
+  (args (Bitno16R Bit16Rn))
+  (syntax "$Bitno16R,$Bit16Rn")
+  (base-ifield f-12-4)
+  (encoding (+ (f-12-2 0) Bit16Rn Bitno16R))
+  (ifield-assertion (eq f-12-2 0))
+  (getter (get-register-bit Bit16Rn Bitno16R))
+  (setter (set-register-bit Bit16Rn Bitno16R newval))
+)
+
+(define-pmacro (bit32-Rn-direct-operand group base)
+  (begin
+    (define-derived-operand
+      (name (.sym bit32-Rn-direct- group))
+      (comment "m32c Rn direct bit")
+      (attrs (machine 32))
+      (mode BI)
+      (args ((.sym Bitno32 group) (.sym Bit32Rn group)))
+      (syntax (.str "$Bitno32" group ",$Bit32Rn" group))
+      (base-ifield (.sym f- base -6))
+      (encoding (+ ((.sym f- base -3) 4) (.sym Bit32Rn group) (.sym Bitno32 group)))
+      (ifield-assertion (eq (.sym f- base -3) 4))
+      (getter (get-register-bit (.sym Bit32Rn group) (.sym Bitno32 group)))
+      (setter (set-register-bit (.sym Bit32Rn group) (.sym Bitno32 group) newval))
+    )
+  )
+)
+
+(bit32-Rn-direct-operand Unprefixed  4)
+(bit32-Rn-direct-operand   Prefixed 12)
+
+;-------------------------------------------------------------
+; An direct
+;-------------------------------------------------------------
+
+(define-derived-operand
+  (name bit16-An-direct)
+  (comment "m16c An direct bit")
+  (attrs (machine 16))
+  (mode BI)
+  (args (Bitno16R Bit16An))
+  (syntax "$Bitno16R,$Bit16An")
+  (base-ifield f-12-4)
+  (encoding (+ (f-12-2 1) (f-14-1 0) Bit16An Bitno16R))
+  (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 0)))
+  (getter (get-register-bit Bit16An Bitno16R))
+  (setter (set-register-bit Bit16An Bitno16R newval))
+)
+
+(define-pmacro (bit32-An-direct-operand group base1 base2)
+  (begin
+    (define-derived-operand
+      (name (.sym bit32-An-direct- group))
+      (comment "m32c An direct bit")
+      (attrs (machine 32))
+      (mode BI)
+      (args ((.sym Bitno32 group) (.sym Bit32An group)))
+      (syntax (.str "$Bitno32" group ",$Bit32An" group))
+      (base-ifield (.sym f- base1 -6))
+      (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 1) (.sym Bit32An group) (.sym Bitno32 group)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 1)))
+      (getter (get-register-bit (.sym Bit32An group) (.sym Bitno32 group)))
+      (setter (set-register-bit (.sym Bit32An group) (.sym Bitno32 group) newval))
+    )
+  )
+)
+
+(bit32-An-direct-operand Unprefixed  4  8)
+(bit32-An-direct-operand   Prefixed 12 16)
+
+;-------------------------------------------------------------
+; An indirect
+;-------------------------------------------------------------
+
+(define-derived-operand
+  (name bit16-An-indirect)
+  (comment "m16c An indirect bit")
+  (attrs (machine 16))
+  (mode BI)
+  (args (Bit16An))
+  (syntax "[$Bit16An]")
+  (base-ifield f-12-4)
+  (encoding (+ (f-12-2 1) (f-14-1 1) Bit16An))
+  (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 1)))
+  (getter (get-memory-bit 16 0 Bit16An))
+  (setter (set-memory-bit 16 0 Bit16An newval))
+)
+
+(define-pmacro (bit32-An-indirect-operand group base1 base2)
+  (begin
+    (define-derived-operand
+      (name (.sym bit32-An-indirect- group))
+      (comment "m32c An indirect destination ")
+      (attrs (machine 32))
+      (mode BI)
+      (args ((.sym Bitno32 group) (.sym Bit32An group)))
+      (syntax (.str "$Bitno32" group ",[$Bit32An" group "]"))
+      (base-ifield (.sym f- base1 -6))
+      (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 0) (.sym Bit32An group) (.sym Bitno32 group)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 0)))
+      (getter (get-memory-bit 32 (.sym Bit32An group) (.sym Bitno32 group)))
+      (setter (set-memory-bit 32 (.sym Bit32An group) (.sym Bitno32 group) newval))
+    )
+  )
+)
+
+(bit32-An-indirect-operand Unprefixed  4  8)
+(bit32-An-indirect-operand   Prefixed 12 16)
+
+;-------------------------------------------------------------
+; dsp:d[r] relative
+;-------------------------------------------------------------
+
+(define-pmacro (bit16-relative-operand offset)
+  (begin
+    (define-derived-operand
+      (name (.sym bit16- offset -8-SB-relative))
+      (comment (.str "m16c dsp:8[sb] relative bit " xmode))
+      (attrs (machine 16))
+      (mode BI)
+      (args ((.sym BitBase16- offset -u8)))
+      (syntax (.str "${BitBase16-" offset "-u8}[sb]"))
+      (base-ifield f-12-4)
+      (encoding (+ (f-12-4 #xA) (.sym BitBase16- offset -u8)))
+      (ifield-assertion (eq f-12-4 #xA))
+      (getter (get-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u8)))
+      (setter (set-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u8) newval))
+    )
+    (define-derived-operand
+      (name (.sym bit16- offset -16-SB-relative))
+      (comment (.str "m16c dsp:16[sb] relative bit " xmode))
+      (attrs (machine 16))
+      (mode BI)
+      (args ((.sym BitBase16- offset -u16)))
+      (syntax (.str "${BitBase16-" offset "-u16}[sb]"))
+      (base-ifield f-12-4)
+      (encoding (+ (f-12-4 #xE) (.sym BitBase16- offset -u16)))
+      (ifield-assertion (eq f-12-4 #xE))
+      (getter (get-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u16)))
+      (setter (set-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u16) newval))
+    )
+    (define-derived-operand
+      (name (.sym bit16- offset -8-FB-relative))
+      (comment (.str "m16c dsp:8[fb] relative bit " xmode))
+      (attrs (machine 16))
+      (mode BI)
+      (args ((.sym BitBase16- offset -s8)))
+      (syntax (.str "${BitBase16-" offset "-s8}[fb]"))
+      (base-ifield f-12-4)
+      (encoding (+ (f-12-4 #xB) (.sym BitBase16- offset -s8)))
+      (ifield-assertion (eq f-12-4 #xB))
+      (getter (get-memory-bit 16 (reg h-fb) (.sym BitBase16- offset -s8)))
+      (setter (set-memory-bit 16 (reg h-fb) (.sym BitBase16- offset -s8) newval))
+    )
+    (define-derived-operand
+      (name (.sym bit16- offset -8-An-relative))
+      (comment (.str "m16c dsp:8[An] relative bit " xmode))
+      (attrs (machine 16))
+      (mode BI)
+      (args (Bit16An (.sym Dsp- offset -u8)))
+      (syntax (.str "${Dsp-" offset "-u8}[$Bit16An]"))
+      (base-ifield f-12-4)
+      (encoding (+ (f-12-2 2) (f-14-1 0) (.sym Dsp- offset -u8) Bit16An))
+      (ifield-assertion (andif (eq f-12-2 2) (eq f-14-1 0)))
+      (getter (get-memory-bit 16 (.sym Dsp- offset -u8) Bit16An))
+      (setter (set-memory-bit 16 (.sym Dsp- offset -u8) Bit16An newval))
+    )
+    (define-derived-operand
+      (name (.sym bit16- offset -16-An-relative))
+      (comment (.str "m16c dsp:16[An] relative bit " xmode))
+      (attrs (machine 16))
+      (mode BI)
+      (args (Bit16An (.sym Dsp- offset -u16)))
+      (syntax (.str "${Dsp-" offset "-u16}[$Bit16An]"))
+      (base-ifield f-12-4)
+      (encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u16) Bit16An))
+      (ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0)))
+      (getter (get-memory-bit 16 (.sym Dsp- offset -u16) Bit16An))
+      (setter (set-memory-bit 16 (.sym Dsp- offset -u16) Bit16An newval))
+    )
+  )
+)
+
+(bit16-relative-operand 16)
+
+(define-pmacro (bit32-relative-operand offset group base1 base2)
+  (begin
+    (define-derived-operand
+      (name (.sym bit32- offset -11-SB-relative- group))
+      (comment "m32c bit,base:11[sb] relative bit")
+      (attrs (machine 32))
+      (mode BI)
+      (args ((.sym BitBase32- offset -u11- group)))
+      (syntax (.str "${BitBase32-" offset "-u11-" group "}[sb]"))
+      (base-ifield (.sym f- base1 -12))
+      (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 2) (.sym BitBase32- offset -u11- group)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 2)))
+      (getter (get-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u11- group)))
+      (setter (set-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u11- group) newval))
+    )
+    (define-derived-operand
+      (name (.sym bit32- offset -19-SB-relative- group))
+      (comment "m32c bit,base:19[sb] relative bit")
+      (attrs (machine 32))
+      (mode BI)
+      (args ((.sym BitBase32- offset -u19- group)))
+      (syntax (.str "${BitBase32-" offset "-u19-" group "}[sb]"))
+      (base-ifield (.sym f- base1 -12))
+      (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 2) (.sym BitBase32- offset -u19- group)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 2)))
+      (getter (get-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u19- group)))
+      (setter (set-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u19- group) newval))
+    )
+    (define-derived-operand
+      (name (.sym bit32- offset -11-FB-relative- group))
+      (comment "m32c bit,base:11[fb] relative bit")
+      (attrs (machine 32))
+      (mode BI)
+      (args ((.sym BitBase32- offset -s11- group)))
+      (syntax (.str "${BitBase32-" offset "-s11-" group "}[fb]"))
+      (base-ifield (.sym f- base1 -12))
+      (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 3) (.sym BitBase32- offset -s11- group)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 3)))
+      (getter (get-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s11- group)))
+      (setter (set-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s11- group) newval))
+    )
+    (define-derived-operand
+      (name (.sym bit32- offset -19-FB-relative- group))
+      (comment "m32c bit,base:19[fb] relative bit")
+      (attrs (machine 32))
+      (mode BI)
+      (args ((.sym BitBase32- offset -s19- group)))
+      (syntax (.str "${BitBase32-" offset "-s19-" group "}[fb]"))
+      (base-ifield (.sym f- base1 -12))
+      (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 3) (.sym BitBase32- offset -s19- group)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 3)))
+      (getter (get-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s19- group)))
+      (setter (set-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s19- group) newval))
+    )
+    (define-derived-operand
+      (name (.sym bit32- offset -11-An-relative- group))
+      (comment "m32c bit,base:11[An] relative bit")
+      (attrs (machine 32))
+      (mode BI)
+      (args ((.sym BitBase32- offset -u11- group) (.sym Bit32An group)))
+      (syntax (.str "${BitBase32-" offset "-u11-" group "}[$Bit32An" group "]"))
+      (base-ifield (.sym f- base1 -12))
+      (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -1) 0) (.sym BitBase32- offset -u11- group) (.sym Bit32An group)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -1) 0)))
+      (getter (get-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u11- group)))
+      (setter (set-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u11- group) newval))
+    )
+    (define-derived-operand
+      (name (.sym bit32- offset -19-An-relative- group))
+      (comment "m32c bit,base:19[An] relative bit")
+      (attrs (machine 32))
+      (mode BI)
+      (args ((.sym BitBase32- offset -u19- group) (.sym Bit32An group)))
+      (syntax (.str "${BitBase32-" offset "-u19-" group "}[$Bit32An" group "]"))
+      (base-ifield (.sym f- base1 -12))
+      (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -1) 0) (.sym BitBase32- offset -u19- group) (.sym Bit32An group)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -1) 0)))
+      (getter (get-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u19- group)))
+      (setter (set-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u19- group) newval))
+    )
+    (define-derived-operand
+      (name (.sym bit32- offset -27-An-relative- group))
+      (comment "m32c bit,base:27[An] relative bit")
+      (attrs (machine 32))
+      (mode BI)
+      (args ((.sym BitBase32- offset -u27- group) (.sym Bit32An group)))
+      (syntax (.str "${BitBase32-" offset "-u27-" group "}[$Bit32An" group "]"))
+      (base-ifield (.sym f- base1 -12))
+      (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -1) 0) (.sym BitBase32- offset -u27- group) (.sym Bit32An group)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -1) 0)))
+      (getter (get-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u27- group)))
+      (setter (set-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u27- group) newval))
+    )
+  )
+)
+
+(bit32-relative-operand 16 Unprefixed  4  8)
+(bit32-relative-operand 24   Prefixed 12 16)
+
+(define-derived-operand
+  (name bit16-11-SB-relative-S)
+  (comment "m16c bit,base:11[sb] relative bit")
+  (attrs (machine 16))
+  (mode BI)
+  (args (BitBase16-8-u11-S))
+  (syntax "${BitBase16-8-u11-S}[sb]")
+  (base-ifield (.sym f-5-3))
+  (encoding (+ BitBase16-8-u11-S))
+;  (ifield-assertion (#t))
+  (getter (get-memory-bit 16 (reg h-sb) BitBase16-8-u11-S))
+  (setter (set-memory-bit 16 (reg h-sb) BitBase16-8-u11-S newval))
+)
+
+(define-derived-operand
+  (name Rn16-push-S-derived)
+  (comment "m16c r0[lh] for push,pop short version")
+  (attrs (machine 16))
+  (mode QI)
+  (args (Rn16-push-S))
+  (syntax "${Rn16-push-S}")
+  (base-ifield (.sym f-4-1))
+  (encoding (+ Rn16-push-S))
+;  (ifield-assertion (#t))
+  (getter (trunc QI Rn16-push-S))
+  (setter (set Rn16-push-S newval))
+)
+
+(define-derived-operand
+  (name An16-push-S-derived)
+  (comment "m16c r0[lh] for push,pop short version")
+  (attrs (machine 16))
+  (mode HI)
+  (args (An16-push-S))
+  (syntax "${An16-push-S}")
+  (base-ifield (.sym f-4-1))
+  (encoding (+ An16-push-S))
+;  (ifield-assertion (#t))
+  (getter (trunc QI An16-push-S))
+  (setter (set An16-push-S newval))
+)
+
+;-------------------------------------------------------------
+; Absolute address
+;-------------------------------------------------------------
+
+(define-pmacro (bit16-absolute offset)
+  (begin
+    (define-derived-operand
+      (name (.sym bit16- offset -16-absolute))
+      (comment "m16c absolute address")
+      (attrs (machine 16))
+      (mode BI)
+      (args ((.sym BitBase16- offset -u16)))
+      (syntax (.str "${BitBase16-" offset "-u16}"))
+      (base-ifield f-12-4)
+      (encoding (+ (f-12-4 #xF) (.sym BitBase16- offset -u16)))
+      (ifield-assertion (eq f-12-4 #xF))
+      (getter (get-memory-bit 16 0 (.sym BitBase16- offset -u16)))
+      (setter (set-memory-bit 16 0 (.sym BitBase16- offset -u16) newval))
+    )
+  )
+)
+
+(bit16-absolute 16)
+
+(define-pmacro (bit32-absolute offset group base1 base2)
+  (begin
+    (define-derived-operand
+      (name (.sym bit32- offset -19-absolute- group))
+      (comment "m32c absolute address bit")
+      (attrs (machine 32))
+      (mode BI)
+      (args ((.sym BitBase32- offset -u19- group)))
+      (syntax (.str "${BitBase32-" offset "-u19-" group "}"))
+      (base-ifield (.sym f- base1 -12))
+      (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym BitBase32- offset -u19- group)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3)))
+      (getter (get-memory-bit 32 0 (.sym BitBase32- offset -u19- group)))
+      (setter (set-memory-bit 32 0 (.sym BitBase32- offset -u19- group) newval))
+    )
+    (define-derived-operand
+      (name (.sym bit32- offset -27-absolute- group))
+      (comment "m32c absolute address bit")
+      (attrs (machine 32))
+      (mode BI)
+      (args ((.sym BitBase32- offset -u27- group)))
+      (syntax (.str "${BitBase32-" offset "-u27-" group "}"))
+      (base-ifield (.sym f- base1 -12))
+      (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym BitBase32- offset -u27- group)))
+      (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2)))
+      (getter (get-memory-bit 32 0 (.sym BitBase32- offset -u27- group)))
+      (setter (set-memory-bit 32 0 (.sym BitBase32- offset -u27- group) newval))
+    )
+  )
+)
+
+(bit32-absolute 16 Unprefixed  4  8)
+(bit32-absolute 24   Prefixed 12 16)
+
+;-------------------------------------------------------------
+; Destination operands for short fomat insns
+;-------------------------------------------------------------
+
+(define-derived-operand
+  (name dst16-3-S-R0l-direct-QI)
+  (comment "m16c R0l direct QI")
+  (attrs (machine 16))
+  (mode QI)
+  (args (R0l))
+  (syntax "r0l")
+  (base-ifield f-5-3)
+  (encoding (+ (f-5-3 4)))
+  (ifield-assertion (eq f-5-3 4))
+  (getter (trunc QI R0l))
+  (setter (set R0l newval))
+)
+(define-derived-operand
+  (name dst16-3-S-R0h-direct-QI)
+  (comment "m16c R0h direct QI")
+  (attrs (machine 16))
+  (mode QI)
+  (args (R0h))
+  (syntax "r0h")
+  (base-ifield f-5-3)
+  (encoding (+ (f-5-3 3)))
+  (ifield-assertion (eq f-5-3 3))
+  (getter (trunc QI R0h))
+  (setter (set R0h newval))
+)
+(define-derived-operand
+  (name dst16-3-S-8-8-SB-relative-QI)
+  (comment "m16c SB relative QI")
+  (attrs (machine 16))
+  (mode QI)
+  (args (Dsp-8-u8))
+  (syntax "${Dsp-8-u8}[sb]")
+  (base-ifield f-5-3)
+  (encoding (+ (f-5-3 5) Dsp-8-u8))
+  (ifield-assertion (eq f-5-3 5))
+  (getter (mem16 QI (add Dsp-8-u8 (reg h-sb))))
+  (setter (set (mem16 QI (add Dsp-8-u8 (reg h-sb))) newval))
+)
+(define-derived-operand
+  (name dst16-3-S-8-8-FB-relative-QI)
+  (comment "m16c FB relative QI")
+  (attrs (machine 16))
+  (mode QI)
+  (args (Dsp-8-s8))
+  (syntax "${Dsp-8-s8}[fb]")
+  (base-ifield f-5-3)
+  (encoding (+ (f-5-3 6) Dsp-8-s8))
+  (ifield-assertion (eq f-5-3 6))
+  (getter (mem16 QI (add Dsp-8-s8 (reg h-fb))))
+  (setter (set (mem16 QI (add Dsp-8-s8 (reg h-fb))) newval))
+)
+(define-derived-operand
+  (name dst16-3-S-8-16-absolute-QI)
+  (comment "m16c absolute address QI")
+  (attrs (machine 16))
+  (mode QI)
+  (args (Dsp-8-u16))
+  (syntax "${Dsp-8-u16}")
+  (base-ifield f-5-3)
+  (encoding (+ (f-5-3 7) Dsp-8-u16))
+  (ifield-assertion (eq f-5-3 7))
+  (getter (mem16 QI Dsp-8-u16))
+  (setter (set (mem16 QI Dsp-8-u16) newval))
+)
+(define-derived-operand
+  (name dst16-3-S-16-8-SB-relative-QI)
+  (comment "m16c SB relative QI")
+  (attrs (machine 16))
+  (mode QI)
+  (args (Dsp-16-u8))
+  (syntax "${Dsp-16-u8}[sb]")
+  (base-ifield f-5-3)
+  (encoding (+ (f-5-3 5) Dsp-16-u8))
+  (ifield-assertion (eq f-5-3 5))
+  (getter (mem16 QI (add Dsp-16-u8 (reg h-sb))))
+  (setter (set (mem16 QI (add Dsp-16-u8 (reg h-sb))) newval))
+)
+(define-derived-operand
+  (name dst16-3-S-16-8-FB-relative-QI)
+  (comment "m16c FB relative QI")
+  (attrs (machine 16))
+  (mode QI)
+  (args (Dsp-16-s8))
+  (syntax "${Dsp-16-s8}[fb]")
+  (base-ifield f-5-3)
+  (encoding (+ (f-5-3 6) Dsp-16-s8))
+  (ifield-assertion (eq f-5-3 6))
+  (getter (mem16 QI (add Dsp-16-s8 (reg h-fb))))
+  (setter (set (mem16 QI (add Dsp-16-s8 (reg h-fb))) newval))
+)
+(define-derived-operand
+  (name dst16-3-S-16-16-absolute-QI)
+  (comment "m16c absolute address QI")
+  (attrs (machine 16))
+  (mode QI)
+  (args (Dsp-16-u16))
+  (syntax "${Dsp-16-u16}")
+  (base-ifield f-5-3)
+  (encoding (+ (f-5-3 7) Dsp-16-u16))
+  (ifield-assertion (eq f-5-3 7))
+  (getter (mem16 QI Dsp-16-u16))
+  (setter (set (mem16 QI Dsp-16-u16) newval))
+)
+(define-derived-operand
+  (name srcdst16-r0l-r0h-S-derived)
+  (comment "m16c r0l/r0h operand for short format insns")
+  (attrs (machine 16))
+  (mode SI)
+  (args (SrcDst16-r0l-r0h-S-normal))
+  (syntax "${SrcDst16-r0l-r0h-S-normal}")
+  (base-ifield f-6-3)
+  (encoding (+ (f-6-2 0) SrcDst16-r0l-r0h-S-normal))
+  (ifield-assertion (eq f-6-2 0))
+  (getter (trunc SI SrcDst16-r0l-r0h-S-normal))
+  (setter ()) ; no setter
+)
+(define-derived-operand
+  (name dst32-2-S-R0l-direct-QI)
+  (comment "m32c R0l direct QI")
+  (attrs (machine 32))
+  (mode QI)
+  (args (R0l))
+  (syntax "r0l")
+  (base-ifield f-2-2)
+  (encoding (+ (f-2-2 0)))
+  (ifield-assertion (eq f-2-2 0))
+  (getter (trunc QI R0l))
+  (setter (set R0l newval))
+)
+(define-derived-operand
+  (name dst32-2-S-R0-direct-HI)
+  (comment "m32c R0 direct HI")
+  (attrs (machine 32))
+  (mode HI)
+  (args (R0))
+  (syntax "r0")
+  (base-ifield f-2-2)
+  (encoding (+ (f-2-2 0)))
+  (ifield-assertion (eq f-2-2 0))
+  (getter (trunc HI R0))
+  (setter (set R0 newval))
+)
+(define-derived-operand
+  (name dst32-1-S-A0-direct-HI)
+  (comment "m32c A0 direct HI")
+  (attrs (machine 32))
+  (mode HI)
+  (args (A0))
+  (syntax "a0")
+  (base-ifield f-7-1)
+  (encoding (+ (f-7-1 0)))
+  (ifield-assertion (eq f-7-1 0))
+  (getter (trunc HI A0))
+  (setter (set A0 newval))
+)
+(define-derived-operand
+  (name dst32-1-S-A1-direct-HI)
+  (comment "m32c A1 direct HI")
+  (attrs (machine 32))
+  (mode HI)
+  (args (A1))
+  (syntax "a1")
+  (base-ifield f-7-1)
+  (encoding (+ (f-7-1 1)))
+  (ifield-assertion (eq f-7-1 1))
+  (getter (trunc HI A1))
+  (setter (set A1 newval))
+)
+(define-pmacro (dst32-2-S-operands xmode)
+  (begin
+    (define-derived-operand
+      (name (.sym dst32-2-S-8-SB-relative- xmode))
+      (comment "m32c SB relative for short binary insns")
+      (attrs (machine 32))
+      (mode xmode)
+      (args (Dsp-8-u8))
+      (syntax "${Dsp-8-u8}[sb]")
+      (base-ifield f-2-2)
+      (encoding (+ (f-2-2 2) Dsp-8-u8))
+      (ifield-assertion (eq f-2-2 2))
+      (getter (c-call xmode (.str "operand_getter_" xmode) sb Dsp-8-u8))
+      (setter (c-call DFLT (.str "operand_setter_" xmode) newval sb Dsp-8-u8))
+;      (getter (mem32 xmode (add Dsp-8-u8 (reg h-sb))))
+;      (setter (set (mem32 xmode (add Dsp-8-u8 (reg h-sb))) newval))
+    )
+    (define-derived-operand
+      (name (.sym dst32-2-S-8-FB-relative- xmode))
+      (comment "m32c FB relative for short binary insns")
+      (attrs (machine 32))
+      (mode xmode)
+      (args (Dsp-8-s8))
+      (syntax "${Dsp-8-s8}[fb]")
+      (base-ifield f-2-2)
+      (encoding (+ (f-2-2 3) Dsp-8-s8))
+      (ifield-assertion (eq f-2-2 3))
+      (getter (c-call xmode (.str "operand_getter_" xmode) fb Dsp-8-s8))
+      (setter (c-call DFLT (.str "operand_setter_" xmode) newval fb Dsp-8-s8))
+;      (getter (mem32 xmode (add Dsp-8-s8 (reg h-fb))))
+;      (setter (set (mem32 xmode (add Dsp-8-s8 (reg h-fb))) newval))
+    )
+    (define-derived-operand
+      (name (.sym dst32-2-S-16-absolute- xmode))
+      (comment "m32c absolute address for short binary insns")
+      (attrs (machine 32))
+      (mode xmode)
+      (args (Dsp-8-u16))
+      (syntax "${Dsp-8-u16}")
+      (base-ifield f-2-2)
+      (encoding (+ (f-2-2 1) Dsp-8-u16))
+      (ifield-assertion (eq f-2-2 1))
+      (getter (c-call xmode (.str "operand_getter_" xmode) (const 0) Dsp-8-u16))
+      (setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) Dsp-8-u16))
+;      (getter (mem32 xmode Dsp-8-u16))
+;      (setter (set (mem32 xmode Dsp-8-u16) newval))
+    )
+;     (define-derived-operand
+;       (name (.sym dst32-2-S-8-SB-relative-indirect- xmode))
+;       (comment "m32c SB relative for short binary insns")
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (args (Dsp-16-u8))
+;       (syntax "[${Dsp-16-u8}[sb]]")
+;       (base-ifield f-10-2)
+;       (encoding (+ (f-10-2 2) Dsp-16-u8))
+;       (ifield-assertion (eq f-10-2 2))
+;       (getter (mem32 xmode (indirect-addr (add Dsp-16-u8 (reg h-sb)))))
+;       (setter (set (mem32 xmode (indirect-addr (add Dsp-16-u8 (reg h-sb)))) newval))
+;     )
+;     (define-derived-operand
+;       (name (.sym dst32-2-S-8-FB-relative-indirect- xmode))
+;       (comment "m32c FB relative for short binary insns")
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (args (Dsp-16-s8))
+;       (syntax "[${Dsp-16-s8}[fb]]")
+;       (base-ifield f-10-2)
+;       (encoding (+ (f-10-2 3) Dsp-16-s8))
+;       (ifield-assertion (eq f-10-2 3))
+;       (getter (mem32 xmode (indirect-addr (add Dsp-16-s8 (reg h-fb)))))
+;       (setter (set (mem32 xmode (indirect-addr (add Dsp-16-s8 (reg h-fb)))) newval))
+;     )
+;     (define-derived-operand
+;       (name (.sym dst32-2-S-16-absolute-indirect- xmode))
+;       (comment "m32c absolute address for short binary insns")
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (args (Dsp-16-u16))
+;       (syntax "[${Dsp-16-u16}]")
+;       (base-ifield f-10-2)
+;       (encoding (+ (f-10-2 1) Dsp-16-u16))
+;       (ifield-assertion (eq f-10-2 1))
+;       (getter (mem32 xmode (indirect-addr Dsp-16-u16)))
+;       (setter (set (mem32 xmode (indirect-addr Dsp-16-u16)) newval))
+;     )
+  )
+)
+
+(dst32-2-S-operands QI)
+(dst32-2-S-operands HI)
+(dst32-2-S-operands SI)
+    
+;=============================================================
+; Anyof operands
+;-------------------------------------------------------------
+; Source operands with no additional fields
+;-------------------------------------------------------------
+
+(define-pmacro (src16-basic-operand xmode)
+  (begin
+    (define-anyof-operand
+      (name (.sym src16-basic- xmode))
+      (comment (.str "m16c source operand of size " xmode " with no additional fields"))
+      (attrs (machine 16))
+      (mode xmode)
+      (choices
+       (.sym src16-Rn-direct- xmode)
+       (.sym src16-An-direct- xmode)
+       (.sym src16-An-indirect- xmode)
+      )
+    )
+  )
+)
+(src16-basic-operand QI)
+(src16-basic-operand HI)
+
+(define-pmacro (src32-basic-operand xmode)
+  (begin
+    (define-anyof-operand
+      (name (.sym src32-basic-Unprefixed- xmode))
+      (comment (.str "m32c destination operand of size " xmode " with no additional fields"))
+      (attrs (machine 32))
+      (mode xmode)
+      (choices
+       (.sym src32-Rn-direct-Unprefixed- xmode)
+       (.sym src32-An-direct-Unprefixed- xmode)
+       (.sym src32-An-indirect-Unprefixed- xmode)
+      )
+    )
+    (define-anyof-operand
+      (name (.sym src32-basic-Prefixed- xmode))
+      (comment (.str "m32c destination operand of size " xmode " with no additional fields"))
+      (attrs (machine 32))
+      (mode xmode)
+      (choices
+       (.sym src32-Rn-direct-Prefixed- xmode)
+       (.sym src32-An-direct-Prefixed- xmode)
+       (.sym src32-An-indirect-Prefixed- xmode)
+      )
+    )
+;     (define-anyof-operand
+;       (name (.sym src32-basic-indirect- xmode))
+;       (comment (.str "m32c destination operand of size " xmode " indirect with no additional fields"))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (choices
+;        (.sym src32-An-indirect-indirect- xmode)
+;       )
+;     )
+  )
+)
+
+(src32-basic-operand QI)
+(src32-basic-operand HI)
+(src32-basic-operand SI)
+
+(define-anyof-operand
+  (name src32-basic-ExtPrefixed-QI)
+  (comment "m32c source operand of size QI with no additional fields")
+  (attrs (machine 32))
+  (mode QI)
+  (choices
+   src32-Rn-direct-Prefixed-QI
+   src32-An-indirect-Prefixed-QI
+  )
+)
+
+;-------------------------------------------------------------
+; Source operands with additional fields at offset 16 bits
+;-------------------------------------------------------------
+
+(define-pmacro (src16-16-operand xmode)
+  (begin
+    (define-anyof-operand
+      (name (.sym src16-16-8- xmode))
+      (comment (.str "m16c source operand of size " xmode " with additional 8 bit fields at offset 16"))
+      (attrs (machine 16))
+      (mode xmode)
+      (choices
+       (.sym src16-16-8-An-relative- xmode)
+       (.sym src16-16-8-SB-relative- xmode)
+       (.sym src16-16-8-FB-relative- xmode)
+      )
+    )
+    (define-anyof-operand
+      (name (.sym src16-16-16- xmode))
+      (comment (.str "m16c source operand of size " xmode " with additional 16 bit fields at offset 16"))
+      (attrs (machine 16))
+      (mode xmode)
+      (choices
+       (.sym src16-16-16-An-relative- xmode)
+       (.sym src16-16-16-SB-relative- xmode)
+       (.sym src16-16-16-absolute- xmode)
+      )
+    )
+  )
+)
+(src16-16-operand QI)
+(src16-16-operand HI)
+
+(define-pmacro (src32-16-operand xmode)
+  (begin
+    (define-anyof-operand
+      (name (.sym src32-16-8-Unprefixed- xmode))
+      (comment (.str "m32c source operand of size " xmode " with additional 8 bit fields at offset 16"))
+      (attrs (machine 32))
+      (mode xmode)
+      (choices
+       (.sym src32-16-8-An-relative-Unprefixed- xmode)
+       (.sym src32-16-8-SB-relative-Unprefixed- xmode)
+       (.sym src32-16-8-FB-relative-Unprefixed- xmode)
+      )
+    )
+    (define-anyof-operand
+      (name (.sym src32-16-16-Unprefixed- xmode))
+      (comment (.str "m32c source operand of size " xmode " with additional 16 bit fields at offset 16"))
+      (attrs (machine 32))
+      (mode xmode)
+      (choices
+       (.sym src32-16-16-An-relative-Unprefixed- xmode)
+       (.sym src32-16-16-SB-relative-Unprefixed- xmode)
+       (.sym src32-16-16-FB-relative-Unprefixed- xmode)
+       (.sym src32-16-16-absolute-Unprefixed- xmode)
+      )
+    )
+    (define-anyof-operand
+      (name (.sym src32-16-24-Unprefixed- xmode))
+      (comment (.str "m32c source operand of size " xmode " with additional 24 bit fields at offset 16"))
+      (attrs (machine 32))
+      (mode xmode)
+      (choices
+       (.sym src32-16-24-An-relative-Unprefixed- xmode)
+       (.sym src32-16-24-absolute-Unprefixed- xmode)
+      )
+    )
+  )
+)
+
+(src32-16-operand QI)
+(src32-16-operand HI)
+(src32-16-operand SI)
+
+;-------------------------------------------------------------
+; Source operands with additional fields at offset 24 bits
+;-------------------------------------------------------------
+
+(define-pmacro (src-24-operand group xmode)
+  (begin
+    (define-anyof-operand
+      (name (.sym src32-24-8- group - xmode))
+      (comment (.str "m32c source operand of size " xmode " with additional 8 bit fields at offset 24"))
+      (attrs (machine 32))
+      (mode xmode)
+      (choices
+       (.sym src32-24-8-An-relative- group - xmode)
+       (.sym src32-24-8-SB-relative- group - xmode)
+       (.sym src32-24-8-FB-relative- group - xmode)
+      )
+    )
+    (define-anyof-operand
+      (name (.sym src32-24-16- group - xmode))
+      (comment (.str "m32c source operand of size " xmode " with additional 16 bit fields at offset 16"))
+      (attrs (machine 32))
+      (mode xmode)
+      (choices
+       (.sym src32-24-16-An-relative- group - xmode)
+       (.sym src32-24-16-SB-relative- group - xmode)
+       (.sym src32-24-16-FB-relative- group - xmode)
+       (.sym src32-24-16-absolute- group - xmode)
+      )
+    )
+    (define-anyof-operand
+      (name (.sym src32-24-24- group - xmode))
+      (comment (.str "m32c source operand of size " xmode " with additional 24 bit fields at offset 16"))
+      (attrs (machine 32))
+      (mode xmode)
+      (choices
+       (.sym src32-24-24-An-relative- group - xmode)
+       (.sym src32-24-24-absolute- group - xmode)
+      )
+    )
+  )
+)
+
+(src-24-operand Prefixed   QI)
+(src-24-operand Prefixed   HI)
+(src-24-operand Prefixed   SI)
+
+(define-pmacro (src-24-indirect-operand xmode)
+  (begin
+;     (define-anyof-operand
+;       (name (.sym src32-24-8-indirect- xmode))
+;       (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (choices
+;        (.sym src32-24-8-An-relative-indirect- xmode)
+;        (.sym src32-24-8-SB-relative-indirect- xmode)
+;        (.sym src32-24-8-FB-relative-indirect- xmode)
+;       )
+;     )
+;     (define-anyof-operand
+;       (name (.sym src32-24-16-indirect- xmode))
+;       (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (choices
+;        (.sym src32-24-16-An-relative-indirect- xmode)
+;        (.sym src32-24-16-SB-relative-indirect- xmode)
+;        (.sym src32-24-16-FB-relative-indirect- xmode)
+;       )
+;     )
+;     (define-anyof-operand
+;       (name (.sym src32-24-24-indirect- xmode))
+;       (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (choices
+;        (.sym src32-24-24-An-relative-indirect- xmode)
+;       )
+;     )
+;     (define-anyof-operand
+;       (name (.sym src32-24-16-absolute-indirect- xmode))
+;       (comment (.str "m32c source operand of size " xmode " 16 bit absolute indirect"))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (choices
+;        (.sym src32-24-16-absolute-indirect-derived- xmode)
+;       )
+;     )
+;     (define-anyof-operand
+;       (name (.sym src32-24-24-absolute-indirect- xmode))
+;       (comment (.str "m32c source operand of size " xmode " 24 bit absolute indirect"))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (choices
+;        (.sym src32-24-24-absolute-indirect-derived- xmode)
+;       )
+;     )
+  )
+)
+
+; (src-24-indirect-operand QI)
+; (src-24-indirect-operand HI)
+; (src-24-indirect-operand SI)
+
+;-------------------------------------------------------------
+; Destination operands with no additional fields
+;-------------------------------------------------------------
+
+(define-pmacro (dst16-basic-operand xmode)
+  (begin
+    (define-anyof-operand
+      (name (.sym dst16-basic- xmode))
+      (comment (.str "m16c destination operand of size " xmode " with no additional fields"))
+      (attrs (machine 16))
+      (mode xmode)
+      (choices
+       (.sym dst16-Rn-direct- xmode)
+       (.sym dst16-An-direct- xmode)
+       (.sym dst16-An-indirect- xmode)
+      )
+    )
+  )
+)
+
+(dst16-basic-operand QI)
+(dst16-basic-operand HI)
+(dst16-basic-operand SI)
+
+(define-pmacro (dst32-basic-operand xmode)
+  (begin
+    (define-anyof-operand
+      (name (.sym dst32-basic-Unprefixed- xmode))
+      (comment (.str "m32c destination operand of size " xmode " with no additional fields"))
+      (attrs (machine 32))
+      (mode xmode)
+      (choices
+       (.sym dst32-Rn-direct-Unprefixed- xmode)
+       (.sym dst32-An-direct-Unprefixed- xmode)
+       (.sym dst32-An-indirect-Unprefixed- xmode)
+      )
+    )
+    (define-anyof-operand
+      (name (.sym dst32-basic-Prefixed- xmode))
+      (comment (.str "m32c destination operand of size " xmode " with no additional fields"))
+      (attrs (machine 32))
+      (mode xmode)
+      (choices
+       (.sym dst32-Rn-direct-Prefixed- xmode)
+       (.sym dst32-An-direct-Prefixed- xmode)
+       (.sym dst32-An-indirect-Prefixed- xmode)
+      )
+    )
+  )
+)
+
+(dst32-basic-operand QI)
+(dst32-basic-operand HI)
+(dst32-basic-operand SI)
+
+;-------------------------------------------------------------
+; Destination operands with possible additional fields at offset 16 bits
+;-------------------------------------------------------------
+
+(define-pmacro (dst16-16-operand xmode)
+  (begin
+    (define-anyof-operand
+      (name (.sym dst16-16- xmode))
+      (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16"))
+      (attrs (machine 16))
+      (mode xmode)
+      (choices
+       (.sym dst16-Rn-direct- xmode)
+       (.sym dst16-An-direct- xmode)
+       (.sym dst16-An-indirect- xmode)
+       (.sym dst16-16-8-An-relative- xmode)
+       (.sym dst16-16-16-An-relative- xmode)
+       (.sym dst16-16-8-SB-relative- xmode)
+       (.sym dst16-16-16-SB-relative- xmode)
+       (.sym dst16-16-8-FB-relative- xmode)
+       (.sym dst16-16-16-absolute- xmode)
+      )
+    )
+    (define-anyof-operand
+      (name (.sym dst16-16-8- xmode))
+      (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16"))
+      (attrs (machine 16))
+      (mode xmode)
+      (choices
+       (.sym dst16-16-8-An-relative- xmode)
+       (.sym dst16-16-8-SB-relative- xmode)
+       (.sym dst16-16-8-FB-relative- xmode)
+      )
+    )
+    (define-anyof-operand
+      (name (.sym dst16-16-16- xmode))
+      (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16"))
+      (attrs (machine 16))
+      (mode xmode)
+      (choices
+       (.sym dst16-16-16-An-relative- xmode)
+       (.sym dst16-16-16-SB-relative- xmode)
+       (.sym dst16-16-16-absolute- xmode)
+      )
+    )
+    (define-anyof-operand
+      (name (.sym dst16-16-16sa- xmode))
+      (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16"))
+      (attrs (machine 16))
+      (mode xmode)
+      (choices
+       (.sym dst16-16-16-SB-relative- xmode)
+       (.sym dst16-16-16-absolute- xmode)
+      )
+    )
+    (define-anyof-operand
+      (name (.sym dst16-16-20ar- xmode))
+      (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16"))
+      (attrs (machine 16))
+      (mode xmode)
+      (choices
+       (.sym dst16-16-20-An-relative- xmode)
+      )
+    )
+  )
+)
+
+(dst16-16-operand QI)
+(dst16-16-operand HI)
+(dst16-16-operand SI)
+
+(define-anyof-operand
+  (name dst16-16-Ext-QI)
+  (comment "m16c destination operand of size QI for 'ext' insns with additional fields at offset 16")
+  (attrs (machine 16))
+  (mode QI)
+  (choices
+   dst16-Rn-direct-Ext-QI
+   dst16-An-indirect-Ext-QI
+   dst16-16-8-An-relative-Ext-QI
+   dst16-16-16-An-relative-Ext-QI
+   dst16-16-8-SB-relative-Ext-QI
+   dst16-16-16-SB-relative-Ext-QI
+   dst16-16-8-FB-relative-Ext-QI
+   dst16-16-16-absolute-Ext-QI
+  )
+)
+
+(define-derived-operand
+  (name dst16-An-indirect-Mova-HI)
+  (comment "m16c addressof An indirect destination HI")
+  (attrs (ISA m16c))
+  (mode HI)
+  (args (Dst16An))
+  (syntax "[$Dst16An]")
+  (base-ifield f-12-4)
+  (encoding (+ (f-12-2 1) (f-14-1 1) Dst16An))
+  (ifield-assertion
+    (andif (eq f-12-2 1) (eq f-14-1 1)))
+  (getter Dst16An)
+  (setter (nop))
+  )
+
+(define-derived-operand
+  (name dst16-16-8-An-relative-Mova-HI)
+  (comment
+    "m16c addressof dsp:8[An] relative destination HI")
+  (attrs (ISA m16c))
+  (mode HI)
+  (args (Dst16An Dsp-16-u8))
+  (syntax "${Dsp-16-u8}[$Dst16An]")
+  (base-ifield f-12-4)
+  (encoding
+    (+ (f-12-2 2) (f-14-1 0) Dsp-16-u8 Dst16An))
+  (ifield-assertion
+    (andif (eq f-12-2 2) (eq f-14-1 0)))
+  (getter (add Dsp-16-u8 Dst16An))
+  (setter (nop))
+)
+(define-derived-operand
+  (name dst16-16-16-An-relative-Mova-HI)
+  (comment
+    "m16c addressof dsp:16[An] relative destination HI")
+  (attrs (ISA m16c))
+  (mode HI)
+  (args (Dst16An Dsp-16-u16))
+  (syntax "${Dsp-16-u16}[$Dst16An]")
+  (base-ifield f-12-4)
+  (encoding
+    (+ (f-12-2 3) (f-14-1 0) Dsp-16-u16 Dst16An))
+  (ifield-assertion
+    (andif (eq f-12-2 3) (eq f-14-1 0)))
+  (getter (add Dsp-16-u16 Dst16An))
+  (setter (nop))
+  )
+(define-derived-operand
+  (name dst16-16-8-SB-relative-Mova-HI)
+  (comment
+    "m16c addressof dsp:8[sb] relative destination HI")
+  (attrs (ISA m16c))
+  (mode HI)
+  (args (Dsp-16-u8))
+  (syntax "${Dsp-16-u8}[sb]")
+  (base-ifield f-12-4)
+  (encoding (+ (f-12-4 10) Dsp-16-u8))
+  (ifield-assertion (eq f-12-4 10))
+  (getter (add Dsp-16-u8 (reg h-sb)))
+  (setter (nop))
+)
+(define-derived-operand
+  (name dst16-16-16-SB-relative-Mova-HI)
+  (comment
+    "m16c addressof dsp:16[sb] relative destination HI")
+  (attrs (ISA m16c))
+  (mode HI)
+  (args (Dsp-16-u16))
+  (syntax "${Dsp-16-u16}[sb]")
+  (base-ifield f-12-4)
+  (encoding (+ (f-12-4 14) Dsp-16-u16))
+  (ifield-assertion (eq f-12-4 14))
+  (getter (add Dsp-16-u16 (reg h-sb)))
+  (setter (nop))
+  )
+(define-derived-operand
+  (name dst16-16-8-FB-relative-Mova-HI)
+  (comment
+    "m16c addressof dsp:8[fb] relative destination HI")
+  (attrs (ISA m16c))
+  (mode HI)
+  (args (Dsp-16-s8))
+  (syntax "${Dsp-16-s8}[fb]")
+  (base-ifield f-12-4)
+  (encoding (+ (f-12-4 11) Dsp-16-s8))
+  (ifield-assertion (eq f-12-4 11))
+  (getter (add Dsp-16-s8 (reg h-fb)))
+  (setter (nop))
+    )
+(define-derived-operand
+  (name dst16-16-16-absolute-Mova-HI)
+  (comment "m16c addressof absolute address HI")
+  (attrs (ISA m16c))
+  (mode HI)
+  (args (Dsp-16-u16))
+  (syntax "${Dsp-16-u16}")
+  (base-ifield f-12-4)
+  (encoding (+ (f-12-4 15) Dsp-16-u16))
+  (ifield-assertion (eq f-12-4 15))
+  (getter Dsp-16-u16)
+  (setter (nop))
+  )
+
+(define-anyof-operand
+  (name dst16-16-Mova-HI)
+  (comment "m16c addressof destination operand of size HI with additional fields at offset 16")
+  (attrs (machine 16))
+  (mode HI)
+  (choices
+   dst16-An-indirect-Mova-HI
+   dst16-16-8-An-relative-Mova-HI
+   dst16-16-16-An-relative-Mova-HI
+   dst16-16-8-SB-relative-Mova-HI
+   dst16-16-16-SB-relative-Mova-HI
+   dst16-16-8-FB-relative-Mova-HI
+   dst16-16-16-absolute-Mova-HI
+  )
+)
+
+(define-derived-operand
+  (name dst32-An-indirect-Unprefixed-Mova-SI)
+  (comment "m32c addressof An indirect destination SI")
+  (attrs (ISA m32c))
+  (mode SI)
+  (args (Dst32AnUnprefixed))
+  (syntax "[$Dst32AnUnprefixed]")
+  (base-ifield f-4-6)
+  (encoding
+    (+ (f-4-3 0) (f-8-1 0) Dst32AnUnprefixed))
+  (ifield-assertion
+    (andif (eq f-4-3 0) (eq f-8-1 0)))
+  (getter Dst32AnUnprefixed)
+  (setter (nop))
+  )
+
+(define-derived-operand
+  (name dst32-16-8-An-relative-Unprefixed-Mova-SI)
+  (comment "m32c addressof dsp:8[An] relative destination SI")
+  (attrs (ISA m32c))
+  (mode SI)
+  (args (Dst32AnUnprefixed Dsp-16-u8))
+  (syntax "${Dsp-16-u8}[$Dst32AnUnprefixed]")
+  (base-ifield f-4-6)
+  (encoding
+    (+ (f-4-3 1)
+       (f-8-1 0)
+       Dsp-16-u8
+       Dst32AnUnprefixed))
+  (ifield-assertion
+    (andif (eq f-4-3 1) (eq f-8-1 0)))
+  (getter (add Dsp-16-u8 Dst32AnUnprefixed))
+  (setter (nop))
+)
+
+(define-derived-operand
+  (name dst32-16-16-An-relative-Unprefixed-Mova-SI)
+  (comment
+    "m32c addressof dsp:16[An] relative destination SI")
+  (attrs (ISA m32c))
+  (mode SI)
+  (args (Dst32AnUnprefixed Dsp-16-u16))
+  (syntax "${Dsp-16-u16}[$Dst32AnUnprefixed]")
+  (base-ifield f-4-6)
+  (encoding
+    (+ (f-4-3 2)
+       (f-8-1 0)
+       Dsp-16-u16
+       Dst32AnUnprefixed))
+  (ifield-assertion
+    (andif (eq f-4-3 2) (eq f-8-1 0)))
+  (getter (add Dsp-16-u16 Dst32AnUnprefixed))
+  (setter (nop))
+  )
+
+(define-derived-operand
+  (name dst32-16-24-An-relative-Unprefixed-Mova-SI)
+  (comment "addressof m32c dsp:16[An] relative destination SI")
+  (attrs (ISA m32c))
+  (mode SI)
+  (args (Dst32AnUnprefixed Dsp-16-u24))
+  (syntax "${Dsp-16-u24}[$Dst32AnUnprefixed]")
+  (base-ifield f-4-6)
+  (encoding
+    (+ (f-4-3 3)
+       (f-8-1 0)
+       Dsp-16-u24
+       Dst32AnUnprefixed))
+  (ifield-assertion
+    (andif (eq f-4-3 3) (eq f-8-1 0)))
+  (getter (add Dsp-16-u24 Dst32AnUnprefixed))
+  (setter (nop))
+  )
+
+(define-derived-operand
+  (name dst32-16-8-SB-relative-Unprefixed-Mova-SI)
+  (comment "m32c addressof dsp:8[sb] relative destination SI")
+  (attrs (ISA m32c))
+  (mode SI)
+  (args (Dsp-16-u8))
+  (syntax "${Dsp-16-u8}[sb]")
+  (base-ifield f-4-6)
+  (encoding (+ (f-4-3 1) (f-8-2 2) Dsp-16-u8))
+  (ifield-assertion
+    (andif (eq f-4-3 1) (eq f-8-2 2)))
+  (getter (add Dsp-16-u8 (reg h-sb)))
+  (setter (nop))
+  )
+
+(define-derived-operand
+  (name dst32-16-16-SB-relative-Unprefixed-Mova-SI)
+  (comment "m32c addressof dsp:16[sb] relative destination SI")
+  (attrs (ISA m32c))
+  (mode SI)
+  (args (Dsp-16-u16))
+  (syntax "${Dsp-16-u16}[sb]")
+  (base-ifield f-4-6)
+  (encoding (+ (f-4-3 2) (f-8-2 2) Dsp-16-u16))
+  (ifield-assertion
+    (andif (eq f-4-3 2) (eq f-8-2 2)))
+  (getter (add Dsp-16-u16 (reg h-sb)))
+  (setter (nop))
+  )
+
+(define-derived-operand
+  (name dst32-16-8-FB-relative-Unprefixed-Mova-SI)
+  (comment "m32c addressof dsp:8[fb] relative destination SI")
+  (attrs (ISA m32c))
+  (mode SI)
+  (args (Dsp-16-s8))
+  (syntax "${Dsp-16-s8}[fb]")
+  (base-ifield f-4-6)
+  (encoding (+ (f-4-3 1) (f-8-2 3) Dsp-16-s8))
+  (ifield-assertion
+    (andif (eq f-4-3 1) (eq f-8-2 3)))
+  (getter (add Dsp-16-s8 (reg h-fb)))
+  (setter (nop))
+  )
+
+(define-derived-operand
+  (name dst32-16-16-FB-relative-Unprefixed-Mova-SI)
+  (comment "m32c addressof dsp:16[fb] relative destination SI")
+  (attrs (ISA m32c))
+  (mode SI)
+  (args (Dsp-16-s16))
+  (syntax "${Dsp-16-s16}[fb]")
+  (base-ifield f-4-6)
+  (encoding (+ (f-4-3 2) (f-8-2 3) Dsp-16-s16))
+  (ifield-assertion
+    (andif (eq f-4-3 2) (eq f-8-2 3)))
+  (getter (add Dsp-16-s16 (reg h-fb)))
+  (setter (nop))
+  )
+
+(define-derived-operand
+  (name dst32-16-16-absolute-Unprefixed-Mova-SI)
+  (comment "m32c addressof absolute address SI") (attrs (ISA m32c))
+  (mode SI)
+  (args (Dsp-16-u16))
+  (syntax "${Dsp-16-u16}")
+  (base-ifield f-4-6)
+  (encoding (+ (f-4-3 3) (f-8-2 3) Dsp-16-u16))
+  (ifield-assertion
+    (andif (eq f-4-3 3) (eq f-8-2 3)))
+  (getter Dsp-16-u16)
+  (setter (nop))
+  )
+
+(define-derived-operand
+  (name dst32-16-24-absolute-Unprefixed-Mova-SI)
+  (comment "m32c addressof absolute address SI") (attrs (ISA m32c))
+  (mode SI)
+  (args (Dsp-16-u24))
+  (syntax "${Dsp-16-u24}")
+  (base-ifield f-4-6)
+  (encoding (+ (f-4-3 3) (f-8-2 2) Dsp-16-u24))
+  (ifield-assertion
+    (andif (eq f-4-3 3) (eq f-8-2 2)))
+  (getter Dsp-16-u24)
+  (setter (nop))
+  )
+
+(define-anyof-operand
+  (name dst32-16-Unprefixed-Mova-SI)
+  (comment
+    "m32c addressof destination operand of size SI with additional fields at offset 16")
+  (attrs (ISA m32c))
+  (mode SI)
+  (choices
+    dst32-An-indirect-Unprefixed-Mova-SI
+    dst32-16-8-An-relative-Unprefixed-Mova-SI
+    dst32-16-16-An-relative-Unprefixed-Mova-SI
+    dst32-16-24-An-relative-Unprefixed-Mova-SI
+    dst32-16-8-SB-relative-Unprefixed-Mova-SI
+    dst32-16-16-SB-relative-Unprefixed-Mova-SI
+    dst32-16-8-FB-relative-Unprefixed-Mova-SI
+    dst32-16-16-FB-relative-Unprefixed-Mova-SI
+    dst32-16-16-absolute-Unprefixed-Mova-SI
+    dst32-16-24-absolute-Unprefixed-Mova-SI))
+
+(define-pmacro (dst32-16-operand xmode)
+  (begin
+    (define-anyof-operand
+      (name (.sym dst32-16-Unprefixed- xmode))
+      (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16"))
+      (attrs (machine 32))
+      (mode xmode)
+      (choices
+       (.sym dst32-Rn-direct-Unprefixed- xmode)
+       (.sym dst32-An-direct-Unprefixed- xmode)
+       (.sym dst32-An-indirect-Unprefixed- xmode)
+       (.sym dst32-16-8-An-relative-Unprefixed- xmode)
+       (.sym dst32-16-16-An-relative-Unprefixed- xmode)
+       (.sym dst32-16-24-An-relative-Unprefixed- xmode)
+       (.sym dst32-16-8-SB-relative-Unprefixed- xmode)
+       (.sym dst32-16-16-SB-relative-Unprefixed- xmode)
+       (.sym dst32-16-8-FB-relative-Unprefixed- xmode)
+       (.sym dst32-16-16-FB-relative-Unprefixed- xmode)
+       (.sym dst32-16-16-absolute-Unprefixed- xmode)
+       (.sym dst32-16-24-absolute-Unprefixed- xmode)
+      )
+    )
+    (define-anyof-operand
+      (name (.sym dst32-16-8-Unprefixed- xmode))
+      (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16"))
+      (attrs (machine 32))
+      (mode xmode)
+      (choices
+       (.sym dst32-16-8-An-relative-Unprefixed- xmode)
+       (.sym dst32-16-8-SB-relative-Unprefixed- xmode)
+       (.sym dst32-16-8-FB-relative-Unprefixed- xmode)
+      )
+    )
+    (define-anyof-operand
+      (name (.sym dst32-16-16-Unprefixed- xmode))
+      (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16"))
+      (attrs (machine 32))
+      (mode xmode)
+      (choices
+       (.sym dst32-16-16-An-relative-Unprefixed- xmode)
+       (.sym dst32-16-16-SB-relative-Unprefixed- xmode)
+       (.sym dst32-16-16-FB-relative-Unprefixed- xmode)
+       (.sym dst32-16-16-absolute-Unprefixed- xmode)
+      )
+    )
+    (define-anyof-operand
+      (name (.sym dst32-16-16sa-Unprefixed- xmode))
+      (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16"))
+      (attrs (machine 32))
+      (mode xmode)
+      (choices
+       (.sym dst32-16-16-SB-relative-Unprefixed- xmode)
+       (.sym dst32-16-16-FB-relative-Unprefixed- xmode)
+       (.sym dst32-16-16-absolute-Unprefixed- xmode)
+      )
+    )
+    (define-anyof-operand
+      (name (.sym dst32-16-24-Unprefixed- xmode))
+      (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16"))
+      (attrs (machine 32))
+      (mode xmode)
+      (choices
+       (.sym dst32-16-24-An-relative-Unprefixed- xmode)
+       (.sym dst32-16-24-absolute-Unprefixed- xmode)
+      )
+    )
+  )
+)
+
+(dst32-16-operand QI)
+(dst32-16-operand HI)
+(dst32-16-operand SI)
+
+(define-pmacro (dst32-16-Ext-operand smode dmode)
+  (begin
+    (define-anyof-operand
+      (name (.sym dst32-16-ExtUnprefixed- smode))
+      (comment (.str "m32c destination operand of size " smode " with additional fields at offset 16"))
+      (attrs (machine 32))
+      (mode dmode)
+      (choices
+       (.sym dst32-Rn-direct-ExtUnprefixed- smode)
+       (.sym dst32-An-direct-Unprefixed- dmode) ; ExtUnprefixed mode not required for this operand -- use the normal dmode version
+       (.sym dst32-An-indirect-ExtUnprefixed- smode)
+       (.sym dst32-16-8-An-relative-ExtUnprefixed- smode)
+       (.sym dst32-16-16-An-relative-ExtUnprefixed- smode)
+       (.sym dst32-16-24-An-relative-ExtUnprefixed- smode)
+       (.sym dst32-16-8-SB-relative-ExtUnprefixed- smode)
+       (.sym dst32-16-16-SB-relative-ExtUnprefixed- smode)
+       (.sym dst32-16-8-FB-relative-ExtUnprefixed- smode)
+       (.sym dst32-16-16-FB-relative-ExtUnprefixed- smode)
+       (.sym dst32-16-16-absolute-ExtUnprefixed- smode)
+       (.sym dst32-16-24-absolute-ExtUnprefixed- smode)
+      )
+    )
+  )
+)
+
+(dst32-16-Ext-operand QI HI)
+(dst32-16-Ext-operand HI SI)
+
+(define-anyof-operand
+  (name dst32-16-Unprefixed-Mulex-HI)
+  (comment "m32c destination operand of size HI with additional fields at offset 16")
+  (attrs (machine 32))
+  (mode HI)
+  (choices
+   dst32-R3-direct-Unprefixed-HI
+   dst32-An-direct-Unprefixed-HI
+   dst32-An-indirect-Unprefixed-HI
+   dst32-16-8-An-relative-Unprefixed-HI
+   dst32-16-16-An-relative-Unprefixed-HI
+   dst32-16-24-An-relative-Unprefixed-HI
+   dst32-16-8-SB-relative-Unprefixed-HI
+   dst32-16-16-SB-relative-Unprefixed-HI
+   dst32-16-8-FB-relative-Unprefixed-HI
+   dst32-16-16-FB-relative-Unprefixed-HI
+   dst32-16-16-absolute-Unprefixed-HI
+   dst32-16-24-absolute-Unprefixed-HI
+  )
+)
+;-------------------------------------------------------------
+; Destination operands with possible additional fields at offset 24 bits
+;-------------------------------------------------------------
+
+(define-pmacro (dst16-24-operand xmode)
+  (begin
+    (define-anyof-operand
+      (name (.sym dst16-24- xmode))
+      (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 24"))
+      (attrs (machine 16))
+      (mode xmode)
+      (choices
+       (.sym dst16-Rn-direct- xmode)
+       (.sym dst16-An-direct- xmode)
+       (.sym dst16-An-indirect- xmode)
+       (.sym dst16-24-8-An-relative- xmode)
+       (.sym dst16-24-16-An-relative- xmode)
+       (.sym dst16-24-8-SB-relative- xmode)
+       (.sym dst16-24-16-SB-relative- xmode)
+       (.sym dst16-24-8-FB-relative- xmode)
+       (.sym dst16-24-16-absolute- xmode)
+      )
+    )
+  )
+)
+
+(dst16-24-operand QI)
+(dst16-24-operand HI)
+
+(define-pmacro (dst32-24-operand xmode)
+  (begin
+    (define-anyof-operand
+      (name (.sym dst32-24-Unprefixed- xmode))
+      (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
+      (attrs (machine 32))
+      (mode xmode)
+      (choices
+       (.sym dst32-Rn-direct-Unprefixed- xmode)
+       (.sym dst32-An-direct-Unprefixed- xmode)
+       (.sym dst32-An-indirect-Unprefixed- xmode)
+       (.sym dst32-24-8-An-relative-Unprefixed- xmode)
+       (.sym dst32-24-16-An-relative-Unprefixed- xmode)
+       (.sym dst32-24-24-An-relative-Unprefixed- xmode)
+       (.sym dst32-24-8-SB-relative-Unprefixed- xmode)
+       (.sym dst32-24-16-SB-relative-Unprefixed- xmode)
+       (.sym dst32-24-8-FB-relative-Unprefixed- xmode)
+       (.sym dst32-24-16-FB-relative-Unprefixed- xmode)
+       (.sym dst32-24-16-absolute-Unprefixed- xmode)
+       (.sym dst32-24-24-absolute-Unprefixed- xmode)
+      )
+    )
+    (define-anyof-operand
+      (name (.sym dst32-24-Prefixed- xmode))
+      (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
+      (attrs (machine 32))
+      (mode xmode)
+      (choices
+       (.sym dst32-Rn-direct-Prefixed- xmode)
+       (.sym dst32-An-direct-Prefixed- xmode)
+       (.sym dst32-An-indirect-Prefixed- xmode)
+       (.sym dst32-24-8-An-relative-Prefixed- xmode)
+       (.sym dst32-24-16-An-relative-Prefixed- xmode)
+       (.sym dst32-24-24-An-relative-Prefixed- xmode)
+       (.sym dst32-24-8-SB-relative-Prefixed- xmode)
+       (.sym dst32-24-16-SB-relative-Prefixed- xmode)
+       (.sym dst32-24-8-FB-relative-Prefixed- xmode)
+       (.sym dst32-24-16-FB-relative-Prefixed- xmode)
+       (.sym dst32-24-16-absolute-Prefixed- xmode)
+       (.sym dst32-24-24-absolute-Prefixed- xmode)
+      )
+    )
+    (define-anyof-operand
+      (name (.sym dst32-24-8-Prefixed- xmode))
+      (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
+      (attrs (machine 32))
+      (mode xmode)
+      (choices
+       (.sym dst32-24-8-An-relative-Prefixed- xmode)
+       (.sym dst32-24-8-SB-relative-Prefixed- xmode)
+       (.sym dst32-24-8-FB-relative-Prefixed- xmode)
+      )
+    )
+    (define-anyof-operand
+      (name (.sym dst32-24-16-Prefixed- xmode))
+      (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
+      (attrs (machine 32))
+      (mode xmode)
+      (choices
+       (.sym dst32-24-16-An-relative-Prefixed- xmode)
+       (.sym dst32-24-16-SB-relative-Prefixed- xmode)
+       (.sym dst32-24-16-FB-relative-Prefixed- xmode)
+       (.sym dst32-24-16-absolute-Prefixed- xmode)
+      )
+    )
+    (define-anyof-operand
+      (name (.sym dst32-24-24-Prefixed- xmode))
+      (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
+      (attrs (machine 32))
+      (mode xmode)
+      (choices
+       (.sym dst32-24-24-An-relative-Prefixed- xmode)
+       (.sym dst32-24-24-absolute-Prefixed- xmode)
+      )
+    )
+;     (define-anyof-operand
+;       (name (.sym dst32-24-indirect- xmode))
+;       (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (choices
+;        (.sym dst32-An-indirect-indirect- xmode)
+;        (.sym dst32-24-8-An-relative-indirect- xmode)
+;        (.sym dst32-24-16-An-relative-indirect- xmode)
+;        (.sym dst32-24-24-An-relative-indirect- xmode)
+;        (.sym dst32-24-8-SB-relative-indirect- xmode)
+;        (.sym dst32-24-16-SB-relative-indirect- xmode)
+;        (.sym dst32-24-8-FB-relative-indirect- xmode)
+;        (.sym dst32-24-16-FB-relative-indirect- xmode)
+;       )
+;     )
+;     (define-anyof-operand
+;       (name (.sym dst32-basic-indirect- xmode))
+;       (comment (.str "m32c destination operand of size " xmode " with no additional fields"))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (choices
+;        (.sym dst32-An-indirect-indirect- xmode)
+;       )
+;     )
+;     (define-anyof-operand
+;       (name (.sym dst32-24-8-indirect- xmode))
+;       (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (choices
+;        (.sym dst32-24-8-An-relative-indirect- xmode)
+;        (.sym dst32-24-8-SB-relative-indirect- xmode)
+;        (.sym dst32-24-8-FB-relative-indirect- xmode)
+;       )
+;     )
+;     (define-anyof-operand
+;       (name (.sym dst32-24-16-indirect- xmode))
+;       (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (choices
+;        (.sym dst32-24-16-An-relative-indirect- xmode)
+;        (.sym dst32-24-16-SB-relative-indirect- xmode)
+;        (.sym dst32-24-16-FB-relative-indirect- xmode)
+;       )
+;     )
+;     (define-anyof-operand
+;       (name (.sym dst32-24-24-indirect- xmode))
+;       (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (choices
+;        (.sym dst32-24-24-An-relative-indirect- xmode)
+;       )
+;     )
+;     (define-anyof-operand
+;       (name (.sym dst32-24-absolute-indirect- xmode))
+;       (comment (.str "m32c destination operand of size " xmode " absolute indirect"))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (choices
+;        (.sym dst32-24-16-absolute-indirect-derived- xmode)
+;        (.sym dst32-24-24-absolute-indirect-derived- xmode)
+;       )
+;     )
+;     (define-anyof-operand
+;       (name (.sym dst32-24-16-absolute-indirect- xmode))
+;       (comment (.str "m32c destination operand of size " xmode " absolute indirect"))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (choices
+;        (.sym dst32-24-16-absolute-indirect-derived- xmode)
+;       )
+;     )
+;     (define-anyof-operand
+;       (name (.sym dst32-24-24-absolute-indirect- xmode))
+;       (comment (.str "m32c destination operand of size " xmode " absolute indirect"))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (choices
+;        (.sym dst32-24-24-absolute-indirect-derived- xmode)
+;       )
+;     )
+  )
+)
+
+(dst32-24-operand QI)
+(dst32-24-operand HI)
+(dst32-24-operand SI)
+
+;-------------------------------------------------------------
+; Destination operands with possible additional fields at offset 32 bits
+;-------------------------------------------------------------
+
+(define-pmacro (dst16-32-operand xmode)
+  (begin
+    (define-anyof-operand
+      (name (.sym dst16-32- xmode))
+      (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 32"))
+      (attrs (machine 16))
+      (mode xmode)
+      (choices
+       (.sym dst16-Rn-direct- xmode)
+       (.sym dst16-An-direct- xmode)
+       (.sym dst16-An-indirect- xmode)
+       (.sym dst16-32-8-An-relative- xmode)
+       (.sym dst16-32-16-An-relative- xmode)
+       (.sym dst16-32-8-SB-relative- xmode)
+       (.sym dst16-32-16-SB-relative- xmode)
+       (.sym dst16-32-8-FB-relative- xmode)
+       (.sym dst16-32-16-absolute- xmode)
+      )
+    )
+  )
+)
+(dst16-32-operand QI)
+(dst16-32-operand HI)
+
+; This macro actually handles operands at offset 32, 40 and 48 bits
+(define-pmacro (dst32-32plus-operand offset xmode)
+  (begin
+    (define-anyof-operand
+      (name (.sym dst32- offset -Unprefixed- xmode))
+      (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32"))
+      (attrs (machine 32))
+      (mode xmode)
+      (choices
+       (.sym dst32-Rn-direct-Unprefixed- xmode)
+       (.sym dst32-An-direct-Unprefixed- xmode)
+       (.sym dst32-An-indirect-Unprefixed- xmode)
+       (.sym dst32- offset -8-An-relative-Unprefixed- xmode)
+       (.sym dst32- offset -16-An-relative-Unprefixed- xmode)
+       (.sym dst32- offset -24-An-relative-Unprefixed- xmode)
+       (.sym dst32- offset -8-SB-relative-Unprefixed- xmode)
+       (.sym dst32- offset -16-SB-relative-Unprefixed- xmode)
+       (.sym dst32- offset -8-FB-relative-Unprefixed- xmode)
+       (.sym dst32- offset -16-FB-relative-Unprefixed- xmode)
+       (.sym dst32- offset -16-absolute-Unprefixed- xmode)
+       (.sym dst32- offset -24-absolute-Unprefixed- xmode)
+      )
+    )
+    (define-anyof-operand
+      (name (.sym dst32- offset -Prefixed- xmode))
+      (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32"))
+      (attrs (machine 32))
+      (mode xmode)
+      (choices
+       (.sym dst32-Rn-direct-Prefixed- xmode)
+       (.sym dst32-An-direct-Prefixed- xmode)
+       (.sym dst32-An-indirect-Prefixed- xmode)
+       (.sym dst32- offset -8-An-relative-Prefixed- xmode)
+       (.sym dst32- offset -16-An-relative-Prefixed- xmode)
+       (.sym dst32- offset -24-An-relative-Prefixed- xmode)
+       (.sym dst32- offset -8-SB-relative-Prefixed- xmode)
+       (.sym dst32- offset -16-SB-relative-Prefixed- xmode)
+       (.sym dst32- offset -8-FB-relative-Prefixed- xmode)
+       (.sym dst32- offset -16-FB-relative-Prefixed- xmode)
+       (.sym dst32- offset -16-absolute-Prefixed- xmode)
+       (.sym dst32- offset -24-absolute-Prefixed- xmode)
+      )
+    )
+;     (define-anyof-operand
+;       (name (.sym dst32- offset -indirect- xmode))
+;       (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32"))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (choices
+;        (.sym dst32-An-indirect-indirect- xmode)
+;        (.sym dst32- offset -8-An-relative-indirect- xmode)
+;        (.sym dst32- offset -16-An-relative-indirect- xmode)
+;        (.sym dst32- offset -24-An-relative-indirect- xmode)
+;        (.sym dst32- offset -8-SB-relative-indirect- xmode)
+;        (.sym dst32- offset -16-SB-relative-indirect- xmode)
+;        (.sym dst32- offset -8-FB-relative-indirect- xmode)
+;        (.sym dst32- offset -16-FB-relative-indirect- xmode)
+;       )
+;     )
+;     (define-anyof-operand
+;       (name (.sym dst32- offset -absolute-indirect- xmode))
+;       (comment (.str "m32c destination operand of size " xmode " absolute indirect"))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (choices
+;        (.sym dst32- offset -16-absolute-indirect-derived- xmode)
+;        (.sym dst32- offset -24-absolute-indirect-derived- xmode)
+;       )
+;     )
+  )
+)
+
+(dst32-32plus-operand 32 QI)
+(dst32-32plus-operand 32 HI)
+(dst32-32plus-operand 32 SI)
+(dst32-32plus-operand 40 QI)
+(dst32-32plus-operand 40 HI)
+(dst32-32plus-operand 40 SI)
+
+;-------------------------------------------------------------
+; Destination operands with possible additional fields at offset 48 bits
+;-------------------------------------------------------------
+
+(define-pmacro (dst32-48-operand offset xmode)
+  (begin
+    (define-anyof-operand
+      (name (.sym dst32- offset -Prefixed- xmode))
+      (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32"))
+      (attrs (machine 32))
+      (mode xmode)
+      (choices
+       (.sym dst32-Rn-direct-Prefixed- xmode)
+       (.sym dst32-An-direct-Prefixed- xmode)
+       (.sym dst32-An-indirect-Prefixed- xmode)
+       (.sym dst32- offset -8-An-relative-Prefixed- xmode)
+       (.sym dst32- offset -16-An-relative-Prefixed- xmode)
+       (.sym dst32- offset -24-An-relative-Prefixed- xmode)
+       (.sym dst32- offset -8-SB-relative-Prefixed- xmode)
+       (.sym dst32- offset -16-SB-relative-Prefixed- xmode)
+       (.sym dst32- offset -8-FB-relative-Prefixed- xmode)
+       (.sym dst32- offset -16-FB-relative-Prefixed- xmode)
+       (.sym dst32- offset -16-absolute-Prefixed- xmode)
+       (.sym dst32- offset -24-absolute-Prefixed- xmode)
+      )
+    )
+;     (define-anyof-operand
+;       (name (.sym dst32- offset -indirect- xmode))
+;       (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32"))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (choices
+;        (.sym dst32-An-indirect-indirect- xmode)
+;        (.sym dst32- offset -8-An-relative-indirect- xmode)
+;        (.sym dst32- offset -16-An-relative-indirect- xmode)
+;        (.sym dst32- offset -24-An-relative-indirect- xmode)
+;        (.sym dst32- offset -8-SB-relative-indirect- xmode)
+;        (.sym dst32- offset -16-SB-relative-indirect- xmode)
+;        (.sym dst32- offset -8-FB-relative-indirect- xmode)
+;        (.sym dst32- offset -16-FB-relative-indirect- xmode)
+;       )
+;     )
+;     (define-anyof-operand
+;       (name (.sym dst32- offset -absolute-indirect- xmode))
+;       (comment (.str "m32c destination operand of size " xmode " absolute indirect"))
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (choices
+;        (.sym dst32- offset -16-absolute-indirect-derived- xmode)
+;        (.sym dst32- offset -24-absolute-indirect-derived- xmode)
+;       )
+;     )
+  )
+)
+
+(dst32-48-operand 48 QI)
+(dst32-48-operand 48 HI)
+(dst32-48-operand 48 SI)
+
+;-------------------------------------------------------------
+; Bit operands for m16c
+;-------------------------------------------------------------
+
+(define-pmacro (bit16-operand offset)
+  (begin
+    (define-anyof-operand
+      (name (.sym bit16- offset))
+      (comment (.str "m16c bit operand with possible additional fields at offset 24"))
+      (attrs (machine 16))
+      (mode BI)
+      (choices
+       bit16-Rn-direct
+       bit16-An-direct
+       bit16-An-indirect
+       (.sym bit16- offset -8-An-relative)
+       (.sym bit16- offset -16-An-relative)
+       (.sym bit16- offset -8-SB-relative)
+       (.sym bit16- offset -16-SB-relative)
+       (.sym bit16- offset -8-FB-relative)
+       (.sym bit16- offset -16-absolute)
+      )
+    )
+    (define-anyof-operand
+      (name (.sym bit16- offset -basic))
+      (comment (.str "m16c bit operand with no additional fields"))
+      (attrs (machine 16))
+      (mode BI)
+      (choices
+       bit16-An-indirect
+      )
+    )
+    (define-anyof-operand
+      (name (.sym bit16- offset -8))
+      (comment (.str "m16c bit operand with possible additional fields at offset 24"))
+      (attrs (machine 16))
+      (mode BI)
+      (choices
+       bit16-Rn-direct
+       bit16-An-direct
+       (.sym bit16- offset -8-An-relative)
+       (.sym bit16- offset -8-SB-relative)
+       (.sym bit16- offset -8-FB-relative)
+      )
+    )
+    (define-anyof-operand
+      (name (.sym bit16- offset -16))
+      (comment (.str "m16c bit operand with possible additional fields at offset 24"))
+      (attrs (machine 16))
+      (mode BI)
+      (choices
+       (.sym bit16- offset -16-An-relative)
+       (.sym bit16- offset -16-SB-relative)
+       (.sym bit16- offset -16-absolute)
+      )
+    )
+  )
+)
+
+(bit16-operand 16)
+
+;-------------------------------------------------------------
+; Bit operands for m32c
+;-------------------------------------------------------------
+
+(define-pmacro (bit32-operand offset group)
+  (begin
+    (define-anyof-operand
+      (name (.sym bit32- offset - group))
+      (comment (.str "m32c bit operand with possible additional fields at offset 24"))
+      (attrs (machine 32))
+      (mode BI)
+      (choices
+       (.sym bit32-Rn-direct- group)
+       (.sym bit32-An-direct- group)
+       (.sym bit32-An-indirect- group)
+       (.sym bit32- offset -11-An-relative- group)
+       (.sym bit32- offset -19-An-relative- group)
+       (.sym bit32- offset -27-An-relative- group)
+       (.sym bit32- offset -11-SB-relative- group)
+       (.sym bit32- offset -19-SB-relative- group)
+       (.sym bit32- offset -11-FB-relative- group)
+       (.sym bit32- offset -19-FB-relative- group)
+       (.sym bit32- offset -19-absolute- group)
+       (.sym bit32- offset -27-absolute- group)
+      )
+    )
+  )
+)
+
+(bit32-operand 16 Unprefixed)
+(bit32-operand 24 Prefixed)
+
+(define-anyof-operand
+  (name bit32-basic-Unprefixed)
+  (comment "m32c bit operand with no additional fields")
+  (attrs (machine 32))
+  (mode BI)
+  (choices
+   bit32-Rn-direct-Unprefixed
+   bit32-An-direct-Unprefixed
+   bit32-An-indirect-Unprefixed
+  )
+)
+
+(define-anyof-operand
+  (name bit32-16-8-Unprefixed)
+  (comment "m32c bit operand with 8 bit additional fields")
+  (attrs (machine 32))
+  (mode BI)
+  (choices
+   bit32-16-11-An-relative-Unprefixed
+   bit32-16-11-SB-relative-Unprefixed
+   bit32-16-11-FB-relative-Unprefixed
+  )
+)
+
+(define-anyof-operand
+  (name bit32-16-16-Unprefixed)
+  (comment "m32c bit operand with 16 bit additional fields")
+  (attrs (machine 32))
+  (mode BI)
+  (choices
+   bit32-16-19-An-relative-Unprefixed
+   bit32-16-19-SB-relative-Unprefixed
+   bit32-16-19-FB-relative-Unprefixed
+   bit32-16-19-absolute-Unprefixed
+  )
+)
+
+(define-anyof-operand
+  (name bit32-16-24-Unprefixed)
+  (comment "m32c bit operand with 24 bit additional fields")
+  (attrs (machine 32))
+  (mode BI)
+  (choices
+   bit32-16-27-An-relative-Unprefixed
+   bit32-16-27-absolute-Unprefixed
+  )
+)
+
+;-------------------------------------------------------------
+; Operands for short format binary insns
+;-------------------------------------------------------------
+
+(define-anyof-operand
+  (name src16-2-S)
+  (comment "m16c source operand of size QI for short format insns")
+  (attrs (machine 16))
+  (mode QI)
+  (choices
+   src16-2-S-8-SB-relative-QI
+   src16-2-S-8-FB-relative-QI
+   src16-2-S-16-absolute-QI
+  )
+)
+
+(define-anyof-operand
+  (name src32-2-S-QI)
+  (comment "m32c source operand of size QI for short format insns")
+  (attrs (machine 32))
+  (mode QI)
+  (choices
+   src32-2-S-8-SB-relative-QI
+   src32-2-S-8-FB-relative-QI
+   src32-2-S-16-absolute-QI
+  )
+)
+
+(define-anyof-operand
+  (name src32-2-S-HI)
+  (comment "m32c source operand of size QI for short format insns")
+  (attrs (machine 32))
+  (mode HI)
+  (choices
+   src32-2-S-8-SB-relative-HI
+   src32-2-S-8-FB-relative-HI
+   src32-2-S-16-absolute-HI
+  )
+)
+
+(define-anyof-operand
+  (name Dst16-3-S-8)
+  (comment "m16c destination operand of size QI for short format insns")
+  (attrs (machine 16))
+  (mode QI)
+  (choices
+   dst16-3-S-R0l-direct-QI
+   dst16-3-S-R0h-direct-QI
+   dst16-3-S-8-8-SB-relative-QI
+   dst16-3-S-8-8-FB-relative-QI
+   dst16-3-S-8-16-absolute-QI
+  )
+)
+
+(define-anyof-operand
+  (name Dst16-3-S-16)
+  (comment "m16c destination operand of size QI for short format insns")
+  (attrs (machine 16))
+  (mode QI)
+  (choices
+   dst16-3-S-R0l-direct-QI
+   dst16-3-S-R0h-direct-QI
+   dst16-3-S-16-8-SB-relative-QI
+   dst16-3-S-16-8-FB-relative-QI
+   dst16-3-S-16-16-absolute-QI
+  )
+)
+
+(define-anyof-operand
+  (name srcdst16-r0l-r0h-S)
+  (comment "m16c r0l/r0h operand of size QI for short format insns")
+  (attrs (machine 16))
+  (mode SI)
+  (choices
+   srcdst16-r0l-r0h-S-derived
+  )
+)
+
+(define-anyof-operand
+  (name dst32-2-S-basic-QI)
+  (comment "m32c r0l operand of size QI for short format binary insns")
+  (attrs (machine 32))
+  (mode QI)
+  (choices
+   dst32-2-S-R0l-direct-QI
+  )
+)
+
+(define-anyof-operand
+  (name dst32-2-S-basic-HI)
+  (comment "m32c r0 operand of size HI for short format binary insns")
+  (attrs (machine 32))
+  (mode HI)
+  (choices
+   dst32-2-S-R0-direct-HI
+  )
+)
+
+(define-pmacro (dst32-2-S-operands xmode)
+  (begin
+    (define-anyof-operand
+      (name (.sym dst32-2-S-8- xmode))
+      (comment "m32c operand of size " xmode " for short format binary insns")
+      (attrs (machine 32))
+      (mode xmode)
+      (choices
+       (.sym dst32-2-S-8-SB-relative- xmode)
+       (.sym dst32-2-S-8-FB-relative- xmode)
+      )
+    )
+    (define-anyof-operand
+      (name (.sym dst32-2-S-16- xmode))
+      (comment "m32c operand of size " xmode " for short format binary insns")
+      (attrs (machine 32))
+      (mode xmode)
+      (choices
+       (.sym dst32-2-S-16-absolute- xmode)
+      )
+    )
+;     (define-anyof-operand
+;       (name (.sym dst32-2-S-8-indirect- xmode))
+;       (comment "m32c operand of size " xmode " for short format binary insns")
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (choices
+;        (.sym dst32-2-S-8-SB-relative-indirect- xmode)
+;        (.sym dst32-2-S-8-FB-relative-indirect- xmode)
+;       )
+;     )
+;     (define-anyof-operand
+;       (name (.sym dst32-2-S-absolute-indirect- xmode))
+;       (comment "m32c operand of size " xmode " for short format binary insns")
+;       (attrs (machine 32))
+;       (mode xmode)
+;       (choices
+;        (.sym dst32-2-S-16-absolute-indirect- xmode)
+;       )
+;     )
+  )
+)
+    
+(dst32-2-S-operands QI)
+(dst32-2-S-operands HI)
+(dst32-2-S-operands SI)
+
+(define-anyof-operand
+  (name dst32-an-S)
+  (comment "m32c An operand for short format binary insns")
+  (attrs (machine 32))
+  (mode HI)
+  (choices
+   dst32-1-S-A0-direct-HI
+   dst32-1-S-A1-direct-HI
+  )
+)
+
+(define-anyof-operand
+  (name bit16-11-S)
+  (comment "m16c bit operand for short format insns")
+  (attrs (machine 16))
+  (mode BI)
+  (choices
+   bit16-11-SB-relative-S
+  )
+)
+
+(define-anyof-operand
+  (name Rn16-push-S-anyof)
+  (comment "m16c bit operand for short format insns")
+  (attrs (machine 16))
+  (mode QI)
+  (choices
+   Rn16-push-S-derived
+  )
+)
+
+(define-anyof-operand
+  (name An16-push-S-anyof)
+  (comment "m16c bit operand for short format insns")
+  (attrs (machine 16))
+  (mode HI)
+  (choices
+   An16-push-S-derived
+  )
+)
+
+;=============================================================
+; Common macros for instruction definitions
+;
+(define-pmacro (set-z x)
+  (sequence ()
+            (set zbit (zflag x)))
+       
+)
+
+(define-pmacro (set-s x)
+  (sequence ()
+            (set sbit (nflag x)))
+)
+
+(define-pmacro (set-z-and-s x)
+  (sequence ()
+            (set-z x)
+            (set-s x))
+)
+\f
+;=============================================================
+; Unary insn macros
+;-------------------------------------------------------------
+
+(define-pmacro (unary-insn-defn-g mach group mode wstr op encoding sem opg)
+  (dni (.sym op mach wstr - group)
+       (.str op wstr opg " dst" mach "-" group "-" mode)
+       ((machine mach) RL_1ADDR)
+       (.str op wstr opg " ${dst" mach "-" group "-" mode "}")
+       encoding
+       (sem mode (.sym dst mach - group - mode))
+       ())
+)
+
+(define-pmacro (unary-insn-defn mach group mode wstr op encoding sem)
+  (unary-insn-defn-g mach group mode wstr op encoding sem "")
+)
+
+
+(define-pmacro (unary16-defn-g mode wstr wbit op opc1 opc2 opc3 sem opg)
+  (unary-insn-defn-g 16 16 mode wstr op
+                    (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16- mode))
+                    sem opg)
+)
+(define-pmacro (unary16-defn mode wstr wbit op opc1 opc2 opc3 sem)
+  (unary-16-defn-g mode wstr wbit op opc1 opc2 opc3 sem "")
+)
+
+(define-pmacro (unary32-defn-g mode wstr wbit op opc1 opc2 opc3 sem opg)
+  (begin
+    ; Multi insns are tried for assembly in the reverse order in which they appear here, so
+    ; define the absolute-indirect insns first in order to prevent them from being selected
+    ; when the mode is register-indirect
+;     (unary-insn-defn 32 24-absolute-indirect mode wstr op
+;                   (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (.sym dst32-24-absolute-indirect- mode) (f-18-2 opc2) (f-20-4 opc3))
+;                   sem)
+    (unary-insn-defn-g 32 16-Unprefixed mode wstr op
+                      (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3))
+                      sem opg)
+;     (unary-insn-defn 32 24-indirect mode wstr op
+;                   (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (.sym dst32-24-indirect- mode) (f-18-2 opc2) (f-20-4 opc3))
+;                   sem)
+  )
+)
+(define-pmacro (unary32-defn mode wstr wbit op opc1 opc2 opc3 sem)
+  (unary32-defn-g mode wstr wbit op opc1 opc2 opc3 sem "")
+)
+
+(define-pmacro (unary-insn-mach-g mach op opc1 opc2 opc3 sem opg)
+  (begin
+    (.apply (.sym unary mach -defn-g) (QI .b 0 op opc1 opc2 opc3 sem opg))
+    (.apply (.sym unary mach -defn-g) (HI .w 1 op opc1 opc2 opc3 sem opg))
+  )
+)
+(define-pmacro (unary-insn-mach mach op opc1 opc2 opc3 sem)
+  (unary-insn-mach-g mach op opc1 opc2 opc3 sem "")
+)
+
+(define-pmacro (unary-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
+  (begin
+    (unary-insn-mach-g 16 op opc16-1 opc16-2 opc16-3 sem "")
+    (unary-insn-mach-g 32 op opc32-1 opc32-2 opc32-3 sem "")
+  )
+)
+
+(define-pmacro (unary-insn-g op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
+  (begin
+    (unary-insn-mach-g 16 op opc16-1 opc16-2 opc16-3 sem "$G")
+    (unary-insn-mach-g 32 op opc32-1 opc32-2 opc32-3 sem "$G")
+  )
+)
+
+;-------------------------------------------------------------
+; Sign/zero extension macros
+;-------------------------------------------------------------
+
+(define-pmacro (ext-insn-defn mach group smode dmode wstr op encoding sem)
+  (dni (.sym op mach wstr - group)
+       (.str op wstr " dst" mach "-" group "-" smode)
+       ((machine mach))
+       (.str op wstr " ${dst" mach "-" group "-" smode "}")
+       encoding
+       (sem smode dmode (.sym dst mach - group - smode) (.sym dst mach - group - smode))
+       ())
+)
+
+(define-pmacro (ext16-defn smode dmode wstr wbit op opc1 opc2 opc3 sem)
+  (ext-insn-defn 16 16-Ext smode dmode wstr op
+                  (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-Ext- smode))
+                  sem)
+)
+
+(define-pmacro (ext32-defn smode dmode wstr wbit op opc1 opc2 opc3 sem)
+  (ext-insn-defn 32 16-ExtUnprefixed smode dmode wstr op
+                (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst32-16-ExtUnprefixed- smode))
+                sem)
+)
+
+(define-pmacro (ext32-binary-insn src-group dst-group op wstr encoding sem)
+  (dni (.sym op 32 wstr - src-group - dst-group)
+       (.str op 32 wstr  " src32-" src-group "-QI,dst32-" dst-group "-HI")
+       ((machine 32))
+       (.str op wstr " ${src32-" src-group "-QI},${dst32-" dst-group "-HI}")
+       encoding
+       (sem QI HI (.sym src32- src-group -QI) (.sym dst32 - dst-group -HI))
+       ())
+)
+
+(define-pmacro (ext32-binary-defn op wstr opc1 opc2 sem)
+  (begin
+    (ext32-binary-insn basic-ExtPrefixed 24-Prefixed op wstr
+                      (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-basic-ExtPrefixed-QI dst32-24-Prefixed-HI (f-20-4 opc2))
+                      sem)
+    (ext32-binary-insn 24-24-Prefixed 48-Prefixed op wstr
+                      (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-24-24-Prefixed-QI dst32-48-Prefixed-HI (f-20-4 opc2))
+                      sem)
+    (ext32-binary-insn 24-16-Prefixed 40-Prefixed op wstr
+                      (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-24-16-Prefixed-QI dst32-40-Prefixed-HI (f-20-4 opc2))
+                      sem)
+    (ext32-binary-insn 24-8-Prefixed 32-Prefixed op wstr
+                      (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-24-8-Prefixed-QI dst32-32-Prefixed-HI (f-20-4 opc2))
+                      sem)
+  )
+)
+
+;=============================================================
+; Binary Arithmetic macros
+;
+;-------------------------------------------------------------
+;<arith>.size:S src2,r0[l] -- for m32c
+;-------------------------------------------------------------
+
+(define-pmacro (binary-arith32-S-src2 op xmode wstr wbit opc1 opc2 sem)
+  (dni (.sym op 32 wstr .S-src2-r0- xmode)
+       (.str op 32 wstr ":S src2,r0[l]")
+       ((machine 32))
+       (.str op wstr"$S ${src32-2-S-" xmode "},${Dst32R0" xmode "-S}")
+       (+ opc1 opc2 (.sym src32-2-S- xmode) (f-7-1 wbit))
+       (sem xmode (.sym src32-2-S- xmode) (.sym Dst32R0 xmode -S))
+       ())
+)
+
+;-------------------------------------------------------------
+;<arith>.b:S src2,r0l/r0h -- for m16c
+;-------------------------------------------------------------
+
+(define-pmacro (binary-arith16-b-S-src2 op opc1 opc2 sem)
+  (begin
+    (dni (.sym op 16 .b.S-src2)
+        (.str op ".b:S src2,r0[lh]")
+        ((machine 16))
+        (.str op ".b$S ${src16-2-S},${Dst16RnQI-S}")
+        (+ opc1 opc2 Dst16RnQI-S src16-2-S)
+        (sem QI src16-2-S Dst16RnQI-S)
+        ())
+    (dni (.sym op 16 .b.S-r0l-r0h)
+        (.str op ".b:S r0l/r0h")
+        ((machine 16))
+        (.str op ".b$S ${srcdst16-r0l-r0h-S}")
+        (+ opc1 opc2 srcdst16-r0l-r0h-S)
+        (if (eq srcdst16-r0l-r0h-S 0)
+            (sem QI R0h R0l)
+            (sem QI R0l R0h))
+        ())
+  )
+)
+
+;-------------------------------------------------------------
+;<arith>.b:S #imm8,dst3 -- for m16c
+;-------------------------------------------------------------
+
+(define-pmacro (binary-arith16-b-S-imm8-dst3 op sz opc1 opc2 sem)
+  (dni (.sym op 16 .b.S-imm8-dst3)
+       (.str op sz ":S imm8,dst3")
+       ((machine 16))
+       (.str op sz "$S #${Imm-8-QI},${Dst16-3-S-16}")
+       (+ opc1 opc2 Dst16-3-S-16 Imm-8-QI)
+       (sem QI Imm-8-QI Dst16-3-S-16)
+       ())
+)
+
+;-------------------------------------------------------------
+;<arith>.size:Q #imm4,sp -- for m16c
+;-------------------------------------------------------------
+
+(define-pmacro (binary-arith16-Q-sp op opc1 opc2 opc3 sem)
+  (dni (.sym op 16 -wQ-sp)
+       (.str op ".w:q #imm4,sp")
+       ((machine 16))
+       (.str op ".w$Q #${Imm-12-s4},sp")
+       (+ opc1 opc2 opc3 Imm-12-s4)
+       (sem QI Imm-12-s4 sp)
+       ())
+)
+
+;-------------------------------------------------------------
+;<arith>.size:G #imm,sp -- for m16c
+;-------------------------------------------------------------
+
+(define-pmacro (binary-arith16-G-sp-defn mode wstr wbit op opc1 opc2 opc3 opc4 sem)
+  (dni (.sym op 16 wstr - G-sp)
+       (.str op wstr " imm-sp " mode)
+       ((machine 16))
+       (.str op wstr "$G #${Imm-16-" mode "},sp")
+       (+ opc1 opc2 (f-7-1 wbit) opc3 opc4 (.sym Imm-16- mode))
+       (sem mode (.sym Imm-16- mode) sp)
+       ())
+)
+
+(define-pmacro (binary-arith16-G-sp op opc1 opc2 opc3 opc4 sem)
+  (begin
+    (binary-arith16-G-sp-defn QI .b 0 op opc1 opc2 opc3 opc4 sem)
+    (binary-arith16-G-sp-defn HI .w 1 op opc1 opc2 opc3 opc4 sem)
+  )
+)
+
+;-------------------------------------------------------------
+;<arith>.size:G #imm,dst -- for m16c and m32c
+;-------------------------------------------------------------
+
+(define-pmacro (binary-arith-imm-dst-defn mach src dstgroup dmode wstr op suffix encoding sem)
+  (dni (.sym op mach wstr - imm-G - dstgroup)
+       (.str op wstr " " mach "-imm-G-" dstgroup "-" dmode)
+       ((machine mach) RL_1ADDR)
+       (.str op wstr "$"suffix " #${" src "},${dst" mach "-" dstgroup "-" dmode "}")
+       encoding
+       (sem dmode src (.sym dst mach - dstgroup - dmode))
+       ())
+)
+
+; m16c variants
+(define-pmacro (binary-arith16-imm-dst-defn smode dmode wstr wbit op suffix opc1 opc2 opc3 sem)
+  (begin
+    (binary-arith-imm-dst-defn 16 (.sym Imm-32- smode) 16-16 dmode wstr op suffix
+                              (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- dmode) (.sym Imm-32- smode))
+                              sem)
+    (binary-arith-imm-dst-defn 16 (.sym Imm-24- smode) 16-8 dmode wstr op suffix
+                              (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- dmode) (.sym Imm-24- smode))
+                              sem)
+    (binary-arith-imm-dst-defn 16 (.sym Imm-16- smode) basic dmode wstr op suffix
+                              (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- dmode) (.sym Imm-16- smode))
+                              sem)
+  )
+)
+
+; m32c Unprefixed variants
+(define-pmacro (binary-arith32-imm-dst-Unprefixed smode dmode wstr wbit op suffix opc1 opc2 opc3 sem)
+  (begin
+    (binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 16-24-Unprefixed dmode wstr op suffix
+                              (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-16-24-Unprefixed- dmode) (.sym Imm-40- smode))
+                              sem)
+    (binary-arith-imm-dst-defn 32 (.sym Imm-32- smode) 16-16-Unprefixed dmode wstr op suffix
+                              (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-16-16-Unprefixed- dmode) (.sym Imm-32- smode))
+                              sem)
+    (binary-arith-imm-dst-defn 32 (.sym Imm-24- smode) 16-8-Unprefixed dmode wstr op suffix
+                              (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-16-8-Unprefixed- dmode) (.sym Imm-24- smode))
+                              sem)
+    (binary-arith-imm-dst-defn 32 (.sym Imm-16- smode) basic-Unprefixed dmode wstr op suffix
+                              (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-basic-Unprefixed- dmode) (.sym Imm-16- smode))
+                              sem)
+  )
+)
+
+; m32c Prefixed variants
+(define-pmacro (binary-arith32-imm-dst-Prefixed smode dmode wstr wbit op suffix opc1 opc2 opc3 sem)
+  (begin
+    (binary-arith-imm-dst-defn 32 (.sym Imm-48- smode) 24-24-Prefixed dmode wstr op suffix
+                              (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-24-Prefixed- dmode) (.sym Imm-48- smode))
+                              sem)
+    (binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 24-16-Prefixed dmode wstr op suffix
+                              (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-16-Prefixed- dmode) (.sym Imm-40- smode))
+                              sem)
+    (binary-arith-imm-dst-defn 32 (.sym Imm-32- smode) 24-8-Prefixed dmode wstr op suffix
+                              (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-8-Prefixed- dmode) (.sym Imm-32- smode))
+                              sem)
+    (binary-arith-imm-dst-defn 32 (.sym Imm-24- smode) basic-Prefixed dmode wstr op suffix
+                              (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-basic-Prefixed- dmode) (.sym Imm-24- smode))
+                              sem)
+  )
+)
+
+; All m32c variants
+(define-pmacro (binary-arith32-imm-dst-defn smode dmode wstr wbit op suffix opc1 opc2 opc3 sem)
+  (begin
+    ; Multi insns are tried for assembly in the reverse order in which they appear here, so
+    ; define the absolute-indirect insns first in order to prevent them from being selected
+    ; when the mode is register-indirect
+;     (binary-arith-imm-dst-defn 32 (.sym Imm-48- smode) 24-24-absolute-indirect dmode wstr op suffix
+;                             (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-24-absolute-indirect- dmode) (.sym Imm-48- smode))
+;                             sem)
+;     (binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 24-16-absolute-indirect dmode wstr op suffix
+;                             (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-16-absolute-indirect- dmode) (.sym Imm-40- smode))
+;                             sem)
+    ; Unprefixed modes next
+    (binary-arith32-imm-dst-Unprefixed smode dmode wstr wbit op suffix opc1 opc2 opc3 sem)
+
+    ; Remaining indirect modes
+;     (binary-arith-imm-dst-defn 32 (.sym Imm-24- smode) basic-indirect dmode wstr op suffix
+;                             (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-basic-indirect- dmode) (.sym Imm-24- smode))
+;                             sem)
+;     (binary-arith-imm-dst-defn 32 (.sym Imm-48- smode) 24-24-indirect dmode wstr op suffix
+;                             (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-24-indirect- dmode) (.sym Imm-48- smode))
+;                             sem)
+;     (binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 24-16-indirect dmode wstr op suffix
+;                             (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-16-indirect- dmode) (.sym Imm-40- smode))
+;                             sem)
+;     (binary-arith-imm-dst-defn 32 (.sym Imm-32- smode) 24-8-indirect dmode wstr op suffix
+;                             (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-8-indirect- dmode) (.sym Imm-32- smode))
+;                             sem)
+  )
+)
+
+(define-pmacro (binary-arith-imm-dst-mach mach op suffix opc1 opc2 opc3 sem)
+  (begin
+    (.apply (.sym binary-arith mach -imm-dst-defn) (QI QI .b 0 op suffix opc1 opc2 opc3 sem))
+    (.apply (.sym binary-arith mach -imm-dst-defn) (HI HI .w 1 op suffix opc1 opc2 opc3 sem))
+  )
+)
+
+(define-pmacro (binary-arith-imm-dst op suffix opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
+  (begin
+    (binary-arith-imm-dst-mach 16 op suffix opc16-1 opc16-2 opc16-3 sem)
+    (binary-arith-imm-dst-mach 32 op suffix opc32-1 opc32-2 opc32-3 sem)
+  )
+)
+
+;-------------------------------------------------------------
+;<arith>.size:Q #imm4,dst -- for m16c and m32c
+;-------------------------------------------------------------
+
+(define-pmacro (binary-arith-imm4-dst-defn mach src dstgroup mode wstr op encoding sem)
+  (dni (.sym op mach wstr - imm4-Q - dstgroup)
+       (.str op wstr " " mach "-imm4-Q-" dstgroup "-" mode)
+       ((machine mach) RL_1ADDR)
+       (.str op wstr "$Q #${" src "},${dst" mach "-" dstgroup "-" mode "}")
+       encoding
+       (sem mode src (.sym dst mach - dstgroup - mode))
+       ())
+)
+
+; m16c variants
+(define-pmacro (binary-arith16-imm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem)
+  (binary-arith-imm4-dst-defn 16 Imm-8-s4 16 mode wstr op
+                  (+ opc1 opc2 (f-7-1 wbit2) Imm-8-s4 (.sym dst16-16- mode))
+                  sem)
+)
+
+(define-pmacro (binary-arith16-shimm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem)
+  (binary-arith-imm4-dst-defn 16 Imm-sh-8-s4 16 mode wstr op
+                  (+ opc1 opc2 (f-7-1 wbit2) Imm-sh-8-s4 (.sym dst16-16- mode))
+                  sem)
+)
+
+; m32c variants
+(define-pmacro (binary-arith32-imm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem)
+  (begin
+    ; Multi insns are tried for assembly in the reverse order in which they appear here, so
+    ; define the absolute-indirect insns first in order to prevent them from being selected
+    ; when the mode is register-indirect
+;     (binary-arith-imm4-dst-defn 32 Imm-20-s4 24-absolute-indirect mode wstr op
+;                   (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-absolute-indirect- mode) (f-18-2 opc2) Imm-20-s4)
+;                   sem)
+    (binary-arith-imm4-dst-defn 32 Imm-12-s4 16-Unprefixed mode wstr op
+                    (+ (f-0-3 opc1) (f-3-1 wbit1) (f-7-1 wbit2) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) Imm-12-s4)
+                    sem)
+;     (binary-arith-imm4-dst-defn 32 Imm-20-s4 24-indirect mode wstr op
+;                   (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-indirect- mode) (f-18-2 opc2) Imm-20-s4)
+;                   sem)
+  )
+)
+
+(define-pmacro (binary-arith32-shimm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem)
+  (begin
+    ; Multi insns are tried for assembly in the reverse order in which they appear here, so
+    ; define the absolute-indirect insns first in order to prevent them from being selected
+    ; when the mode is register-indirect
+;     (binary-arith-imm4-dst-defn 32 Imm-sh-20-s4 24-absolute-indirect mode wstr op
+;                   (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-absolute-indirect- mode) (f-18-2 opc2) Imm-sh-20-s4)
+;                   sem)
+    (binary-arith-imm4-dst-defn 32 Imm-sh-12-s4 16-Unprefixed mode wstr op
+                    (+ (f-0-3 opc1) (f-3-1 wbit1) (f-7-1 wbit2) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) Imm-sh-12-s4)
+                    sem)
+;     (binary-arith-imm4-dst-defn 32 Imm-sh-20-s4 24-indirect mode wstr op
+;                   (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-indirect- mode) (f-18-2 opc2) Imm-sh-20-s4)
+;                   sem)
+  )
+)
+
+(define-pmacro (binary-arith-imm4-dst-mach mach op opc1 opc2 sem)
+  (begin
+    (.apply (.sym binary-arith mach -imm4-dst-defn) (QI .b 0 0 op opc1 opc2 sem))
+    (.apply (.sym binary-arith mach -imm4-dst-defn) (HI .w 0 1 op opc1 opc2 sem))
+  )
+)
+
+(define-pmacro (binary-arith-imm4-dst op opc16-1 opc16-2 opc32-1 opc32-2 sem)
+  (begin
+    (binary-arith-imm4-dst-mach 16 op opc16-1 opc16-2 sem)
+    (binary-arith-imm4-dst-mach 32 op opc32-1 opc32-2 sem)
+  )
+)
+
+;-------------------------------------------------------------
+;<arith>.size:G src,dst -- for m16c and m32c
+;-------------------------------------------------------------
+
+(define-pmacro (binary-arith-src-dst-defn mach srcgroup dstgroup smode dmode wstr op suffix encoding sem)
+  (dni (.sym op mach wstr - srcgroup - dstgroup)
+       (.str op wstr " dst" mach "-" srcgroup "-" dstgroup "-" dmode)
+       ((machine mach) RL_2ADDR)
+       (.str op wstr "$" suffix " ${src" mach "-" srcgroup "-" smode "},${dst" mach "-" dstgroup "-" dmode "}")
+       encoding
+       (sem dmode (.sym src mach - srcgroup - smode) (.sym dst mach - dstgroup - dmode))
+       ())
+)
+
+; m16c variants
+(define-pmacro (binary-arith16-src-dst-defn smode dmode wstr wbit op suffix opc1 opc2 sem)
+  (begin
+    (binary-arith-src-dst-defn 16 basic 16 smode dmode wstr op suffix
+                              (+ opc1 opc2 (f-7-1 wbit) (.sym src16-basic- smode) (.sym dst16-16- dmode))
+                              sem)
+    (binary-arith-src-dst-defn 16 16-16 32 smode dmode wstr op suffix
+                              (+ opc1 opc2 (f-7-1 wbit) (.sym src16-16-16- smode) (.sym dst16-32- dmode))
+                              sem)
+    (binary-arith-src-dst-defn 16 16-8 24 smode dmode wstr op suffix
+                              (+ opc1 opc2 (f-7-1 wbit) (.sym src16-16-8- smode) (.sym dst16-24- dmode))
+                              sem)
+  )
+)
+
+; m32c Prefixed variants
+(define-pmacro (binary-arith32-src-dst-Prefixed smode dmode wstr wbit op suffix opc1 opc2 sem)
+  (begin
+    (binary-arith-src-dst-defn 32 basic-Prefixed 24-Prefixed smode dmode wstr op suffix
+                              (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-basic-Prefixed- smode) (.sym dst32-24-Prefixed- dmode) (f-20-4 opc2))
+                              sem)
+    (binary-arith-src-dst-defn 32 24-24-Prefixed 48-Prefixed smode dmode wstr op suffix
+                              (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-24-24-Prefixed- smode) (.sym dst32-48-Prefixed- dmode) (f-20-4 opc2))
+                              sem)
+    (binary-arith-src-dst-defn 32 24-16-Prefixed 40-Prefixed smode dmode wstr op suffix
+                              (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-24-16-Prefixed- smode) (.sym dst32-40-Prefixed- dmode) (f-20-4 opc2))
+                              sem)
+    (binary-arith-src-dst-defn 32 24-8-Prefixed 32-Prefixed smode dmode wstr op suffix
+                              (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-24-8-Prefixed- smode) (.sym dst32-32-Prefixed- dmode) (f-20-4 opc2))
+                              sem)
+  )
+)
+
+; all m32c variants
+(define-pmacro (binary-arith32-src-dst-defn smode dmode wstr wbit op suffix opc1 opc2 sem)
+  (begin
+    ; Multi insns are tried for assembly in the reverse order in which they appear here, so
+    ; define the absolute-indirect insns first in order to prevent them from being selected
+    ; when the mode is register-indirect
+;     (binary-arith-src-dst-defn 32 24-24-absolute-indirect 48-absolute-indirect smode dmode wstr op suffix
+;                             (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
+;                                (.sym src32-24-24-absolute-indirect- smode) (.sym dst32-48-absolute-indirect- dmode) (f-20-4 opc2))
+;                             sem)
+;     (binary-arith-src-dst-defn 32 24-16-absolute-indirect 40-absolute-indirect smode dmode wstr op suffix
+;                             (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
+;                                (.sym src32-24-16-absolute-indirect- smode) (.sym dst32-40-absolute-indirect- dmode) (f-20-4 opc2))
+;                             sem)
+;     (binary-arith-src-dst-defn 32 24-24-absolute-indirect 48-Prefixed smode dmode wstr op suffix
+;                             (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit)
+;                                (.sym src32-24-24-absolute-indirect- smode) (.sym dst32-48-Prefixed- dmode) (f-20-4 opc2))
+;                             sem)
+;     (binary-arith-src-dst-defn 32 24-16-absolute-indirect 40-Prefixed smode dmode wstr op suffix
+;                             (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit)
+;                                (.sym src32-24-16-absolute-indirect- smode) (.sym dst32-40-Prefixed- dmode) (f-20-4 opc2))
+;                             sem)
+;     (binary-arith-src-dst-defn 32 24-24-absolute-indirect 48-indirect smode dmode wstr op suffix
+;                             (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
+;                                (.sym src32-24-24-absolute-indirect- smode) (.sym dst32-48-indirect- dmode) (f-20-4 opc2))
+;                             sem)
+;     (binary-arith-src-dst-defn 32 24-16-absolute-indirect 40-indirect smode dmode wstr op suffix
+;                             (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
+;                                (.sym src32-24-16-absolute-indirect- smode) (.sym dst32-40-indirect- dmode) (f-20-4 opc2))
+;                             sem)
+;     (binary-arith-src-dst-defn 32 basic-Prefixed 24-absolute-indirect smode dmode wstr op suffix
+;                             (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
+;                                (.sym src32-basic-Prefixed- smode) (.sym dst32-24-absolute-indirect- dmode) (f-20-4 opc2))
+;                             sem)
+;     (binary-arith-src-dst-defn 32 24-24-Prefixed 48-absolute-indirect smode dmode wstr op suffix
+;                             (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
+;                                (.sym src32-24-24-Prefixed- smode) (.sym dst32-48-absolute-indirect- dmode) (f-20-4 opc2))
+;                             sem)
+;     (binary-arith-src-dst-defn 32 24-16-Prefixed 40-absolute-indirect smode dmode wstr op suffix
+;                             (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
+;                                (.sym src32-24-16-Prefixed- smode) (.sym dst32-40-absolute-indirect- dmode) (f-20-4 opc2))
+;                             sem)
+;     (binary-arith-src-dst-defn 32 24-8-Prefixed 32-absolute-indirect smode dmode wstr op suffix
+;                             (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
+;                                (.sym src32-24-8-Prefixed- smode) (.sym dst32-32-absolute-indirect- dmode) (f-20-4 opc2))
+;                             sem)
+;     (binary-arith-src-dst-defn 32 basic-indirect 24-absolute-indirect smode dmode wstr op suffix
+;                             (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
+;                                (.sym src32-basic-indirect- smode) (.sym dst32-24-absolute-indirect- dmode) (f-20-4 opc2))
+;                             sem)
+;     (binary-arith-src-dst-defn 32 24-24-indirect 48-absolute-indirect smode dmode wstr op suffix
+;                             (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
+;                                (.sym src32-24-24-indirect- smode) (.sym dst32-48-absolute-indirect- dmode) (f-20-4 opc2))
+;                             sem)
+;     (binary-arith-src-dst-defn 32 24-16-indirect 40-absolute-indirect smode dmode wstr op suffix
+;                             (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
+;                                (.sym src32-24-16-indirect- smode) (.sym dst32-40-absolute-indirect- dmode) (f-20-4 opc2))
+;                             sem)
+;     (binary-arith-src-dst-defn 32 24-8-indirect 32-absolute-indirect smode dmode wstr op suffix
+;                             (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
+;                                (.sym src32-24-8-indirect- smode) (.sym dst32-32-absolute-indirect- dmode) (f-20-4 opc2))
+;                             sem)
+    (binary-arith-src-dst-defn 32 basic-Unprefixed 16-Unprefixed smode dmode wstr op suffix
+                              (+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-basic-Unprefixed- smode) (.sym dst32-16-Unprefixed- dmode) (f-12-4 opc2))
+                              sem)
+    (binary-arith-src-dst-defn 32 16-24-Unprefixed 40-Unprefixed smode dmode wstr op suffix
+                              (+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-16-24-Unprefixed- smode) (.sym dst32-40-Unprefixed- dmode) (f-12-4 opc2))
+                              sem)
+    (binary-arith-src-dst-defn 32 16-16-Unprefixed 32-Unprefixed smode dmode wstr op suffix
+                              (+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-16-16-Unprefixed- smode) (.sym dst32-32-Unprefixed- dmode) (f-12-4 opc2))
+                              sem)
+    (binary-arith-src-dst-defn 32 16-8-Unprefixed 24-Unprefixed smode dmode wstr op suffix
+                              (+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-16-8-Unprefixed- smode) (.sym dst32-24-Unprefixed- dmode) (f-12-4 opc2))
+                              sem)
+;     (binary-arith-src-dst-defn 32 basic-indirect 24-Prefixed smode dmode wstr op suffix
+;                             (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit)
+;                                (.sym src32-basic-indirect- smode) (.sym dst32-24-Prefixed- dmode) (f-20-4 opc2))
+;                             sem)
+;     (binary-arith-src-dst-defn 32 24-24-indirect 48-Prefixed smode dmode wstr op suffix
+;                             (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit)
+;                                (.sym src32-24-24-indirect- smode) (.sym dst32-48-Prefixed- dmode) (f-20-4 opc2))
+;                             sem)
+;     (binary-arith-src-dst-defn 32 24-16-indirect 40-Prefixed smode dmode wstr op suffix
+;                             (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit)
+;                                (.sym src32-24-16-indirect- smode) (.sym dst32-40-Prefixed- dmode) (f-20-4 opc2))
+;                             sem)
+;     (binary-arith-src-dst-defn 32 24-8-indirect 32-Prefixed smode dmode wstr op suffix
+;                             (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit)
+;                                (.sym src32-24-8-indirect- smode) (.sym dst32-32-Prefixed- dmode) (f-20-4 opc2))
+;                             sem)
+;     (binary-arith-src-dst-defn 32 basic-Prefixed 24-indirect smode dmode wstr op suffix
+;                             (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
+;                                (.sym src32-basic-Prefixed- smode) (.sym dst32-24-indirect- dmode) (f-20-4 opc2))
+;                             sem)
+;     (binary-arith-src-dst-defn 32 24-24-Prefixed 48-indirect smode dmode wstr op suffix
+;                             (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
+;                                (.sym src32-24-24-Prefixed- smode) (.sym dst32-48-indirect- dmode) (f-20-4 opc2))
+;                             sem)
+;     (binary-arith-src-dst-defn 32 24-16-Prefixed 40-indirect smode dmode wstr op suffix
+;                             (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
+;                                (.sym src32-24-16-Prefixed- smode) (.sym dst32-40-indirect- dmode) (f-20-4 opc2))
+;                             sem)
+;     (binary-arith-src-dst-defn 32 24-8-Prefixed 32-indirect smode dmode wstr op suffix
+;                             (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
+;                                (.sym src32-24-8-Prefixed- smode) (.sym dst32-32-indirect- dmode) (f-20-4 opc2))
+;                             sem)
+;     (binary-arith-src-dst-defn 32 basic-indirect 24-indirect smode dmode wstr op suffix
+;                             (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
+;                                (.sym src32-basic-indirect- smode) (.sym dst32-24-indirect- dmode) (f-20-4 opc2))
+;                             sem)
+;     (binary-arith-src-dst-defn 32 24-24-indirect 48-indirect smode dmode wstr op suffix
+;                             (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
+;                                (.sym src32-24-24-indirect- smode) (.sym dst32-48-indirect- dmode) (f-20-4 opc2))
+;                             sem)
+;     (binary-arith-src-dst-defn 32 24-16-indirect 40-indirect smode dmode wstr op suffix
+;                             (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
+;                                (.sym src32-24-16-indirect- smode) (.sym dst32-40-indirect- dmode) (f-20-4 opc2))
+;                             sem)
+;     (binary-arith-src-dst-defn 32 24-8-indirect 32-indirect smode dmode wstr op suffix
+;                             (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
+;                                (.sym src32-24-8-indirect- smode) (.sym dst32-32-indirect- dmode) (f-20-4 opc2))
+;                             sem)
+  )
+)
+
+(define-pmacro (binary-arith-src-dst-mach mach op suffix opc1 opc2 sem)
+  (begin
+    (.apply (.sym binary-arith mach -src-dst-defn) (QI QI .b 0 op suffix opc1 opc2 sem))
+    (.apply (.sym binary-arith mach -src-dst-defn) (HI HI .w 1 op suffix opc1 opc2 sem))
+  )
+)
+
+(define-pmacro (binary-arith-src-dst op suffix opc16-1 opc16-2 opc32-1 opc32-2 sem)
+  (begin
+    (binary-arith-src-dst-mach 16 op suffix opc16-1 opc16-2 sem)
+    (binary-arith-src-dst-mach 32 op suffix opc32-1 opc32-2 sem)
+  )
+)
+
+;-------------------------------------------------------------
+;<arith>.size:S #imm,dst -- for m32c
+;-------------------------------------------------------------
+
+(define-pmacro (binary-arith32-s-imm-dst-defn src dstgroup mode wstr op encoding sem)
+  (dni (.sym op 32 wstr - imm-S - dstgroup)
+       (.str op wstr " 32-imm-S-" dstgroup "-" mode)
+       ((machine 32))
+       (.str op wstr "$S #${" src "},${dst32-" dstgroup "-" mode "}")
+       encoding
+       (sem mode src (.sym dst32- dstgroup - mode))
+       ())
+)
+
+(define-pmacro (binary-arith32-z-imm-dst-defn src dstgroup mode wstr op encoding sem)
+  (dni (.sym op 32 wstr - imm-Z - dstgroup)
+       (.str op wstr " 32-imm-Z-" dstgroup "-" mode)
+       ((machine 32))
+       (.str op wstr "$Z #0,${dst32-" dstgroup "-" mode "}")
+       encoding
+       (sem mode (const 0) (.sym dst32- dstgroup - mode))
+       ())
+)
+
+(define-pmacro (binary-arith32-s-imm-dst mode wstr wbit op opc1 opc2 sem)
+  (begin
+;     (binary-arith32-s-imm-dst-defn (.sym Imm-32- mode) 2-S-absolute-indirect mode wstr op
+;                             (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-absolute-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-32- mode))
+;                             sem)
+    (binary-arith32-s-imm-dst-defn (.sym Imm-8- mode) 2-S-basic mode wstr op
+                              (+ (f-0-2 opc1) (.sym dst32-2-S-basic- mode) (f-4-3 opc2) (f-7-1 wbit) (.sym Imm-8- mode))
+                              sem)
+    (binary-arith32-s-imm-dst-defn (.sym Imm-24- mode) 2-S-16 mode wstr op
+                              (+ (f-0-2 opc1) (.sym dst32-2-S-16- mode) (f-4-3 opc2) (f-7-1 wbit) (.sym Imm-24- mode))
+                              sem)
+    (binary-arith32-s-imm-dst-defn (.sym Imm-16- mode) 2-S-8 mode wstr op
+                              (+ (f-0-2 opc1) (.sym dst32-2-S-8- mode) (f-4-3 opc2) (f-7-1 wbit) (.sym Imm-16- mode))
+                              sem)
+;     (binary-arith32-s-imm-dst-defn (.sym Imm-24- mode) 2-S-8-indirect mode wstr op
+;                             (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-8-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-24- mode))
+;                             sem)
+  )
+)
+
+(define-pmacro (binary-arith32-z-imm-dst mode wstr wbit op opc1 opc2 sem)
+  (begin
+;     (binary-arith32-z-imm-dst-defn (.sym Imm-32- mode) 2-S-absolute-indirect mode wstr op
+;                             (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-absolute-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-32- mode))
+;                             sem)
+    (binary-arith32-z-imm-dst-defn (.sym Imm-8- mode) 2-S-basic mode wstr op
+                              (+ (f-0-2 opc1) (.sym dst32-2-S-basic- mode) (f-4-3 opc2) (f-7-1 wbit))
+                              sem)
+    (binary-arith32-z-imm-dst-defn (.sym Imm-24- mode) 2-S-16 mode wstr op
+                              (+ (f-0-2 opc1) (.sym dst32-2-S-16- mode) (f-4-3 opc2) (f-7-1 wbit))
+                              sem)
+    (binary-arith32-z-imm-dst-defn (.sym Imm-16- mode) 2-S-8 mode wstr op
+                              (+ (f-0-2 opc1) (.sym dst32-2-S-8- mode) (f-4-3 opc2) (f-7-1 wbit))
+                              sem)
+;     (binary-arith32-z-imm-dst-defn (.sym Imm-24- mode) 2-S-8-indirect mode wstr op
+;                             (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-8-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-24- mode))
+;                             sem)
+  )
+)
+
+;-------------------------------------------------------------
+;<arith>.L:S #imm1,An -- for m32c
+;-------------------------------------------------------------
+
+(define-pmacro (binary-arith32-l-s-imm1-an op opc1 opc2 sem)
+  (begin
+    (dni (.sym op 32.l-s-imm1-S-an)
+        (.str op ".l 32-imm1-S-an")
+        ((machine 32))
+        (.str op ".l$S #${Imm1-S},${dst32-an-S}")
+        (+ opc1 Imm1-S opc2 dst32-an-S)
+        (sem SI Imm1-S dst32-an-S)
+        ())
+  )
+)
+
+;-------------------------------------------------------------
+;<arith>.L:Q #imm3,sp -- for m32c
+;-------------------------------------------------------------
+
+(define-pmacro (binary-arith32-l-q-imm3-sp op opc1 opc2 sem)
+  (begin
+    (dni (.sym op 32.l-imm3-Q)
+        (.str op ".l 32-imm3-Q")
+        ((machine 32))
+        (.str op ".l$Q #${Imm3-S},sp")
+        (+ opc1 Imm3-S opc2)
+        (sem SI Imm3-S sp)
+        ())
+  )
+)
+
+;-------------------------------------------------------------
+;<arith>.L:S #imm8,sp -- for m32c
+;-------------------------------------------------------------
+
+(define-pmacro (binary-arith32-l-s-imm8-sp op opc1 opc2 opc3 opc4 sem)
+  (begin
+    (dni (.sym op 32.l-imm8-S)
+        (.str op ".l 32-imm8-S")
+        ((machine 32))
+        (.str op ".l$S #${Imm-16-QI},sp")
+        (+ opc1 opc2 opc3 opc4 Imm-16-QI)
+        (sem SI Imm-16-QI sp)
+        ())
+  )
+)
+
+;-------------------------------------------------------------
+;<arith>.L:G #imm16,sp -- for m32c
+;-------------------------------------------------------------
+
+(define-pmacro (binary-arith32-l-g-imm16-sp op opc1 opc2 opc3 opc4 sem)
+  (begin
+    (dni (.sym op 32.l-imm16-G)
+        (.str op ".l 32-imm16-G")
+        ((machine 32))
+        (.str op ".l$G #${Imm-16-HI},sp")
+        (+ opc1 opc2 opc3 opc4 Imm-16-HI)
+        (sem SI Imm-16-HI sp)
+        ())
+  )
+)
+
+;-------------------------------------------------------------
+;<arith>jnz.size #imm4,dst,label -- for m16c and m32c
+;-------------------------------------------------------------
+
+(define-pmacro (arith-jnz-imm4-dst-defn mach src dstgroup label mode wstr op encoding sem)
+  (dni (.sym op mach wstr - imm4 - dstgroup)
+       (.str op wstr " " mach "-imm4-" dstgroup "-" label "-" mode)
+       (RL_JUMP RELAXABLE (machine mach))
+       (.str op wstr " #${" src "},${dst" mach "-" dstgroup "-" mode "},${" label "}")
+       encoding
+       (sem mode src (.sym dst mach - dstgroup - mode) label)
+       ())
+)
+
+; m16c variants
+(define-pmacro (arith-jnz16-imm4-dst-defn mode wstr wbit op i4n opc1 opc2 sem)
+  (begin
+    (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) basic Lab-16-8 mode wstr op
+                            (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-basic- mode) Lab-16-8)
+                            sem)
+    (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) 16-16 Lab-32-8 mode wstr op
+                            (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-16- mode) Lab-32-8)
+                            sem)
+    (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) 16-8 Lab-24-8 mode wstr op
+                            (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-8- mode) Lab-24-8)
+                            sem)
+  )
+)
+
+; m32c variants
+(define-pmacro (arith-jnz32-imm4-dst-defn mode wstr wbit op i4n opc1 opc2 sem)
+  (begin
+    (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) basic-Unprefixed Lab-16-8 mode wstr op
+                    (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-16-8)
+                    sem)
+    (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-24-Unprefixed Lab-40-8 mode wstr op
+                    (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-40-8)
+                    sem)
+    (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-16-Unprefixed Lab-32-8 mode wstr op
+                    (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-32-8)
+                    sem)
+    (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-8-Unprefixed Lab-24-8 mode wstr op
+                    (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-24-8)
+                    sem)
+  )
+)
+
+(define-pmacro (arith-jnz-imm4-dst-mach mach op i4n opc1 opc2 sem)
+  (begin
+    (.apply (.sym arith-jnz mach -imm4-dst-defn) (QI .b 0 op i4n opc1 opc2 sem))
+    (.apply (.sym arith-jnz mach -imm4-dst-defn) (HI .w 1 op i4n opc1 opc2 sem))
+  )
+)
+
+(define-pmacro (arith-jnz-imm4-dst op i4n opc16-1 opc16-2 opc32-1 opc32-2 sem)
+  (begin
+    (arith-jnz-imm4-dst-mach 16 op i4n opc16-1 opc16-2 sem)
+    (arith-jnz-imm4-dst-mach 32 op i4n opc32-1 opc32-2 sem)
+  )
+)
+
+;-------------------------------------------------------------
+;mov.size dsp8[sp],dst -- for m16c and m32c
+;-------------------------------------------------------------
+(define-pmacro (mov-dspsp-dst-defn mach dstgroup dsp mode wstr op encoding sem)
+  (dni (.sym op mach wstr -dspsp-dst- dstgroup)
+       (.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode)
+       ((machine mach))
+       (.str op wstr "$G ${" dsp "}[sp],${dst" mach "-" dstgroup "-" mode "}")
+       encoding
+       (sem mach mode dsp (.sym dst mach - dstgroup - mode))
+       ())
+)
+(define-pmacro (mov-src-dspsp-defn mach dstgroup dsp mode wstr op encoding sem)
+  (dni (.sym op mach wstr -dst-dspsp- dstgroup)
+       (.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode)
+       ((machine mach))
+       (.str op wstr "$G ${dst" mach "-" dstgroup "-" mode "},${" dsp "}[sp]")
+       encoding
+       (sem mach mode (.sym dst mach - dstgroup - mode) dsp)
+       ())
+)
+
+; m16c variants
+(define-pmacro (mov16-dspsp-dst-defn mode wstr wbit op opc1 opc2 opc3 sem)
+  (begin
+    (mov-dspsp-dst-defn 16 basic Dsp-16-s8 mode wstr op
+                            (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-s8)
+                            sem)
+    (mov-dspsp-dst-defn 16 16-16 Dsp-32-s8 mode wstr op
+                            (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-s8)
+                            sem)
+    (mov-dspsp-dst-defn 16 16-8 Dsp-24-s8 mode wstr op
+                            (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-s8)
+                            sem)
+  )
+)
+
+(define-pmacro (mov16-src-dspsp-defn mode wstr wbit op opc1 opc2 opc3 sem)
+  (begin
+    (mov-src-dspsp-defn 16 basic Dsp-16-s8 mode wstr op
+                            (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-s8)
+                            sem)
+    (mov-src-dspsp-defn 16 16-16 Dsp-32-s8 mode wstr op
+                            (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-s8)
+                            sem)
+    (mov-src-dspsp-defn 16 16-8 Dsp-24-s8 mode wstr op
+                            (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-s8)
+                            sem)
+  )
+)
+
+; m32c variants
+(define-pmacro (mov32-dspsp-dst-defn mode wstr wbit op opc1 opc2 opc3 sem)
+  (begin
+    (mov-dspsp-dst-defn 32 basic-Unprefixed Dsp-16-s8 mode wstr op
+                    (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-16-s8)
+                    sem)
+    (mov-dspsp-dst-defn 32 16-24-Unprefixed Dsp-40-s8 mode wstr op
+                    (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-40-s8)
+                    sem)
+    (mov-dspsp-dst-defn 32 16-16-Unprefixed Dsp-32-s8 mode wstr op
+                    (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-32-s8)
+                    sem)
+    (mov-dspsp-dst-defn 32 16-8-Unprefixed Dsp-24-s8 mode wstr op
+                    (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-24-s8)
+                    sem)
+  )
+)
+(define-pmacro (mov32-src-dspsp-defn mode wstr wbit op opc1 opc2 opc3 sem)
+  (begin
+    (mov-src-dspsp-defn 32 basic-Unprefixed Dsp-16-s8 mode wstr op
+                    (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-16-s8)
+                    sem)
+    (mov-src-dspsp-defn 32 16-24-Unprefixed Dsp-40-s8 mode wstr op
+                    (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-40-s8)
+                    sem)
+    (mov-src-dspsp-defn 32 16-16-Unprefixed Dsp-32-s8 mode wstr op
+                    (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-32-s8)
+                    sem)
+    (mov-src-dspsp-defn 32 16-8-Unprefixed Dsp-24-s8 mode wstr op
+                    (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-24-s8)
+                    sem)
+  )
+)
+
+(define-pmacro (mov-src-dspsp-mach mach op opc1 opc2 opc3 sem)
+  (begin
+    (.apply (.sym mov mach -src-dspsp-defn) (QI .b 0 op opc1 opc2 opc3 sem))
+    (.apply (.sym mov mach -src-dspsp-defn) (HI .w 1 op opc1 opc2 opc3 sem))
+  )
+)
+
+(define-pmacro (mov-dspsp-dst-mach mach op opc1 opc2 opc3 sem)
+  (begin
+    (.apply (.sym mov mach -dspsp-dst-defn) (QI .b 0 op opc1 opc2 opc3 sem))
+    (.apply (.sym mov mach -dspsp-dst-defn) (HI .w 1 op opc1 opc2 opc3 sem))
+  )
+)
+
+(define-pmacro (mov-dspsp-dst op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
+  (begin
+    (mov-dspsp-dst-mach 16 op opc16-1 opc16-2 opc16-3 sem)
+    (mov-dspsp-dst-mach 32 op opc32-1 opc32-2 opc32-3 sem)
+  )
+)
+(define-pmacro (mov-src-dspsp op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
+  (begin
+    (mov-src-dspsp-mach 16 op opc16-1 opc16-2 opc16-3 sem)
+    (mov-src-dspsp-mach 32 op opc32-1 opc32-2 opc32-3 sem)
+  )
+)
+
+;-------------------------------------------------------------
+; lde dsp24,dst -- for m16c
+;-------------------------------------------------------------
+
+(define-pmacro (lde-dst-dsp mode wstr wbit dstgroup srcdisp)
+  (begin
+
+    (dni (.sym lde wstr - dstgroup -u20)
+        (.str "lde" wstr "-" dstgroup "-u20")
+        ((machine 16))
+        (.str "lde" wstr " ${" srcdisp "},${dst16-" dstgroup "-" mode "}")
+        (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x8)
+         (.sym dst16- dstgroup - mode) srcdisp)
+        (nop)
+        ())
+
+    (dni (.sym lde wstr - dstgroup -u20a0)
+        (.str "lde" wstr "-" dstgroup "-u20a0")
+        ((machine 16))
+        (.str "lde" wstr " ${" srcdisp "}[a0],${dst16-" dstgroup "-" mode "}")
+        (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x9)
+         (.sym dst16- dstgroup - mode) srcdisp)
+        (nop)
+        ())
+
+    (dni (.sym lde wstr - dstgroup -a1a0)
+        (.str "lde" wstr "-" dstgroup "-a1a0")
+        ((machine 16))
+        (.str "lde" wstr " [a1a0],${dst16-" dstgroup "-" mode "}")
+        (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #xa)
+         (.sym dst16- dstgroup - mode))
+        (nop)
+        ())
+    )
+  )
+
+(define-pmacro (lde-dst mode wstr wbit)
+  (begin
+    ; like:       QI   .b   0 
+    (lde-dst-dsp mode wstr wbit basic Dsp-16-u20)
+    (lde-dst-dsp mode wstr wbit 16-8  Dsp-24-u20)
+    (lde-dst-dsp mode wstr wbit 16-16 Dsp-32-u20)
+  )
+)
+
+;-------------------------------------------------------------
+; ste dst,dsp24 -- for m16c
+;-------------------------------------------------------------
+
+(define-pmacro (ste-dst-dsp mode wstr wbit dstgroup srcdisp)
+  (begin
+
+    (dni (.sym ste wstr - dstgroup -u20)
+        (.str "ste" wstr "-" dstgroup "-u20")
+        ((machine 16))
+        (.str "ste" wstr " ${dst16-" dstgroup "-" mode "},${" srcdisp "}")
+        (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x0)
+         (.sym dst16- dstgroup - mode) srcdisp)
+        (nop)
+        ())
+
+    (dni (.sym ste wstr - dstgroup -u20a0)
+        (.str "ste" wstr "-" dstgroup "-u20a0")
+        ((machine 16))
+        (.str "ste" wstr " ${dst16-" dstgroup "-" mode "},${" srcdisp "}[a0]")
+        (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x1)
+         (.sym dst16- dstgroup - mode) srcdisp)
+        (nop)
+        ())
+
+    (dni (.sym ste wstr - dstgroup -a1a0)
+        (.str "ste" wstr "-" dstgroup "-a1a0")
+        ((machine 16))
+        (.str "ste" wstr " ${dst16-" dstgroup "-" mode "},[a1a0]")
+        (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x2)
+         (.sym dst16- dstgroup - mode))
+        (nop)
+        ())
+    )
+  )
+
+(define-pmacro (ste-dst mode wstr wbit)
+  (begin
+    ; like:       QI   .b   0 
+    (ste-dst-dsp mode wstr wbit basic Dsp-16-u20)
+    (ste-dst-dsp mode wstr wbit 16-8  Dsp-24-u20)
+    (ste-dst-dsp mode wstr wbit 16-16 Dsp-32-u20)
+  )
+)
+
+;=============================================================
+; Division
+;-------------------------------------------------------------
+
+(define-pmacro (div-sem divop modop opmode reg src quot rem max min)
+  (sequence ()
+           (if (eq src 0)
+               (set obit (const BI 1))
+               (sequence ((opmode quot-result) (opmode rem-result))
+                         (set quot-result (divop opmode (ext opmode reg) src))
+                         (set rem-result  (modop opmode (ext opmode reg) src))
+                         (set obit (orif (gt opmode quot-result max)
+                                         (lt opmode quot-result min)))
+                         (set quot quot-result)
+                         (set rem  rem-result))))
+)
+
+;<divop>.size #imm -- for m16c and m32c
+(define-pmacro (div-imm-defn mach wstr op src encoding divop modop opmode reg quot rem max min sem)
+  (dni (.sym op mach wstr - src)
+       (.str op mach wstr "-" src)
+       ((machine mach))
+       (.str op wstr " #${" src "}")
+       encoding
+       (sem divop modop opmode reg src quot rem max min)
+       ())
+)
+(define-pmacro (div16-imm-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 opc4 sem)
+  (div-imm-defn 16 wstr op (.sym Imm-16 - smode)
+               (+ opc1 opc2 (f-7-1 wbit) opc3 opc4 (.sym Imm-16 - smode))
+               divop modop opmode reg quot rem max min
+               sem)
+)
+(define-pmacro (div32-imm-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 opc4 sem)
+  (div-imm-defn 32 wstr op (.sym Imm-16 - smode)
+               (+ (f-0-4 opc1) (f-4-4 opc2) (f-8-3 opc3) (f-11-1 wbit) (f-12-4 opc4) (.sym Imm-16 - smode))
+               divop modop opmode reg quot rem max min
+               sem)
+)
+(define-pmacro (div-imm-mach mach op divop modop opmode max-QI min-QI max-HI min-HI opc1 opc2 opc3 opc4 sem)
+  (begin
+    (.apply (.sym div mach -imm-defn) (QI .b 0 op divop modop opmode R0   R0l R0h max-QI min-QI opc1 opc2 opc3 opc4 sem))
+    (.apply (.sym div mach -imm-defn) (HI .w 1 op divop modop opmode R2R0 R0  R2  max-HI min-HI opc1 opc2 opc3 opc4 sem))
+  )
+)
+(define-pmacro (div-imm op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 opc16-4 opc32-1 opc32-2 opc32-3 opc32-4 sem)
+  (begin
+    (div-imm-mach 16 op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 opc16-4 sem)
+    (div-imm-mach 32 op divop modop opmode max-QI min-QI max-HI min-HI opc32-1 opc32-2 opc32-3 opc32-4 sem)
+  )
+)
+
+;<divop>.size src -- for m16c and m32c
+(define-pmacro (div-src-defn mach wstr op src encoding divop modop opmode reg quot rem max min sem)
+  (dni (.sym op mach wstr - src)
+       (.str op mach wstr "-" src)
+       ((machine mach))
+       (.str op wstr " ${" src "}")
+       encoding
+       (sem divop modop opmode reg src quot rem max min)
+       ())
+)
+(define-pmacro (div16-src-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 sem)
+  (div-src-defn 16 wstr op (.sym dst16-16 - smode)
+               (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16 - smode))
+               divop modop opmode reg quot rem max min
+               sem)
+)
+(define-pmacro (div32-src-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 sem)
+  (begin
+    ; Multi insns are tried for assembly in the reverse order in which they appear here, so
+    ; define the absolute-indirect insns first in order to prevent them from being selected
+    ; when the mode is register-indirect
+;     (div-src-defn 32 wstr op (.sym dst32-24-absolute-indirect- smode)
+;                (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (f-18-2 opc2) (f-20-4 opc3) (.sym dst32-24-absolute-indirect - smode))
+;                divop modop opmode reg quot rem max min
+;                sem)
+    (div-src-defn 32 wstr op (.sym dst32-16-Unprefixed- smode)
+                 (+ (f-0-4 opc1) (f-7-1 wbit) (f-10-2 opc2) (f-12-4 opc3) (.sym dst32-16-Unprefixed- smode))
+                 divop modop opmode reg quot rem max min
+                 sem)
+;     (div-src-defn 32 wstr op (.sym dst32-24-indirect- smode)
+;                (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (f-18-2 opc2) (f-20-4 opc3) (.sym dst32-24-indirect - smode))
+;                divop modop opmode reg quot rem max min
+;                sem)
+  )
+)
+(define-pmacro (div-src-mach mach op divop modop opmode max-QI min-QI max-HI min-HI opc1 opc2 opc3 sem)
+  (begin
+    (.apply (.sym div mach -src-defn) (QI .b 0 op divop modop opmode R0   R0l R0h max-QI min-QI opc1 opc2 opc3 sem))
+    (.apply (.sym div mach -src-defn) (HI .w 1 op divop modop opmode R2R0 R0  R2  max-HI min-HI opc1 opc2 opc3 sem))
+  )
+)
+(define-pmacro (div-src op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
+  (begin
+    (div-src-mach 16 op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 sem)
+    (div-src-mach 32 op divop modop opmode max-QI min-QI max-HI min-HI opc32-1 opc32-2 opc32-3 sem)
+  )
+)
+
+;=============================================================
+; Bit manipulation
+;
+(define-pmacro (bit-insn-defn mach op suffix opnd encoding sem)
+  (dni (.sym op mach - suffix - opnd)
+       (.str op mach ":" suffix " " opnd)
+       ((machine mach))
+       (.str op "$" suffix " ${" opnd "}")
+       encoding
+       (sem opnd)
+       ())
+)
+
+(define-pmacro (bitsrc16-defn op opc1 opc2 opc3 sem)
+  (bit-insn-defn 16 op X bit16-16
+                (+ opc1 opc2 opc3 bit16-16)
+                sem)
+)
+
+(define-pmacro (bitsrc32-defn op opc1 opc2 opc3 sem)
+  (begin
+    (bit-insn-defn 32 op X bit32-24-Prefixed
+                  (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) bit32-24-Prefixed (f-15-1 opc2) (f-18-3 opc3))
+                  sem)
+  )
+)
+
+(define-pmacro (bitsrc-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
+  (begin
+    (bitsrc16-defn op opc16-1 opc16-2 opc16-3 sem)
+    (bitsrc32-defn op opc32-1 opc32-2 opc32-3 sem)
+  )
+)
+
+(define-pmacro (bitdst16-defn op opc1 opc2 opc3 opc4 opc5 opc6 sem)
+  (begin
+    (bit-insn-defn 16 op G bit16-16-basic (+ opc1 opc2 opc3 bit16-16-basic) sem)
+    (bit-insn-defn 16 op G bit16-16-16    (+ opc1 opc2 opc3 bit16-16-16) sem)
+    (bit-insn-defn 16 op S bit16-11-S     (+ opc4 opc5 opc6 bit16-11-S) sem)
+    (bit-insn-defn 16 op G bit16-16-8     (+ opc1 opc2 opc3 bit16-16-8) sem)
+  )
+)
+
+(define-pmacro (bitdst32-defn op opc1 opc2 opc3 sem)
+  (begin
+    (bit-insn-defn 32 op X bit32-16-Unprefixed
+                  (+ (f-0-4 opc1) bit32-16-Unprefixed (f-7-1 opc2) (f-10-3 opc3))
+                  sem)
+  )
+)
+
+(define-pmacro (bitdstnos-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
+  (begin
+    (bitsrc16-defn op opc16-1 opc16-2 opc16-3 sem)
+    (bitdst32-defn op opc32-1 opc32-2 opc32-3 sem)
+  )
+)
+
+(define-pmacro (bitdst-insn op opc16-1 opc16-2 opc16-3 opc16-4 opc16-5 opc16-6 opc32-1 opc32-2 opc32-3 sem)
+  (begin
+    (bitdst16-defn op opc16-1 opc16-2 opc16-3 opc16-4 opc16-5 opc16-6 sem)
+    (bitdst32-defn op opc32-1 opc32-2 opc32-3 sem)
+  )
+)
+
+;=============================================================
+; Bit condition
+;
+(define-pmacro (bitcond-insn-defn mach op bit-opnd cond-opnd encoding sem)
+  (dni (.sym op mach - bit-opnd - cond-opnd)
+       (.str op mach " " bit-opnd " " cond-opnd)
+       ((machine mach))
+       (.str op "${" cond-opnd "} ${" bit-opnd "}")
+       encoding
+       (sem mach bit-opnd cond-opnd)
+       ())
+)
+
+(define-pmacro (bitcond16-defn op opc1 opc2 opc3 sem)
+  (begin
+    (bitcond-insn-defn 16 op bit16-16-basic cond16-16 (+ opc1 opc2 opc3 bit16-16-basic cond16-16) sem)
+    (bitcond-insn-defn 16 op bit16-16-16    cond16-32 (+ opc1 opc2 opc3 bit16-16-16 cond16-32) sem)
+    (bitcond-insn-defn 16 op bit16-16-8     cond16-24 (+ opc1 opc2 opc3 bit16-16-8 cond16-24) sem) 
+  )
+)
+
+(define-pmacro (bitcond32-defn op opc1 opc2 opc3 sem)
+  (begin
+    (bitcond-insn-defn 32 op bit32-16-24-Unprefixed cond32-40
+                      (+ (f-0-4 opc1) bit32-16-24-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-40)
+                      sem)
+    (bitcond-insn-defn 32 op bit32-16-16-Unprefixed cond32-32
+                      (+ (f-0-4 opc1) bit32-16-16-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-32)
+                      sem)
+    (bitcond-insn-defn 32 op bit32-16-8-Unprefixed cond32-24
+                      (+ (f-0-4 opc1) bit32-16-8-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-24)
+                      sem)
+    (bitcond-insn-defn 32 op bit32-basic-Unprefixed cond32-16
+                      (+ (f-0-4 opc1) bit32-basic-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-16)
+                      sem)
+  )
+)
+
+(define-pmacro (bitcond-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
+  (begin
+    (bitcond16-defn op opc16-1 opc16-2 opc16-3 sem)
+    (bitcond32-defn op opc32-1 opc32-2 opc32-3 sem)
+  )
+)
+
+;=============================================================
+;<insn>.size #imm1,#imm2,dst -- for m32c
+;
+(define-pmacro (insn-imm1-imm2-dst-defn src1 src2 dstgroup xmode wstr op encoding sem)
+  (dni (.sym op 32 wstr - src1 - src2 - dstgroup)
+       (.str op 32 wstr "-" src1 "-" src2 "-" dstgroup "-" xmode)
+       ((machine 32))
+       (.str op wstr " #${" src1 "},#${" src2 "},${dst32-" dstgroup "-" xmode "}")
+       encoding
+       (sem xmode src1 src2 (.sym dst32- dstgroup - xmode))
+       ())
+)
+
+; m32c Prefixed variants
+(define-pmacro (insn32-imm1-imm2-dst-Prefixed-defn xmode wstr wbit base1 base2 base3 base4 op opc1 opc2 opc3 sem)
+  (begin
+    (insn-imm1-imm2-dst-defn (.sym Imm-48- xmode) (.sym Imm- base4 - xmode) 24-24-Prefixed xmode wstr op
+                            (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3)
+                               (.sym dst32-24-24-Prefixed- xmode) (.sym Imm-48- xmode) (.sym Imm- base4 - xmode))
+                            sem)
+    (insn-imm1-imm2-dst-defn (.sym Imm-40- xmode) (.sym Imm- base3 - xmode) 24-16-Prefixed xmode wstr op
+                            (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3)
+                               (.sym dst32-24-16-Prefixed- xmode) (.sym Imm-40- xmode) (.sym Imm- base3 - xmode))
+                            sem)
+    (insn-imm1-imm2-dst-defn (.sym Imm-32- xmode) (.sym Imm- base2 - xmode) 24-8-Prefixed xmode wstr op
+                            (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3)
+                               (.sym dst32-24-8-Prefixed- xmode) (.sym Imm-32- xmode) (.sym Imm- base2 - xmode))
+                            sem)
+    (insn-imm1-imm2-dst-defn (.sym Imm-24- xmode) (.sym Imm- base1 - xmode) basic-Prefixed xmode wstr op
+                            (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3)
+                               (.sym dst32-basic-Prefixed- xmode) (.sym Imm-24- xmode) (.sym Imm- base1 - xmode))
+                            sem)
+  )
+)
+
+; m32c Unprefixed variants
+(define-pmacro (insn32-imm1-imm2-dst-Unprefixed-defn xmode wstr wbit base1 base2 base3 base4 op opc1 opc2 opc3 sem)
+  (begin
+    (insn-imm1-imm2-dst-defn (.sym Imm-40- xmode) (.sym Imm- base4 - xmode) 16-24-Unprefixed xmode wstr op
+                            (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3)
+                               (.sym dst32-16-24-Unprefixed- xmode) (.sym Imm-40- xmode) (.sym Imm- base4 - xmode))
+                            sem)
+    (insn-imm1-imm2-dst-defn (.sym Imm-32- xmode) (.sym Imm- base3 - xmode) 16-16-Unprefixed xmode wstr op
+                            (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3)
+                               (.sym dst32-16-16-Unprefixed- xmode) (.sym Imm-32- xmode) (.sym Imm- base3 - xmode))
+                            sem)
+    (insn-imm1-imm2-dst-defn (.sym Imm-24- xmode) (.sym Imm- base2 - xmode) 16-8-Unprefixed xmode wstr op
+                            (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3)
+                               (.sym dst32-16-8-Unprefixed- xmode) (.sym Imm-24- xmode) (.sym Imm- base2 - xmode))
+                            sem)
+    (insn-imm1-imm2-dst-defn (.sym Imm-16- xmode) (.sym Imm- base1 - xmode) basic-Unprefixed xmode wstr op
+                            (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3)
+                               (.sym dst32-basic-Unprefixed- xmode) (.sym Imm-16- xmode) (.sym Imm- base1 - xmode))
+                            sem)
+  )
+)
+
+(define-pmacro (insn-imm1-imm2-dst-Prefixed op opc32-1 opc32-2 opc32-3 sem)
+  (begin
+    (insn32-imm1-imm2-dst-Prefixed-defn QI .b 0 32 40 48 56 op opc32-1 opc32-2 opc32-3 sem)
+    (insn32-imm1-imm2-dst-Prefixed-defn HI .w 1 40 48 56 64 op opc32-1 opc32-2 opc32-3 sem)
+  )
+)
+(define-pmacro (insn-imm1-imm2-dst-Unprefixed op opc32-1 opc32-2 opc32-3 sem)
+  (begin
+    (insn32-imm1-imm2-dst-Unprefixed-defn QI .b 0 24 32 40 48 op opc32-1 opc32-2 opc32-3 sem)
+    (insn32-imm1-imm2-dst-Unprefixed-defn HI .w 1 32 40 48 56 op opc32-1 opc32-2 opc32-3 sem)
+  )
+)
+\f
+;=============================================================
+; Insn definitions
+;-------------------------------------------------------------
+; abs - absolute
+;-------------------------------------------------------------
+
+(define-pmacro (abs-sem mode dst)
+  (sequence ((mode result))
+           (set result (abs mode dst))
+           (set obit (eq result dst))
+           (set-z-and-s result)
+           (set dst result))
+)
+(unary-insn abs (f-0-4 7) (f-4-3 3) (f-8-4 #xF) #xA #x1 #xF abs-sem)
+
+;-------------------------------------------------------------
+; adcf - addition carry flag
+;-------------------------------------------------------------
+
+(define-pmacro (adcf-sem mode dst)
+  (sequence ((mode result))
+           (set result (addc mode dst 0 cbit))
+           (set obit (add-oflag mode dst 0 cbit))
+           (set cbit (add-cflag mode dst 0 cbit))
+           (set-z-and-s result)
+           (set dst result))
+)
+(unary-insn adcf (f-0-4 7) (f-4-3 3) (f-8-4 #xE) #xB #x1 #xE adcf-sem)
+
+;-------------------------------------------------------------
+; add - binary addition
+;-------------------------------------------------------------
+
+(define-pmacro (add-sem mode src1 dst)
+  (sequence ((mode result))
+           (set result (add mode src1 dst))
+           (set obit (add-oflag mode src1 dst 0))
+           (set cbit (add-cflag mode src1 dst 0))
+           (set-z-and-s result)
+           (set dst result))
+)
+
+; add.L:G #imm32,dst (m32 #2)
+(binary-arith32-imm-dst-defn SI SI .l 0 add G #x8 #x3 #x1 add-sem)
+; add.size:G #imm,dst (m16 #1 m32 #1)
+(binary-arith-imm-dst add G (f-0-4 7) (f-4-3 3) (f-8-4 4) #x8 #x2 #xE add-sem)
+; add.size:Q #imm4,dst (m16 #2 m32 #3)
+(binary-arith-imm4-dst add (f-0-4 #xC) (f-4-3 4) #x7 #x3 add-sem)
+(binary-arith32-imm4-dst-defn SI .l 1 0 add #x7 #x3 add-sem)
+; add.b:S #imm8,dst3 (m16 #3)
+(binary-arith16-b-S-imm8-dst3 add ".b" (f-0-4 8) (f-4-1 0) add-sem)
+; add.BW:Q #imm4,sp (m16 #7)
+(binary-arith16-Q-sp add (f-0-4 7) (f-4-4 #xD) (f-8-4 #xB) add-sem)
+(dnmi add16-bQ-sp "add16-bQ-sp" ()
+      "add.b:q #${Imm-12-s4},sp"
+      (emit add16-wQ-sp Imm-12-s4))
+; add.BW:G #imm,sp (m16 #6)
+(binary-arith16-G-sp add (f-0-4 7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #xB) add-sem)
+; add.BW:G src,dst (m16 #4 m32 #6)
+(binary-arith-src-dst add G (f-0-4 #xA) (f-4-3 0) #x1 #x8 add-sem)
+; add.B.S src2,r0l/r0h (m16 #5)
+(binary-arith16-b-S-src2 add (f-0-4 2) (f-4-1 0) add-sem)
+; add.L:G src,dst (m32 #7)
+(binary-arith32-src-dst-defn SI SI .l 1 add G #x1 #x2 add-sem)
+; add.L:S #imm{1,2},A0/A1 (m32 #5)
+(binary-arith32-l-s-imm1-an add (f-0-2 2) (f-3-4 6) add-sem)
+; add.L:Q #imm3,sp (m32 #9)
+(binary-arith32-l-q-imm3-sp add (f-0-2 1) (f-4-3 1) add-sem)
+; add.L:S #imm8,sp (m32 #10)
+(binary-arith32-l-s-imm8-sp add (f-0-4 #xb) (f-4-4 6) (f-8-4 0) (f-12-4 3) add-sem)
+; add.L:G #imm16,sp (m32 #8)
+(binary-arith32-l-g-imm16-sp add (f-0-4 #xb) (f-4-4 6) (f-8-4 1) (f-12-4 3) add-sem)
+; add.BW:S #imm,dst2 (m32 #4)
+(binary-arith32-s-imm-dst QI .b 0 add #x0 #x3 add-sem)
+(binary-arith32-s-imm-dst HI .w 1 add #x0 #x3 add-sem)
+
+;-------------------------------------------------------------
+; adc - binary add with carry
+;-------------------------------------------------------------
+
+(define-pmacro (addc-sem mode src dst)
+  (sequence ((mode result))
+           (set result (addc mode src dst cbit))
+           (set obit (add-oflag mode src dst cbit))
+           (set cbit (add-cflag mode src dst cbit))
+           (set-z-and-s result)
+           (set dst result))
+)
+
+; adc.size:G #imm,dst
+(binary-arith16-imm-dst-defn QI QI .b 0 adc X (f-0-4 7) (f-4-3 3) (f-8-4 6) addc-sem)
+(binary-arith16-imm-dst-defn HI HI .w 1 adc X (f-0-4 7) (f-4-3 3) (f-8-4 6) addc-sem)
+(binary-arith32-imm-dst-Prefixed QI QI .b 0 adc X #x8 #x2 #xE addc-sem)
+(binary-arith32-imm-dst-Prefixed HI HI .w 1 adc X #x8 #x2 #xE addc-sem)
+
+; adc.BW:G src,dst
+(binary-arith16-src-dst-defn QI QI .b 0 adc X (f-0-4 #xB) (f-4-3 0) addc-sem)
+(binary-arith16-src-dst-defn HI HI .w 1 adc X (f-0-4 #xB) (f-4-3 0) addc-sem)
+(binary-arith32-src-dst-Prefixed QI QI .b 0 adc X #x1 #x4 addc-sem)
+(binary-arith32-src-dst-Prefixed HI HI .w 1 adc X #x1 #x4 addc-sem)
+
+;-------------------------------------------------------------
+; dadc - decimal add with carry
+; dadd - decimal addition
+;-------------------------------------------------------------
+
+(define-pmacro (dadc-sem mode src dst)
+  (sequence ((mode result))
+           (set result (subc mode dst src (not cbit)))
+           (set cbit (sub-cflag mode dst src (not cbit)))
+           (set-z-and-s result)
+           (set dst result))
+)
+
+(define-pmacro (decimal-subtraction16-insn op opc1 opc2)
+  (begin
+    ; op.b #imm8,r0l
+    (dni (.sym op 16.b-imm8)
+        (.str op ".b #imm8")
+        ((machine 16))
+        (.str op ".b #${Imm-16-QI},r0l")
+        (+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 opc1) Imm-16-QI)
+        ((.sym op -sem) QI Imm-16-QI R0l)
+        ())
+    ; op.w #imm16,r0
+    (dni (.sym op 16.w-imm16)
+        (.str op ".b #imm16")
+        ((machine 16))
+        (.str op ".w #${Imm-16-HI},r0")
+        (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 opc1) Imm-16-HI)
+        ((.sym op -sem) HI Imm-16-HI R0)
+        ())
+    ; op.b #r0h,r0l
+    (dni (.sym op 16.b-r0h-r0l)
+        (.str op ".b r0h,r0l")
+        ((machine 16))
+        (.str op ".b r0h,r0l")
+        (+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 opc2))
+        ((.sym op -sem) QI R0h R0l)
+        ())
+    ; op.w #r1,r0
+    (dni (.sym op 16.w-r1-r0)
+        (.str op ".b r1,r0")
+        ((machine 16))
+        (.str op ".w r1,r0")
+        (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 opc2))
+        ((.sym op -sem) HI R1 R0)
+        ())
+  )
+)
+
+; dadc for m16c
+(decimal-subtraction16-insn dadc #xE #x6 )
+
+; dadc.size #imm,dst
+(binary-arith32-imm-dst-Prefixed QI QI .b 0 dadc X #x8 #x0 #xE dadc-sem)
+(binary-arith32-imm-dst-Prefixed HI HI .w 1 dadc X #x8 #x0 #xE dadc-sem)
+; dadc.BW src,dst
+(binary-arith32-src-dst-Prefixed QI QI .b 0 dadc X #x1 #x8 dadc-sem)
+(binary-arith32-src-dst-Prefixed HI HI .w 1 dadc X #x1 #x8 dadc-sem)
+
+(define-pmacro (dadd-sem mode src dst)
+  (sequence ((mode result))
+           (set result (subc mode dst src 0))
+           (set cbit (sub-cflag mode dst src 0))
+           (set-z-and-s result)
+           (set dst result))
+)
+
+; dadd for m16c
+(decimal-subtraction16-insn dadd #xC #x4)
+
+; dadd.size #imm,dst
+(binary-arith32-imm-dst-Prefixed QI QI .b 0 dadd X #x8 #x1 #xE dadd-sem)
+(binary-arith32-imm-dst-Prefixed HI HI .w 1 dadd X #x8 #x1 #xE dadd-sem)
+; dadd.BW src,dst
+(binary-arith32-src-dst-Prefixed QI QI .b 0 dadd X #x1 #x0 dadd-sem)
+(binary-arith32-src-dst-Prefixed HI HI .w 1 dadd X #x1 #x0 dadd-sem)
+
+;-------------------------------------------------------------;
+; addx - Add extend sign with no carry
+;-------------------------------------------------------------;
+
+(define-pmacro (addx-sem mode src dst)
+  (sequence ((SI source) (SI result))
+           (set source (zext SI (trunc QI src)))
+           (set result (add SI source dst))
+           (set obit (add-oflag SI source dst 0))
+           (set cbit (add-cflag SI source dst 0))
+           (set-z-and-s result)
+           (set dst result))
+)
+
+; addx #imm,dst
+(binary-arith32-imm-dst-defn QI SI "" 0 addx X #x8 #x1 #x1 addx-sem)
+; addx src,dst
+(binary-arith32-src-dst-defn QI SI "" 0 addx X #x1 #x2 addx-sem)
+
+;-------------------------------------------------------------
+; adjnz - Add/Sub and branch if not zero
+;-------------------------------------------------------------
+
+(define-pmacro (arith-jnz-sem mode src dst label)
+  (sequence ((mode result))
+           (set result (add mode src dst))
+           (set dst result)
+           (if (ne result 0)
+               (set pc label)))
+)
+
+; adjnz.size #imm4,dst,label
+(arith-jnz-imm4-dst adjnz s4 (f-0-4 #xF) (f-4-3 4) #xf #x1 arith-jnz-sem)
+
+;-------------------------------------------------------------
+; and - binary and
+;-------------------------------------------------------------
+
+(define-pmacro (and-sem mode src1 dst)
+  (sequence ((mode result))
+           (set result (and mode src1 dst))
+           (set-z-and-s result)
+           (set dst result))
+)
+
+; and.size:G #imm,dst (m16 #1 m32 #1)
+(binary-arith-imm-dst and G (f-0-4 7) (f-4-3 3) (f-8-4 2) #x8 #x3 #xF and-sem)
+; and.b:S #imm8,dst3 (m16 #2)
+(binary-arith16-b-S-imm8-dst3 and ".b" (f-0-4 9) (f-4-1 0) and-sem)
+; and.BW:G src,dst (m16 #3 m32 #3)
+(binary-arith-src-dst and G (f-0-4 #x9) (f-4-3 0) #x1 #xD and-sem)
+; and.B.S src2,r0l/r0h (m16 #4)
+(binary-arith16-b-S-src2 and (f-0-4 1) (f-4-1 0) and-sem)
+; and.BW:S #imm,dst2 (m32 #2)
+(binary-arith32-s-imm-dst QI .b 0 and #x1 #x6 and-sem)
+(binary-arith32-s-imm-dst HI .w 1 and #x1 #x6 and-sem)
+
+;-------------------------------------------------------------
+; band - bit and
+;-------------------------------------------------------------
+
+(define-pmacro (band-sem src)
+  (set cbit (and src cbit))
+)
+(bitsrc-insn band (f-0-4 7) (f-4-4 #xE) (f-8-4 4) #xD #x0 #x1 band-sem)
+
+;-------------------------------------------------------------
+; bclr - bit clear
+;-------------------------------------------------------------
+
+(define-pmacro (bclr-sem dst)
+  (set dst 0)
+)
+(bitdst-insn bclr (f-0-4 7) (f-4-4 #xE) (f-8-4 8) (f-0-2 1) (f-2-2 0) (f-4-1 0) #xD #x0 #x6 bclr-sem)
+
+;-------------------------------------------------------------
+; bitindex - bit index
+;-------------------------------------------------------------
+
+(define-pmacro (bitindex-sem mode dst)
+  (set BitIndex dst)
+)
+(unary-insn-defn 32 16-Unprefixed QI .b bitindex
+                    (+ (f-0-4 #xC) (f-7-1 0) dst32-16-Unprefixed-QI (f-10-2 #x2) (f-12-4 #xE))
+                    bitindex-sem)
+(unary-insn-defn 32 16-Unprefixed HI .w bitindex
+                    (+ (f-0-4 #xC) (f-7-1 1) dst32-16-Unprefixed-HI (f-10-2 #x2) (f-12-4 #xE))
+                    bitindex-sem)
+
+;-------------------------------------------------------------
+; bmCnd - bit move condition
+;-------------------------------------------------------------
+
+(define-pmacro (test-condition16 cond)
+  (case UQI cond
+       ((#x00) (trunc BI cbit))
+       ((#x01) (not (or cbit zbit)))
+       ((#x02) (trunc BI zbit))
+       ((#x03) (trunc BI sbit))
+       ((#x04) (or zbit (xor sbit obit)))
+       ((#x05) (trunc BI obit))
+       ((#x06) (xor sbit obit))
+       ((#xf8) (not cbit))
+       ((#xf9) (or cbit zbit))
+       ((#xfa) (not zbit))
+       ((#xfb) (not sbit))
+       ((#xfc) (not (or zbit (xor sbit obit))))
+       ((#xfd) (not obit))
+       ((#xfe) (not (xor sbit obit)))
+       (else   (const BI 0))
+  )
+)
+
+(define-pmacro (test-condition32 cond)
+  (case UQI cond
+       ((#x00) (not cbit))
+       ((#x01) (or cbit zbit))
+       ((#x02) (not zbit))
+       ((#x03) (not sbit))
+       ((#x04) (not obit))
+       ((#x05) (not (or zbit (xor sbit obit))))
+       ((#x06) (not (xor sbit obit)))
+       ((#x08) (trunc BI cbit))
+       ((#x09) (not (or cbit zbit)))
+       ((#x0a) (trunc BI zbit))
+       ((#x0b) (trunc BI sbit))
+       ((#x0c) (trunc BI obit))
+       ((#x0d) (or zbit (xor sbit obit)))
+       ((#x0e) (xor sbit obit))
+       (else   (const BI 0))
+  )
+)
+
+(define-pmacro (bitcond-sem mach op cond)
+  (if ((.sym test-condition mach) cond)
+      (set op 1)
+      (set op 0))
+)
+(bitcond-insn bm (f-0-4 7) (f-4-4 #xE) (f-8-4 2) #xD #x0 #x2 bitcond-sem)
+
+(dni bm16-c
+     "bm16 C"
+     ((machine 16))
+     "bm$cond16c c"
+     (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xD) cond16c)
+     (bitcond-sem 16 cbit cond16c)
+     ())
+
+(dni bm32-c
+     "bm32 C"
+     ((machine 32))
+     "bm$cond32 c"
+     (+ (f-0-4 #xD) (f-4-4 #x9) (f-8-1 0) (f-10-3 5) cond32)
+     (bitcond-sem 32 cbit cond32)
+     ())
+
+;-------------------------------------------------------------
+; bnand
+;-------------------------------------------------------------
+
+(define-pmacro (bnand-sem src)
+  (set cbit (and (inv src) cbit))
+)
+(bitsrc-insn bnand (f-0-4 7) (f-4-4 #xE) (f-8-4 5) #xD #x0 #x3 bnand-sem)
+
+;-------------------------------------------------------------
+; bnor
+;-------------------------------------------------------------
+
+(define-pmacro (bnor-sem src)
+  (set cbit (or (inv src) cbit))
+)
+(bitsrc-insn bnor (f-0-4 7) (f-4-4 #xE) (f-8-4 7) #xD #x0 #x6 bnor-sem)
+
+;-------------------------------------------------------------
+; bnot
+;-------------------------------------------------------------
+
+(define-pmacro (bnot-sem dst)
+  (set dst (inv dst))
+)
+(bitdst-insn bnot (f-0-4 7) (f-4-4 #xE) (f-8-4 #xA) (f-0-2 1) (f-2-2 1) (f-4-1 0) #xD #x0 #x3 bnot-sem)
+
+;-------------------------------------------------------------
+; bntst
+;-------------------------------------------------------------
+
+(define-pmacro (bntst-sem src)
+  (set cbit (inv src))
+  (set zbit (inv src))
+)
+(bitsrc-insn bntst (f-0-4 7) (f-4-4 #xE) (f-8-4 3) #xD #x0 #x0 bntst-sem)
+
+;-------------------------------------------------------------
+; bnxor
+;-------------------------------------------------------------
+
+(define-pmacro (bnxor-sem src)
+  (set cbit (xor (inv src) cbit))
+)
+(bitsrc-insn bnxor (f-0-4 7) (f-4-4 #xE) (f-8-4 #xD) #xD #x0 #x7 bnxor-sem)
+
+;-------------------------------------------------------------
+; bor
+;-------------------------------------------------------------
+
+(define-pmacro (bor-sem src)
+  (set cbit (or src cbit))
+)
+(bitsrc-insn bor (f-0-4 7) (f-4-4 #xE) (f-8-4 #x6) #xD #x0 #x4 bor-sem)
+
+;-------------------------------------------------------------
+; brk
+;-------------------------------------------------------------
+
+(dni brk16
+     "brk"
+     ((machine 16))
+     "brk"
+     (+ (f-0-4 #x0) (f-4-4 #x0))
+     (nop)
+     ())
+
+(dni brk32
+     "brk"
+     ((machine 32))
+     "brk"
+     (+ (f-0-4 #x0) (f-4-4 #x0))
+     (nop)
+     ())
+
+;-------------------------------------------------------------
+; brk2
+;-------------------------------------------------------------
+
+(dni brk232
+     "brk2"
+     ((machine 32))
+     "brk2"
+     (+ (f-0-4 #x0) (f-4-4 #x8))
+     (nop)
+     ())
+
+;-------------------------------------------------------------
+; bset
+;-------------------------------------------------------------
+
+(define-pmacro (bset-sem dst)
+  (set dst 1)
+)
+(bitdst-insn bset (f-0-4 7) (f-4-4 #xE) (f-8-4 9) (f-0-2 1) (f-2-2 0) (f-4-1 1) #xD #x0 #x7 bset-sem)
+
+;-------------------------------------------------------------
+; btst
+;-------------------------------------------------------------
+
+(define-pmacro (btst-sem dst)
+  (set zbit (inv dst))
+  (set cbit dst)
+)
+(bitdst16-defn btst (f-0-4 7) (f-4-4 #xE) (f-8-4 #xB) (f-0-2 1) (f-2-2 1) (f-4-1 1) btst-sem)
+
+(bit-insn-defn 32 btst G bit32-16-Unprefixed
+              (+ (f-0-4 #xD) bit32-16-Unprefixed (f-7-1 #x0) (f-10-3 #x0))
+              btst-sem)
+
+(dni btst.s "btst:s" ((machine 32))
+     "btst:s ${Bit3-S},${Dsp-8-u16}"
+     (+ (f-0-2 #x0) (f-4-3 #x5) Bit3-S Dsp-8-u16)
+     () ())
+
+;-------------------------------------------------------------
+; btstc
+;-------------------------------------------------------------
+
+(define-pmacro (btstc-sem dst)
+  (set zbit (inv dst))
+  (set cbit dst)
+  (set dst (const 0))
+)
+(bitdstnos-insn btstc (f-0-4 7) (f-4-4 #xE) (f-8-4 #x0) #xD #x0 #x4 btstc-sem)
+
+;-------------------------------------------------------------
+; btsts
+;-------------------------------------------------------------
+
+(define-pmacro (btsts-sem dst)
+  (set zbit (inv dst))
+  (set cbit dst)
+  (set dst (const 0))
+)
+(bitdstnos-insn btsts (f-0-4 7) (f-4-4 #xE) (f-8-4 #x1) #xD #x0 #x5 btsts-sem)
+
+;-------------------------------------------------------------
+; bxor
+;-------------------------------------------------------------
+
+(define-pmacro (bxor-sem src)
+  (set cbit (xor src cbit))
+)
+(bitsrc-insn bxor (f-0-4 7) (f-4-4 #xE) (f-8-4 #xC) #xD #x0 #x5 bxor-sem)
+
+;-------------------------------------------------------------
+; clip
+;-------------------------------------------------------------
+
+(define-pmacro (clip-sem mode imm1 imm2 dest)
+  (sequence ()
+           (if (gt mode imm1 dest)
+               (set dest imm1))
+           (if (lt mode imm2 dest)
+               (set dest imm2)))
+)
+
+(insn-imm1-imm2-dst-Prefixed clip #x8 #x3 #xE clip-sem)
+
+;-------------------------------------------------------------
+; cmp - binary compare
+;-------------------------------------------------------------
+
+(define-pmacro (cmp-sem mode src1 dst)
+  (sequence ((mode result))
+           (set result (sub mode dst src1))
+           (set obit (sub-oflag mode dst src1 0))
+           (set cbit (not (sub-cflag mode dst src1 0)))
+           (set-z-and-s result))
+)
+
+; cmp.L:G #imm32,dst (m32 #2)
+(binary-arith32-imm-dst-defn SI SI .l 0 cmp G #xA #x3 #x1 cmp-sem)
+; cmp.size:G #imm,dst (m16 #1 m32 #1)
+(binary-arith-imm-dst cmp G (f-0-4 7) (f-4-3 3) (f-8-4 8) #x9 #x2 #xE cmp-sem)
+; cmp.size:Q #imm4,dst (m16 #2 m32 #3)
+(binary-arith-imm4-dst cmp (f-0-4 #xD) (f-4-3 0) #x7 #x1 cmp-sem)
+; cmp.b:S #imm8,dst3 (m16 #3)
+(binary-arith16-b-S-imm8-dst3 cmp ".b" (f-0-4 #xE) (f-4-1 0) cmp-sem)
+; cmp.BW:G src,dst (m16 #4 m32 #5)
+(binary-arith-src-dst cmp G (f-0-4 #xC) (f-4-3 0) #x1 #x6 cmp-sem)
+; cmp.B.S src2,r0l/r0h (m16 #5)
+(binary-arith16-b-S-src2 cmp (f-0-4 3) (f-4-1 1) cmp-sem)
+; cmp.L:G src,dst (m32 #6)
+(binary-arith32-src-dst-defn SI SI .l 1 cmp G #x1 #x1 cmp-sem)
+; cmp.BW:S #imm,dst2 (m32 #4)
+(binary-arith32-s-imm-dst QI .b 0 cmp #x1 #x3 cmp-sem)
+(binary-arith32-s-imm-dst HI .w 1 cmp #x1 #x3 cmp-sem)
+; cmp.BW:s src2,r0[l] (m32 #7)
+(binary-arith32-S-src2 cmp QI .b 0 (f-0-2 1) (f-4-3 0) cmp-sem)
+(binary-arith32-S-src2 cmp HI .w 1 (f-0-2 1) (f-4-3 0) cmp-sem)
+
+;-------------------------------------------------------------
+; cmpx - binary compare extend sign
+;-------------------------------------------------------------
+
+(define-pmacro (cmpx-sem mode src1 dst)
+  (sequence ((mode result))
+           (set result (sub mode dst (ext mode src1)))
+           (set obit (sub-oflag mode dst (ext mode src1) 0))
+           (set cbit (sub-cflag mode dst (ext mode src1) 0))
+           (set-z-and-s result))
+)
+
+(binary-arith32-imm-dst-defn QI SI "" 0 cmpx X #xA #x1 #x1 cmpx-sem)
+
+;-------------------------------------------------------------
+; dec - decrement
+;-------------------------------------------------------------
+
+(define-pmacro (dec-sem mode dest)
+  (sequence ((mode result))
+           (set result (sub mode dest 1))
+           (set-z-and-s result)
+           (set dest result))
+)
+
+(dni dec16.b
+     "dec.b Dst16-3-S-8"
+     ((machine 16))
+     "dec.b ${Dst16-3-S-8}"
+     (+ (f-0-4 #xA) (f-4-1 #x1) Dst16-3-S-8)
+     (dec-sem QI Dst16-3-S-8)
+     ())
+
+(dni dec16.w
+     "dec.w Dst16An-S"
+     ((machine 16))
+     "dec.w ${Dst16An-S}"
+     (+ (f-0-4 #xF) (f-5-3 #x2) Dst16An-S)
+     (dec-sem HI Dst16An-S)
+     ())
+
+(unary32-defn QI .b 0 dec #xB #x0 #xE dec-sem)
+(unary32-defn HI .w 1 dec #xB #x0 #xE dec-sem)
+
+;-------------------------------------------------------------
+; div - divide
+; divu - divide unsigned
+; divx - divide extension
+;-------------------------------------------------------------
+
+; div.BW #imm
+(div-imm div  div  mod  SI  127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #x1) #xB #x0 #x2 #x3 div-sem)
+(div-imm divu udiv umod USI 255    0 65535      0 (f-0-4 #x7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #x0) #xB #x0 #x0 #x3 div-sem)
+(div-imm divx div  mod  SI  127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #x3) #xB #x2 #x2 #x3 div-sem)
+; div.BW src
+(div-src div  div  mod  SI  127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 3) (f-8-4 #xD) #x8 #x1 #xE div-sem)
+(div-src divu udiv umod USI 255    0 65535      0 (f-0-4 #x7) (f-4-3 3) (f-8-4 #xC) #x8 #x0 #xE div-sem)
+(div-src divx div  mod  SI  127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 3) (f-8-4 #x9) #x9 #x1 #xE div-sem)
+
+(div-src-defn 32 .l div dst32-24-Prefixed-SI
+             (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xA) (f-15-1 1) (f-18-2 #x1) (f-20-4 #xf) dst32-24-Prefixed-SI)
+             div mod SI R2R0 R2R0 NoRemainder #x7fffffff (neg SI #x80000000)
+             div-sem)
+(div-src-defn 32 .l divu dst32-24-Prefixed-SI
+             (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xA) (f-15-1 1) (f-18-2 #x0) (f-20-4 #xf) dst32-24-Prefixed-SI)
+             udiv umod USI R2R0 R2R0 NoRemainder #x80000000 0
+             div-sem)
+(div-src-defn 32 .l divx dst32-24-Prefixed-SI
+             (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xA) (f-15-1 1) (f-18-2 #x2) (f-20-4 #xf) dst32-24-Prefixed-SI)
+             div mod SI R2R0 R2R0 NoRemainder #x7fffffff (neg SI #x80000000)
+             div-sem)
+
+;-------------------------------------------------------------
+; dsbb - decimal subtraction with borrow
+; dsub - decimal subtraction
+;-------------------------------------------------------------
+
+(define-pmacro (dsbb-sem mode src dst)
+  (sequence ((mode result))
+           (set result (subc mode dst src (not cbit)))
+           (set cbit (sub-cflag mode dst src (not cbit)))
+           (set-z-and-s result)
+           (set dst result))
+)
+
+; dsbb for m16c
+(decimal-subtraction16-insn dsbb #xF #x7)
+
+; dsbb.size #imm,dst
+(binary-arith32-imm-dst-Prefixed QI QI .b 0 dsbb X #x9 #x0 #xE dsbb-sem)
+(binary-arith32-imm-dst-Prefixed HI HI .w 1 dsbb X #x9 #x0 #xE dsbb-sem)
+; dsbb.BW src,dst
+(binary-arith32-src-dst-Prefixed QI QI .b 0 dsbb X #x1 #xA dsbb-sem)
+(binary-arith32-src-dst-Prefixed HI HI .w 1 dsbb X #x1 #xA dsbb-sem)
+
+(define-pmacro (dsub-sem mode src dst)
+  (sequence ((mode result))
+           (set result (subc mode dst src 0))
+           (set cbit (sub-cflag mode dst src 0))
+           (set-z-and-s result)
+           (set dst result))
+)
+
+; dsub for m16c
+(decimal-subtraction16-insn dsub #xD #x5)
+
+; dsub.size #imm,dst
+(binary-arith32-imm-dst-Prefixed QI QI .b 0 dsub X #x9 #x1 #xE dsub-sem)
+(binary-arith32-imm-dst-Prefixed HI HI .w 1 dsub X #x9 #x1 #xE dsub-sem)
+; dsub.BW src,dst
+(binary-arith32-src-dst-Prefixed QI QI .b 0 dsub X #x1 #x2 dsub-sem)
+(binary-arith32-src-dst-Prefixed HI HI .w 1 dsub X #x1 #x2 dsub-sem)
+
+;-------------------------------------------------------------
+; sub - binary subtraction
+;-------------------------------------------------------------
+
+(define-pmacro (sub-sem mode src1 dst)
+  (sequence ((mode result))
+           (set result (sub mode dst src1))
+           (set obit (sub-oflag mode dst src1 0))
+           (set cbit (sub-cflag mode dst src1 0))
+           (set dst result)
+           (set-z-and-s result)))
+
+; sub.size:G #imm,dst (m16 #1 m32 #1)
+(binary-arith-imm-dst sub G (f-0-4 7) (f-4-3 3) (f-8-4 5) #x8 #x3 #xE sub-sem)
+; sub.b:S #imm8,dst3 (m16 #2)
+(binary-arith16-b-S-imm8-dst3 sub ".b" (f-0-4 8) (f-4-1 1) sub-sem)
+; sub.BW:G src,dst (m16 #3 m32 #4)
+(binary-arith-src-dst sub G (f-0-4 #xA) (f-4-3 4) #x1 #xA sub-sem)
+; sub.B.S src2,r0l/r0h (m16 #4)
+(binary-arith16-b-S-src2 sub (f-0-4 2) (f-4-1 1) sub-sem)
+; sub.L:G #imm32,dst (m32 #2)
+(binary-arith32-imm-dst-defn SI SI .l 0 sub G #x9 #x3 #x1 sub-sem)
+; sub.BW:S #imm,dst2 (m32 #3)
+(binary-arith32-s-imm-dst QI .b 0 sub #x0 #x7 sub-sem)
+(binary-arith32-s-imm-dst HI .w 1 sub #x0 #x7 sub-sem)
+; sub.L:G src,dst (m32 #5)
+(binary-arith32-src-dst-defn SI SI .l 1 sub G #x1 #x0 sub-sem)
+
+;-------------------------------------------------------------
+; enter - enter function
+; exitd - exit and deallocate stack frame
+;-------------------------------------------------------------
+
+(define-pmacro (enter16-sem mach amt)
+     (sequence ()
+               (set (reg h-sp) (sub (reg h-sp) 2))
+               (set (mem16 HI (reg h-sp)) (reg h-fb))
+               (set (reg h-fb) (reg h-sp))
+               (set (reg h-sp) (sub (reg h-sp) amt))))
+
+(define-pmacro (exit16-sem mach)
+     (sequence ((SI newpc))
+               (set (reg h-sp) (reg h-fb))
+               (set (reg h-fb) (mem16 HI (reg h-sp)))
+               (set (reg h-sp) (add (reg h-sp) 2))
+               (set newpc (mem16 HI (reg h-sp)))
+               (set (reg h-sp) (add (reg h-sp) 2))
+               (set newpc (or newpc (sll (mem16 QI (reg h-sp)) (const 16))))
+               (set (reg h-sp) (add (reg h-sp) 1))
+              (set pc newpc)))
+
+(define-pmacro (enter32-sem mach amt)
+     (sequence ()
+               (set (reg h-sp) (sub (reg h-sp) 4))
+               (set (mem32 SI (reg h-sp)) (reg h-fb))
+               (set (reg h-fb) (reg h-sp))
+               (set (reg h-sp) (sub (reg h-sp) amt))))
+
+(define-pmacro (exit32-sem mach)
+     (sequence ((SI newpc))
+               (set (reg h-sp) (reg h-fb))
+               (set (reg h-fb) (mem32 SI (reg h-sp)))
+               (set (reg h-sp) (add (reg h-sp) 4))
+               (set newpc (mem32 SI (reg h-sp)))
+               (set (reg h-sp) (add (reg h-sp) 4))
+              (set pc newpc)))
+
+(dni enter16 "enter #Imm-16-QI" ((machine 16))
+     ("enter #${Dsp-16-u8}")
+     (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 2) Dsp-16-u8)
+     (enter16-sem 16 Dsp-16-u8)
+     ())
+
+(dni exitd16 "exitd" ((machine 16))
+     ("exitd")
+     (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 2))
+     (exit16-sem 16)
+     ())
+
+(dni enter32 "enter #Imm-8-QI" ((machine 32))
+     ("enter #${Dsp-8-u8}")
+     (+ (f-0-4 #xE) (f-4-4 #xC) Dsp-8-u8)
+     (enter32-sem 32 Dsp-8-u8)
+     ())
+
+(dni exitd32 "exitd" ((machine 32))
+     ("exitd")
+     (+ (f-0-4 #xF) (f-4-4 #xC))
+     (exit32-sem 32)
+     ())
+
+;-------------------------------------------------------------
+; fclr - flag register clear
+; fset - flag register set
+;-------------------------------------------------------------
+
+(define-pmacro (set-flags-sem flag)
+  (sequence ((SI tmp))
+           (case DFLT flag
+                 ((#x0) (set cbit 1))
+                 ((#x1) (set dbit 1))
+                 ((#x2) (set zbit 1))
+                 ((#x3) (set sbit 1))
+                 ((#x4) (set bbit 1))
+                 ((#x5) (set obit 1))
+                 ((#x6) (set ibit 1))
+                 ((#x7) (set ubit 1)))
+           )
+  )
+
+(define-pmacro (clear-flags-sem flag)
+  (sequence ((SI tmp))
+           (case DFLT flag
+                 ((#x0) (set cbit 0))
+                 ((#x1) (set dbit 0))
+                 ((#x2) (set zbit 0))
+                 ((#x3) (set sbit 0))
+                 ((#x4) (set bbit 0))
+                 ((#x5) (set obit 0))
+                 ((#x6) (set ibit 0))
+                 ((#x7) (set ubit 0)))
+           )
+  )
+
+(dni fclr16 "fclr flag" ((machine 16))
+     ("fclr ${flags16}")
+     (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) flags16 (f-12-4 5))
+     (clear-flags-sem flags16)
+     ())
+
+(dni fset16 "fset flag" ((machine 16))
+     ("fset ${flags16}")
+     (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) flags16 (f-12-4 4))
+     (set-flags-sem flags16)
+     ())
+
+(dni fclr "fclr" ((machine 32))
+     ("fclr ${flags32}")
+     (+ (f-0-4 #xD) (f-4-4 3) (f-8-4 #xE) (f-12-1 1) flags32)
+     (clear-flags-sem flags32)
+     ())
+
+(dni fset "fset" ((machine 32))
+     ("fset ${flags32}")
+     (+ (f-0-4 #xD) (f-4-4 1) (f-8-4 #xE) (f-12-1 1) flags32)
+     (set-flags-sem flags32)
+     ())
+
+;-------------------------------------------------------------
+; inc - increment
+;-------------------------------------------------------------
+
+(define-pmacro (inc-sem mode dest)
+  (sequence ((mode result))
+           (set result (add mode dest 1))
+           (set-z-and-s result)
+           (set dest result))
+)
+
+(dni inc16.b
+     "inc.b Dst16-3-S-8"
+     ((machine 16))
+     "inc.b ${Dst16-3-S-8}"
+     (+ (f-0-4 #xA) (f-4-1 #x0) Dst16-3-S-8)
+     (inc-sem QI Dst16-3-S-8)
+     ())
+
+(dni inc16.w
+     "inc.w Dst16An-S"
+     ((machine 16))
+     "inc.w ${Dst16An-S}"
+     (+ (f-0-4 #xB) (f-5-3 #x2) Dst16An-S)
+     (inc-sem HI Dst16An-S)
+     ())
+
+(unary32-defn QI .b 0 inc #xA #x0 #xE inc-sem)
+(unary32-defn HI .w 1 inc #xA #x0 #xE inc-sem)
+
+;-------------------------------------------------------------
+; freit - fast return from interrupt (m32)
+; int - interrupt
+; into - interrupt on overflow
+;-------------------------------------------------------------
+
+; ??? semantics
+(dni freit32 "FREIT" ((machine 32))
+     ("freit")
+     (+ (f-0-4 9) (f-4-4 #xF))
+     (nop)
+     ())
+
+(dni int16 "int Dsp-10-u6" ((machine 16))
+     ("int #${Dsp-10-u6}")
+     (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-2 3) Dsp-10-u6)
+     (c-call VOID "do_int" pc Dsp-10-u6)
+     ())
+
+(dni into16 "into" ((machine 16))
+     ("into")
+     (+ (f-0-4 #xF) (f-4-4 6))
+     (nop)
+     ())
+
+(dni int32 "int Dsp-8-u6" ((machine 32))
+     ("int #${Dsp-8-u6}")
+     (+ (f-0-4 #xB) (f-4-4 #xE) Dsp-8-u6 (f-14-2 0))
+     (c-call VOID "do_int" pc Dsp-8-u6)
+     ())
+
+(dni into32 "into" ((machine 32))
+     ("into")
+     (+ (f-0-4 #xB) (f-4-4 #xF))
+     (nop)
+     ())
+
+;-------------------------------------------------------------
+; index (m32c)
+;-------------------------------------------------------------
+
+; TODO add support to insns allowing index
+(define-pmacro (indexb-sem mode d) (set SrcIndex d) (set DstIndex d))
+(define-pmacro (indexbd-sem mode d) (set SrcIndex (const 0)) (set DstIndex d))
+(define-pmacro (indexbs-sem mode d) (set SrcIndex d) (set DstIndex (const 0)))
+(define-pmacro (indexw-sem mode d)
+  (set SrcIndex (sll d (const 2))) (set DstIndex (sll d (const 2))))
+(define-pmacro (indexwd-sem mode d)
+  (set SrcIndex (const 0)) (set DstIndex (sll d (const 2))))
+(define-pmacro (indexws-sem mode d)
+  (set SrcIndex (sll d (const 2))) (set DstIndex (const 0)))
+(define-pmacro (indexl-sem mode d)
+  (set SrcIndex d) (set DstIndex (sll d (const 2))))
+(define-pmacro (indexld-sem mode d)
+  (set SrcIndex (const 0)) (set DstIndex (sll d (const 2))))
+(define-pmacro (indexls-sem mode d)
+  (set SrcIndex (sll d (const 2))) (set DstIndex (const 0)))
+
+; Note that "wbit" not where the size bit goes here, hence, it's
+; always 0 in these calls but op2 differs instead.
+
+; indexb src (index byte)
+(unary32-defn QI .b 0 indexb #x8 0 #x3 indexb-sem)
+(unary32-defn HI .w 0 indexb #x8 1 #x3 indexb-sem)
+; indexbd src (index byte dest)
+(unary32-defn QI .b 0 indexbd #xA 0 3 indexbd-sem)
+(unary32-defn HI .w 0 indexbd #xA 1 3 indexbd-sem)
+; indexbs src (index byte src)
+(unary32-defn QI .b 0 indexbs #xC 0 3 indexbs-sem)
+(unary32-defn HI .w 0 indexbs #xC 1 3 indexbs-sem)
+; indexl src (index long)
+(unary32-defn QI .b 0 indexl 9 2 3 indexl-sem)
+(unary32-defn HI .w 0 indexl 9 3 3 indexl-sem)
+; indexld src (index long dest)
+(unary32-defn QI .b 0 indexld #xB 2 3 indexld-sem)
+(unary32-defn HI .w 0 indexld #xB 3 3 indexld-sem)
+; indexls src (index long src)
+(unary32-defn QI .b 0 indexls 9 0 3 indexls-sem)
+(unary32-defn HI .w 0 indexls 9 1 3 indexls-sem)
+; indexw src (index word)
+(unary32-defn QI .b 0 indexw 8 2 3 indexw-sem)
+(unary32-defn HI .w 0 indexw 8 3 3 indexw-sem)
+; indexwd src (index word dest)
+(unary32-defn QI .b 0 indexwd #xA 2 3 indexwd-sem)
+(unary32-defn HI .w 0 indexwd #xA 3 3 indexwd-sem)
+; indexws (index word src)
+(unary32-defn QI .b 0 indexws #xC 2 3 indexws-sem)
+(unary32-defn HI .w 0 indexws #xC 3 3 indexws-sem)
+
+;-------------------------------------------------------------
+; jcc - jump on condition
+;-------------------------------------------------------------
+
+(define-pmacro (jcnd32-sem cnd label)
+  (sequence ()
+           (case DFLT cnd
+                 ((#x00) (if (not cbit) (set pc label))) ;ltu nc
+                 ((#x01) (if (not (and cbit (not zbit))) (set pc label))) ;leu
+                 ((#x02) (if (not zbit) (set pc label))) ;ne nz
+                 ((#x03) (if (not sbit) (set pc label))) ;pz
+                 ((#x04) (if (not obit) (set pc label))) ;no
+                 ((#x05) (if (not (or zbit (xor sbit obit))) (set pc label))) ;gt
+                 ((#x06) (if (not (xor sbit obit)) (set pc label))) ;ge
+                 ((#x08) (if (trunc BI cbit) (set pc label))) ;geu c
+                 ((#x09) (if (and cbit (not zbit)) (set pc label))) ;gtu
+                 ((#x0a) (if (trunc BI zbit) (set pc label))) ;eq z
+                 ((#x0b) (if (trunc BI sbit) (set pc label))) ;n
+                 ((#x0c) (if (trunc BI obit) (set pc label))) ;o
+                 ((#x0d) (if (or zbit (xor sbit obit)) (set pc label))) ;le
+                 ((#x0e) (if (xor sbit obit) (set pc label))) ;lt
+                 )
+       )
+  )
+
+(define-pmacro (jcnd16-sem cnd label)
+  (sequence ()
+           (case DFLT cnd
+                 ((#x00) (if (trunc BI cbit) (set pc label))) ;geu c
+                 ((#x01) (if (and cbit (not zbit)) (set pc label))) ;gtu
+                 ((#x02) (if (trunc BI zbit) (set pc label))) ;eq z
+                 ((#x03) (if (trunc BI sbit) (set pc label))) ;n
+                 ((#x04) (if (not cbit) (set pc label))) ;ltu nc
+                 ((#x05) (if (not (and cbit (not zbit))) (set pc label))) ;leu
+                 ((#x06) (if (not zbit) (set pc label))) ;ne nz
+                 ((#x07) (if (not sbit) (set pc label))) ;pz
+                 ((#x08) (if (or zbit (xor sbit obit)) (set pc label))) ;le
+                 ((#x09) (if (trunc BI obit) (set pc label))) ;o
+                 ((#x0a) (if (not (xor sbit obit)) (set pc label))) ;ge
+                 ((#x0c) (if (not (or zbit (xor sbit obit))) (set pc label))) ;gt
+                 ((#x0d) (if (not obit) (set pc label))) ;no
+                 ((#x0e) (if (xor sbit obit) (set pc label))) ;lt
+                 )
+       )
+  )
+
+(dni jcnd16-5
+     "jCnd label"
+     (RL_JUMP RELAXABLE (machine 16))
+     "j$cond16j5 ${Lab-8-8}"
+     (+ (f-0-4 #x6) (f-4-1 1) cond16j5 Lab-8-8)
+     (jcnd16-sem cond16j5 Lab-8-8)
+     ()
+)
+
+(dni jcnd16
+     "jCnd label"
+     (RL_JUMP RELAXABLE (machine 16))
+     "j$cond16j ${Lab-16-8}"
+     (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xC) cond16j Lab-16-8)
+     (jcnd16-sem cond16j Lab-16-8)
+     ()
+)
+
+(dni jcnd32
+     "jCnd label"
+     (RL_JUMP RELAXABLE (machine 32))
+     "j$cond32j ${Lab-8-8}"
+     (+ (f-0-1 1) (f-4-3 5) cond32j Lab-8-8)
+     (jcnd32-sem cond32j Lab-8-8)
+     ()
+)
+
+;-------------------------------------------------------------
+; jmp - jump
+;-------------------------------------------------------------
+
+; jmp.s label3 (m16 #1)
+(dni jmp16.s "jmp.s Lab-5-3" (RL_JUMP RELAXABLE (machine 16))
+     ("jmp.s ${Lab-5-3}")
+     (+ (f-0-4 6) (f-4-1 0) Lab-5-3)
+     (sequence () (set pc Lab-5-3))
+     ())
+; jmp.b label8 (m16 #2)
+(dni jmp16.b "jmp.b Lab-8-8" (RL_JUMP RELAXABLE (machine 16))
+     ("jmp.b ${Lab-8-8}")
+     (+ (f-0-4 #xF) (f-4-4 #xE) Lab-8-8)
+     (sequence () (set pc Lab-8-8))
+     ())
+; jmp.w label16 (m16 #3)
+(dni jmp16.w "jmp.w Lab-8-16" (RL_JUMP RELAXABLE (machine 16))
+     ("jmp.w ${Lab-8-16}")
+     (+ (f-0-4 #xF) (f-4-4 4) Lab-8-16)
+     (sequence () (set pc Lab-8-16))
+     ())
+; jmp.a label24 (m16 #4)
+(dni jmp16.a "jmp.a Lab-8-24" (RL_JUMP RELAXABLE (machine 16))
+     ("jmp.a ${Lab-8-24}")
+     (+ (f-0-4 #xF) (f-4-4 #xC) Lab-8-24)
+     (sequence () (set pc Lab-8-24))
+     ())
+
+(define-pmacro (jmp16-sem mode dst)
+  (set pc (and dst #xfffff))
+)
+(define-pmacro (jmp32-sem mode dst)
+  (set pc dst)
+)
+; jmpi.w dst (m16 #1 m32 #2)
+(unary-insn-defn 16 16 HI .w jmpi (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 2) dst16-16-HI) jmp16-sem)
+(unary-insn-defn 32 16-Unprefixed HI .w jmpi (+ (f-0-4 #xC) (f-7-1 1) dst32-16-Unprefixed-HI (f-10-2 #x0) (f-12-4 #xF)) jmp32-sem)
+; jmpi.a dst (m16 #2 m32 #2)
+(unary-insn-defn 16 16 SI .a jmpi (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 0) dst16-16-SI) jmp16-sem)
+(unary-insn-defn 32 16-Unprefixed SI .a jmpi (+ (f-0-4 #x8) (f-7-1 0) dst32-16-Unprefixed-SI (f-10-2 #x0) (f-12-4 1)) jmp32-sem)
+; jmps imm8 (m16 #1)
+(dni jmps16 "jmps Imm-8-QI" ((machine 16))
+     ("jmps #${Imm-8-QI}")
+     (+ (f-0-4 #xE) (f-4-4 #xE) Imm-8-QI)
+     (sequence () (set pc Imm-8-QI))
+     ())
+; jmp.s label3 (m32 #1)
+(dni jmp32.s
+     "jmp.s label"
+     (RL_JUMP RELAXABLE (machine 32))
+     "jmp.s ${Lab32-jmp-s}"
+     (+ (f-0-2 1) (f-4-3 5) Lab32-jmp-s)
+     (set pc Lab32-jmp-s)
+     ()
+)
+; jmp.b label8 (m32 #2)
+(dni jmp32.b "jmp.b Lab-8-8" (RL_JUMP RELAXABLE (machine 32))
+     ("jmp.b ${Lab-8-8}")
+     (+ (f-0-4 #xB) (f-4-4 #xB) Lab-8-8)
+     (set pc Lab-8-8)
+     ())
+; jmp.w label16 (m32 #3)
+(dni jmp32.w "jmp.w Lab-8-16" (RL_JUMP RELAXABLE (machine 32))
+     ("jmp.w ${Lab-8-16}")
+     (+ (f-0-4 #xC) (f-4-4 #xE) Lab-8-16)
+     (set pc Lab-8-16)
+     ())
+; jmp.a label24 (m32 #4)
+(dni jmp32.a "jmp.a Lab-8-24" (RL_JUMP RELAXABLE (machine 32))
+     ("jmp.a ${Lab-8-24}")
+     (+ (f-0-4 #xC) (f-4-4 #xC) Lab-8-24)
+     (set pc Lab-8-24)
+     ())
+; jmp.s imm8 (m32 #1)
+(dni jmps32 "jmps Imm-8-QI" (RL_JUMP (machine 32))
+     ("jmps #${Imm-8-QI}")
+     (+ (f-0-4 #xD) (f-4-4 #xC) Imm-8-QI)
+     (set pc Imm-8-QI)
+     ())
+
+;-------------------------------------------------------------
+; jsr jump subroutine
+;-------------------------------------------------------------
+
+(define-pmacro (jsr16-sem length dst)
+  (sequence ((SI tpc))
+           (set tpc (add pc length))
+           (set (reg h-sp) (sub (reg h-sp) 2))
+           (set (mem16 HI (reg h-sp)) (srl (and tpc #xffff00) 8))
+           (set (reg h-sp) (sub (reg h-sp) 1))
+           (set (mem16 QI (reg h-sp)) (and tpc #xff))
+           (set pc dst)
+           )
+)
+(define-pmacro (jsr32-sem length dst)
+  (sequence ((SI tpc))
+           (set tpc (add pc length))
+           (set (reg h-sp) (sub (reg h-sp) 2))
+           (set (mem32 HI (reg h-sp)) (srl (and tpc #xffff0000) 16))
+           (set (reg h-sp) (sub (reg h-sp) 2))
+           (set (mem32 HI (reg h-sp)) (and tpc #xffff))
+           (set pc dst)
+           )
+)
+
+; jsr.w label16 (m16 #1)
+(dni jsr16.w "jsr.w Lab-8-16" (RL_JUMP RELAXABLE (machine 16))
+     ("jsr.w ${Lab-8-16}")
+     (+ (f-0-4 #xF) (f-4-4 5) Lab-8-16)
+     (jsr16-sem 3 Lab-8-16)
+     ())
+; jsr.a label24 (m16 #2)
+(dni jsr16.a "jsr.a Lab-8-24" (RL_JUMP RELAXABLE (machine 16))
+     ("jsr.a ${Lab-8-24}")
+     (+ (f-0-4 #xF) (f-4-4 #xD) Lab-8-24)
+     (jsr16-sem 4 Lab-8-24)
+     ())
+(define-pmacro (jsri-defn mode op16 op16-1 op16-2 op16-3        op16-sem 
+                              op32 op32-1 op32-2 op32-3 op32-4 op32-sem len)
+  (begin
+    (dni (.sym jsri16 mode - op16)
+        (.str "jsri." mode " " op16)
+        (RL_1ADDR (machine 16))
+        (.str "jsri." mode " ${" op16 "}")
+        (+ op16-1 op16-2 op16-3 op16)
+        (op16-sem len op16)
+        ())
+    (dni (.sym jsri32 mode - op32)
+        (.str "jsri." mode " " op32)
+        (RL_1ADDR (machine 32))
+        (.str "jsri." mode " ${" op32 "}")
+        (+ op32-1 op32-2 op32-3 op32-4 op32)
+        (op32-sem len op32)
+        ())
+    )
+  )
+; jsri.w dst (m16 #1 m32 #1))
+(jsri-defn w dst16-16-20ar-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem 
+             dst32-16-24-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 4)
+(jsri-defn w dst16-16-16sa-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem 
+             dst32-16-16sa-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 4)
+(jsri-defn w dst16-16-8-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem 
+             dst32-16-8-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 3)
+(jsri-defn w dst16-basic-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem 
+             dst32-basic-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 2)
+
+; jsri.a (m16 #2 m32 #2)
+(jsri-defn a dst16-16-20ar-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem 
+             dst32-16-24-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 4)
+(jsri-defn a dst16-16-8-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem 
+             dst32-16-8-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 3)
+(jsri-defn a dst16-16-16sa-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem 
+             dst32-16-16sa-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 4)
+(jsri-defn a dst16-basic-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem 
+             dst32-basic-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 2)
+
+(dni jsri32.a "jsr.w dst32-16-24-Unprefixed-HI" (RL_1ADDR (machine 32))
+     ("jsri.a ${dst32-16-24-Unprefixed-SI}")
+     (+ (f-0-4 #x9) (f-7-1 0) dst32-16-24-Unprefixed-SI (f-10-2 #x0) (f-12-4 #x1))
+     (jsr32-sem 6 dst32-16-24-Unprefixed-SI)
+     ())
+; jsr.w label16 (m32 #1)
+(dni jsr32.w "jsr.w label" (RL_JUMP RELAXABLE (machine 32))
+     ("jsr.w ${Lab-8-16}")
+     (+ (f-0-4 #xC) (f-4-4 #xF) Lab-8-16)
+     (jsr32-sem 3 Lab-8-16)
+     ())
+; jsr.a label16 (m32 #2)
+(dni jsr32.a "jsr.a label" (RL_JUMP (machine 32))
+     ("jsr.a ${Lab-8-24}")
+     (+ (f-0-4 #xC) (f-4-4 #xD) Lab-8-24)
+     (jsr32-sem 4 Lab-8-24)
+     ())
+; jsrs imm8 (m16 #1)
+(dni jsrs16 "jsrs Imm-8-QI" ((machine 16))
+     ("jsrs #${Imm-8-QI}")
+     (+ (f-0-4 #xE) (f-4-4 #xF) Imm-8-QI)
+     (jsr16-sem 2 Imm-8-QI)
+     ())
+; jsrs imm8 (m32 #1)
+(dni jsrs "jsrs #Imm-8-QI" ((machine 32))
+     ("jsrs #${Imm-8-QI}")
+     (+ (f-0-4 #xD) (f-4-4 #xD) Imm-8-QI)
+     (jsr32-sem 2 Imm-8-QI)
+     ())
+
+;-------------------------------------------------------------
+; ldc - load control register
+; stc - store control register
+;-------------------------------------------------------------
+
+(define-pmacro (ldc32-cr1-sem src dst)
+  (sequence ()
+           (case DFLT dst
+                 ((#x0) (set (reg h-dct0) src))
+                 ((#x1) (set (reg h-dct1) src))
+                 ((#x2) (sequence ((HI tflag))
+                                  (set tflag src)
+                                  (if (and tflag #x1) (set cbit 1)) 
+                                  (if (and tflag #x2) (set dbit 1)) 
+                                  (if (and tflag #x4) (set zbit 1)) 
+                                  (if (and tflag #x8) (set sbit 1)) 
+                                  (if (and tflag #x10) (set bbit 1)) 
+                                  (if (and tflag #x20) (set obit 1)) 
+                                  (if (and tflag #x40) (set ibit 1)) 
+                                  (if (and tflag #x80) (set ubit 1))))
+                 ((#x3) (set (reg h-svf) src))
+                 ((#x4) (set (reg h-drc0) src))
+                 ((#x5) (set (reg h-drc1) src))
+                 ((#x6) (set (reg h-dmd0) src))
+                 ((#x7) (set (reg h-dmd1) src))
+           )
+  )
+)
+(define-pmacro (ldc32-cr2-sem src dst)
+  (sequence ()
+           (case DFLT dst
+                 ((#x0) (set (reg h-intb) src))
+                 ((#x1) (set (reg h-sp) src))
+                 ((#x2) (set (reg h-sb) src))
+                 ((#x3) (set (reg h-fb) src))
+                 ((#x4) (set (reg h-svp) src))
+                 ((#x5) (set (reg h-vct) src))
+                 ((#x7) (set (reg h-isp) src))
+           )
+  )
+)
+(define-pmacro (ldc32-cr3-sem src dst)
+  (sequence ()
+           (case DFLT dst
+                 ((#x2) (set (reg h-dma0) src))
+                 ((#x3) (set (reg h-dma1) src))
+                 ((#x4) (set (reg h-dra0) src))
+                 ((#x5) (set (reg h-dra1) src))
+                 ((#x6) (set (reg h-dsa0) src))
+                 ((#x7) (set (reg h-dsa1) src))
+           )
+  )
+)
+(define-pmacro (ldc16-sem src dst)
+  (sequence ()
+           (case DFLT dst
+                 ((#x1) (set (reg h-intb) src))
+                 ((#x2) (set (reg h-intb) (or (reg h-intb) (sll src (const 16)))))
+                 ((#x3) (sequence ((HI tflag))
+                                  (set tflag src)
+                                  (if (and tflag #x1) (set cbit 1)) 
+                                  (if (and tflag #x2) (set dbit 1)) 
+                                  (if (and tflag #x4) (set zbit 1)) 
+                                  (if (and tflag #x8) (set sbit 1)) 
+                                  (if (and tflag #x10) (set bbit 1)) 
+                                  (if (and tflag #x20) (set obit 1)) 
+                                  (if (and tflag #x40) (set ibit 1)) 
+                                  (if (and tflag #x80) (set ubit 1))))
+                 ((#x4) (set (reg h-isp) src))
+                 ((#x5) (set (reg h-sp) src))
+                 ((#x6) (set (reg h-sb) src))
+                 ((#x7) (set (reg h-fb) src))
+           )
+  )
+)
+
+(define-pmacro (stc32-cr1-sem src dst)
+  (sequence ()
+           (case DFLT src
+                 ((#x0) (set dst (reg h-dct0)))
+                 ((#x1) (set dst (reg h-dct1)))
+                 ((#x2) (sequence ((HI tflag))
+                                  (set tflag 0)
+                                  (if (eq cbit 1) (set tflag (or tflag #x1)))
+                                  (if (eq dbit 1) (set tflag (or tflag #x2)))
+                                  (if (eq zbit 1) (set tflag (or tflag #x4)))
+                                  (if (eq sbit 1) (set tflag (or tflag #x8)))
+                                  (if (eq bbit 1) (set tflag (or tflag #x10)))
+                                  (if (eq obit 1) (set tflag (or tflag #x20)))
+                                  (if (eq ibit 1) (set tflag (or tflag #x40)))
+                                  (if (eq ubit 1) (set tflag (or tflag #x80)))
+                                  (set dst tflag)))
+                 ((#x3) (set dst (reg h-svf)))
+                 ((#x4) (set dst (reg h-drc0)))
+                 ((#x5) (set dst (reg h-drc1)))
+                 ((#x6) (set dst (reg h-dmd0)))
+                 ((#x7) (set dst (reg h-dmd1)))
+           )
+  )
+)
+(define-pmacro (stc32-cr2-sem src dst)
+  (sequence ()
+           (case DFLT src
+                 ((#x0) (set dst (reg h-intb)))
+                 ((#x1) (set dst (reg h-sp)))
+                 ((#x2) (set dst (reg h-sb)))
+                 ((#x3) (set dst (reg h-fb)))
+                 ((#x4) (set dst (reg h-svp)))
+                 ((#x5) (set dst (reg h-vct)))
+                 ((#x7) (set dst (reg h-isp)))
+           )
+  )
+)
+(define-pmacro (stc32-cr3-sem src dst)
+  (sequence ()
+           (case DFLT src
+                 ((#x2) (set dst (reg h-dma0)))
+                 ((#x3) (set dst (reg h-dma1)))
+                 ((#x4) (set dst (reg h-dra0)))
+                 ((#x5) (set dst (reg h-dra1)))
+                 ((#x6) (set dst (reg h-dsa0)))
+                 ((#x7) (set dst (reg h-dsa1)))
+           )
+  )
+)
+(define-pmacro (stc16-sem src dst)
+  (sequence ()
+           (case DFLT src
+                 ((#x1) (set dst (and (reg h-intb) (const #xffff))))
+                 ((#x2) (set dst (srl (reg h-intb) (const 16))))
+                 ((#x3) (sequence ((HI tflag))
+                                  (set tflag 0)
+                                  (if (eq cbit 1) (set tflag (or tflag #x1)))
+                                  (if (eq dbit 1) (set tflag (or tflag #x2)))
+                                  (if (eq zbit 1) (set tflag (or tflag #x4)))
+                                  (if (eq sbit 1) (set tflag (or tflag #x8)))
+                                  (if (eq bbit 1) (set tflag (or tflag #x10)))
+                                  (if (eq obit 1) (set tflag (or tflag #x20)))
+                                  (if (eq ibit 1) (set tflag (or tflag #x40)))
+                                  (if (eq ubit 1) (set tflag (or tflag #x80)))
+                                  (set dst tflag)))
+                 ((#x4) (set dst (reg h-isp)))
+                 ((#x5) (set dst (reg h-sp)))
+                 ((#x6) (set dst (reg h-sb)))
+                 ((#x7) (set dst (reg h-fb)))
+           )
+  )
+)
+
+(dni ldc16.imm16 "ldc #imm,dst" ((machine 16))
+     ("ldc #${Imm-16-HI},${cr16}")
+     (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) (f-12-4 0) cr16 Imm-16-HI)
+     (ldc16-sem Imm-16-HI cr16)
+     ())
+ 
+(dni ldc16.dst "ldc src,dest" ((machine 16))
+     ("ldc ${dst16-16-HI},${cr16}")
+     (+ (f-0-4 7) (f-4-4 #xA) (f-8-1 1) cr16 dst16-16-HI)
+     (ldc16-sem dst16-16-HI cr16)
+     ())
+; ldc src,dest (m32c #4)
+(dni ldc32.src-cr1 "ldc src,dst" ((machine 32))
+     ("ldc ${dst32-24-Prefixed-HI},${cr1-Prefixed-32}")
+     (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-HI  (f-15-1 1) (f-18-2 0) (f-20-1 1) cr1-Prefixed-32)
+     (ldc32-cr1-sem dst32-24-Prefixed-HI cr1-Prefixed-32)
+     ())
+; ldc src,dest (m32c #5)
+(dni ldc32.src-cr2 "ldc src,dest" ((machine 32))
+     ("ldc ${dst32-16-Unprefixed-SI},${cr2-32}")
+     (+ (f-0-4 #xD) dst32-16-Unprefixed-SI (f-7-1 1) (f-10-2 0) (f-12-1 0) cr2-32)
+     (ldc32-cr2-sem dst32-16-Unprefixed-SI cr2-32)
+     ())
+; ldc src,dest (m32c #6)
+(dni ldc32.src-cr3 "ldc src,dst" ((machine 32))
+     ("ldc ${dst32-24-Prefixed-SI},${cr3-Prefixed-32}")
+     (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-SI (f-15-1 1) (f-18-2 0) (f-20-1 0) cr3-Prefixed-32)
+     (ldc32-cr3-sem dst32-24-Prefixed-SI cr3-Prefixed-32)
+     ())
+; ldc src,dest (m32c #1)
+(dni ldc32.imm16-cr1 "ldc #imm,dst" ((machine 32))
+     ("ldc #${Imm-16-HI},${cr1-Unprefixed-32}")
+     (+ (f-0-4 #xD) (f-4-4 5) (f-8-4 #xA) (f-12-1 1) cr1-Unprefixed-32 Imm-16-HI)
+     (ldc32-cr1-sem Imm-16-HI cr1-Unprefixed-32)
+     ())
+; ldc src,dest (m32c #2)
+(dni ldc32.imm16-cr2 "ldc #imm,dst" ((machine 32))
+     ("ldc #${Dsp-16-u24},${cr2-32}")
+     (+ (f-0-4 #xD) (f-4-4 5) (f-8-4 2) (f-12-1 1)  cr2-32 Dsp-16-u24)
+     (ldc32-cr2-sem Dsp-16-u24 cr2-32)
+     ())
+; ldc src,dest (m32c #3) 
+(dni ldc32.imm16-cr3 "ldc #imm,dst" ((machine 32))
+     ("ldc #${Dsp-16-u24},${cr3-Unprefixed-32}")
+     (+ (f-0-4 #xD) (f-4-4 5) (f-8-4 6) (f-12-1 1) cr3-Unprefixed-32 Dsp-16-u24)
+     (ldc32-cr3-sem Dsp-16-u24 cr3-Unprefixed-32)
+     ())
+ 
+(dni stc16.src "stc src,dest" ((machine 16))
+     ("stc ${cr16},${dst16-16-HI}")
+     (+ (f-0-4 7) (f-4-4 #xB) (f-8-1 1) cr16 dst16-16-HI)
+     (stc16-sem cr16 dst16-16-HI )
+     ())
+
+(dni stc16.pc "stc pc,dest" ((machine 16))
+     ("stc pc,${dst16-16-HI}")
+     (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xC) dst16-16-HI)
+     (sequence () (set dst16-16-HI (reg h-pc)))
+     ())
+
+(dni stc32.src-cr1 "stc src,dst" ((machine 32))
+     ("stc ${cr1-Prefixed-32},${dst32-24-Prefixed-HI}")
+     (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-HI  (f-15-1 1) (f-18-2 1) (f-20-1 1) cr1-Prefixed-32)
+     (stc32-cr1-sem cr1-Prefixed-32 dst32-24-Prefixed-HI )
+     ())
+ 
+(dni stc32.src-cr2 "stc src,dest" ((machine 32))
+     ("stc ${cr2-32},${dst32-16-Unprefixed-SI}")
+     (+ (f-0-4 #xD) dst32-16-Unprefixed-SI (f-7-1 1) (f-10-2 0) (f-12-1 2) cr2-32)
+     (stc32-cr2-sem cr2-32 dst32-16-Unprefixed-SI )
+     ())
+
+(dni stc32.src-cr3 "stc src,dst" ((machine 32))
+     ("stc ${cr3-Prefixed-32},${dst32-24-Prefixed-SI}")
+     (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-SI (f-15-1 1) (f-18-2 1) (f-20-1 0) cr3-Prefixed-32)
+     (stc32-cr3-sem cr3-Prefixed-32 dst32-24-Prefixed-SI )
+     ())
+ 
+;-------------------------------------------------------------
+; ldctx - load context
+; stctx - store context
+;-------------------------------------------------------------
+
+; ??? semantics
+(dni ldctx16 "ldctx abs16,abs24" ((machine 16))
+     ("ldctx ${Dsp-16-u16},${Dsp-32-u24}")
+     (+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 #x0) Dsp-16-u16 Dsp-32-u24)
+     (nop)
+     ())
+(dni ldctx32 "ldctx abs16,abs24" ((machine 32))
+     ("ldctx ${Dsp-16-u16},${Dsp-32-u24}")
+     (+ (f-0-4 #xB) (f-4-4 #x6) (f-8-4 #xC) (f-12-4 #x3) Dsp-16-u16 Dsp-32-u24)
+     (nop)
+     ())
+(dni stctx16 "stctx abs16,abs24" ((machine 16))
+     ("stctx ${Dsp-16-u16},${Dsp-32-u24}")
+     (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 #x0) Dsp-16-u16 Dsp-32-u24)
+     (nop)
+     ())
+(dni stctx32 "stctx abs16,abs24" ((machine 32))
+     ("stctx ${Dsp-16-u16},${Dsp-32-u24}")
+     (+ (f-0-4 #xB) (f-4-4 #x6) (f-8-4 #xD) (f-12-4 #x3) Dsp-16-u16 Dsp-32-u24)
+     (nop)
+     ())
+
+;-------------------------------------------------------------
+; lde - load from extra far data area (m16)
+; ste - store to extra far data area (m16)
+;-------------------------------------------------------------
+
+(lde-dst QI .b 0)
+(lde-dst HI .w 1)
+
+(ste-dst QI .b 0)
+(ste-dst HI .w 1)
+
+;-------------------------------------------------------------
+; ldipl - load interrupt permission level
+;-------------------------------------------------------------
+
+; ??? semantics
+; ldintb <==> ldc #imm,intbh ; ldc #imm,intbl
+
+(dni ldipl16.imm "ldipl #imm" ((machine 16))
+     ("ldipl #${Imm-13-u3}")
+     (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xA) (f-12-1 0) Imm-13-u3)
+     (nop)
+     ())
+(dni ldipl32.imm "ldipl #imm" ((machine 32))
+     ("ldipl #${Imm-13-u3}")
+     (+ (f-0-4 #xD) (f-4-4 5) (f-8-4 #xE) (f-12-1 1) Imm-13-u3)
+     (nop)
+     ())
+
+
+;-------------------------------------------------------------
+; max - maximum value
+;-------------------------------------------------------------
+
+; TODO check semantics for min -1,0
+(define-pmacro (max-sem mode src dst)
+  (sequence ()
+           (if (gt mode src dst)
+               (set mode dst src)))
+)
+
+; max.size:G #imm,dst
+(binary-arith32-imm-dst-Prefixed QI QI .b 0 max X #x8 #x3 #xF max-sem)
+(binary-arith32-imm-dst-Prefixed HI HI .w 1 max X #x8 #x3 #xF max-sem)
+
+; max.BW:G src,dst
+(binary-arith32-src-dst-Prefixed QI QI .b 0 max X #x1 #xD max-sem)
+(binary-arith32-src-dst-Prefixed HI HI .w 1 max X #x1 #xD max-sem)
+
+;-------------------------------------------------------------
+; min - minimum value
+;-------------------------------------------------------------
+
+(define-pmacro (min-sem mode src dst)
+  (sequence ()
+         (if (lt mode src dst)
+            (set mode dst src)))
+)
+
+; min.size:G #imm,dst
+(binary-arith32-imm-dst-Prefixed QI QI .b 0 min X #x8 #x2 #xF min-sem)
+(binary-arith32-imm-dst-Prefixed HI HI .w 1 min X #x8 #x2 #xF min-sem)
+
+; min.BW:G src,dst
+(binary-arith32-src-dst-Prefixed QI QI .b 0 min X #x1 #xC min-sem)
+(binary-arith32-src-dst-Prefixed HI HI .w 1 min X #x1 #xC min-sem)
+
+;-------------------------------------------------------------
+; mov - move
+;-------------------------------------------------------------
+
+(define-pmacro (mov-sem mode src1 dst)
+  (sequence ((mode result))
+           (set result src1)
+           (set-z-and-s result)
+           (set mode dst src1))
+)
+
+(define-pmacro (mov-dspsp-dst-sem mach mode src1 dst)
+  (set dst (mem-mach mach mode (add sp src1)))
+)
+
+(define-pmacro (mov-src-dspsp-sem mach mode src dst1)
+  (set (mem-mach mach mode (add sp dst1)) src)
+)
+
+(define-pmacro (mov16-imm-an-defn size mode imm regn op1 op2)
+  (dni (.sym mov16. size .S-imm- regn)
+       (.str "mov." size ":S " imm "," regn)
+       ((machine 16))
+       (.str "mov." size "$S #${" imm "}," regn)
+       (+ op1 op2 imm)
+       (mov-sem mode imm (reg (.sym h- regn))) 
+       ())
+)
+; mov.size:G #imm,dst (m16 #1 m32 #1)
+(binary-arith-imm-dst mov G (f-0-4 7) (f-4-3 2) (f-8-4 #xC) #x9 #x2 #xF mov-sem)
+; mov.L:G #imm32,dst (m32 #2)
+(binary-arith32-imm-dst-defn SI SI .l 0 mov G #xB #x3 #x1 mov-sem)
+; mov.BW:S #imm,dst2 (m32 #4)
+(binary-arith32-s-imm-dst QI .b 0 mov #x0 #x2 mov-sem)
+(binary-arith32-s-imm-dst HI .w 1 mov #x0 #x2 mov-sem)
+; mov.b:S #imm8,dst3 (m16 #3)
+(binary-arith16-b-S-imm8-dst3 mov ".b" (f-0-4 #xC) (f-4-1 0) mov-sem)
+; mov.b:S #imm8,aN (m16 #4)
+(mov16-imm-an-defn b QI Imm-8-QI a0 (f-0-4 #xE) (f-4-4 2))
+(mov16-imm-an-defn b QI Imm-8-QI a1 (f-0-4 #xE) (f-4-4 #xA))
+(mov16-imm-an-defn w HI Imm-8-HI a0 (f-0-4 #xA) (f-4-4 2))
+(mov16-imm-an-defn w HI Imm-8-HI a1 (f-0-4 #xA) (f-4-4 #xA))
+; mov.WL:S #imm,A0/A1 (m32 #5)
+(define-pmacro (mov32-wl-s-defn mode sz op1 imm regn op2)
+  (dni (.sym mov32- sz - regn)
+       (.str "mov." sz ":s" imm "," regn)
+       ((machine 32))
+       (.str "mov." sz "$S #${" imm "}," regn)
+       (+ (f-0-4 op1) (f-4-4 op2) imm)
+       (mov-sem mode imm (reg (.sym h- regn)))
+       ())
+)
+(mov32-wl-s-defn HI w #x9 Imm-8-HI a0 #xC)
+(mov32-wl-s-defn HI w #x9 Imm-8-HI a1 #xD)
+(mov32-wl-s-defn SI l #xB Dsp-8-s24 a0 #xC)
+(mov32-wl-s-defn SI l #xB Dsp-8-s24 a1 #xD)
+
+; mov.size:Q #imm4,dst (m16 #2 m32 #3)
+(binary-arith16-imm4-dst-defn QI .b 0 0 mov (f-0-4 #xD) (f-4-3 4) mov-sem)
+(binary-arith16-imm4-dst-defn HI .w 0 1 mov (f-0-4 #xD) (f-4-3 4) mov-sem)
+(binary-arith32-imm4-dst-defn QI .b 1 0 mov #x7 #x2 mov-sem)
+(binary-arith32-imm4-dst-defn HI .w 1 1 mov #x7 #x2 mov-sem)
+
+; mov.BW:Z #0,dst (m16 #5 m32 #6)
+(dni mov16.b-Z-imm8-dst3
+     "mov.b:Z #0,Dst16-3-S-8"
+     ((machine 16))
+     "mov.b$Z #0,${Dst16-3-S-8}"
+     (+ (f-0-4 #xB) (f-4-1 #x0) Dst16-3-S-8)
+     (mov-sem QI (const 0) Dst16-3-S-8)
+     ())
+; (binary-arith16-b-Z-imm8-dst3 mov ".b" (f-0-4 #xB) (f-4-1 0) mov-sem)
+(binary-arith32-z-imm-dst QI .b 0 mov #x0 #x1 mov-sem)
+(binary-arith32-z-imm-dst HI .w 1 mov #x0 #x1 mov-sem)
+; mov.BW:G src,dst (m16 #6 m32 #7)
+(binary-arith-src-dst mov G (f-0-4 #x7) (f-4-3 1) #x1 #xB mov-sem)
+; mov.B:S src2,a0/a1 (m16 #7)
+(dni (.sym mov 16 .b.S-An)
+     (.str mov ".b:S src2,a[01]")
+     ((machine 16))
+     (.str mov ".b$S ${src16-2-S},${Dst16AnQI-S}")
+     (+ (f-0-4 #x3) (f-4-1 0) Dst16AnQI-S src16-2-S)
+     (mov-sem QI src16-2-S Dst16AnQI-S)
+     ())
+(define-pmacro (mov16-b-s-an-defn op1 op2 op2c)
+  (dni (.sym mov16.b.S- op1 - op2)
+       (.str mov ".b:S " op1 "," op2)
+       ((machine 16))
+       (.str mov ".b$S " op1 "," op2)
+       (+ (f-0-4 #x3) op2c)
+       (mov-sem QI (reg (.sym h- op1)) (reg (.sym h- op2)))
+       ())
+  )
+(mov16-b-s-an-defn r0l a1 (f-4-4 #x4))
+(mov16-b-s-an-defn r0h a0 (f-4-4 #x0))
+
+; mov.L:G src,dst (m32 #8)
+(binary-arith32-src-dst-defn SI SI .l 1 mov G #x1 #x3 mov-sem)
+; mov.B:S r0l/r0h,dst2 (m16 #8)
+(dni (.sym mov 16 .b.S-Rn-An)
+     (.str mov ".b:S r0[lh],src2")
+     ((machine 16))
+     (.str mov ".b$S ${Dst16RnQI-S},${src16-2-S}")
+     (+ (f-0-4 #x0) (f-4-1 0) Dst16RnQI-S src16-2-S)
+     (mov-sem QI src16-2-S Dst16RnQI-S)
+     ())
+
+; mov.B.S src2,r0l/r0h (m16 #9)
+(binary-arith16-b-S-src2 mov (f-0-4 0) (f-4-1 1) mov-sem)
+
+; mov.BW:S src2,r0l/r0 (m32 #9)
+; mov.BW:S src2,r1l/r1 (m32 #10)
+(define-pmacro (mov32-src-r sz szcode mode src dst opc1 opc2)
+  (begin
+    (dni (.sym mov32. sz - src - dst)
+        (.str "mov." sz "src," dst)
+        ((machine 32))
+        (.str "mov."  sz "$S ${" (.sym src - mode) "}," dst)
+        (+ (f-0-2 opc1) (.sym src - mode) (f-4-3 opc2) (f-7-1 szcode))
+        (mov-sem mode (.sym src - mode) (reg (.sym h- dst)))
+        ())
+    )
+  )
+(mov32-src-r b 0 QI dst32-2-S-16 r0l 0 4)
+(mov32-src-r w 1 HI dst32-2-S-16 r0 0 4)
+(mov32-src-r b 0 QI dst32-2-S-8 r0l 0 4)
+(mov32-src-r w 1 HI dst32-2-S-8 r0 0 4)
+(mov32-src-r b 0 QI dst32-2-S-basic r1l 1 7)
+(mov32-src-r w 1 HI dst32-2-S-basic r1 1 7)
+(mov32-src-r b 0 QI dst32-2-S-16 r1l 1 7)
+(mov32-src-r w 1 HI dst32-2-S-16 r1 1 7)
+(mov32-src-r b 0 QI dst32-2-S-8 r1l 1 7)
+(mov32-src-r w 1 HI dst32-2-S-8 r1 1 7)
+
+; mov.BW:S r0l/r0,dst2 (m32 #11)
+(define-pmacro (mov32-r-dest sz szcode mode src dst opc1 opc2)
+  (begin
+    (dni (.sym mov32. sz - src - dst)
+        (.str "mov." sz "src," dst)
+        ((machine 32))
+        (.str "mov."  sz "$S " src ",${" (.sym dst - mode) "}")
+        (+ (f-0-2 opc1) (.sym dst - mode) (f-4-3 opc2) (f-7-1 szcode))
+        (mov-sem mode (reg (.sym h- src)) (.sym dst - mode))
+        ())
+    )
+  )
+(mov32-r-dest b 0 QI r0l dst32-2-S-16 0 0)
+(mov32-r-dest w 1 HI r0  dst32-2-S-16 0 0)
+(mov32-r-dest b 0 QI r0l dst32-2-S-8  0 0)
+(mov32-r-dest w 1 HI r0  dst32-2-S-8  0 0)
+
+; mov.L:S src,A0/A1    (m32 #12)
+(define-pmacro (mov32-src-a src dst dstcode opc1 opc2)
+  (begin
+    (dni (.sym mov32. sz - src - dst)
+        (.str "mov." sz "src," dst)
+        ((machine 32))
+        (.str "mov.l" "$S ${" (.sym src - SI) "}," dst)
+        (+ (f-0-2 opc1) (.sym src - SI) (f-4-3 opc2) (f-7-1 dstcode))
+        (mov-sem SI (.sym src - SI) (reg (.sym h- dst)))
+        ())
+    )
+  )
+(mov32-src-a dst32-2-S-16 a0 0 1 4)
+(mov32-src-a dst32-2-S-16 a1 1 1 4)
+(mov32-src-a dst32-2-S-8 a0 0 1 4)
+(mov32-src-a dst32-2-S-8 a1 1 1 4)
+
+; mov.BW:G dsp8[sp],dst (m16 #10 m32 #13)
+; mov.BW:G src,dsp8[sp] (m16 #11 m32 #14)
+(mov-dspsp-dst mov (f-0-4 #x7) (f-4-3 2) (f-8-4 #xB) #xB #x0 #xF mov-dspsp-dst-sem)
+(mov-src-dspsp mov (f-0-4 #x7) (f-4-3 2) (f-8-4 #x3) #xA #x0 #xF mov-src-dspsp-sem)
+
+;-------------------------------------------------------------
+; mova - move effective address
+;-------------------------------------------------------------
+
+(define-pmacro (mov16a-defn dst dstop dstcode)
+  (dni (.sym mova16. src - dst)
+       (.str "mova src," dst)
+       ((machine 16))
+       (.str "mova ${dst16-16-Mova-HI}," dst)
+       (+ (f-0-4 #xE) (f-4-4 #xB) dst16-16-Mova-HI (f-8-4 dstcode))
+       (sequence () (set HI (reg dstop) dst16-16-Mova-HI))
+       ())
+)
+(mov16a-defn r0 h-r0 0)
+(mov16a-defn r1 h-r1 1)
+(mov16a-defn r2 h-r2 2)
+(mov16a-defn r3 h-r3 3)
+(mov16a-defn a0 h-a0 4)
+(mov16a-defn a1 h-a1 5)
+
+(define-pmacro (mov32a-defn dst dstop dstcode)
+  (dni (.sym mova32. src - dst)
+       (.str "mova src," dst)
+       ((machine 32))
+       (.str "mova ${dst32-16-Unprefixed-Mova-SI}," dst)
+       (+ (f-0-4 #xD) dst32-16-Unprefixed-Mova-SI (f-7-1 1) (f-10-2 1) (f-12-1 1) (f-13-3 dstcode))
+       (sequence () (set SI (reg dstop) dst32-16-Unprefixed-Mova-SI))
+       ())
+)
+(mov32a-defn r2r0 h-r2r0 0)
+(mov32a-defn r3r1 h-r3r1 1)
+(mov32a-defn a0 h-a0 2)
+(mov32a-defn a1 h-a1 3)
+
+;-------------------------------------------------------------
+; movDir - move nibble
+;-------------------------------------------------------------
+
+(define-pmacro (movdir-sem nib src dst)
+  (sequence ((SI tmp))
+           (case DFLT nib
+                 ((0) (set dst (or (and dst #xf0) (and src #xf))))
+                 ((1) (set dst (or (and dst #x0f) (sll (and src #xf) 4))))
+                 ((2) (set dst (or (and dst #xf0) (srl (and src #xf0) 4))))
+                 ((3) (set dst (or (and dst #x0f) (and src #xf0))))
+                 )
+           )
+  )
+; movDir src,dst
+(define-pmacro (mov16dir-1-defn nib dircode dir)
+  (dni (.sym mov nib 16 ".r0l-dst")
+       (.str "mov" nib " r0l,dst")
+       ((machine 16))
+       (.str "mov" nib " r0l,${dst16-16-QI}")
+       (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 dir) dst16-16-QI)
+       (movdir-sem dircode (reg h-r0l) dst16-16-QI)
+       ())
+)
+(mov16dir-1-defn ll 0 8)
+(mov16dir-1-defn lh 1 #xA)
+(mov16dir-1-defn hl 2 9)
+(mov16dir-1-defn hh 3 #xB)
+(define-pmacro (mov16dir-2-defn nib dircode dir)
+  (dni (.sym mov nib 16 ".src-r0l")
+       (.str "mov" nib " src,r0l")
+       ((machine 16))
+       (.str "mov" nib " ${dst16-16-QI},r0l")
+       (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 dir) dst16-16-QI)
+       (movdir-sem dircode dst16-16-QI (reg h-r0l))
+       ())
+)
+(mov16dir-2-defn ll 0 0)
+(mov16dir-2-defn lh 1 2)
+(mov16dir-2-defn hl 2 1)
+(mov16dir-2-defn hh 3 3)
+
+(define-pmacro (mov32dir-1-defn nib o1o0)
+  (dni (.sym mov nib 32 ".r0l-dst")
+       (.str "mov" nib " r0l,dst")
+       ((machine 32))
+       (.str "mov" nib " r0l,${dst32-24-Prefixed-QI}")
+       (+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #xB) dst32-24-Prefixed-QI (f-15-1 0) (f-18-2 o1o0) (f-20-4 #xE))
+       (movdir-sem o1o0 (reg h-r0l) dst32-24-Prefixed-QI)
+       ())
+)
+(mov32dir-1-defn ll 0)
+(mov32dir-1-defn lh 1)
+(mov32dir-1-defn hl 2)
+(mov32dir-1-defn hh 3)
+(define-pmacro (mov32dir-2-defn nib o1o0)
+  (dni (.sym mov nib 32 ".src-r0l")
+       (.str "mov" nib " src,r0l")
+       ((machine 32))
+       (.str "mov" nib " ${dst32-24-Prefixed-QI},r0l")
+       (+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #xA) dst32-24-Prefixed-QI (f-15-1 0) (f-18-2 o1o0) (f-20-4 #xE))
+       (movdir-sem o1o0 dst32-24-Prefixed-QI (reg h-r0l))
+       ())
+)
+(mov32dir-2-defn ll 0)
+(mov32dir-2-defn lh 1)
+(mov32dir-2-defn hl 2)
+(mov32dir-2-defn hh 3)
+
+;-------------------------------------------------------------
+; movx - move extend sign (m32)
+;-------------------------------------------------------------
+
+(define-pmacro (movx-sem mode src dst)
+  (sequence ((SI source) (SI result))
+           (set SI result src)
+           (set-z-and-s result)
+           (set dst result))
+)
+
+; movx #imm,dst
+(binary-arith32-imm-dst-defn QI SI "" 0 movx X #xB #x1 #x1 movx-sem)
+
+;-------------------------------------------------------------
+; mul - multiply
+;-------------------------------------------------------------
+
+(define-pmacro (mul-sem mode src1 dst)
+  (sequence ((mode result))
+           (set obit (add-oflag mode src1 dst 0))
+           (set result (mul mode src1 dst))
+           (set dst result))
+)
+
+; mul.BW #imm,dst
+(binary-arith-imm-dst mul G (f-0-4 7) (f-4-3 6) (f-8-4 5) #x8 #x1 #xF mul-sem)
+; mul.BW src,dst
+(binary-arith-src-dst mul G (f-0-4 #x7) (f-4-3 4) #x1 #xC mul-sem)
+
+(dni mul_l "mul.l src,r2r0" ((machine 32))
+     ("mul.l ${dst32-24-Prefixed-SI},r2r0")
+     (+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #x8) (f-15-1 #x1) (f-18-2 #x1) (f-20-4 #xf)
+       dst32-24-Prefixed-SI)
+     () ())
+
+(dni mulu_l "mulu.l src,r2r0" ((machine 32))
+     ("mulu.l ${dst32-24-Prefixed-SI},r2r0")
+     (+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #x8) (f-15-1 #x1) (f-18-2 #x0) (f-20-4 #xf)
+       dst32-24-Prefixed-SI)
+     () ())
+;-------------------------------------------------------------
+; mulex - multiple extend sign (m32)
+;-------------------------------------------------------------
+
+; mulex src,dst
+; (dni mulex-absolute-indirect "mulex [src]" ((machine 32))
+;      ("mulex ${dst32-24-absolute-indirect-HI}")
+;      (+ (f-0-4 0) (f-4-4 9) (f-8-4 #xC) dst32-24-absolute-indirect-HI (f-15-1 1) (f-18-2 3) (f-20-4 #xE))
+;      (set R1R2R0 (mul DI (ext DI R2R0) (ext DI dst32-24-absolute-indirect-HI)))
+;      ())
+(dni mulex "mulex src" ((machine 32))
+     ("mulex ${dst32-16-Unprefixed-Mulex-HI}")
+     (+ (f-0-4 #xC) dst32-16-Unprefixed-Mulex-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xE))
+     (set R1R2R0 (mul DI (ext DI R2R0) (ext DI dst32-16-Unprefixed-Mulex-HI)))
+     ())
+; (dni mulex-indirect "mulex [src]" ((machine 32))
+;      ("mulex ${dst32-24-indirect-HI}")
+;      (+ (f-0-4 0) (f-4-4 9) (f-8-4 #xC) dst32-24-indirect-HI (f-15-1 1) (f-18-2 3) (f-20-4 #xE))
+;      (set R1R2R0 (mul DI (ext DI R2R0) (ext DI dst32-24-indirect-HI)))
+;      ())
+
+;-------------------------------------------------------------
+; mulu - multiply unsigned
+;-------------------------------------------------------------
+
+(define-pmacro (mulu-sem mode src1 dst)
+  (sequence ((mode result))
+           (set obit (add-oflag mode src1 dst 0))
+           (set result (mul mode src1 dst))
+           (set dst result))
+)
+
+; mulu.BW #imm,dst
+(binary-arith-imm-dst mulu G (f-0-4 7) (f-4-3 6) (f-8-4 4) #x8 #x0 #xF mulu-sem)
+; mulu.BW src,dst
+(binary-arith-src-dst mulu G (f-0-4 #x7) (f-4-3 0) #x1 #x4 mulu-sem)
+
+;-------------------------------------------------------------
+; neg - twos complement
+;-------------------------------------------------------------
+
+(define-pmacro (neg-sem mode dst)
+  (sequence ((mode result))
+           (set result (neg mode dst))
+           (set-z-and-s result)
+           (set dst result))
+)
+
+; neg.BW:G
+(unary-insn neg (f-0-4 7) (f-4-3 2) (f-8-4 #x5) #xA #x2 #xF neg-sem)
+
+;-------------------------------------------------------------
+; not - twos complement
+;-------------------------------------------------------------
+
+(define-pmacro (not-sem mode dst)
+  (sequence ((mode result))
+           (set result (not mode dst))
+           (set-z-and-s result)
+           (set dst result))
+)
+
+; not.BW:G
+(unary-insn-g not (f-0-4 7) (f-4-3 2) (f-8-4 #x7) #xA #x1 #xE not-sem)
+
+(dni not16.b.s
+     "not.b:s Dst16-3-S-8"
+     ((machine 16))
+     "not.b:s ${Dst16-3-S-8}"
+     (+ (f-0-4 #xb) (f-4-1 #x1) Dst16-3-S-8)
+     (not-sem QI Dst16-3-S-8)
+     ())
+
+;-------------------------------------------------------------
+; nop
+;-------------------------------------------------------------
+
+(dni nop16
+     "nop"
+     ((machine 16))
+     "nop"
+     (+ (f-0-4 #x0) (f-4-4 #x4))
+     (nop)
+     ())
+
+(dni nop32
+     "nop"
+     ((machine 32))
+     "nop"
+     (+ (f-0-4 #xD) (f-4-4 #xE))
+     (nop)
+     ())
+
+;-------------------------------------------------------------
+; or - logical or
+;-------------------------------------------------------------
+
+(define-pmacro (or-sem mode src1 dst)
+  (sequence ((mode result))
+           (set result (or mode src1 dst))
+           (set-z-and-s result)
+           (set dst result))
+)
+
+; or.BW #imm,dst (m16 #1 m32 #1)
+(binary-arith-imm-dst or G (f-0-4 7) (f-4-3 3) (f-8-4 3) #x8 #x2 #xF or-sem)
+; or.b:S #imm8,dst3 (m16 #2 m32 #2)
+(binary-arith16-b-S-imm8-dst3 or ".b" (f-0-4 9) (f-4-1 1) or-sem)
+(binary-arith32-s-imm-dst QI .b 0 or #x1 #x2 or-sem)
+(binary-arith32-s-imm-dst HI .w 1 or #x1 #x2 or-sem)
+; or.BW src,dst (m16 #3 m32 #3)
+(binary-arith-src-dst or G (f-0-4 #x9) (f-4-3 4) #x1 #x5 or-sem)
+; or.b:S src,r0[lh] (m16)
+(binary-arith16-b-S-src2 or (f-0-4 1) (f-4-1 1) or-sem)
+
+;-------------------------------------------------------------
+; pop - restore register/memory
+;-------------------------------------------------------------
+
+; TODO future: split this into .b and .w semantics
+(define-pmacro (pop-sem-mach mach mode dst)
+  (sequence ((mode b_or_w) (SI length))
+           (set b_or_w -1)
+           (set b_or_w (srl b_or_w #x8))
+           (if (eq b_or_w #x0)
+               (set length 1)    ; .b
+               (set length 2))   ; .w
+           
+           (case DFLT length
+                 ((1) (set dst (mem-mach mach QI (reg h-sp))))
+                 ((2) (set dst (mem-mach mach HI (reg h-sp)))))
+           (set (reg h-sp) (add (reg h-sp) length))
+           )
+)
+
+(define-pmacro (pop-sem16 mode dest) (pop-sem-mach 16 mode dest))
+(define-pmacro (pop-sem32 mode dest) (pop-sem-mach 32 mode dest))
+
+; pop.BW:G (m16 #1)
+(unary-insn-mach-g 16 pop (f-0-4 7) (f-4-3 2) (f-8-4 #xD) pop-sem16 $G)
+; pop.BW:G (m32 #1)
+(unary-insn-mach 32 pop #xB #x2 #xF pop-sem32)
+
+; pop.b:S r0l/r0h
+(dni pop16.b-s-rn  "pop.b:S r0[lh]" ((machine 16))
+     "pop.b$S ${Rn16-push-S-anyof}"
+     (+ (f-0-4 #x9) Rn16-push-S-anyof (f-5-3 #x2))
+     (pop-sem16 QI Rn16-push-S-anyof)
+     ())
+; pop.w:S a0/a1
+(dni pop16.b-s-an  "pop.w:S a[01]" ((machine 16))
+     "pop.w$S ${An16-push-S-anyof}"
+     (+ (f-0-4 #xD) An16-push-S-anyof (f-5-3 #x2))
+     (pop-sem16 HI An16-push-S-anyof)
+     ())
+
+;-------------------------------------------------------------
+; popc - pop control register
+; pushc - push control register
+;-------------------------------------------------------------
+
+(define-pmacro (popc32-cr1-sem mode dst)
+  (sequence ()
+           (case DFLT dst
+                 ((#x0) (set (reg h-dct0) (mem32 mode (reg h-sp))))
+                 ((#x1) (set (reg h-dct1) (mem32 mode (reg h-sp))))
+                 ((#x2) (sequence ((HI tflag))
+                                  (set tflag (mem32 mode (reg h-sp)))
+                                  (if (and tflag #x1) (set cbit 1)) 
+                                  (if (and tflag #x2) (set dbit 1)) 
+                                  (if (and tflag #x4) (set zbit 1)) 
+                                  (if (and tflag #x8) (set sbit 1)) 
+                                  (if (and tflag #x10) (set bbit 1)) 
+                                  (if (and tflag #x20) (set obit 1)) 
+                                  (if (and tflag #x40) (set ibit 1)) 
+                                  (if (and tflag #x80) (set ubit 1))))
+                 ((#x3) (set (reg h-svf) (mem32 mode (reg h-sp))))
+                 ((#x4) (set (reg h-drc0) (mem32 mode (reg h-sp))))
+                 ((#x5) (set (reg h-drc1) (mem32 mode (reg h-sp))))
+                 ((#x6) (set (reg h-dmd0) (mem32 mode (reg h-sp))))
+                 ((#x7) (set (reg h-dmd1) (mem32 mode (reg h-sp))))
+           )
+           (set (reg h-sp) (add (reg h-sp) 2))
+  )
+)
+(define-pmacro (popc32-cr2-sem mode dst)
+  (sequence ()
+           (case DFLT dst
+                 ((#x0) (set (reg h-intb) (mem32 mode (reg h-sp))))
+                 ((#x1) (set (reg h-sp) (mem32 mode (reg h-sp))))
+                 ((#x2) (set (reg h-sb) (mem32 mode (reg h-sp))))
+                 ((#x3) (set (reg h-fb) (mem32 mode (reg h-sp))))
+                 ((#x7) (set (reg h-isp) (mem32 mode (reg h-sp))))
+           )
+           (set (reg h-sp) (add (reg h-sp) 4))
+  )
+)
+(define-pmacro (popc16-sem mode dst)
+  (sequence ()
+           (case DFLT dst
+                 ((#x1) (set (reg h-intb) (or (and (reg h-intb) #x0000)
+                                              (mem16 mode (reg h-sp)))))
+                 ((#x2) (set (reg h-intb) (or (and (reg h-intb) #xffff0000)
+                                              (mem16 mode (reg h-sp)))))
+                 ((#x3) (sequence ((HI tflag))
+                                  (set tflag (mem16 mode (reg h-sp)))
+                                  (if (and tflag #x1) (set cbit 1)) 
+                                  (if (and tflag #x2) (set dbit 1)) 
+                                  (if (and tflag #x4) (set zbit 1)) 
+                                  (if (and tflag #x8) (set sbit 1)) 
+                                  (if (and tflag #x10) (set bbit 1)) 
+                                  (if (and tflag #x20) (set obit 1)) 
+                                  (if (and tflag #x40) (set ibit 1)) 
+                                  (if (and tflag #x80) (set ubit 1))))
+                 ((#x4) (set (reg h-isp) (mem16 mode (reg h-sp))))
+                 ((#x5) (set (reg h-sp) (mem16 mode (reg h-sp))))
+                 ((#x6) (set (reg h-sb) (mem16 mode (reg h-sp))))
+                 ((#x7) (set (reg h-fb) (mem16 mode (reg h-sp))))
+           )
+           (set (reg h-sp) (add (reg h-sp) 2))
+  )
+)
+; popc dest (m16c #1)
+(dni popc16.imm16 "popc dst" ((machine 16))
+     ("popc ${cr16}")
+     (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) (f-12-4 3) cr16)
+     (popc16-sem HI cr16)
+     ())
+; popc dest (m32c #1)
+(dni popc32.imm16-cr1 "popc dst" ((machine 32))
+     ("popc ${cr1-Unprefixed-32}")
+     (+ (f-0-4 #xD) (f-4-4 3) (f-8-4 #xA) (f-12-1 1) cr1-Unprefixed-32)
+     (popc32-cr1-sem HI cr1-Unprefixed-32)
+     ())
+; popc dest (m32c #2)
+(dni popc32.imm16-cr2 "popc dst" ((machine 32))
+     ("popc ${cr2-32}")
+     (+ (f-0-4 #xD) (f-4-4 3) (f-8-4 2) (f-12-1 1) cr2-32)
+     (popc32-cr2-sem SI cr2-32)
+     ())
+
+(define-pmacro (pushc32-cr1-sem mode dst)
+  (sequence ()
+           (set (reg h-sp) (sub (reg h-sp) 2))
+           (case DFLT dst
+                 ((#x0) (set (mem32 mode (reg h-sp)) (reg h-dct0)))
+                 ((#x1) (set (mem32 mode (reg h-sp)) (reg h-dct1)))
+                 ((#x2) (sequence ((HI tflag))
+                                  (set tflag 0)
+                                  (if (eq cbit 1) (set tflag (or tflag #x1)))
+                                  (if (eq dbit 1) (set tflag (or tflag #x2)))
+                                  (if (eq zbit 1) (set tflag (or tflag #x4)))
+                                  (if (eq sbit 1) (set tflag (or tflag #x8)))
+                                  (if (eq bbit 1) (set tflag (or tflag #x10)))
+                                  (if (eq obit 1) (set tflag (or tflag #x20)))
+                                  (if (eq ibit 1) (set tflag (or tflag #x40)))
+                                  (if (eq ubit 1) (set tflag (or tflag #x80)))
+                                  (set (mem32 mode (reg h-sp)) tflag)))
+                 ((#x3) (set (mem32 mode (reg h-sp)) (reg h-svf)))
+                 ((#x4) (set (mem32 mode (reg h-sp)) (reg h-drc0)))
+                 ((#x5) (set (mem32 mode (reg h-sp)) (reg h-drc1)))
+                 ((#x6) (set (mem32 mode (reg h-sp)) (reg h-dmd0)))
+                 ((#x7) (set (mem32 mode (reg h-sp)) (reg h-dmd1)))
+           )
+  )
+)
+(define-pmacro (pushc32-cr2-sem mode dst)
+  (sequence ()
+           (set (reg h-sp) (sub (reg h-sp) 4))
+           (case DFLT dst
+                 ((#x0) (set (mem32 mode (reg h-sp)) (reg h-intb)))
+                 ((#x1) (set (mem32 mode (reg h-sp)) (reg h-sp)))
+                 ((#x2) (set (mem32 mode (reg h-sp)) (reg h-sb)))
+                 ((#x3) (set (mem32 mode (reg h-sp)) (reg h-fb)))
+                 ((#x7) (set (mem32 mode (reg h-sp)) (reg h-isp)))
+           )
+  )
+)
+(define-pmacro (pushc16-sem mode dst)
+  (sequence ()
+           (set (reg h-sp) (sub (reg h-sp) 2))
+           (case DFLT dst
+                 ((#x1) (set (mem16 mode (reg h-sp)) (and (reg h-intb) #xffff)))
+                 ((#x2) (set (mem16 mode (reg h-sp)) (and (reg h-intb) #xffff0000)))
+                 ((#x3) (sequence ((HI tflag))
+                                  (if (eq cbit 1) (set tflag (or tflag #x1)))
+                                  (if (eq dbit 1) (set tflag (or tflag #x2)))
+                                  (if (eq zbit 1) (set tflag (or tflag #x4)))
+                                  (if (eq sbit 1) (set tflag (or tflag #x8)))
+                                  (if (eq bbit 1) (set tflag (or tflag #x10)))
+                                  (if (eq obit 1) (set tflag (or tflag #x20)))
+                                  (if (eq ibit 1) (set tflag (or tflag #x40)))
+                                  (if (eq ubit 1) (set tflag (or tflag #x80)))
+                                  (set (mem16 mode (reg h-sp)) tflag)))
+                  
+                 ((#x4) (set (mem16 mode (reg h-sp)) (reg h-isp)))
+                 ((#x5) (set (mem16 mode (reg h-sp)) (reg h-sp)))
+                 ((#x6) (set (mem16 mode (reg h-sp)) (reg h-sb)))
+                 ((#x7) (set (mem16 mode (reg h-sp)) (reg h-fb)))
+           )
+  )
+)
+; pushc src (m16c)
+(dni pushc16.imm16 "pushc dst" ((machine 16))
+     ("pushc ${cr16}")
+     (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) (f-12-4 2) cr16)
+     (pushc16-sem HI cr16)
+     ())
+; pushc src (m32c #1)
+(dni pushc32.imm16-cr1 "pushc dst" ((machine 32))
+     ("pushc ${cr1-Unprefixed-32}")
+     (+ (f-0-4 #xD) (f-4-4 1) (f-8-4 #xA) (f-12-1 1) cr1-Unprefixed-32)
+     (pushc32-cr1-sem HI cr1-Unprefixed-32)
+     ())
+; pushc src (m32c #2)
+(dni pushc32.imm16-cr2 "pushc dst" ((machine 32))
+     ("pushc ${cr2-32}")
+     (+ (f-0-4 #xD) (f-4-4 1) (f-8-4 2) (f-12-1 1) cr2-32)
+     (pushc32-cr2-sem SI cr2-32)
+     ())
+
+;-------------------------------------------------------------
+; popm - pop multiple
+; pushm - push multiple
+;-------------------------------------------------------------
+
+(define-pmacro (popm-sem machine dst)
+     (sequence ((SI addrlen))
+              (if (eq machine 16)
+                  (set addrlen 2)
+                  (set addrlen 4))
+               (if (and dst 1)
+                  (sequence () (set R0 (mem-mach machine HI (reg h-sp)))
+                            (set (reg h-sp) (add (reg h-sp) 2))))
+               (if (and dst 2)
+                  (sequence () (set R1 (mem-mach machine HI (reg h-sp)))
+                            (set (reg h-sp) (add (reg h-sp) 2))))
+              (if (and dst 4)
+                  (sequence () (set R2 (mem-mach machine HI (reg h-sp)))
+                            (set (reg h-sp) (add (reg h-sp) 2))))
+               (if (and dst 8)
+                  (sequence () (set R3 (mem-mach machine HI (reg h-sp)))
+                            (set (reg h-sp) (add (reg h-sp) 2))))
+               (if (and dst 16)
+                  (sequence () (set A0 (mem-mach machine HI (reg h-sp)))
+                            (set (reg h-sp) (add (reg h-sp) addrlen))))
+               (if (and dst 32)
+                  (sequence () (set A1 (mem-mach machine HI (reg h-sp)))
+                            (set (reg h-sp) (add (reg h-sp) addrlen))))
+               (if (and dst 64)
+                  (sequence () (set (reg h-sb) (mem-mach machine HI (reg h-sp)))
+                            (set (reg h-sp) (add (reg h-sp) addrlen))))
+               (if (eq dst 128)
+                  (sequence () (set (reg h-fb) (mem-mach machine HI (reg h-sp)))
+                            (set (reg h-sp) (add (reg h-sp) addrlen))))
+              )
+)
+
+(define-pmacro (pushm-sem machine dst)
+     (sequence ((SI count) (SI addrlen))
+              (if (eq machine 16)
+                  (set addrlen 2)
+                  (set addrlen 4))
+               (if (eq dst 1)
+                  (sequence () (set (reg h-sp) (sub (reg h-sp) addrlen))
+                            (set (mem-mach machine HI (reg h-sp)) (reg h-fb))))
+               (if (and dst 2)
+                  (sequence () (set (reg h-sp) (sub (reg h-sp) addrlen))
+                            (set (mem-mach machine HI (reg h-sp)) (reg h-sb))))
+               (if (and dst 4)
+                  (sequence () (set (reg h-sp) (sub (reg h-sp) addrlen))
+                            (set (mem-mach machine HI (reg h-sp)) A1)))
+               (if (and dst 8)
+                  (sequence () (set (reg h-sp) (sub (reg h-sp) addrlen))
+                            (set (mem-mach machine HI (reg h-sp)) A0)))
+               (if (and dst 16)
+                  (sequence () (set (reg h-sp) (sub (reg h-sp) 2))
+                            (set (mem-mach machine HI (reg h-sp)) R3)))
+              (if (and dst 32)
+                  (sequence () (set (reg h-sp) (sub (reg h-sp) 2))
+                            (set (mem-mach machine HI (reg h-sp)) R2)))
+               (if (and dst 64)
+                  (sequence () (set (reg h-sp) (sub (reg h-sp) 2))
+                            (set (mem-mach machine HI (reg h-sp)) R1)))
+               (if (and dst 128)
+                  (sequence () (set (reg h-sp) (sub (reg h-sp) 2))
+                            (set (mem-mach machine HI (reg h-sp)) R0)))
+              )
+)
+
+(dni popm16 "popm regs" ((machine 16))
+     ("popm ${Regsetpop}")
+     (+ (f-0-4 #xE) (f-4-4 #xD) Regsetpop)
+     (popm-sem 16 Regsetpop)
+     ())
+(dni pushm16 "pushm regs" ((machine 16))
+     ("pushm ${Regsetpush}")
+     (+ (f-0-4 #xE) (f-4-4 #xC) Regsetpush)
+     (pushm-sem 16 Regsetpush)
+     ())
+(dni popm "popm regs" ((machine 32))
+     ("popm ${Regsetpop}")
+     (+ (f-0-4 #x8) (f-4-4 #xE) Regsetpop)
+     (popm-sem 32 Regsetpop)
+     ())
+(dni pushm "pushm regs" ((machine 32))
+     ("pushm ${Regsetpush}")
+     (+ (f-0-4 #x8) (f-4-4 #xF) Regsetpush)
+     (pushm-sem 32 Regsetpush)
+     ())
+
+;-------------------------------------------------------------
+; push - Save register/memory/immediate data
+;-------------------------------------------------------------
+
+; TODO future: split this into .b and .w semantics
+(define-pmacro (push-sem-mach mach mode dst)
+  (sequence ((mode b_or_w) (SI length))
+           (set b_or_w -1)
+           (set b_or_w (srl b_or_w #x8))
+           (if (eq b_or_w #x0)
+               (set length 1)    ; .b
+               (if (eq b_or_w #xff)
+                   (set length 2)   ; .w
+                   (set length 4))) ; .l
+           (set (reg h-sp) (sub (reg h-sp) length))
+           (case DFLT length
+                 ((1) (set (mem-mach mach QI (reg h-sp)) dst))
+                 ((2) (set (mem-mach mach HI (reg h-sp)) dst))
+                 ((4) (set (mem-mach mach SI (reg h-sp)) dst)))
+           )
+  )
+
+(define-pmacro (push-sem16 mode dst) (push-sem-mach 16 mode dst))
+(define-pmacro (push-sem32 mode dst) (push-sem-mach 32 mode dst))
+
+; push.BW:G imm (m16 #1 m32 #1)
+(dni push16.b.G-imm "push.b:G #Imm-16-QI" ((machine 16))
+     ("push.b$G #${Imm-16-QI}")
+     (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 2) Imm-16-QI)
+     (push-sem16 QI Imm-16-QI)
+     ())
+ 
+(dni push16.w.G-imm "push.w:G #Imm-16-HI" ((machine 16))
+     ("push.w$G #${Imm-16-HI}")
+     (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 2) Imm-16-HI)
+     (push-sem16 HI Imm-16-HI)
+     ())
+
+(dni push32.b.imm "push.b #Imm-8-QI" ((machine 32))
+     ("push.b #${Imm-8-QI}")
+     (+ (f-0-4 #xA) (f-4-4 #xE) Imm-8-QI)
+     (push-sem32 QI Imm-8-QI)
+     ())
+ 
+(dni push32.w.imm "push.w #Imm-8-HI" ((machine 32))
+     ("push.w #${Imm-8-HI}")
+     (+ (f-0-4 #xA) (f-4-4 #xF) Imm-8-HI)
+     (push-sem32 HI Imm-8-HI)
+     ())
+
+; push.BW:G src (m16 #2)
+(unary-insn-mach-g 16 push (f-0-4 7) (f-4-3 2) (f-8-4 #x4) push-sem16 $G)
+; push.BW:G src (m32 #2)
+(unary-insn-mach 32 push #xC #x0 #xE push-sem32)
+
+
+; push.b:S r0l/r0h (m16 #3)
+(dni push16.b-s-rn  "push.b:S r0[lh]" ((machine 16))
+     "push.b$S ${Rn16-push-S-anyof}"
+     (+ (f-0-4 #x8) Rn16-push-S-anyof (f-5-3 #x2))
+     (push-sem16 QI Rn16-push-S-anyof)
+     ())
+; push.w:S a0/a1 (m16 #4)
+(dni push16.b-s-an  "push.w:S a[01]" ((machine 16))
+     "push.w$S ${An16-push-S-anyof}"
+     (+ (f-0-4 #xC) An16-push-S-anyof (f-5-3 #x2))
+     (push-sem16 HI An16-push-S-anyof)
+     ())
+
+; push.l imm32 (m32 #3)
+(dni push32.l.imm "push.l #Imm-16-SI" ((machine 32))
+     ("push.l #${Imm-16-SI}")
+     (+ (f-0-4 #xB) (f-4-4 6) (f-8-4 5) (f-12-4 3) Imm-16-SI)
+     (push-sem32 SI Imm-16-SI)
+     ())
+; push.l src (m32 #4)
+(unary-insn-defn 32 16-Unprefixed SI .l push (+ (f-0-4 #xA) (f-7-1 0) dst32-16-Unprefixed-SI (f-10-2 0) (f-12-4 1)) push-sem32)
+
+;-------------------------------------------------------------
+; pusha - push effective address
+;------------------------------------------------------------
+
+(define-pmacro (push16a-sem mode dst)
+  (sequence ()
+           (set (reg h-sp) (sub (reg h-sp) 2))
+           (set (mem16 HI (reg h-sp)) dst))
+)
+(define-pmacro (push32a-sem mode dst)
+  (sequence ()
+           (set (reg h-sp) (sub (reg h-sp) 4))
+           (set (mem32 SI (reg h-sp)) dst))
+)
+(unary-insn-defn 16 16-Mova HI "" pusha (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 9) dst16-16-Mova-HI) push16a-sem)
+(unary-insn-defn 32 16-Unprefixed-Mova SI "" pusha (+ (f-0-4 #xB) (f-7-1 0) dst32-16-Unprefixed-Mova-SI (f-10-2 0) (f-12-4 1)) push32a-sem)
+
+;-------------------------------------------------------------
+; reit - return from interrupt
+;-------------------------------------------------------------
+
+; ??? semantics
+(dni reit16 "REIT" ((machine 16))
+     ("reit")
+     (+ (f-0-4 #xF) (f-4-4 #xB))
+     (nop)
+     ())
+(dni reit32 "REIT" ((machine 32))
+     ("reit")
+     (+ (f-0-4 9) (f-4-4 #xE))
+     (nop)
+     ())
+
+;-------------------------------------------------------------
+; rmpa - repeat multiple and addition
+;-------------------------------------------------------------
+
+; TODO semantics
+(dni rmpa16.b "rmpa.size" ((machine 16))
+     ("rmpa.b")
+     (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 1))
+     (nop)
+     ())
+(dni rmpa16.w "rmpa.size" ((machine 16))
+     ("rmpa.w")
+     (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 1))
+     (nop)
+     ())
+(dni rmpa32.b "rmpa.size" ((machine 32))
+     ("rmpa.b")
+     (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 4) (f-12-4 3))
+     (nop)
+     ())
+ 
+(dni rmpa32.w "rmpa.size" ((machine 32))
+     ("rmpa.w")
+     (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 5) (f-12-4 3))
+     (nop)
+     ())
+
+;-------------------------------------------------------------
+; rolc - rotate left with carry
+;-------------------------------------------------------------
+
+; TODO check semantics
+; TODO future: split this into .b and .w semantics
+(define-pmacro (rolc-sem mode dst)
+  (sequence ((mode result) (SI ocbit) (mode b_or_w) (USI mask))
+           (set b_or_w -1)
+           (set b_or_w (srl b_or_w #x8))
+           (if (eq b_or_w #x0)
+               (set mask #x8000)      ; .b
+               (set mask #x80000000)) ; .w
+           (set ocbit cbit)
+           (set cbit (and dst mask))
+           (set result (sll mode dst 1))
+           (set result (or result ocbit))
+           (set-z-and-s result)
+           (set dst result))
+)
+; rolc.BW src,dst
+(unary-insn rolc (f-0-4 7) (f-4-3 3) (f-8-4 #xA) #xB #x2 #xE rolc-sem)
+
+;-------------------------------------------------------------
+; rorc - rotate right with carry
+;-------------------------------------------------------------
+
+; TODO check semantics
+; TODO future: split this into .b and .w semantics
+(define-pmacro (rorc-sem mode dst)
+  (sequence ((mode result) (SI ocbit) (mode b_or_w) (USI mask) (SI shamt))
+           (set b_or_w -1)
+           (set b_or_w (srl b_or_w #x8))
+           (if (eq b_or_w #x0)
+               (sequence () (set mask #x7fff) (set shamt 15))     ; .b
+               (sequence () (set mask #x7fffffff) (set shamt 31))) ; .w
+           (set ocbit cbit)
+           (set cbit (and dst #x1))
+           (set result (srl mode dst (const 1)))
+           (set result (or (and result mask) (sll ocbit shamt)))
+           (set-z-and-s result)
+           (set dst result))
+)
+; rorc.BW src,dst
+(unary-insn rorc (f-0-4 7) (f-4-3 3) (f-8-4 #xB) #xA #x2 #xE rorc-sem)
+
+;-------------------------------------------------------------
+; rot - rotate
+;-------------------------------------------------------------
+
+; TODO future: split this into .b and .w semantics
+(define-pmacro (rot-1-sem mode src1 dst)
+  (sequence ((mode tmp) (mode b_or_w) (USI mask) (SI shift))
+           (case DFLT src1
+                 ((#x0) (set shift 1))
+                 ((#x1) (set shift 2))
+                 ((#x2) (set shift 3))
+                 ((#x3) (set shift 4))
+                 ((#x4) (set shift 5))
+                 ((#x5) (set shift 6))
+                 ((#x6) (set shift 7))
+                 ((#x7) (set shift 8))
+                 ((-8) (set shift -1))
+                 ((-7) (set shift -2))
+                 ((-6) (set shift -3))
+                 ((-5) (set shift -4))
+                 ((-4) (set shift -5))
+                 ((-3) (set shift -6))
+                 ((-2) (set shift -7))
+                 ((-1) (set shift -8))
+                 (else (set shift 0))
+                 )
+           (set b_or_w -1)
+           (set b_or_w (srl b_or_w #x8))
+           (if (eq b_or_w #x0)
+               (set mask #x7fff)     ; .b
+               (set mask #x7fffffff)) ; .w
+           (set tmp dst)
+           (if (gt mode shift 0)
+               (sequence ()
+                         (set tmp (rol mode tmp shift))
+                         (set cbit (and tmp #x1)))
+               (sequence ()
+                         (set tmp (ror mode tmp (mul shift -1)))
+                         (set cbit (and tmp mask))))
+           (set-z-and-s tmp)
+           (set dst tmp))
+)
+(define-pmacro (rot-2-sem mode dst)
+  (sequence ((mode tmp) (mode b_or_w) (USI mask))
+           (set b_or_w -1)
+           (set b_or_w (srl b_or_w #x8))
+           (if (eq b_or_w #x0)
+               (set mask #x7fff)     ; .b
+               (set mask #x7fffffff)) ; .w
+           (set tmp dst)
+           (if (gt mode (reg h-r1h) 0)
+               (sequence ()
+                         (set tmp (rol mode tmp (reg h-r1h)))
+                         (set cbit (and tmp #x1)))
+               (sequence ()
+                         (set tmp (ror mode tmp (reg h-r1h)))
+                         (set cbit (and tmp mask))))
+           (set-z-and-s tmp)
+           (set dst tmp))
+)
+
+; rot.BW #imm4,dst
+(binary-arith16-shimm4-dst-defn QI .b 0 0 rot (f-0-4 #xE) (f-4-3 0) rot-1-sem)
+(binary-arith16-shimm4-dst-defn HI .w 0 1 rot (f-0-4 #xE) (f-4-3 0) rot-1-sem)
+(binary-arith32-shimm4-dst-defn QI .b 0 0 rot #x7 #x2 rot-1-sem)
+(binary-arith32-shimm4-dst-defn HI .w 0 1 rot #x7 #x2 rot-1-sem)
+; rot.BW src,dst
+
+(dni rot16.b-dst "rot r1h,dest" ((machine 16))
+     ("rot.b r1h,${dst16-16-QI}")
+     (+ (f-0-4 7) (f-4-4 #x4) (f-8-4 #x6) dst16-16-QI)
+     (rot-2-sem QI dst16-16-QI)
+     ())
+(dni rot16.w-dst "rot r1h,dest" ((machine 16))
+     ("rot.w r1h,${dst16-16-HI}")
+     (+ (f-0-4 7) (f-4-4 #x5) (f-8-4 #x6) dst16-16-HI)
+     (rot-2-sem HI dst16-16-HI)
+     ())
+ 
+(dni rot32.b-dst "rot r1h,dest" ((machine 32))
+     ("rot.b r1h,${dst32-16-Unprefixed-QI}")
+     (+ (f-0-4 #xA) dst32-16-Unprefixed-QI (f-7-1 0) (f-10-2 3) (f-12-4 #xF))
+     (rot-2-sem QI dst32-16-Unprefixed-QI)
+     ())
+(dni rot32.w-dst "rot r1h,dest" ((machine 32))
+     ("rot.w r1h,${dst32-16-Unprefixed-HI}")
+     (+ (f-0-4 #xA) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xF))
+     (rot-2-sem HI dst32-16-Unprefixed-HI)
+     ())
+
+;-------------------------------------------------------------
+; rts - return from subroutine
+;-------------------------------------------------------------
+
+(define-pmacro (rts16-sem)
+  (sequence ((SI tpc))
+           (set tpc (mem16 HI (reg h-sp)))
+           (set (reg h-sp) (add (reg h-sp) 2))
+           (set tpc (or tpc (sll (mem16 QI (reg h-sp)) 16)))
+           (set (reg h-sp) (add (reg h-sp) 1))
+           (set pc tpc)
+           )
+)
+(define-pmacro (rts32-sem)
+  (sequence ((SI tpc))
+           (set tpc (mem32 HI (reg h-sp)))
+           (set (reg h-sp) (add (reg h-sp) 2))
+           (set tpc (or tpc (sll (mem32 HI (reg h-sp)) 16)))
+           (set (reg h-sp) (add (reg h-sp) 2))
+           (set pc tpc)
+           )
+)
+
+(dni rts16 "rts" ((machine 16))
+     ("rts")
+     (+ (f-0-4 #xF) (f-4-4 3))
+     (rts16-sem)
+     ())
+
+(dni rts32 "rts" ((machine 32))
+     ("rts")
+     (+ (f-0-4 #xD) (f-4-4 #xF))
+     (rts32-sem)
+     ())
+
+;-------------------------------------------------------------
+; sbb - subtract with borrow
+;-------------------------------------------------------------
+
+(define-pmacro (sbb-sem mode src dst)
+  (sequence ((mode result))
+           (set result (subc mode dst src cbit))
+           (set obit (add-oflag mode dst src cbit))
+           (set cbit (add-oflag mode dst src cbit))
+           (set-z-and-s result)
+           (set dst result))
+)
+
+; sbb.size:G #imm,dst
+(binary-arith16-imm-dst-defn QI QI .b 0 sbb X (f-0-4 7) (f-4-3 3) (f-8-4 7) sbb-sem)
+(binary-arith16-imm-dst-defn HI HI .w 1 sbb X (f-0-4 7) (f-4-3 3) (f-8-4 7) sbb-sem)
+(binary-arith32-imm-dst-Prefixed QI QI .b 0 sbb X #x9 #x2 #xE sbb-sem)
+(binary-arith32-imm-dst-Prefixed HI HI .w 1 sbb X #x9 #x2 #xE sbb-sem)
+
+; sbb.BW:G src,dst
+(binary-arith16-src-dst-defn QI QI .b 0 sbb X (f-0-4 #xB) (f-4-3 4) sbb-sem)
+(binary-arith16-src-dst-defn HI HI .w 1 sbb X (f-0-4 #xB) (f-4-3 4) sbb-sem)
+(binary-arith32-src-dst-Prefixed QI QI .b 0 sbb X #x1 #x6 sbb-sem)
+(binary-arith32-src-dst-Prefixed HI HI .w 1 sbb X #x1 #x6 sbb-sem)
+
+;-------------------------------------------------------------
+; sbjnz - subtract then jump on not zero
+;-------------------------------------------------------------
+
+(define-pmacro (sub-jnz-sem mode src dst label)
+  (sequence ((mode result))
+           (set result (sub mode dst src))
+           (set dst result)
+           (if (ne result 0)
+               (set pc label)))
+)
+
+; sbjnz.size #imm4,dst,label
+(arith-jnz-imm4-dst sbjnz s4n (f-0-4 #xF) (f-4-3 4) #xf #x1 sub-jnz-sem)
+
+;-------------------------------------------------------------
+; sccnd - store condition on condition (m32)
+;-------------------------------------------------------------
+
+(define-pmacro (sccnd-sem cnd dst)
+  (sequence ()
+           (set dst 0)
+           (case DFLT cnd
+                 ((#x00) (if (not cbit) (set dst 1))) ;ltu nc
+                 ((#x01) (if (or cbit zbit) (set dst 1))) ;leu
+                 ((#x02) (if (not zbit) (set dst 1))) ;ne nz
+                 ((#x03) (if (not sbit) (set dst 1))) ;pz
+                 ((#x04) (if (not obit) (set dst 1))) ;no
+                 ((#x05) (if (not (or zbit (xor sbit obit))) (set dst 1))) ;gt
+                 ((#x06) (if (xor sbit obit) (set dst 1))) ;ge
+                 ((#x08) (if (trunc BI cbit) (set dst 1))) ;geu c
+                 ((#x09) (if (not (or cbit zbit)) (set dst 1))) ;gtu
+                 ((#x0a) (if (trunc BI zbit) (set dst 1))) ;eq z
+                 ((#x0b) (if (trunc BI sbit) (set dst 1))) ;n
+                 ((#x0c) (if (trunc BI obit) (set dst 1))) ;o
+                 ((#x0d) (if (or zbit (xor sbit obit)) (set dst 1))) ;le
+                 ((#x0e) (if (xor sbit obit) (set dst 1))) ;lt
+                 )
+       )
+  )
+
+; scCND dst
+(dni sccnd
+     "sccnd dst"
+     ((machine 32))
+     "sc$sccond32 ${dst32-16-Unprefixed-HI}"
+     (+ (f-0-4 #xD) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) sccond32)
+     (sccnd-sem sccond32 dst32-16-Unprefixed-HI)
+     ())
+
+;-------------------------------------------------------------
+; scmpu - string compare unequal (m32)
+;-------------------------------------------------------------
+
+; TODO semantics
+(dni scmpu.b "scmpu.b" ((machine 32))
+     ("scmpu.b")
+     (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 #xC) (f-12-4 3))
+     (c-call VOID "scmpu_QI_semantics")
+     ())
+
+(dni scmpu.w "scmpu.w" ((machine 32))
+     ("scmpu.w")
+     (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 #xD) (f-12-4 3))
+     (c-call VOID "scmpu_HI_semantics")
+     ())
+
+;-------------------------------------------------------------
+; sha - shift arithmetic
+;-------------------------------------------------------------
+
+; TODO future: split this into .b and .w semantics
+(define-pmacro (sha-sem mode src1 dst)
+  (sequence ((mode result)(mode shift)(mode shmode))
+            (case DFLT src1
+                  ((#x0) (set shift 1))
+                  ((#x1) (set shift 2))
+                  ((#x2) (set shift 3))
+                  ((#x3) (set shift 4))
+                  ((#x4) (set shift 5))
+                  ((#x5) (set shift 6))
+                  ((#x6) (set shift 7))
+                  ((#x7) (set shift 8))
+                  ((-8) (set shift -1))
+                  ((-7) (set shift -2))
+                  ((-6) (set shift -3))
+                  ((-5) (set shift -4))
+                  ((-4) (set shift -5))
+                  ((-3) (set shift -6))
+                  ((-2) (set shift -7))
+                  ((-1) (set shift -8))
+                  (else (set shift 0))
+                  )
+            (set shmode -1)
+            (set shmode (srl shmode #x8))
+            (if (lt mode shift #x0) (set result (sra mode dst (mul shift -1))))
+            (if (gt mode shift 0) (set result (sll mode dst shift)))
+            (if (eq shmode #x0) ; QI
+                (sequence
+                  ((mode cbitamt))
+                   (if (lt mode shift #x0)
+                       (set cbitamt (sub #x8 shift)) ; sra
+                       (set cbitamt (sub shift 1)))  ; sll
+                   (set cbit (srl (and (sll dst cbitamt) #x80) #x7))
+                   (set obit (ne (and dst #x80) (and result #x80)))
+                   ))
+            (if (eq shmode #xff) ; HI
+                (sequence
+                  ((mode cbitamt))
+                   (if (lt mode shift #x0)
+                       (set cbitamt (sub 16 shift)) ; sra
+                       (set cbitamt (sub shift 1))) ; sll
+                   (set cbit (srl (and (sll dst cbitamt) #x8000) #xf))
+                   (set obit (ne (and dst #x8000) (and result #x8000)))
+                   ))
+           (set-z-and-s result)
+           (set dst result))
+)
+(define-pmacro (shar1h-sem mode dst)
+  (sequence ((mode result)(mode shmode))
+            (set shmode -1)
+            (set shmode (srl shmode #x8))
+            (if (lt mode (reg h-r1h) 0) (set result (sra mode dst (reg h-r1h))))
+            (if (gt mode (reg h-r1h) 0) (set result (sll mode dst (reg h-r1h))))
+            (if (eq shmode #x0) ; QI
+                (sequence
+                  ((mode cbitamt))
+                   (if (lt mode (reg h-r1h) #x0)
+                       (set cbitamt (sub #x8 (reg h-r1h))) ; sra
+                       (set cbitamt (sub (reg h-r1h) 1)))  ; sll
+                   (set cbit (srl (and (sll dst cbitamt) #x80) #x7))
+                   (set obit (ne (and dst #x80) (and result #x80)))
+                   ))
+            (if (eq shmode #xff) ; HI
+                (sequence
+                  ((mode cbitamt))
+                   (if (lt mode (reg h-r1h) #x0)
+                       (set cbitamt (sub 16 (reg h-r1h))) ; sra
+                       (set cbitamt (sub (reg h-r1h) 1))) ; sll
+                   (set cbit (srl (and (sll dst cbitamt) #x8000) #xf))
+                   (set obit (ne (and dst #x8000) (and result #x8000)))
+                   ))
+           (set-z-and-s result)
+           (set dst result))
+)
+; sha.BW #imm4,dst (m16 #1 m32 #1)
+(binary-arith16-shimm4-dst-defn QI .b 0 0 sha (f-0-4 #xF) (f-4-3 0) sha-sem)
+(binary-arith16-shimm4-dst-defn HI .w 0 1 sha (f-0-4 #xF) (f-4-3 0) sha-sem)
+(binary-arith32-shimm4-dst-defn QI .b 1 0 sha #x7 #x0 sha-sem)
+(binary-arith32-shimm4-dst-defn HI .w 1 1 sha #x7 #x0 sha-sem)
+; sha.BW r1h,dst (m16 #2 m32 #3)
+(dni sha16.b-dst "sha.b r1h,dest" ((machine 16))
+     ("sha.b r1h,${dst16-16-QI}")
+     (+ (f-0-4 7) (f-4-4 4) (f-8-4 #xF) dst16-16-QI)
+     (shar1h-sem HI dst16-16-QI)
+     ())
+(dni sha16.w-dst "sha.w r1h,dest" ((machine 16))
+     ("sha.w r1h,${dst16-16-HI}")
+     (+ (f-0-4 7) (f-4-4 5) (f-8-4 #xF) dst16-16-HI)
+     (shar1h-sem HI dst16-16-HI)
+     ())
+(dni sha32.b-dst "sha.b r1h,dest" ((machine 32))
+     ("sha.b r1h,${dst32-16-Unprefixed-QI}")
+     (+ (f-0-4 #xB) dst32-16-Unprefixed-QI (f-7-1 0) (f-10-2 3) (f-12-4 #xE))
+     (shar1h-sem QI dst32-16-Unprefixed-QI)
+     ())
+(dni sha32.w-dst "sha.w r1h,dest" ((machine 32))
+     ("sha.w r1h,${dst32-16-Unprefixed-HI}")
+     (+ (f-0-4 #xB) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xE))
+     (shar1h-sem HI dst32-16-Unprefixed-HI)
+     ())
+; sha.L #imm,dst (m16 #3)
+(dni sha16-L-imm-r2r0 "sha.L #Imm-sh-12-s4,r2r0" ((machine 16))
+     "sha.l #${Imm-sh-12-s4},r2r0"
+     (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #xA) Imm-sh-12-s4)
+     (sha-sem SI Imm-sh-12-s4 (reg h-r2r0))
+     ())
+(dni sha16-L-imm-r3r1 "sha.L #Imm-sh-12-s4,r3r1" ((machine 16))
+     "sha.l #${Imm-sh-12-s4},r3r1"
+     (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #xB) Imm-sh-12-s4)
+     (sha-sem SI Imm-sh-12-s4 (reg h-r3r1))
+     ())
+; sha.L r1h,dst (m16 #4)
+(dni sha16-L-r1h-r2r0 "sha.L r1h,r2r0" ((machine 16))
+     "sha.l r1h,r2r0"
+     (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 2) (f-12-4 1))
+     (sha-sem SI (reg h-r1h) (reg h-r2r0))
+     ())
+(dni sha16-L-r1h-r3r1 "sha.L r1h,r3r1" ((machine 16))
+     "sha.l r1h,r3r1"
+     (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 3) (f-12-4 1))
+     (sha-sem SI (reg h-r1h) (reg h-r3r1))
+     ())
+; sha.L #imm8,dst (m32 #2)
+(binary-arith32-imm-dst-defn QI SI .l 0 sha X #xA #x2 #x1 sha-sem)
+; sha.L r1h,dst (m32 #4)
+(dni sha32.l-dst "sha.l r1h,dest" ((machine 32))
+     ("sha.l r1h,${dst32-16-Unprefixed-SI}")
+     (+ (f-0-4 #xC) dst32-16-Unprefixed-SI (f-7-1 0) (f-10-2 1) (f-12-4 1))
+     (shar1h-sem QI dst32-16-Unprefixed-SI)
+     ())
+
+;-------------------------------------------------------------
+; shanc - shift arithmetic non carry (m32)
+;-------------------------------------------------------------
+
+; TODO check semantics
+; shanc.L #imm8,dst
+(binary-arith32-imm-dst-defn QI SI .l 0 shanc X #xC #x2 #x1 sha-sem)
+
+;-------------------------------------------------------------
+; shl - shift logical
+;-------------------------------------------------------------
+
+; TODO future: split this into .b and .w semantics
+(define-pmacro (shl-sem mode src1 dst)
+  (sequence ((mode result)(mode shift)(mode shmode))
+           (case DFLT src1
+                 ((#x0) (set shift 1))
+                 ((#x1) (set shift 2))
+                 ((#x2) (set shift 3))
+                 ((#x3) (set shift 4))
+                 ((#x4) (set shift 5))
+                 ((#x5) (set shift 6))
+                 ((#x6) (set shift 7))
+                 ((#x7) (set shift 8))
+                 ((-8) (set shift -1))
+                 ((-7) (set shift -2))
+                 ((-6) (set shift -3))
+                 ((-5) (set shift -4))
+                 ((-4) (set shift -5))
+                 ((-3) (set shift -6))
+                 ((-2) (set shift -7))
+                 ((-1) (set shift -8))
+                 (else (set shift 0))
+                 )
+           (set shmode -1)
+           (set shmode (srl shmode #x8))
+           (if (lt mode shift #x0) (set result (srl mode dst (mul shift -1))))
+           (if (gt mode shift 0) (set result (sll mode dst shift)))
+           (if (eq shmode #x0) ; QI
+               (sequence
+                 ((mode cbitamt))
+                 (if (lt mode shift #x0)
+                     (set cbitamt (sub #x8 shift)); srl
+                     (set cbitamt (sub shift 1))) ; sll
+                 (set cbit (srl (and (sll dst cbitamt) #x80) #x7))
+                 (set obit (ne (and dst #x80) (and result #x80)))
+                 ))
+           (if (eq shmode #xff) ; HI
+               (sequence
+                 ((mode cbitamt))
+                 (if (lt mode shift #x0)
+                     (set cbitamt (sub 16 shift)) ; srl
+                     (set cbitamt (sub shift 1))) ; sll
+                 (set cbit (srl (and (sll dst cbitamt) #x8000) #xf))
+                 (set obit (ne (and dst #x8000) (and result #x8000)))
+                 ))
+           (set-z-and-s result)
+           (set dst result))
+  )
+(define-pmacro (shlr1h-sem mode dst)
+  (sequence ((mode result)(mode shmode))
+           (set shmode -1)
+           (set shmode (srl shmode #x8))
+           (if (lt mode (reg h-r1h) 0) (set result (srl mode dst (reg h-r1h))))
+           (if (gt mode (reg h-r1h) 0) (set result (sll mode dst (reg h-r1h))))
+           (if (eq shmode #x0) ; QI
+               (sequence
+                 ((mode cbitamt))
+                 (if (lt mode (reg h-r1h) #x0)
+                     (set cbitamt (sub #x8 (reg h-r1h))) ; srl
+                     (set cbitamt (sub (reg h-r1h) 1)))  ; sll
+                 (set cbit (srl (and (sll dst cbitamt) #x80) #x7))
+                 (set obit (ne (and dst #x80) (and result #x80)))
+                 ))
+           (if (eq shmode #xff) ; HI
+               (sequence
+                 ((mode cbitamt))
+                 (if (lt mode (reg h-r1h) #x0)
+                     (set cbitamt (sub 16 (reg h-r1h))) ; srl
+                     (set cbitamt (sub (reg h-r1h) 1))) ; sll
+                 (set cbit (srl (and (sll dst cbitamt) #x8000) #xf))
+                 (set obit (ne (and dst #x8000) (and result #x8000)))
+                 ))
+           (set-z-and-s result)
+           (set dst result))
+  )
+; shl.BW #imm4,dst (m16 #1 m32 #1)
+(binary-arith16-shimm4-dst-defn QI .b 0 0 shl (f-0-4 #xE) (f-4-3 4) shl-sem)
+(binary-arith16-shimm4-dst-defn HI .w 0 1 shl (f-0-4 #xE) (f-4-3 4) shl-sem)
+(binary-arith32-shimm4-dst-defn QI .b 0 0 shl #x7 #x0 shl-sem)
+(binary-arith32-shimm4-dst-defn HI .w 0 1 shl #x7 #x0 shl-sem)
+; shl.BW r1h,dst (m16 #2 m32 #3)
+(dni shl16.b-dst "shl.b r1h,dest" ((machine 16))
+     ("shl.b r1h,${dst16-16-QI}")
+     (+ (f-0-4 7) (f-4-4 4) (f-8-4 #xE) dst16-16-QI)
+     (shlr1h-sem HI dst16-16-QI)
+     ())
+(dni shl16.w-dst "shl.w r1h,dest" ((machine 16))
+     ("shl.w r1h,${dst16-16-HI}")
+     (+ (f-0-4 7) (f-4-4 5) (f-8-4 #xE) dst16-16-HI)
+     (shlr1h-sem HI dst16-16-HI)
+     ())
+(dni shl32.b-dst "shl.b r1h,dest" ((machine 32))
+     ("shl.b r1h,${dst32-16-Unprefixed-QI}")
+     (+ (f-0-4 #xA) dst32-16-Unprefixed-QI (f-7-1 0) (f-10-2 3) (f-12-4 #xE))
+     (shlr1h-sem QI dst32-16-Unprefixed-QI)
+     ())
+(dni shl32.w-dst "shl.w r1h,dest" ((machine 32))
+     ("shl.w r1h,${dst32-16-Unprefixed-HI}")
+     (+ (f-0-4 #xA) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xE))
+     (shlr1h-sem HI dst32-16-Unprefixed-HI)
+     ())
+; shl.L #imm,dst (m16 #3)
+(dni shl16-L-imm-r2r0 "shl.L #Imm-sh-12-s4,r2r0" ((machine 16))
+     "shl.l #${Imm-sh-12-s4},r2r0"
+     (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #x8) Imm-sh-12-s4)
+     (shl-sem SI Imm-sh-12-s4 (reg h-r2r0))
+     ())
+(dni shl16-L-imm-r3r1 "shl.L #Imm-sh-12-s4,r3r1" ((machine 16))
+     "shl.l #${Imm-sh-12-s4},r3r1"
+     (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #x9) Imm-sh-12-s4)
+     (shl-sem SI Imm-sh-12-s4 (reg h-r3r1))
+     ())
+; shl.L r1h,dst (m16 #4)
+(dni shl16-L-r1h-r2r0 "shl.L r1h,r2r0" ((machine 16))
+     "shl.l r1h,r2r0"
+     (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 0) (f-12-4 1))
+     (shl-sem SI (reg h-r1h) (reg h-r2r0))
+     ())
+(dni shl16-L-r1h-r3r1 "shl.L r1h,r3r1" ((machine 16))
+     "shl.l r1h,r3r1"
+     (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 1) (f-12-4 1))
+     (shl-sem SI (reg h-r1h) (reg h-r3r1))
+     ())
+; shl.L #imm8,dst (m32 #2)
+(binary-arith32-imm-dst-defn QI SI .l 0 shl X #x9 #x2 #x1 shl-sem)
+; shl.L r1h,dst (m32 #4)
+(dni shl32.l-dst "shl.l r1h,dest" ((machine 32))
+     ("shl.l r1h,${dst32-16-Unprefixed-SI}")
+     (+ (f-0-4 #xC) dst32-16-Unprefixed-SI (f-7-1 0) (f-10-2 0) (f-12-4 1))
+     (shlr1h-sem QI dst32-16-Unprefixed-SI)
+     ())
+
+;-------------------------------------------------------------
+; shlnc - shift logical non carry
+;-------------------------------------------------------------
+
+; TODO check semantics
+; shlnc.L #imm8,dst
+(binary-arith32-imm-dst-defn QI SI .l 0 shlnc X #x8 #x2 #x1 shl-sem)
+
+;-------------------------------------------------------------
+; sin - string input (m32)
+;-------------------------------------------------------------
+
+; TODO semantics
+(dni sin32.b "sin" ((machine 32))
+     ("sin.b")
+     (+ (f-0-4 #xB) (f-4-4 2) (f-8-4 8) (f-12-4 3))
+     (c-call VOID "sin_QI_semantics")
+     ())
+
+(dni sin32.w "sin" ((machine 32))
+     ("sin.w")
+     (+ (f-0-4 #xB) (f-4-4 2) (f-8-4 9) (f-12-4 3))
+     (c-call VOID "sin_HI_semantics")
+     ())
+
+;-------------------------------------------------------------
+; smovb - string move backward
+;-------------------------------------------------------------
+
+; TODO semantics
+(dni smovb16.b "smovb.b" ((machine 16))
+     ("smovb.b")
+     (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 9))
+     (c-call VOID "smovb_QI_semantics")
+     ())
+ 
+(dni smovb16.w "smovb.w" ((machine 16))
+     ("smovb.w")
+     (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 9))
+     (c-call VOID "smovb_HI_semantics")
+     ())
+
+(dni smovb32.b "smovb.b" ((machine 32))
+     ("smovb.b")
+     (+ (f-0-4 #xB) (f-4-4 6) (f-8-4 8) (f-12-4 3))
+     (c-call VOID "smovb_QI_semantics")
+     ())
+
+(dni smovb32.w "smovb.w" ((machine 32))
+     ("smovb.w")
+     (+ (f-0-4 #xB) (f-4-4 6) (f-8-4 9) (f-12-4 3))
+     (c-call VOID "smovb_HI_semantics")
+     ())
+
+;-------------------------------------------------------------
+; smovf - string move forward (m32)
+;-------------------------------------------------------------
+
+; TODO semantics
+(dni smovf16.b "smovf.b" ((machine 16))
+     ("smovf.b")
+     (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 8))
+     (c-call VOID "smovf_QI_semantics")
+     ())
+
+(dni smovf16.w "smovf.w" ((machine 16))
+     ("smovf.w")
+     (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 8))
+     (c-call VOID "smovf_HI_semantics")
+     ())
+
+(dni smovf32.b "smovf.b" ((machine 32))
+     ("smovf.b")
+     (+ (f-0-4 #xB) (f-4-4 0) (f-8-4 8)  (f-12-4 3))
+     (c-call VOID "smovf_QI_semantics")
+     ())
+
+(dni smovf32.w "smovf.w" ((machine 32))
+     ("smovf.w")
+     (+ (f-0-4 #xB) (f-4-4 0) (f-8-4 9)  (f-12-4 3))
+     (c-call VOID "smovf_HI_semantics")
+     ())
+
+;-------------------------------------------------------------
+; smovu - string move unequal (m32)
+;-------------------------------------------------------------
+
+; TODO semantics
+(dni smovu.b "smovu.b" ((machine 32))
+     ("smovu.b")
+     (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 8)  (f-12-4 3))
+     (c-call VOID "smovu_QI_semantics")
+     ())
+
+(dni smovu.w "smovu.w" ((machine 32))
+     ("smovu.w")
+     (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 9)  (f-12-4 3))
+     (c-call VOID "smovu_HI_semantics")
+     ())
+
+;-------------------------------------------------------------
+; sout - string output (m32)
+;-------------------------------------------------------------
+
+; TODO semantics
+(dni sout.b "sout.b" ((machine 32))
+     ("sout.b")
+     (+ (f-0-4 #xB) (f-4-4 4) (f-8-4 8) (f-12-4 3))
+     (c-call VOID "sout_QI_semantics")
+     ())
+
+(dni sout.w "sout" ((machine 32))
+     ("sout.w")
+     (+ (f-0-4 #xB) (f-4-4 4) (f-8-4 9) (f-12-4 3))
+     (c-call VOID "sout_HI_semantics")
+     ())
+
+;-------------------------------------------------------------
+; sstr - string store
+;-------------------------------------------------------------
+
+; TODO semantics
+(dni sstr16.b "sstr.b" ((machine 16))
+     ("sstr.b")
+     (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 #xA))
+     (c-call VOID "sstr_QI_semantics")
+     ())
+
+(dni sstr16.w "sstr.w" ((machine 16))
+     ("sstr.w")
+     (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 #xA))
+     (c-call VOID "sstr_HI_semantics")
+     ())
+
+(dni sstr.b "sstr" ((machine 32))
+     ("sstr.b")
+     (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 0) (f-12-4 3))
+     (c-call VOID "sstr_QI_semantics")
+     ())
+
+(dni sstr.w "sstr" ((machine 32))
+     ("sstr.w")
+     (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 1) (f-12-4 3))
+     (c-call VOID "sstr_HI_semantics")
+     ())
+
+;-------------------------------------------------------------
+; stnz - store on not zero
+;-------------------------------------------------------------
+
+(define-pmacro (stnz-sem mode src dst)
+  (sequence ()
+           (if (ne zbit (const 1))
+               (set dst src)))
+)
+; stnz #imm8,dst3 (m16)
+(binary-arith16-b-S-imm8-dst3 stnz "" (f-0-4 #xD) (f-4-1 0) stnz-sem)
+; stnz.BW #imm,dst (m32)
+(binary-arith32-imm-dst-defn QI QI .b 0 stnz X #x9 #x1 #xF stnz-sem)
+(binary-arith32-imm-dst-defn HI HI .w 1 stnz X #x9 #x1 #xF stnz-sem)
+
+;-------------------------------------------------------------
+; stz - store on zero
+;-------------------------------------------------------------
+
+(define-pmacro (stz-sem mode src dst)
+  (sequence ()
+           (if (eq zbit (const 1))
+               (set dst src)))
+)
+; stz #imm8,dst3 (m16)
+(binary-arith16-b-S-imm8-dst3 stz "" (f-0-4 #xC) (f-4-1 1) stz-sem)
+; stz.BW #imm,dst (m32)
+(binary-arith32-imm-dst-defn QI QI .b 0 stz X #x9 #x0 #xF stz-sem)
+(binary-arith32-imm-dst-defn HI HI .w 1 stz X #x9 #x0 #xF stz-sem)
+
+;-------------------------------------------------------------
+; stzx - store on zero extention
+;-------------------------------------------------------------
+
+(define-pmacro (stzx-sem mode src1 src2 dst)
+  (sequence ()
+           (if (eq zbit (const 1))
+               (set dst src1)
+               (set dst src2)))
+  )
+; stzx #imm8,dst3 (m16)
+(dni stzx16-imm8-imm8-r0h "stzx #Imm8,#Imm8,r0h" ((machine 16))
+     ("stzx #${Imm-8-QI},#${Imm-16-QI},r0h")
+     (+ (f-0-4 #xD) (f-4-4 #xB) Imm-8-QI Imm-16-QI)
+     (stzx-sem QI Imm-8-QI Imm-16-QI (reg h-r0h))
+     ())
+(dni stzx16-imm8-imm8-r0l "stzx #Imm8,#Imm8,r0l" ((machine 16))
+     ("stzx #${Imm-8-QI},#${Imm-16-QI},r0l")
+     (+ (f-0-4 #xD) (f-4-4 #xC) Imm-8-QI Imm-16-QI)
+     (stzx-sem QI Imm-8-QI Imm-16-QI (reg h-r0l))
+     ())
+(dni stzx16-imm8-imm8-dsp8sb "stzx #Imm8,#Imm8,dsp8[sb]" ((machine 16))
+     ("stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-u8}[sb]")
+     (+ (f-0-4 #xD) (f-4-4 #xD) Imm-8-QI Dsp-16-u8 Imm-24-QI)
+     (stzx-sem QI Imm-8-QI Imm-16-QI (mem16 QI (add (reg h-sb) Dsp-24-u8)))
+     ())
+(dni stzx16-imm8-imm8-dsp8fb "stzx #Imm8,#Imm8,dsp8[fb]" ((machine 16))
+     ("stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-s8}[fb]")
+     (+ (f-0-4 #xD) (f-4-4 #xE) Imm-8-QI Dsp-16-s8 Imm-24-QI)
+     (stzx-sem QI Imm-8-QI Imm-24-QI (mem16 QI (add (reg h-fb) Dsp-16-s8)))
+     ())
+(dni stzx16-imm8-imm8-abs16 "stzx #Imm8,#Imm8,abs16" ((machine 16))
+     ("stzx #${Imm-8-QI},#${Imm-32-QI},${Dsp-16-u16}")
+     (+ (f-0-4 #xD) (f-4-4 #xF) Imm-8-QI Dsp-16-u16 Imm-32-QI)
+     (stzx-sem QI Imm-8-QI Imm-32-QI (mem16 QI Dsp-16-u16))
+     ())
+; stzx.BW #imm,dst (m32)
+(insn-imm1-imm2-dst-Unprefixed stzx #x9 #x3 #xF stzx-sem)
+
+;-------------------------------------------------------------
+; subx - subtract extend (m32)
+;-------------------------------------------------------------
+
+(define-pmacro (subx-sem mode src1 dst)
+  (sequence ((mode result))
+           (set result (sub mode dst (ext mode src1)))
+           (set obit (sub-oflag mode dst (ext mode src1) 0))
+           (set cbit (sub-cflag mode dst (ext mode src1) 0))
+           (set dst result)
+           (set-z-and-s result)))
+; subx #imm8,dst
+(binary-arith32-imm-dst-defn QI SI "" 0 subx G #x9 #x1 #x1 subx-sem)
+; subx src,dst
+(binary-arith32-src-dst-defn QI SI "" 0 subx G #x1 #x0 subx-sem)
+
+;-------------------------------------------------------------
+; tst - test
+;-------------------------------------------------------------
+
+(define-pmacro (tst-sem mode src1 dst)
+  (sequence ((mode result))
+           (set result (and mode dst src1))
+           (set-z-and-s result))
+)
+
+; tst.BW #imm,dst (m16 #1 m32 #1)
+(binary-arith-imm-dst tst G (f-0-4 7) (f-4-3 3) (f-8-4 0) #x9 #x3 #xE tst-sem)
+; tst.BW src,dst (m16 #2 m32 #3)
+(binary-arith16-src-dst-defn QI QI .b 0 tst X (f-0-4 #x8) (f-4-3 0) tst-sem)
+(binary-arith16-src-dst-defn HI HI .w 1 tst X (f-0-4 #x8) (f-4-3 0) tst-sem)
+(binary-arith32-src-dst-Prefixed QI QI .b 0 tst G #x1 #x9 tst-sem)
+(binary-arith32-src-dst-Prefixed HI HI .w 1 tst G #x1 #x9 tst-sem)
+; tst.BW:S #imm,dst2 (m32 #2)
+(binary-arith32-s-imm-dst QI .b 0 tst #x0 #x6 tst-sem)
+(binary-arith32-s-imm-dst HI .w 1 tst #x0 #x6 tst-sem)
+
+;-------------------------------------------------------------
+; und - undefined
+;-------------------------------------------------------------
+
+(dni und16 "und" ((machine 16))
+     ("und")
+     (+ (f-0-4 #xF) (f-4-4 #xF))
+     (nop)
+     ())
+
+(dni und32 "und" ((machine 32))
+     ("und")
+     (+ (f-0-4 #xF) (f-4-4 #xF))
+     (nop)
+     ())
+
+;-------------------------------------------------------------
+; wait
+;-------------------------------------------------------------
+
+; ??? semantics
+(dni wait16 "wait" ((machine 16))
+     ("wait")
+     (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 3))
+     (nop)
+     ())
+
+(dni wait "wait" ((machine 32))
+     ("wait")
+     (+ (f-0-4 #xB) (f-4-4 2) (f-8-4 0) (f-12-4 3))
+     (nop)
+     ())
+
+;-------------------------------------------------------------
+; xchg - exchange
+;-------------------------------------------------------------
+
+(define-pmacro (xchg-sem mode src dst)
+  (sequence ((mode result))
+           (set result src)
+           (set src dst)
+           (set dst result))
+  )
+(define-pmacro (xchg16-defn mode sz szc src srcreg)
+  (dni (.sym xchg16 sz - srcreg)
+       (.str "xchg" sz "-" srcreg ",dst16-16-" mode)
+       ((machine 16))
+       (.str "xchg." sz " " srcreg ",${dst16-16-" mode "}")
+       (+ (f-0-4 #x7) (f-4-3 #x5) (f-7-1 szc) (f-8-2 0) (f-10-2 src) (.sym dst16-16- mode))
+       (xchg-sem mode (reg (.sym h- srcreg)) (.sym dst16-16- mode))
+       ())
+)
+(xchg16-defn QI b 0 0 r0l)
+(xchg16-defn QI b 0 1 r0h)
+(xchg16-defn QI b 0 2 r1l)
+(xchg16-defn QI b 0 3 r1h)
+(xchg16-defn HI w 1 0 r0)
+(xchg16-defn HI w 1 1 r1)
+(xchg16-defn HI w 1 2 r2)
+(xchg16-defn HI w 1 3 r3)
+(define-pmacro (xchg32-defn mode sz szc src srcreg)
+  (dni (.sym xchg32 sz - srcreg)
+       (.str "xchg" sz "-" srcreg ",dst32-16-Unprefixed-" mode)
+       ((machine 32))
+       (.str "xchg." sz " " srcreg ",${dst32-16-Unprefixed-" mode "}")
+       (+ (f-0-4 #xD) (.sym dst32-16-Unprefixed- mode) (f-7-1 szc) (f-10-2 0) (f-12-1 1) (f-13-3 src))
+       (xchg-sem mode (reg (.sym h- srcreg)) (.sym dst32-16-Unprefixed- mode))
+       ())
+) 
+(xchg32-defn QI b 0 0 r0l)
+(xchg32-defn QI b 0 1 r1l)
+(xchg32-defn QI b 0 2 a0)
+(xchg32-defn QI b 0 3 a1)
+(xchg32-defn QI b 0 4 r0h)
+(xchg32-defn QI b 0 5 r1h)
+(xchg32-defn HI w 1 0 r0)
+(xchg32-defn HI w 1 1 r1)
+(xchg32-defn HI w 1 2 a0)
+(xchg32-defn HI w 1 3 a1)
+(xchg32-defn HI w 1 4 r2)
+(xchg32-defn HI w 1 5 r3)
+
+;-------------------------------------------------------------
+; xor - exclusive or
+;-------------------------------------------------------------
+
+(define-pmacro (xor-sem mode src1 dst)
+  (sequence ((mode result))
+           (set result (xor mode src1 dst))
+           (set-z-and-s result)
+           (set dst result))
+)
+
+; xor.BW #imm,dst (m16 #1 m32 #1)
+(binary-arith-imm-dst xor G (f-0-4 7) (f-4-3 3) (f-8-4 1) #x9 #x0 #xE xor-sem)
+; xor.BW src,dst (m16 #3 m32 #3)
+(binary-arith-src-dst xor G (f-0-4 #x8) (f-4-3 4) #x1 #x9 xor-sem)
+
+;-------------------------------------------------------------
+; Widening
+;-------------------------------------------------------------
+
+(define-pmacro (exts-sem smode dmode src dst)
+  (set dst (ext dmode (trunc smode src)))
+)
+(define-pmacro (extz-sem smode dmode src dst)
+  (set dst (zext dmode (trunc smode src)))
+)
+
+; exts.b dst for m16c
+(ext16-defn QI HI .b 0 exts (f-0-4 7) (f-4-3 6) (f-8-4 6) exts-sem)
+
+; exts.w r0 for m16c
+(dni exts16.w-r0
+     "exts.w r0"
+     ((machine 16))
+     "exts.w r0"
+     (+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 3))
+     (exts-sem HI SI R0 R2R0)
+     ())
+
+; exts.size dst for m32c
+(ext32-defn QI HI .b 0 exts (f-0-4 #xC) (f-10-2 1) (f-12-4 #xE) exts-sem)
+(ext32-defn HI SI .w 1 exts (f-0-4 #xC) (f-10-2 1) (f-12-4 #xE) exts-sem)
+; exts.b src,dst for m32c
+(ext32-binary-defn exts .b #x1 #x7 exts-sem)
+
+; extz.b src,dst for m32c
+(ext32-binary-defn extz "" #x1 #xB extz-sem)
+
+;-------------------------------------------------------------
+; Indirect
+;-------------------------------------------------------------
+ 
+; TODO semantics
+(dni srcind "SRC-INDIRECT" ((machine 32))
+     ("src-indirect")
+     (+ (f-0-4 4) (f-4-4 1))
+     (set (reg h-src-indirect) 1)
+     ())
+ 
+(dni destind "DEST-INDIRECT" ((machine 32))
+     ("dest-indirect")
+     (+ (f-0-4 0) (f-4-4 9))
+     (set (reg h-dst-indirect) 1)
+     ())
+ 
+(dni srcdestind "SRC-DEST-INDIRECT" ((machine 32))
+     ("src-dest-indirect")
+     (+ (f-0-4 4) (f-4-4 9))
+     (sequence () (set (reg h-src-indirect) 1) (set (reg h-dst-indirect) 1))
+     ())

diff --git a/cpu/m32c.opc b/cpu/m32c.opc
new file mode 100644 (file)
index 0000000..40c3075
--- /dev/null
+++ b/cpu/m32c.opc
@@ -0,0 +1,1187 @@
+/* m32c opcode support.  -*- C -*-
+
+   Copyright 2005, 2007, 2009 Free Software Foundation, Inc.
+
+   Contributed by Red Hat Inc; developed under contract from Renesas
+
+   This file is part of the GNU Binutils.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+
+/* This file is an addendum to m32c.cpu.  Heavy use of C code isn't
+   appropriate in .cpu files, so it resides here.  This especially applies
+   to assembly/disassembly where parsing/printing can be quite involved.
+   Such things aren't really part of the specification of the cpu, per se,
+   so .cpu files provide the general framework and .opc files handle the
+   nitty-gritty details as necessary.
+
+   Each section is delimited with start and end markers.
+
+   <arch>-opc.h additions use: "-- opc.h"
+   <arch>-opc.c additions use: "-- opc.c"
+   <arch>-asm.c additions use: "-- asm.c"
+   <arch>-dis.c additions use: "-- dis.c"
+   <arch>-ibd.h additions use: "-- ibd.h".  */
+\f
+/* -- opc.h */
+
+/* Needed for RTL's 'ext' and 'trunc' operators.  */
+#include "cgen-types.h"
+#include "cgen-ops.h"
+
+/* We can't use the default hash size because many bits are used by
+   operands.  */
+#define CGEN_DIS_HASH_SIZE 1
+#define CGEN_DIS_HASH(buf, value) 0
+#define CGEN_VERBOSE_ASSEMBLER_ERRORS
+#define CGEN_VALIDATE_INSN_SUPPORTED
+
+extern int m32c_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
+
+#define CGEN_ASM_HASH_SIZE 0xffff
+#define CGEN_ASM_HASH(mnem) m32c_asm_hash ((mnem))
+
+/* -- */
+\f
+/* -- opc.c */
+static unsigned int
+m32c_asm_hash (const char *mnem)
+{
+  unsigned int h;
+  
+  /* The length of the mnemonic for the Jcnd insns is 1.  Hash jsri.  */
+  if (mnem[0] == 'j' && mnem[1] != 's')
+    return 'j';
+  
+  /* Don't hash scCND  */
+  if (mnem[0] == 's' && mnem[1] == 'c')
+    return 's';
+  
+  /* Don't hash bmCND  */
+  if (mnem[0] == 'b' && mnem[1] == 'm')
+    return 'b';
+  
+  for (h = 0; *mnem && *mnem != ' ' && *mnem != ':'; ++mnem)
+    h += *mnem;
+  return h % CGEN_ASM_HASH_SIZE;
+}
+\f
+/* -- asm.c */
+#include "safe-ctype.h"
+
+#define MACH_M32C 5            /* Must match md_begin.  */
+
+static int
+m32c_cgen_isa_register (const char **strp)
+ {
+   int u;
+   const char *s = *strp;
+   static char * m32c_register_names [] = 
+     {
+       "r0", "r1", "r2", "r3", "r0l", "r0h", "r1l", "r1h",
+       "a0", "a1", "r2r0", "r3r1", "sp", "fb", "dct0", "dct1", "flg", "svf",
+       "drc0", "drc1", "dmd0", "dmd1", "intb", "svp", "vct", "isp", "dma0",
+       "dma1", "dra0", "dra1", "dsa0", "dsa1", 0
+     };
+ 
+   for (u = 0; m32c_register_names[u]; u++)
+     {
+       int len = strlen (m32c_register_names[u]);
+
+       if (memcmp (m32c_register_names[u], s, len) == 0
+          && (s[len] == 0 || ! ISALNUM (s[len])))
+        return 1;
+     }
+   return 0;
+}
+
+#define PARSE_UNSIGNED                                                 \
+  do                                                                   \
+    {                                                                  \
+      /* Don't successfully parse literals beginning with '['.  */     \
+      if (**strp == '[')                                               \
+       return "Invalid literal"; /* Anything -- will not be seen.  */  \
+                                                                       \
+      errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value);\
+      if (errmsg)                                                      \
+       return errmsg;                                                  \
+    }                                                                  \
+  while (0)
+
+#define PARSE_SIGNED                                                   \
+  do                                                                   \
+    {                                                                  \
+      /* Don't successfully parse literals beginning with '['.  */     \
+      if (**strp == '[')                                               \
+       return "Invalid literal"; /* Anything -- will not be seen.  */  \
+                                                                       \
+      errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);  \
+      if (errmsg)                                                      \
+       return errmsg;                                                  \
+    }                                                                  \
+  while (0)
+
+static const char *
+parse_unsigned6 (CGEN_CPU_DESC cd, const char **strp,
+                int opindex, unsigned long *valuep)
+{
+  const char *errmsg = 0;
+  unsigned long value;
+
+  PARSE_UNSIGNED;
+
+  if (value > 0x3f)
+    return _("imm:6 immediate is out of range");
+
+  *valuep = value;
+  return 0;
+}
+
+static const char *
+parse_unsigned8 (CGEN_CPU_DESC cd, const char **strp,
+                int opindex, unsigned long *valuep)
+{
+  const char *errmsg = 0;
+  unsigned long value;
+  long have_zero = 0;
+
+  if (strncasecmp (*strp, "%dsp8(", 6) == 0)
+    {
+      enum cgen_parse_operand_result result_type;
+      bfd_vma value;
+      const char *errmsg;
+
+      *strp += 6;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_8,
+                                  & result_type, & value);
+      if (**strp != ')')
+       return _("missing `)'");
+      (*strp) ++;
+
+      if (errmsg == NULL
+         && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+       {
+         return _("%dsp8() takes a symbolic address, not a number");
+       }
+      *valuep = value;
+      return errmsg;
+    }
+
+  if (strncmp (*strp, "0x0", 3) == 0 
+      || (**strp == '0' && *(*strp + 1) != 'x'))
+    have_zero = 1;
+
+  PARSE_UNSIGNED;
+
+  if (value > 0xff)
+    return _("dsp:8 immediate is out of range");
+
+  /* If this field may require a relocation then use larger dsp16.  */
+  if (! have_zero && value == 0)
+    return _("dsp:8 immediate is out of range");
+
+  *valuep = value;
+  return 0;
+}
+
+static const char *
+parse_signed4 (CGEN_CPU_DESC cd, const char **strp,
+              int opindex, signed long *valuep)
+{
+  const char *errmsg = 0;
+  signed long value;
+  long have_zero = 0;
+
+  if (strncmp (*strp, "0x0", 3) == 0 
+      || (**strp == '0' && *(*strp + 1) != 'x'))
+    have_zero = 1;
+
+  PARSE_SIGNED;
+
+  if (value < -8 || value > 7)
+    return _("Immediate is out of range -8 to 7");
+
+  /* If this field may require a relocation then use larger dsp16.  */
+  if (! have_zero && value == 0)
+    return _("Immediate is out of range -8 to 7");
+
+  *valuep = value;
+  return 0;
+}
+
+static const char *
+parse_signed4n (CGEN_CPU_DESC cd, const char **strp,
+               int opindex, signed long *valuep)
+{
+  const char *errmsg = 0;
+  signed long value;
+  long have_zero = 0;
+
+  if (strncmp (*strp, "0x0", 3) == 0 
+      || (**strp == '0' && *(*strp + 1) != 'x'))
+    have_zero = 1;
+
+  PARSE_SIGNED;
+
+  if (value < -7 || value > 8)
+    return _("Immediate is out of range -7 to 8");
+
+  /* If this field may require a relocation then use larger dsp16.  */
+  if (! have_zero && value == 0)
+    return _("Immediate is out of range -7 to 8");
+
+  *valuep = -value;
+  return 0;
+}
+
+static const char *
+parse_signed8 (CGEN_CPU_DESC cd, const char **strp,
+              int opindex, signed long *valuep)
+{
+  const char *errmsg = 0;
+  signed long value;
+
+  if (strncasecmp (*strp, "%hi8(", 5) == 0)
+    {
+      enum cgen_parse_operand_result result_type;
+      bfd_vma value;
+      const char *errmsg;
+
+      *strp += 5;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32C_HI8,
+                                  & result_type, & value);
+      if (**strp != ')')
+       return _("missing `)'");
+      (*strp) ++;
+
+      if (errmsg == NULL
+         && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+       {
+         value >>= 16;
+       }
+      *valuep = value;
+      return errmsg;
+    }
+
+  PARSE_SIGNED;
+
+  if (value <= 255 && value > 127)
+    value -= 0x100;
+
+  if (value < -128 || value > 127)
+    return _("dsp:8 immediate is out of range");
+
+  *valuep = value;
+  return 0;
+}
+
+static const char *
+parse_unsigned16 (CGEN_CPU_DESC cd, const char **strp,
+                int opindex, unsigned long *valuep)
+{
+  const char *errmsg = 0;
+  unsigned long value;
+  long have_zero = 0;
+
+  if (strncasecmp (*strp, "%dsp16(", 7) == 0)
+    {
+      enum cgen_parse_operand_result result_type;
+      bfd_vma value;
+      const char *errmsg;
+
+      *strp += 7;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_16,
+                                  & result_type, & value);
+      if (**strp != ')')
+       return _("missing `)'");
+      (*strp) ++;
+
+      if (errmsg == NULL
+         && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+       {
+         return _("%dsp16() takes a symbolic address, not a number");
+       }
+      *valuep = value;
+      return errmsg;
+    }
+
+  /* Don't successfully parse literals beginning with '['.  */
+  if (**strp == '[')
+    return "Invalid literal"; /* Anything -- will not be seen.  */
+
+  /* Don't successfully parse register names.  */
+  if (m32c_cgen_isa_register (strp))
+    return "Invalid literal"; /* Anything -- will not be seen.  */
+
+  if (strncmp (*strp, "0x0", 3) == 0 
+      || (**strp == '0' && *(*strp + 1) != 'x'))
+    have_zero = 1;
+  
+  errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value);
+  if (errmsg)
+    return errmsg;
+
+  if (value > 0xffff)
+    return _("dsp:16 immediate is out of range");
+
+  /* If this field may require a relocation then use larger dsp24.  */
+  if (cd->machs == MACH_M32C && ! have_zero && value == 0
+      && (strncmp (*strp, "[a", 2) == 0
+         || **strp == ','
+         || **strp == 0))
+    return _("dsp:16 immediate is out of range");
+
+  *valuep = value;
+  return 0;
+}
+
+static const char *
+parse_signed16 (CGEN_CPU_DESC cd, const char **strp,
+              int opindex, signed long *valuep)
+{
+  const char *errmsg = 0;
+  signed long value;
+
+  if (strncasecmp (*strp, "%lo16(", 6) == 0)
+    {
+      enum cgen_parse_operand_result result_type;
+      bfd_vma value;
+      const char *errmsg;
+
+      *strp += 6;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
+                                  & result_type, & value);
+      if (**strp != ')')
+       return _("missing `)'");
+      (*strp) ++;
+
+      if (errmsg == NULL
+         && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+       {
+         value &= 0xffff;
+       }
+      *valuep = value;
+      return errmsg;
+    }
+
+  if (strncasecmp (*strp, "%hi16(", 6) == 0)
+    {
+      enum cgen_parse_operand_result result_type;
+      bfd_vma value;
+      const char *errmsg;
+
+      *strp += 6;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16,
+                                  & result_type, & value);
+      if (**strp != ')')
+       return _("missing `)'");
+      (*strp) ++;
+
+      if (errmsg == NULL
+         && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+       {
+         value >>= 16;
+       }
+      *valuep = value;
+      return errmsg;
+    }
+
+  PARSE_SIGNED;
+
+  if (value <= 65535 && value > 32767)
+    value -= 0x10000;
+
+  if (value < -32768 || value > 32767)
+    return _("dsp:16 immediate is out of range");
+
+  *valuep = value;
+  return 0;
+}
+
+static const char *
+parse_unsigned20 (CGEN_CPU_DESC cd, const char **strp,
+                int opindex, unsigned long *valuep)
+{
+  const char *errmsg = 0;
+  unsigned long value;
+  
+  /* Don't successfully parse literals beginning with '['.  */
+  if (**strp == '[')
+    return "Invalid literal"; /* Anything -- will not be seen.  */
+
+  /* Don't successfully parse register names.  */
+  if (m32c_cgen_isa_register (strp))
+    return "Invalid literal"; /* Anything -- will not be seen.  */
+
+  errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value);
+  if (errmsg)
+    return errmsg;
+
+  if (value > 0xfffff)
+    return _("dsp:20 immediate is out of range");
+
+  *valuep = value;
+  return 0;
+}
+
+static const char *
+parse_unsigned24 (CGEN_CPU_DESC cd, const char **strp,
+                int opindex, unsigned long *valuep)
+{
+  const char *errmsg = 0;
+  unsigned long value;
+  
+  /* Don't successfully parse literals beginning with '['.  */
+  if (**strp == '[')
+    return "Invalid literal"; /* Anything -- will not be seen.  */
+
+  /* Don't successfully parse register names.  */
+  if (m32c_cgen_isa_register (strp))
+    return "Invalid literal"; /* Anything -- will not be seen.  */
+
+  errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value);
+  if (errmsg)
+    return errmsg;
+
+  if (value > 0xffffff)
+    return _("dsp:24 immediate is out of range");
+
+  *valuep = value;
+  return 0;
+}
+
+/* This should only be used for #imm->reg.  */
+static const char *
+parse_signed24 (CGEN_CPU_DESC cd, const char **strp,
+                int opindex, signed long *valuep)
+{
+  const char *errmsg = 0;
+  signed long value;
+
+  PARSE_SIGNED;
+
+  if (value <= 0xffffff && value > 0x7fffff)
+    value -= 0x1000000;
+
+  if (value > 0xffffff)
+    return _("dsp:24 immediate is out of range");
+
+  *valuep = value;
+  return 0;
+}
+
+static const char *
+parse_signed32 (CGEN_CPU_DESC cd, const char **strp,
+               int opindex, signed long *valuep)
+{
+  const char *errmsg = 0;
+  signed long value;
+  
+  errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
+  if (errmsg)
+    return errmsg;
+
+  *valuep = value;
+  return 0;
+}
+
+static const char *
+parse_imm1_S (CGEN_CPU_DESC cd, const char **strp,
+            int opindex, signed long *valuep)
+{
+  const char *errmsg = 0;
+  signed long value;
+
+  errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
+  if (errmsg)
+    return errmsg;
+
+  if (value < 1 || value > 2)
+    return _("immediate is out of range 1-2");
+
+  *valuep = value;
+  return 0;
+}
+
+static const char *
+parse_imm3_S (CGEN_CPU_DESC cd, const char **strp,
+            int opindex, signed long *valuep)
+{
+  const char *errmsg = 0;
+  signed long value;
+  
+  errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
+  if (errmsg)
+    return errmsg;
+
+  if (value < 1 || value > 8)
+    return _("immediate is out of range 1-8");
+
+  *valuep = value;
+  return 0;
+}
+
+static const char *
+parse_bit3_S (CGEN_CPU_DESC cd, const char **strp,
+            int opindex, signed long *valuep)
+{
+  const char *errmsg = 0;
+  signed long value;
+  
+  errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
+  if (errmsg)
+    return errmsg;
+
+  if (value < 0 || value > 7)
+    return _("immediate is out of range 0-7");
+
+  *valuep = value;
+  return 0;
+}
+
+static const char *
+parse_lab_5_3 (CGEN_CPU_DESC cd,
+              const char **strp,
+              int opindex ATTRIBUTE_UNUSED,
+              int opinfo,
+              enum cgen_parse_operand_result *type_addr,
+              bfd_vma *valuep)
+{
+  const char *errmsg = 0;
+  bfd_vma value;
+  enum cgen_parse_operand_result op_res;
+
+  errmsg = cgen_parse_address (cd, strp, M32C_OPERAND_LAB_5_3,
+                              opinfo, & op_res, & value);
+
+  if (type_addr)
+    *type_addr = op_res;
+
+  if (op_res == CGEN_PARSE_OPERAND_RESULT_QUEUED)
+    {
+      /* This is a hack; the field cannot handle near-zero signed
+        offsets that CGEN wants to put in to indicate an "empty"
+        operand at first.  */
+      *valuep = 2;
+      return 0;
+    }
+  if (errmsg)
+    return errmsg;
+
+  if (value < 2 || value > 9)
+    return _("immediate is out of range 2-9");
+
+  *valuep = value;
+  return 0;
+}
+
+static const char *
+parse_Bitno16R (CGEN_CPU_DESC cd, const char **strp,
+               int opindex, unsigned long *valuep)
+{
+  const char *errmsg = 0;
+  unsigned long value;
+
+  errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value);
+  if (errmsg)
+    return errmsg;
+
+  if (value > 15)
+    return _("Bit number for indexing general register is out of range 0-15");
+
+  *valuep = value;
+  return 0;
+}
+
+static const char *
+parse_unsigned_bitbase (CGEN_CPU_DESC cd, const char **strp,
+                       int opindex, unsigned long *valuep,
+                       unsigned bits, int allow_syms)
+{
+  const char *errmsg = 0;
+  unsigned long bit;
+  unsigned long base;
+  const char *newp = *strp;
+  unsigned long long bitbase;
+  long have_zero = 0;
+
+  errmsg = cgen_parse_unsigned_integer (cd, & newp, opindex, & bit);
+  if (errmsg)
+    return errmsg;
+
+  if (*newp != ',')
+    return "Missing base for bit,base:8";
+
+  ++newp;
+
+  if (strncmp (newp, "0x0", 3) == 0 
+      || (newp[0] == '0' && newp[1] != 'x'))
+    have_zero = 1;
+
+  errmsg = cgen_parse_unsigned_integer (cd, & newp, opindex, & base);
+  if (errmsg)
+    return errmsg;
+
+  bitbase = (unsigned long long) bit + ((unsigned long long) base * 8);
+
+  if (bitbase >= (1ull << bits))
+    return _("bit,base is out of range");
+
+  /* If this field may require a relocation then use larger displacement.  */
+  if (! have_zero && base == 0)
+    {
+      switch (allow_syms) {
+      case 0:
+       return _("bit,base out of range for symbol");
+      case 1:
+       break;
+      case 2:
+       if (strncmp (newp, "[sb]", 4) != 0)
+         return _("bit,base out of range for symbol");
+       break;
+      }
+    }
+
+  *valuep = bitbase;
+  *strp = newp;
+  return 0;
+}
+
+static const char *
+parse_signed_bitbase (CGEN_CPU_DESC cd, const char **strp,
+                     int opindex, signed long *valuep,
+                     unsigned bits, int allow_syms)
+{
+  const char *errmsg = 0;
+  unsigned long bit;
+  signed long base;
+  const char *newp = *strp;
+  long long bitbase;
+  long long limit;
+  long have_zero = 0;
+
+  errmsg = cgen_parse_unsigned_integer (cd, & newp, opindex, & bit);
+  if (errmsg)
+    return errmsg;
+
+  if (*newp != ',')
+    return "Missing base for bit,base:8";
+
+  ++newp;
+
+  if (strncmp (newp, "0x0", 3) == 0 
+      || (newp[0] == '0' && newp[1] != 'x'))
+    have_zero = 1;
+
+  errmsg = cgen_parse_signed_integer (cd, & newp, opindex, & base);
+  if (errmsg)
+    return errmsg;
+
+  bitbase = (long long)bit + ((long long)base * 8);
+
+  limit = 1ll << (bits - 1);
+  if (bitbase < -limit || bitbase >= limit)
+    return _("bit,base is out of range");
+
+  /* If this field may require a relocation then use larger displacement.  */
+  if (! have_zero && base == 0 && ! allow_syms)
+    return _("bit,base out of range for symbol");
+
+  *valuep = bitbase;
+  *strp = newp;
+  return 0;
+}
+
+static const char *
+parse_unsigned_bitbase8 (CGEN_CPU_DESC cd, const char **strp,
+                        int opindex, unsigned long *valuep)
+{
+  return parse_unsigned_bitbase (cd, strp, opindex, valuep, 8, 0);
+}
+
+static const char *
+parse_unsigned_bitbase11 (CGEN_CPU_DESC cd, const char **strp,
+                        int opindex, unsigned long *valuep)
+{
+  return parse_unsigned_bitbase (cd, strp, opindex, valuep, 11, 0);
+}
+
+static const char *
+parse_unsigned_bitbase16 (CGEN_CPU_DESC cd, const char **strp,
+                         int opindex, unsigned long *valuep)
+{
+  return parse_unsigned_bitbase (cd, strp, opindex, valuep, 16, 1);
+}
+
+static const char *
+parse_unsigned_bitbase19 (CGEN_CPU_DESC cd, const char **strp,
+                        int opindex, unsigned long *valuep)
+{
+  return parse_unsigned_bitbase (cd, strp, opindex, valuep, 19, 2);
+}
+
+static const char *
+parse_unsigned_bitbase27 (CGEN_CPU_DESC cd, const char **strp,
+                        int opindex, unsigned long *valuep)
+{
+  return parse_unsigned_bitbase (cd, strp, opindex, valuep, 27, 1);
+}
+
+static const char *
+parse_signed_bitbase8 (CGEN_CPU_DESC cd, const char **strp,
+                      int opindex, signed long *valuep)
+{
+  return parse_signed_bitbase (cd, strp, opindex, valuep, 8, 1);
+}
+
+static const char *
+parse_signed_bitbase11 (CGEN_CPU_DESC cd, const char **strp,
+                      int opindex, signed long *valuep)
+{
+  return parse_signed_bitbase (cd, strp, opindex, valuep, 11, 0);
+}
+
+static const char *
+parse_signed_bitbase19 (CGEN_CPU_DESC cd, const char **strp,
+                      int opindex, signed long *valuep)
+{
+  return parse_signed_bitbase (cd, strp, opindex, valuep, 19, 1);
+}
+
+/* Parse the suffix as :<char> or as nothing followed by a whitespace.  */
+
+static const char *
+parse_suffix (const char **strp, char suffix)
+{
+  const char *newp = *strp;
+  
+  if (**strp == ':' && TOLOWER (*(*strp + 1)) == suffix)
+    newp = *strp + 2;
+
+  if (ISSPACE (*newp))
+    {
+      *strp = newp;
+      return 0;
+    }
+       
+  return "Invalid suffix"; /* Anything -- will not be seen.  */
+}
+
+static const char *
+parse_S (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp,
+        int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED)
+{
+  return parse_suffix (strp, 's');
+}
+
+static const char *
+parse_G (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp,
+        int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED)
+{
+  return parse_suffix (strp, 'g');
+}
+
+static const char *
+parse_Q (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp,
+        int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED)
+{
+  return parse_suffix (strp, 'q');
+}
+
+static const char *
+parse_Z (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp,
+        int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED)
+{
+  return parse_suffix (strp, 'z');
+}
+
+/* Parse an empty suffix. Fail if the next char is ':'.  */
+
+static const char *
+parse_X (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp,
+        int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED)
+{
+  if (**strp == ':')
+    return "Unexpected suffix";
+  return 0;
+}
+
+static const char *
+parse_r0l_r0h (CGEN_CPU_DESC cd, const char **strp,
+              int opindex ATTRIBUTE_UNUSED, signed long *valuep)
+{
+  const char *errmsg;
+  signed long value;
+  signed long junk;
+  const char *newp = *strp;
+
+  /* Parse r0[hl].  */
+  errmsg = cgen_parse_keyword (cd, & newp, & m32c_cgen_opval_h_r0l_r0h, & value);
+  if (errmsg)
+    return errmsg;
+
+  if (*newp != ',')
+    return _("not a valid r0l/r0h pair");
+  ++newp;
+
+  /* Parse the second register in the pair.  */
+  if (value == 0) /* r0l */
+    errmsg = cgen_parse_keyword (cd, & newp, & m32c_cgen_opval_h_r0h, & junk);
+  else
+    errmsg = cgen_parse_keyword (cd, & newp, & m32c_cgen_opval_h_r0l, & junk);
+  if (errmsg)
+    return errmsg;
+
+  *strp = newp;
+  *valuep = ! value;
+  return 0;
+}
+
+/* Accept .b or .w in any case.  */
+
+static const char *
+parse_size (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp,
+           int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED)
+{
+  if (**strp == '.'
+      && (*(*strp + 1) == 'b' || *(*strp + 1) == 'B'
+         || *(*strp + 1) == 'w' || *(*strp + 1) == 'W'))
+    {
+      *strp += 2;
+      return NULL;
+    }
+
+  return _("Invalid size specifier");
+}
+
+/* Special check to ensure that instruction exists for given machine.  */
+
+int
+m32c_cgen_insn_supported (CGEN_CPU_DESC cd,
+                         const CGEN_INSN *insn)
+{
+  int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH);
+  CGEN_BITSET isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA);
+
+  /* If attributes are absent, assume no restriction.  */
+  if (machs == 0)
+    machs = ~0;
+
+  return ((machs & cd->machs)
+          && cgen_bitset_intersect_p (& isas, cd->isas));
+}
+
+/* Parse a set of registers, R0,R1,A0,A1,SB,FB.  */
+
+static const char *
+parse_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+             const char **strp,
+             int opindex ATTRIBUTE_UNUSED,
+             unsigned long *valuep,
+             int push)
+{
+  const char *errmsg = 0;
+  int regno = 0;
+ 
+  *valuep = 0;
+  while (**strp && **strp != ')')
+    {
+      if (**strp == 'r' || **strp == 'R')
+       {
+         ++*strp;
+         regno = **strp - '0';
+         if (regno > 4)
+           errmsg = _("Register number is not valid");
+       }
+      else if (**strp == 'a' || **strp == 'A')
+       {
+         ++*strp;
+         regno = **strp - '0';
+         if (regno > 2)
+           errmsg = _("Register number is not valid");
+         regno = **strp - '0' + 4;
+       }
+      
+      else if (strncasecmp (*strp, "sb", 2) == 0 || strncasecmp (*strp, "SB", 2) == 0)
+       {
+         regno = 6;
+         ++*strp;
+       }
+      
+      else if (strncasecmp (*strp, "fb", 2) == 0 || strncasecmp (*strp, "FB", 2) == 0)
+       {
+         regno = 7;
+         ++*strp;
+       }
+      
+      if (push) /* Mask is reversed for push.  */
+       *valuep |= 0x80 >> regno;
+      else
+       *valuep |= 1 << regno;
+
+      ++*strp;
+      if (**strp == ',')
+        {
+          if (*(*strp + 1) == ')')
+            break;
+          ++*strp;
+        }
+    }
+
+  if (!*strp)
+    errmsg = _("Register list is not valid");
+
+  return errmsg;
+}
+
+#define POP  0
+#define PUSH 1
+
+static const char *
+parse_pop_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+                 const char **strp,
+                 int opindex ATTRIBUTE_UNUSED,
+                 unsigned long *valuep)
+{
+  return parse_regset (cd, strp, opindex, valuep, POP);
+}
+
+static const char *
+parse_push_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+                  const char **strp,
+                  int opindex ATTRIBUTE_UNUSED,
+                  unsigned long *valuep)
+{
+  return parse_regset (cd, strp, opindex, valuep, PUSH);
+}
+
+/* -- dis.c */
+
+#include "elf/m32c.h"
+#include "elf-bfd.h"
+
+/* Always print the short insn format suffix as ':<char>'.  */
+
+static void
+print_suffix (void * dis_info, char suffix)
+{
+  disassemble_info *info = dis_info;
+
+  (*info->fprintf_func) (info->stream, ":%c", suffix);
+}
+
+static void
+print_S (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+        void * dis_info,
+        long value ATTRIBUTE_UNUSED,
+        unsigned int attrs ATTRIBUTE_UNUSED,
+        bfd_vma pc ATTRIBUTE_UNUSED,
+        int length ATTRIBUTE_UNUSED)
+{
+  print_suffix (dis_info, 's');
+}
+
+
+static void
+print_G (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+        void * dis_info,
+        long value ATTRIBUTE_UNUSED,
+        unsigned int attrs ATTRIBUTE_UNUSED,
+        bfd_vma pc ATTRIBUTE_UNUSED,
+        int length ATTRIBUTE_UNUSED)
+{
+  print_suffix (dis_info, 'g');
+}
+
+static void
+print_Q (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+        void * dis_info,
+        long value ATTRIBUTE_UNUSED,
+        unsigned int attrs ATTRIBUTE_UNUSED,
+        bfd_vma pc ATTRIBUTE_UNUSED,
+        int length ATTRIBUTE_UNUSED)
+{
+  print_suffix (dis_info, 'q');
+}
+
+static void
+print_Z (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+        void * dis_info,
+        long value ATTRIBUTE_UNUSED,
+        unsigned int attrs ATTRIBUTE_UNUSED,
+        bfd_vma pc ATTRIBUTE_UNUSED,
+        int length ATTRIBUTE_UNUSED)
+{
+  print_suffix (dis_info, 'z');
+}
+
+/* Print the empty suffix.  */
+
+static void
+print_X (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+        void * dis_info ATTRIBUTE_UNUSED,
+        long value ATTRIBUTE_UNUSED,
+        unsigned int attrs ATTRIBUTE_UNUSED,
+        bfd_vma pc ATTRIBUTE_UNUSED,
+        int length ATTRIBUTE_UNUSED)
+{
+  return;
+}
+
+static void
+print_r0l_r0h (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+              void * dis_info,
+              long value,
+              unsigned int attrs ATTRIBUTE_UNUSED,
+              bfd_vma pc ATTRIBUTE_UNUSED,
+              int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = dis_info;
+
+  if (value == 0)
+    (*info->fprintf_func) (info->stream, "r0h,r0l");
+  else
+    (*info->fprintf_func) (info->stream, "r0l,r0h");
+}
+
+static void
+print_unsigned_bitbase (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+                       void * dis_info,
+                       unsigned long value,
+                       unsigned int attrs ATTRIBUTE_UNUSED,
+                       bfd_vma pc ATTRIBUTE_UNUSED,
+                       int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = dis_info;
+
+  (*info->fprintf_func) (info->stream, "%ld,0x%lx", value & 0x7, value >> 3);
+}
+
+static void
+print_signed_bitbase (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+                     void * dis_info,
+                     signed long value,
+                     unsigned int attrs ATTRIBUTE_UNUSED,
+                     bfd_vma pc ATTRIBUTE_UNUSED,
+                     int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = dis_info;
+
+  (*info->fprintf_func) (info->stream, "%ld,%ld", value & 0x7, value >> 3);
+}
+
+static void
+print_size (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+           void * dis_info,
+           long value ATTRIBUTE_UNUSED,
+           unsigned int attrs ATTRIBUTE_UNUSED,
+           bfd_vma pc ATTRIBUTE_UNUSED,
+           int length ATTRIBUTE_UNUSED)
+{
+  /* Always print the size as '.w'.  */
+  disassemble_info *info = dis_info;
+
+  (*info->fprintf_func) (info->stream, ".w");
+}
+
+#define POP  0
+#define PUSH 1
+
+static void print_pop_regset  (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
+static void print_push_regset (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
+
+/* Print a set of registers, R0,R1,A0,A1,SB,FB.  */
+
+static void
+print_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+             void * dis_info,
+             long value,
+             unsigned int attrs ATTRIBUTE_UNUSED,
+             bfd_vma pc ATTRIBUTE_UNUSED,
+             int length ATTRIBUTE_UNUSED,
+             int push)
+{
+  static char * m16c_register_names [] = 
+  {
+    "r0", "r1", "r2", "r3", "a0", "a1", "sb", "fb"
+  };
+  disassemble_info *info = dis_info;
+  int mask;
+  int index = 0;
+  char* comma = "";
+
+  if (push)
+    mask = 0x80;
+  else
+    mask = 1;
+ 
+  if (value & mask)
+    {
+      (*info->fprintf_func) (info->stream, "%s", m16c_register_names [0]);
+      comma = ",";
+    }
+
+  for (index = 1; index <= 7; ++index)
+    {
+      if (push)
+        mask >>= 1;
+      else
+        mask <<= 1;
+
+      if (value & mask)
+        {
+          (*info->fprintf_func) (info->stream, "%s%s", comma,
+                                m16c_register_names [index]);
+          comma = ",";
+        }
+    }
+}
+
+static void
+print_pop_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+                 void * dis_info,
+                 long value,
+                 unsigned int attrs ATTRIBUTE_UNUSED,
+                 bfd_vma pc ATTRIBUTE_UNUSED,
+                 int length ATTRIBUTE_UNUSED)
+{
+  print_regset (cd, dis_info, value, attrs, pc, length, POP);
+}
+
+static void
+print_push_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+                  void * dis_info,
+                  long value,
+                  unsigned int attrs ATTRIBUTE_UNUSED,
+                  bfd_vma pc ATTRIBUTE_UNUSED,
+                  int length ATTRIBUTE_UNUSED)
+{
+  print_regset (cd, dis_info, value, attrs, pc, length, PUSH);
+}
+
+static void
+print_signed4n (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+               void * dis_info,
+               signed long value,
+               unsigned int attrs ATTRIBUTE_UNUSED,
+               bfd_vma pc ATTRIBUTE_UNUSED,
+               int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = dis_info;
+
+  (*info->fprintf_func) (info->stream, "%ld", -value);
+}

diff --git a/cpu/m32r.cpu b/cpu/m32r.cpu
new file mode 100644 (file)
index 0000000..e24fc3d
--- /dev/null
+++ b/cpu/m32r.cpu
@@ -0,0 +1,2427 @@
+; Renesas M32R CPU description.  -*- Scheme -*-
+;
+; Copyright 1998, 1999, 2000, 2001, 2003, 2007, 2009
+; Free Software Foundation, Inc.
+;
+; Contributed by Red Hat Inc; developed under contract from Mitsubishi
+; Electric Corporation.
+;
+; This file is part of the GNU Binutils.
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 3 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, write to the Free Software
+; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+; MA 02110-1301, USA.
+
+(include "simplify.inc")
+
+; FIXME: Delete sign extension of accumulator results.
+; Sign extension is done when accumulator is read.
+
+; define-arch must appear first
+
+(define-arch
+  (name m32r) ; name of cpu family
+  (comment "Renesas M32R")
+  (default-alignment aligned)
+  (insn-lsb0? #f)
+  (machs m32r m32rx m32r2)
+  (isas m32r)
+)
+
+; Attributes.
+
+; An attribute to describe which pipeline an insn runs in.
+; O_OS is a special attribute for sll, sra, sla, slli, srai, slai.
+; These instructions have O attribute for m32rx and OS attribute for m32r2.
+
+(define-attr
+  (for insn)
+  (type enum)
+  (name PIPE)
+  (comment "parallel execution pipeline selection")
+  (values NONE O S OS O_OS)
+)
+
+; A derived attribute that says which insns can be executed in parallel
+; with others.  This is a required attribute for architectures with
+; parallel execution.
+
+(define-attr
+  (for insn)
+  (type enum)
+  (name PARALLEL)
+  (attrs META) ; do not define in any generated file for now
+  (values NO YES)
+  (default (if (eq-attr (current-insn) PIPE NONE) (symbol NO) (symbol YES)))
+)
+
+; Instruction set parameters.
+
+(define-isa
+  (name m32r)
+
+  ; This is 32 because 16 bit insns always appear as pairs.
+  ; ??? See if this can go away.  It's only used by the disassembler (right?)
+  ; to decide how long an unknown insn is.  One value isn't sufficient (e.g. if
+  ; on a 16 bit (and not 32 bit) boundary, will only want to advance pc by 16.)
+  (default-insn-bitsize 32)
+
+  ; Number of bytes of insn we can initially fetch.
+  ; The M32R is tricky in that insns are either two 16-bit insns
+  ; (executed sequentially or in parallel) or one 32-bit insn.
+  ; So on one hand the base insn size is 16 bits, but on another it's 32.
+  ; 32 is chosen because:
+  ; - if the chip were ever bi-endian it is believed that the byte order would
+  ;   be based on 32 bit quantities
+  ; - 32 bit insns are always aligned on 32 bit boundaries
+  ; - the pc will never stop on a 16 bit (and not 32 bit) boundary
+  ;   [well actually it can, but there are no branches to such places]
+  (base-insn-bitsize 32)
+
+  ; Used in computing bit numbers.
+  (default-insn-word-bitsize 32)
+
+  ; The m32r fetches 2 insns at a time.
+  (liw-insns 2)
+
+  ; While the m32r can execute insns in parallel, the base mach can't
+  ; (other than nop).  The base mach is greatly handicapped by this, but
+  ; we still need to cleanly handle it.
+  (parallel-insns 2)
+
+  ; Initial bitnumbers to decode insns by.
+  (decode-assist (0 1 2 3 8 9 10 11))
+
+  ; Classification of instructions that fit in the various frames.
+  ; wip, not currently used
+  (insn-types (long ; name
+              31 ; length
+              (eq-attr (current-insn) LENGTH 31) ; matching insns
+              (0 1 2 7 8 9 10) ; decode-assist
+              )
+             (short
+              15
+              (eq-attr (current-insn) LENGTH 15) ; matching insns
+              (0 1 2 7 8 9 10)
+              )
+             )
+
+  ; Instruction framing.
+  ; Each m32r insn is either one 32 bit insn, two 16 bit insns executed
+  ; serially (left->right), or two 16 bit insns executed parallelly.
+  ; wip, not currently used
+  (frame long32 ; name
+        ((long)) ; list of insns in frame, plus constraint
+        "$0"   ; assembler
+        (+ (1 1) (31 $0)) ; value
+        (sequence () (execute $0)) ; action
+        )
+  (frame serial2x16
+        ((short)
+         (short))
+        "$0 -> $1"
+        (+ (1 0) (15 $0) (1 0) (15 $1))
+        (sequence ()
+                  (execute $0)
+                  (execute $1))
+        )
+  (frame parallel2x16
+        ((short (eq-attr (current-insn) PIPE "O,BOTH"))
+         (short (eq-attr (current-insn) PIPE "S,BOTH")))
+        "$0 || $1"
+        (+ (1 0) (15 $0) (1 1) (15 $1))
+        (parallel ()
+                  (execute $0)
+                  (execute $1))
+        )
+)
+\f
+; Cpu family definitions.
+
+; ??? define-cpu-family [and in general "cpu-family"] might be clearer than
+; define-cpu.
+; ??? Have define-arch provide defaults for architecture that define-cpu can
+; then override [reduces duplication in define-cpu].
+; ??? Another way to go is to delete cpu-families entirely and have one mach
+; able to inherit things from another mach (would also need the ability to
+; not only override specific inherited things but also disable some,
+; e.g. if an insn wasn't supported).
+
+(define-cpu
+  ; cpu names must be distinct from the architecture name and machine names.
+  ; The "b" suffix stands for "base" and is the convention.
+  ; The "f" suffix stands for "family" and is the convention.
+  (name m32rbf)
+  (comment "Renesas M32R base family")
+  (endian either)
+  (word-bitsize 32)
+  ; Override isa spec (??? keeps things simpler, though it was more true
+  ; in the early days and not so much now).
+  (parallel-insns 1)
+)
+
+(define-cpu
+  (name m32rxf)
+  (comment "Renesas M32Rx family")
+  (endian either)
+  (word-bitsize 32)
+  ; Generated files have an "x" suffix.
+  (file-transform "x")
+)
+
+(define-cpu
+  (name m32r2f)
+  (comment "Renesas M32R2 family")
+  (endian either)
+  (word-bitsize 32)
+  ; Generated files have an "2" suffix.
+  (file-transform "2")
+)
+
+(define-mach
+  (name m32r)
+  (comment "Generic M32R cpu")
+  (cpu m32rbf)
+)
+
+(define-mach
+  (name m32rx)
+  (comment "M32RX cpu")
+  (cpu m32rxf)
+)
+
+(define-mach
+  (name m32r2)
+  (comment "M32R2 cpu")
+  (cpu m32r2f)
+)
+\f
+; Model descriptions.
+
+; The meaning of this value is wip but at the moment it's intended to describe
+; the implementation (i.e. what -mtune=foo does in sparc gcc).
+;
+; Notes while wip:
+; - format of pipeline entry:
+;   (pipeline name (stage1-name ...) (stage2-name ...) ...)
+;   The contents of a stage description is wip.
+; - each mach must have at least one model
+; - the default model must be the first one
+;- maybe have `retire' support update total cycle count to handle current
+;  parallel insn cycle counting problems
+
+(define-model
+  (name m32r/d) (comment "m32r/d") (attrs)
+  (mach m32r)
+
+  ;(prefetch)
+  ;(retire)
+
+  (pipeline p-non-mem "" () ((fetch) (decode) (execute) (writeback)))
+  (pipeline p-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))
+
+  ; `state' is a list of variables for recording model state
+  (state
+   ; bit mask of h-gr registers, =1 means value being loaded from memory
+   (h-gr UINT)
+   )
+
+  (unit u-exec "Execution Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((sr INT -1) (dr INT -1)) ; inputs
+       ((dr INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-cmp "Compare Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((src1 INT -1) (src2 INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  (unit u-mac "Multiply/Accumulate Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((src1 INT -1) (src2 INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  (unit u-cti "Branch Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((sr INT -1)) ; inputs
+       ((pc)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-load "Memory Load Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((sr INT)
+        ;(ld-mem AI)
+        ) ; inputs
+       ((dr INT)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-store "Memory Store Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((src1 INT) (src2 INT)) ; inputs
+       () ; ((st-mem AI)) ; outputs
+       () ; profile action (default)
+       )
+)
+
+(define-model
+  (name test) (comment "test") (attrs)
+  (mach m32r)
+  (pipeline all "" () ((fetch) (decode) (execute) (writeback)))
+  (unit u-exec "Execution Unit" ()
+       1 1 ; issue done
+       () () () ())
+)
+
+; Each mach must have at least one model.
+
+(define-model
+  (name m32rx) (comment "m32rx") (attrs)
+  (mach m32rx)
+
+  ; ??? It's 6 stages but I forget the details right now.
+  (pipeline p-o "" () ((fetch) (decode) (execute) (writeback)))
+  (pipeline p-s "" () ((fetch) (decode) (execute) (writeback)))
+  (pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))
+
+  (unit u-exec "Execution Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((sr INT -1) (dr INT -1)) ; inputs
+       ((dr INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-cmp "Compare Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((src1 INT -1) (src2 INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  (unit u-mac "Multiply/Accumulate Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((src1 INT -1) (src2 INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  (unit u-cti "Branch Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((sr INT -1)) ; inputs
+       ((pc)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-load "Memory Load Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((sr INT)) ; inputs
+       ((dr INT)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-store "Memory Store Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((src1 INT) (src2 INT)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+)
+
+(define-model
+  (name m32r2) (comment "m32r2") (attrs)
+  (mach m32r2)
+
+  ; ??? It's 6 stages but I forget the details right now.
+  (pipeline p-o "" () ((fetch) (decode) (execute) (writeback)))
+  (pipeline p-s "" () ((fetch) (decode) (execute) (writeback)))
+  (pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))
+
+  (unit u-exec "Execution Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((sr INT -1) (dr INT -1)) ; inputs
+       ((dr INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-cmp "Compare Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((src1 INT -1) (src2 INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  (unit u-mac "Multiply/Accumulate Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((src1 INT -1) (src2 INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  (unit u-cti "Branch Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((sr INT -1)) ; inputs
+       ((pc)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-load "Memory Load Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((sr INT)) ; inputs
+       ((dr INT)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-store "Memory Store Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((src1 INT) (src2 INT)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+)
+\f
+; The instruction fetch/execute cycle.
+; This is split into two parts as sometimes more than one instruction is
+; decoded at once.
+; The `const SI' argument to decode/execute is used to distinguish
+; multiple instructions processed at the same time (e.g. m32r).
+;
+; ??? This is wip, and not currently used.
+; ??? Needs to be moved to define-isa.
+
+; This is how to fetch and decode an instruction.
+
+;(define-extract
+;  (sequence VOID
+;          (if VOID (ne AI (and AI pc (const AI 3)) (const AI 0))
+;              (sequence VOID
+;                        (set-quiet USI (scratch UHI insn1) (ifetch UHI pc))
+;                        (decode VOID pc (and UHI insn1 (const UHI #x7fff))
+;                                (const SI 0)))
+;              (sequence VOID
+;                        (set-quiet USI (scratch USI insn) (ifetch USI pc))
+;                        (if VOID (ne USI (and USI insn (const USI #x80000000))
+;                                   (const USI 0))
+;                            (decode VOID pc (srl USI insn (const WI 16)) (const SI 0))
+;                            (sequence VOID
+;                                      ; ??? parallel support
+;                                      (decode VOID pc (srl USI insn (const WI 16))
+;                                              (const SI 0))
+;                                      (decode VOID (add AI pc (const AI 2))
+;                                              (and USI insn (const WI #x7fff))
+;                                              (const SI 1))))))
+;          )
+;)
+
+; This is how to execute a decoded instruction.
+
+;(define-execute
+;  (sequence VOID () ; () is empty option list
+;           ((AI new_pc))
+;           (set AI new_pc (execute: AI (const 0)) #:quiet)
+;           (set AI pc new_pc #:direct)
+;           )
+;)
+
+; FIXME: It might simplify things to separate the execute process from the
+; one that updates the PC.
+\f
+; Instruction fields.
+;
+; Attributes:
+; PCREL-ADDR: pc relative value (for reloc and disassembly purposes)
+; ABS-ADDR: absolute address (for reloc and disassembly purposes?)
+; RESERVED: bits are not used to decode insn, must be all 0
+; RELOC: there is a relocation associated with this field (experiment)
+
+(define-attr
+  (for ifield operand)
+  (type boolean)
+  (name RELOC)
+  (comment "there is a reloc associated with this field (experiment)")
+)
+
+(dnf f-op1       "op1"                 () 0 4)
+(dnf f-op2       "op2"                 () 8 4)
+(dnf f-cond      "cond"                () 4 4)
+(dnf f-r1        "r1"                  () 4 4)
+(dnf f-r2        "r2"                  () 12 4)
+(df f-simm8      "simm8"               () 8 8 INT #f #f)
+(df f-simm16     "simm16"              () 16 16 INT #f #f)
+(dnf f-shift-op2 "shift op2"           () 8 3)
+(dnf f-uimm3     "uimm3"               () 5 3)
+(dnf f-uimm4     "uimm4"               () 12 4)
+(dnf f-uimm5     "uimm5"               () 11 5)
+(dnf f-uimm8     "uimm8"               () 8 8)
+(dnf f-uimm16    "uimm16"              () 16 16)
+(dnf f-uimm24    "uimm24"              (ABS-ADDR RELOC) 8 24)
+(dnf f-hi16      "high 16 bits"        (SIGN-OPT) 16 16)
+(df f-disp8      "disp8, slot unknown" (PCREL-ADDR RELOC) 8 8 INT
+    ((value pc) (sra WI (sub WI value (and WI pc (const -4))) (const 2)))
+    ((value pc) (add WI (sll WI value (const 2)) (and WI pc (const -4)))))
+(df f-disp16     "disp16"              (PCREL-ADDR RELOC) 16 16 INT
+    ((value pc) (sra WI (sub WI value pc) (const 2)))
+    ((value pc) (add WI (sll WI value (const 2)) pc)))
+(df f-disp24     "disp24"              (PCREL-ADDR RELOC) 8 24 INT
+    ((value pc) (sra WI (sub WI value pc) (const 2)))
+    ((value pc) (add WI (sll WI value (const 2)) pc)))
+
+(dnf f-op23      "op2.3"               ()  9 3)
+(dnf f-op3       "op3"                 () 14 2)
+(dnf f-acc       "acc"                 ()  8 1)
+(dnf f-accs      "accs"                () 12 2)
+(dnf f-accd      "accd"                ()  4 2)
+(dnf f-bits67    "bits67"              ()  6 2)
+(dnf f-bit4      "bit4"                ()  4 1)
+(dnf f-bit14     "bit14"               () 14 1)
+
+(define-ifield (name f-imm1) (comment "1 bit immediate, 0->1 1->2")
+  (attrs)
+  (start 15) (length 1)
+  (encode (value pc) (sub WI value (const WI 1)))
+  (decode (value pc) (add WI value (const WI 1)))
+)
+\f
+; Enums.
+
+; insn-op1: bits 0-3
+; FIXME: should use die macro or some such
+(define-normal-insn-enum insn-op1 "insn format enums" () OP1_ f-op1
+  ("0" "1" "2" "3" "4" "5" "6" "7"
+   "8" "9" "10" "11" "12" "13" "14" "15")
+)
+
+; insn-op2: bits 8-11
+; FIXME: should use die macro or some such
+(define-normal-insn-enum insn-op2 "op2 enums" () OP2_ f-op2
+  ("0" "1" "2" "3" "4" "5" "6" "7"
+   "8" "9" "10" "11" "12" "13" "14" "15")
+)
+\f
+; Hardware pieces.
+; These entries list the elements of the raw hardware.
+; They're also used to provide tables and other elements of the assembly
+; language.
+
+(dnh h-pc "program counter" (PC PROFILE) (pc) () () ())
+
+(dnh h-hi16 "high 16 bits" ()
+     (immediate (UINT 16))
+     () () ()
+)
+
+; These two aren't technically needed.
+; They're here for illustration sake mostly.
+; Plus they cause the value to be stored in the extraction buffers to only
+; be 16 bits wide (vs 32 or 64).  Whoopie ding.  But it's fun.
+(dnh h-slo16 "signed low 16 bits" ()
+     (immediate (INT 16))
+     () () ()
+)
+(dnh h-ulo16 "unsigned low 16 bits" ()
+     (immediate (UINT 16))
+     () () ()
+)
+
+(define-keyword
+  (name gr-names)
+  (print-name h-gr)
+  (prefix "")
+  (values (fp 13) (lr 14) (sp 15)
+         (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7)
+         (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15))
+)
+
+(define-hardware
+  (name h-gr)
+  (comment "general registers")
+  (attrs PROFILE CACHE-ADDR)
+  (type register WI (16))
+  (indices extern-keyword gr-names)
+)
+
+(define-keyword
+  (name cr-names)
+  (print-name h-cr)
+  (prefix "")
+  (values (psw 0)   (cbr 1)   (spi 2)   (spu 3)
+         (bpc 6)   (bbpsw 8) (bbpc 14) (evb 5)
+         (cr0 0)   (cr1 1)   (cr2 2)   (cr3 3)
+         (cr4 4)   (cr5 5)   (cr6 6)   (cr7 7)
+         (cr8 8)   (cr9 9)   (cr10 10) (cr11 11)
+         (cr12 12) (cr13 13) (cr14 14) (cr15 15))
+)
+
+(define-hardware
+  (name h-cr)
+  (comment "control registers")
+  (type register UWI (16))
+  (indices extern-keyword cr-names)
+  (get (index) (c-call UWI "@cpu@_h_cr_get_handler" index))
+  (set (index newval) (c-call VOID "@cpu@_h_cr_set_handler" index newval))
+)
+
+; The actual accumulator is only 56 bits.
+; The top 8 bits are sign extended from bit 8 (when counting msb = bit 0).
+; To simplify the accumulator instructions, no attempt is made to keep the
+; top 8 bits properly sign extended (currently there's no point since they
+; all ignore them).  When the value is read it is properly sign extended
+; [in the `get' handler].
+(define-hardware
+  (name h-accum)
+  (comment "accumulator")
+  (type register DI)
+  (get () (c-call DI "@cpu@_h_accum_get_handler"))
+  (set (newval) (c-call VOID "@cpu@_h_accum_set_handler" newval))
+)
+
+; FIXME: Revisit after sanitization can be removed.  Remove h-accum.
+(define-hardware
+  (name h-accums)
+  (comment "accumulators")
+  (attrs (MACH m32rx,m32r2))
+  (type register DI (2))
+  (indices keyword "" ((a0 0) (a1 1)))
+  ; get/set so a0 accesses are redirected to h-accum.
+  ; They're also so reads can properly sign extend the value.
+  ; FIXME: Needn't be a function call.
+  (get (index) (c-call DI "@cpu@_h_accums_get_handler" index))
+  (set (index newval) (c-call VOID "@cpu@_h_accums_set_handler" index newval))
+)
+
+; For condbit operand.  FIXME: Need to allow spec of get/set of operands.
+; Having this separate from h-psw keeps the parts that use it simpler
+; [since they greatly outnumber those that use h-psw].
+(dsh h-cond "condition bit" () (register BI))
+
+; The actual values of psw,bpsw,bbpsw are recorded here to allow access
+; to them as a unit.
+(define-hardware
+  (name h-psw)
+  (comment "psw part of psw")
+  (type register UQI)
+  ; get/set to handle cond bit.
+  ; FIXME: missing: use's and clobber's
+  ; FIXME: remove c-call?
+  (get () (c-call UQI "@cpu@_h_psw_get_handler"))
+  (set (newval) (c-call VOID "@cpu@_h_psw_set_handler" newval))
+)
+(dsh h-bpsw  "backup psw"      () (register UQI))
+(dsh h-bbpsw "backup bpsw"     () (register UQI))
+
+; FIXME: Later make add get/set specs and support SMP.
+(dsh h-lock  "lock"  () (register BI))
+\f
+; Instruction Operands.
+; These entries provide a layer between the assembler and the raw hardware
+; description, and are used to refer to hardware elements in the semantic
+; code.  Usually there's a bit of over-specification, but in more complicated
+; instruction sets there isn't.
+
+; M32R specific operand attributes:
+
+(define-attr
+  (for operand)
+  (type boolean)
+  (name HASH-PREFIX)
+  (comment "immediates have an optional '#' prefix")
+)
+
+; ??? Convention says this should be o-sr, but then the insn definitions
+; should refer to o-sr which is clumsy.  The "o-" could be implicit, but
+; then it should be implicit for all the symbols here, but then there would
+; be confusion between (f-)simm8 and (h-)simm8.
+; So for now the rule is exactly as it appears here.
+
+(dnop sr     "source register"              () h-gr   f-r2)
+(dnop dr     "destination register"         () h-gr   f-r1)
+;; The assembler relies upon the fact that dr and src1 are the same field.
+;; FIXME: Revisit.
+(dnop src1   "source register 1"            () h-gr   f-r1)
+(dnop src2   "source register 2"            () h-gr   f-r2)
+(dnop scr    "source control register"      () h-cr   f-r2)
+(dnop dcr    "destination control register" () h-cr   f-r1)
+
+(dnop simm8  "8 bit signed immediate"       (HASH-PREFIX) h-sint f-simm8)
+(dnop simm16 "16 bit signed immediate"      (HASH-PREFIX) h-sint f-simm16)
+(dnop uimm3  "3 bit unsigned number"        (HASH-PREFIX) h-uint f-uimm3)
+(dnop uimm4  "4 bit trap number"            (HASH-PREFIX) h-uint f-uimm4)
+(dnop uimm5  "5 bit shift count"            (HASH-PREFIX) h-uint f-uimm5)
+(dnop uimm8  "8 bit unsigned immediate"     (HASH-PREFIX) h-uint f-uimm8)
+(dnop uimm16 "16 bit unsigned immediate"    (HASH-PREFIX) h-uint f-uimm16)
+
+(dnop imm1   "1 bit immediate"              ((MACH m32rx,m32r2) HASH-PREFIX) h-uint f-imm1)
+(dnop accd   "accumulator destination register" ((MACH m32rx,m32r2))        h-accums f-accd)
+(dnop accs   "accumulator source register"  ((MACH m32rx,m32r2))            h-accums f-accs)
+(dnop acc    "accumulator reg (d)"          ((MACH m32rx,m32r2))            h-accums f-acc)
+
+; slo16,ulo16 are used in both with-hash-prefix/no-hash-prefix cases.
+; e.g. add3 r3,r3,#1 and ld r3,@(4,r4).  We could use HASH-PREFIX.
+; Instead we create a fake operand `hash'.  The m32r is an illustration port,
+; so we often try out various ways of doing things.
+
+(define-operand (name hash) (comment "# prefix") (attrs)
+  (type h-sint) ; doesn't really matter
+  (index f-nil)
+  (handlers (parse "hash") (print "hash"))
+)
+
+; For high(foo),shigh(foo).
+(define-operand
+  (name hi16)
+  (comment "high 16 bit immediate, sign optional")
+  (attrs)
+  (type h-hi16)
+  (index f-hi16)
+  (handlers (parse "hi16"))
+)
+
+; For low(foo),sda(foo).
+(define-operand
+  (name slo16)
+  (comment "16 bit signed immediate, for low()")
+  (attrs)
+  (type h-slo16)
+  (index f-simm16)
+  (handlers (parse "slo16"))
+)
+
+; For low(foo).
+(define-operand
+  (name ulo16)
+  (comment "16 bit unsigned immediate, for low()")
+  (attrs)
+  (type h-ulo16)
+  (index f-uimm16)
+  (handlers (parse "ulo16"))
+)
+
+(dnop uimm24 "24 bit address" (HASH-PREFIX) h-addr f-uimm24)
+
+(define-operand
+  (name disp8)
+  (comment "8 bit displacement")
+  (attrs RELAX)
+  (type h-iaddr)
+  (index f-disp8)
+  ; ??? Early experiments had insert/extract fields here.
+  ; Moving these to f-disp8 made things cleaner, but may wish to re-introduce
+  ; fields here to handle more complicated cases.
+)
+
+(dnop disp16 "16 bit displacement" () h-iaddr f-disp16)
+(dnop disp24 "24 bit displacement" (RELAX) h-iaddr f-disp24)
+
+; These hardware elements are refered to frequently.
+
+(dnop condbit "condition bit" (SEM-ONLY) h-cond f-nil)
+(dnop accum "accumulator" (SEM-ONLY) h-accum f-nil)
+\f
+; Instruction definitions.
+;
+; Notes while wip:
+; - dni is a cover macro to the real "this is an instruction" keyword.
+;   The syntax of the real one is yet to be determined.
+;   At the lowest level (i.e. the "real" one) it will probably take a variable
+;   list of arguments where each argument [perhaps after the standard three of
+;   name, comment, attrs] is "(keyword arg-to-keyword)".  This syntax is simple
+;   and yet completely upward extensible.  And given the macro facility, one
+;   needn't code at that low a level so even though it'll be more verbose than
+;   necessary it won't matter.  This same reasoning can be applied to most
+;   types of entries in this file.
+
+; M32R specific instruction attributes:
+
+; FILL-SLOT: Need next insn to begin on 32 bit boundary.
+; (A "slot" as used here is a 32 bit quantity that can either be filled with
+; one 32 bit insn or two 16 bit insns which go in the "left bin" and "right
+; bin" where the left bin is the one with a lower address).
+
+(define-attr
+  (for insn)
+  (type boolean)
+  (name FILL-SLOT)
+  (comment "fill right bin with `nop' if insn is in left bin")
+)
+
+(define-attr
+  (for insn)
+  (type boolean)
+  (name SPECIAL)
+  (comment "non-public m32rx insn")
+)
+
+(define-attr
+  (for insn)
+  (type boolean)
+  (name SPECIAL_M32R)
+  (comment "non-public m32r insn")
+)
+
+(define-attr
+  (for insn)
+  (type boolean)
+  (name SPECIAL_FLOAT)
+  (comment "floating point insn")
+)
+
+; IDOC attribute for instruction documentation.
+
+(define-attr
+  (for insn)
+  (type enum)
+  (name IDOC)
+  (comment "insn kind for documentation")
+  (attrs META)
+  (values
+   (MEM - () "Memory")
+   (ALU - () "ALU")
+   (BR - () "Branch")
+   (ACCUM - () "Accumulator")
+   (MAC - () "Multiply/Accumulate")
+   (MISC - () "Miscellaneous")
+  )
+)
+
+(define-pmacro (bin-op mnemonic op2-op sem-op imm-prefix imm)
+  (begin
+     (dni mnemonic
+         (.str mnemonic " reg/reg")
+         ((PIPE OS) (IDOC ALU))
+         (.str mnemonic " $dr,$sr")
+         (+ OP1_0 op2-op dr sr)
+         (set dr (sem-op dr sr))
+         ()
+     )
+     (dni (.sym mnemonic "3")
+         (.str mnemonic " reg/" imm)
+         ((IDOC ALU))
+         (.str mnemonic "3 $dr,$sr," imm-prefix "$" imm)
+         (+ OP1_8 op2-op dr sr imm)
+         (set dr (sem-op sr imm))
+         ()
+     )
+   )
+)
+(bin-op add OP2_10 add "$hash" slo16)
+; sub isn't present because sub3 doesn't exist.
+(bin-op and OP2_12 and "" uimm16)
+(bin-op or OP2_14 or "$hash" ulo16)
+(bin-op xor OP2_13 xor "" uimm16)
+
+(dni addi "addi"
+     ((PIPE OS) (IDOC ALU))
+     ;#.(string-append "addi " "$dr,$simm8") ; #. experiment
+     "addi $dr,$simm8"
+     (+ OP1_4 dr simm8)
+     (set dr (add dr simm8))
+     ((m32r/d (unit u-exec))
+      (m32rx (unit u-exec))
+      (m32r2 (unit u-exec)))
+)
+
+(dni addv "addv"
+     ((PIPE OS) (IDOC ALU))
+     "addv $dr,$sr"
+     (+ OP1_0 OP2_8 dr sr)
+     (parallel ()
+              (set dr (add dr sr))
+              (set condbit (add-oflag dr sr (const 0))))
+     ()
+)
+
+(dni addv3 "addv3"
+     ((IDOC ALU))
+     "addv3 $dr,$sr,$simm16"
+     (+ OP1_8 OP2_8 dr sr simm16)
+     (parallel ()
+              (set dr (add sr simm16))
+              (set condbit (add-oflag sr simm16 (const 0))))
+     ()
+)
+
+(dni addx "addx"
+     ((PIPE OS) (IDOC ALU))
+     "addx $dr,$sr"
+     (+ OP1_0 OP2_9 dr sr)
+     (parallel ()
+              (set dr (addc dr sr condbit))
+              (set condbit (add-cflag dr sr condbit)))
+     ()
+)
+
+(dni bc8 "bc with 8 bit displacement"
+     (COND-CTI (PIPE O) (IDOC BR))
+     "bc.s $disp8"
+     (+ OP1_7 (f-r1 12) disp8)
+     (if condbit (set pc disp8))
+     ((m32r/d (unit u-cti))
+      (m32rx (unit u-cti))
+      (m32r2 (unit u-cti)))
+)
+
+(dnmi bc8r "relaxable bc8"
+     (COND-CTI RELAXABLE (PIPE O) (IDOC BR))
+     "bc $disp8"
+     (emit bc8 disp8)
+)
+
+(dni bc24 "bc with 24 bit displacement"
+     (COND-CTI (IDOC BR))
+     "bc.l $disp24"
+     (+ OP1_15 (f-r1 12) disp24)
+     (if condbit (set pc disp24))
+     ((m32r/d (unit u-cti))
+      (m32rx (unit u-cti))
+      (m32r2 (unit u-cti)))
+)
+
+(dnmi bc24r "relaxable bc24"
+     (COND-CTI RELAXED (IDOC BR))
+     "bc $disp24"
+     (emit bc24 disp24)
+)
+
+(dni beq "beq"
+     (COND-CTI (IDOC BR))
+     "beq $src1,$src2,$disp16"
+     (+ OP1_11 OP2_0 src1 src2 disp16)
+     (if (eq src1 src2) (set pc disp16))
+     ((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
+      (m32rx (unit u-cti) (unit u-cmp (cycles 0)))
+      (m32r2 (unit u-cti) (unit u-cmp (cycles 0))))
+)
+
+(define-pmacro (cbranch sym comment op2-op comp-op)
+  (dni sym comment (COND-CTI (IDOC BR))
+       (.str sym " $src2,$disp16")
+       (+ OP1_11 op2-op (f-r1 0) src2 disp16)
+       (if (comp-op src2 (const WI 0)) (set pc disp16))
+       ((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
+        (m32rx (unit u-cti) (unit u-cmp (cycles 0)))
+        (m32r2 (unit u-cti) (unit u-cmp (cycles 0))))
+       )
+)
+(cbranch beqz "beqz" OP2_8 eq)
+(cbranch bgez "bgez" OP2_11 ge)
+(cbranch bgtz "bgtz" OP2_13 gt)
+(cbranch blez "blez" OP2_12 le)
+(cbranch bltz "bltz" OP2_10 lt)
+(cbranch bnez "bnez" OP2_9 ne)
+
+(dni bl8 "bl with 8 bit displacement"
+     (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR))
+     "bl.s $disp8"
+     (+ OP1_7 (f-r1 14) disp8)
+     (sequence ()
+              (set (reg h-gr 14)
+                   (add (and pc (const -4)) (const 4)))
+              (set pc disp8))
+     ((m32r/d (unit u-cti))
+      (m32rx (unit u-cti))
+      (m32r2 (unit u-cti)))
+)
+
+(dnmi bl8r "relaxable bl8"
+     (UNCOND-CTI FILL-SLOT RELAXABLE (PIPE O) (IDOC BR))
+     "bl $disp8"
+     (emit bl8 disp8)
+)
+
+(dni bl24 "bl with 24 bit displacement"
+     (UNCOND-CTI (IDOC BR))
+     "bl.l $disp24"
+     (+ OP1_15 (f-r1 14) disp24)
+     (sequence ()
+              (set (reg h-gr 14) (add pc (const 4)))
+              (set pc disp24))
+     ((m32r/d (unit u-cti))
+      (m32rx (unit u-cti))
+      (m32r2 (unit u-cti)))
+)
+
+(dnmi bl24r "relaxable bl24"
+     (UNCOND-CTI RELAXED (IDOC BR))
+     "bl $disp24"
+     (emit bl24 disp24)
+)
+
+(dni bcl8 "bcl with 8 bit displacement"
+     (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR))
+     "bcl.s $disp8"
+     (+ OP1_7 (f-r1 8) disp8)
+     (if condbit
+         (sequence ()
+                  (set (reg h-gr 14)
+                       (add (and pc (const -4))
+                            (const 4)))
+                  (set pc disp8)))
+     ((m32rx (unit u-cti))
+      (m32r2 (unit u-cti)))
+)
+
+(dnmi bcl8r "relaxable bcl8"
+     (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR))
+     "bcl $disp8"
+     (emit bcl8 disp8)
+)
+
+(dni bcl24 "bcl with 24 bit displacement"
+     (COND-CTI (MACH m32rx,m32r2) (IDOC BR))
+     "bcl.l $disp24"
+     (+ OP1_15 (f-r1 8) disp24)
+     (if condbit
+         (sequence ()
+                  (set (reg h-gr 14) (add pc (const 4)))
+                  (set pc disp24)))
+     ((m32rx (unit u-cti))
+      (m32r2 (unit u-cti)))
+)
+
+(dnmi bcl24r "relaxable bcl24"
+     (COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR))
+     "bcl $disp24"
+     (emit bcl24 disp24)
+)
+
+(dni bnc8 "bnc with 8 bit displacement"
+     (COND-CTI (PIPE O) (IDOC BR))
+     "bnc.s $disp8"
+     (+ OP1_7 (f-r1 13) disp8)
+     (if (not condbit) (set pc disp8))
+     ((m32r/d (unit u-cti))
+      (m32rx (unit u-cti))
+      (m32r2 (unit u-cti)))
+)
+
+(dnmi bnc8r "relaxable bnc8"
+     (COND-CTI RELAXABLE (PIPE O) (IDOC BR))
+     "bnc $disp8"
+     (emit bnc8 disp8)
+)
+
+(dni bnc24 "bnc with 24 bit displacement"
+     (COND-CTI (IDOC BR))
+     "bnc.l $disp24"
+     (+ OP1_15 (f-r1 13) disp24)
+     (if (not condbit) (set pc disp24))
+     ((m32r/d (unit u-cti))
+      (m32rx (unit u-cti))
+      (m32r2 (unit u-cti)))
+)
+
+(dnmi bnc24r "relaxable bnc24"
+     (COND-CTI RELAXED (IDOC BR))
+     "bnc $disp24"
+     (emit bnc24 disp24)
+)
+
+(dni bne "bne"
+     (COND-CTI (IDOC BR))
+     "bne $src1,$src2,$disp16"
+     (+ OP1_11 OP2_1 src1 src2 disp16)
+     (if (ne src1 src2) (set pc disp16))
+     ((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
+      (m32rx (unit u-cti) (unit u-cmp (cycles 0)))
+      (m32r2 (unit u-cti) (unit u-cmp (cycles 0))))
+)
+
+(dni bra8 "bra with 8 bit displacement"
+     (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR))
+     "bra.s $disp8"
+     (+ OP1_7 (f-r1 15) disp8)
+     (set pc disp8)
+     ((m32r/d (unit u-cti))
+      (m32rx (unit u-cti))
+      (m32r2 (unit u-cti)))
+)
+
+(dnmi bra8r "relaxable bra8"
+     (UNCOND-CTI FILL-SLOT RELAXABLE (PIPE O) (IDOC BR))
+     "bra $disp8"
+     (emit bra8 disp8)
+)
+
+(dni bra24 "bra with 24 displacement"
+     (UNCOND-CTI (IDOC BR))
+     "bra.l $disp24"
+     (+ OP1_15 (f-r1 15) disp24)
+     (set pc disp24)
+     ((m32r/d (unit u-cti))
+      (m32rx (unit u-cti))
+      (m32r2 (unit u-cti)))
+)
+
+(dnmi bra24r "relaxable bra24"
+     (UNCOND-CTI RELAXED (IDOC BR))
+     "bra $disp24"
+     (emit bra24 disp24)
+)
+
+(dni bncl8 "bncl with 8 bit displacement"
+     (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR))
+     "bncl.s $disp8"
+     (+ OP1_7 (f-r1 9) disp8)
+     (if (not condbit) 
+         (sequence ()
+                  (set (reg h-gr 14)
+                       (add (and pc (const -4))
+                            (const 4)))
+                  (set pc disp8)))
+     ((m32rx (unit u-cti))
+      (m32r2 (unit u-cti)))
+)
+
+(dnmi bncl8r "relaxable bncl8"
+     (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR))
+     "bncl $disp8"
+     (emit bncl8 disp8)
+)
+
+(dni bncl24 "bncl with 24 bit displacement"
+     (COND-CTI (MACH m32rx,m32r2) (IDOC BR))
+     "bncl.l $disp24"
+     (+ OP1_15 (f-r1 9) disp24)
+     (if (not condbit)
+         (sequence ()
+                  (set (reg h-gr 14) (add pc (const 4)))
+                  (set pc disp24)))
+     ((m32rx (unit u-cti))
+      (m32r2 (unit u-cti)))
+)
+
+(dnmi bncl24r "relaxable bncl24"
+     (COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR))
+     "bncl $disp24"
+     (emit bncl24 disp24)
+)
+
+(dni cmp "cmp"
+     ((PIPE OS) (IDOC ALU))
+     "cmp $src1,$src2"
+     (+ OP1_0 OP2_4 src1 src2)
+     (set condbit (lt src1 src2))
+     ((m32r/d (unit u-cmp))
+      (m32rx (unit u-cmp))
+      (m32r2 (unit u-cmp)))
+)
+
+(dni cmpi "cmpi"
+     ((IDOC ALU))
+     "cmpi $src2,$simm16"
+     (+ OP1_8 (f-r1 0) OP2_4 src2 simm16)
+     (set condbit (lt src2 simm16))
+     ((m32r/d (unit u-cmp))
+      (m32rx (unit u-cmp))
+      (m32r2 (unit u-cmp)))
+)
+
+(dni cmpu "cmpu"
+     ((PIPE OS) (IDOC ALU))
+     "cmpu $src1,$src2"
+     (+ OP1_0 OP2_5 src1 src2)
+     (set condbit (ltu src1 src2))
+     ((m32r/d (unit u-cmp))
+      (m32rx (unit u-cmp))
+      (m32r2 (unit u-cmp)))
+)
+
+(dni cmpui "cmpui"
+     ((IDOC ALU))
+     "cmpui $src2,$simm16"
+     (+ OP1_8 (f-r1 0) OP2_5 src2 simm16)
+     (set condbit (ltu src2 simm16))
+     ((m32r/d (unit u-cmp))
+      (m32rx (unit u-cmp))
+      (m32r2 (unit u-cmp)))
+)
+
+(dni cmpeq "cmpeq"
+     ((MACH m32rx,m32r2) (PIPE OS) (IDOC ALU))
+     "cmpeq $src1,$src2"
+     (+ OP1_0 OP2_6 src1 src2)
+     (set condbit (eq src1 src2))
+     ((m32rx (unit u-cmp))
+      (m32r2 (unit u-cmp)))
+)
+
+(dni cmpz "cmpz"
+     ((MACH m32rx,m32r2) (PIPE OS) (IDOC ALU))
+     "cmpz $src2"
+     (+ OP1_0 OP2_7 (f-r1 0) src2)
+     (set condbit (eq src2 (const 0)))
+     ((m32rx (unit u-cmp))
+      (m32r2 (unit u-cmp)))
+)
+
+(dni div "div"
+     ((IDOC ALU))
+     "div $dr,$sr"
+     (+ OP1_9 OP2_0 dr sr (f-simm16 0))
+     (if (ne sr (const 0)) (set dr (div dr sr)))
+     ((m32r/d (unit u-exec (cycles 37)))
+      (m32rx (unit u-exec (cycles 37)))
+      (m32r2 (unit u-exec (cycles 37))))
+)
+
+(dni divu "divu"
+     ((IDOC ALU))
+     "divu $dr,$sr"
+     (+ OP1_9 OP2_1 dr sr (f-simm16 0))
+     (if (ne sr (const 0)) (set dr (udiv dr sr)))
+     ((m32r/d (unit u-exec (cycles 37)))
+      (m32rx (unit u-exec (cycles 37)))
+      (m32r2 (unit u-exec (cycles 37))))
+)
+
+(dni rem "rem"
+     ((IDOC ALU))
+     "rem $dr,$sr"
+     (+ OP1_9 OP2_2 dr sr (f-simm16 0))
+     ; FIXME: Check rounding direction.
+     (if (ne sr (const 0)) (set dr (mod dr sr)))
+     ((m32r/d (unit u-exec (cycles 37)))
+      (m32rx (unit u-exec (cycles 37)))
+      (m32r2 (unit u-exec (cycles 37))))
+)
+
+(dni remu "remu"
+     ((IDOC ALU))
+     "remu $dr,$sr"
+     (+ OP1_9 OP2_3 dr sr (f-simm16 0))
+     ; FIXME: Check rounding direction.
+     (if (ne sr (const 0)) (set dr (umod dr sr)))
+     ((m32r/d (unit u-exec (cycles 37)))
+      (m32rx (unit u-exec (cycles 37)))
+      (m32r2 (unit u-exec (cycles 37))))
+)
+
+(dni remh "remh"
+     ((MACH m32r2))
+     "remh $dr,$sr"
+     (+ OP1_9 OP2_2 dr sr (f-simm16 #x10))
+     ; FIXME: Check rounding direction.
+     (if (ne sr (const 0)) (set dr (mod (ext WI (trunc HI dr)) sr)))
+     ((m32r2 (unit u-exec (cycles 21))))
+)
+
+(dni remuh "remuh"
+     ((MACH m32r2))
+     "remuh $dr,$sr"
+     (+ OP1_9 OP2_3 dr sr (f-simm16 #x10))
+     ; FIXME: Check rounding direction.
+     (if (ne sr (const 0)) (set dr (umod dr sr)))
+     ((m32r2 (unit u-exec (cycles 21))))
+)
+
+(dni remb "remb"
+     ((MACH m32r2))
+     "remb $dr,$sr"
+     (+ OP1_9 OP2_2 dr sr (f-simm16 #x18))
+     ; FIXME: Check rounding direction.
+     (if (ne sr (const 0)) (set dr (mod (ext WI (trunc BI dr)) sr)))
+     ((m32r2 (unit u-exec (cycles 21))))
+)
+
+(dni remub "remub"
+     ((MACH m32r2))
+     "remub $dr,$sr"
+     (+ OP1_9 OP2_3 dr sr (f-simm16 #x18))
+     ; FIXME: Check rounding direction.
+     (if (ne sr (const 0)) (set dr (umod dr sr)))
+     ((m32r2 (unit u-exec (cycles 21))))
+)
+
+(dni divuh "divuh"
+     ((MACH m32r2))
+     "divuh $dr,$sr"
+     (+ OP1_9 OP2_1 dr sr (f-simm16 #x10))
+     (if (ne sr (const 0)) (set dr (udiv dr sr)))
+     ((m32r2 (unit u-exec (cycles 21))))
+)
+
+(dni divb "divb"
+     ((MACH m32r2))
+     "divb $dr,$sr"
+     (+ OP1_9 OP2_0 dr sr (f-simm16 #x18))
+     (if (ne sr (const 0)) (set dr (div (ext WI (trunc BI dr)) sr)))
+     ((m32r2 (unit u-exec (cycles 21))))
+)
+
+(dni divub "divub"
+     ((MACH m32r2))
+     "divub $dr,$sr"
+     (+ OP1_9 OP2_1 dr sr (f-simm16 #x18))
+     (if (ne sr (const 0)) (set dr (udiv dr sr)))
+     ((m32r2 (unit u-exec (cycles 21))))
+)
+
+(dni divh "divh"
+     ((MACH m32rx,m32r2) (IDOC ALU))
+     "divh $dr,$sr"
+     (+ OP1_9 OP2_0 dr sr (f-simm16 #x10))
+     (if (ne sr (const 0)) (set dr (div (ext WI (trunc HI dr)) sr)))
+     ((m32rx (unit u-exec (cycles 21)))
+      (m32r2 (unit u-exec (cycles 21))))
+)
+
+(dni jc "jc"
+     (COND-CTI (MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
+     "jc $sr"
+     (+ OP1_1 (f-r1 12) OP2_12 sr)
+     (if condbit (set pc (and sr (const -4))))
+     ((m32rx (unit u-cti))
+      (m32r2 (unit u-cti)))
+)
+
+(dni jnc "jnc"
+     (COND-CTI (MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
+     "jnc $sr"
+     (+ OP1_1 (f-r1 13) OP2_12 sr)
+     (if (not condbit) (set pc (and sr (const -4))))
+     ((m32rx (unit u-cti))
+      (m32r2 (unit u-cti)))
+)
+
+(dni jl "jl"
+     (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR))
+     "jl $sr"
+     (+ OP1_1 (f-r1 14) OP2_12 sr)
+     (parallel ()
+              (set (reg h-gr 14)
+                   (add (and pc (const -4)) (const 4)))
+              (set pc (and sr (const -4))))
+     ((m32r/d (unit u-cti))
+      (m32rx (unit u-cti))
+      (m32r2 (unit u-cti)))
+)
+
+(dni jmp "jmp"
+     (UNCOND-CTI (PIPE O) (IDOC BR))
+     "jmp $sr"
+     (+ OP1_1 (f-r1 15) OP2_12 sr)
+     (set pc (and sr (const -4)))
+     ; The above works now so this kludge has been commented out.
+     ; It's kept around because the f-r1 reference in the semantic part
+     ; should work.
+     ; FIXME: kludge, instruction decoding not finished.
+     ; But this should work, so that's another FIXME.
+     ;(sequence VOID (if VOID (eq SI f-r1 (const SI 14))
+     ; FIXME: abuf->insn should be a macro of some sort.
+     ;(sequence VOID
+     ;        (if VOID (eq SI (c-code SI "((abuf->insn >> 8) & 15)")
+     ;                   (const SI 14))
+     ;            (set WI (reg WI h-gr 14)
+     ;                 (add WI (and WI pc (const WI -4)) (const WI 4))))
+     ;        (set WI pc sr))
+     ((m32r/d (unit u-cti))
+      (m32rx (unit u-cti))
+      (m32r2 (unit u-cti)))
+)
+
+(define-pmacro (no-ext-expr mode expr) expr)
+(define-pmacro (ext-expr mode expr) (ext mode expr))
+(define-pmacro (zext-expr mode expr) (zext mode expr))
+
+(define-pmacro (load-op suffix op2-op mode ext-op)
+  (begin
+    (dni (.sym ld suffix) (.str "ld" suffix)
+        ((PIPE O) (IDOC MEM))
+        (.str "ld" suffix " $dr,@$sr")
+        (+ OP1_2 op2-op dr sr)
+        (set dr (ext-op WI (mem mode sr)))
+        ((m32r/d (unit u-load))
+         (m32rx (unit u-load))
+         (m32r2 (unit u-load)))
+        )
+    (dnmi (.sym ld suffix "-2") (.str "ld" suffix "-2")
+         (NO-DIS (PIPE O) (IDOC MEM))
+         (.str "ld" suffix " $dr,@($sr)")
+         (emit (.sym ld suffix) dr sr))
+    (dni (.sym ld suffix -d) (.str "ld" suffix "-d")
+        ((IDOC MEM))
+        (.str "ld" suffix " $dr,@($slo16,$sr)")
+        (+ OP1_10 op2-op dr sr slo16)
+        (set dr (ext-op WI (mem mode (add sr slo16))))
+        ((m32r/d (unit u-load (cycles 2)))
+         (m32rx (unit u-load (cycles 2)))
+         (m32r2 (unit u-load (cycles 2))))
+        )
+    (dnmi (.sym ld suffix -d2) (.str "ld" suffix "-d2")
+         (NO-DIS (IDOC MEM))
+         (.str "ld" suffix " $dr,@($sr,$slo16)")
+         (emit (.sym ld suffix -d) dr sr slo16))
+    )
+)
+(load-op "" OP2_12 WI no-ext-expr)
+(load-op b OP2_8 QI ext-expr)
+(load-op h OP2_10 HI ext-expr)
+(load-op ub OP2_9 QI zext-expr)
+(load-op uh OP2_11 HI zext-expr)
+
+(dni ld-plus "ld+"
+     ((PIPE O) (IDOC MEM))
+     "ld $dr,@$sr+"
+     (+ OP1_2 dr OP2_14 sr)
+     (parallel ()
+              ; wip: memory addresses in profiling support
+              ;(set dr (name ld-mem (mem WI sr)))
+              (set dr (mem WI sr))
+              (set sr (add sr (const 4))))
+     ; Note: `pred' is the constraint.  Also useful here is (ref name)
+     ; and returns true if operand <name> was referenced
+     ; (where "referenced" means _read_ if input operand and _written_ if
+     ; output operand).
+     ; args to unit are "unit-name (name1 value1) ..."
+     ; - cycles(done),issue,pred are also specified this way
+     ; - if unspecified, default is used
+     ; - for ins/outs, extra arg is passed that says what was specified
+     ;   - this is AND'd with `written' for outs
+     ((m32r/d (unit u-load (pred (const 1)))
+             (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1))))
+      (m32rx (unit u-load)
+            (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1))))
+      (m32r2 (unit u-load)
+            (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1))))
+      )
+)
+
+(dnmi pop "pop"
+      ((PIPE O) (IDOC MEM))
+      "pop $dr"
+      (emit ld-plus dr (sr 15)) ; "ld %0,@sp+"
+)
+
+(dni ld24 "ld24"
+     ((IDOC MEM))
+     "ld24 $dr,$uimm24"
+     (+ OP1_14 dr uimm24)
+     (set dr uimm24)
+     ()
+)
+
+; ldi8 appears before ldi16 so we try the shorter version first
+
+(dni ldi8 "ldi8"
+     ((PIPE OS) (IDOC ALU))
+     "ldi8 $dr,$simm8"
+     (+ OP1_6 dr simm8)
+     (set dr simm8)
+     ()
+)
+
+(dnmi ldi8a "ldi8 alias"
+     ((PIPE OS) (IDOC ALU))
+     "ldi $dr,$simm8"
+     (emit ldi8 dr simm8)
+)
+
+(dni ldi16 "ldi16"
+     ((IDOC ALU))
+     "ldi16 $dr,$hash$slo16"
+     (+ OP1_9 OP2_15 (f-r2 0) dr slo16)
+     (set dr slo16)
+     ()
+)
+
+(dnmi ldi16a "ldi16 alias"
+     ((IDOC ALU))
+     "ldi $dr,$hash$slo16"
+     (emit ldi16 dr slo16)
+)
+
+(dni lock "lock"
+     ((PIPE O) (IDOC MISC))
+     "lock $dr,@$sr"
+     (+ OP1_2 OP2_13 dr sr)
+     (sequence ()
+              (set (reg h-lock) (const BI 1))
+              (set dr (mem WI sr)))
+     ((m32r/d (unit u-load))
+      (m32rx (unit u-load))
+      (m32r2 (unit u-load)))
+)
+
+(dni machi "machi"
+     (
+      ; (MACH m32r) is a temporary hack.  This insn collides with machi-a
+      ; in the simulator so disable it for m32rx.
+      (MACH m32r) (PIPE S) (IDOC MAC)
+     )
+     "machi $src1,$src2"
+     (+ OP1_3 OP2_4 src1 src2)
+     ; FIXME: TRACE_RESULT will print the wrong thing since we
+     ; alter one of the arguments.
+     (set accum
+         (sra DI
+              (sll DI
+                   (add DI
+                        accum
+                        (mul DI
+                             (ext DI (and WI src1 (const #xffff0000)))
+                             (ext DI (trunc HI (sra WI src2 (const 16))))))
+                   (const 8))
+              (const 8)))
+     ((m32r/d (unit u-mac)))
+)
+
+(dni machi-a "machi-a"
+     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
+     "machi $src1,$src2,$acc"
+     (+ OP1_3 src1 acc (f-op23 4) src2)
+     (set acc
+         (sra DI
+              (sll DI
+                   (add DI
+                        acc
+                        (mul DI
+                             (ext DI (and WI src1 (const #xffff0000)))
+                             (ext DI (trunc HI (sra WI src2 (const 16))))))
+                   (const 8))
+              (const 8)))
+     ((m32rx (unit u-mac))
+      (m32r2 (unit u-mac)))
+)
+
+(dni maclo "maclo"
+     ((MACH m32r) (PIPE S) (IDOC MAC))
+     "maclo $src1,$src2"
+     (+ OP1_3 OP2_5 src1 src2)
+     (set accum
+         (sra DI
+              (sll DI
+                   (add DI
+                        accum
+                        (mul DI
+                             (ext DI (sll WI src1 (const 16)))
+                             (ext DI (trunc HI src2))))
+                   (const 8))
+              (const 8)))
+     ((m32r/d (unit u-mac)))
+)
+
+(dni maclo-a "maclo-a"
+     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
+     "maclo $src1,$src2,$acc"
+     (+ OP1_3 src1 acc (f-op23 5) src2)
+     (set acc
+         (sra DI
+              (sll DI
+                   (add DI
+                        acc
+                        (mul DI
+                             (ext DI (sll WI src1 (const 16)))
+                             (ext DI (trunc HI src2))))
+                   (const 8))
+              (const 8)))
+     ((m32rx (unit u-mac))
+      (m32r2 (unit u-mac)))
+)
+
+(dni macwhi "macwhi"
+     ((MACH m32r) (PIPE S) (IDOC MAC))
+     "macwhi $src1,$src2"
+     (+ OP1_3 OP2_6 src1 src2)
+     (set accum
+         (sra DI
+              (sll DI
+                   (add DI
+                        accum
+                        (mul DI
+                             (ext DI src1)
+                             (ext DI (trunc HI (sra WI src2 (const 16))))))
+                   (const 8))
+              (const 8)))
+     ((m32r/d (unit u-mac)))
+)
+
+(dni macwhi-a "macwhi-a"
+     ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC MAC))
+     "macwhi $src1,$src2,$acc"
+     (+ OP1_3 src1 acc (f-op23 6) src2)
+     ; Note that this doesn't do the sign extension, which is correct.
+     (set acc
+         (add acc
+              (mul (ext DI src1)
+                   (ext DI (trunc HI (sra src2 (const 16)))))))
+     ((m32rx (unit u-mac))
+      (m32r2 (unit u-mac)))
+)
+
+(dni macwlo "macwlo"
+     ((MACH m32r) (PIPE S) (IDOC MAC))
+     "macwlo $src1,$src2"
+     (+ OP1_3 OP2_7 src1 src2)
+     (set accum
+         (sra DI
+              (sll DI
+                   (add DI
+                        accum
+                        (mul DI
+                             (ext DI src1)
+                             (ext DI (trunc HI src2))))
+                   (const 8))
+              (const 8)))
+     ((m32r/d (unit u-mac)))
+)
+
+(dni macwlo-a "macwlo-a"
+     ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC MAC))
+     "macwlo $src1,$src2,$acc"
+     (+ OP1_3 src1 acc (f-op23 7) src2)
+     ; Note that this doesn't do the sign extension, which is correct.
+     (set acc
+         (add acc
+              (mul (ext DI src1)
+                   (ext DI (trunc HI src2)))))
+     ((m32rx (unit u-mac))
+      (m32r2 (unit u-mac)))
+)
+
+(dni mul "mul"
+     ((PIPE S) (IDOC ALU))
+     "mul $dr,$sr"
+     (+ OP1_1 OP2_6 dr sr)
+     (set dr (mul dr sr))
+     ((m32r/d (unit u-exec (cycles 4)))
+      (m32rx (unit u-exec (cycles 4)))
+      (m32r2 (unit u-exec (cycles 4))))
+)
+
+(dni mulhi "mulhi"
+     ((MACH m32r) (PIPE S) (IDOC ACCUM))
+     "mulhi $src1,$src2"
+     (+ OP1_3 OP2_0 src1 src2)
+     (set accum
+         (sra DI
+              (sll DI
+                   (mul DI
+                        (ext DI (and WI src1 (const #xffff0000)))
+                        (ext DI (trunc HI (sra WI src2 (const 16)))))
+                   (const 16))
+              (const 16)))
+     ((m32r/d (unit u-mac)))
+)
+
+(dni mulhi-a "mulhi-a"
+     ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
+     "mulhi $src1,$src2,$acc"
+     (+ OP1_3 (f-op23 0) src1 acc src2)
+     (set acc
+         (sra DI
+              (sll DI
+                   (mul DI
+                        (ext DI (and WI src1 (const #xffff0000)))
+                        (ext DI (trunc HI (sra WI src2 (const 16)))))
+                   (const 16))
+              (const 16)))
+     ((m32rx (unit u-mac))
+      (m32r2 (unit u-mac)))
+)
+
+(dni mullo "mullo"
+     ((MACH m32r) (PIPE S) (IDOC ACCUM))
+     "mullo $src1,$src2"
+     (+ OP1_3 OP2_1 src1 src2)
+     (set accum
+         (sra DI
+              (sll DI
+                   (mul DI
+                        (ext DI (sll WI src1 (const 16)))
+                        (ext DI (trunc HI src2)))
+                   (const 16))
+              (const 16)))
+     ((m32r/d (unit u-mac)))
+)
+
+(dni mullo-a "mullo-a"
+     ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
+     "mullo $src1,$src2,$acc"
+     (+ OP1_3 src1 acc (f-op23 1) src2)
+     (set acc
+         (sra DI
+              (sll DI
+                   (mul DI
+                        (ext DI (sll WI src1 (const 16)))
+                        (ext DI (trunc HI src2)))
+                   (const 16))
+              (const 16)))
+     ((m32rx (unit u-mac))
+      (m32r2 (unit u-mac)))
+)
+
+(dni mulwhi "mulwhi"
+     ((MACH m32r) (PIPE S) (IDOC ACCUM))
+     "mulwhi $src1,$src2"
+     (+ OP1_3 OP2_2 src1 src2)
+     (set accum
+         (sra DI
+              (sll DI
+                   (mul DI
+                        (ext DI src1)
+                        (ext DI (trunc HI (sra WI src2 (const 16)))))
+                   (const 8))
+              (const 8)))
+     ((m32r/d (unit u-mac)))
+)
+
+(dni mulwhi-a "mulwhi-a"
+     ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC ACCUM))
+     "mulwhi $src1,$src2,$acc"
+     (+ OP1_3 src1 acc (f-op23 2) src2)
+     ; Note that this doesn't do the sign extension, which is correct.
+     (set acc
+         (mul (ext DI src1)
+              (ext DI (trunc HI (sra src2 (const 16))))))
+     ((m32rx (unit u-mac))
+      (m32r2 (unit u-mac)))
+)
+
+(dni mulwlo "mulwlo"
+     ((MACH m32r) (PIPE S) (IDOC ACCUM))
+     "mulwlo $src1,$src2"
+     (+ OP1_3 OP2_3 src1 src2)
+     (set accum
+         (sra DI
+              (sll DI
+                   (mul DI
+                        (ext DI src1)
+                        (ext DI (trunc HI src2)))
+                   (const 8))
+              (const 8)))
+     ((m32r/d (unit u-mac)))
+)
+
+(dni mulwlo-a "mulwlo-a"
+     ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC ACCUM))
+     "mulwlo $src1,$src2,$acc"
+     (+ OP1_3 src1 acc (f-op23 3) src2)
+     ; Note that this doesn't do the sign extension, which is correct.
+     (set acc
+         (mul (ext DI src1)
+              (ext DI (trunc HI src2))))
+     ((m32rx (unit u-mac))
+      (m32r2 (unit u-mac)))
+)
+
+(dni mv "mv"
+     ((PIPE OS) (IDOC ALU))
+     "mv $dr,$sr"
+     (+ OP1_1 OP2_8 dr sr)
+     (set dr sr)
+     ()
+)
+
+(dni mvfachi "mvfachi"
+     ((MACH m32r) (PIPE S) (IDOC ACCUM))
+     "mvfachi $dr"
+     (+ OP1_5 OP2_15 (f-r2 0) dr)
+     (set dr (trunc WI (sra DI accum (const 32))))
+     ((m32r/d (unit u-exec (cycles 2))))
+)
+
+(dni mvfachi-a "mvfachi-a"
+     ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
+     "mvfachi $dr,$accs"
+     (+ OP1_5 dr OP2_15 accs (f-op3 0))
+     (set dr (trunc WI (sra DI accs (const 32))))
+     ((m32rx (unit u-exec (cycles 2)))
+      (m32r2 (unit u-exec (cycles 2))))
+)
+
+(dni mvfaclo "mvfaclo"
+     ((MACH m32r) (PIPE S) (IDOC ACCUM))
+     "mvfaclo $dr"
+     (+ OP1_5 OP2_15 (f-r2 1) dr)
+     (set dr (trunc WI accum))
+     ((m32r/d (unit u-exec (cycles 2))))
+)
+
+(dni mvfaclo-a "mvfaclo-a"
+     ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
+     "mvfaclo $dr,$accs"
+     (+ OP1_5 dr OP2_15 accs (f-op3 1))
+     (set dr (trunc WI accs))
+     ((m32rx (unit u-exec (cycles 2)))
+      (m32r2 (unit u-exec (cycles 2))))
+)
+
+(dni mvfacmi "mvfacmi"
+     ((MACH m32r) (PIPE S) (IDOC ACCUM))
+     "mvfacmi $dr"
+     (+ OP1_5 OP2_15 (f-r2 2) dr)
+     (set dr (trunc WI (sra DI accum (const 16))))
+     ((m32r/d (unit u-exec (cycles 2))))
+)
+
+(dni mvfacmi-a "mvfacmi-a"
+     ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
+     "mvfacmi $dr,$accs"
+     (+ OP1_5 dr OP2_15 accs (f-op3 2))
+     (set dr (trunc WI (sra DI accs (const 16))))
+     ((m32rx (unit u-exec (cycles 2)))
+      (m32r2 (unit u-exec (cycles 2))))
+)
+
+(dni mvfc "mvfc"
+     ((PIPE O) (IDOC MISC))
+     "mvfc $dr,$scr"
+     (+ OP1_1 OP2_9 dr scr)
+     (set dr scr)
+     ()
+)
+
+(dni mvtachi "mvtachi"
+     ((MACH m32r) (PIPE S) (IDOC ACCUM))
+     "mvtachi $src1"
+     (+ OP1_5 OP2_7 (f-r2 0) src1)
+     (set accum
+         (or DI
+             (and DI accum (const DI #xffffffff))
+             (sll DI (ext DI src1) (const 32))))
+     ((m32r/d (unit u-exec (in sr src1))))
+)
+
+(dni mvtachi-a "mvtachi-a"
+     ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
+     "mvtachi $src1,$accs"
+     (+ OP1_5 src1 OP2_7 accs (f-op3 0))
+     (set accs
+         (or DI
+             (and DI accs (const DI #xffffffff))
+             (sll DI (ext DI src1) (const 32))))
+     ((m32rx (unit u-exec (in sr src1)))
+      (m32r2 (unit u-exec (in sr src1))))
+)
+
+(dni mvtaclo "mvtaclo"
+     ((MACH m32r) (PIPE S) (IDOC ACCUM))
+     "mvtaclo $src1"
+     (+ OP1_5 OP2_7 (f-r2 1) src1)
+     (set accum
+         (or DI
+             (and DI accum (const DI #xffffffff00000000))
+             (zext DI src1)))
+     ((m32r/d (unit u-exec (in sr src1))))
+)
+
+(dni mvtaclo-a "mvtaclo-a"
+     ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
+     "mvtaclo $src1,$accs"
+     (+ OP1_5 src1 OP2_7 accs (f-op3 1))
+     (set accs
+         (or DI
+             (and DI accs (const DI #xffffffff00000000))
+             (zext DI src1)))
+     ((m32rx (unit u-exec (in sr src1)))
+      (m32r2 (unit u-exec (in sr src1))))
+)
+
+(dni mvtc "mvtc"
+     ((PIPE O) (IDOC MISC))
+     "mvtc $sr,$dcr"
+     (+ OP1_1 OP2_10 dcr sr)
+     (set dcr sr)
+     ()
+)
+
+(dni neg "neg"
+     ((PIPE OS) (IDOC ALU))
+     "neg $dr,$sr"
+     (+ OP1_0 OP2_3 dr sr)
+     (set dr (neg sr))
+     ()
+)
+
+(dni nop "nop"
+     ((PIPE OS) (IDOC MISC))
+     "nop"
+     (+ OP1_7 OP2_0 (f-r1 0) (f-r2 0))
+     (c-code VOID "PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);\n")
+     ; FIXME: quick hack: parallel nops don't contribute to cycle count.
+     ; Other kinds of nops do however (which we currently ignore).
+     ((m32r/d (unit u-exec (cycles 0)))
+      (m32rx (unit u-exec (cycles 0)))
+      (m32r2 (unit u-exec (cycles 0))))
+)
+
+(dni not "not"
+     ((PIPE OS) (IDOC ALU))
+     "not $dr,$sr"
+     (+ OP1_0 OP2_11 dr sr)
+     (set dr (inv sr))
+     ()
+)
+
+(dni rac "rac"
+     ((MACH m32r) (PIPE S) (IDOC MAC))
+     "rac"
+     (+ OP1_5 OP2_9 (f-r1 0) (f-r2 0))
+     (sequence ((DI tmp1))
+              (set tmp1 (sll DI accum (const 1)))
+              (set tmp1 (add DI tmp1 (const DI #x8000)))
+              (set accum
+                   (cond DI
+                         ((gt tmp1 (const DI #x00007fffffff0000))
+                          (const DI #x00007fffffff0000))
+                         ((lt tmp1 (const DI #xffff800000000000))
+                          (const DI #xffff800000000000))
+                         (else (and tmp1 (const DI #xffffffffffff0000)))))
+              )
+     ((m32r/d (unit u-mac)))
+)
+
+(dni rac-dsi "rac-dsi"
+     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
+     "rac $accd,$accs,$imm1"
+     (+ OP1_5 accd (f-bits67 0) OP2_9 accs (f-bit14 0) imm1)
+     (sequence ((DI tmp1))
+              (set tmp1 (sll accs imm1))
+              (set tmp1 (add tmp1 (const DI #x8000)))
+              (set accd
+                   (cond DI
+                         ((gt tmp1 (const DI #x00007fffffff0000))
+                          (const DI #x00007fffffff0000))
+                         ((lt tmp1 (const DI #xffff800000000000))
+                          (const DI #xffff800000000000))
+                         (else (and tmp1 (const DI #xffffffffffff0000)))))
+              )
+     ((m32rx (unit u-mac))
+      (m32r2 (unit u-mac)))
+)
+
+(dnmi rac-d "rac-d"
+     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
+     "rac $accd"
+     (emit rac-dsi accd (f-accs 0) (f-imm1 0))
+)
+
+(dnmi rac-ds "rac-ds"
+     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
+     "rac $accd,$accs"
+     (emit rac-dsi accd accs (f-imm1 0))
+)
+
+
+(dni rach "rach"
+     ((MACH m32r) (PIPE S) (IDOC MAC))
+     "rach"
+     (+ OP1_5 OP2_8 (f-r1 0) (f-r2 0))
+     (sequence ((DI tmp1))
+              ; Lop off top 8 bits.
+              ; The sign bit we want to use is bit 55 so the 64 bit value
+              ; isn't properly signed which we deal with in the if's below.
+              (set tmp1 (and accum (const DI #xffffffffffffff)))
+              (if (andif (ge tmp1 (const DI #x003fff80000000))
+                         (le tmp1 (const DI #x7fffffffffffff)))
+                  (set tmp1 (const DI #x003fff80000000))
+                  ; else part
+                  (if (andif (ge tmp1 (const DI #x80000000000000))
+                             (le tmp1 (const DI #xffc00000000000)))
+                      (set tmp1 (const DI #xffc00000000000))
+                      (set tmp1 (and (add accum (const DI #x40000000))
+                                     (const DI #xffffffff80000000)))))
+              (set tmp1 (sll tmp1 (const 1)))
+              ; Sign extend top 8 bits.
+              (set accum
+                   ; FIXME: 7?
+                   (sra DI (sll DI tmp1 (const 7)) (const 7)))
+              )
+     ((m32r/d (unit u-mac)))
+)
+
+(dni rach-dsi "rach-dsi"
+     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
+     "rach $accd,$accs,$imm1"
+     (+ OP1_5 accd (f-bits67 0) OP2_8 accs (f-bit14 0) imm1)
+     (sequence ((DI tmp1))
+              (set tmp1 (sll accs imm1))
+              (set tmp1 (add tmp1 (const DI #x80000000)))
+              (set accd
+                   (cond DI
+                         ((gt tmp1 (const DI #x00007fff00000000))
+                          (const DI #x00007fff00000000))
+                         ((lt tmp1 (const DI #xffff800000000000))
+                          (const DI #xffff800000000000))
+                         (else (and tmp1 (const DI #xffffffff00000000)))))
+              )
+     ((m32rx (unit u-mac))
+      (m32r2 (unit u-mac)))
+)
+
+(dnmi rach-d "rach-d"
+     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
+     "rach $accd"
+     (emit rach-dsi accd (f-accs 0) (f-imm1 0))
+)
+
+(dnmi rach-ds "rach-ds"
+     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
+     "rach $accd,$accs"
+     (emit rach-dsi accd accs (f-imm1 0))
+)
+
+(dni rte "rte"
+     (UNCOND-CTI (PIPE O) (IDOC BR))
+     "rte"
+     (+ OP1_1 OP2_13 (f-r1 0) (f-r2 6))
+     (sequence ()
+              ; pc = bpc & -4
+              (set pc (and (reg h-cr 6) (const -4)))
+              ; bpc = bbpc
+              (set (reg h-cr 6) (reg h-cr 14))
+              ; psw = bpsw
+              (set (reg h-psw) (reg h-bpsw))
+              ; bpsw = bbpsw
+              (set (reg h-bpsw) (reg h-bbpsw))
+     )
+     ()
+)
+
+(dni seth "seth"
+     ((IDOC ALU))
+     "seth $dr,$hash$hi16"
+     (+ OP1_13 OP2_12 dr (f-r2 0) hi16)
+     (set dr (sll WI hi16 (const 16)))
+     ()
+)
+
+(define-pmacro (shift-op sym op2-r-op op2-3-op op2-i-op sem-op)
+  (begin
+     (dni sym sym ((PIPE O_OS) (IDOC ALU))
+         (.str sym " $dr,$sr")
+         (+ OP1_1 op2-r-op dr sr)
+         (set dr (sem-op dr (and sr (const 31))))
+         ()
+     )
+     (dni (.sym sym "3") sym ((IDOC ALU))
+         (.str sym "3 $dr,$sr,$simm16")
+         (+ OP1_9 op2-3-op dr sr simm16)
+         (set dr (sem-op sr (and WI simm16 (const 31))))
+         ()
+     )
+     (dni (.sym sym "i") sym ((PIPE O_OS) (IDOC ALU))
+         (.str sym "i $dr,$uimm5")
+         (+ OP1_5 (f-shift-op2 op2-i-op) dr uimm5)
+         (set dr (sem-op dr uimm5))
+         ()
+     )
+   )
+)
+(shift-op sll OP2_4 OP2_12 2 sll)
+(shift-op sra OP2_2 OP2_10 1 sra)
+(shift-op srl OP2_0 OP2_8 0 srl)
+
+(define-pmacro (store-op suffix op2-op mode)
+  (begin
+    (dni (.sym st suffix) (.str "st" suffix)
+        ((PIPE O) (IDOC MEM))
+        (.str "st" suffix " $src1,@$src2")
+        (+ OP1_2 op2-op src1 src2)
+        (set mode (mem mode src2) src1)
+        ((m32r/d (unit u-store (cycles 1)))
+         (m32rx (unit u-store (cycles 1)))
+         (m32r2 (unit u-store (cycles 1))))
+        )
+    (dnmi (.sym st suffix "-2") (.str "st" suffix "-2")
+         (NO-DIS (PIPE O) (IDOC MEM))
+         (.str "st" suffix " $src1,@($src2)")
+         (emit (.sym st suffix) src1 src2))
+    (dni (.sym st suffix -d) (.str "st" suffix "-d")
+        ((IDOC MEM))
+        (.str "st" suffix " $src1,@($slo16,$src2)")
+        (+ OP1_10 op2-op src1 src2 slo16)
+        (set mode (mem mode (add src2 slo16)) src1)
+        ((m32r/d (unit u-store (cycles 2)))
+         (m32rx (unit u-store (cycles 2)))
+         (m32r2 (unit u-store (cycles 2))))
+        )
+    (dnmi (.sym st suffix -d2) (.str "st" suffix "-d2")
+         (NO-DIS (IDOC MEM))
+         (.str "st" suffix " $src1,@($src2,$slo16)")
+         (emit (.sym st suffix -d) src1 src2 slo16))
+    )
+)
+(store-op "" OP2_4 WI)
+(store-op b OP2_0 QI)
+(store-op h OP2_2 HI)
+
+(dni st-plus "st+"
+     ((PIPE O) (IDOC MEM))
+     "st $src1,@+$src2"
+     (+ OP1_2 OP2_6 src1 src2)
+     ; This has to be coded carefully to avoid an "earlyclobber" of src2.
+     (sequence ((WI new-src2))
+              (set new-src2 (add WI src2 (const WI 4)))
+              (set (mem WI new-src2) src1)
+              (set src2 new-src2))
+     ((m32r/d (unit u-store)
+             (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
+      (m32rx (unit u-store)
+            (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
+      (m32r2 (unit u-store)
+            (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
+      )
+)
+
+(dni sth-plus "sth+"
+     ((MACH m32rx,m32r2) (PIPE O) SPECIAL)
+     "sth $src1,@$src2+"
+     (+ OP1_2 OP2_3 src1 src2)
+     ; This has to be coded carefully to avoid an "earlyclobber" of src2.
+     (sequence ((WI new-src2))
+              (set new-src2 src2)
+              (set (mem HI new-src2) src1)
+              (set src2 (add new-src2 (const 2))))
+     ((m32rx (unit u-store)
+           (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
+      (m32r2 (unit u-store)
+           (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
+      )
+)
+
+(dni stb-plus "stb+"
+     ((MACH m32rx,m32r2) (PIPE O) SPECIAL)
+     "stb $src1,@$src2+"
+     (+ OP1_2 OP2_1 src1 src2)
+     ; This has to be coded carefully to avoid an "earlyclobber" of src2.
+     (sequence ((WI new-src2))
+              (set new-src2 src2)
+              (set (mem QI new-src2) src1)
+              (set src2 (add new-src2 (const 1))))
+     ((m32rx (unit u-store)
+           (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
+      (m32r2 (unit u-store)
+           (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
+      )
+)
+
+(dni st-minus "st-"
+     ((PIPE O) (IDOC MEM))
+     "st $src1,@-$src2"
+     (+ OP1_2 OP2_7 src1 src2)
+     ; This is the original way.  It doesn't work for parallel execution
+     ; because of the earlyclobber of src2.
+     ;(sequence ()
+     ;        (set src2 (sub src2 (const 4)))
+     ;        (set (mem WI src2) src1))
+     (sequence ((WI new-src2))
+              (set new-src2 (sub src2 (const 4)))
+              (set (mem WI new-src2) src1)
+              (set src2 new-src2))
+     ((m32r/d (unit u-store)
+             (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
+      (m32rx (unit u-store)
+            (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
+      (m32r2 (unit u-store)
+            (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
+      )
+)
+
+(dnmi push "push" ((PIPE O) (IDOC MEM))
+  "push $src1"
+  (emit st-minus src1 (src2 15)) ; "st %0,@-sp"
+)
+
+(dni sub "sub"
+     ((PIPE OS) (IDOC ALU))
+     "sub $dr,$sr"
+     (+ OP1_0 OP2_2 dr sr)
+     (set dr (sub dr sr))
+     ()
+)
+
+(dni subv "sub:rv"
+     ((PIPE OS) (IDOC ALU))
+     "subv $dr,$sr"
+     (+ OP1_0 OP2_0 dr sr)
+     (parallel ()
+              (set dr (sub dr sr))
+              (set condbit (sub-oflag dr sr (const 0))))
+     ()
+)
+
+(dni subx "sub:rx"
+     ((PIPE OS) (IDOC ALU))
+     "subx $dr,$sr"
+     (+ OP1_0 OP2_1 dr sr)
+     (parallel ()
+              (set dr (subc dr sr condbit))
+              (set condbit (sub-cflag dr sr condbit)))
+     ()
+)
+
+(dni trap "trap"
+     (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC MISC))
+     "trap $uimm4"
+     (+ OP1_1 OP2_15 (f-r1 0) uimm4)
+     (sequence ()
+              ; bbpc = bpc
+              (set (reg h-cr 14) (reg h-cr 6))
+              ; Set bpc to the return address.  Actually it's not quite the
+              ; return address as RTE rounds the address down to a word
+              ; boundary.
+              (set (reg h-cr 6) (add pc (const 4)))
+              ; bbpsw = bpsw
+              (set (reg h-bbpsw) (reg h-bpsw))
+              ; bpsw = psw
+              (set (reg h-bpsw) (reg h-psw))
+              ; sm is unchanged, ie,c are set to zero.
+              (set (reg h-psw) (and (reg h-psw) (const #x80)))
+              ; m32r_trap handles operating vs user mode
+              (set WI pc (c-call WI "m32r_trap" pc uimm4))
+     )
+     ()
+)
+
+(dni unlock "unlock"
+     ((PIPE O) (IDOC MISC))
+     "unlock $src1,@$src2"
+     (+ OP1_2 OP2_5 src1 src2)
+     (sequence ()
+              (if (reg h-lock)
+                  (set (mem WI src2) src1))
+              (set (reg h-lock) (const BI 0)))
+     ((m32r/d (unit u-load))
+      (m32rx (unit u-load))
+      (m32r2 (unit u-load)))
+)
+
+; Saturate into byte.
+(dni satb "satb"
+     ((MACH m32rx,m32r2) (IDOC ALU))
+     "satb $dr,$sr"
+     (+ OP1_8 dr OP2_6 sr (f-uimm16 #x0300))
+     (set dr
+         ; FIXME: min/max would simplify this nicely of course.
+         (cond WI
+               ((ge sr (const 127)) (const 127))
+               ((le sr (const -128)) (const -128))
+               (else sr)))
+     ()
+)
+
+; Saturate into half word.
+(dni sath "sath"
+     ((MACH m32rx,m32r2) (IDOC ALU))
+     "sath $dr,$sr"
+     (+ OP1_8 dr OP2_6 sr (f-uimm16 #x0200))
+     (set dr
+         (cond WI
+               ((ge sr (const 32767)) (const 32767))
+               ((le sr (const -32768)) (const -32768))
+               (else sr)))
+     ()
+)
+
+; Saturate word.
+(dni sat "sat"
+     ((MACH m32rx,m32r2) SPECIAL (IDOC ALU))
+     "sat $dr,$sr"
+     (+ OP1_8 dr OP2_6 sr (f-uimm16 0))
+     (set dr
+         (if WI condbit
+              (if WI (lt sr (const 0))
+                   (const #x7fffffff)
+                   (const #x80000000))
+              sr))
+     ()
+)
+
+; Parallel compare byte zeros.
+; Set C bit in condition register if any byte in source register is zero.
+(dni pcmpbz "pcmpbz"
+     ((MACH m32rx,m32r2) (PIPE OS) SPECIAL (IDOC ALU))
+     "pcmpbz $src2"
+     (+ OP1_0 (f-r1 3) OP2_7 src2)
+     (set condbit
+         (cond BI
+                ((eq (and src2 (const #xff)) (const 0)) (const BI 1))
+                ((eq (and src2 (const #xff00)) (const 0)) (const BI 1))
+                ((eq (and src2 (const #xff0000)) (const 0)) (const BI 1))
+                ((eq (and src2 (const #xff000000)) (const 0)) (const BI 1))
+                (else (const BI 0))))
+     ((m32rx (unit u-cmp))
+      (m32r2 (unit u-cmp)))
+)
+
+; Add accumulators
+(dni sadd "sadd"
+     ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
+     "sadd"
+     (+ OP1_5 (f-r1 0) OP2_14 (f-r2 4))
+     (set (reg h-accums 0)
+         (add (sra (reg h-accums 1) (const 16))
+              (reg h-accums 0)))
+     ((m32rx (unit u-mac))
+      (m32r2 (unit u-mac)))
+)
+
+; Multiply and add into accumulator 1
+(dni macwu1 "macwu1"
+     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
+     "macwu1 $src1,$src2"
+     (+ OP1_5 src1 OP2_11 src2)
+     (set (reg h-accums 1)
+         (sra DI
+               (sll DI
+                     (add DI
+                           (reg h-accums 1)
+                           (mul DI
+                                 (ext DI src1)
+                                 (ext DI (and src2 (const #xffff)))))
+                     (const 8))
+               (const 8)))
+     ((m32rx (unit u-mac))
+      (m32r2 (unit u-mac)))
+)
+
+; Multiply and subtract from accumulator 0
+(dni msblo "msblo"
+     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
+     "msblo $src1,$src2"
+     (+ OP1_5 src1 OP2_13 src2)
+     (set accum
+         (sra DI
+               (sll DI
+                     (sub accum
+                          (sra DI
+                                (sll DI
+                                      (mul DI
+                                            (ext DI (trunc HI src1))
+                                            (ext DI (trunc HI src2)))
+                                      (const 32))
+                                (const 16)))
+                     (const 8))
+               (const 8)))
+     ((m32rx (unit u-mac))
+      (m32r2 (unit u-mac)))
+)
+
+; Multiply into accumulator 1
+(dni mulwu1 "mulwu1"
+     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
+     "mulwu1 $src1,$src2"
+     (+ OP1_5 src1 OP2_10 src2)
+     (set (reg h-accums 1)
+         (sra DI
+               (sll DI
+                     (mul DI
+                           (ext DI src1)
+                           (ext DI (and src2 (const #xffff))))
+                     (const 16))
+               (const 16)))
+     ((m32rx (unit u-mac))
+      (m32r2 (unit u-mac)))
+)
+
+; Multiply and add into accumulator 1
+(dni maclh1 "maclh1"
+     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
+     "maclh1 $src1,$src2"
+     (+ OP1_5 src1 OP2_12 src2)
+     (set (reg h-accums 1)
+         (sra DI
+               (sll DI
+                   (add DI
+                         (reg h-accums 1)
+                         (sll DI
+                               (ext DI
+                                     (mul SI
+                                           (ext SI (trunc HI src1))
+                                           (sra SI src2 (const SI 16))))
+                             (const 16)))
+                   (const 8))
+              (const 8)))
+     ((m32rx (unit u-mac))
+      (m32r2 (unit u-mac)))
+)
+
+; skip instruction if C
+(dni sc "sc"
+     ((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
+     "sc"
+     (+ OP1_7 (f-r1 4) OP2_0 (f-r2 1))
+     (skip (zext INT condbit))
+     ()
+)
+
+; skip instruction if not C
+(dni snc "snc"
+     ((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
+     "snc"
+     (+ OP1_7 (f-r1 5) OP2_0 (f-r2 1))
+     (skip (zext INT (not condbit)))
+     ()
+)
+
+; PSW &= ((~ uimm8) | 0xff00)
+(dni clrpsw "clrpsw"
+     ((PIPE O) SPECIAL_M32R)
+     "clrpsw $uimm8"
+     (+ OP1_7 (f-r1 2) uimm8)
+     (set USI (reg h-cr 0)
+              (and USI (reg h-cr 0)
+                  (or USI (zext SI (inv QI uimm8)) (const #xff00))))
+     ()
+)
+
+; PSW |= (unsigned char) uimm8
+(dni setpsw "setpsw"
+     ((PIPE O) SPECIAL_M32R)
+     "setpsw $uimm8"
+     (+ OP1_7 (f-r1 1) uimm8)
+     (set USI (reg h-cr 0) uimm8)
+     ()
+)
+
+; bset
+(dni bset "bset"
+     (SPECIAL_M32R)
+     "bset $uimm3,@($slo16,$sr)"
+     (+ OP1_10 (f-bit4 0) uimm3 OP2_6 sr slo16)
+     (set QI (mem QI (add sr slo16))
+             (or QI (mem QI (add sr slo16))
+                (sll QI (const 1) (sub (const 7) uimm3))))
+     ()
+)
+
+; bclr
+(dni bclr "bclr"
+     (SPECIAL_M32R)
+     "bclr $uimm3,@($slo16,$sr)"
+     (+ OP1_10 (f-bit4 0) uimm3  OP2_7 sr slo16)
+     (set QI (mem QI (add sr slo16))
+             (and QI (mem QI (add sr slo16))
+                   (inv QI (sll QI (const 1) (sub (const 7) uimm3)))))
+     ()
+)
+
+; btst
+(dni btst "btst"
+     (SPECIAL_M32R (PIPE O))
+     "btst $uimm3,$sr"
+     (+ OP1_0 (f-bit4 0) uimm3 OP2_15 sr)
+     (set condbit (and QI (srl QI sr (sub (const 7) uimm3)) (const 1)))
+     ()
+)

diff --git a/cpu/m32r.opc b/cpu/m32r.opc
new file mode 100644 (file)
index 0000000..3100fee
--- /dev/null
+++ b/cpu/m32r.opc
@@ -0,0 +1,324 @@
+/* M32R opcode support.  -*- C -*-
+
+   Copyright 1998, 1999, 2000, 2001, 2004, 2005, 2007, 2009
+   Free Software Foundation, Inc.
+
+   Contributed by Red Hat Inc; developed under contract from
+   Mitsubishi Electric Corporation.
+
+   This file is part of the GNU Binutils.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+
+/* This file is an addendum to m32r.cpu.  Heavy use of C code isn't
+   appropriate in .cpu files, so it resides here.  This especially applies
+   to assembly/disassembly where parsing/printing can be quite involved.
+   Such things aren't really part of the specification of the cpu, per se,
+   so .cpu files provide the general framework and .opc files handle the
+   nitty-gritty details as necessary.
+
+   Each section is delimited with start and end markers.
+
+   <arch>-opc.h additions use: "-- opc.h"
+   <arch>-opc.c additions use: "-- opc.c"
+   <arch>-asm.c additions use: "-- asm.c"
+   <arch>-dis.c additions use: "-- dis.c"
+   <arch>-ibd.h additions use: "-- ibd.h"  */
+\f
+/* -- opc.h */
+
+#undef  CGEN_DIS_HASH_SIZE
+#define CGEN_DIS_HASH_SIZE 256
+#undef  CGEN_DIS_HASH
+#if 0
+#define X(b) (((unsigned char *) (b))[0] & 0xf0)
+#define CGEN_DIS_HASH(buffer, value) \
+(X (buffer) | \
+ (X (buffer) == 0x40 || X (buffer) == 0xe0 || X (buffer) == 0x60 || X (buffer) == 0x50 ? 0 \
+  : X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \
+  : X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \
+  : ((((unsigned char *) (buffer))[1] & 0xf0) >> 4)))
+#else
+#define CGEN_DIS_HASH(buffer, value) m32r_cgen_dis_hash (buffer, value)
+extern unsigned int m32r_cgen_dis_hash (const char *, CGEN_INSN_INT);
+#endif
+
+/* -- */
+\f
+/* -- opc.c */
+unsigned int
+m32r_cgen_dis_hash (const char * buf ATTRIBUTE_UNUSED, CGEN_INSN_INT value)
+{
+  unsigned int x;
+
+  if (value & 0xffff0000) /* 32bit instructions.  */
+    value = (value >> 16) & 0xffff;
+
+  x = (value >> 8) & 0xf0;
+  if (x == 0x40 || x == 0xe0 || x == 0x60 || x == 0x50)
+    return x;
+
+  if (x == 0x70 || x == 0xf0)
+    return x | ((value >> 8) & 0x0f);
+
+  if (x == 0x30)
+    return x | ((value & 0x70) >> 4);
+  else
+    return x | ((value & 0xf0) >> 4);
+}
+
+/* -- */
+\f
+/* -- asm.c */
+static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'");
+
+/* Handle '#' prefixes (i.e. skip over them).  */
+
+static const char *
+parse_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+           const char **strp,
+           int opindex ATTRIBUTE_UNUSED,
+           long *valuep ATTRIBUTE_UNUSED)
+{
+  if (**strp == '#')
+    ++*strp;
+  return NULL;
+}
+
+/* Handle shigh(), high().  */
+
+static const char *
+parse_hi16 (CGEN_CPU_DESC cd,
+           const char **strp,
+           int opindex,
+           unsigned long *valuep)
+{
+  const char *errmsg;
+  enum cgen_parse_operand_result result_type;
+  bfd_vma value;
+
+  if (**strp == '#')
+    ++*strp;
+
+  if (strncasecmp (*strp, "high(", 5) == 0)
+    {
+      *strp += 5;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_ULO,
+                                  & result_type, & value);
+      if (**strp != ')')
+       return MISSING_CLOSING_PARENTHESIS;
+      ++*strp;
+      if (errmsg == NULL
+         && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+       {
+         value >>= 16;
+         value &= 0xffff;
+       }
+      *valuep = value;
+      return errmsg;
+    }
+  else if (strncasecmp (*strp, "shigh(", 6) == 0)
+    {
+      *strp += 6;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_SLO,
+                                  & result_type, & value);
+      if (**strp != ')')
+       return MISSING_CLOSING_PARENTHESIS;
+      ++*strp;
+      if (errmsg == NULL
+         && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+       {
+         value += 0x8000;
+         value >>= 16;
+         value &= 0xffff;
+       }
+      *valuep = value;
+      return errmsg;
+    }
+
+  return cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
+}
+
+/* Handle low() in a signed context.  Also handle sda().
+   The signedness of the value doesn't matter to low(), but this also
+   handles the case where low() isn't present.  */
+
+static const char *
+parse_slo16 (CGEN_CPU_DESC cd,
+            const char ** strp,
+            int opindex,
+            long * valuep)
+{
+  const char *errmsg;
+  enum cgen_parse_operand_result result_type;
+  bfd_vma value;
+
+  if (**strp == '#')
+    ++*strp;
+
+  if (strncasecmp (*strp, "low(", 4) == 0)
+    {
+      *strp += 4;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16,
+                                  & result_type, & value);
+      if (**strp != ')')
+       return MISSING_CLOSING_PARENTHESIS;
+      ++*strp;
+      if (errmsg == NULL
+         && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+       value = ((value & 0xffff) ^ 0x8000) - 0x8000;
+      *valuep = value;
+      return errmsg;
+    }
+
+  if (strncasecmp (*strp, "sda(", 4) == 0)
+    {
+      *strp += 4;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_SDA16,
+                                  NULL, & value);
+      if (**strp != ')')
+       return MISSING_CLOSING_PARENTHESIS;
+      ++*strp;
+      *valuep = value;
+      return errmsg;
+    }
+
+  return cgen_parse_signed_integer (cd, strp, opindex, valuep);
+}
+
+/* Handle low() in an unsigned context.
+   The signedness of the value doesn't matter to low(), but this also
+   handles the case where low() isn't present.  */
+
+static const char *
+parse_ulo16 (CGEN_CPU_DESC cd,
+            const char **strp,
+            int opindex,
+            unsigned long *valuep)
+{
+  const char *errmsg;
+  enum cgen_parse_operand_result result_type;
+  bfd_vma value;
+
+  if (**strp == '#')
+    ++*strp;
+
+  if (strncasecmp (*strp, "low(", 4) == 0)
+    {
+      *strp += 4;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16,
+                                  & result_type, & value);
+      if (**strp != ')')
+       return MISSING_CLOSING_PARENTHESIS;
+      ++*strp;
+      if (errmsg == NULL
+         && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+       value &= 0xffff;
+      *valuep = value;
+      return errmsg;
+    }
+
+  return cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
+}
+
+/* -- */
+\f
+/* -- dis.c */
+/* Immediate values are prefixed with '#'.  */
+
+#define CGEN_PRINT_NORMAL(cd, info, value, attrs, pc, length)  \
+  do                                                           \
+    {                                                          \
+      if (CGEN_BOOL_ATTR ((attrs), CGEN_OPERAND_HASH_PREFIX))  \
+       (*info->fprintf_func) (info->stream, "#");              \
+    }                                                          \
+  while (0)
+
+/* Handle '#' prefixes as operands.  */
+
+static void
+print_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+           void * dis_info,
+           long value ATTRIBUTE_UNUSED,
+           unsigned int attrs ATTRIBUTE_UNUSED,
+           bfd_vma pc ATTRIBUTE_UNUSED,
+           int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+
+  (*info->fprintf_func) (info->stream, "#");
+}
+
+#undef  CGEN_PRINT_INSN
+#define CGEN_PRINT_INSN my_print_insn
+
+static int
+my_print_insn (CGEN_CPU_DESC cd,
+              bfd_vma pc,
+              disassemble_info *info)
+{
+  bfd_byte buffer[CGEN_MAX_INSN_SIZE];
+  bfd_byte *buf = buffer;
+  int status;
+  int buflen = (pc & 3) == 0 ? 4 : 2;
+  int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
+  bfd_byte *x;
+
+  /* Read the base part of the insn.  */
+
+  status = (*info->read_memory_func) (pc - ((!big_p && (pc & 3) != 0) ? 2 : 0),
+                                     buf, buflen, info);
+  if (status != 0)
+    {
+      (*info->memory_error_func) (status, pc, info);
+      return -1;
+    }
+
+  /* 32 bit insn?  */
+  x = (big_p ? &buf[0] : &buf[3]);
+  if ((pc & 3) == 0 && (*x & 0x80) != 0)
+    return print_insn (cd, pc, info, buf, buflen);
+
+  /* Print the first insn.  */
+  if ((pc & 3) == 0)
+    {
+      buf += (big_p ? 0 : 2);
+      if (print_insn (cd, pc, info, buf, 2) == 0)
+       (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
+      buf += (big_p ? 2 : -2);
+    }
+
+  x = (big_p ? &buf[0] : &buf[1]);
+  if (*x & 0x80)
+    {
+      /* Parallel.  */
+      (*info->fprintf_func) (info->stream, " || ");
+      *x &= 0x7f;
+    }
+  else
+    (*info->fprintf_func) (info->stream, " -> ");
+
+  /* The "& 3" is to pass a consistent address.
+     Parallel insns arguably both begin on the word boundary.
+     Also, branch insns are calculated relative to the word boundary.  */
+  if (print_insn (cd, pc & ~ (bfd_vma) 3, info, buf, 2) == 0)
+    (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
+
+  return (pc & 3) ? 2 : 4;
+}
+
+/* -- */

diff --git a/cpu/mt.cpu b/cpu/mt.cpu
new file mode 100644 (file)
index 0000000..bb987f3
--- /dev/null
+++ b/cpu/mt.cpu
@@ -0,0 +1,1352 @@
+; Morpho Technologies MT Arch description.  -*- Scheme -*-
+; Copyright 2001, 2007, 2009 Free Software Foundation, Inc.
+;
+; Contributed by Red Hat Inc; developed under contract from
+; Morpho Technologies.
+;
+; This file is part of the GNU Binutils.
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 3 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, write to the Free Software
+; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+; MA 02110-1301, USA.
+
+(include "simplify.inc")
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Define The Architecture, Attributes, ISA, CPU, Machine, And Model. ;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; define-arch must appear first
+(define-arch
+  (name mt) ; name of cpu family
+  (comment "Morpho Technologies mRISC family")
+  (default-alignment aligned)
+  (insn-lsb0? #t)
+  (machs ms1 ms1-003 ms2)
+  (isas mt)
+)
+
+; Instruction set parameters.
+
+(define-isa
+  (name mt)
+  (comment "Morpho Technologies MT ISA")
+  (default-insn-word-bitsize 32)
+  (default-insn-bitsize 32)
+  (base-insn-bitsize 32)
+  (parallel-insns 2)
+)
+\f
+; Cpu family definitions.
+
+
+(define-cpu
+  ; cpu names must be distinct from the architecture name and machine names.
+  (name ms1bf)
+  (comment "Morpho Technologies mRISC family")
+  (endian big)
+  (word-bitsize 32)
+)
+
+(define-cpu
+  ; cpu names must be distinct from the architecture name and machine names.
+  (name ms1-003bf)
+  (comment "Morpho Technologies mRISC family")
+  (endian big)
+  (word-bitsize 32)
+)
+
+(define-cpu
+  ; cpu names must be distinct from the architecture name and machine names.
+  (name ms2bf)
+  (comment "Morpho Technologies mRISC family")
+  (endian big)
+  (word-bitsize 32)
+)
+
+(define-mach
+  (name ms1)
+  (comment "Morpho Technologies mrisc")
+  (cpu ms1bf)
+  (isas mt)
+)
+
+(define-mach
+  (name ms1-003)
+  (comment "Morpho Technologies mrisc")
+  (cpu ms1-003bf)
+  (isas mt)
+)
+
+(define-mach
+  (name ms2)
+  (comment "Morpho Technologies ms2")
+  (cpu ms2bf)
+  (isas mt)
+)
+
+\f
+; Model descriptions.
+; Can probably take the u-exec out.  We'll see.
+(define-model
+  (name ms1)
+  (comment "Morpho Technologies mrisc")
+  (mach ms1)
+  (unit u-exec "Execution Unit" ()
+       1 1 ; issue done
+       () ; state
+       () ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+)
+
+(define-model
+  (name ms1-003)
+  (comment "Morpho Technologies mrisc")
+  (mach ms1-003)
+  (unit u-exec "Execution Unit" ()
+       1 1 ; issue done
+       () ; state
+       () ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+)
+
+(define-model
+  (name ms2)
+  (comment "Morpho Technologies ms2")
+  (mach ms2)
+  (unit u-exec "Execution Unit" ()
+       1 1 ; issue done
+       () ; state
+       () ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+)
+
+; FIXME: It might simplify things to separate the execute process from the
+; one that updates the PC.
+\f
+
+;;;;;;;;;;;;;;;;;;;;;;;;
+;; Instruction Fields ;;
+;;;;;;;;;;;;;;;;;;;;;;;;
+
+; Attributes:
+; PCREL-ADDR: pc relative value (for reloc and disassembly purposes)
+; ABS-ADDR: absolute address (for reloc and disassembly purposes?)
+; RESERVED: bits are not used to decode insn, must be all 0
+; RELOC: there is a relocation associated with this field (experiment)
+;
+; f-msys: Identify a a morphosys insns.  1 if msys, 0 if not.
+; f-opc: 6 bit opcode for non-morphosys instructions.
+; f-msopc: 6 bit opcode for morphosys instructions.
+; f-imm: flag to indicate use of an immediate operand.  1 if yes, 0 if no.
+; f-sr1: source resgister 1. (also used for MSYS insns)
+; f-sr2: source register 2. (also used for MSYS insns)
+; f-dr: destination register when located in bits 19:16.
+; f-drrr: destination register when located in bits 15:12. (also for MSYS insns)
+; f-imm16: 16 bit immediate value when not an offset.
+; f-imm16a: 16 bit immediate value when it's a pc-rel offset.
+; f-uu4a: unused 4 bit field.
+; f-uu4b: second unsed 4 bit field.
+; f-uu1: unused 1 bit field
+; f-uu12: unused 12 bit field.
+; f-uu16: unused 16 bit field.
+; f-uu24: unused 24 bit field.
+
+(dnf f-msys      "morphosys insn flag"         () 31 1)
+(dnf f-opc       "opcode field"                        () 30 6)
+(dnf f-imm       "immedate flag"               () 24 1)
+(dnf f-uu24      "unused 24 bits"               () 23 24)
+(dnf f-sr1       "sr1 register field"  (ABS-ADDR) 23 4)
+(dnf f-sr2       "sr2 register field"  (ABS-ADDR) 19 4)
+(dnf f-dr        "dr register field"   (ABS-ADDR) 19 4)
+(dnf f-drrr      "drrr register field" (ABS-ADDR) 15 4)
+(dnf f-imm16u    "unsigned 16 bit immediate"    () 15 16)
+(df  f-imm16s    "signed 16 bit immediate"      () 15 16 INT ((value pc) (add HI value 0)) ((value pc) (add HI value 0)))
+(dnf f-imm16a   "pc-rel offset"      (PCREL-ADDR) 15 16)
+(dnf f-uu4a      "unused 4 bit field"          () 19 4)
+(dnf f-uu4b      "unused 4 bit field"          () 23 4)
+(dnf f-uu12      "unused 12 bit field"         () 11 12)
+(dnf f-uu8       "unused 8 bit field"           () 15 8)
+(dnf f-uu16      "unused 16 bit field"                 () 15 16)
+(dnf f-uu1       "unused 1 bit field"          ()  7 1)
+
+; The following ifields are used exclusively for the MorphoSys instructions.
+; In a few cases, a bit field is used for something in addition to what its
+; name suggests.  For the most part, the names are meaningful though.
+
+(dnf f-msopc     "opcode field"                        () 30 5)
+(dnf f-uu-26-25  "unused 26 bits"               () 25 26)
+(dnf f-mask      "mask"                                () 25 16)
+(dnf f-bankaddr  "bank address"                        () 25 13)
+(dnf f-rda       "rda"                         () 25 1)
+(dnf f-uu-2-25   "unused bits  25 & 24"                () 25 2)
+(dnf f-rbbc      "Omega network configuration" () 25 2)
+(dnf f-perm     "perm"                         () 25 2)
+(dnf f-mode      "mode"                         () 25 2)
+(dnf f-uu-1-24   "testing"                     () 24 1)
+(dnf f-wr        "wr"                          () 24 1)
+(dnf f-fbincr    "fb incr"                      () 23 4)
+(dnf f-uu-2-23   "unused bits 23 and 22"       () 23 2)
+(dnf f-xmode     "xmode"                       () 23 1)
+(dnf f-a23      "a23"                          () 23 1)
+(dnf f-mask1     "mask1"                       () 22 3)
+(dnf f-cr       "cr"                           () 22 3)
+(dnf f-type      "type"                                () 21 2)
+(dnf f-incamt    "increment amount"             () 19 8)
+(dnf f-cbs      "cbs"                          () 19 2)
+(dnf f-uu-1-19   "unused bit 19"               () 19 1)
+(dnf f-ball      "b_all"                       () 19 1)
+(dnf f-colnum    "column number"               () 18 3)
+(dnf f-brc       "b_r_c"                       () 18 3)
+(dnf f-incr     "incr"                         () 17 6)
+(dnf f-fbdisp    "frame buffer displacement"   () 15 6)
+(dnf f-uu-4-15   "unused bits 15,14,13,12"     () 15 4)
+(dnf f-length   "length"                       () 15 3)
+(dnf f-uu-1-15   "unused bit 15"               () 15 1)
+(dnf f-rc        "row/column context"          () 15 1)
+(dnf f-rcnum     "starting cell of cntxt mem." () 14 3)
+(dnf f-rownum    "row number"                  () 14 3)
+(dnf f-cbx      "cbx"                          () 14 3)
+(dnf f-id        "id"                           () 14 1)
+(dnf f-size      "size"                         () 13 14)
+(dnf f-rownum1   "row number"                  () 12 3)
+(dnf f-uu-3-11   "unused 3 bits (11-9)"         () 11 3)
+(dnf f-rc1       "row/column context"          () 11 1)
+(dnf f-ccb      "ccb"                          () 11 1)
+(dnf f-cbrb      "data-bus orientation"                () 10 1)
+(dnf f-cdb      "cdb"                          () 10 1)
+(dnf f-rownum2   "row number"                  ()  9 3)
+(dnf f-cell      "cell"                        ()  9 3)
+(dnf f-uu-3-9    "unused 3 bits (9-7)"          ()  9 3)
+(dnf f-contnum   "context number"              ()  8 9)
+(dnf f-uu-1-6    "unused bit 6"                 ()  6 1)
+(dnf f-dup       "dup"                         ()  6 1)
+(dnf f-rc2       "rc2"                         ()  6 1)
+(dnf f-ctxdisp   "context displacement"                ()  5 6)
+
+; additional fields in ms2
+(dnf f-imm16l    "loop count"                   () 23 16)
+(df  f-loopo    "loop offset"                  () 7 8 UINT
+    ((value pc) (srl SI value 2))
+    ((value pc) (add SI (sll value 2) 8))
+ )
+(dnf f-cb1sel    "cb1 select"                   () 25 3)
+(dnf f-cb2sel    "cb2 select"                   () 22 3)
+(dnf f-cb1incr   "cb1 increment"                (SIGNED) 19 6)
+(dnf f-cb2incr   "cb2 increment"                (SIGNED) 13 6)
+(dnf f-rc3       "row/colum context"            ()  7 1)
+
+; The following is just for a test
+(dnf f-msysfrsr2 "sr2 for msys"                        () 19 4)
+(dnf f-brc2      "b_r_c2"                       () 14 3)
+(dnf f-ball2     "b_all2"                       () 15 1)
+
+\f
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Enumerations Of Instruction Fields ;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; insn-msys: bit 31.  1 for Morphosys Insns, 0 if not.
+(define-normal-insn-enum insn-msys "msys enums" () MSYS_ f-msys
+  (NO YES)
+)
+
+; insn-opc: bits 30 through 25 .  Non-MorphoSys Instructions
+; Note - the documentation is wrong for the encoding of the DBNZ
+; instruction.  It is actually 011110.  See Issue 67699.
+(define-normal-insn-enum insn-opc "opc enums" () OPC_ f-opc
+  (ADD  ADDU SUB  SUBU MUL   -      -    -
+   AND  OR   XOR  NAND NOR   XNOR   LDUI -
+   LSL  LSR  ASR  -    -     -      -    -
+   BRLT BRLE BREQ JMP  JAL   BRNEQ  DBNZ LOOP
+   LDW  STW  -    -    -     -      -    -
+   -    -    -    -    -     -      -    -
+   EI   DI   SI   RETI BREAK IFLUSH -    -
+  )
+)
+
+; insn-msopc: bits 30 through 26 .  MorphoSys Instructions
+(define-normal-insn-enum insn-msopc "msopc enums" () MSOPC_ f-msopc
+  (LDCTXT LDFB      STFB    FBCB     MFBCB    FBCCI     FBRCI     FBCRI
+   FBRRI  MFBCCI    MFBRCI  MFBCRI   MFBRRI   FBCBDR    RCFBCB    MRCFBCB
+   CBCAST DUPCBCAST WFBI    WFB      RCRISC   FBCBINC   RCXMODE   INTLVR
+   WFBINC MWFBINC   WFBINCR MWFBINCR FBCBINCS MFBCBINCS FBCBINCRS MFBCBINCRS
+   -      -         -       -        -        -         -         -
+  )
+)
+
+; insn-imm: bit 24.  Immediate operand indicator.
+(define-normal-insn-enum insn-imm "imm enums" () IMM_ f-imm
+  ; This bit specifies whether and immediate operand will be present.
+  ; It's 1 if there is, 0 if there is not.
+  (NO YES)
+)
+;;;;;;;;;;;;;;;;
+;; Attributes ;;
+;;;;;;;;;;;;;;;;
+
+; Might not need this.  Keep if for the sim just in case.
+;(define-attr
+;  (for insn)
+;  (type boolean)
+;  (name EXT-SKIP-INSN)
+;  (comment "instruction is a PAGE, LOADL or LOADH instruction")
+;)
+  
+(define-attr
+  (for insn)
+  (type boolean)
+  (name LOAD-DELAY)
+  (comment "insn has a load delay")
+)
+  
+(define-attr
+  (for insn)
+  (type boolean)
+  (name MEMORY-ACCESS)
+  (comment "insn performs a memory access")
+)
+
+(define-attr
+  (for insn)
+  (type boolean)
+  (name AL-INSN)
+  (comment "insn is an arithmetic or logic insn.")
+)
+
+(define-attr
+  (for insn)
+  (type boolean)
+  (name IO-INSN)
+  (comment "insn performs an I/O operation")
+)
+
+(define-attr
+  (for insn)
+  (type boolean)
+  (name BR-INSN)
+  (comment "insn performs an I/O operation")
+)
+
+(define-attr
+  (for insn)
+  (type boolean)
+  (name JAL-HAZARD)
+  (comment "insn has jal-like hazard")
+)
+
+(define-pmacro (define-reg-use-attr regfield)
+  (define-attr
+    (for insn)
+    (type boolean)
+    (name (.sym "USES-" (.upcase regfield)))
+    (comment ("insn accesses register operand " regfield))))
+
+(define-reg-use-attr "frdr")
+(define-reg-use-attr "frdrrr")
+(define-reg-use-attr "frsr1")
+(define-reg-use-attr "frsr2")
+
+
+; Might not need this.  Keep it for the sim just in case.
+(define-attr
+  (for insn)
+  (type boolean)
+  (name SKIPA)
+  (comment "instruction is a SKIP instruction")
+)
+
+ 
+;;;;;;;;;;;;;;;;;;;;; 
+;; Hardware Pieces ;;
+;;;;;;;;;;;;;;;;;;;;;
+
+;(define-pmacro (build-reg-name n) (.splice (.str "$" n) n))
+
+; These are the 16 registers that the chip has.  In later versions
+; where there will be more registers, this will need to be expanded.
+; Note that there are two entries for the registers with two names.
+(define-hardware
+  (name h-spr)
+  (comment "special-purpose registers")
+  (type register SI (16))
+  (indices keyword "" (("R0" 0) ("R1" 1) ("R2" 2) ("R3" 3) ("R4" 4) ("R5" 5)
+  ("R6" 6) ("R7" 7) ("R8" 8) ("R9" 9) ("R10" 10) ("R11" 11) ("R12" 12) ("fp" 12)
+  ("R13" 13) ("sp" 13) ("R14" 14) ("ra" 14) ("R15" 15) ("ira" 15)))
+;  (get (index) (and (raw-reg h-spr) #xffffffff))
+;  (set (index value) (set (raw-reg h-spr) (and value #xffffffff)))
+)
+
+; This is the  program counter.
+(dnh h-pc "program counter" (PC PROFILE) (pc) () () ())
+
+(define-keyword
+   (name msys-syms)
+   (print-name h-nil)
+   (prefix "")
+   (values (DUP 1) (XX 0))
+)
+
+;;;;;;;;;;;;;;
+;; Operands ;;
+;;;;;;;;;;;;;;
+
+(define-operand (name frsr1) (comment "register") (attrs) 
+  (type h-spr) (index f-sr1) )
+(define-operand (name frsr2) (comment "register") (attrs) 
+  (type h-spr) (index f-sr2) )
+(define-operand (name frdr) (comment "register") (attrs) 
+  (type h-spr) (index f-dr) )
+(define-operand (name frdrrr) (comment "register") (attrs) 
+  (type h-spr) (index f-drrr) )
+(define-operand (name imm16) (comment "immediate value - sign extd") (attrs) 
+  (type h-sint) (index f-imm16s) (handlers (parse "imm16") (print "dollarhex")))
+(define-operand (name imm16z) (comment "immediate value - zero extd") (attrs) 
+  (type h-uint) (index f-imm16u) (handlers (parse "imm16") (print "dollarhex")))
+(define-operand (name imm16o) (comment "immediate value") (attrs PCREL-ADDR) 
+  (type h-uint) (index f-imm16s) (handlers (parse "imm16") (print "pcrel")))
+
+; Operands for MorphoSys Instructions
+
+(define-operand (name rc) (comment "rc") (attrs) 
+  (type h-uint) (index f-rc) (handlers (parse "rc") (print "dollarhex")))
+
+(define-operand (name rcnum) (comment "rcnum") (attrs) 
+  (type h-uint) (index f-rcnum) (handlers (print "dollarhex")))
+
+(define-operand (name contnum) (comment "context number") (attrs) 
+  (type h-uint) (index f-contnum) (handlers (print "dollarhex")))
+
+(define-operand (name rbbc) (comment "omega network configuration") (attrs) 
+  (type h-uint) (index f-rbbc) (handlers (parse "rbbc") (print "dollarhex")))
+
+(define-operand (name colnum) (comment "column number") (attrs) 
+  (type h-uint) (index f-colnum) (handlers (print "dollarhex")))
+
+(define-operand (name rownum) (comment "row number") (attrs) 
+  (type h-uint) (index f-rownum) (handlers (print "dollarhex")))
+
+(define-operand (name rownum1) (comment "row number") (attrs) 
+  (type h-uint) (index f-rownum1) (handlers (print "dollarhex")))
+
+(define-operand (name rownum2) (comment "row number") (attrs) 
+  (type h-uint) (index f-rownum2) (handlers (print "dollarhex")))
+
+(define-operand (name rc1) (comment "rc1") (attrs) 
+  (type h-uint) (index f-rc1) (handlers (parse "rc") (print "dollarhex")))
+
+(define-operand (name rc2) (comment "rc2") (attrs) 
+  (type h-uint) (index f-rc2) (handlers (parse "rc") (print "dollarhex")))
+
+(define-operand (name cbrb) (comment "data-bus orientation") (attrs) 
+  (type h-uint) (index f-cbrb) (handlers (parse "cbrb") (print "dollarhex")))
+
+(define-operand (name cell) (comment "cell") (attrs) 
+  (type h-uint) (index f-cell) (handlers (print "dollarhex")))
+
+(define-operand (name dup) (comment "dup") (attrs) 
+  (type h-uint) (index f-dup) (handlers (parse "dup") (print "dollarhex")))
+
+(define-operand (name ctxdisp) (comment "context displacement") (attrs) 
+  (type h-uint) (index f-ctxdisp) (handlers (print "dollarhex")))
+
+(define-operand (name fbdisp) (comment "frame buffer displacement") (attrs) 
+  (type h-uint) (index f-fbdisp) (handlers (print "dollarhex")))
+
+(define-operand (name type) (comment "type") (attrs) 
+  (type h-uint) (index f-type) (handlers (parse "type") (print "dollarhex")))
+
+(define-operand (name mask) (comment "mask") (attrs) 
+  (type h-uint) (index f-mask) (handlers (print "dollarhex")))
+
+(define-operand (name bankaddr) (comment "bank address") (attrs) 
+  (type h-uint) (index f-bankaddr) (handlers (print "dollarhex")))
+
+(define-operand (name incamt) (comment "increment amount") (attrs) 
+  (type h-uint) (index f-incamt) (handlers (print "dollarhex")))
+
+(define-operand (name xmode) (comment "xmode") (attrs) 
+  (type h-uint) (index f-xmode) (handlers (parse "xmode") (print "dollarhex")))
+
+(define-operand (name mask1) (comment "mask1") (attrs) 
+  (type h-uint) (index f-mask1) (handlers (print "dollarhex")))
+
+(define-operand (name ball) (comment "b_all") (attrs) 
+  (type h-uint) (index f-ball) (handlers (parse "ball") (print "dollarhex")))
+
+(define-operand (name brc) (comment "b_r_c") (attrs) 
+  (type h-uint) (index f-brc) (handlers (print "dollarhex")))
+
+(define-operand (name rda) (comment "rd") (attrs) 
+  (type h-uint) (index f-rda) (handlers (print "dollarhex")))
+
+(define-operand (name wr) (comment "wr") (attrs) 
+  (type h-uint) (index f-wr) (handlers (print "dollarhex")))
+
+(define-operand (name ball2) (comment "b_all2") (attrs)
+  (type h-uint) (index f-ball2) (handlers (parse "ball") (print "dollarhex")))
+
+(define-operand (name brc2) (comment "b_r_c2") (attrs)
+  (type h-uint) (index f-brc2) (handlers (print "dollarhex")))
+(define-operand (name perm) (comment "perm") (attrs)
+  (type h-uint) (index f-perm) (handlers (print "dollarhex")))
+(define-operand (name a23)   (comment "a23") (attrs)
+  (type h-uint) (index f-a23) (handlers (print "dollarhex")))
+(define-operand (name cr)   (comment "c-r") (attrs)
+  (type h-uint) (index f-cr) (handlers (print "dollarhex")))
+(define-operand (name cbs)     (comment "cbs") (attrs)
+  (type h-uint) (index f-cbs) (handlers (print "dollarhex")))
+(define-operand (name incr)    (comment "incr") (attrs)
+  (type h-uint) (index f-incr) (handlers (print "dollarhex")))
+(define-operand (name length)  (comment "length") (attrs)
+  (type h-uint) (index f-length) (handlers (print "dollarhex")))
+(define-operand (name cbx)     (comment "cbx") (attrs)
+  (type h-uint) (index f-cbx) (handlers (print "dollarhex")))
+(define-operand (name ccb)     (comment "ccb") (attrs)
+  (type h-uint) (index f-ccb) (handlers (print "dollarhex")))
+(define-operand (name cdb)     (comment "cdb") (attrs)
+  (type h-uint) (index f-cdb) (handlers (print "dollarhex")))
+
+; For the INTLVR insn
+(define-operand (name mode) (comment "mode") (attrs)
+  (type h-uint) (index f-mode) (handlers (print "dollarhex")))
+(define-operand (name id) (comment "i/d") (attrs)
+  (type h-uint) (index f-id) (handlers (print "dollarhex")))
+(define-operand (name size) (comment "size") (attrs)
+  (type h-uint) (index f-size) (handlers (print "dollarhex")))
+
+(define-operand (name fbincr)  (comment "fb incr") (attrs)
+  (type h-uint) (index f-fbincr) (handlers (print "dollarhex")))
+
+; For the ms2 insns
+(define-operand (name loopsize) (comment "immediate value")
+  (attrs (MACH ms2) PCREL-ADDR)
+  (type h-uint) (index f-loopo) (handlers (parse "loopsize") (print "pcrel")))
+(define-operand (name imm16l) (comment "immediate value")
+  (attrs (MACH ms2))
+  (type h-uint) (index f-imm16l) (handlers (print "dollarhex")))
+(define-operand (name rc3) (comment "rc3") (attrs (MACH ms2))
+  (type h-uint) (index f-rc3) (handlers (parse "rc") (print "dollarhex")))
+(define-operand (name cb1sel) (comment "cb1sel") (attrs (MACH ms2))
+  (type h-uint) (index f-cb1sel) (handlers (print "dollarhex")))
+(define-operand (name cb2sel) (comment "cb2sel") (attrs (MACH ms2))
+  (type h-uint) (index f-cb2sel) (handlers (print "dollarhex")))
+(define-operand (name cb1incr) (comment "cb1incr") (attrs (MACH ms2))
+  (type h-sint) (index f-cb1incr) (handlers (print "dollarhex")))
+(define-operand (name cb2incr) (comment "cb2incr") (attrs (MACH ms2))
+  (type h-sint) (index f-cb2incr) (handlers (print "dollarhex")))
+
+; Probaby won't need most of these.
+(define-pmacro r0    (reg h-spr #x0))
+(define-pmacro r1    (reg h-spr #x01))
+(define-pmacro r2    (reg h-spr #x02))
+(define-pmacro r3    (reg h-spr #x03))
+(define-pmacro r4    (reg h-spr #x04))
+(define-pmacro r5    (reg h-spr #x05))
+(define-pmacro r6    (reg h-spr #x06))
+(define-pmacro r7    (reg h-spr #x07))
+(define-pmacro r8    (reg h-spr #x08))
+(define-pmacro r9    (reg h-spr #x09))
+(define-pmacro r10   (reg h-spr #xA))
+(define-pmacro r11   (reg h-spr #xB))
+(define-pmacro r12   (reg h-spr #xC))
+(define-pmacro fp    (reg h-spr #xC))
+(define-pmacro r13   (reg h-spr #xD))
+(define-pmacro sp    (reg h-spr #xD))
+(define-pmacro r14   (reg h-spr #xE))
+(define-pmacro ra    (reg h-spr #xE))
+(define-pmacro r15   (reg h-spr #xF))
+(define-pmacro ira   (reg h-spr #xF))
+
+; delayed set
+(define-pmacro (dset dest src) (set (delay 1 dest) src))
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Instructions As Defined In the MorphoRisc ISA Document ;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; Arithmetic Instructions
+
+(dni add "ADD DstReg, SrcReg1, SrcReg2"
+     (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
+     "add $frdrrr,$frsr1,$frsr2"
+     (+ MSYS_NO OPC_ADD IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
+     (set frdrrr (add SI frsr1 frsr2))
+     ()
+)
+
+(dni addu "ADDU DstReg, SrcReg1, SrcReg2"
+     (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
+     "addu $frdrrr,$frsr1,$frsr2"
+     (+ MSYS_NO OPC_ADDU IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
+     (set frdrrr (add USI frsr1 frsr2))
+     ()
+)
+
+(dni addi "ADDI DstReg, SrcReg1 UnsImm"
+     (AL-INSN USES-FRDR USES-FRSR1)
+     "addi $frdr,$frsr1,#$imm16"
+     (+ MSYS_NO OPC_ADD IMM_YES frsr1 frdr imm16)
+     (sequence((HI tmp))
+        (set HI tmp (and imm16 #xffff))
+       (set frdr (add SI frsr1 (ext SI tmp)))
+     )
+     ()
+)
+
+(dni addui "ADDUI DstReg, SrcReg1, UnsImm"
+     (AL-INSN USES-FRDR USES-FRSR1)
+     "addui $frdr,$frsr1,#$imm16z"
+     (+ MSYS_NO OPC_ADDU IMM_YES frsr1 frdr imm16z)
+     (set frdr (add USI frsr1 (ext USI imm16z)))
+     ()
+)
+
+(dni sub "SUB DstReg, SrcReg1, SrcReg2"
+     (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
+     "sub $frdrrr,$frsr1,$frsr2"
+     (+ MSYS_NO OPC_SUB IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
+     (set frdrrr (sub SI frsr1 frsr2))
+     ()
+)
+
+(dni subu "SUBU DstReg, SrcReg1, SrcReg2"
+     (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
+     "subu $frdrrr,$frsr1,$frsr2"
+     (+ MSYS_NO OPC_SUBU IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
+     (set frdrrr (sub USI frsr1 frsr2))
+     ()
+)
+
+(dni subi "SUBI DstReg, SrcReg1, UnsImm"
+     (AL-INSN USES-FRDR USES-FRSR1)
+     "subi $frdr,$frsr1,#$imm16"
+     (+ MSYS_NO OPC_SUB IMM_YES frsr1 frdr imm16)
+     (sequence((HI tmp))
+        (set HI tmp (and imm16 #xffff))
+       (set frdr (sub SI frsr1 (ext SI tmp)))
+     )
+     ;(set frdr (sub SI frsr1 (ext SI imm16)))
+     ()
+)
+
+(dni subui "SUBUI DstReg, SrcReg1, UnsImm"
+     (AL-INSN USES-FRDR USES-FRSR1)
+     "subui $frdr,$frsr1,#$imm16z"
+     (+ MSYS_NO OPC_SUBU IMM_YES frsr1 frdr imm16z)
+     (set frdr (sub USI frsr1 (ext USI imm16z)))
+     ()
+)
+
+(dni mul "MUL DstReg, SrcReg1, SrcReg2"
+     ((MACH ms1-003,ms2) AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
+     "mul $frdrrr,$frsr1,$frsr2"
+     (+ MSYS_NO OPC_MUL IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
+     (sequence((HI op1) (HI op2))
+        (set op1 (and frsr1 #xffff))
+         (if (or (lt op1 (const -32768)) (gt op1 (const 32767)))
+            (error "operand out of range")
+         )
+        (set op2 (and frsr2 #xffff))
+         (if (or (lt op2 (const -32768)) (gt op2 (const 32767)))
+            (error "operand out of range")
+         )
+        (set frdrrr (mul SI (ext SI op1) (ext SI op2)))
+     )
+     ()
+)
+
+(dni muli "MULI DstReg, SrcReg1, UnsImm"
+     ((MACH ms1-003,ms2) AL-INSN USES-FRDR USES-FRSR1)
+     "muli $frdr,$frsr1,#$imm16"
+     (+ MSYS_NO OPC_MUL IMM_YES frsr1 frdr imm16)
+     (sequence((HI op1) (HI op2))
+        (set op1 (and frsr1 #xffff))
+         (if (or (lt op1 (const -32768)) (gt op1 (const 32767)))
+            (error "operand out of range")
+         )
+         (set op2 (and imm16 #xffff))
+         (if (eq op1 (const 0))
+          (error "op1 is 0")
+         )
+         (if (eq op2 (const 0))
+          (error "op2 is 0")
+         )
+        (set frdr (mul SI (ext SI op1) (ext SI op2)))
+     )
+     ()
+)
+
+; Logical Instructions
+
+(dni and "AND DstReg, SrcReg1, SrcReg2"
+     (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
+     "and $frdrrr,$frsr1,$frsr2"
+     (+ MSYS_NO OPC_AND IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
+     (set frdrrr (and frsr1 frsr2))
+     ()
+)
+
+(dni andi "ANDI DstReg, SrcReg1, UnsImm"
+     (AL-INSN USES-FRDR USES-FRSR1)
+     "andi $frdr,$frsr1,#$imm16z"
+     (+ MSYS_NO OPC_AND IMM_YES frsr1 frdr imm16z)
+     (set frdr (and frsr1 (ext USI imm16z)))
+     ()
+)
+
+(dni or "OR DstReg, SrcReg1, SrcReg2"
+     (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
+     "or $frdrrr,$frsr1,$frsr2"
+     (+ MSYS_NO OPC_OR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
+     (set frdrrr (or frsr1 frsr2))
+     ()
+)
+
+(dni nop "nop"
+     ()
+     "nop"
+     (+ MSYS_NO OPC_OR IMM_NO (f-uu24 0))
+     (nop)
+     ()
+)
+
+(dni ori "ORI DstReg, SrcReg1, UnsImm"
+     (AL-INSN USES-FRDR USES-FRSR1)
+     "ori $frdr,$frsr1,#$imm16z"
+     (+ MSYS_NO OPC_OR IMM_YES frsr1 frdr imm16z)
+     (set frdr (or frsr1 (ext USI imm16z)))
+     ()
+)
+
+(dni xor "XOR DstReg, SrcReg1, SrcReg2"
+     (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
+     "xor $frdrrr,$frsr1,$frsr2"
+     (+ MSYS_NO OPC_XOR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
+     (set frdrrr (xor frsr1 frsr2))
+     ()
+)
+
+(dni xori "XORI DstReg, SrcReg1, UnsImm"
+     (AL-INSN USES-FRDR USES-FRSR1)
+     "xori $frdr,$frsr1,#$imm16z"
+     (+ MSYS_NO OPC_XOR IMM_YES frsr1 frdr imm16z)
+     (set frdr (xor frsr1 (ext USI imm16z)))
+     ()
+)
+
+(dni nand "NAND DstReg, SrcReg1, SrcReg2"
+     (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
+     "nand $frdrrr,$frsr1,$frsr2"
+     (+ MSYS_NO OPC_NAND IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
+     (set frdrrr (inv (and frsr1 frsr2)))
+     ()
+)
+
+(dni nandi "NANDI DstReg, SrcReg1, UnsImm"
+     (AL-INSN USES-FRDR USES-FRSR1)
+     "nandi $frdr,$frsr1,#$imm16z"
+     (+ MSYS_NO OPC_NAND IMM_YES frsr1 frdr imm16z)
+     (set frdr (inv (and frsr1 (ext USI imm16z))))
+     ()
+)
+
+(dni nor "NOR DstReg, SrcReg1, SrcReg2"
+     (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
+     "nor $frdrrr,$frsr1,$frsr2"
+     (+ MSYS_NO OPC_NOR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
+     (set frdrrr (inv (or frsr1 frsr2)))
+     ()
+)
+
+(dni nori "NORI DstReg, SrcReg1, UnsImm"
+     (AL-INSN USES-FRDR USES-FRSR1)
+     "nori $frdr,$frsr1,#$imm16z"
+     (+ MSYS_NO OPC_NOR IMM_YES frsr1 frdr imm16z)
+     (set frdr (inv (or frsr1 (ext USI imm16z))))
+     ()
+)
+
+(dni xnor "XNOR DstReg, SrcReg1, SrcReg2"
+     (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
+     "xnor $frdrrr,$frsr1,$frsr2"
+     (+ MSYS_NO OPC_XNOR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
+     (set frdrrr (inv (xor frsr1 frsr2)))
+     ()
+)
+
+(dni xnori "XNORI DstReg, SrcReg1, UnsImm"
+     (AL-INSN USES-FRDR USES-FRSR1)
+     "xnori $frdr,$frsr1,#$imm16z"
+     (+ MSYS_NO OPC_XNOR IMM_YES frsr1 frdr imm16z)
+     (set frdr (inv (xor frsr1 (ext USI imm16z))))
+     ()
+)
+
+(dni ldui "LDUI DstReg, UnsImm"
+     (AL-INSN USES-FRDR)
+     "ldui $frdr,#$imm16z"
+     (+ MSYS_NO OPC_LDUI IMM_YES (f-uu4b 0) frdr imm16z)
+     (set frdr (and (sll imm16z 16) #xffff0000))
+     ()
+)
+
+; Shift Instructions
+
+(dni lsl "LSL DstReg, SrcReg1, SrcReg2"
+     (USES-FRDRRR USES-FRSR1 USES-FRSR2)
+     "lsl $frdrrr,$frsr1,$frsr2"
+     (+ MSYS_NO OPC_LSL IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
+     (set frdrrr (sll frsr1 frsr2))
+     ()
+)
+
+(dni lsli "LSLI DstReg, SrcReg1, UnsImm"
+     (USES-FRDR USES-FRSR1)
+     "lsli $frdr,$frsr1,#$imm16"
+     (+ MSYS_NO OPC_LSL IMM_YES frsr1 frdr imm16)
+     (set frdr (sll frsr1 imm16))
+     ()
+)
+
+(dni lsr "LSR DstReg, SrcReg1, SrcReg2"
+     (USES-FRDRRR USES-FRSR1 USES-FRSR2)
+     "lsr $frdrrr,$frsr1,$frsr2"
+     (+ MSYS_NO OPC_LSR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
+     (set frdrrr (srl frsr1 frsr2))
+     ()
+)
+
+(dni lsri "LSRI DstReg, SrcReg1, UnsImm"
+     (USES-FRDR USES-FRSR1)
+     "lsri $frdr,$frsr1,#$imm16"
+     (+ MSYS_NO OPC_LSR IMM_YES frsr1 frdr imm16)
+     (set frdr (srl frsr1 imm16))
+     ()
+)
+
+(dni asr "ASR DstReg, SrcReg1, SrcReg2"
+     (USES-FRDRRR USES-FRSR1 USES-FRSR2)
+     "asr $frdrrr,$frsr1,$frsr2"
+     (+ MSYS_NO OPC_ASR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
+     (set frdrrr (sra frsr1 frsr2))
+     ()
+)
+
+(dni asri "ASRI DstReg, SrcReg1, UnsImm"
+     (USES-FRDR USES-FRSR1)
+     "asri $frdr,$frsr1,#$imm16"
+     (+ MSYS_NO OPC_ASR IMM_YES frsr1 frdr imm16)
+     (set frdr (sra frsr1 imm16))
+     ()
+)
+
+; Control Transfer Instructions
+
+(dni brlt "BRLT SrcReg1, SrcReg2, label"
+     (BR-INSN DELAY-SLOT USES-FRDRRR USES-FRSR1 USES-FRSR2)
+     "brlt $frsr1,$frsr2,$imm16o"
+     (+ MSYS_NO OPC_BRLT IMM_YES frsr1 frsr2 imm16o)
+     (sequence()
+        (if (lt USI frsr1 frsr2)
+            (dset pc (add pc (ext SI imm16o))))
+     )
+     ()
+)
+
+(dni brle "BRLE SrcReg1, SrcReg2, label"
+     (BR-INSN DELAY-SLOT USES-FRSR1 USES-FRSR2)
+     "brle $frsr1,$frsr2,$imm16o"
+     (+ MSYS_NO OPC_BRLE IMM_YES frsr1 frsr2 imm16o)
+     (sequence()
+        (if (le USI frsr1 frsr2)
+            (dset pc (add pc (ext SI imm16o))))
+     )
+     ()
+)
+
+(dni breq "BREQ SrcReg1, SrcReg2, label"
+     (BR-INSN DELAY-SLOT USES-FRSR1 USES-FRSR2)
+     "breq $frsr1,$frsr2,$imm16o"
+     (+ MSYS_NO OPC_BREQ IMM_YES frsr1 frsr2 imm16o)
+     (sequence()
+        (if (eq USI frsr1 frsr2)
+            (dset pc (add pc (ext SI imm16o))))
+     )
+     ()
+)
+
+(dni brne "BRNE SrcReg1, SrcReg2, label"
+     (BR-INSN DELAY-SLOT USES-FRSR1 USES-FRSR2)
+     "brne $frsr1,$frsr2,$imm16o"
+     (+ MSYS_NO OPC_BRNEQ IMM_YES frsr1 frsr2 imm16o)
+     (sequence()
+        (if (not (eq USI frsr1 frsr2))
+            (dset pc (add pc (ext SI imm16o))))
+     )
+     ()
+)
+
+(dni jmp "JMP, label"
+     (DELAY-SLOT BR-INSN)
+     "jmp $imm16o"
+     (+ MSYS_NO OPC_JMP IMM_YES (f-uu4b 0) (f-uu4a 0) imm16o)
+     (dset pc (add pc (ext SI imm16o)))
+     ()
+)
+
+(dni jal "JAL DstReg, SrcReg1"
+     (BR-INSN DELAY-SLOT BR-INSN USES-FRDR USES-FRSR1 JAL-HAZARD)
+     "jal $frdrrr,$frsr1"
+     (+ MSYS_NO OPC_JAL IMM_NO frsr1 (f-uu4a 0) frdrrr (f-uu12 0))
+     (sequence()
+         (if (eq frsr1 #x0)
+           (c-call VOID "do_syscall" pc)
+           (sequence()   ; else part.  Do non-syscall stuff here.
+               (dset frdrrr (add pc #x8))
+               (dset pc frsr1)
+            ) 
+         )
+     )
+     ()
+)
+
+(dni dbnz "DBNZ SrcReg1, label"
+     ((MACH ms1-003,ms2) BR-INSN DELAY-SLOT USES-FRSR1)
+     "dbnz $frsr1,$imm16o"
+     (+ MSYS_NO OPC_DBNZ IMM_YES frsr1 (f-uu4a 0) imm16o)
+     (sequence()
+        (if (not (eq USI frsr1 0))
+            (dset pc (add pc (ext SI imm16o))))
+     )
+     ()
+)
+
+; Interrupt Control Instructions
+
+(dni ei "EI - Enable Interrupt Processing"
+     ()
+     "ei"
+     (+ MSYS_NO OPC_EI IMM_NO (f-uu4b 0) (f-uu4a 0) (f-uu16 0))
+     (c-call VOID "enable_interrupts")
+     ()
+)
+
+(dni di "DI - Disable Interrupt Processing"
+     ()
+     "di"
+     (+ MSYS_NO OPC_DI IMM_NO (f-uu4b 0) (f-uu4a 0) (f-uu16 0))
+     (c-call VOID "disable_interrupts")
+     ()
+)
+
+(dni si "SI - Send software Interrupt"
+     (DELAY-SLOT BR-INSN USES-FRDR)
+     "si $frdrrr"
+     (+ MSYS_NO OPC_SI IMM_NO (f-uu4b 0) (f-uu4a 0) frdrrr (f-uu12 0))
+     ;(sequence() 
+     ;   (dset frdr (add pc #x4))
+     ;   (c-call VOID "do_syscall1" pc)
+     ;   ; (dset pc frsr1) Do this later when we have the address.
+     ;)
+     (sequence() 
+        (set frdrrr (add pc #x4))
+        (c-call VOID "do_syscall" pc)
+        ; (set pc frsr1) Do this later when we have the address.
+     )
+     ()
+)
+
+(dni reti "RETI SrcReg1"
+     (DELAY-SLOT BR-INSN USES-FRSR1 JAL-HAZARD)
+     "reti $frsr1"
+     (+ MSYS_NO OPC_RETI IMM_NO frsr1 (f-uu4a 0) (f-uu16 0))
+     (sequence()
+       (c-call VOID "enable_interrupts")
+       (dset pc frsr1)
+     )
+     ()
+)
+
+; Memory Access Instructions
+
+(dni ldw "LDW DstReg, SrcReg1, Imm"
+     (LOAD-DELAY MEMORY-ACCESS USES-FRDR USES-FRSR1)
+     "ldw $frdr,$frsr1,#$imm16"
+     (+ MSYS_NO OPC_LDW IMM_YES frsr1 frdr imm16)
+     (sequence((USI ea) (HI tmp))
+      (set HI tmp (and imm16 #xffff))
+      (set ea (and (add SI frsr1 (ext SI tmp)) #xfffffffc))
+      (set frdr (mem SI ea))
+     )
+     ()
+)
+
+(dni stw "STW SrcReg2, SrcReg1, Imm"
+     (MEMORY-ACCESS USES-FRSR1 USES-FRSR2)
+     "stw $frsr2,$frsr1,#$imm16"
+     (+ MSYS_NO OPC_STW IMM_YES frsr1 frsr2 imm16)
+     (sequence((USI ea) (HI tmp))
+      (set HI tmp (and imm16 #xffff))
+      (set ea (and (add SI frsr1 (ext SI tmp)) #xfffffffc))
+      (set (mem SI ea) frsr2)
+     )
+     ()
+)
+
+; Break Instruction
+
+(dni break "BREAK"
+     ()
+     "break"
+     (+ MSYS_NO OPC_BREAK (f-imm 0) (f-uu24 0))
+     (c-call VOID "do_break" pc)
+     ()
+)
+
+; Cache Flush Instruction
+
+(dni iflush "IFLUSH"
+     ((MACH ms1-003,ms2))
+     "iflush"
+     (+ MSYS_NO OPC_IFLUSH (f-imm 0) (f-uu24 0))
+     (nop)
+     ()
+)
+
+; MorphoSys Instructions
+
+(dni ldctxt "LDCTXT SRC1, SRC2, r/c, r/c#, context#"
+     ((MACH ms1))
+     "ldctxt $frsr1,$frsr2,#$rc,#$rcnum,#$contnum"
+     (+ MSYS_YES MSOPC_LDCTXT (f-uu-2-25 0) frsr1 frsr2 rc rcnum (f-uu-3-11 0)
+       contnum )
+     (nop)
+     ()
+)
+
+(dni ldfb "LDFB SRC1, byte#"
+     ((MACH ms1))
+     "ldfb $frsr1,$frsr2,#$imm16z"
+     (+ MSYS_YES MSOPC_LDFB (f-uu-2-25 0) frsr1 frsr2 imm16z)
+     (nop)
+     ()
+)
+
+(dni stfb "STFB SRC1, SRC2, byte "
+     ((MACH ms1))
+     "stfb $frsr1,$frsr2,#$imm16z"
+     (+ MSYS_YES MSOPC_STFB (f-uu-2-25 0) frsr1 frsr2 imm16z)
+     (nop)
+     ()
+)
+
+(dni fbcb "FBCB SRC1, RT/BR1/BR2/CS, B_all, B_r_c, r/c, CB/RB, cell, dup, ctx_disp"
+     ((MACH ms1,ms1-003))
+     "fbcb $frsr1,#$rbbc,#$ball,#$brc,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp"
+     (+ MSYS_YES MSOPC_FBCB rbbc frsr1 ball brc (f-uu-4-15 0) rc cbrb cell dup ctxdisp)
+     (nop)
+     ()
+)
+
+(dni mfbcb "MFBCB SRC1, RT/BR1/BR2/CS, SRC2, r/c, CB/RB, cell, dup, ctx_disp"
+     ()
+     "mfbcb $frsr1,#$rbbc,$frsr2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp"
+     (+ MSYS_YES MSOPC_MFBCB rbbc frsr1 frsr2 (f-uu-4-15 0) rc1 cbrb cell dup ctxdisp)
+     (nop)
+     ()
+)
+
+(dni fbcci "FBCCI SRC1, RT/BR1/BR2/CS, B_all, B_r_c, FB_disp, cell, dup, ctx_disp"
+     ()
+     "fbcci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp"
+     (+ MSYS_YES MSOPC_FBCCI rbbc frsr1 ball brc fbdisp cell dup ctxdisp)
+     (nop)
+     ()
+)
+
+(dni fbrci "FBRCI SRC1, RT/BR1/BR2/CS, B_all, B_r_c, FB_disp, cell, dup, ctx_disp"
+     ()
+     "fbrci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp"
+     (+ MSYS_YES MSOPC_FBRCI rbbc frsr1 ball brc fbdisp cell dup ctxdisp)
+     (nop)
+     ()
+)
+
+(dni fbcri "FBCRI SRC1, RT/BR1/BR2/CS, B_all, B_r_c, FB_disp, cell, dup, ctx_disp"
+     ()
+     "fbcri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp"
+     (+ MSYS_YES MSOPC_FBCRI rbbc frsr1 ball brc fbdisp cell dup ctxdisp)
+     (nop)
+     ()
+)
+
+(dni fbrri "FBRRI SRC1, RT/BR1/BR2/CS, B_all, B_r_c, FB_disp, cell, dup, ctx_disp"
+     ()
+     "fbrri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp"
+     (+ MSYS_YES MSOPC_FBRRI rbbc frsr1 ball brc fbdisp cell dup ctxdisp)
+     (nop)
+     ()
+)
+
+(dni mfbcci "MFBCCI SRC1, RT/BR1/BR2/CS, SRC2, FB_disp, cell, dup, ctx_disp"
+     ()
+     "mfbcci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp"
+     (+ MSYS_YES MSOPC_MFBCCI rbbc frsr1 frsr2 fbdisp cell dup ctxdisp)
+     (nop)
+     ()
+)
+
+(dni mfbrci "MFBRCI SRC1, RT/BR1/BR2/CS, SRC2, FB_disp, cell, dup, ctx_disp"
+     ()
+     "mfbrci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp"
+     (+ MSYS_YES MSOPC_MFBRCI rbbc frsr1 frsr2 fbdisp cell dup ctxdisp)
+     (nop)
+     ()
+)
+
+(dni mfbcri "MFBCRI SRC1, RT/BR1/BR2/CS, SRC2, FB_disp, cell, dup, ctx_disp"
+     ()
+     "mfbcri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp"
+     (+ MSYS_YES MSOPC_MFBCRI rbbc frsr1 frsr2 fbdisp cell dup ctxdisp)
+     (nop)
+     ()
+)
+
+(dni mfbrri "MFBRRI SRC1, RT/BR1/BR2/CS, SRC2, FB_disp, cell, dup, ctx_disp"
+     ()
+     "mfbrri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp"
+     (+ MSYS_YES MSOPC_MFBRRI rbbc frsr1 frsr2 fbdisp cell dup ctxdisp)
+     (nop)
+     ()
+)
+
+(dni fbcbdr "FBCBDR SRC1, RT/BR1/BR2/CS, SRC2, B_all, B_r_c, r/c, CB/RB, cell, dup, ctx_disp"
+     ()
+     "fbcbdr $frsr1,#$rbbc,$frsr2,#$ball2,#$brc2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp"
+     (+ MSYS_YES MSOPC_FBCBDR rbbc frsr1 frsr2 ball2 brc2 rc1 cbrb cell dup ctxdisp)
+     (nop)
+     ()
+)
+
+(dni rcfbcb "RCFBCB RT/BR1/BR2/CS, type, B_all, B_r_c, row#, r/c, CB/RB, cell, dup, ctx_disp"
+     ()
+     "rcfbcb #$rbbc,#$type,#$ball,#$brc,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp"
+     (+ MSYS_YES MSOPC_RCFBCB rbbc (f-uu-2-23 0) type ball brc (f-uu-1-15 0) rownum rc1 cbrb cell dup ctxdisp)
+     (nop)
+     ()
+)
+
+(dni mrcfbcb "MRCFBCB SRC2, RT/BR1/BR2/CS, type, row#, r/c, CB/RB, cell, dup, ctx_disp"
+     ()
+     "mrcfbcb $frsr2,#$rbbc,#$type,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp"
+     (+ MSYS_YES MSOPC_MRCFBCB rbbc (f-uu-2-23 0) type frsr2 (f-uu-1-15 0) rownum rc1 cbrb cell dup ctxdisp)
+     (nop)
+     ()
+)
+
+(dni cbcast "CBCAST mask, r/c, ctx_disp "
+     ()
+     "cbcast #$mask,#$rc2,#$ctxdisp"
+     (+ MSYS_YES MSOPC_CBCAST mask (f-uu-3-9 0) rc2 ctxdisp)
+     (nop)
+     ()
+)
+
+(dni dupcbcast "DUPCBCAST mask, cell, r/c, ctx_disp "
+     ()
+     "dupcbcast #$mask,#$cell,#$rc2,#$ctxdisp"
+     (+ MSYS_YES MSOPC_DUPCBCAST mask cell rc2 ctxdisp)
+     (nop)
+     ()
+)
+
+(dni wfbi "WFBI Bank_address, row#, cell, dup, ctx_disp "
+     ()
+    "wfbi #$bankaddr,#$rownum1,#$cell,#$dup,#$ctxdisp"
+     (+ MSYS_YES MSOPC_WFBI bankaddr rownum1 cell dup ctxdisp)
+     (nop)
+     ()
+)
+
+;(dni wfb "WFB SRC1, SRC2, FB_disp, row#, ctx_disp"
+;     ()
+;     "wfb $frsr1,$frsr2,#$fbdisp,#$rownum,#$ctxdisp"
+;     (+ MSYS_YES MSOPC_WFB (f-uu-2-25 0) frsr1 frsr2 fbdisp rownum (f-uu-1-6 0) ctxdisp)
+;     (nop)
+;     ()
+;)
+
+(dni wfb "WFB, DRC1,SRC2,FB_disp,row#,ctx_disp"
+      ()
+      "wfb $frsr1,$frsr2,#$fbdisp,#$rownum2,#$ctxdisp"
+      (+ MSYS_YES MSOPC_WFB (f-uu-2-25 0) frsr1 frsr2 fbdisp rownum2 (f-uu-1-6 0) ctxdisp)
+      (nop)
+      ()
+)
+
+
+(dni rcrisc "RCRISC DEST, RT/BR1/BR2/CS, SRC1, column#, r/c, CB/RB, cell, dup, ctx_disp"
+     ()
+     "rcrisc $frdrrr,#$rbbc,$frsr1,#$colnum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp"
+     (+ MSYS_YES MSOPC_RCRISC rbbc frsr1 (f-uu-1-19 0) colnum frdrrr rc1 cbrb cell dup ctxdisp)
+     (nop)
+     ()
+)
+
+(dni fbcbinc "FBCBINC SRC1, RT/BR1/BR2/CS, Incr_amount, r/c, CB/RB, cell, dup, ctx_disp "
+     ()
+     "fbcbinc $frsr1,#$rbbc,#$incamt,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp"
+     (+ MSYS_YES MSOPC_FBCBINC rbbc frsr1 incamt rc1 cbrb cell dup ctxdisp)
+     (nop)
+     ()
+)
+
+(dni rcxmode "RCXMODE SRC2, rd, wr, xmode, mask, FB_disp, row#, r/c, ctx_disp"
+     ()
+     "rcxmode $frsr2,#$rda,#$wr,#$xmode,#$mask1,#$fbdisp,#$rownum2,#$rc2,#$ctxdisp"
+     (+ MSYS_YES MSOPC_RCXMODE rda wr xmode mask1 frsr2 fbdisp rownum2 rc2 ctxdisp)
+     (nop)
+     ()
+)
+
+(dni interleaver "INTLVR ireg, mode, ireg, i/d, size"
+     ()
+     "intlvr $frsr1,#$mode,$frsr2,#$id,#$size"
+     (+ MSYS_YES MSOPC_INTLVR mode frsr1 frsr2 (f-uu-1-15 0) id size)
+     (nop)
+     ()
+)
+
+;; Issue 66262: The documenatation gives the wrong order for 
+;;               the arguments to the WFBINC instruction.
+(dni wfbinc "WFBINC type, ccb/rcb, incr, all, c/r, length, rca_row, word, dup, ctxt_disp"
+     ((MACH ms1-003,ms2))
+     "wfbinc #$rda,#$wr,#$fbincr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp"
+     (+ MSYS_YES MSOPC_WFBINC rda wr fbincr ball colnum length rownum1 rownum2 dup ctxdisp)
+     (nop)
+     ()
+)
+
+(dni mwfbinc "MWFBINC mreg, type, ccb/rcb, incr, length, rca_row, word, dup, ctxt_disp"
+     ((MACH ms1-003,ms2))
+     "mwfbinc $frsr2,#$rda,#$wr,#$fbincr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp"
+     (+ MSYS_YES MSOPC_MWFBINC rda wr fbincr frsr2 length rownum1 rownum2 dup ctxdisp)
+     (nop)
+     ()
+)
+
+(dni wfbincr "WFBINCR ireg, type, ccb/rcb, all, c/r, length, rca_row, word, dup, ctxt_disp"
+     ((MACH ms1-003,ms2))
+     "wfbincr $frsr1,#$rda,#$wr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp"
+     (+ MSYS_YES MSOPC_WFBINCR rda wr frsr1 ball colnum length rownum1 rownum2 dup ctxdisp)
+     (nop)
+     ()
+)
+
+(dni mwfbincr "MWFBINCR ireg, mreg, type, ccb/rcb, length, rca_row, word, dup, ctxt_disp"
+     ((MACH ms1-003,ms2))
+     "mwfbincr $frsr1,$frsr2,#$rda,#$wr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp"
+     (+ MSYS_YES MSOPC_MWFBINCR rda wr frsr1 frsr2 length rownum1 rownum2 dup ctxdisp)
+     (nop)
+     ()
+)
+
+(dni fbcbincs "FBCBINCS             perm, all, c/r, cbs, incr, ccb/rcb, cdb/rdb, word, dup, ctxt_disp"
+     ((MACH ms1-003,ms2))
+     "fbcbincs #$perm,#$a23,#$cr,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp"
+     (+ MSYS_YES MSOPC_FBCBINCS perm a23 cr cbs incr ccb cdb rownum2 dup ctxdisp)
+     (nop)
+     ()
+)
+
+(dni mfbcbincs "MFBCBINCS              ireg, perm, cbs, incr, ccb/rcb, cdb/rdb, word, dup, ctxt_disp"
+     ((MACH ms1-003,ms2))
+     "mfbcbincs $frsr1,#$perm,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp"
+     (+ MSYS_YES MSOPC_MFBCBINCS perm frsr1 cbs incr ccb cdb rownum2 dup ctxdisp)
+     (nop)
+     ()
+)
+
+(dni fbcbincrs "FBCBINCRS           ireg, perm, all, c/r, cbs, ccb/rcb, cdb/rdb, word, dup, ctxt_disp"
+     ((MACH ms1-003,ms2))
+     "fbcbincrs $frsr1,#$perm,#$ball,#$colnum,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp"
+     (+ MSYS_YES MSOPC_FBCBINCRS perm frsr1 ball colnum (f-uu-1-15 0) cbx ccb cdb rownum2 dup ctxdisp)
+     (nop)
+     ()
+)
+
+(dni mfbcbincrs "MFBCBINCRS ireg, mreg, perm, cbs, ccb/rcb, cdb/rdb, word, dup, ctxt_disp"
+     ((MACH ms1-003,ms2))
+     "mfbcbincrs $frsr1,$frsr2,#$perm,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp"
+     (+ MSYS_YES MSOPC_MFBCBINCRS perm frsr1 frsr2 (f-uu-1-15 0) cbx ccb cdb rownum2 dup ctxdisp)
+     (nop)
+     ()
+)
+
+; MS2 instructions
+(dni loop "LOOP SrcReg1, label"
+     ((MACH ms2) DELAY-SLOT USES-FRSR1)
+     "loop $frsr1,$loopsize"
+     (+ MSYS_NO OPC_LOOP IMM_NO frsr1 (f-uu4a 0) (f-uu8 0) loopsize)
+     (nop)      ;; to be filled in
+     ()
+)
+
+(dni loopi "LOOPI niter, label"
+     ((MACH ms2) DELAY-SLOT)
+     "loopi #$imm16l,$loopsize"
+     (+ MSYS_NO OPC_LOOP IMM_YES imm16l loopsize)
+     (nop)      ;; to be filled in
+     ()
+)
+
+(dni dfbc "dfbc cb1sel,cb2sel,cb1inc,cb2inc,dr/c,cr/c,ctxdisp"
+     ((MACH ms2))
+     "dfbc #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp"
+     (+ MSYS_YES MSOPC_LDCTXT cb1sel cb2sel cb1incr cb2incr rc3 rc2 ctxdisp)
+     (nop)
+     ()
+)
+
+(dni dwfb "dwfb cb1sel,cb2sel,cb1inc,cb2inc,cr/c,ctxdisp"
+     ((MACH ms2))
+     "dwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc2,#$ctxdisp"
+     (+ MSYS_YES MSOPC_LDFB cb1sel cb2sel cb1incr cb2incr (f-uu1 0) rc2 ctxdisp)
+     (nop)
+     ()
+)
+
+(dni fbwfb "fbwfb cb1sel,cb2sel,cb1inc,cb2inc,r0/1,cr/c,ctxdisp"
+     ((MACH ms2))
+     "fbwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp"
+     (+ MSYS_YES MSOPC_STFB cb1sel cb2sel cb1incr cb2incr rc3 rc2 ctxdisp)
+     (nop)
+     ()
+)
+
+(dni dfbr "dfbr cb1sel,cb2sel,reg,W/O1,W/O2,mode,cr/c,ctxdisp"
+     ((MACH ms2) USES-FRSR2)
+     "dfbr #$cb1sel,#$cb2sel,$frsr2,#$length,#$rownum1,#$rownum2,#$rc2,#$ctxdisp"
+     (+ MSYS_YES MSOPC_FBCB cb1sel cb2sel frsr2 length rownum1 rownum2 rc2 ctxdisp)
+     (nop)
+     ()
+)

diff --git a/cpu/mt.opc b/cpu/mt.opc
new file mode 100644 (file)
index 0000000..3da6d0e
--- /dev/null
+++ b/cpu/mt.opc
@@ -0,0 +1,472 @@
+/* Morpho Technologies mRISC opcode support, for GNU Binutils.  -*- C -*-
+   Copyright 2001, 2007, 2008, 2009 Free Software Foundation, Inc.
+
+   Contributed by Red Hat Inc; developed under contract from
+   Morpho Technologies.
+
+   This file is part of the GNU Binutils.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+
+/* Each section is delimited with start and end markers.
+
+   <arch>-opc.h additions use: "-- opc.h"
+   <arch>-opc.c additions use: "-- opc.c"
+   <arch>-asm.c additions use: "-- asm.c"
+   <arch>-dis.c additions use: "-- dis.c"
+   <arch>-ibd.h additions use: "-- ibd.h"  */
+\f
+/* -- opc.h */
+
+/* Check applicability of instructions against machines.  */
+#define CGEN_VALIDATE_INSN_SUPPORTED
+
+/* Allows reason codes to be output when assembler errors occur.  */
+#define CGEN_VERBOSE_ASSEMBLER_ERRORS
+
+/* Override disassembly hashing - there are variable bits in the top
+   byte of these instructions.  */
+#define CGEN_DIS_HASH_SIZE 8
+#define CGEN_DIS_HASH(buf, value) (((* (unsigned char *) (buf)) >> 5) % CGEN_DIS_HASH_SIZE)
+
+#define CGEN_ASM_HASH_SIZE 127
+#define CGEN_ASM_HASH(insn) mt_asm_hash (insn)
+
+extern unsigned int mt_asm_hash (const char *);
+
+extern int mt_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
+
+\f
+/* -- opc.c */
+#include "safe-ctype.h"
+
+/* Special check to ensure that instruction exists for given machine.  */
+
+int
+mt_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
+{
+  int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH);
+
+  /* No mach attribute?  Assume it's supported for all machs.  */
+  if (machs == 0)
+    return 1;
+  
+  return ((machs & cd->machs) != 0);
+}
+
+/* A better hash function for instruction mnemonics.  */
+
+unsigned int
+mt_asm_hash (const char* insn)
+{
+  unsigned int hash;
+  const char* m = insn;
+
+  for (hash = 0; *m && ! ISSPACE (*m); m++)
+    hash = (hash * 23) ^ (0x1F & TOLOWER (*m));
+
+  /* printf ("%s %d\n", insn, (hash % CGEN_ASM_HASH_SIZE)); */
+
+  return hash % CGEN_ASM_HASH_SIZE;
+}
+
+\f
+/* -- asm.c */
+/* Range checking for signed numbers.  Returns 0 if acceptable
+   and 1 if the value is out of bounds for a signed quantity.  */
+
+static int 
+signed_out_of_bounds (long val)
+{
+  if ((val < -32768) || (val > 32767))
+    return 1;
+  return 0;
+}
+
+static const char *
+parse_loopsize (CGEN_CPU_DESC cd,
+               const char **strp,
+               int opindex,
+               void *arg)
+{
+  signed long * valuep = (signed long *) arg;
+  const char *errmsg;
+  bfd_reloc_code_real_type code = BFD_RELOC_NONE;
+  enum cgen_parse_operand_result result_type;
+  bfd_vma value;
+
+  /* Is it a control transfer instructions?  */ 
+  if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_LOOPSIZE)
+    {
+      code = BFD_RELOC_MT_PCINSN8;
+      errmsg = cgen_parse_address (cd, strp, opindex, code,
+                                   & result_type, & value);
+      *valuep = value;
+      return errmsg;
+    }
+
+  abort ();
+}
+
+static const char *
+parse_imm16 (CGEN_CPU_DESC cd,
+            const char **strp,
+            int opindex,
+            void *arg)
+{
+  signed long * valuep = (signed long *) arg;
+  const char *errmsg;
+  enum cgen_parse_operand_result result_type;
+  bfd_reloc_code_real_type code = BFD_RELOC_NONE;
+  bfd_vma value;
+
+  /* Is it a control transfer instructions?  */ 
+  if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_IMM16O)
+    {
+      code = BFD_RELOC_16_PCREL;
+      errmsg = cgen_parse_address (cd, strp, opindex, code,
+                                   & result_type, & value);
+      if (errmsg == NULL)
+       {
+         if (signed_out_of_bounds (value))
+           errmsg = _("Operand out of range. Must be between -32768 and 32767.");
+       }
+      *valuep = value;
+      return errmsg;
+    }
+
+  /* If it's not a control transfer instruction, then
+     we have to check for %OP relocating operators.  */
+  if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_IMM16L)
+    ;
+  else if (strncmp (*strp, "%hi16", 5) == 0)
+    {
+      *strp += 5;
+      code = BFD_RELOC_HI16;
+    }
+  else if (strncmp (*strp, "%lo16", 5) == 0)
+    {
+      *strp += 5;
+      code = BFD_RELOC_LO16;
+    }
+
+  /* If we found a %OP relocating operator, then parse it as an address.
+     If not, we need to parse it as an integer, either signed or unsigned
+     depending on which operand type we have.  */
+  if (code != BFD_RELOC_NONE)
+    {
+       /* %OP relocating operator found.  */
+       errmsg = cgen_parse_address (cd, strp, opindex, code,
+                                   & result_type, & value);
+       if (errmsg == NULL)
+        {
+           switch (result_type)
+            {
+            case (CGEN_PARSE_OPERAND_RESULT_NUMBER):
+              if (code == BFD_RELOC_HI16)
+                value = (value >> 16) & 0xFFFF;
+              else if (code == BFD_RELOC_LO16)
+                value = value  & 0xFFFF;
+              else 
+                errmsg = _("Biiiig Trouble in parse_imm16!");
+              break;
+
+            case (CGEN_PARSE_OPERAND_RESULT_QUEUED):
+              /* No special processing for this case.  */
+              break;
+
+            default:
+              errmsg = _("The percent-operator's operand is not a symbol");
+              break;
+             }
+        }
+       *valuep = value;
+    }
+  else
+    {
+      /* Parse hex values like 0xffff as unsigned, and sign extend
+        them manually.  */
+      int parse_signed = (opindex == (CGEN_OPERAND_TYPE)MT_OPERAND_IMM16);
+
+      if ((*strp)[0] == '0'
+         && ((*strp)[1] == 'x' || (*strp)[1] == 'X'))
+       parse_signed = 0;
+
+      /* No relocating operator.  Parse as an number.  */
+      if (parse_signed)
+       {
+          /* Parse as as signed integer.  */
+ 
+          errmsg = cgen_parse_signed_integer (cd, strp, opindex, valuep);
+
+          if (errmsg == NULL) 
+           {
+#if 0
+             /* Manual range checking is needed for the signed case.  */
+             if (*valuep & 0x8000)
+                value = 0xffff0000 | *valuep;
+             else 
+                value = *valuep;
+
+             if (signed_out_of_bounds (value))
+               errmsg = _("Operand out of range. Must be between -32768 and 32767.");
+             /* Truncate to 16 bits. This is necessary
+                because cgen will have sign extended *valuep.  */
+             *valuep &= 0xFFFF; 
+#endif
+           }
+       }
+      else  
+       {
+          /* MT_OPERAND_IMM16Z.  Parse as an unsigned integer.  */
+          errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, (unsigned long *) valuep);
+
+         if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_IMM16
+             && *valuep >= 0x8000
+             && *valuep <= 0xffff)
+           *valuep -= 0x10000;
+       }
+    }
+
+  return errmsg;
+}
+
+
+static const char *
+parse_dup (CGEN_CPU_DESC cd,
+          const char **strp,
+          int opindex,
+          unsigned long *valuep)
+{
+  const char *errmsg = NULL;
+
+  if (strncmp (*strp, "dup", 3) == 0 || strncmp (*strp, "DUP", 3) == 0)
+    {
+      *strp += 3;
+      *valuep = 1;
+    }
+  else if (strncmp (*strp, "xx", 2) == 0 || strncmp (*strp, "XX", 2) == 0)
+    {
+      *strp += 2;
+      *valuep = 0;
+    }
+  else
+    errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
+
+  return errmsg;
+}
+
+
+static const char *
+parse_ball (CGEN_CPU_DESC cd,
+           const char **strp,
+           int opindex,
+           unsigned long *valuep)
+{
+  const char *errmsg = NULL;
+
+  if (strncmp (*strp, "all", 3) == 0 || strncmp (*strp, "ALL", 3) == 0)
+    {
+      *strp += 3;
+      *valuep = 1;
+    }
+  else if (strncmp (*strp, "one", 3) == 0 || strncmp (*strp, "ONE", 3) == 0)
+    {
+      *strp += 3;
+      *valuep = 0;
+    }
+  else
+    errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
+
+  return errmsg;
+}
+
+static const char *
+parse_xmode (CGEN_CPU_DESC cd,
+            const char **strp,
+            int opindex,
+            unsigned long *valuep)
+{
+  const char *errmsg = NULL;
+
+  if (strncmp (*strp, "pm", 2) == 0 || strncmp (*strp, "PM", 2) == 0)
+    {
+      *strp += 2;
+      *valuep = 1;
+    }
+  else if (strncmp (*strp, "xm", 2) == 0 || strncmp (*strp, "XM", 2) == 0)
+    {
+      *strp += 2;
+      *valuep = 0;
+    }
+  else
+    errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
+
+  return errmsg;
+}
+
+static const char *
+parse_rc (CGEN_CPU_DESC cd,
+         const char **strp,
+         int opindex,
+         unsigned long *valuep)
+{
+  const char *errmsg = NULL;
+
+  if (strncmp (*strp, "r", 1) == 0 || strncmp (*strp, "R", 1) == 0)
+    {
+      *strp += 1;
+      *valuep = 1;
+    }
+  else if (strncmp (*strp, "c", 1) == 0 || strncmp (*strp, "C", 1) == 0)
+    {
+      *strp += 1;
+      *valuep = 0;
+    }
+  else
+    errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
+
+  return errmsg;
+}
+
+static const char *
+parse_cbrb (CGEN_CPU_DESC cd,
+           const char **strp,
+           int opindex,
+           unsigned long *valuep)
+{
+  const char *errmsg = NULL;
+
+  if (strncmp (*strp, "rb", 2) == 0 || strncmp (*strp, "RB", 2) == 0)
+    {
+      *strp += 2;
+      *valuep = 1;
+    }
+  else if (strncmp (*strp, "cb", 2) == 0 || strncmp (*strp, "CB", 2) == 0)
+    {
+      *strp += 2;
+      *valuep = 0;
+    }
+  else
+    errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
+
+  return errmsg;
+}
+
+static const char *
+parse_rbbc (CGEN_CPU_DESC cd,
+           const char **strp,
+           int opindex,
+           unsigned long *valuep)
+{
+  const char *errmsg = NULL;
+
+  if (strncmp (*strp, "rt", 2) == 0 || strncmp (*strp, "RT", 2) == 0)
+    {
+      *strp += 2;
+      *valuep = 0;
+    }
+  else if (strncmp (*strp, "br1", 3) == 0 || strncmp (*strp, "BR1", 3) == 0)
+    {
+      *strp += 3;
+      *valuep = 1;
+    }
+  else if (strncmp (*strp, "br2", 3) == 0 || strncmp (*strp, "BR2", 3) == 0)
+    {
+      *strp += 3;
+      *valuep = 2;
+    }
+  else if (strncmp (*strp, "cs", 2) == 0 || strncmp (*strp, "CS", 2) == 0)
+    {
+      *strp += 2;
+      *valuep = 3;
+    }
+  else
+    errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
+
+  return errmsg;
+}
+
+static const char *
+parse_type (CGEN_CPU_DESC cd,
+           const char **strp,
+           int opindex,
+           unsigned long *valuep)
+{
+  const char *errmsg = NULL;
+
+  if (strncmp (*strp, "odd", 3) == 0 || strncmp (*strp, "ODD", 3) == 0)
+    {
+      *strp += 3;
+      *valuep = 0;
+    }
+  else if (strncmp (*strp, "even", 4) == 0 || strncmp (*strp, "EVEN", 4) == 0)
+    {
+      *strp += 4;
+      *valuep = 1;
+    }
+  else if (strncmp (*strp, "oe", 2) == 0 || strncmp (*strp, "OE", 2) == 0)
+    {
+      *strp += 2;
+      *valuep = 2;
+    }
+  else
+    errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
+
+ if ((errmsg == NULL) && (*valuep == 3))
+    errmsg = _("invalid operand.  type may have values 0,1,2 only.");
+
+  return errmsg;
+}
+
+/* -- dis.c */
+static void print_dollarhex (CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int);
+static void print_pcrel (CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int);
+
+static void
+print_dollarhex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+                void * dis_info,
+                long value,
+                unsigned int attrs ATTRIBUTE_UNUSED,
+                bfd_vma pc ATTRIBUTE_UNUSED,
+                int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+
+  info->fprintf_func (info->stream, "$%lx", value);
+
+  if (0)
+    print_normal (cd, dis_info, value, attrs, pc, length);
+}
+
+static void
+print_pcrel (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+            void * dis_info,
+            long value,
+            unsigned int attrs ATTRIBUTE_UNUSED,
+            bfd_vma pc ATTRIBUTE_UNUSED,
+            int length ATTRIBUTE_UNUSED)
+{
+  print_address (cd, dis_info, value + pc, attrs, pc, length);
+}
+
+/* -- */
+
+
+
+
+

diff --git a/cpu/sh.cpu b/cpu/sh.cpu
new file mode 100644 (file)
index 0000000..d9ece1a
--- /dev/null
+++ b/cpu/sh.cpu
@@ -0,0 +1,369 @@
+; Hitachi SH architecture description.  -*- Scheme -*-
+;
+; Copyright 2000, 2001, 2007, 2009 Free Software Foundation, Inc.
+;
+; Contributed by Red Hat Inc; developed under contract from Hitachi
+; Semiconductor (America) Inc.
+;
+; This file is part of the GNU Binutils.
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 3 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, write to the Free Software
+; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+; MA 02110-1301, USA.
+
+
+(include "simplify.inc")
+
+(define-arch
+  (name sh)
+  (comment "Hitachi SuperH (SH)")
+  (insn-lsb0? #t)
+  (machs sh2 sh3 sh3e sh4 sh5)
+  (isas compact media)
+)
+
+\f
+; Instruction sets.
+
+(define-isa
+  (name media)
+  (comment "SHmedia 32-bit instruction set")
+  (base-insn-bitsize 32)
+)
+
+(define-isa
+  (name compact)
+  (comment "SHcompact 16-bit instruction set")
+  (base-insn-bitsize 16)
+)
+
+\f
+; CPU family.
+
+(define-cpu
+  (name sh64)
+  (comment "SH 64-bit family")
+  (endian either)
+  (word-bitsize 32)
+)
+\f
+
+(define-mach
+  (name sh2)
+  (comment "SH-2 CPU core")
+  (cpu sh64)
+  (isas compact)
+)
+
+(define-mach
+  (name sh3)
+  (comment "SH-3 CPU core")
+  (cpu sh64)
+  (isas compact)
+)
+
+(define-mach
+  (name sh3e)
+  (comment "SH-3e CPU core")
+  (cpu sh64)
+  (isas compact)
+)
+
+(define-mach
+  (name sh4)
+  (comment "SH-4 CPU core")
+  (cpu sh64)
+  (isas compact)
+)
+
+(define-mach
+  (name sh5)
+  (comment "SH-5 CPU core")
+  (cpu sh64)
+  (isas compact media)
+)
+
+(define-model
+  (name sh5)
+  (comment "SH-5 reference implementation")
+  (mach sh5)
+  (unit u-exec "Execution unit" ()
+       1 1 ; issue done
+       () () () ())
+)
+\f
+; Hardware elements.
+
+(define-hardware
+  (name h-pc)
+  (comment "Program counter")
+  (attrs PC (ISA compact,media))
+  (type pc UDI)
+  (get () (raw-reg h-pc))
+  (set (newval) (sequence ()
+                         (set (raw-reg h-ism) (and newval 1))
+                         (set (raw-reg h-pc) (and newval (inv UDI 1)))))
+)
+
+(define-pmacro (-build-greg-name n) ((.sym r n) n))
+
+(define-hardware
+  (name h-gr)
+  (comment "General purpose integer registers")
+  (attrs (ISA media,compact))
+  (type register DI (64))
+  (indices keyword "" (.map -build-greg-name (.iota 64)))
+  (get (index)
+       (if DI (eq index 63)
+          (const 0)
+          (raw-reg h-gr index)))
+  (set (index newval)
+       (if (ne index 63)
+          (set (raw-reg h-gr index) newval)
+          (nop)))
+)
+
+(define-hardware
+  (name h-grc)
+  (comment "General purpose integer registers (SHcompact view)")
+  (attrs VIRTUAL (ISA compact))
+  (type register SI (16))
+  (indices keyword "" (.map -build-greg-name (.iota 16)))
+  (get (index)
+       (and (raw-reg h-gr index) (zext DI #xFFFFFFFF)))
+  (set (index newval)
+       (set (raw-reg h-gr index) (ext DI newval)))
+)
+
+(define-pmacro (-build-creg-name n) ((.sym cr n) n))
+
+(define-hardware
+  (name h-cr)
+  (comment "Control registers")
+  (attrs (ISA media))
+  (type register DI (64))
+  (indices keyword "" (.map -build-creg-name (.iota 64)))
+  (get (index)
+       (if DI (eq index 0)
+          (zext DI (reg h-sr))
+          (raw-reg h-cr index)))
+  (set (index newval)
+       (if (eq index 0)
+          (set (reg h-sr) newval)
+          (set (raw-reg h-cr index) newval)))
+)
+
+(define-hardware
+  (name h-sr)
+  (comment "Status register")
+  (attrs (ISA compact,media))
+  (type register SI)
+)
+
+(define-hardware
+  (name h-fpscr)
+  (comment "Floating point status and control register")
+  (attrs (ISA compact,media))
+  (type register SI)
+)
+
+(define-hardware
+  (name h-frbit)
+  (comment "Floating point register file bit")
+  (attrs (ISA media,compact) VIRTUAL)
+  (type register BI)
+  (get () (and (srl (reg h-sr) 14) 1))
+  (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 14))) (sll SI newvalue 14))))
+)
+
+(define-hardware
+  (name h-szbit)
+  (comment "Floating point transfer size bit")
+  (attrs (ISA media,compact) VIRTUAL)
+  (type register BI)
+  (get () (and (srl (reg h-sr) 13) 1))
+  (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 13))) (sll SI newvalue 13))))
+)
+
+(define-hardware
+  (name h-prbit)
+  (comment "Floating point precision bit")
+  (attrs (ISA media,compact) VIRTUAL)
+  (type register BI)
+  (get () (and (srl (reg h-sr) 12) 1))
+  (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 12))) (sll SI newvalue 12))))
+)
+
+(define-hardware
+  (name h-sbit)
+  (comment "Multiply-accumulate saturation flag")
+  (attrs (ISA compact) VIRTUAL)
+  (type register BI)
+  (get () (and (srl (reg h-sr) 1) 1))
+  (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv 2)) (sll SI newvalue 1))))
+)
+
+(define-hardware
+  (name h-mbit)
+  (comment "Divide-step M flag")
+  (attrs (ISA compact) VIRTUAL)
+  (type register BI)
+  (get () (and (srl (reg h-sr) 9) 1))
+  (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 9))) (sll SI newvalue 9))))
+)
+
+(define-hardware
+  (name h-qbit)
+  (comment "Divide-step Q flag")
+  (attrs (ISA compact) VIRTUAL)
+  (type register BI)
+  (get () (and (srl (reg h-sr) 8) 1))
+  (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 8))) (sll SI newvalue 8))))
+)
+
+(define-pmacro (-build-freg-name n) ((.sym fr n) n))
+
+(define-hardware
+  (name h-fr)
+  (comment "Single precision floating point registers")
+  (attrs (ISA media,compact))
+  (type register SF (64))
+  (indices keyword "" (.map -build-freg-name (.iota 64)))
+)
+
+
+(define-pmacro (-build-fpair-name n) ((.sym fp n) n))
+
+(define-hardware
+  (name h-fp)
+  (comment "Single precision floating point register pairs")
+  (attrs (ISA media,compact))
+  (type register DF (32))
+  (indices keyword "" (.map -build-fpair-name (.iota 32)))
+)
+
+(define-pmacro (-build-fvec-name n) ((.sym fv n) n))
+
+(define-hardware
+  (name h-fv)
+  (comment "Single precision floating point vectors")
+  (attrs VIRTUAL (ISA media,compact))
+  (type register SF (16))
+  (indices keyword "" (.map -build-fvec-name (.iota 16)))
+  ; Mask with $F to ensure 0 <= index < 15.
+  (get (index) (reg h-fr (mul (and UQI index 15) 4)))
+  (set (index newval) (set (reg h-fr (mul (and UQI index 15) 4)) newval))
+)
+
+(define-hardware
+  (name h-fmtx)
+  (comment "Single precision floating point matrices")
+  (attrs VIRTUAL (ISA media))
+  (type register SF (4))
+  (indices keyword "" ((mtrx0 0) (mtrx1 1) (mtrx2 2) (mtrx3 3)))
+  ; Mask with $3 to ensure 0 <= index < 4.
+  (get (index) (reg h-fr (mul (and UQI index 3) 16)))
+  (set (index newval) (set (reg h-fr (mul (and UQI index 3) 16)) newval))
+)
+
+(define-pmacro (-build-dreg-name n) ((.sym dr n) n))
+
+(define-hardware
+  (name h-dr)
+  (comment "Double precision floating point registers")
+  (attrs (ISA media,compact) VIRTUAL)
+  (type register DF (32))
+  (indices keyword "" (.map -build-dreg-name (.iota 64)))
+  (get (index)
+       (subword DF
+               (or
+                (sll DI (zext DI (subword SI (reg h-fr index) 0)) 32)
+                (zext DI (subword SI (reg h-fr (add index 1)) 0))) 0))
+  (set (index newval)
+       (sequence ()
+                (set (reg h-fr index)
+                     (subword SF (subword SI newval 0) 0))
+                (set (reg h-fr (add index 1))
+                     (subword SF (subword SI newval 1) 0))))
+)
+
+(define-hardware
+  (name h-tr)
+  (comment "Branch target registers")
+  (attrs (ISA media))
+  (type register DI (8))
+  (indices keyword "" ((tr0 0) (tr1 1) (tr2 2) (tr3 3) (tr4 4) (tr5 5) (tr6 6) (tr7 7)))
+)
+
+(define-hardware
+  (name h-endian)
+  (comment "Current endian mode")
+  (attrs (ISA compact,media) VIRTUAL)
+  (type register BI)
+  (get () (c-call BI "sh64_endian"))
+  (set (newval) (error "cannot alter target byte order mid-program"))
+)
+
+(define-hardware
+  (name h-ism)
+  (comment "Current instruction set mode")
+  (attrs (ISA compact,media))
+  (type register BI)
+  (get () (raw-reg h-ism))
+  (set (newval) (error "cannot set ism directly"))
+)
+
+\f
+; Operands.
+
+(dnop endian "Endian mode" ((ISA compact,media)) h-endian f-nil)
+(dnop ism    "Instruction set mode" ((ISA compact,media)) h-ism f-nil)
+
+; Universally useful macros.
+
+; A pmacro for use in semantic bodies of unimplemented insns.
+(define-pmacro (unimp mnemonic) (nop))
+
+; Join 2 ints together in natural bit order.
+(define-pmacro (-join-si s1 s0)
+  (or (sll (zext DI s1) 32)
+      (zext DI s0)))
+
+; Join 4 half-ints together in natural bit order.
+(define-pmacro (-join-hi h3 h2 h1 h0)
+  (or (sll (zext DI h3) 48)
+      (or (sll (zext DI h2) 32)
+         (or (sll (zext DI h1) 16)
+             (zext DI h0)))))
+
+; Join 8 quarter-ints together in natural bit order.
+(define-pmacro (-join-qi b7 b6 b5 b4 b3 b2 b1 b0)
+  (or (sll (zext DI b7) 56)
+      (or (sll (zext DI b6) 48)
+         (or (sll (zext DI b5) 40)
+             (or (sll (zext DI b4) 32)
+                 (or (sll (zext DI b3) 24)
+                     (or (sll (zext DI b2) 16)
+                         (or (sll (zext DI b1) 8)
+                             (zext DI b0)))))))))
+
+\f
+; Include the two instruction set descriptions from their respective
+; source files.
+
+(if (keep-isa? (compact))
+    (include "sh64-compact.cpu"))
+
+(if (keep-isa? (media))
+    (include "sh64-media.cpu"))

diff --git a/cpu/sh.opc b/cpu/sh.opc
new file mode 100644 (file)
index 0000000..364fccc
--- /dev/null
+++ b/cpu/sh.opc
@@ -0,0 +1,77 @@
+/* SHmedia opcode support.  -*- C -*-
+
+   Copyright 2000, 2005, 2007, 2009 Free Software Foundation, Inc.
+
+   Contributed by Red Hat Inc; developed under contract from Hitachi
+   Semiconductor (America) Inc.
+
+   This file is part of the GNU Binutils.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+
+/* This file is an addendum to sh-media.cpu.  Heavy use of C code isn't
+   appropriate in .cpu files, so it resides here.  This especially applies
+   to assembly/disassembly where parsing/printing can be quite involved.
+   Such things aren't really part of the specification of the cpu, per se,
+   so .cpu files provide the general framework and .opc files handle the
+   nitty-gritty details as necessary.
+
+   Each section is delimited with start and end markers.
+
+   <arch>-opc.h additions use: "-- opc.h"
+   <arch>-opc.c additions use: "-- opc.c"
+   <arch>-asm.c additions use: "-- asm.c"
+   <arch>-dis.c additions use: "-- dis.c"
+   <arch>-ibd.h additions use: "-- ibd.h"  */
+\f
+/* -- opc.h */
+
+/* Allows reason codes to be output when assembler errors occur.  */
+#define CGEN_VERBOSE_ASSEMBLER_ERRORS
+
+/* Override disassembly hashing - there are variable bits in the top
+   byte of these instructions.  */
+#define CGEN_DIS_HASH_SIZE 8
+#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 6) % CGEN_DIS_HASH_SIZE)
+
+/* -- asm.c */
+
+static const char *
+parse_fsd (CGEN_CPU_DESC cd,
+          const char ** strp,
+          int opindex,
+          long * valuep)
+{
+  abort ();
+}
+
+/* -- dis.c */
+
+static void
+print_likely (CGEN_CPU_DESC cd,
+             void * dis_info,
+             long value,
+             unsigned int attrs,
+             bfd_vma pc,
+             int length)
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+
+  (*info->fprintf_func) (info->stream, (value) ? "/l" : "/u");
+}
+
+/* -- */

diff --git a/cpu/sh64-compact.cpu b/cpu/sh64-compact.cpu
new file mode 100644 (file)
index 0000000..5b1b863
--- /dev/null
+++ b/cpu/sh64-compact.cpu
@@ -0,0 +1,1748 @@
+; Hitachi SHcompact instruction set description.  -*- Scheme -*-
+;
+; Copyright 2000, 2007, 2009 Free Software Foundation, Inc.
+;
+; Contributed by Red Hat Inc; developed under contract from Hitachi
+; Semiconductor (America) Inc.
+;
+; This file is part of the GNU Binutils.
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 3 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, write to the Free Software
+; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+; MA 02110-1301, USA.
+\f
+; dshcf -- define-normal-sh-compact-field
+
+(define-pmacro (dshcf xname xcomment ignored xstart xlength)
+  (dnf xname xcomment ((ISA compact)) xstart xlength))
+
+; dshcop -- define-normal-sh-compact-operand
+
+(define-pmacro (dshcop xname xcomment ignored xhardware xfield)
+  (dnop xname xcomment ((ISA compact)) xhardware xfield))
+
+\f
+; SHcompact-specific attributes.
+
+(define-attr
+  (for insn)
+  (type boolean)
+  (name ILLSLOT)
+  (comment "instruction may not appear in a delay slot")
+)
+
+(define-attr
+  (for insn)
+  (type boolean)
+  (name FP-INSN)
+  (comment "floating point instruction")
+)
+
+(define-keyword
+  (name frc-names)
+  (attrs (ISA compact))
+  (print-name h-frc)
+  (values (fr0   0) (fr1   1) (fr2   2) (fr3   3) (fr4   4) (fr5   5)
+         (fr6   6) (fr7   7) (fr8   8) (fr9   9) (fr10 10) (fr11 11)
+         (fr12 12) (fr13 13) (fr14 14) (fr15 15))
+)
+
+(define-keyword
+  (name drc-names)
+  (attrs (ISA compact))
+  (print-name h-drc)
+  (values (dr0 0) (dr2 2) (dr4 4) (dr6 6) (dr8 8) (dr10 10) (dr12 12) (dr14 14))
+)
+
+(define-keyword
+  (name xf-names)
+  (attrs (ISA compact))
+  (print-name h-xf)
+  (values (xf0   0) (xf1   1) (xf2   2) (xf3   3) (xf4   4) (xf5   5)
+         (xf6   6) (xf7   7) (xf8   8) (xf9   9) (xf10 10) (xf11 11)
+         (xf12 12) (xf13 13) (xf14 14) (xf15 15))
+)
+
+; Hardware specific to the SHcompact mode.
+
+(define-pmacro (front) (mul 16 frbit))
+(define-pmacro (back) (mul 16 (not frbit)))
+
+(define-hardware
+  (name h-frc)
+  (comment "Single precision floating point registers")
+  (attrs VIRTUAL (ISA compact))
+  (indices extern-keyword frc-names)
+  (type register SF (16))
+  (get (index) (reg h-fr (add (front) index)))
+  (set (index newval) (set (reg h-fr (add (front) index)) newval))
+)
+
+(define-hardware
+  (name h-drc)
+  (comment "Double precision floating point registers")
+  (attrs VIRTUAL (ISA compact))
+  (indices extern-keyword drc-names)
+  (type register DF (8))
+  (get (index) (reg h-dr (add (front) index)))
+  (set (index newval) (set (reg h-dr (add (front) index)) newval))
+)
+
+(define-hardware
+  (name h-xf)
+  (comment "Extended single precision floating point registers")
+  (attrs VIRTUAL (ISA compact))
+  (indices extern-keyword xf-names)
+  (type register SF (16))
+  (get (index) (reg h-fr (add (back) index)))
+  (set (index newval) (set (reg h-fr (add (back) index)) newval))
+)
+
+(define-hardware
+  (name h-xd)
+  (comment "Extended double precision floating point registers")
+  (attrs VIRTUAL (ISA compact))
+  (indices extern-keyword frc-names)
+  (type register DF (8))
+  (get (index) (reg h-dr (add (back) index)))
+  (set (index newval) (set (reg h-dr (add (back) index)) newval))
+)
+
+(define-hardware
+  (name h-fvc)
+  (comment "Single precision floating point vectors")
+  (attrs VIRTUAL (ISA compact))
+  (indices keyword "" ((fv0 0) (fv4 4) (fv8 8) (fv12 12)))
+  (type register SF (4))
+  (get (index) (reg h-fr (add (front) index)))
+  (set (index newval) (set (reg h-fr (add (front) index)) newval))
+)
+
+(define-hardware
+  (name h-fpccr)
+  (comment "SHcompact floating point status/control register")
+  (attrs VIRTUAL (ISA compact))
+  (type register SI)
+  (get () (or (or (or (raw-reg h-fpscr) (sll SI prbit 19)) (sll SI szbit 20)) (sll SI frbit 21)))
+  (set (newvalue) (sequence ()
+                           (set (reg h-fpscr) newvalue)
+                           (set prbit (and (srl newvalue 19) 1))
+                           (set szbit (and (srl newvalue 20) 1))
+                           (set frbit (and (srl newvalue 21) 1))))
+)
+
+(define-hardware
+  (name h-gbr)
+  (comment "Global base register")
+  (attrs VIRTUAL (ISA compact))
+  (type register SI)
+  (get () (subword SI (raw-reg h-gr 16) 1))
+  (set (newval) (set (raw-reg h-gr 16) (ext DI newval)))
+)
+
+(define-hardware
+  (name h-pr)
+  (comment "Procedure link register")
+  (attrs VIRTUAL (ISA compact))
+  (type register SI)
+  (get () (subword SI (raw-reg h-gr 18) 1))
+  (set (newval) (set (raw-reg h-gr 18) (ext DI newval)))
+)
+
+(define-hardware
+  (name h-macl)
+  (comment "Multiple-accumulate low register")
+  (attrs VIRTUAL (ISA compact))
+  (type register SI)
+  (get () (subword SI (raw-reg h-gr 17) 1))
+  (set (newval) (set (raw-reg h-gr 17) (-join-si (subword SI (raw-reg h-gr 17) 0) newval)))
+)
+
+(define-hardware
+  (name h-mach)
+  (comment "Multiply-accumulate high register")
+  (attrs VIRTUAL (ISA compact))
+  (type register SI)
+  (get () (subword SI (raw-reg h-gr 17) 0))
+  (set (newval) (set (raw-reg h-gr 17) (-join-si newval (subword SI (raw-reg h-gr 17) 1))))
+)
+  
+(define-hardware
+  (name h-tbit)
+  (comment "Condition code flag")
+  (attrs VIRTUAL (ISA compact))
+  (type register BI)
+  (get () (and BI (raw-reg h-gr 19) 1))
+  (set (newval) (set (raw-reg h-gr 19) (or (and (raw-reg h-gr 19) (inv DI 1)) (zext DI newval))))
+)
+
+\f
+(dshcf f-op4     "Opcode (4 bits)"         ()  15   4)
+(dshcf f-op8     "Opcode (8 bits)"         ()  15   8)
+(dshcf f-op16    "Opcode (16 bits)"        ()  15  16)
+
+(dshcf f-sub4    "Sub opcode (4 bits)"     ()   3   4)
+(dshcf f-sub8    "Sub opcode (8 bits)"     ()   7   8)
+(dshcf f-sub10   "Sub opcode (10 bits)"    ()   9  10)
+
+(dshcf f-rn      "Register selector n"     ()  11   4)
+(dshcf f-rm      "Register selector m"     ()   7   4)
+
+(dshcf f-8-1     "One bit at bit 8"        ()   8   1)
+
+(df  f-disp8  "Displacement (8 bits)"  ((ISA compact) PCREL-ADDR) 7 8 INT
+     ((value pc) (sra SI value 1))
+     ((value pc) (add SI (sll SI value 1) (add pc 4))))
+
+(df  f-disp12 "Displacement (12 bits)" ((ISA compact) PCREL-ADDR) 11 12 INT
+     ((value pc) (sra SI value 1))
+     ((value pc) (add SI (sll SI value 1) (add pc 4))))
+
+(dshcf f-imm8    "Immediate (8 bits)"      ()   7   8)
+(dshcf f-imm4    "Immediate (4 bits)"      ()   3   4)
+
+(df f-imm4x2     "Immediate (4 bits)"      ((ISA compact)) 3 4 UINT
+    ((value pc) (srl SI value 1))
+    ((value pc) (sll SI value 1)))
+
+(df f-imm4x4     "Immediate (4 bits)"      ((ISA compact)) 3 4 UINT
+    ((value pc) (srl SI value 2))
+    ((value pc) (sll SI value 2)))
+
+(df f-imm8x2     "Immediate (8 bits)"      ((ISA compact)) 7 8 UINT
+    ((value pc) (sra SI value 1))
+    ((value pc) (sll SI value 1)))
+
+(df f-imm8x4     "Immediate (8 bits)"      ((ISA compact)) 7 8 UINT
+    ((value pc) (sra SI value 2))
+    ((value pc) (sll SI value 2)))
+
+(df f-dn "Double selector n" ((ISA compact)) 11 3 UINT
+    ((value pc) (srl SI value 1))
+    ((value pc) (sll SI value 1)))
+
+(df f-dm         "Double selector m"       ((ISA compact)) 7 3 UINT
+    ((value pc) (srl SI value 1))
+    ((value pc) (sll SI value 1)))
+
+(df f-vn         "Vector selector n"       ((ISA compact)) 11 2 UINT
+    ((value pc) (srl SI value 2))
+    ((value pc) (sll SI value 2)))
+
+(df f-vm         "Vector selector m"       ((ISA compact)) 9 2 UINT
+    ((value pc) (srl SI value 2))
+    ((value pc) (sll SI value 2)))
+
+(df f-xn         "Extended selector n"     ((ISA compact)) 11 3 UINT
+    ((value pc) (srl SI value 1))
+    ((value pc) (add SI (sll SI value 1) 1)))
+
+(df f-xm         "Extended selector m"     ((ISA compact)) 7 3 UINT
+    ((value pc) (srl SI value 1))
+    ((value pc) (add SI (sll SI value 1) 1)))
+
+\f
+; Operands.
+
+(dshcop rm     "Left general purpose register"          ()   h-grc   f-rm)
+(dshcop rn     "Right general purpose register"         ()   h-grc   f-rn)
+(dshcop r0     "Register 0"                             ()   h-grc   0)
+
+(dshcop frn    "Single precision register"              ()   h-frc   f-rn)
+(dshcop frm    "Single precision register"              ()   h-frc   f-rm)
+
+(dshcop fvn    "Left floating point vector"             ()   h-fvc   f-vn)
+(dshcop fvm    "Right floating point vector"            ()   h-fvc   f-vm)
+
+(dshcop drn    "Left double precision register"         ()   h-drc   f-dn)
+(dshcop drm    "Right double precision register"        ()   h-drc   f-dm)
+
+(dshcop imm4   "Immediate value (4 bits)"              ()   h-sint  f-imm4)
+(dshcop imm8   "Immediate value (8 bits)"               ()   h-sint  f-imm8)
+(dshcop uimm8  "Immediate value (8 bits unsigned)"      ()   h-uint  f-imm8)
+
+(dshcop imm4x2 "Immediate value (4 bits, 2x scale)"     ()   h-uint  f-imm4x2)
+(dshcop imm4x4 "Immediate value (4 bits, 4x scale)"     ()   h-uint  f-imm4x4)
+(dshcop imm8x2 "Immediate value (8 bits, 2x scale)"     ()   h-uint  f-imm8x2)
+(dshcop imm8x4 "Immediate value (8 bits, 4x scale)"     ()   h-uint  f-imm8x4)
+
+(dshcop disp8  "Displacement (8 bits)"                  ()   h-iaddr f-disp8)
+(dshcop disp12 "Displacement (12 bits)"                 ()   h-iaddr f-disp12)
+
+(dshcop rm64   "Register m (64 bits)"                   ()   h-gr    f-rm)
+(dshcop rn64   "Register n (64 bits)"                   ()   h-gr    f-rn)
+
+(dshcop gbr    "Global base register"                   ()   h-gbr   f-nil)
+(dshcop pr     "Procedure link register"                ()   h-pr    f-nil)
+
+(dshcop fpscr  "Floating point status/control register" ()   h-fpccr f-nil)
+
+(dshcop tbit   "Condition code flag"                    ()   h-tbit  f-nil)
+(dshcop sbit   "Multiply-accumulate saturation flag"    ()   h-sbit  f-nil)
+(dshcop mbit   "Divide-step M flag"                     ()   h-mbit  f-nil)
+(dshcop qbit   "Divide-step Q flag"                     ()   h-qbit  f-nil)
+(dshcop fpul   "Floating point ???"                    ()   h-fr    32)
+
+(dshcop frbit  "Floating point register bank bit"       ()   h-frbit f-nil)
+(dshcop szbit  "Floating point transfer size bit"       ()   h-szbit f-nil)
+(dshcop prbit  "Floating point precision bit"           ()   h-prbit f-nil)
+
+(dshcop macl   "Multiply-accumulate low register"       ()   h-macl  f-nil)
+(dshcop mach   "Multiply-accumulate high register"      ()   h-mach  f-nil)
+
+
+(define-operand (name fsdm) (comment "bar")
+  (attrs (ISA compact)) (type h-frc) (index f-rm) (handlers (parse "fsd")))
+
+(define-operand (name fsdn) (comment "bar")
+  (attrs (ISA compact)) (type h-frc) (index f-rn))
+\f
+
+; Cover macro to dni to indicate these are all SHcompact instructions.
+; dshmi: define-normal-sh-compact-insn
+
+(define-pmacro (dshci xname xcomment xattrs xsyntax xformat xsemantics)
+  (define-insn
+    (name (.sym xname -compact))
+    (comment xcomment)
+    (.splice attrs (.unsplice xattrs) (ISA compact))
+    (syntax xsyntax)
+    (format xformat)
+    (semantics xsemantics)))
+
+(define-pmacro (dr operand) (reg h-dr (index-of operand)))
+(define-pmacro (xd x) (reg h-xd (and (index-of x) (inv QI 1))))
+\f
+(dshci add "Add"
+       ()
+       "add $rm, $rn"
+       (+ (f-op4 3) rn rm (f-sub4 12))
+       (set rn (add rn rm)))
+
+(dshci addi "Add immediate"
+       ()
+       "add #$imm8, $rn"
+       (+ (f-op4 7) rn imm8)
+       (set rn (add rn (ext SI (and QI imm8 255)))))
+
+(dshci addc "Add with carry"
+       ()
+       "addc $rm, $rn"
+       (+ (f-op4 3) rn rm (f-sub4 14))
+       (sequence ((BI flag))
+                (set flag (add-cflag rn rm tbit))
+                (set rn (addc rn rm tbit))
+                (set tbit flag)))
+
+(dshci addv "Add with overflow"
+       ()
+       "addv $rm, $rn"
+       (+ (f-op4 3) rn rm (f-sub4 15))
+       (sequence ((BI t))
+                (set t (add-oflag rn rm 0))
+                (set rn (add rn rm))
+                (set tbit t)))
+
+(dshci and "Bitwise AND"
+       ()
+       "and $rm64, $rn64"
+       (+ (f-op4 2) rn64 rm64 (f-sub4 9))
+       (set rn64 (and rm64 rn64)))
+
+(dshci andi "Bitwise AND immediate"
+       ()
+       "and #$uimm8, r0"
+       (+ (f-op8 #xc9) uimm8)
+       (set r0 (and r0 (zext DI uimm8))))
+
+(dshci andb "Bitwise AND memory byte"
+       ()
+       "and.b #$imm8, @(r0, gbr)"
+       (+ (f-op8 #xcd) imm8)
+       (sequence ((DI addr) (UQI data))
+                (set addr (add r0 gbr))
+                (set data (and (mem UQI addr) imm8))
+                (set (mem UQI addr) data)))
+
+(dshci bf "Conditional branch"
+       ()
+       "bf $disp8"
+       (+ (f-op8 #x8b) disp8)
+       (if (not tbit)
+          (set pc disp8)))
+
+(dshci bfs "Conditional branch with delay slot"
+       ()
+       "bf/s $disp8"
+       (+ (f-op8 #x8f) disp8)
+       (if (not tbit)
+          (delay 1 (set pc disp8))))
+
+(dshci bra "Branch"
+       ()
+       "bra $disp12"
+       (+ (f-op4 10) disp12)
+       (delay 1 (set pc disp12)))
+
+(dshci braf "Branch far"
+       ()
+       "braf $rn"
+       (+ (f-op4 0) rn (f-sub8 35))
+       (delay 1 (set pc (add (ext DI rn) (add pc 4)))))
+
+(dshci brk "Breakpoint"
+       ()
+       "brk"
+       (+ (f-op16 59))
+       (c-call "sh64_break" pc))
+
+(dshci bsr "Branch to subroutine"
+       ()
+       "bsr $disp12"
+       (+ (f-op4 11) disp12)
+       (delay 1 (sequence ()
+                         (set pr (add pc 4))
+                         (set pc disp12))))
+
+(dshci bsrf "Branch to far subroutine"
+       ()
+       "bsrf $rn"
+       (+ (f-op4 0) rn (f-sub8 3))
+       (delay 1 (sequence ()
+                         (set pr (add pc 4))
+                         (set pc (add (ext DI rn) (add pc 4))))))
+       
+(dshci bt "Conditional branch"
+       ()
+       "bt $disp8"
+       (+ (f-op8 #x89) disp8)
+       (if tbit
+          (set pc disp8)))
+
+(dshci bts "Conditional branch with delay slot"
+       ()
+       "bt/s $disp8"
+       (+ (f-op8 #x8d) disp8)
+       (if tbit
+          (delay 1 (set pc disp8))))
+
+(dshci clrmac "Clear MACL and MACH"
+       ()
+       "clrmac"
+       (+ (f-op16 40))
+       (sequence ()
+                (set macl 0)
+                (set mach 0)))
+
+(dshci clrs "Clear S-bit"
+       ()
+       "clrs"
+       (+ (f-op16 72))
+       (set sbit 0))
+
+(dshci clrt "Clear T-bit"
+       ()
+       "clrt"
+       (+ (f-op16 8))
+       (set tbit 0))
+
+(dshci cmpeq "Compare if equal"
+       ()
+       "cmp/eq $rm, $rn"
+       (+ (f-op4 3) rn rm (f-sub4 0))
+       (set tbit (eq rm rn)))
+
+(dshci cmpeqi "Compare if equal (immediate)"
+       ()
+       "cmp/eq #$imm8, r0"
+       (+ (f-op8 #x88) imm8)
+       (set tbit (eq r0 (ext SI (and QI imm8 255)))))
+
+(dshci cmpge "Compare if greater than or equal"
+       ()
+       "cmp/ge $rm, $rn"
+       (+ (f-op4 3) rn rm (f-sub4 3))
+       (set tbit (ge rn rm)))
+
+(dshci cmpgt "Compare if greater than"
+       ()
+       "cmp/gt $rm, $rn"
+       (+ (f-op4 3) rn rm (f-sub4 7))
+       (set tbit (gt rn rm)))
+
+(dshci cmphi "Compare if greater than (unsigned)"
+       ()
+       "cmp/hi $rm, $rn"
+       (+ (f-op4 3) rn rm (f-sub4 6))
+       (set tbit (gtu rn rm)))
+
+(dshci cmphs "Compare if greater than or equal (unsigned)"
+       ()
+       "cmp/hs $rm, $rn"
+       (+ (f-op4 3) rn rm (f-sub4 2))
+       (set tbit (geu rn rm)))
+
+(dshci cmppl "Compare if greater than zero"
+       ()
+       "cmp/pl $rn"
+       (+ (f-op4 4) rn (f-sub8 21))
+       (set tbit (gt rn 0)))
+
+(dshci cmppz "Compare if greater than or equal zero"
+       ()
+       "cmp/pz $rn"
+       (+ (f-op4 4) rn (f-sub8 17))
+       (set tbit (ge rn 0)))
+
+(dshci cmpstr "Compare bytes"
+       ()
+       "cmp/str $rm, $rn"
+       (+ (f-op4 2) rn rm (f-sub4 12))
+       (sequence ((BI t) (SI temp))
+                (set temp (xor rm rn))
+                (set t (eq (and temp #xff000000) 0))
+                (set t (or (eq (and temp #xff0000) 0) t))
+                (set t (or (eq (and temp #xff00) 0) t))
+                (set t (or (eq (and temp #xff) 0) t))
+                (set tbit (if BI (gtu t 0) 1 0))))
+
+(dshci div0s "Initialise divide-step state for signed division"
+       ()
+       "div0s $rm, $rn"
+       (+ (f-op4 2) rn rm (f-sub4 7))
+       (sequence ()
+                (set qbit (srl rn 31))
+                (set mbit (srl rm 31))
+                (set tbit (if BI (eq (srl rm 31) (srl rn 31)) 0 1))))
+
+(dshci div0u "Initialise divide-step state for unsigned division"
+       ()
+       "div0u"
+       (+ (f-op16 25))
+       (sequence ()
+                (set tbit 0)
+                (set qbit 0)
+                (set mbit 0)))
+
+(dshci div1 "Divide step"
+       ()
+       "div1 $rm, $rn"
+       (+ (f-op4 3) rn rm (f-sub4 4))
+       (sequence ((BI oldq) (SI tmp0) (UQI tmp1))
+                (set oldq qbit)
+                (set qbit (srl rn 31))
+                (set rn (or (sll rn 1) (zext SI tbit)))
+                (if (not oldq)
+                    (if (not mbit)
+                        (sequence ()
+                                  (set tmp0 rn)
+                                  (set rn (sub rn rm))
+                                  (set tmp1 (gtu rn tmp0))
+                                  (if (not qbit)
+                                      (set qbit (if BI tmp1 1 0))
+                                      (set qbit (if BI (eq tmp1 0) 1 0))))
+                        (sequence ()
+                                  (set tmp0 rn)
+                                  (set rn (add rn rm))
+                                  (set tmp1 (ltu rn tmp0))
+                                  (if (not qbit)
+                                      (set qbit (if BI (eq tmp1 0) 1 0))
+                                      (set qbit (if BI tmp1 1 0)))))
+                    (if (not mbit)
+                        (sequence ()
+                                  (set tmp0 rn)
+                                  (set rn (add rm rn))
+                                  (set tmp1 (ltu rn tmp0))
+                                  (if (not qbit)
+                                      (set qbit (if BI tmp1 1 0))
+                                      (set qbit (if BI (eq tmp1 0) 1 0))))
+                        (sequence ()
+                                  (set tmp0 rn)
+                                  (set rn (sub rn rm))
+                                  (set tmp1 (gtu rn tmp0))
+                                  (if (not qbit)
+                                      (set qbit (if BI (eq tmp1 0) 1 0))
+                                      (set qbit (if BI tmp1 1 0))))))
+                (set tbit (if BI (eq qbit mbit) 1 0))))
+
+(dshci dmulsl "Multiply long (signed)"
+       ()
+       "dmuls.l $rm, $rn"
+       (+ (f-op4 3) rn rm (f-sub4 13))
+       (sequence ((DI result))
+                (set result (mul (ext DI rm) (ext DI rn)))
+                (set mach (subword SI result 0))
+                (set macl (subword SI result 1))))
+
+(dshci dmulul "Multiply long (unsigned)"
+       ()
+       "dmulu.l $rm, $rn"
+       (+ (f-op4 3) rn rm (f-sub4 5))
+       (sequence ((DI result))
+                (set result (mul (zext DI rm) (zext DI rn)))
+                (set mach (subword SI result 0))
+                (set macl (subword SI result 1))))
+
+(dshci dt "Decrement and set"
+       ()
+       "dt $rn"
+       (+ (f-op4 4) rn (f-sub8 16))
+       (sequence ()
+                (set rn (sub rn 1))
+                (set tbit (eq rn 0))))
+
+(dshci extsb "Sign extend byte"
+       ()
+       "exts.b $rm, $rn"
+       (+ (f-op4 6) rn rm (f-sub4 14))
+       (set rn (ext SI (subword QI rm 3))))
+
+(dshci extsw "Sign extend word"
+       ()
+       "exts.w $rm, $rn"
+       (+ (f-op4 6) rn rm (f-sub4 15))
+       (set rn (ext SI (subword HI rm 1))))
+
+(dshci extub "Zero extend byte"
+       ()
+       "extu.b $rm, $rn"
+       (+ (f-op4 6) rn rm (f-sub4 12))
+       (set rn (zext SI (subword QI rm 3))))
+
+(dshci extuw "Zero etxend word"
+       ()
+       "extu.w $rm, $rn"
+       (+ (f-op4 6) rn rm (f-sub4 13))
+       (set rn (zext SI (subword HI rm 1))))
+
+(dshci fabs "Floating point absolute"
+       (FP-INSN)
+       "fabs $fsdn"
+       (+ (f-op4 15) fsdn (f-sub8 #x5d))
+       (if prbit
+          (set (dr fsdn) (c-call DF "sh64_fabsd" (dr fsdn)))
+          (set fsdn (c-call SF "sh64_fabss" fsdn))))
+
+(dshci fadd "Floating point add"
+       (FP-INSN)
+       "fadd $fsdm, $fsdn"
+       (+ (f-op4 15) fsdn fsdm (f-sub4 0))
+       (if prbit
+          (set (dr fsdn) (c-call DF "sh64_faddd" (dr fsdm) (dr fsdn)))
+          (set fsdn (c-call SF "sh64_fadds" fsdm fsdn))))
+
+(dshci fcmpeq "Floating point compare equal"
+       (FP-INSN)
+       "fcmp/eq $fsdm, $fsdn"
+       (+ (f-op4 15) fsdn fsdm (f-sub4 4))
+       (if prbit
+          (set tbit (c-call BI "sh64_fcmpeqd" (dr fsdm) (dr fsdn)))
+          (set tbit (c-call BI "sh64_fcmpeqs" fsdm fsdn))))
+       
+(dshci fcmpgt "Floating point compare greater than"
+       (FP-INSN)
+       "fcmp/gt $fsdm, $fsdn"
+       (+ (f-op4 15) fsdn fsdm (f-sub4 5))
+       (if prbit
+          (set tbit (c-call BI "sh64_fcmpgtd" (dr fsdn) (dr fsdm)))
+          (set tbit (c-call BI "sh64_fcmpgts" fsdn fsdm))))
+
+(dshci fcnvds "Floating point convert (double to single)"
+       (FP-INSN)
+       "fcnvds $drn, fpul"
+       (+ (f-op4 15) drn (f-8-1 10) (f-sub8 #xbd))
+       (set fpul (c-call SF "sh64_fcnvds" drn)))
+
+(dshci fcnvsd "Floating point convert (single to double)"
+       (FP-INSN)
+       "fcnvsd fpul, $drn"
+       (+ (f-op4 15) drn (f-8-1 0) (f-sub8 #xad))
+       (set drn (c-call DF "sh64_fcnvsd" fpul)))
+
+(dshci fdiv "Floating point divide"
+       (FP-INSN)
+       "fdiv $fsdm, $fsdn"
+       (+ (f-op4 15) fsdn fsdm (f-sub4 3))
+       (if prbit
+          (set (dr fsdn) (c-call DF "sh64_fdivd" (dr fsdn) (dr fsdm)))
+          (set fsdn (c-call SF "sh64_fdivs" fsdn fsdm))))
+
+(dshci fipr "Floating point inner product"
+       (FP-INSN)
+       "fipr $fvm, $fvn"
+       (+ (f-op4 15) fvn fvm (f-sub8 #xed))
+       (sequence ((QI m) (QI n) (SF res))
+                (set m (index-of fvm))
+                (set n (index-of fvn))
+                (set res (c-call SF "sh64_fmuls" fvm fvn))
+                (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-frc (add m 1)) (reg h-frc (add n 1)))))
+                (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-frc (add m 2)) (reg h-frc (add n 2)))))
+                (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-frc (add m 3)) (reg h-frc (add n 3)))))
+                (set (reg h-frc (add n 3)) res)))
+
+(dshci flds "Floating point load status register"
+       (FP-INSN)
+       "flds $frn"
+       (+ (f-op4 15) frn (f-sub8 #x1d))
+       (set fpul frn))
+
+(dshci fldi0 "Floating point load immediate 0.0"
+       (FP-INSN)
+       "fldi0 $frn"
+       (+ (f-op4 15) frn (f-sub8 #x8d))
+       (set frn (c-call SF "sh64_fldi0")))
+
+(dshci fldi1 "Floating point load immediate 1.0"
+       (FP-INSN)
+       "fldi1 $frn"
+       (+ (f-op4 15) frn (f-sub8 #x9d))
+       (set frn (c-call SF "sh64_fldi1")))
+
+(dshci float "Floating point integer conversion"
+       (FP-INSN)
+       "float fpul, $fsdn"
+       (+ (f-op4 15) fsdn (f-sub8 #x2d))
+       (if prbit
+          (set (dr fsdn) (c-call DF "sh64_floatld" fpul))
+          (set fsdn (c-call SF "sh64_floatls" fpul))))
+
+(dshci fmac "Floating point multiply and accumulate"
+       (FP-INSN)
+       "fmac fr0, $frm, $frn"
+       (+ (f-op4 15) frn frm (f-sub4 14))
+       (set frn (c-call SF "sh64_fmacs" (reg h-frc 0) frm frn)))
+
+(define-pmacro (even x) (eq (and x 1) 0))
+(define-pmacro (odd x)  (eq (and x 1) 1))
+(define-pmacro (extd x) (odd (index-of x)))
+
+(dshci fmov1 "Floating point move (register to register)"
+       (FP-INSN)
+       "fmov $frm, $frn"
+       (+ (f-op4 15) frn frm (f-sub4 12))
+       (if (not szbit)
+          ; single precision operation
+          (set frn frm)
+          ; double or extended operation
+          (if (extd frm)
+              (if (extd frn)
+                  (set (xd frn) (xd frm))
+                  (set (dr frn) (xd frm)))
+              (if (extd frn)
+                  (set (xd frn) (dr frm))
+                  (set (dr frn) (dr frm))))))
+
+(dshci fmov2 "Floating point load"
+       (FP-INSN)
+       "fmov @$rm, $frn"
+       (+ (f-op4 15) frn rm (f-sub4 8))
+       (if (not szbit)
+          ; single precision operation
+          (set frn (mem SF rm))
+          ; double or extended operation
+          (if (extd frn)
+              (set (xd frn) (mem DF rm))
+              (set (dr frn) (mem DF rm)))))
+
+(dshci fmov3 "Floating point load (post-increment)"
+       (FP-INSN)
+       "fmov @${rm}+, frn"
+       (+ (f-op4 15) frn rm (f-sub4 9))
+       (if (not szbit)
+          ; single precision operation
+          (sequence ()
+                    (set frn (mem SF rm))
+                    (set rm (add rm 4)))
+          ; double or extended operation
+          (sequence ()
+                    (if (extd frn)
+                        (set (xd frn) (mem DF rm))
+                        (set (dr frn) (mem DF rm)))
+                    (set rm (add rm 8)))))
+
+(dshci fmov4 "Floating point load (register/register indirect)"
+       (FP-INSN)
+       "fmov @(r0, $rm), $frn"
+       (+ (f-op4 15) frn rm (f-sub4 6))
+       (if (not szbit)
+          ; single precision operation
+          (set frn (mem SF (add r0 rm)))
+          ; double or extended operation
+          (if (extd frn)
+              (set (xd frn) (mem DF (add r0 rm)))
+              (set (dr frn) (mem DF (add r0 rm))))))
+
+(dshci fmov5 "Floating point store"
+       (FP-INSN)
+       "fmov $frm, @$rn"
+       (+ (f-op4 15) rn frm (f-sub4 10))
+       (if (not szbit)
+          ; single precision operation
+          (set (mem SF rn) frm)
+          ; double or extended operation
+          (if (extd frm)
+              (set (mem DF rn) (xd frm))
+              (set (mem DF rn) (dr frm)))))
+
+(dshci fmov6 "Floating point store (pre-decrement)"
+       (FP-INSN)
+       "fmov $frm, @-$rn"
+       (+ (f-op4 15) rn frm (f-sub4 11))
+       (if (not szbit)
+          ; single precision operation
+          (sequence ()
+                    (set rn (sub rn 4))
+                    (set (mem SF rn) frm))
+          ; double or extended operation
+          (sequence ()
+                    (set rn (sub rn 8))
+                    (if (extd frm)
+                        (set (mem DF rn) (xd frm))
+                        (set (mem DF rn) (dr frm))))))
+
+(dshci fmov7 "Floating point store (register/register indirect)"
+       (FP-INSN)
+       "fmov $frm, @(r0, $rn)"
+       (+ (f-op4 15) rn frm (f-sub4 7))
+       (if (not szbit)
+          ; single precision operation
+          (set (mem SF (add r0 rn)) frm)
+          ; double or extended operation
+          (if (extd frm)
+              (set (mem DF (add r0 rn)) (xd frm))
+              (set (mem DF (add r0 rn)) (dr frm)))))
+
+(dshci fmul "Floating point multiply"
+       (FP-INSN)
+       "fmul $fsdm, $fsdn"
+       (+ (f-op4 15) fsdn fsdm (f-sub4 2))
+       (if prbit
+          (set (dr fsdn) (c-call DF "sh64_fmuld" (dr fsdm) (dr fsdn)))
+          (set fsdn (c-call SF "sh64_fmuls" fsdm fsdn))))
+
+(dshci fneg "Floating point negate"
+       (FP-INSN)
+       "fneg $fsdn"
+       (+ (f-op4 15) fsdn (f-sub8 #x4d))
+       (if prbit
+          (set (dr fsdn) (c-call DF "sh64_fnegd" (dr fsdn)))
+          (set fsdn (c-call SF "sh64_fnegs" fsdn))))
+
+(dshci frchg "Toggle floating point register banks"
+       (FP-INSN)
+       "frchg"
+       (+ (f-op16 #xfbfd))
+       (set frbit (not frbit)))
+
+(dshci fschg "Set size of floating point transfers"
+       (FP-INSN)
+       "fschg"
+       (+ (f-op16 #xf3fd))
+       (set szbit (not szbit)))
+
+(dshci fsqrt "Floating point square root"
+       (FP-INSN)
+       "fsqrt $fsdn"
+       (+ (f-op4 15) fsdn (f-sub8 #x6d))
+       (if prbit
+          (set (dr fsdn) (c-call DF "sh64_fsqrtd" (dr fsdn)))
+          (set fsdn (c-call SF "sh64_fsqrts" fsdn))))
+
+(dshci fsts "Floating point store status register"
+       (FP-INSN)
+      "fsts fpul, $frn"
+       (+ (f-op4 15) frn (f-sub8 13))
+       (set frn fpul))
+
+(dshci fsub "Floating point subtract"
+       (FP-INSN)
+       "fsub $fsdm, $fsdn"
+       (+ (f-op4 15) fsdn fsdm (f-sub4 1))
+       (if prbit
+          (set (dr fsdn) (c-call DF "sh64_fsubd" (dr fsdn) (dr fsdm)))
+          (set fsdn (c-call SF "sh64_fsubs" fsdn fsdm))))
+
+(dshci ftrc "Floating point truncate"
+       (FP-INSN)
+       "ftrc $fsdn, fpul"
+       (+ (f-op4 15) fsdn (f-sub8 #x3d))
+       (set fpul (if SF prbit
+                    (c-call SF "sh64_ftrcdl" (dr fsdn))
+                    (c-call SF "sh64_ftrcsl" fsdn))))
+
+(dshci ftrv "Floating point transform vector"
+       (FP-INSN)
+       "ftrv xmtrx, $fvn"
+       (+ (f-op4 15) fvn (f-sub10 #x1fd))
+       (sequence ((QI n) (SF res))
+                (set n (index-of fvn))
+                (set res (c-call SF "sh64_fmuls" (reg h-xf 0) (reg h-frc n)))
+                (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 4)  (reg h-frc (add n 1)))))
+                (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 8)  (reg h-frc (add n 2)))))
+                (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 12) (reg h-frc (add n 3)))))
+                (set (reg h-frc n) res)
+                (set res (c-call SF "sh64_fmuls" (reg h-xf 1) (reg h-frc n)))
+                (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 5)  (reg h-frc (add n 1)))))
+                (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 9)  (reg h-frc (add n 2)))))
+                (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 13) (reg h-frc (add n 3)))))
+                (set (reg h-frc (add n 1)) res)
+                (set res (c-call SF "sh64_fmuls" (reg h-xf 2) (reg h-frc n)))
+                (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 6)  (reg h-frc (add n 1)))))
+                (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 10) (reg h-frc (add n 2)))))
+                (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 14) (reg h-frc (add n 3)))))
+                (set (reg h-frc (add n 2)) res)
+                (set res (c-call SF "sh64_fmuls" (reg h-xf 3) (reg h-frc n)))
+                (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 7)  (reg h-frc (add n 1)))))
+                (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 11) (reg h-frc (add n 2)))))
+                (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 15) (reg h-frc (add n 3)))))
+                (set (reg h-frc (add n 3)) res)))
+
+(dshci jmp "Jump"
+       ()
+       "jmp @$rn"
+       (+ (f-op4 4) rn (f-sub8 43))
+       (delay 1 (set pc rn)))
+
+(dshci jsr "Jump to subroutine"
+       ()
+       "jsr @$rn"
+       (+ (f-op4 4) rn (f-sub8 11))
+       (delay 1 (sequence ()
+                         (set pr (add pc 4))
+                         (set pc rn))))
+
+(dshci ldc "Load control register (GBR)"
+       ()
+       "ldc $rn, gbr"
+       (+ (f-op4 4) rn (f-sub8 30))
+       (set gbr rn))
+
+(dshci ldcl "Load control register (GBR)"
+       ()
+       "ldc.l @${rn}+, gbr"
+       (+ (f-op4 4) rn (f-sub8 39))
+       (sequence ()
+                (set gbr (mem SI rn))
+                (set rn (add rn 4))))
+
+(dshci lds-fpscr "Load status register (FPSCR)"
+       ()
+       "lds $rn, fpscr"
+       (+ (f-op4 4) rn (f-sub8 106))
+       (set fpscr rn))
+
+(dshci ldsl-fpscr "Load status register (FPSCR)"
+       ()
+       "lds.l @${rn}+, fpscr"
+       (+ (f-op4 4) rn (f-sub8 102))
+       (sequence ()
+                (set fpscr (mem SI rn))
+                (set rn (add rn 4))))
+
+(dshci lds-fpul "Load status register (FPUL)"
+       ()
+       "lds $rn, fpul"
+       (+ (f-op4 4) rn (f-sub8 90))
+       ; Use subword to convert rn's mode.
+       (set fpul (subword SF rn 0)))
+
+(dshci ldsl-fpul "Load status register (FPUL)"
+       ()
+       "lds.l @${rn}+, fpul"
+       (+ (f-op4 4) rn (f-sub8 86))
+       (sequence ()
+                (set fpul (mem SF rn))
+                (set rn (add rn 4))))
+
+(dshci lds-mach "Load status register (MACH)"
+       ()
+       "lds $rn, mach"
+       (+ (f-op4 4) rn (f-sub8 10))
+       (set mach rn))
+
+(dshci ldsl-mach "Load status register (MACH), post-increment"
+       ()
+       "lds.l @${rn}+, mach"
+       (+ (f-op4 4) rn (f-sub8 6))
+       (sequence ()
+                (set mach (mem SI rn))
+                (set rn (add rn 4))))
+
+(dshci lds-macl "Load status register (MACL)"
+       ()
+       "lds $rn, macl"
+       (+ (f-op4 4) rn (f-sub8 26))
+       (set macl rn))
+
+(dshci ldsl-macl "Load status register (MACL), post-increment"
+       ()
+       "lds.l @${rn}+, macl"
+       (+ (f-op4 4) rn (f-sub8 22))
+       (sequence ()
+                (set macl (mem SI rn))
+                (set rn (add rn 4))))
+
+(dshci lds-pr "Load status register (PR)"
+       ()
+       "lds $rn, pr"
+       (+ (f-op4 4) rn (f-sub8 42))
+       (set pr rn))
+
+(dshci ldsl-pr "Load status register (PR), post-increment"
+       ()
+       "lds.l @${rn}+, pr"
+       (+ (f-op4 4) rn (f-sub8 38))
+       (sequence ()
+                (set pr (mem SI rn))
+                (set rn (add rn 4))))
+
+(dshci macl "Multiply and accumulate (long)"
+       ()
+       "mac.l @${rm}+, @${rn}+"
+       (+ (f-op4 0) rn rm (f-sub4 15))
+       (sequence ((DI tmpry) (DI mac) (DI result) (SI x) (SI y))
+                (set x (mem SI rn))
+                (set rn (add rn 4))
+                (if (eq (index-of rn) (index-of rm))
+                    (sequence ()
+                              (set rn (add rn 4))
+                              (set rm (add rm 4))))
+                (set y (mem SI rm))
+                (set rm (add rm 4))
+                (set tmpry (mul (zext DI x) (zext DI y)))
+                (set mac (or DI (sll (zext DI mach) 32) (zext DI macl)))
+                (set result (add mac tmpry))
+                (sequence ()
+                          (if sbit
+                              (sequence ((SI min) (SI max))
+                                        (set max (srl (inv DI 0) 16))
+                                       ; Preserve bit 48 for sign.
+                                        (set min (srl (inv DI 0) 15))
+                                        (if (gt result max)
+                                            (set result max)
+                                            (if (lt result min)
+                                                (set result min)))))
+                          (set mach (subword SI result 0))
+                          (set macl (subword SI result 1)))))
+
+(dshci macw "Multiply and accumulate (word)"
+       ()
+       "mac.w @${rm}+, @${rn}+"
+       (+ (f-op4 4) rn rm (f-sub4 15))
+       (sequence ((SI tmpry) (DI mac) (DI result) (HI x) (HI y))
+                (set x (mem HI rn))
+                (set rn (add rn 2))
+                (if (eq (index-of rn) (index-of rm))
+                    (sequence ()
+                              (set rn (add rn 2))
+                              (set rm (add rm 2))))
+                (set y (mem HI rm))
+                (set rm (add rm 2))
+                (set tmpry (mul (zext SI x) (zext SI y)))
+                (if sbit
+                    (sequence ()
+                              (if (add-oflag tmpry macl 0)
+                                  (set mach 1))
+                              (set macl (add tmpry macl)))
+                    (sequence ()
+                              (set mac (or DI (sll (zext DI mach) 32) (zext DI macl)))
+                              (set result (add mac (ext DI tmpry)))
+                              (set mach (subword SI result 0))
+                              (set macl (subword SI result 1))))))
+
+(dshci mov "Move"
+       ()
+       "mov $rm64, $rn64"
+       (+ (f-op4 6) rn64 rm64 (f-sub4 3))
+       (set rn64 rm64))
+
+(dshci movi "Move immediate"
+       ()
+       "mov #$imm8, $rn"
+       (+ (f-op4 14) rn imm8)
+       (set rn (ext DI (and QI imm8 255))))
+
+(dshci movb1 "Store byte to memory (register indirect w/ zero displacement)"
+       ()
+       "mov.b $rm, @$rn"
+       (+ (f-op4 2) rn rm (f-sub4 0))
+       (set (mem UQI rn) (subword UQI rm 3)))
+
+(dshci movb2 "Store byte to memory (register indirect w/ pre-decrement)"
+       ()
+       "mov.b $rm, @-$rn"
+       (+ (f-op4 2) rn rm (f-sub4 4))
+       (sequence ((DI addr))
+                (set addr (sub rn 1))
+                (set (mem UQI addr) (subword UQI rm 3))
+                (set rn addr)))
+
+(dshci movb3 "Store byte to memory (register/register indirect)"
+       ()
+       "mov.b $rm, @(r0,$rn)"
+       (+ (f-op4 0) rn rm (f-sub4 4))
+       (set (mem UQI (add r0 rn)) (subword UQI rm 3)))
+
+(dshci movb4 "Store byte to memory (GBR-relative w/ displacement)"
+       ()
+       "mov.b r0, @($imm8, gbr)"
+       (+ (f-op8 #xc0) imm8)
+       (sequence ((DI addr))
+                (set addr (add gbr imm8))
+                (set (mem UQI addr) (subword UQI r0 3))))
+
+(dshci movb5 "Store byte to memory (register indirect w/ displacement)"
+       ()
+       "mov.b r0, @($imm4, $rm)"
+       (+ (f-op8 #x80) rm imm4)
+       (sequence ((DI addr))
+                (set addr (add rm imm4))
+                (set (mem UQI addr) (subword UQI r0 3))))
+
+(dshci movb6 "Load byte from memory (register indirect w/ zero displacement)"
+       ()
+       "mov.b @$rm, $rn"
+       (+ (f-op4 6) rn rm (f-sub4 0))
+       (set rn (ext SI (mem QI rm))))
+
+(dshci movb7 "Load byte from memory (register indirect w/ post-increment)"
+       ()
+       "mov.b @${rm}+, $rn"
+       (+ (f-op4 6) rn rm (f-sub4 4))
+       (sequence ((QI data))
+                (set data (mem QI rm))
+                (if (eq (index-of rm) (index-of rn))
+                    (set rm (ext SI data))
+                    (set rm (add rm 1)))
+                (set rn (ext SI data))))
+
+(dshci movb8 "Load byte from memory (register/register indirect)"
+       ()
+       "mov.b @(r0, $rm), $rn"
+       (+ (f-op4 0) rn rm (f-sub4 12))
+       (set rn (ext SI (mem QI (add r0 rm)))))
+
+(dshci movb9 "Load byte from memory (GBR-relative with displacement)"
+       ()
+       "mov.b @($imm8, gbr), r0"
+       (+ (f-op8 #xc4) imm8)
+       (set r0 (ext SI (mem QI (add gbr imm8)))))
+
+(dshci movb10 "Load byte from memory (register indirect w/ displacement)"
+       ()
+       "mov.b @($imm4, $rm), r0"
+       (+ (f-op8 #x84) rm imm4)
+       (set r0 (ext SI (mem QI (add rm imm4)))))
+
+(dshci movl1 "Store long word to memory (register indirect w/ zero displacement)"
+       ()
+       "mov.l $rm, @$rn"
+       (+ (f-op4 2) rn rm (f-sub4 2))
+       (set (mem SI rn) rm))
+
+(dshci movl2 "Store long word to memory (register indirect w/ pre-decrement)"
+       ()
+       "mov.l $rm, @-$rn"
+       (+ (f-op4 2) rn rm (f-sub4 6))
+       (sequence ((SI addr))
+                (set addr (sub rn 4))
+                (set (mem SI addr) rm)
+                (set rn addr)))
+
+(dshci movl3 "Store long word to memory (register/register indirect)"
+       ()
+       "mov.l $rm, @(r0, $rn)"
+       (+ (f-op4 0) rn rm (f-sub4 6))
+       (set (mem SI (add r0 rn)) rm))
+
+(dshci movl4 "Store long word to memory (GBR-relative w/ displacement)"
+       ()
+       "mov.l r0, @($imm8x4, gbr)"
+       (+ (f-op8 #xc2) imm8x4)
+       (set (mem SI (add gbr imm8x4)) r0))
+
+(dshci movl5 "Store long word to memory (register indirect w/ displacement)"
+       ()
+       "mov.l $rm, @($imm4x4, $rn)"
+       (+ (f-op4 1) rn rm imm4x4)
+       (set (mem SI (add rn imm4x4)) rm))
+
+(dshci movl6 "Load long word to memory (register indirect w/ zero displacement)"
+       ()
+       "mov.l @$rm, $rn"
+       (+ (f-op4 6) rn rm (f-sub4 2))
+       (set rn (mem SI rm)))
+
+(dshci movl7 "Load long word from memory (register indirect w/ post-increment)"
+       ()
+       "mov.l @${rm}+, $rn"
+       (+ (f-op4 6) rn rm (f-sub4 6))
+       (sequence ()
+                (set rn (mem SI rm))
+                (if (eq (index-of rm) (index-of rn))
+                    (set rm rn)
+                    (set rm (add rm 4)))))
+
+(dshci movl8 "Load long word from memory (register/register indirect)"
+       ()
+       "mov.l @(r0, $rm), $rn"
+       (+ (f-op4 0) rn rm (f-sub4 14))
+       (set rn (mem SI (add r0 rm))))
+
+(dshci movl9 "Load long word from memory (GBR-relative w/ displacement)"
+       ()
+       "mov.l @($imm8x4, gbr), r0"
+       (+ (f-op8 #xc6) imm8x4)
+       (set r0 (mem SI (add gbr imm8x4))))
+
+(dshci movl10 "Load long word from memory (PC-relative w/ displacement)"
+       (ILLSLOT)
+       "mov.l @($imm8x4, pc), $rn"
+       (+ (f-op4 13) rn imm8x4)
+       (set rn (mem SI (add imm8x4 (and (add pc 4) (inv 3))))))
+
+(dshci movl11 "Load long word from memory (register indirect w/ displacement)"
+       ()
+       "mov.l @($imm4x4, $rm), $rn"
+       (+ (f-op4 5) rn rm imm4x4)
+       (set rn (mem SI (add rm imm4x4))))
+
+(dshci movw1 "Store word to memory (register indirect w/ zero displacement)"
+       ()
+       "mov.w $rm, @$rn"
+       (+ (f-op4 2) rn rm (f-sub4 1))
+       (set (mem HI rn) (subword HI rm 1)))
+
+(dshci movw2 "Store word to memory (register indirect w/ pre-decrement)"
+       ()
+       "mov.w $rm, @-$rn"
+       (+ (f-op4 2) rn rm (f-sub4 5))
+       (sequence ((DI addr))
+                (set addr (sub rn 2))
+                (set (mem HI addr) (subword HI rm 1))
+                (set rn addr)))
+
+(dshci movw3 "Store word to memory (register/register indirect)"
+       ()
+       "mov.w $rm, @(r0, $rn)"
+       (+ (f-op4 0) rn rm (f-sub4 5))
+       (set (mem HI (add r0 rn)) (subword HI rm 1)))
+
+(dshci movw4 "Store word to memory (GBR-relative w/ displacement)"
+       ()
+       "mov.w r0, @($imm8x2, gbr)"
+       (+ (f-op8 #xc1) imm8x2)
+       (set (mem HI (add gbr imm8x2)) (subword HI r0 1)))
+
+(dshci movw5 "Store word to memory (register indirect w/ displacement)"
+       ()
+       "mov.w r0, @($imm4x2, $rn)"
+       (+ (f-op8 #x81) rn imm4x2)
+       (set (mem HI (add rn imm4x2)) (subword HI r0 1)))
+
+(dshci movw6 "Load word from memory (register indirect w/ zero displacement)"
+       ()
+       "mov.w @$rm, $rn"
+       (+ (f-op4 6) rn rm (f-sub4 1))
+       (set rn (ext SI (mem HI rm))))
+
+(dshci movw7 "Load word from memory (register indirect w/ post-increment)"
+       ()
+       "mov.w @${rm}+, $rn"
+       (+ (f-op4 6) rn rm (f-sub4 5))
+       (sequence ((HI data))
+                (set data (mem HI rm))
+                (if (eq (index-of rm) (index-of rn))
+                    (set rm (ext SI data))
+                    (set rm (add rm 2)))
+                (set rn (ext SI data))))
+
+(dshci movw8 "Load word from memory (register/register indirect)"
+       ()
+       "mov.w @(r0, $rm), $rn"
+       (+ (f-op4 0) rn rm (f-sub4 13))
+       (set rn (ext SI (mem HI (add r0 rm)))))
+
+(dshci movw9 "Load word from memory (GBR-relative w/ displacement)"
+       ()
+       "mov.w @($imm8x2, gbr), r0"
+       (+ (f-op8 #xc5) imm8x2)
+       (set r0 (ext SI (mem HI (add gbr imm8x2)))))
+
+(dshci movw10 "Load word from memory (PC-relative w/ displacement)"
+       (ILLSLOT)
+       "mov.w @($imm8x2, pc), $rn"
+       (+ (f-op4 9) rn imm8x2)
+       (set rn (ext SI (mem HI (add (add pc 4) imm8x2)))))
+
+(dshci movw11 "Load word from memory (register indirect w/ displacement)"
+       ()
+       "mov.w @($imm4x2, $rm), r0"
+       (+ (f-op8 #x85) rm imm4x2)
+       (set r0 (ext SI (mem HI (add rm imm4x2)))))
+
+(dshci mova "Move effective address"
+       (ILLSLOT)
+       "mova @($imm8x4, pc), r0"
+       (+ (f-op8 #xc7) imm8x4)
+       (set r0 (add (and (add pc 4) (inv 3)) imm8x4)))
+
+(dshci movcal "Move with cache block allocation"
+       ()
+       "movca.l r0, @$rn"
+       (+ (f-op4 0) rn (f-sub8 #xc3))
+       (set (mem SI rn) r0))
+       
+(dshci movt "Move t-bit"
+       ()
+       "movt $rn"
+       (+ (f-op4 0) rn (f-sub8 41))
+       (set rn (zext SI tbit)))
+
+(dshci mull "Multiply"
+       ()
+       "mul.l $rm, $rn"
+       (+ (f-op4 0) rn rm (f-sub4 7))
+       (set macl (mul rm rn)))
+
+(dshci mulsw "Multiply words (signed)"
+       ()
+       "muls.w $rm, $rn"
+       (+ (f-op4 2) rn rm (f-sub4 15))
+       (set macl (mul (ext SI (subword HI rm 1)) (ext SI (subword HI rn 1)))))
+
+(dshci muluw "Multiply words (unsigned)"
+       ()
+       "mulu.w $rm, $rn"
+       (+ (f-op4 2) rn rm (f-sub4 14))
+       (set macl (mul (zext SI (subword HI rm 1)) (zext SI (subword HI rn 1)))))
+
+(dshci neg "Negate"
+       ()
+       "neg $rm, $rn"
+       (+ (f-op4 6) rn rm (f-sub4 11))
+       (set rn (neg rm)))
+
+(dshci negc "Negate with carry"
+       ()
+       "negc $rm, $rn"
+       (+ (f-op4 6) rn rm (f-sub4 10))
+       (sequence ((BI flag))
+                (set flag (sub-cflag 0 rm tbit))
+                (set rn (subc 0 rm tbit))
+                (set tbit flag)))
+
+(dshci nop "No operation"
+       ()
+       "nop"
+       (+ (f-op16 9))
+       (nop))
+
+(dshci not "Bitwise NOT"
+       ()
+       "not $rm64, $rn64"
+       (+ (f-op4 6) rn64 rm64 (f-sub4 7))
+       (set rn64 (inv rm64)))
+
+(dshci ocbi "Invalidate operand cache block"
+       ()
+       "ocbi @$rn"
+       (+ (f-op4 0) rn (f-sub8 147))
+       (unimp "ocbi"))
+
+(dshci ocbp "Purge operand cache block"
+       ()
+       "ocbp @$rn"
+       (+ (f-op4 0) rn (f-sub8 163))
+       (unimp "ocbp"))
+
+(dshci ocbwb "Write back operand cache block"
+       ()
+       "ocbwb @$rn"
+       (+ (f-op4 0) rn (f-sub8 179))
+       (unimp "ocbwb"))
+
+(dshci or "Bitwise OR"
+       ()
+       "or $rm64, $rn64"
+       (+ (f-op4 2) rn64 rm64 (f-sub4 11))
+       (set rn64 (or rm64 rn64)))
+
+(dshci ori "Bitwise OR immediate"
+       ()
+       "or #$uimm8, r0"
+       (+ (f-op8 #xcb) uimm8)
+       (set r0 (or r0 (zext DI uimm8))))
+
+(dshci orb "Bitwise OR immediate"
+       ()
+       "or.b #$imm8, @(r0, gbr)"
+       (+ (f-op8 #xcf) imm8)
+       (sequence ((DI addr) (UQI data))
+                (set addr (add r0 gbr))
+                (set data (or (mem UQI addr) imm8))
+                (set (mem UQI addr) data)))
+
+(dshci pref "Prefetch data"
+       ()
+       "pref @$rn"
+       (+ (f-op4 0) rn (f-sub8 131))
+       (unimp "pref"))
+
+(dshci rotcl "Rotate with carry left"
+       ()
+       "rotcl $rn"
+       (+ (f-op4 4) rn (f-sub8 36))
+       (sequence ((BI temp))
+                (set temp (srl rn 31))
+                (set rn (or (sll rn 1) tbit))
+                (set tbit (if BI temp 1 0))))
+
+(dshci rotcr "Rotate with carry right"
+       ()
+       "rotcr $rn"
+       (+ (f-op4 4) rn (f-sub8 37))
+       (sequence ((BI lsbit) (SI temp))
+                (set lsbit (if BI (eq (and rn 1) 0) 0 1))
+                (set temp tbit)
+                (set rn (or (srl rn 1) (sll temp 31)))
+                (set tbit (if BI lsbit 1 0))))
+
+(dshci rotl "Rotate left"
+       ()
+       "rotl $rn"
+       (+ (f-op4 4) rn (f-sub8 4))
+       (sequence ((BI temp))
+                (set temp (srl rn 31))
+                (set rn (or (sll rn 1) temp))
+                (set tbit (if BI temp 1 0))))
+
+(dshci rotr "Rotate right"
+       ()
+       "rotr $rn"
+       (+ (f-op4 4) rn (f-sub8 5))
+       (sequence ((BI lsbit) (SI temp))
+                (set lsbit (if BI (eq (and rn 1) 0) 0 1))
+                (set temp lsbit)
+                (set rn (or (srl rn 1) (sll temp 31)))
+                (set tbit (if BI lsbit 1 0))))
+
+(dshci rts "Return from subroutine"
+       ()
+       "rts"
+       (+ (f-op16 11))
+       (delay 1 (set pc pr)))
+
+(dshci sets "Set S-bit"
+       ()
+       "sets"
+       (+ (f-op16 88))
+       (set sbit 1))
+
+(dshci sett "Set T-bit"
+       ()
+       "sett"
+       (+ (f-op16 24))
+       (set tbit 1))
+
+(dshci shad "Shift arithmetic dynamic"
+       ()
+       "shad $rm, $rn"
+       (+ (f-op4 4) rn rm (f-sub4 12))
+       (sequence ((QI shamt))
+                (set shamt (and QI rm 31))
+                (if (ge rm 0)
+                    (set rn (sll rn shamt))
+                    (if (ne shamt 0)
+                        (set rn (sra rn (sub 32 shamt)))
+                        (if (lt rn 0)
+                            (set rn (neg 1))
+                            (set rn 0))))))
+
+(dshci shal "Shift left arithmetic one bit"
+       ()
+       "shal $rn"
+       (+ (f-op4 4) rn (f-sub8 32))
+       (sequence ((BI t))
+                (set t (srl rn 31))
+                (set rn (sll rn 1))
+                (set tbit (if BI t 1 0))))
+
+(dshci shar "Shift right arithmetic one bit"
+       ()
+       "shar $rn"
+       (+ (f-op4 4) rn (f-sub8 33))
+       (sequence ((BI t))
+                (set t (and rn 1))
+                (set rn (sra rn 1))
+                (set tbit (if BI t 1 0))))
+
+(dshci shld "Shift logical dynamic"
+       ()
+       "shld $rm, $rn"
+       (+ (f-op4 4) rn rm (f-sub4 13))
+       (sequence ((QI shamt))
+                (set shamt (and QI rm 31))
+                (if (ge rm 0)
+                    (set rn (sll rn shamt))
+                    (if (ne shamt 0)
+                        (set rn (srl rn (sub 32 shamt)))
+                        (set rn 0)))))
+
+(dshci shll "Shift left logical one bit"
+       ()
+       "shll $rn"
+       (+ (f-op4 4) rn (f-sub8 0))
+       (sequence ((BI t))
+                (set t (srl rn 31))
+                (set rn (sll rn 1))
+                (set tbit (if BI t 1 0))))
+
+(dshci shll2 "Shift left logical two bits"
+       ()
+       "shll2 $rn"
+       (+ (f-op4 4) rn (f-sub8 8))
+       (set rn (sll rn 2)))
+
+(dshci shll8 "Shift left logical eight bits"
+       ()
+       "shll8 $rn"
+       (+ (f-op4 4) rn (f-sub8 24))
+       (set rn (sll rn 8)))
+
+(dshci shll16 "Shift left logical sixteen bits"
+       ()
+       "shll16 $rn"
+       (+ (f-op4 4) rn (f-sub8 40))
+       (set rn (sll rn 16)))
+
+(dshci shlr "Shift right logical one bit"
+       ()
+       "shlr $rn"
+       (+ (f-op4 4) rn (f-sub8 1))
+       (sequence ((BI t))
+                (set t (and rn 1))
+                (set rn (srl rn 1))
+                (set tbit (if BI t 1 0))))
+
+(dshci shlr2 "Shift right logical two bits"
+       ()
+       "shlr2 $rn"
+       (+ (f-op4 4) rn (f-sub8 9))
+       (set rn (srl rn 2)))
+
+(dshci shlr8 "Shift right logical eight bits"
+       ()
+       "shlr8 $rn"
+       (+ (f-op4 4) rn (f-sub8 25))
+       (set rn (srl rn 8)))
+
+(dshci shlr16 "Shift right logical sixteen bits"
+       ()
+       "shlr16 $rn"
+       (+ (f-op4 4) rn (f-sub8 41))
+       (set rn (srl rn 16)))
+
+(dshci stc-gbr "Store control register (GBR)"
+       ()
+       "stc gbr, $rn"
+       (+ (f-op4 0) rn (f-sub8 18))
+       (set rn gbr))
+
+(dshci stcl-gbr "Store control register (GBR)"
+       ()
+       "stc.l gbr, @-$rn"
+       (+ (f-op4 4) rn (f-sub8 19))
+       (sequence ((DI addr))
+                (set addr (sub rn 4))
+                (set (mem SI addr) gbr)
+                (set rn addr)))
+
+(dshci sts-fpscr "Store status register (FPSCR)"
+       ()
+       "sts fpscr, $rn"
+       (+ (f-op4 0) rn (f-sub8 106))
+       (set rn fpscr))
+
+(dshci stsl-fpscr "Store status register (FPSCR)"
+       ()
+       "sts.l fpscr, @-$rn"
+       (+ (f-op4 4) rn (f-sub8 98))
+       (sequence ((DI addr))
+                (set addr (sub rn 4))
+                (set (mem SI addr) fpscr)
+                (set rn addr)))
+
+(dshci sts-fpul "Store status register (FPUL)"
+       ()
+       "sts fpul, $rn"
+       (+ (f-op4 0) rn (f-sub8 90))
+       (set rn (subword SI fpul 0)))
+
+(dshci stsl-fpul "Store status register (FPUL)"
+       ()
+       "sts.l fpul, @-$rn"
+       (+ (f-op4 4) rn (f-sub8 82))
+       (sequence ((DI addr))
+                (set addr (sub rn 4))
+                (set (mem SF addr) fpul)
+                (set rn addr)))
+
+(dshci sts-mach "Store status register (MACH)"
+       ()
+       "sts mach, $rn"
+       (+ (f-op4 0) rn (f-sub8 10))
+       (set rn mach))
+
+(dshci stsl-mach "Store status register (MACH)"
+       ()
+       "sts.l mach, @-$rn"
+       (+ (f-op4 4) rn (f-sub8 2))
+       (sequence ((DI addr))
+                (set addr (sub rn 4))
+                (set (mem SI addr) mach)
+                (set rn addr)))
+
+(dshci sts-macl "Store status register (MACL)"
+       ()
+       "sts macl, $rn"
+       (+ (f-op4 0) rn (f-sub8 26))
+       (set rn macl))
+
+(dshci stsl-macl "Store status register (MACL)"
+       ()
+       "sts.l macl, @-$rn"
+       (+ (f-op4 4) rn (f-sub8 18))
+       (sequence ((DI addr))
+                (set addr (sub rn 4))
+                (set (mem SI addr) macl)
+                (set rn addr)))
+
+(dshci sts-pr "Store status register (PR)"
+       ()
+       "sts pr, $rn"
+       (+ (f-op4 0) rn (f-sub8 42))
+       (set rn pr))
+
+(dshci stsl-pr "Store status register (PR)"
+       ()
+       "sts.l pr, @-$rn"
+       (+ (f-op4 4) rn (f-sub8 34))
+       (sequence ((DI addr))
+                (set addr (sub rn 4))
+                (set (mem SI addr) pr)
+                (set rn addr)))
+
+(dshci sub "Subtract"
+       ()
+       "sub $rm, $rn"
+       (+ (f-op4 3) rn rm (f-sub4 8))
+       (set rn (sub rn rm)))
+
+(dshci subc "Subtract and detect carry"
+       ()
+       "subc $rm, $rn"
+       (+ (f-op4 3) rn rm (f-sub4 10))
+       (sequence ((BI flag))
+                (set flag (sub-cflag rn rm tbit))
+                (set rn (subc rn rm tbit))
+                (set tbit flag)))
+
+(dshci subv "Subtract and detect overflow"
+       ()
+       "subv $rm, $rn"
+       (+ (f-op4 3) rn rm (f-sub4 11))
+       (sequence ((BI t))
+                (set t (sub-oflag rn rm 0))
+                (set rn (sub rn rm))
+                (set tbit (if BI t 1 0))))
+
+(dshci swapb "Swap bytes"
+       ()
+       "swap.b $rm, $rn"
+       (+ (f-op4 6) rn rm (f-sub4 8))
+       (sequence ((UHI top-half) (UQI byte1) (UQI byte0))
+                (set top-half (subword HI rm 0))
+                (set byte1 (subword QI rm 2))
+                (set byte0 (subword QI rm 3))
+                (set rn (or SI (sll SI top-half 16) (or SI (sll SI byte0 8) byte1)))))
+
+(dshci swapw "Swap words"
+       ()
+       "swap.w $rm, $rn"
+       (+ (f-op4 6) rn rm (f-sub4 9))
+       (set rn (or (srl rm 16) (sll rm 16))))
+
+(dshci tasb "Test and set byte"
+       ()
+       "tas.b @$rn"
+       (+ (f-op4 4) rn (f-sub8 27))
+       (sequence ((UQI byte))
+                (set byte (mem UQI rn))
+                (set tbit (if BI (eq byte 0) 1 0))
+                (set byte (or byte 128))
+                (set (mem UQI rn) byte)))
+
+(dshci trapa "Trap"
+       (ILLSLOT)
+       "trapa #$uimm8"
+       (+ (f-op8 #xc3) uimm8)
+       (c-call "sh64_compact_trapa" uimm8 pc))
+
+(dshci tst "Test and set t-bit"
+       ()
+       "tst $rm, $rn"
+       (+ (f-op4 2) rn rm (f-sub4 8))
+       (set tbit (if BI (eq (and rm rn) 0) 1 0)))
+
+(dshci tsti "Test and set t-bit immediate" 
+       ()
+       "tst #$uimm8, r0"
+       (+ (f-op8 #xc8) uimm8)
+       (set tbit (if BI (eq (and r0 (zext SI uimm8)) 0) 1 0)))
+
+(dshci tstb "Test and set t-bit immedate with memory byte"
+       ()
+       "tst.b #$imm8, @(r0, gbr)"
+       (+ (f-op8 #xcc) imm8)
+       (sequence ((DI addr))
+                (set addr (add r0 gbr))
+                (set tbit (if BI (eq (and (mem UQI addr) imm8) 0) 1 0))))
+
+(dshci xor "Exclusive OR"
+       ()
+       "xor $rm64, $rn64"
+       (+ (f-op4 2) rn64 rm64 (f-sub4 10))
+       (set rn64 (xor rn64 rm64)))
+
+(dshci xori "Exclusive OR immediate"
+       ()
+       "xor #$uimm8, r0"
+       (+ (f-op8 #xca) uimm8)
+       (set (reg h-gr 0) (xor (reg h-gr 0) (zext DI uimm8))))
+
+(dshci xorb "Exclusive OR immediate with memory byte"
+       ()
+       "xor.b #$imm8, @(r0, gbr)"
+       (+ (f-op8 #xce) imm8)
+       (sequence ((DI addr) (UQI data))
+                (set addr (add r0 gbr))
+                (set data (xor (mem UQI addr) imm8))
+                (set (mem UQI addr) data)))
+
+(dshci xtrct "Extract"
+       ()
+       "xtrct $rm, $rn"
+       (+ (f-op4 2) rn rm (f-sub4 13))
+       (set rn (or (sll rm 16) (srl rn 16))))

diff --git a/cpu/sh64-media.cpu b/cpu/sh64-media.cpu
new file mode 100644 (file)
index 0000000..80dd74a
--- /dev/null
+++ b/cpu/sh64-media.cpu
@@ -0,0 +1,1733 @@
+; Hitachi SHmedia instruction set description.  -*- Scheme -*-
+;
+; Copyright 2000, 2001, 2007, 2009 Free Software Foundation, Inc.
+;
+; Contributed by Red Hat Inc; developed under contract from Hitachi
+; Semiconductor (America) Inc.
+;
+; This file is part of the GNU Binutils.
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 3 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, write to the Free Software
+; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+; MA 02110-1301, USA.
+
+\f
+; dshmf -- define-normal-sh-media-field
+
+(define-pmacro (dshmf xname xcomment ignored xstart xlength)
+  (dnf xname xcomment ((ISA media)) xstart xlength))
+
+; dshmop -- define-normal-sh-media-operand
+
+(define-pmacro (dshmop xname xcomment ignored xhardware xfield)
+  (dnop xname xcomment ((ISA media)) xhardware xfield))
+
+; dnshmi -- define-normal-sh-media-insn
+
+(define-pmacro (dshmi xname xcomment xattrs xsyntax xformat xsemantics)
+  (define-insn
+    (name xname)
+    (comment xcomment)
+    (.splice attrs (.unsplice xattrs) (ISA media))
+    (syntax xsyntax)
+    (format xformat)
+    (semantics xsemantics)))
+
+; Saturation functions.
+; Force a value `i' into words `n' bits wide.
+; See Hitachi SH-5 CPU core, volume 2, p. 25 for details.
+
+; saturate -- signed saturatation function
+
+(define-pmacro (saturate mode n i)
+  (if mode (lt i (neg mode (sll mode 1 (sub n 1))))
+      (neg (sll mode 1 (sub n 1)))
+      (if mode (lt i (sll mode 1 (sub n 1)))
+         i
+         (sub mode (sll mode 1 (sub n 1)) 1))))
+
+; usaturate -- unsigned saturation function
+
+(define-pmacro (usaturate mode n i)
+  (if mode (lt i (const mode 0))
+      (const mode 0)
+      (if mode (lt i (sll mode 1 n))
+         i
+         (sub mode (sll mode 1 n) 1))))
+
+\f
+; Ifields.
+
+(dshmf f-op          "Opcode"                       ()  31  6)
+(dshmf f-ext         "Extension opcode"             ()  19  4)
+(dshmf f-rsvd        "Reserved"                    (RESERVED)   3  4)
+
+(dshmf f-left        "Left register"                ()  25  6)
+(dshmf f-right       "Right register"               ()  15  6)
+(dshmf f-dest        "Destination register"         ()   9  6)
+
+(define-multi-ifield
+  (name f-left-right)
+  (comment "Left and right matched register pair")
+  (attrs (ISA media))
+  (mode UINT)
+  (subfields f-left f-right)
+  (insert (sequence ()
+                   (set (ifield f-left)
+                        (and (ifield f-left-right) 63))
+                   (set (ifield f-right)
+                        (and (ifield f-left-right) 63))))
+  (extract (set (ifield f-left-right) (ifield f-left)))
+)
+
+(dshmf f-tra         "Target register"              ()   6  3)
+(dshmf f-trb         "Target register"              ()  22  3)
+(dshmf f-likely      "Likely bit"                   ()   9  1)
+(dshmf f-25          "Three unused bits at bit 25"  ()  25  3)
+(dshmf f-8-2         "Two unused bits at bit 8"     ()   8  2)
+
+(df f-imm6   "Immediate value (6 bits)"      ((ISA media)) 15 6 INT #f #f)
+(df f-imm10  "Immediate value (10 bits)"     ((ISA media)) 19 10 INT #f #f)
+(df f-imm16  "Immediate value (16 bits)"     ((ISA media)) 25 16 INT #f #f)
+
+(dshmf f-uimm6       "Immediate value (6 bits)"     ()  15  6)
+(dshmf f-uimm16      "Immediate value (16 bits)"    ()  25 16)
+
+; Various displacement fields.
+; The 10 bit field, for example, has different scaling for displacements.
+
+(df f-disp6         "Displacement (6 bits)"        ((ISA media)) 15 6 INT #f #f)
+
+(df f-disp6x32       "Displacement (6 bits)"        ((ISA media)) 15 6 INT
+    ((value pc) (sra SI value 5))
+    ((value pc) (sll SI value 5)))
+
+(df f-disp10         "Displacement (10 bits)"       ((ISA media)) 19 10 INT #f #f)
+
+(df f-disp10x8       "Displacement (10 bits)"       ((ISA media)) 19 10 INT
+    ((value pc) (sra SI value 3))
+    ((value pc) (sll SI value 3)))
+
+(df f-disp10x4       "Displacement (10 bits)"       ((ISA media)) 19 10 INT
+    ((value pc) (sra SI value 2))
+    ((value pc) (sll SI value 2)))
+
+(df f-disp10x2       "Displacement (10 bits)"       ((ISA media)) 19 10 INT
+    ((value pc) (sra SI value 1))
+    ((value pc) (sll SI value 1)))
+
+(df f-disp16         "Displacement (16 bits)"       ((ISA media) PCREL-ADDR) 25 16 INT
+    ((value pc) (sra DI value 2))
+    ((value pc) (add DI (sll DI value 2) pc)))
+
+\f
+; Operands.
+
+(dshmop rm        "Left general purpose reg"            ()  h-gr    f-left)
+(dshmop rn        "Right general purpose reg"           ()  h-gr    f-right)
+(dshmop rd        "Destination general purpose reg"     ()  h-gr    f-dest)
+
+(dshmop frg       "Left single precision register"      ()  h-fr    f-left)
+(dshmop frh       "Right single precision register"     ()  h-fr    f-right)
+(dshmop frf       "Destination single precision reg"    ()  h-fr    f-dest)
+(dshmop frgh      "Single precision register pair"      ()  h-fr    f-left-right)
+
+(dshmop fpf       "Pair of single precision registers"  ()  h-fp    f-dest)
+
+(dshmop fvg       "Left single precision vector"        ()  h-fv    f-left)
+(dshmop fvh       "Right single precision vector"       ()  h-fv    f-right)
+(dshmop fvf       "Destination single precision vector" ()  h-fv    f-dest)
+(dshmop mtrxg     "Left single precision matrix"        ()  h-fmtx  f-left)
+
+(dshmop drg       "Left double precision register"      ()  h-dr    f-left)
+(dshmop drh       "Right double precision register"     ()  h-dr    f-right)
+(dshmop drf       "Destination double precision reg"    ()  h-dr    f-dest)
+(dshmop drgh      "Double precision register pair"      ()  h-dr    f-left-right)
+
+(dshmop fpscr     "Floating point status register"      ()  h-fpscr f-nil)
+(dshmop crj       "Control register j"                  ()  h-cr    f-dest)
+(dshmop crk       "Control register k"                 ()  h-cr    f-left)
+
+(dshmop tra       "Target register a"                   ()  h-tr    f-tra)
+(dshmop trb       "Target register b"                   ()  h-tr    f-trb)
+
+(dshmop disp6     "Displacement (6 bits)"              ()  h-sint  f-disp6)
+(dshmop disp6x32  "Displacement (6 bits, scale 32)"     ()  h-sint  f-disp6x32)
+(dshmop disp10    "Displacement (10 bits)"              ()  h-sint  f-disp10)
+(dshmop disp10x2  "Displacement (10 bits, scale 2)"     ()  h-sint  f-disp10x2)
+(dshmop disp10x4  "Displacement (10 bits, scale 4)"     ()  h-sint  f-disp10x4)
+(dshmop disp10x8  "Displacement (10 bits, scale 8)"     ()  h-sint  f-disp10x8)
+(dshmop disp16    "Displacement (16 bits)"              ()  h-sint  f-disp16)
+
+(dshmop imm6      "Immediate (6 bits)"                  ()  h-sint  f-imm6)
+(dshmop imm10     "Immediate (10 bits)"                 ()  h-sint  f-imm10)
+(dshmop imm16     "Immediate (16 bits)"                 ()  h-sint  f-imm16)
+(dshmop uimm6     "Immediate (6 bits)"                  ()  h-uint  f-uimm6)
+(dshmop uimm16    "Unsigned immediate (16 bits)"        ()  h-uint  f-uimm16)
+
+; FIXME: provide these parse/print functions in `sh-media.opc'.
+
+(define-operand (name likely) (comment "Likely branch?") (attrs (ISA media))
+  (type h-uint) (index f-likely) (handlers (parse "likely") (print "likely")))
+
+\f
+; Instructions.
+
+(dshmi add "Add"
+       ()
+       "add $rm, $rn, $rd"
+       (+ (f-op 0) rm (f-ext 9) rn rd (f-rsvd 0))
+       (set rd (add rm rn)))
+
+(dshmi addl "Add long"
+       ()
+       "add.l $rm, $rn, $rd"
+       (+ (f-op 0) rm (f-ext 8) rn rd (f-rsvd 0))
+       (set rd (add (subword SI rm 1) (subword SI rn 1))))
+
+(dshmi addi "Add immediate"
+       ()
+       "addi $rm, $disp10, $rd"
+       (+ (f-op 52) rm disp10 rd (f-rsvd 0))
+       (set rd (add rm (ext DI disp10))))
+
+(dshmi addil "Add immediate long"
+       ()
+       "addi.l $rm, $disp10, $rd"
+       (+ (f-op 53) rm disp10 rd (f-rsvd 0))
+       (set rd (ext DI (add (ext SI disp10) (subword SI rm 1)))))
+
+(dshmi addzl "Add zero extended long"
+       ()
+       "addz.l $rm, $rn, $rd"
+       (+ (f-op 0) rm (f-ext 12) rn rd (f-rsvd 0))
+       (set rd (zext DI (add (subword SI rm 1) (subword SI rn 1)))))
+
+(dshmi alloco "Allocate operand cache block"
+       ()
+       "alloco $rm, $disp6x32"
+       (+ (f-op 56) rm (f-ext 4) disp6x32 (f-dest 63) (f-rsvd 0))
+       (unimp "alloco"))
+
+(dshmi and "AND"
+       ()
+       "and $rm, $rn, $rd"
+       (+ (f-op 1) rm (f-ext 11) rn rd (f-rsvd 0))
+       (set rd (and rm rn)))
+
+(dshmi andc "AND complement"
+       ()
+       "andc $rm, $rn, $rd"
+       (+ (f-op 1) rm (f-ext 15) rn rd (f-rsvd 0))
+       (set rd (and rm (inv rn))))
+
+(dshmi andi "AND immediate"
+       ()
+       "andi $rm, $disp10, $rd"
+       (+ (f-op 54) rm disp10 rd (f-rsvd 0))
+       (set rd (and rm (ext DI disp10))))
+
+(dshmi beq "Branch if equal"
+       ()
+       "beq$likely $rm, $rn, $tra"
+       (+ (f-op 25) rm (f-ext 1) rn likely (f-8-2 0) tra (f-rsvd 0))
+       (if (eq rm rn)
+          (set pc tra)))
+
+(dshmi beqi "Branch if equal immediate"
+       ()
+       "beqi$likely $rm, $imm6, $tra"
+       (+ (f-op 57) rm (f-ext 1) imm6 likely (f-8-2 0) tra (f-rsvd 0))
+       (if (eq rm (ext DI imm6))
+          (set pc tra)))
+
+(dshmi bge "Branch if greater than or equal"
+       ()
+       "bge$likely $rm, $rn, $tra"
+       (+ (f-op 25) rm (f-ext 3) rn likely (f-8-2 0) tra (f-rsvd 0))
+       (if (ge rm rn)
+          (set pc tra)))
+
+(dshmi bgeu "Branch if greater than or equal (unsigned comparison)"
+       ()
+       "bgeu$likely $rm, $rn, $tra"
+       (+ (f-op 25) rm (f-ext 11) rn likely (f-8-2 0) tra (f-rsvd 0))
+       (if (geu rm rn)
+          (set pc tra)))
+
+(dshmi bgt "Branch greater than"
+       ()
+       "bgt$likely $rm, $rn, $tra"
+       (+ (f-op 25) rm (f-ext 7) rn likely (f-8-2 0) tra (f-rsvd 0))
+       (if (gt rm rn)
+          (set pc tra)))
+
+(dshmi bgtu "Branch greater than (unsigned comparison)"
+       ()
+       "bgtu$likely $rm, $rn, $tra"
+       (+ (f-op 25) rm (f-ext 15) rn likely (f-8-2 0) tra (f-rsvd 0))
+       (if (gtu rm rn)
+          (set pc tra)))
+
+(dshmi blink "Branch and link"
+       ()
+       "blink $trb, $rd"
+       (+ (f-op 17) (f-25 0) trb (f-ext 1) (f-right 63) rd (f-rsvd 0))
+       (sequence ()
+                (set rd (or (add pc 4) 1))
+                (set pc trb)))
+
+(dshmi bne "Branch if not equal"
+       ()
+       "bne$likely $rm, $rn, $tra"
+       (+ (f-op 25) rm (f-ext 5) rn likely (f-8-2 0) tra (f-rsvd 0))
+       (if (ne rm rn)
+          (set pc tra)))
+
+(dshmi bnei "Branch if not equal immediate"
+       ()
+       "bnei$likely $rm, $imm6, $tra"
+       (+ (f-op 57) rm (f-ext 5) rn likely (f-8-2 0) tra (f-rsvd 0))
+       (if (ne rm (ext DI imm6))
+          (set pc tra)))
+
+(dshmi brk "Breakpoint instruction"
+       ()
+       "brk"
+       (+ (f-op 27) (f-left 63) (f-ext 5) (f-right 63) (f-dest 63) (f-rsvd 0))
+       (c-call "sh64_break" pc))
+
+(define-pmacro (-byterev-step)
+  (sequence ()
+    (set result (or (sll result 8) (and source 255)))
+    (set source (srl source 8)))
+)
+
+(dshmi byterev "Byte reverse"
+       ()
+       "byterev $rm, $rd"
+       (+ (f-op 0) rm (f-ext 15) (f-right 63) rd (f-rsvd 0))
+       (sequence ((DI source) (DI result))
+                (set source rm)
+                (set result 0)
+                (-byterev-step)
+                (-byterev-step)
+                (-byterev-step)
+                (-byterev-step)
+                (-byterev-step)
+                (-byterev-step)
+                (-byterev-step)
+                (-byterev-step)
+                (set rd result)))
+
+(dshmi cmpeq "Compare equal"
+       ()
+       "cmpeq $rm, $rn, $rd"
+       (+ (f-op 0) rm (f-ext 1) rn rd (f-rsvd 0))
+       (set rd (if DI (eq rm rn) 1 0)))
+
+(dshmi cmpgt "Compare greater than"
+       ()
+       "cmpgt $rm, $rn, $rd"
+       (+ (f-op 0) rm (f-ext 3) rn rd (f-rsvd 0))
+       (set rd (if DI (gt rm rn) 1 0)))
+
+(dshmi cmpgtu "Compare greater than (unsigned comparison)"
+       ()
+       "cmpgtu $rm,$rn, $rd"
+       (+ (f-op 0) rm (f-ext 7) rn rd (f-rsvd 0))
+       (set rd (if DI (gtu rm rn) 1 0)))
+
+(dshmi cmveq "Conditional move if equal to zero"
+       ()
+       "cmveq $rm, $rn, $rd"
+       (+ (f-op 8) rm (f-ext 1) rn rd (f-rsvd 0))
+       (if (eq rm 0)
+          (set rd rn)))
+
+(dshmi cmvne "Conditional move if not equal to zero"
+       ()
+       "cmvne $rm, $rn, $rd"
+       (+ (f-op 8) rm (f-ext 5) rn rd (f-rsvd 0))
+       (if (ne rm 0)
+          (set rd rn)))
+
+(dshmi fabsd "Floating point absolute (double)"
+       ()
+       "fabs.d $drgh, $drf"
+       (+ (f-op 6) drgh (f-ext 1) drf (f-rsvd 0))
+       (set drf (c-call DF "sh64_fabsd" drgh)))
+
+(dshmi fabss "Floating point absolute (single)"
+       ()
+       "fabs.s $frgh, $frf"
+       (+ (f-op 6) frgh (f-ext 0) frf (f-rsvd 0))
+       (set frf (c-call SF "sh64_fabss" frgh)))
+
+(dshmi faddd "Floating point add (double)"
+       ()
+       "fadd.d $drg, $drh, $drf"
+       (+ (f-op 13) drg (f-ext 1) drh drf (f-rsvd 0))
+       (set drf (c-call DF "sh64_faddd" drg drh)))
+
+(dshmi fadds "Floating point add (single)"
+       ()
+       "fadd.s $frg, $frh, $frf"
+       (+ (f-op 13) frg (f-ext 0) frh frf (f-rsvd 0))
+       (set frf (c-call SF "sh64_fadds" frg frh)))
+
+(dshmi fcmpeqd "Floating point compare if equal (double)"
+       ()
+       "fcmpeq.d $drg, $drh, $rd"
+       (+ (f-op 12) drg (f-ext 9) drh rd (f-rsvd 0))
+       (set rd (zext DI (c-call BI "sh64_fcmpeqd" drg drh))))
+
+(dshmi fcmpeqs "Floating point compare if equal (single)"
+       ()
+       "fcmpeq.s $frg, $frh, $rd"
+       (+ (f-op 12) frg (f-ext 8) frh rd (f-rsvd 0))
+       (set rd (zext DI (c-call BI "sh64_fcmpeqs" frg frh))))
+
+(dshmi fcmpged "Floating compare compare if greater than or equal (double)"
+       ()
+       "fcmpge.d $drg, $drh, $rd"
+       (+ (f-op 12) drg (f-ext 15) drh rd (f-rsvd 0))
+       (set rd (zext DI (c-call BI "sh64_fcmpged" drg drh))))
+
+(dshmi fcmpges "Floating point compare if greater than or equal (single)"
+       ()
+       "fcmpge.s $frg, $frh, $rd"
+       (+ (f-op 12) frg (f-ext 14) frh rd (f-rsvd 0))
+       (set rd (zext DI (c-call BI "sh64_fcmpges" frg frh))))
+
+(dshmi fcmpgtd "Floating point compare if greater than (double)"
+       ()
+       "fcmpgt.d $drg, $drh, $rd"
+       (+ (f-op 12) drg (f-ext 13) drh rd (f-rsvd 0))
+       (set rd (zext DI (c-call BI "sh64_fcmpgtd" drg drh))))
+
+(dshmi fcmpgts "Floating point compare if greater than (single)"
+       ()
+       "fcmpgt.s $frg, $frh, $rd"
+       (+ (f-op 12) frg (f-ext 12) frh rd (f-rsvd 0))
+       (set rd (zext DI (c-call BI "sh64_fcmpgts" frg frh))))
+
+(dshmi fcmpund "Floating point unordered comparison (double)"
+       ()
+       "fcmpun.d $drg, $drh, $rd"
+       (+ (f-op 12) drg (f-ext 11) drh rd (f-rsvd 0))
+       (set rd (zext DI (c-call BI "sh64_fcmpund" drg drh))))
+
+(dshmi fcmpuns "Floating point unordered comparison (single)"
+       ()
+       "fcmpun.s $frg, $frh, $rd"
+       (+ (f-op 12) frg (f-ext 10) frh rd (f-rsvd 0))
+       (set rd (zext DI (c-call BI "sh64_fcmpuns" frg frh))))
+
+(dshmi fcnvds "Floating point coversion (double to single)"
+       ()
+       "fcnv.ds $drgh, $frf"
+       (+ (f-op 14) drgh (f-ext 7) frf (f-rsvd 0))
+       (set frf (c-call SF "sh64_fcnvds" drgh)))
+
+(dshmi fcnvsd "Floating point conversion (single to double)"
+       ()
+       "fcnv.sd $frgh, $drf"
+       (+ (f-op 14) frgh (f-ext 6) drf (f-rsvd 0))
+       (set drf (c-call DF "sh64_fcnvsd" frgh)))
+
+(dshmi fdivd "Floating point divide (double)"
+       ()
+       "fdiv.d $drg, $drh, $drf"
+       (+ (f-op 13) drg (f-ext 5) drh drf (f-rsvd 0))
+       (set drf (c-call DF "sh64_fdivd" drg drh)))
+
+(dshmi fdivs "Floating point divide (single)"
+       ()
+       "fdiv.s $frg, $frh, $frf"
+       (+ (f-op 13) frg (f-ext 4) frh frf (f-rsvd 0))
+       (set frf (c-call SF "sh64_fdivs" frg frh)))
+
+(dshmi fgetscr "Floating point get from FPSCR"
+       ()
+       "fgetscr $frf"
+       (+ (f-op 7) (f-left 63) (f-ext 2) (f-right 63) frf (f-rsvd 0))
+       (unimp "fputscr"))
+       ; FIXME: this should work!
+       ; (set frf fpscr))
+
+(dshmi fiprs "Floating point inner product (single)"
+       ()
+       "fipr.s $fvg, $fvh, $frf"
+       (+ (f-op 5) fvg (f-ext 6) fvh frf (f-rsvd 0))
+       (sequence ((UQI g) (UQI h) (SF temp))
+                (set g (index-of fvg))
+                (set h (index-of fvh))
+                (set temp (c-call SF "sh64_fmuls" (reg h-fr g) (reg h-fr h)))
+                (set temp (c-call SF "sh64_fadds" temp
+                  (c-call SF "sh64_fmuls" (reg h-fr (add g 1)) (reg h-fr (add h 1)))))
+                (set temp (c-call SF "sh64_fadds" temp
+                  (c-call SF "sh64_fmuls" (reg h-fr (add g 2)) (reg h-fr (add h 2)))))
+                (set temp (c-call SF "sh64_fadds" temp
+                  (c-call SF "sh64_fmuls" (reg h-fr (add g 3)) (reg h-fr (add h 3)))))
+                (set frf temp)))
+
+(dshmi fldd "Floating point load (double)"
+       ()
+       "fld.d $rm, $disp10x8, $drf"
+       (+ (f-op 39) rm disp10x8 drf (f-rsvd 0))
+       (set drf (mem DF (add rm disp10x8))))
+
+(dshmi fldp "Floating point load (pair of singles)"
+       ()
+       "fld.p $rm, $disp10x8, $fpf"
+       (+ (f-op 38) rm disp10x8 fpf (f-rsvd 0))
+       (sequence ((QI f))
+                (set f (index-of fpf))
+                (set (reg h-fr f) (mem SF (add rm disp10x8)))
+                (set (reg h-fr (add f 1)) (mem SF (add rm (add disp10x8 4))))))
+
+(dshmi flds "Floating point load (single)"
+       ()
+       "fld.s $rm, $disp10x4, $frf"
+       (+ (f-op 37) rm disp10x4 frf (f-rsvd 0))
+       (set frf (mem SF (add rm disp10x4))))
+
+(dshmi fldxd "Floating point extended load (double)"
+       ()
+       "fldx.d $rm, $rn, $drf"
+       (+ (f-op 7) rm (f-ext 9) rn frf (f-rsvd 0))
+       (set drf (mem DF (add rm rn))))
+
+(dshmi fldxp "Floating point extended load (pair of singles)"
+       ()
+       "fldx.p $rm, $rn, $fpf"
+       (+ (f-op 7) rm (f-ext 13) rn fpf (f-rsvd 0))
+       (sequence ((QI f))
+                (set f (index-of fpf))
+                (set (reg h-fr f) (mem SF (add rm rn)))
+                (set (reg h-fr (add f 1)) (mem SF (add rm (add rn 4))))))
+
+(dshmi fldxs "Floating point extended load (single)"
+       ()
+       "fldx.s $rm, $rn, $frf"
+       (+ (f-op 7) rm (f-ext 8) rn frf (f-rsvd 0))
+       (set frf (mem SF (add rm rn))))
+
+(dshmi floatld "Floating point conversion (long to double)"
+       ()
+       "float.ld $frgh, $drf"
+       (+ (f-op 14) frgh (f-ext 14) drf (f-rsvd 0))
+       (set drf (c-call DF "sh64_floatld" frgh)))
+
+(dshmi floatls "Floating point conversion (long to single)"
+       ()
+       "float.ls $frgh, $frf"
+       (+ (f-op 14) frgh (f-ext 12) frf (f-rsvd 0))
+       (set frf (c-call SF "sh64_floatls" frgh)))
+
+(dshmi floatqd "Floating point conversion (quad to double)"
+       ()
+       "float.qd $drgh, $drf"
+       (+ (f-op 14) drgh (f-ext 13) drf (f-rsvd 0))
+       (set drf (c-call DF "sh64_floatqd" drgh)))
+
+(dshmi floatqs "Floating point conversion (quad to single)"
+       ()
+       "float.qs $drgh, $frf"
+       (+ (f-op 14) drgh (f-ext 15) frf (f-rsvd 0))
+       (set frf (c-call SF "sh64_floatqs" drgh)))
+
+(dshmi fmacs "Floating point multiply and accumulate (single)"
+       ()
+       "fmac.s $frg, $frh, $frf"
+       (+ (f-op 13) frg (f-ext 14) frh frf (f-rsvd 0))
+       (set frf (c-call SF "sh64_fadds" frf (c-call SF "sh64_fmuls" frg frh))))
+
+(dshmi fmovd "Floating point move double"
+       ()
+       "fmov.d $drgh, $drf"
+       (+ (f-op 14) drgh (f-ext 1) drf (f-rsvd 0))
+       (set drf drgh))
+
+(dshmi fmovdq "Floating point move (double to quad integer)"
+       ()
+       "fmov.dq $drgh, $rd"
+       (+ (f-op 12) drgh (f-ext 1) rd (f-rsvd 0))
+       (set rd (subword DI drgh 0)))
+
+(dshmi fmovls "Floating point move (lower to single)"
+       ()
+       "fmov.ls $rm, $frf"
+       (+ (f-op 7) rm (f-ext 0) (f-right 63) frf (f-rsvd 0))
+       (set frf (subword SF (subword SI rm 1) 0)))
+
+(dshmi fmovqd "Floating point move (quad to double)"
+       ()
+       "fmov.qd $rm, $drf"
+       (+ (f-op 7) rm (f-ext 1) (f-right 63) frf (f-rsvd 0))
+       (set drf (subword DF rm 0)))
+
+(dshmi fmovs "Floating point move (single)"
+       ()
+       "fmov.s $frgh, $frf"
+       (+ (f-op 14) frgh (f-ext 0) frf (f-rsvd 0))
+       (set frf frgh))
+
+(dshmi fmovsl "Floating point move (single to lower)"
+       ()
+       "fmov.sl $frgh, $rd"
+       (+ (f-op 12) frgh (f-ext 0) rd (f-rsvd 0))
+       (set rd (ext DI (subword SI frgh 1))))
+
+(dshmi fmuld "Floating point multiply (double)"
+       ()
+       "fmul.d $drg, $drh, $drf"
+       (+ (f-op 13) drg (f-ext 7) drh drf (f-rsvd 0))
+       (set drf (c-call DF "sh64_fmuld" drg drh)))
+
+(dshmi fmuls "Floating point multiply (single)"
+       ()
+       "fmul.s $frg, $frh, $frf"
+       (+ (f-op 13) frg (f-ext 6) frh frf (f-rsvd 0))
+       (set frf (c-call SF "sh64_fmuls" frg frh)))
+
+(dshmi fnegd "Floating point negate (double)"
+       ()
+       "fneg.d $drgh, $drf"
+       (+ (f-op 6) drgh (f-ext 3) drf (f-rsvd 0))
+       (set drf (c-call DF "sh64_fnegd" drgh)))
+
+(dshmi fnegs "Floating point negate (single)"
+       ()
+       "fneg.s $frgh, $frf"
+       (+ (f-op 6) frgh (f-ext 2) frf (f-rsvd 0))
+       (set frf (c-call SF "sh64_fnegs" frgh)))
+
+(dshmi fputscr "Floating point put to FPSCR"
+       ()
+       "fputscr $frgh"
+       (+ (f-op 12) frgh (f-ext 2) (f-dest 63) (f-rsvd 0))
+       (unimp "fputscr"))
+       ; FIXME: this should work!
+       ; (set fpscr (subword SI frgh 0)))
+
+(dshmi fsqrtd "Floating point square root (double)"
+       ()
+       "fsqrt.d $drgh, $drf"
+       (+ (f-op 14) drgh (f-ext 5) drf (f-rsvd 0))
+       (set drf (c-call DF "sh64_fsqrtd" drgh)))
+
+(dshmi fsqrts "Floating point squart root (single)"
+       ()
+       "fsqrt.s $frgh, $frf"
+       (+ (f-op 14) frgh (f-ext 4) frf (f-rsvd 0))
+       (set frf (c-call SF "sh64_fsqrts" frgh)))
+
+(dshmi fstd "Floating point store (double)"
+       ()
+       "fst.d $rm, $disp10x8, $drf"
+       (+ (f-op 47) rm disp10x8 drf (f-rsvd 0))
+       (set (mem DF (add rm disp10x8)) drf))
+
+(dshmi fstp "Floating point store (pair of singles)"
+       ()
+       "fst.p $rm, $disp10x8, $fpf"
+       (+ (f-op 46) rm disp10x8 fpf (f-rsvd 0))
+       (sequence ((QI f))
+                (set f (index-of fpf))
+                (set (mem SF (add rm disp10x8)) (reg h-fr f))
+                (set (mem SF (add rm (add disp10x8 4))) (reg h-fr (add f 1)))))
+
+(dshmi fsts "Floating point store (single)"
+       ()
+       "fst.s $rm, $disp10x4, $frf"
+       (+ (f-op 45) rm disp10x4 frf (f-rsvd 0))
+       (set (mem SF (add rm disp10x4)) frf))
+
+(dshmi fstxd "Floating point extended store (double)"
+       ()
+       "fstx.d $rm, $rn, $drf"
+       (+ (f-op 15) rm (f-ext 9) rn drf (f-rsvd 0))
+       (set (mem DF (add rm rn)) drf))
+
+(dshmi fstxp "Floating point extended store (pair of singles)"
+       ()
+       "fstx.p $rm, $rn, $fpf"
+       (+ (f-op 15) rm (f-ext 13) rn fpf (f-rsvd 0))
+       (sequence ((QI f))
+                (set f (index-of fpf))
+                (set (mem SF (add rm rn)) (reg h-fr f))
+                (set (mem SF (add rm (add rn 4))) (reg h-fr (add f 1)))))
+
+(dshmi fstxs "Floating point extended store (single)"
+       ()
+       "fstx.s $rm, $rn, $frf"
+       (+ (f-op 15) rm (f-ext 8) rn frf (f-rsvd 0))
+       (set (mem SF (add rm rn)) frf))
+
+(dshmi fsubd "Floating point subtract (double)"
+       ()
+       "fsub.d $drg, $drh, $drf"
+       (+ (f-op 13) frg (f-ext 3) frh frf (f-rsvd 0))
+       (set drf (c-call DF "sh64_fsubd" drg drh)))
+
+(dshmi fsubs "Floating point subtract (single)"
+       ()
+       "fsub.s $frg, $frh, $frf"
+       (+ (f-op 13) frg (f-ext 2) frh frf (f-rsvd 0))
+       (set frf (c-call SF "sh64_fsubs" frg frh)))
+
+(dshmi ftrcdl "Floating point conversion (double to long)"
+       ()
+       "ftrc.dl $drgh, $frf"
+       (+ (f-op 14) drgh (f-ext 11) frf (f-rsvd 0))
+       (set frf (c-call SF "sh64_ftrcdl" drgh)))
+
+(dshmi ftrcsl "Floating point conversion (single to long)"
+       ()
+       "ftrc.sl $frgh, $frf"
+       (+ (f-op 14) frgh (f-ext 8) frf (f-rsvd 0))
+       (set frf (c-call SF "sh64_ftrcsl" frgh)))
+
+(dshmi ftrcdq "Floating point conversion (double to quad)"
+       ()
+       "ftrc.dq $drgh, $drf"
+       (+ (f-op 14) drgh (f-ext 9) frf (f-rsvd 0))
+       (set drf (c-call DF "sh64_ftrcdq" drgh)))
+
+(dshmi ftrcsq "Floating point conversion (single to quad)"
+       ()
+       "ftrc.sq $frgh, $drf"
+       (+ (f-op 14) frgh (f-ext 10) drf (f-rsvd 0))
+       (set drf (c-call DF "sh64_ftrcsq" frgh)))
+
+(dshmi ftrvs "Floating point matrix multiply"
+       ()
+       "ftrv.s $mtrxg, $fvh, $fvf"
+       (+ (f-op 5) mtrxg (f-ext 14) fvh fvf (f-rsvd 0))
+       (c-call "sh64_ftrvs" (index-of mtrxg) (index-of fvh) (index-of fvf)))
+
+(dshmi getcfg "Get configuration register"
+       ()
+       "getcfg $rm, $disp6, $rd"
+       (+ (f-op 48) rm (f-ext 15) disp6 rd (f-rsvd 0))
+       (unimp "getcfg"))
+
+(dshmi getcon "Get control register"
+       ()
+       "getcon $crk, $rd"
+       (+ (f-op 9) crk (f-ext 15) (f-right 63) rd (f-rsvd 0))
+       (set rd crk))
+
+(dshmi gettr "Get target register"
+       ()
+       "gettr $trb, $rd"
+       (+ (f-op 17) (f-25 0) trb (f-ext 5) (f-right 63) rd (f-rsvd 0))
+       (set rd trb))
+
+(dshmi icbi "Invalidate instruction cache block"
+       ()
+       "icbi $rm, $disp6x32"
+       (+ (f-op 56) rm (f-ext 5) disp6x32 (f-dest 63) (f-rsvd 0))
+       (unimp "icbi"))
+
+(dshmi ldb "Load byte"
+       ()
+       "ld.b $rm, $disp10, $rd"
+       (+ (f-op 32) rm disp10 rd (f-rsvd 0))
+       (set rd (ext DI (mem QI (add rm (ext DI disp10))))))
+
+(dshmi ldl "Load long word"
+       ()
+       "ld.l $rm, $disp10x4, $rd"
+       (+ (f-op 34) rm disp10x4 rd (f-rsvd 0))
+       (set rd (ext DI (mem SI (add rm (ext DI disp10x4))))))
+
+(dshmi ldq "Load quad word"
+       ()
+       "ld.q $rm, $disp10x8, $rd"
+       (+ (f-op 35) rm disp10x8 rd (f-rsvd 0))
+       (set rd (mem DI (add rm (ext DI disp10x8)))))
+
+(dshmi ldub "Load unsigned byte"
+       ()
+       "ld.ub $rm, $disp10, $rd"
+       (+ (f-op 36) rm disp10 rd (f-rsvd 0))
+       (set rd (zext DI (mem QI (add rm (ext DI disp10))))))
+
+(dshmi lduw "Load unsigned word"
+       ()
+       "ld.uw $rm, $disp10x2, $rd"
+       (+ (f-op 44) rm disp10 rd (f-rsvd 0))
+       (set rd (zext DI (mem HI (add rm (ext DI disp10x2))))))
+
+(dshmi ldw "Load word"
+       ()
+       "ld.w $rm, $disp10x2, $rd"
+       (+ (f-op 33) rm disp10 rd (f-rsvd 0))
+       (set rd (ext DI (mem HI (add rm (ext DI disp10x2))))))
+
+(dshmi ldhil "Load high part (long word)"
+       ()
+       "ldhi.l $rm, $disp6, $rd"
+       (+ (f-op 48) rm (f-ext 6) disp6 rd (f-rsvd 0))
+       ; FIXME.
+       (unimp "ldhil"))
+
+(dshmi ldhiq "Load high part (quad word)"
+       ()
+       "ldhi.q $rm, $disp6, $rd"
+       (+ (f-op 48) rm (f-ext 7) disp6 rd (f-rsvd 0))
+       ; FIXME.
+       (unimp "ldhiq"))
+
+(dshmi ldlol "Load low part (long word)"
+       ()
+       "ldlo.l $rm, $disp6, $rd"
+       (+ (f-op 48) rm (f-ext 2) disp6 rd (f-rsvd 0))
+       ; FIXME.
+       (unimp "ldlol"))
+
+(dshmi ldloq "Load low part (quad word)"
+       ()
+       "ldlo.q $rm, $disp6, $rd"
+       (+ (f-op 48) rm (f-ext 3) disp6 rd (f-rsvd 0))
+       ; FIXME;
+       (unimp "ldloq"))
+
+(dshmi ldxb "Load byte (extended displacement)"
+       ()
+       "ldx.b $rm, $rn, $rd"
+       (+ (f-op 16) rm (f-ext 0) rn rd (f-rsvd 0))
+       (set rd (ext DI (mem QI (add rm rn)))))
+
+(dshmi ldxl "Load long word (extended displacement)"
+       ()
+       "ldx.l $rm, $rn, $rd"
+       (+ (f-op 16) rm (f-ext 2) rn rd (f-rsvd 0))
+       (set rd (ext DI (mem SI (add rm rn)))))
+
+(dshmi ldxq "Load quad word (extended displacement)"
+       ()
+       "ldx.q $rm, $rn, $rd"
+       (+ (f-op 16) rm (f-ext 3) rn rd (f-rsvd 0))
+       (set rd (mem DI (add rm rn))))
+
+(dshmi ldxub "Load unsigned byte (extended displacement)"
+       ()
+       "ldx.ub $rm, $rn, $rd"
+       (+ (f-op 16) rm (f-ext 4) rn rd (f-rsvd 0))
+       (set rd (zext DI (mem UQI (add rm rn)))))
+
+(dshmi ldxuw "Load unsigned word (extended displacement)"
+       ()
+       "ldx.uw $rm, $rn, $rd"
+       (+ (f-op 16) rm (f-ext 5) rn rd (f-rsvd 0))
+       (set rd (zext DI (mem UHI (add rm rn)))))
+
+(dshmi ldxw "Load word (extended displacement)"
+       ()
+       "ldx.w $rm, $rn, $rd"
+       (+ (f-op 16) rm (f-ext 1) rn rd (f-rsvd 0))
+       (set rd (ext DI (mem HI (add rm rn)))))
+
+\f
+; Macros to facilitate multimedia instructions.
+
+(define-pmacro (slice-byte expr)
+  (sequence ((QI result7) (QI result6) (QI result5) (QI result4)
+            (QI result3) (QI result2) (QI result1) (QI result0))
+           (set result0 (expr (subword QI rm 7) (subword QI rn 7)))
+           (set result1 (expr (subword QI rm 6) (subword QI rn 6)))
+           (set result2 (expr (subword QI rm 5) (subword QI rn 5)))
+           (set result3 (expr (subword QI rm 4) (subword QI rn 4)))
+           (set result4 (expr (subword QI rm 3) (subword QI rn 3)))
+           (set result5 (expr (subword QI rm 2) (subword QI rn 2)))
+           (set result6 (expr (subword QI rm 1) (subword QI rn 1)))
+           (set result7 (expr (subword QI rm 0) (subword QI rn 0)))
+           (set rd (-join-qi result7 result6 result5 result4 result3 result2
+                          result1 result0))))
+
+(define-pmacro (slice-word expr)
+  (sequence ((HI result3) (HI result2) (HI result1) (HI result0))
+           (set result0 (expr (subword HI rm 3) (subword HI rn 3)))
+           (set result1 (expr (subword HI rm 2) (subword HI rn 2)))
+           (set result2 (expr (subword HI rm 1) (subword HI rn 1)))
+           (set result3 (expr (subword HI rm 0) (subword HI rn 0)))
+           (set rd (-join-hi result3 result2 result1 result0))))
+
+(define-pmacro (slice-word-unop expr)
+  (sequence ((HI result3) (HI result2) (HI result1) (HI result0))
+           (set result0 (expr (subword HI rm 3)))
+           (set result1 (expr (subword HI rm 2)))
+           (set result2 (expr (subword HI rm 1)))
+           (set result3 (expr (subword HI rm 0)))
+           (set rd (-join-hi result3 result2 result1 result0))))
+
+(define-pmacro (slice-long expr)
+  (sequence ((SI result1) (SI result0))
+           (set result0 (expr (subword SI rm 1) (subword SI rn 1)))
+           (set result1 (expr (subword SI rm 0) (subword SI rn 0)))
+           (set rd (-join-si result1 result0))))
+
+(define-pmacro (slice-long-unop expr)
+  (sequence ((SI result1) (SI result0))
+           (set result0 (expr (subword SI rm 1)))
+           (set result1 (expr (subword SI rm 0)))
+           (set rd (-join-si result1 result0))))
+
+; Multimedia instructions.
+
+(dshmi mabsl "Multimedia absolute value (long word)"
+       ()
+       "mabs.l $rm, $rd"
+       (+ (f-op 10) rm (f-ext 10) (f-right 63) rd (f-rsvd 0))
+       (slice-long-unop abs))
+
+(dshmi mabsw "Multimedia absolute value (word)"
+       ()
+       "mabs.w $rm, $rd"
+       (+ (f-op 10) rm (f-ext 9) (f-right 63) rd (f-rsvd 0))
+       (slice-word-unop abs))
+
+(dshmi maddl "Multimedia add (long word)"
+       ()
+       "madd.l $rm, $rn, $rd"
+       (+ (f-op 2) rm (f-ext 2) rn rd (f-rsvd 0))
+       (slice-long add))
+
+(dshmi maddw "Multimedia add (word)"
+       ()
+       "madd.w $rm, $rn, $rd"
+       (+ (f-op 2) rm (f-ext 1) rn rd (f-rsvd 0))
+       (slice-word add))
+
+(define-pmacro (-maddsl arg1 arg2) (saturate SI 32 (add arg1 arg2)))
+(dshmi maddsl "Multimedia add (saturating, long word)"
+       ()
+       "madds.l $rm, $rn, $rd"
+       (+ (f-op 2) rm (f-ext 6) rn rd (f-rsvd 0))
+       (slice-long -maddsl))
+
+(define-pmacro (-maddsub arg1 arg2) (usaturate QI 8 (add arg1 arg2)))
+(dshmi maddsub "Multimedia add (saturating, unsigned byte)"
+       ()
+       "madds.ub $rm, $rn, $rd"
+       (+ (f-op 2) rm (f-ext 4) rn rd (f-rsvd 0))
+       (slice-byte -maddsub))
+
+(define-pmacro (-maddsw arg1 arg2) (saturate HI 16 (add arg1 arg2)))
+(dshmi maddsw "Multimedia add (saturating, word)"
+       ()
+       "madds.w $rm, $rn, $rd"
+       (+ (f-op 2) rm (f-ext 5) rn rd (f-rsvd 0))
+       (slice-word -maddsw))
+
+(define-pmacro (-mcmpeq mode arg1 arg2)
+  (if mode (eq arg1 arg2) (inv mode 0) (const mode 0)))
+
+(define-pmacro (-mcmpeqb arg1 arg2) (-mcmpeq QI arg1 arg2))
+(dshmi mcmpeqb "Multimedia compare equal (byte)"
+       ()
+       "mcmpeq.b $rm, $rn, $rd"
+       (+ (f-op 10) rm (f-ext 0) rn rd (f-rsvd 0))
+       (slice-byte -mcmpeqb))
+
+(define-pmacro (-mcmpeql arg1 arg2) (-mcmpeq SI arg1 arg2))
+(dshmi mcmpeql "Multimedia compare equal (long word)"
+       ()
+       "mcmpeq.l $rm, $rn, $rd"
+       (+ (f-op 10) rm (f-ext 2) rn rd (f-rsvd 0))
+       (slice-long -mcmpeql))
+
+(define-pmacro (-mcmpeqw arg1 arg2) (-mcmpeq HI arg1 arg2))
+(dshmi mcmpeqw "Multimedia compare equal (word)"
+       ()
+       "mcmpeq.w $rm, $rn, $rd"
+       (+ (f-op 10) rm (f-ext 1) rn rd (f-rsvd 0))
+       (slice-word -mcmpeqw))
+
+(define-pmacro (-mcmpgt mode arg1 arg2)
+  (if mode (gt arg1 arg2) (inv mode 0) (const mode 0)))
+(define-pmacro (-mcmpgtu mode arg1 arg2)
+  (if mode (gtu arg1 arg2) (inv mode 0) (const mode 0)))
+
+(define-pmacro (-mcmpgtl arg1 arg2) (-mcmpgt SI arg1 arg2))
+(dshmi mcmpgtl "Multimedia compare greater than (long word)"
+       ()
+       "mcmpgt.l $rm, $rn, $rd"
+       (+ (f-op 10) rm (f-ext 6) rn rd (f-rsvd 0))
+       (slice-long -mcmpgtl))
+
+(define-pmacro (-mcmpgtub arg1 arg2) (-mcmpgtu QI arg1 arg2))
+(dshmi mcmpgtub "Multimediate compare unsigned greater than (byte)"
+       ()
+       "mcmpgt.ub $rm, $rn, $rd"
+       (+ (f-op 10) rm (f-ext 4) rn rd (f-rsvd 0))
+       (slice-byte -mcmpgtub))
+
+(define-pmacro (-mcmpgtw arg1 arg2) (-mcmpgt HI arg1 arg2))
+(dshmi mcmpgtw "Multimedia compare greater than (word)"
+       ()
+       "mcmpgt.w $rm, $rn, $rd"
+       (+ (f-op 10) rm (f-ext 5) rn rd (f-rsvd 0))
+       (slice-word -mcmpgtw))
+
+(dshmi mcmv "Multimedia conditional move"
+       ()
+       "mcmv $rm, $rn, $rd"
+       (+ (f-op 18) rm (f-ext 3) rn rd (f-rsvd 0))
+       (set rd (or (and rm rn) (and rd (inv rn)))))
+
+(dshmi mcnvslw "Multimedia convert/saturate (long to word)"
+       ()
+       "mcnvs.lw $rm, $rn, $rd"
+       (+ (f-op 19) rm (f-ext 13) rn rd (f-rsvd 0))
+       (sequence ((HI result3) (HI result2) (HI result1) (HI result0))
+                (set result0 (saturate HI 16 (subword SI rm 0)))
+                (set result1 (saturate HI 16 (subword SI rm 1)))
+                (set result2 (saturate HI 16 (subword SI rn 0)))
+                (set result3 (saturate HI 16 (subword SI rn 1)))
+                (set rd (-join-hi result3 result2 result1 result0))))
+
+(dshmi mcnvswb "Multimedia convert/saturate (word to byte)"
+       ()
+       "mcnvs.wb $rm, $rn, $rd"
+       (+ (f-op 19) rm (f-ext 8) rn rd (f-rsvd 0))
+       (sequence ((QI result7) (QI result6) (QI result5) (QI result4) 
+                 (QI result3) (QI result2) (QI result1) (QI result0))
+                (set result0 (saturate QI 8 (subword HI rm 0)))
+                (set result1 (saturate QI 8 (subword HI rm 1)))
+                (set result2 (saturate QI 8 (subword HI rm 2)))
+                (set result3 (saturate QI 8 (subword HI rm 3)))
+                (set result4 (saturate QI 8 (subword HI rn 0)))
+                (set result5 (saturate QI 8 (subword HI rn 1)))
+                (set result6 (saturate QI 8 (subword HI rn 2)))
+                (set result7 (saturate QI 8 (subword HI rn 3)))
+                (set rd (-join-qi result7 result6 result5 result4
+                                result3 result2 result1 result0))))
+
+(dshmi mcnvswub "Multimedia convert/saturate (word to unsigned byte)"
+       ()
+       "mcnvs.wub $rm, $rn, $rd"
+       (+ (f-op 19) rm (f-ext 12) rn rd (f-rsvd 0))
+       (sequence ((QI result7) (QI result6) (QI result5) (QI result4)
+                              (QI result3) (QI result2) (QI result1) (QI result0))
+                (set result0 (usaturate QI 8 (subword HI rm 0)))
+                (set result1 (usaturate QI 8 (subword HI rm 1)))
+                (set result2 (usaturate QI 8 (subword HI rm 2)))
+                (set result3 (usaturate QI 8 (subword HI rm 3)))
+                (set result4 (usaturate QI 8 (subword HI rn 0)))
+                (set result5 (usaturate QI 8 (subword HI rn 1)))
+                (set result6 (usaturate QI 8 (subword HI rn 2)))
+                (set result7 (usaturate QI 8 (subword HI rn 3)))
+                (set rd (-join-qi result7 result6 result5 result4 result3
+                                result2 result1 result0))))
+
+; mexter -- generate an mexterN instruction, where:
+;   op = primary opcode
+;   extop = extended opcode
+
+(define-pmacro (make-mextr n op extop)
+  (dshmi (.sym mextr n)
+        (.str "Multimedia extract 64-bit slice (from byte " n ")")
+        ()
+        (.str "mextr" n " $rm, $rn, $rd")
+        (+ (f-op op) rm (f-ext extop) rn rd (f-rsvd 0))
+        (sequence ((QI count) (DI mask) (DI rhs))
+                  (set count (mul QI 8 (sub QI 8 n)))
+                  (set mask (sll DI (inv 0) count))
+                  (set rhs (srl (and rm mask) count))
+                  (set count (mul QI 8 n))
+                  (set mask (srl DI (inv 0) count))
+                  (set rd (or DI rhs (sll DI (and rn mask) count))))))
+
+(make-mextr 1 10  7)
+(make-mextr 2 10 11)
+(make-mextr 3 10 15)
+(make-mextr 4 11  3)
+(make-mextr 5 11  7)
+(make-mextr 6 11 11)
+(make-mextr 7 11 15)
+
+(dshmi mmacfxwl "Multimedia fractional multiply (word to long)"
+       ()
+       "mmacfx.wl $rm, $rn, $rd"
+       (+ (f-op 18) rm (f-ext 1) rn rd (f-rsvd 0))
+       (sequence ((SI temp) (SI result1) (SI result0))
+                (set result0 (subword SI rd 0))
+                (set result1 (subword SI rd 1))
+                (set temp (mul (zext SI (subword HI rm 0)) (zext SI (subword HI rn 0))))
+                (set temp (saturate SI 32 (sll temp 1)))
+                (set result0 (saturate SI 32 (add result0 temp)))
+                (set temp (mul (zext SI (subword HI rm 1)) (zext SI (subword HI rn 1))))
+                (set temp (saturate SI 32 (sll temp 1)))
+                (set result1 (saturate SI 32 (add result1 temp)))
+                (set rd (-join-si result1 result0))))
+
+(dshmi mmacnfx.wl "Multimedia fractional multiple (word to long)"
+       ()
+       "mmacnfx.wl $rm, $rn, $rd"
+       (+ (f-op 18) rn (f-ext 5) rn rd (f-rsvd 0))
+       (sequence ((SI temp) (SI result1) (SI result0))
+                (set result0 (subword SI rd 0))
+                (set result1 (subword SI rd 1))
+                (set temp (mul (zext SI (subword HI rm 0)) (zext SI (subword HI rn 0))))
+                (set temp (saturate SI 32 (sll temp 1)))
+                (set result0 (saturate SI 32 (sub result0 temp)))
+                (set temp (mul (zext SI (subword HI rm 1)) (zext SI (subword HI rn 1))))
+                (set temp (saturate SI 32 (sll temp 1)))
+                (set result1 (saturate SI 32 (sub result1 temp)))
+                (set rd (-join-si result1 result0))))
+
+(dshmi mmull "Multimedia multiply (long word)"
+       ()
+       "mmul.l $rm, $rn, $rd"
+       (+ (f-op 19) rm (f-ext 2) rn rd (f-rsvd 0))
+       (slice-long mul))
+
+(dshmi mmulw "Multimedia multiply (word)"
+       ()
+       "mmul.w $rm, $rn, $rd"
+       (+ (f-op 19) rm (f-ext 1) rn rd (f-rsvd 0))
+       (slice-word mul))
+
+(dshmi mmulfxl "Multimedia fractional multiply (long word)"
+       ()
+       "mmulfx.l $rm, $rn, $rd"
+       (+ (f-op 19) rm (f-ext 6) rn rd (f-rsvd 0))
+       (sequence ((DI temp) (SI result0) (SI result1))
+                (set temp (mul (zext DI (subword SI rm 0)) (zext DI (subword SI rn 0))))
+                (set result0 (saturate SI 32 (sra temp 31)))
+                (set temp (mul (zext DI (subword SI rm 1)) (zext DI (subword SI rn 1))))
+                (set result1 (saturate SI 32 (sra temp 31)))
+                (set rd (-join-si result1 result0))))
+
+(dshmi mmulfxw "Multimedia fractional multiply (word)"
+       ()
+       "mmulfx.w $rm, $rn, $rd"
+       (+ (f-op 19) rm (f-ext 5) rn rd (f-rsvd 0))
+       (sequence ((SI temp) (HI result0) (HI result1) (HI result2) (HI result3))
+                (set temp (mul (zext SI (subword HI rm 0)) (zext SI (subword HI rn 0))))
+                (set result0 (saturate HI 16 (sra temp 15)))
+                (set temp (mul (zext SI (subword HI rm 1)) (zext SI (subword HI rn 1))))
+                (set result1 (saturate HI 16 (sra temp 15)))
+                (set temp (mul (zext SI (subword HI rm 2)) (zext SI (subword HI rn 2))))
+                (set result2 (saturate HI 16 (sra temp 15)))
+                (set temp (mul (zext SI (subword HI rm 3)) (zext SI (subword HI rn 3))))
+                (set result3 (saturate HI 16 (sra temp 15)))
+                (set rd (-join-hi result3 result2 result1 result0))))
+
+(dshmi mmulfxrpw "Multimedia fractional multiply round positive (word op)"
+       ()
+       "mmulfxrp.w $rm, $rn, $rd"
+       (+ (f-op 19) rm (f-ext 9) rn rd (f-rsvd 0))
+       (sequence ((SI temp) (HI result0) (HI result1) (HI result2) (HI result3) (HI c))
+                (set c (sll 1 14))
+                (set temp (mul (zext SI (subword HI rm 0)) (zext SI (subword HI rn 0))))
+                (set result0 (saturate HI 16 (sra (add temp c) 15)))
+                (set temp (mul (zext SI (subword HI rm 1)) (zext SI (subword HI rn 1))))
+                (set result1 (saturate HI 16 (sra (add temp c) 15)))
+                (set temp (mul (zext SI (subword HI rm 2)) (zext SI (subword HI rn 2))))
+                (set result2 (saturate HI 16 (sra (add temp c) 15)))
+                (set temp (mul (zext SI (subword HI rm 3)) (zext SI (subword HI rn 3))))
+                (set result3 (saturate HI 16 (sra (add temp c) 15)))
+                (set rd (-join-hi result3 result2 result1 result0))))
+
+(dshmi mmulhiwl "Multimedia multiply higher halves (word to long)"
+       ()
+       "mmulhi.wl $rm, $rn, $rd"
+       (+ (f-op 19) rm (f-ext 14) rn rd (f-rsvd 0))
+       (sequence ((SI result1) (SI result0))
+                (set result0 (mul (zext SI (subword HI rm 2)) (zext SI (subword HI rn 2))))
+                (set result1 (mul (zext SI (subword HI rm 3)) (zext SI (subword HI rn 3))))
+                (set rd (-join-si result1 result0))))
+
+(dshmi mmullowl "Multimedia multiply lower halves (word to long)"
+       ()
+       "mmullo.wl $rm, $rn, $rd"
+       (+ (f-op 19) rm (f-ext 10) rn rd (f-rsvd 0))
+       (sequence ((SI result1) (SI result0))
+                (set result0 (mul (zext SI (subword HI rm 0)) (zext SI (subword HI rn 0))))
+                (set result1 (mul (zext SI (subword HI rm 1)) (zext SI (subword HI rn 1))))
+                (set rd (-join-si result1 result0))))
+
+(dshmi mmulsumwq "Multimedia multiply and accumulate (word to quad)"
+       ()
+       "mmulsum.wq $rm, $rn, $rd"
+       (+ (f-op 18) rm (f-ext 9) rn rd (f-rsvd 0))
+       (sequence ((DI acc))
+                (set acc (mul SI (zext SI (subword HI rm 0)) (zext SI (subword HI rn 0))))
+                (set acc (add acc (mul SI (zext SI (subword HI rm 1)) (zext SI (subword HI rn 1)))))
+                (set acc (add acc (mul SI (zext SI (subword HI rm 2)) (zext SI (subword HI rn 2)))))
+                (set acc (add acc (mul SI (zext SI (subword HI rm 3)) (zext SI (subword HI rn 3)))))
+                (set rd (add rd acc))))
+
+(dshmi movi "Move immediate"
+       ()
+       "movi $imm16, $rd"
+       (+ (f-op 51) imm16 rd (f-rsvd 0))
+       (set rd (ext DI imm16)))
+
+(dshmi mpermw "Multimedia permutate word"
+       ()
+       "mperm.w $rm, $rn, $rd"
+       (+ (f-op 10) rm (f-ext 13) rn rd (f-rsvd 0))
+       (sequence ((QI control) (HI result3) (HI result2) (HI result1) (HI result0))
+                (set control (and QI rn #x3f))
+                (set result0 (subword HI rm (sub 3 (and control 3))))
+                (set result1 (subword HI rm (sub 3 (and (srl control 2) 3))))
+                (set result2 (subword HI rm (sub 3 (and (srl control 4) 3))))
+                (set result3 (subword HI rm (sub 3 (and (srl control 6) 3))))
+                (set rd (-join-hi result3 result2 result1 result0))))
+
+(dshmi msadubq "Multimedia absolute difference (byte)"
+       ()
+       "msad.ubq $rm, $rn, $rd"
+       (+ (f-op 18) rm (f-ext 0) rn rd (f-rsvd 0))
+       (sequence ((DI acc))
+                (set acc (abs DI (sub (subword QI rm 0) (subword QI rn 1))))
+                (set acc (add DI acc (abs (sub (subword QI rm 1) (subword QI rn 1)))))
+                (set acc (add DI acc (abs (sub (subword QI rm 2) (subword QI rn 2)))))
+                (set acc (add DI acc (abs (sub (subword QI rm 3) (subword QI rn 3)))))
+                (set acc (add DI acc (abs (sub (subword QI rm 4) (subword QI rn 4)))))
+                (set acc (add DI acc (abs (sub (subword QI rm 5) (subword QI rn 5)))))
+                (set acc (add DI acc (abs (sub (subword QI rm 6) (subword QI rn 6)))))
+                (set acc (add DI acc (abs (sub (subword QI rm 7) (subword QI rn 7)))))
+                (set rd (add rd acc))))
+
+(define-pmacro (-mshaldsl arg) (saturate SI 32 (sll arg (and rn 31))))
+(dshmi mshaldsl "Multimedia saturating arithmetic left shift (long word)"
+       ()
+       "mshalds.l $rm, $rn, $rd"
+       (+ (f-op 3) rm (f-ext 6) rn rd (f-rsvd 0))
+       (slice-long-unop -mshaldsl))
+
+(define-pmacro (-mshaldsw arg) (saturate HI 16 (sll arg (and rn 15))))
+(dshmi mshaldsw "Multimedia saturating arithmetic left shift (word)"
+       ()
+       "mshalds.w $rm, $rn, $rd"
+       (+ (f-op 3) rm (f-ext 5) rn rd (f-rsvd 0))
+       (slice-word-unop -mshaldsw))
+
+(define-pmacro (-mshardl arg) (sra arg (and rn 31)))
+(dshmi mshardl "Multimedia arithmetic right shift (long)"
+       ()
+       "mshard.l $rm, $rn, $rd"
+       (+ (f-op 3) rm (f-ext 10) rn rd (f-rsvd 0))
+       (slice-long-unop -mshardl))
+
+(define-pmacro (-mshardw arg) (sra arg (and rn 15)))
+(dshmi mshardw "Multimedia arithmetic right shift (word)"
+       ()
+       "mshard.w $rm, $rn, $rd"
+       (+ (f-op 3) rm (f-ext 9) rn rd (f-rsvd 0))
+       (slice-word-unop -mshardw))
+
+(dshmi mshardsq "Multimedia saturating arithmetic right shift (quad word)"
+       ()
+       "mshards.q $rm, $rn, $rd"
+       (+ (f-op 3) rm (f-ext 11) rn rd (f-rsvd 0))
+       (set rd (saturate DI 16 (sra rm (and rn 63)))))
+
+(dshmi mshfhib "Multimedia shuffle higher-half (byte)"
+       ()
+       "mshfhi.b $rm, $rn, $rd"
+       (+ (f-op 11) rm (f-ext 4) rn rd (f-rsvd 0))
+       (sequence ((QI result7) (QI result6) (QI result5) (QI result4)
+                 (QI result3) (QI result2) (QI result1) (QI result0))
+                (set result0 (subword QI rm 4))
+                (set result1 (subword QI rn 4))
+                (set result2 (subword QI rm 5))
+                (set result3 (subword QI rn 5))
+                (set result4 (subword QI rm 6))
+                (set result5 (subword QI rn 6))
+                (set result6 (subword QI rm 7))
+                (set result7 (subword QI rn 7))
+                (set rd (-join-qi result7 result6 result5 result4 result3
+                                result2 result1 result0))))
+
+(dshmi mshfhil "Multimedia shuffle higher-half (long)"
+       ()
+       "mshfhi.l $rm, $rn, $rd"
+       (+ (f-op 11) rm (f-ext 6) rn rd (f-rsvd 0))
+       (sequence ((SI result1) (SI result0))
+                (set result0 (subword SI rm 1))
+                (set result1 (subword SI rn 1))
+                (set rd (-join-si result1 result0))))
+
+(dshmi mshfhiw "Multimedia shuffle higher-half (word)"
+       ()
+       "mshfhi.w $rm, $rn, $rd"
+       (+ (f-op 11) rm (f-ext 5) rn rd (f-rsvd 0))
+       (sequence ((HI result3) (HI result2) (HI result1) (HI result0))
+                (set result0 (subword HI rm 2))
+                (set result1 (subword HI rn 2))
+                (set result2 (subword HI rm 3))
+                (set result3 (subword HI rn 3))
+                (set rd (-join-hi result3 result2 result1 result0))))
+
+(dshmi mshflob "Multimedia shuffle lower-half (byte)"
+       ()
+       "mshflo.b $rm, $rn, $rd"
+       (+ (f-op 11) rm (f-ext 0) rn rd (f-rsvd 0))
+       (sequence ((QI result7) (QI result6) (QI result5) (QI result4)
+                 (QI result3) (QI result2) (QI result1) (QI result0))
+                (set result0 (subword QI rm 0))
+                (set result1 (subword QI rn 0))
+                (set result2 (subword QI rm 1))
+                (set result3 (subword QI rn 1))
+                (set result4 (subword QI rm 2))
+                (set result5 (subword QI rn 2))
+                (set result6 (subword QI rm 3))
+                (set result7 (subword QI rn 3))
+                (set rd (-join-qi result7 result6 result5 result4 result3
+                                result2 result1 result0))))
+
+(dshmi mshflol "Multimedia shuffle lower-half (long)"
+       ()
+       "mshflo.l $rm, $rn, $rd"
+       (+ (f-op 11) rm (f-ext 2) rn rd (f-rsvd 0))
+       (sequence ((SI result1) (SI result0))
+                (set result0 (subword SI rm 0))
+                (set result1 (subword SI rn 0))
+                (set rd (-join-si result1 result0))))
+
+(dshmi mshflow "Multimedia shuffle lower-half (word)"
+       ()
+       "mshflo.w $rm, $rn, $rd"
+       (+ (f-op 11) rm (f-ext 1) rn rd (f-rsvd 0))
+       (sequence ((HI result3) (HI result2) (HI result1) (HI result0))
+                (set result0 (subword HI rm 0))
+                (set result1 (subword HI rn 0))
+                (set result2 (subword HI rm 1))
+                (set result3 (subword HI rn 1))
+                (set rd (-join-hi result3 result2 result1 result0))))
+
+(define-pmacro (-mshlldl arg) (sll arg (and rn 31)))
+(dshmi mshlldl "Multimedia logical left shift (long word)"
+       ()
+       "mshlld.l $rm, $rn, $rd"
+       (+ (f-op 3) rm (f-ext 2) rn rd (f-rsvd 0))
+       (slice-long-unop -mshlldl))
+
+(define-pmacro (-mshlldw arg) (sll arg (and rn 15)))
+(dshmi mshlldw "Multimedia logical left shift (word)"
+       ()
+       "mshlld.w $rm, $rn, $rd"
+       (+ (f-op 3) rm (f-ext 1) rn rd (f-rsvd 0))
+       (slice-word-unop -mshlldw))
+
+(define-pmacro (-mshlrdl arg) (srl arg (and rn 31)))
+(dshmi mshlrdl "Multimedia logical right shift (long word)"
+       ()
+       "mshlrd.l $rm, $rn, $rd"
+       (+ (f-op 3) rm (f-ext 14) rn rd (f-rsvd 0))
+       (slice-long-unop -mshlrdl))
+
+(define-pmacro (-mshlrdw arg) (srl arg (and rn 15)))
+(dshmi mshlrdw "Multimedia logical right shift (word)"
+       ()
+       "mshlrd.w $rm, $rn, $rd"
+       (+ (f-op 3) rm (f-ext 13) rn rd (f-rsvd 0))
+       (slice-word-unop -mshlrdw))
+
+(dshmi msubl "Multimedia subtract (long word)"
+       ()
+       "msub.l $rm, $rn, $rd"
+       (+ (f-op 2) rm (f-ext 10) rn rd (f-rsvd 0))
+       (slice-long sub))
+
+(dshmi msubw "Multimedia add (word)"
+       ()
+       "msub.w $rm, $rn, $rd"
+       (+ (f-op 2) rm (f-ext 9) rn rd (f-rsvd 0))
+       (slice-word sub))
+
+(define-pmacro (-msubsl arg1 arg2) (saturate SI 32 (sub arg1 arg2)))
+(dshmi msubsl "Multimedia subtract (saturating long)"
+       ()
+       "msubs.l $rm, $rn, $rd"
+       (+ (f-op 2) rm (f-ext 14) rn rd (f-rsvd 0))
+       (slice-long -msubsl))
+
+(define-pmacro (-msubsub arg1 arg2) (usaturate QI 8 (sub arg1 arg2)))
+(dshmi msubsub "Multimedia subtract (saturating byte)"
+       ()
+       "msubs.ub $rm, $rn, $rd"
+       (+ (f-op 2) rm (f-ext 12) rn rd (f-rsvd 0))
+       (slice-byte -msubsub))
+
+(define-pmacro (-msubsw arg1 arg2) (saturate HI 16 (sub arg1 arg2)))
+(dshmi msubsw "Multimedia subtract (saturating word)"
+       ()
+       "msubs.w $rm, $rn, $rd"
+       (+ (f-op 2) rm (f-ext 13) rn rd (f-rsvd 0))
+       (slice-byte -msubsw))
+
+(dshmi mulsl "Multiply signed long"
+       ()
+       "muls.l $rm, $rn, $rd"
+       (+ (f-op 1) rm (f-ext 14) rn rd (f-rsvd 0))
+       (set rd (mul (ext DI (subword SI rm 1)) (ext DI (subword SI rn 1)))))
+
+(dshmi mulul "Multiply unsigned long"
+       ()
+       "mulu.l $rm, $rn, $rd"
+       (+ (f-op 0) rm (f-ext 14) rn rd (f-rsvd 0))
+       (set rd (mul (zext DI (subword SI rm 1)) (zext DI (subword SI rn 1)))))
+
+(dshmi nop "No operation"
+       ()
+       "nop"
+       (+ (f-op 27) (f-left 63) (f-ext 0) (f-right 63) (f-dest 63) (f-rsvd 0))
+       (nop))
+
+(dshmi nsb "Number of consecutive sign bits"
+       ()
+       "nsb $rm, $rd"
+       (+ (f-op 0) rm (f-ext 13) (f-right 63) rd (f-rsvd 0))
+       ; Semantics requires a loop construct, so punt to C.
+       (set rd (c-call DI "sh64_nsb" rm)))
+
+(dshmi ocbi "Invalidate operand cache block"
+       ()
+       "ocbi $rm, $disp6x32"
+       (+ (f-op 56) rm (f-ext 9) disp6x32 (f-dest 63) (f-rsvd 0))
+       (unimp "ocbi"))
+
+(dshmi ocbp "Purge operand cache block"
+       ()
+       "ocbp $rm, $disp6x32"
+       (+ (f-op 56) rm (f-ext 8) disp6x32 (f-dest 63) (f-rsvd 0))
+       (unimp "ocbp"))
+
+(dshmi ocbwb "Write-back operand cache block"
+       ()
+       "ocbwb $rm, $disp6x32"
+       (+ (f-op 56) rm (f-ext 12) disp6x32 (f-dest 63) (f-rsvd 0))
+       (unimp "ocbwb"))
+
+(dshmi or "OR"
+       ()
+       "or $rm, $rn, $rd"
+       (+ (f-op 1) rm (f-ext 9) rn rd (f-rsvd 0))
+       (set rd (or rm rn)))
+
+(dshmi ori "OR immediate"
+       ()
+       "ori $rm, $imm10, $rd"
+       (+ (f-op 55) rm imm10 rd (f-rsvd 0))
+       (set rd (or rm (ext DI imm10))))
+
+(dshmi prefi "Prefetch instruction"
+       ()
+       "prefi $rm, $disp6x32"
+       (+ (f-op 56) rm (f-ext 1) disp6x32 (f-right 63) (f-rsvd 0))
+       (unimp "prefi"))
+
+(dshmi pta "Prepare target register for SHmedia target"
+       ()
+       "pta$likely $disp16, $tra"
+       (+ (f-op 58) disp16 likely (f-8-2 0) tra (f-rsvd 0))
+       (set tra (add disp16 1)))
+
+(dshmi ptabs "Prepare target register with absolute value from register"
+       ()
+       "ptabs$likely $rn, $tra"
+       (+ (f-op 26) (f-left 63) (f-ext 1) rn likely (f-8-2 0) tra (f-rsvd 0))
+       (set tra rn))
+
+(dshmi ptb "Prepare target register for SHcompact target"
+       ()
+       "ptb$likely $disp16, $tra"
+       (+ (f-op 59) disp16 likely (f-8-2 0) tra (f-rsvd 0))
+       (set tra disp16))
+
+(dshmi ptrel "Prepare target register with relative value from register"
+       ()
+       "ptrel$likely $rn, $tra"
+       (+ (f-op 26) (f-left 63) (f-ext 5) rn likely (f-8-2 0) tra (f-rsvd 0))
+       (set tra (add pc rn)))
+
+(dshmi putcfg "Put configuration register"
+       ()
+       "putcfg $rm, $disp6, $rd"
+       (+ (f-op 56) rm (f-ext 15) disp6 rd (f-rsvd 0))
+       (unimp "putcfg"))
+
+(dshmi putcon "Put control register"
+       ()
+       "putcon $rm, $crj"
+       (+ (f-op 27) rm (f-ext 15) (f-right 63) crj (f-rsvd 0))
+       (set crj rm))
+
+(dshmi rte "Return from exception"
+       ()
+       "rte"
+       (+ (f-op 27) (f-left 63) (f-ext 3) (f-right 63) (f-dest 63) (f-rsvd 0))
+       (unimp "rte"))
+
+(dshmi shard "Arithmetic right shift"
+       ()
+       "shard $rm, $rn, $rd"
+       (+ (f-op 1) rm (f-ext 7) rn rd (f-rsvd 0))
+       (set rd (sra rm (and rn 63))))
+
+(dshmi shardl "Arithmetic right shift (long word)"
+       ()
+       "shard.l $rm, $rn, $rd"
+       (+ (f-op 1) rm (f-ext 6) rn rd (f-rsvd 0))
+       (set rd (ext DI (sra (subword SI rm 1) (and rn 63)))))
+
+(dshmi shari "Arithmetic right shift (immediate count)"
+       ()
+       "shari $rm, $uimm6, $rd"
+       (+ (f-op 49) rm (f-ext 7) uimm6 rd (f-rsvd 0))
+       (set rd (sra rm uimm6)))
+
+(dshmi sharil "Arithmetic right shift (long word, immediate count)"
+       ()
+       "shari.l $rm, $uimm6, $rd"
+       (+ (f-op 49) rm (f-ext 6) uimm6 rd (f-rsvd 0))
+       (set rd (ext DI (sra (subword SI rm 1) (and uimm6 63)))))
+
+(dshmi shlld "Logical left shift"
+       ()
+       "shlld $rm, $rn, $rd"
+       (+ (f-op 1) rm (f-ext 1) rn rd (f-rsvd 0))
+       (set rd (sll rm (and rn 63))))
+
+(dshmi shlldl "Logical left shift (long word)"
+       ()
+       "shlld.l $rm, $rn, $rd"
+       (+ (f-op 1) rm (f-ext 0) rn rd (f-rsvd 0))
+       (set rd (ext DI (sll (subword SI rm 1) (and rn 63)))))
+
+(dshmi shlli "Logical left shift (immediate count)"
+       ()
+       "shlli $rm, $uimm6, $rd"
+       (+ (f-op 49) rm (f-ext 1) uimm6 rd (f-rsvd 0))
+       (set rd (sll rm uimm6)))
+
+(dshmi shllil "Logical left shift (long word, immediate count)"
+       ()
+       "shlli.l $rm, $uimm6, $rd"
+       (+ (f-op 49) rm (f-ext 0) uimm6 rd (f-rsvd 0))
+       (set rd (ext DI (sll (subword SI rm 1) (and uimm6 63)))))
+
+(dshmi shlrd "Logical right shift"
+       ()
+       "shlrd $rm, $rn, $rd"
+       (+ (f-op 1) rm (f-ext 3) rn rd (f-rsvd 0))
+       (set rd (srl rm (and rn 63))))
+
+(dshmi shlrdl "Logical right shift (long word)"
+       ()
+       "shlrd.l $rm, $rn, $rd"
+       (+ (f-op 1) rm (f-ext 2) rn rd (f-rsvd 0))
+       (set rd (ext DI (srl (subword SI rm 1) (and rn 63)))))
+
+(dshmi shlri "Logical right shift (immediate count)"
+       ()
+       "shlri $rm, $uimm6, $rd"
+       (+ (f-op 49) rm (f-ext 3) uimm6 rd (f-rsvd 0))
+       (set rd (srl rm uimm6)))
+
+(dshmi shlril "Logical right shift (long word, immediate count)"
+       ()
+       "shlri.l $rm, $uimm6, $rd"
+       (+ (f-op 49) rm (f-ext 2) uimm6 rd (f-rsvd 0))
+       (set rd (ext DI (srl (subword SI rm 1) (and uimm6 63)))))
+
+(dshmi shori "Shift-or immediate"
+       ()
+       "shori $uimm16, $rd"
+       (+ (f-op 50) uimm16 rd (f-rsvd 0))
+       (set rd (or (sll rd 16) (zext DI uimm16))))
+
+(dshmi sleep "Sleep"
+       ()
+       "sleep"
+       (+ (f-op 27) (f-left 63) (f-ext 7) (f-right 63) (f-dest 63) (f-rsvd 0))
+       (unimp "sleep"))
+
+(dshmi stb "Store byte"
+       ()
+       "st.b $rm, $disp10, $rd"
+       (+ (f-op 40) rm disp10 rd (f-rsvd 0))
+       (set (mem UQI (add rm (ext DI disp10))) (and QI rd #xff)))
+
+(dshmi stl "Store long word"
+       ()
+       "st.l $rm, $disp10x4, $rd"
+       (+ (f-op 42) rm disp10x4 rd (f-rsvd 0))
+       (set (mem SI (add rm (ext DI disp10x4))) (and SI rd #xffffffff)))
+
+(dshmi stq "Store quad word"
+       ()
+       "st.q $rm, $disp10x8, $rd"
+       (+ (f-op 43) rm disp10x8 rd (f-rsvd 0))
+       (set (mem DI (add rm (ext DI disp10x8))) rd))
+
+(dshmi stw "Store word"
+       ()
+       "st.w $rm, $disp10x2, $rd"
+       (+ (f-op 41) rm disp10x2 rd (f-rsvd 0))
+       (set (mem HI (add rm (ext DI disp10x2))) (and HI rd #xffff)))
+
+(define-pmacro (-sthi-byte)
+  (sequence ()
+           (set (mem UQI addr) (and QI val #xff))
+           (set val (srl val 8))
+           (set addr (add addr 1))))
+
+(dshmi sthil "Store high part (long word)"
+      ()
+       "sthi.l $rm, $disp6, $rd"
+       (+ (f-op 56) rm (f-ext 6) disp6 rd (f-rsvd 0))
+       (sequence ((DI addr) (QI bytecount) (DI val))
+                (set addr (add rm disp6))
+                (set bytecount (add (and addr 3) 1))
+                (if endian
+                    (set val rd)
+                    (set val (srl rd (sub 32 (mul 8 bytecount)))))
+                (set addr (add (sub addr bytecount) 1))
+                (if (gt bytecount 3)
+                    (-sthi-byte))
+                (if (gt bytecount 2)
+                    (-sthi-byte))
+                (if (gt bytecount 1)
+                    (-sthi-byte))
+                (if (gt bytecount 0)
+                    (-sthi-byte))))
+
+(dshmi sthiq "Store high part (quad word)"
+       ()
+       "sthi.q $rm, $disp6, $rd"
+       (+ (f-op 56) rm (f-ext 7) disp6 rd (f-rsvd 0))
+       (sequence ((DI addr) (QI bytecount) (DI val))
+                (set addr (add rm disp6))
+                (set bytecount (add (and addr 7) 1))
+                (if endian
+                    (set val rd)
+                    (set val (srl rd (sub 64 (mul 8 bytecount)))))
+                (set addr (add (sub addr bytecount) 1))
+                (if (gt bytecount 7)
+                    (-sthi-byte))
+                (if (gt bytecount 6)
+                    (-sthi-byte))
+                (if (gt bytecount 5)
+                    (-sthi-byte))
+                (if (gt bytecount 4)
+                    (-sthi-byte))
+                (if (gt bytecount 3)
+                    (-sthi-byte))
+                (if (gt bytecount 2)
+                    (-sthi-byte))
+                (if (gt bytecount 1)
+                    (-sthi-byte))
+                (if (gt bytecount 0)
+                    (-sthi-byte))))
+
+(dshmi stlol "Store low part (long word)"
+       ()
+       "stlo.l $rm, $disp6, $rd"
+       (+ (f-op 56) rm (f-ext 2) disp6 rd (f-rsvd 0))
+       ; FIXME.
+       (unimp "stlol"))
+
+(dshmi stloq "Store low part (quad word)"
+       ()
+       "stlo.q $rm, $disp6, $rd"
+       (+ (f-op 56) rm (f-ext 3) disp6 rd (f-rsvd 0))
+       ; FIXME.
+       (unimp "stloq"))
+
+(dshmi stxb "Store byte (extended displacement)"
+       ()
+       "stx.b $rm, $rn, $rd"
+       (+ (f-op 24) rm (f-ext 0) rn rd (f-rsvd 0))
+       (set (mem UQI (add rm rn)) (subword QI rd 7)))
+
+(dshmi stxl "Store long (extended displacement)"
+       ()
+       "stx.l $rm, $rn, $rd"
+       (+ (f-op 24) rm (f-ext 2) rn rd (f-rsvd 0))
+       (set (mem SI (add rm rn)) (subword SI rd 1)))
+
+(dshmi stxq "Store quad word (extended displacement)"
+       ()
+       "stx.q $rm, $rn, $rd"
+       (+ (f-op 24) rm (f-ext 3) rn rd (f-rsvd 0))
+       (set (mem DI (add rm rn)) rd))
+
+(dshmi stxw "Store word (extended displacement)"
+       ()
+       "stx.w $rm, $rn, $rd"
+       (+ (f-op 24) rm (f-ext 1) rn rd (f-rsvd 0))
+       (set (mem HI (add rm rn)) (subword HI rd 3)))
+
+(dshmi sub "Subtract"
+       ()
+       "sub $rm, $rn, $rd"
+       (+ (f-op 0) rm (f-ext 11) rn rd (f-rsvd 0))
+       (set rd (sub rm rn)))
+
+(dshmi subl "Subtract long"
+       ()
+       "sub.l $rm, $rn, $rd"
+       (+ (f-op 0) rm (f-ext 10) rn rd (f-rsvd 0))
+       (set rd (ext DI (sub (subword SI rm 1) (subword SI rn 1)))))
+
+(dshmi swapq "Swap quad words"
+       ()
+       "swap.q $rm, $rn, $rd"
+       (+ (f-op 8) rm (f-ext 3) rn rd (f-rsvd 0))
+       (sequence ((DI addr) (DI temp))
+                (set addr (add rm rn))
+                (set temp (mem DI addr))
+                (set (mem DI addr) rd)
+                (set rd temp)))
+
+(dshmi synci "Synchronise instruction fetch"
+       ()
+       "synci"
+       (+ (f-op 27) (f-left 63) (f-ext 2) (f-right 63) (f-dest 63) (f-rsvd 0))
+       (unimp "synci"))
+
+(dshmi synco "Synchronise data operations"
+       ()
+       "synco"
+       (+ (f-op 27) (f-left 63) (f-ext 6) (f-right 63) (f-dest 63) (f-rsvd 0))
+       (unimp "synco"))
+
+(dshmi trapa "Trap"
+       ()
+       "trapa $rm"
+       (+ (f-op 27) rm (f-ext 1) (f-right 63) (f-dest 63) (f-rsvd 0))
+       (c-call "sh64_trapa" rm pc))
+
+(dshmi xor "Exclusive OR"
+       ()
+       "xor $rm, $rn, $rd"
+       (+ (f-op 1) rm (f-ext 13) rn rd (f-rsvd 0))
+       (set rd (xor rm rn)))
+
+(dshmi xori "Exclusive OR immediate"
+       ()
+       "xori $rm, $imm6, $rd"
+       (+ (f-op 49) rm (f-ext 13) rn rd (f-rsvd 0))
+       (set rd (xor rm (ext DI imm6))))

diff --git a/cpu/simplify.inc b/cpu/simplify.inc
new file mode 100644 (file)
index 0000000..808018d
--- /dev/null
+++ b/cpu/simplify.inc
@@ -0,0 +1,218 @@
+; Collection of macros, for GNU Binutils .cpu files. -*- Scheme -*-
+;
+; Copyright 2000, 2007, 2009 Free Software Foundation, Inc.
+;
+; Contributed by Red Hat Inc.
+;
+; This file is part of the GNU Binutils.
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 3 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, write to the Free Software
+; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+; MA 02110-1301, USA.
+\f
+; Enums.
+
+; Define a normal enum without using name/value pairs.
+; This is currently the same as define-full-enum but it needn't remain
+; that way (it's define-full-enum that would change).
+
+(define-pmacro (define-normal-enum name comment attrs prefix vals)
+  "Define a normal enum, fixed number of arguments."
+  (define-full-enum name comment attrs prefix vals)
+)
+
+; Define a normal insn enum.
+
+(define-pmacro (define-normal-insn-enum name comment attrs prefix fld vals)
+  "Define a normal instruction opcode enum."
+  (define-full-insn-enum name comment attrs prefix fld vals)
+)
+\f
+; Instruction fields.
+
+; Normally, fields are unsigned and have no encode/decode needs.
+
+(define-pmacro (define-normal-ifield name comment attrs start length)
+  "Define a normal instruction field."
+  (define-full-ifield name comment attrs start length UINT #f #f)
+)
+
+; For those who don't like typing.
+
+(define-pmacro (df name comment attrs start length mode encode decode)
+  "Shorthand form of normal fields requiring mode, encode/decode."
+  (define-full-ifield name comment attrs start length mode encode decode)
+)
+(define-pmacro dnf
+  "Shorthand form of define-normal-ifield."
+  define-normal-ifield
+)
+
+; Define a normal multi-ifield.
+
+(define-pmacro (define-normal-multi-ifield name comment attrs
+                mode subflds insert extract)
+  "Define a normal multi-part instruction field."
+  (define-full-multi-ifield name comment attrs mode subflds insert extract)
+)
+
+; For those who don't like typing.
+
+(define-pmacro dnmf
+  "Shorthand form of define-normal-multi-ifield."
+  define-normal-multi-ifield
+)
+
+; Simple multi-ifields: mode is UINT, default insert/extract support,
+; default encode/decode support.
+
+(define-pmacro (dsmf name comment attrs subflds)
+  "Define a simple multi-part instruction field."
+  (define-full-multi-ifield name comment attrs UINT subflds #f #f)
+)
+\f
+; Hardware.
+
+; Simpler version for most hardware elements.
+; Allow special assembler support specification but no semantic-name,
+; getter/setter, or layout specs.
+
+(define-pmacro (define-normal-hardware name comment attrs type
+                indices values handlers)
+  "Define a normal hardware element."
+  (define-full-hardware name comment attrs name type
+    indices values handlers () () ())
+)
+
+; For those who don't like typing.
+
+(define-pmacro dnh
+  "Shorthand form of define-normal-hardware."
+  define-normal-hardware
+)
+
+; Simpler version of dnh that leaves out the indices, values, handlers,
+; getter/setter, and layout specs.
+; This is useful for 1 bit registers.
+; ??? While dsh and dnh aren't that distinguishable when perusing a .cpu file,
+; they both take a fixed number of positional arguments, and dsh is a proper
+; subset of dnh with all arguments in the same positions, so methinks things
+; are ok.
+
+(define-pmacro (define-simple-hardware name comment attrs type)
+  "Define a simple hardware element (usually a scalar register)."
+  (define-full-hardware name comment attrs name type () () () () () ())
+)
+
+(define-pmacro dsh
+  "Shorthand form of define-simple-hardware."
+  define-simple-hardware
+)
+\f
+; Operands.
+
+; Simpler version for most operands.
+; Allow special assembler support specification but no handlers or
+; getter/setter specs.
+
+(define-pmacro (define-normal-operand name comment attrs type index)
+  "Define a normal operand."
+  (define-full-operand name comment attrs type DFLT index () () ())
+)
+
+; For those who don't like typing.
+
+(define-pmacro dno
+  "Shorthand form of define-normal-operand."
+  define-normal-operand
+)
+
+; Deprecated, but still in wide use.
+
+(define-pmacro dnop
+  "Shorthand form of define-normal-operand."
+  define-normal-operand
+)
+
+(define-pmacro (dndo x-name x-mode x-args
+                    x-syntax x-base-ifield x-encoding x-ifield-assertion
+                    x-getter x-setter)
+  "Define a normal derived operand."
+  (define-derived-operand
+    (name x-name)
+    (mode x-mode)
+    (args x-args)
+    (syntax x-syntax)
+    (base-ifield x-base-ifield)
+    (encoding x-encoding)
+    (ifield-assertion x-ifield-assertion)
+    (getter x-getter)
+    (setter x-setter)
+    )
+)
+\f
+; Instructions.
+
+; Define an instruction object, normal version.
+; At present all fields must be specified.
+; Fields ifield-assertion is absent.
+
+(define-pmacro (define-normal-insn name comment attrs syntax fmt semantics timing)
+  "Define a normal instruction."
+  (define-full-insn name comment attrs syntax fmt () semantics timing)
+)
+
+; To reduce the amount of typing.
+; Note that this is the same name as the D'ni in MYST.  Oooohhhh.....
+; this must be the right way to go. :-)
+
+(define-pmacro dni
+  "Shorthand form of define-normal-insn."
+  define-normal-insn
+)
+\f
+; Macro instructions.
+
+; Define a macro-insn object, normal version.
+; This only supports expanding to one real insn.
+
+(define-pmacro (define-normal-macro-insn name comment attrs syntax expansion)
+  "Define a normal macro instruction."
+  (define-full-minsn name comment attrs syntax expansion)
+)
+
+; To reduce the amount of typing.
+
+(define-pmacro dnmi
+  "Shorthand form of define-normal-macro-insn."
+  define-normal-macro-insn
+)
+\f
+; Modes.
+; ??? Not currently available for use.
+;
+; Define Normal Mode
+;
+;(define-pmacro (define-normal-mode name comment attrs bits bytes
+;               non-mode-c-type printf-type sem-mode ptr-to host?)
+;  "Define a normal mode.\n"
+;  (define-full-mode name comment attrs bits bytes
+;    non-mode-c-type printf-type sem-mode ptr-to host?)
+;)
+;
+; For those who don't like typing.
+;(define-pmacro dnm
+;  "Shorthand form of define-normal-mode.\n"
+;  define-normal-mode
+;)

diff --git a/cpu/xc16x.cpu b/cpu/xc16x.cpu
new file mode 100644 (file)
index 0000000..efa687d
--- /dev/null
+++ b/cpu/xc16x.cpu
@@ -0,0 +1,3127 @@
+; Infineon XC16X CPU description.  -*- Scheme -*-
+;
+; Copyright 2006, 2007, 2009 Free Software Foundation, Inc.
+;
+; Contributed by KPIT Cummins Infosystems Ltd.; developed under contract 
+; from Infineon Systems, GMBH , Germany.
+;
+; This file is part of the GNU Binutils.
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 3 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, write to the Free Software
+; Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+; 02110-1301, USA.
+
+(define-rtl-version 0 8)
+
+(include "simplify.inc")
+
+; define-arch appears first
+
+(define-arch
+  (name xc16x) ; name of cpu family
+  (comment "Infineon XC16X")
+  (default-alignment aligned)
+  (insn-lsb0? #t)              
+  (machs xc16x)
+  (isas xc16x)
+)
+
+; Attributes.   
+; An attribute to describe which pipeline an insn runs in generally OS.
+(define-attr
+  (for insn)
+  (type enum)
+  (name PIPE)
+  (comment "parallel execution pipeline selection")
+  (values NONE OS)
+)
+
+; Instruction set parameters.
+
+(define-isa
+  (name xc16x)
+  (default-insn-bitsize 32)
+  (base-insn-bitsize 32)
+  (default-insn-word-bitsize 16)
+  (decode-assist (15 14 13 12))
+  ; The XC16X fetches 1 insn at a time.
+  (liw-insns 1)
+  (parallel-insns 1)
+)
+
+; Cpu family definitions.
+
+(define-cpu
+  ; cpu names must be distinct from the architecture name and machine names.
+  ; The "b" suffix stands for "base" and is the convention.
+  ; The "f" suffix stands for "family" and is the convention.
+  (name xc16xbf)
+  (comment "Infineon XC16X base family")
+  (endian little)
+  (insn-chunk-bitsize 32)
+  (word-bitsize 16)
+  (parallel-insns 1)
+)
+
+(define-mach
+  (name xc16x)
+  (comment "Infineon XC16X cpu")
+  (cpu xc16xbf)
+)
+
+; Model descriptions.
+
+(define-model
+  (name xc16x) (comment "XC16X") (attrs)
+  (mach xc16x)
+  
+  (pipeline p-mem "" () ((prefetch) (fetch) (decode) (address) (memory) (execute) (writeback)))
+  
+    ; `state' is a list of variables for recording model state
+    (state
+     ; bit mask of h-gr registers, =1 means value being loaded from memory
+     (h-gr UINT)
+    )
+  
+  (unit u-exec "Execution Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((dr INT -1) (sr INT -1)) ; inputs
+       ((dr INT -1)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-cmp "Compare Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((src1 INT -1) (src2 INT -1)) ; inputs
+       () ; outputs
+       () ; profile action (default)
+       )
+  (unit u-cti "Jump & Call Unit" ()
+       1 1 ; issue done
+       () ; state
+       ((condbit) (sr INT -1)) ; inputs
+       ((pc)) ; outputs
+       () ; profile action (default)
+       )
+  (unit u-mov "Data Movement Unit" ()
+       1 1 ; issue done
+       () ;state
+       ((dr INT -1) (sr INT -1)) ; inputs
+       ((dr INT -1)) ; output
+       () ; profile action (default)
+       )
+ ) 
+ 
+; Instruction fields.
+;
+; Attributes:
+; PCREL-ADDR: pc relative value (for reloc and disassembly purposes)
+; ABS-ADDR: absolute address (for reloc and disassembly purposes)
+; RELOC: there is a relocation associated with this field (experiment)
+
+(define-attr
+  (for ifield operand)
+  (type boolean)
+  (name RELOC)
+  (comment "there is a reloc associated with this field (experiment)")
+)
+
+(dnf f-op1       "op1"                 () 7  4)
+(dnf f-op2       "op2"                 () 3  4)
+(dnf f-condcode  "condcode"            () 7  4)  ;condition code required in other jmps and calls
+(dnf f-icondcode "indrct condcode"     () 15 4)  ;condition code required in other jmpi and calli
+(dnf f-rcond     "relative-cond"       () 7  4)  ;condition code required in JMPR 
+(dnf f-qcond     "qbit"                () 7  4)  ;used in enum of bset/bclear macro
+(dnf f-extccode  "extended condcode"   () 15 5)  ;condition code required in other jmpa and calla
+(dnf f-r0       "r0"                  () 9  2)  ;required where 2 bit register used(only R0-R3)
+(dnf f-r1        "r1"                  () 15 4)
+(dnf f-r2        "r2"                  () 11 4)
+(dnf f-r3        "r3"                  () 12 4)
+(dnf f-r4        "r4"                  () 11 4)
+(dnf f-uimm2     "uimm2"               () 13 2)  ;used for immediate data,eg in ADD,MOV insns
+(dnf f-uimm3     "uimm3"               () 10 3)  ;used for immediate data,eg in ADD,SUB insns
+(dnf f-uimm4     "uimm4"               () 15 4)  ;used for immediate data,eg in MOV insns
+(dnf f-uimm7     "uimm7"               (PCREL-ADDR RELOC) 15 7)        ;used in TRAP
+(dnf f-uimm8     "uimm8"               () 23 8)  ;used in immediate byte data,eg in ADDB,MOVB insns
+(dnf f-uimm16    "uimm16"              () 31 16) ;used for immediate word data
+(dnf f-memory    "memory"              () 31 16) ; used for memory operands 
+(dnf f-memgr8    "memory"             () 31 16) ; memory location of gr
+(dnf f-rel8      "rel8"                (PCREL-ADDR RELOC) 15 8)        ;used in JMPR,CALLR
+(dnf f-relhi8    "relhi8"              (PCREL-ADDR RELOC) 23 8)        ;used in JB,JBC,JNB,JNBS
+(dnf f-reg8      "reg8"                () 15 8)        ;required where 8bit gp register used
+(dnf f-regmem8   "regmem8"             () 15 8) ;required where 8bit register used
+(dnf f-regoff8   "regoff8"             () 15 8)        ;required for offset calc
+(dnf f-reghi8    "reghi8"              () 23 8)        ;required where 8bit register number used
+(dnf f-regb8     "regb8"               () 15 8)        ;required for byte registers RL0,RH0, till RL8,RH8
+(dnf f-seg8      "seg8"                () 15 8) ;used as segment number in JMPS,CALLS
+(dnf f-segnum8   "segnum8"             () 23 8) ;used in EXTS,EXTSR        
+(dnf f-mask8     "mask8"               () 23 8) ;used as mask in BFLDH,BFLDL insns
+(dnf f-pagenum   "page num"            () 25 10);used in EXTP,EXTPR
+(dnf f-datahi8   "datahi8"             () 31 8) ;used for filling with const data
+(dnf f-data8     "data8"               () 23 8) ;used for filling with const data
+(dnf f-offset16  "address offset16"    (ABS-ADDR RELOC) 31 16) ;used in JMPS,JMPA,CALLA,CALLS
+(dnf f-op-bit1   "gap of 1 bit"        () 11 1)        ;used for filling with const data
+(dnf f-op-bit2   "gap of 2 bits"       () 11 2)        ;used for filling with const data
+(dnf f-op-bit4   "gap of 4 bits"       () 11 4) ;used for filling with const data
+(dnf f-op-bit3   "gap of 3 bits"       () 10 3) ;used in CALLA, JMPA
+(dnf f-op-2bit   "gap of 2 bits"       () 10 2) ;used in CALLA
+(dnf f-op-bitone "gap of 1 bit "       () 10 1) ;used in JMPA
+(dnf f-op-onebit "gap of 1 bit "       () 9  1) ;used in JMPA
+(dnf f-op-1bit   "gap of 1 bit "       () 8  1) ;used in JMPA, CALLA
+(dnf f-op-lbit4  "gap of 4 bits"       () 15 4) ;used for filling with const data
+(dnf f-op-lbit2  "gap of 2 bits"       () 15 2) ;used for filling with const data
+(dnf f-op-bit8  "gap of 8 bits"       () 31 8) ;used for filling with const data
+(dnf f-op-bit16         "gap of 16 bits"      () 31 16) ;used for filling with const data
+(dnf f-qbit      "qbit"                () 7  4) ;used in bit field of bset/bclear
+(dnf f-qlobit    "qlobit"              () 31 4) ;used for filling with const data
+(dnf f-qhibit    "qhibit"              () 27 4) ;used for filling with const data
+(dnf f-qlobit2   "qlobit2"             () 27 2) ;used for filling with const data
+(dnf f-pof    "upof16"                 () 31 16) ; used for memory operands 
+
+; Enums.
+; insn-op1: bits 0-3
+(define-normal-insn-enum insn-op1 "insn format enums" () OP1_ f-op1
+  ("0" "1" "2" "3" "4" "5" "6" "7"
+   "8" "9" "10" "11" "12" "13" "14" "15")
+)
+
+; insn-op2: bits 4-7
+(define-normal-insn-enum insn-op2 "op2 enums" () OP2_ f-op2
+  ("0" "1" "2" "3" "4" "5" "6" "7"
+   "8" "9" "10" "11" "12" "13" "14" "15")
+)
+
+;/*for bclr/bset*/
+; insn-rcond: bits 0-3
+(define-normal-insn-enum insn-qcond "bit set/clear enums" () QBIT_ f-qcond
+  (("0" 0) ("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5) ("6" 6) ("7" 7) ("8" 8) ("9" 9) ("10" 10) 
+   ("11" 11) ("12" 12) ("13" 13) ("14" 14) ("15" 15))
+)
+;/************/
+; insn-rcond: bits 0-3
+(define-normal-insn-enum insn-rcond "relative jump condition code op2 enums" () COND_ f-rcond
+  (("UC" 0) ("NET" 1) ("Z" 2) ("NE_NZ" 3) ("V" 4)  ("NV" 5) ("N" 6) ("NN" 7)
+   ("C" 8) ("NC" 9) ("SGT" 10) ("SLE" 11) ("SLT" 12) ("SGE" 13) ("UGT" 14) ("ULE" 15)
+   ("EQ" 2) ("NE" 3) ("ULT" 8) ("UGE" 9))
+)
+
+
+
+; Hardware pieces.
+; These entries list the elements of the raw hardware.
+; They're also used to provide tables and other elements of the assembly
+; language.
+
+(dnh h-pc "program counter" (PC) (pc) () () ())
+
+(define-keyword
+  (name gr-names)
+  (enum-prefix H-GR-)
+  (values (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7)
+         (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15))
+
+)
+(define-hardware
+  (name h-gr)
+  (comment "general registers")
+  (attrs PROFILE CACHE-ADDR)
+  (type register HI (16))
+  (indices extern-keyword gr-names)
+)
+
+;; HACK: Various semantics refer to h-cr.
+;; This is here to keep things working.
+(define-hardware
+  (name h-cr)
+  (comment "cr registers")
+  (attrs PROFILE CACHE-ADDR)
+  (type register HI (16))
+  (indices extern-keyword gr-names)
+)
+
+(define-keyword
+  (name ext-names)
+  (enum-prefix H-EXT-)
+  (values (0x1 0) (0x2 1) (0x3 2) (0x4 3)
+          ("1" 0) ("2" 1) ("3" 2) ("4" 3))
+
+)
+
+(define-hardware
+  (name h-ext)
+  (comment "ext values")
+  (attrs PROFILE CACHE-ADDR)
+  (type register HI (8))
+  (indices extern-keyword ext-names)
+)
+
+(define-keyword
+  (name psw-names)
+  (enum-prefix H-PSW-)
+  (values ("IEN" 136) ("r0.11" 240) ("r1.11" 241) ("r2.11" 242) ("r3.11" 243) ("r4.11" 244)
+                      ("r5.11" 245) ("r6.11" 246) ("r7.11" 247) ("r8.11" 248)
+                      ("r9.11" 249) ("r10.11" 250) ("r11.11" 251) ("r12.11" 252)
+                      ("r13.11" 253) ("r14.11" 254) ("r15.11" 255))
+)
+
+(define-hardware
+  (name h-psw)
+  (comment "ext values")
+  (attrs PROFILE CACHE-ADDR)
+  (type register HI (1))
+  (indices extern-keyword psw-names)
+)
+
+(define-keyword
+  (name grb-names)
+  (enum-prefix H-GRB-)
+  (values (rl0 0) (rh0 1) (rl1 2) (rh1 3) (rl2 4) (rh2 5) (rl3 6) (rh3 7) 
+          (rl4 8) (rh4 9) (rl5 10) (rh5 11) (rl6 12) (rh6 13) (rl7 14) (rh7 15))
+)
+
+(define-hardware
+  (name h-grb)
+  (comment "general registers")
+  (attrs PROFILE CACHE-ADDR)
+  (type register QI (16))
+  (indices extern-keyword grb-names)
+)
+
+(define-keyword
+  (name conditioncode-names)
+  (enum-prefix H-CC-)
+  (values (cc_UC 0) (cc_NET 1) (cc_Z 2) (cc_EQ 2) (cc_NZ 3) (cc_NE 3) (cc_V 4) (cc_NV 5) (cc_N 6)  (cc_NN 7) (cc_ULT 8)  (cc_UGE 9) 
+         (cc_C 8) (cc_NC 9) (cc_SGT 10) (cc_SLE 11) (cc_SLT 12) (cc_SGE 13) (cc_UGT 14) 
+          (cc_ULE 15))
+)
+(define-hardware
+  (name h-cc)
+  (comment "condition codes")
+  (attrs PROFILE CACHE-ADDR)
+  (type register QI (16))
+  (indices extern-keyword conditioncode-names)
+)
+
+(define-keyword
+  (name extconditioncode-names)
+  (enum-prefix H-ECC-)
+  (values(cc_UC 0) (cc_NET 2) (cc_Z 4) (cc_EQ 4) (cc_NZ 6) (cc_NE 6) (cc_V 8) (cc_NV 10) (cc_N 12)  (cc_NN 14) (cc_ULT 16)  (cc_UGE 18) (cc_C 16) (cc_NC 18) (cc_SGT 20) 
+         (cc_SLE 22) (cc_SLT 24) (cc_SGE 26) (cc_UGT 28) (cc_ULE 30) (cc_nusr0 1) 
+         (cc_nusr1 3) (cc_usr0 5) (cc_usr1 7))
+)
+(define-hardware
+  (name h-ecc)
+  (comment "extended condition codes")
+  (attrs PROFILE CACHE-ADDR)
+  (type register QI (4))
+  (indices extern-keyword extconditioncode-names)
+)
+
+(define-keyword
+  (name grb8-names)
+  (enum-prefix H-GRB8-)
+  (values (dpp0 0)  (dpp1 1)  (dpp2 2)  (dpp3 3)
+         (psw 136)   (cp 8)    (mdl 7)   (mdh  6)
+         (mdc 135)   (sp 9)    (csp 4)  (vecseg 137)
+          (stkov 10)  (stkun 11) (cpucon1 12) (cpucon2 13)
+         (zeros 142)  (ones 143) (spseg 134) (tfr 214)
+         (rl0 240) (rh0 241) (rl1 242) (rh1 243) (rl2 244) (rh2 245) (rl3 246) (rh3 247)
+         (rl4 248) (rh4 249) (rl5 250) (rh5 251) (rl6 252) (rh6 253) (rl7 254) (rh7 255))
+)
+
+(define-hardware
+  (name h-grb8)
+  (comment "general byte registers")
+  (attrs PROFILE CACHE-ADDR)
+  (type register QI (36))
+  (indices extern-keyword grb8-names)
+)
+
+(define-keyword
+  (name r8-names)
+  (enum-prefix H-R8-)
+  (values (dpp0 0)  (dpp1 1)  (dpp2 2)  (dpp3 3)
+         (psw 136)   (cp 8)    (mdl 7)   (mdh  6)
+         (mdc 135)   (sp 9)    (csp 4)  (vecseg 137)
+          (stkov 10)  (stkun 11) (cpucon1 12) (cpucon2 13)
+         (zeros 142)  (ones 143) (spseg 134) (tfr 214)
+         (r0 240) (r1 241) (r2 242) (r3 243) (r4 244) (r5 245) (r6 246) (r7 247)
+         (r8 248) (r9 249) (r10 250) (r11 251) (r12 252) (r13 253) (r14 254) (r15 255))
+)
+
+(define-hardware
+  (name h-r8)
+  (comment "registers")
+  (attrs PROFILE CACHE-ADDR)
+  (type register HI (36))
+  (indices extern-keyword r8-names)
+)
+
+(define-keyword
+  (name regmem8-names)
+  (enum-prefix H-REGMEM8-)
+  (values (dpp0 0)  (dpp1 1)  (dpp2 2)  (dpp3 3)
+         (psw 136)   (cp 8)    (mdl 7)   (mdh  6)
+         (mdc 135)   (sp 9)    (csp 4)  (vecseg 137)
+          (stkov 10)  (stkun 11) (cpucon1 12) (cpucon2 13)
+         (zeros 142)  (ones 143) (spseg 134) (tfr 214)
+         (r0 240) (r1 241) (r2 242) (r3 243) (r4 244) (r5 245) (r6 246) (r7 247)
+         (r8 248) (r9 249) (r10 250) (r11 251) (r12 252) (r13 253) (r14 254) (r15 255))
+)
+
+(define-hardware
+  (name h-regmem8)
+  (comment "registers")
+  (attrs )
+  (type register HI (16))
+  (indices extern-keyword regmem8-names)
+)
+
+(define-keyword
+  (name regdiv8-names)
+  (enum-prefix H-REGDIV8-)
+  (values (r0 0) (r1 17) (r2 34) (r3 51) (r4 68) (r5 85) (r6 102) (r7 119)
+         (r8 136) (r9 153) (r10 170) (r11 187) (r12 204) (r13 221) (r14 238) (r15 255))
+)
+
+(define-hardware
+  (name h-regdiv8)
+  (comment "division insn registers")
+  (attrs PROFILE CACHE-ADDR)
+  (type register HI (16))
+  (indices extern-keyword regdiv8-names)
+)
+
+(define-keyword
+  (name reg0-name)
+  (enum-prefix H-REG0-)
+  (values (0x1 1) (0x2 2) (0x3 3) (0x4 4) (0x5 5) (0x6 6) (0x7 7) (0x8 8) (0x9 9) (0xa 10) (0xb 11) 
+          (0xc 12) (0xd 13) (0xe 14) (0xf 15)
+          ("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5) ("6" 6) ("7" 7) ("8" 8) ("9" 9) ("10" 10) ("11" 11) 
+          ("12" 12) ("13" 13) ("14" 14) ("15" 15))
+)
+
+(define-hardware
+  (name h-r0)
+  (comment "for 4-bit data excuding 0")
+  (attrs PROFILE CACHE-ADDR)
+  (type register HI (30))
+  (indices extern-keyword reg0-name)
+)
+
+(define-keyword
+  (name reg0-name1)
+  (enum-prefix H-REG01-)
+  (values (0x1 1) (0x2 2) (0x3 3) (0x4 4) (0x5 5) (0x6 6) (0x7 7)
+          ("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5) ("6" 6) ("7" 7))
+)
+
+(define-hardware
+  (name h-r01)
+  (comment "for 4-bit data excuding 0")
+  (attrs PROFILE CACHE-ADDR)
+  (type register HI (14))
+  (indices extern-keyword reg0-name1)
+)
+
+(define-keyword
+  (name regbmem8-names)
+  (enum-prefix H-REGBMEM8-)
+  (values (dpp0 0)  (dpp1 1)  (dpp2 2)  (dpp3 3)
+         (psw 136)   (cp 8)    (mdl 7)   (mdh  6)
+         (mdc 135)   (sp 9)    (csp 4)  (vecseg 137)
+          (stkov 10)  (stkun 11) (cpucon1 12) (cpucon2 13)
+         (zeros 142)  (ones 143) (spseg 134) (tfr 214)
+         (rl0 240) (rh0 241) (rl1 242) (rh1 243) (rl2 244) (rh2 245) (rl3 246) (rh3 247)
+         (rl4 248) (rh4 249) (rl5 250) (rh5 251) (rl6 252) (rh6 253) (rl7 254) (rh7 255))
+)
+
+(define-hardware
+  (name h-regbmem8)
+  (comment "registers")
+  (attrs PROFILE CACHE-ADDR)
+  (type register HI (36))
+  (indices extern-keyword regbmem8-names)
+)
+
+(define-keyword
+  (name memgr8-names)
+  (enum-prefix H-MEMGR8-)
+  (values (dpp0 65024)  (dpp1 65026)  (dpp2 65028)  (dpp3 65030)
+         (psw 65296)   (cp 65040)    (mdl 65038)   (mdh  65036)
+         (mdc 65294)   (sp 65042)    (csp 65032)  (vecseg 65298)
+          (stkov 65044)  (stkun 65046) (cpucon1 65048) (cpucon2 65050)
+         (zeros 65308)  (ones 65310) (spseg 65292) (tfr 65452) )
+)
+
+(define-hardware
+  (name h-memgr8)
+  (comment "memory location of registers")
+  (attrs )
+  (type register HI (20))
+  (indices extern-keyword memgr8-names)
+)
+
+(dsh h-cond "condition bit" () (register BI))   ;any bit from PSW while comparison
+; This bit is part of the PSW register 
+(dsh h-cbit  "carry bit"               () (register BI))
+
+(dsh h-sgtdis "segmentation enable bit" () (register BI)) ;0 means segmentation enabled
+
+;Instruction operands 
+; -- layer between the assembler and the raw hardware description 
+; -- the main means of manipulating instruction fields in the semantic code 
+
+; XC16X specific operand attributes:
+
+(define-attr
+  (for operand)
+  (type boolean)
+  (name HASH-PREFIX)
+  (comment "immediates have an optional '#' prefix")
+)
+
+(define-attr
+  (for operand)
+  (type boolean)
+  (name DOT-PREFIX)
+  (comment "bit addr have an optional '.' prefix")
+)
+
+(define-attr
+  (for operand)
+  (type boolean)
+  (name POF-PREFIX)
+  (comment "page offset ")
+)
+
+(define-attr
+  (for operand)
+  (type boolean)
+  (name PAG-PREFIX)
+  (comment "page ")
+)
+
+(define-attr
+  (for operand)
+  (type boolean)
+  (name SOF-PREFIX)
+  (comment "segment offset selection")
+)
+
+(define-attr
+  (for operand)
+  (type boolean)
+  (name SEG-PREFIX)
+  (comment "segment")
+)
+
+(dnop sr      "source register"              () h-gr    f-r2)
+(dnop dr      "destination register"         () h-gr    f-r1)
+(dnop dri     "destination register"         () h-gr    f-r4)
+(dnop srb     "source register"              () h-grb   f-r2)
+(dnop drb     "destination register"         () h-grb   f-r1)
+(dnop sr2     "2 bit source register"       () h-gr    f-r0)
+(dnop src1    "source register 1"            () h-gr   f-r1)
+(dnop src2    "source register 2"            () h-gr   f-r2)
+(dnop srdiv   "source register 2"            () h-regdiv8   f-reg8)
+(dnop RegNam  "PSW bits"                     () h-psw f-reg8) 
+(dnop uimm2   "2 bit unsigned number"        (HASH-PREFIX) h-ext f-uimm2) 
+(dnop uimm3   "3 bit unsigned number"        (HASH-PREFIX) h-r01 f-uimm3)
+(dnop uimm4   "4 bit unsigned number"        (HASH-PREFIX) h-uint f-uimm4)
+(dnop uimm7   "7 bit trap number"            (HASH-PREFIX) h-uint f-uimm7)
+(dnop uimm8   "8 bit unsigned immediate"     (HASH-PREFIX) h-uint f-uimm8)
+(dnop uimm16  "16 bit unsigned immediate"    (HASH-PREFIX) h-uint f-uimm16)
+(dnop upof16  "16 bit unsigned immediate"    (POF-PREFIX) h-addr f-memory)
+(dnop reg8    "8 bit word register number"   () h-r8 f-reg8)
+(dnop regmem8 "8 bit word register number"   () h-regmem8 f-regmem8)
+(dnop regbmem8 "8 bit byte register number"  () h-regbmem8 f-regmem8)
+(dnop regoff8 "8 bit word register number"   () h-r8 f-regoff8)
+(dnop reghi8  "8 bit word register number"   () h-r8 f-reghi8)
+(dnop regb8   "8 bit byte register number"   () h-grb8 f-regb8)
+(dnop genreg  "8 bit word register number"   () h-r8 f-regb8)
+(dnop seg     "8 bit segment number"         () h-uint f-seg8)
+(dnop seghi8  "8 bit hi segment number"      () h-uint f-segnum8)
+(dnop caddr   "16 bit address offset"        () h-addr f-offset16)
+(dnop rel     "8 bit signed relative offset" () h-sint f-rel8)
+(dnop relhi   "hi 8 bit signed relative offset" () h-sint f-relhi8)    
+(dnop condbit "condition bit"                (SEM-ONLY) h-cond f-nil)
+(dnop bit1    "gap of 1 bit"                () h-uint f-op-bit1)
+(dnop bit2    "gap of 2 bits"               () h-uint f-op-bit2)
+(dnop bit4    "gap of 4 bits"                () h-uint f-op-bit4)
+(dnop lbit4   "gap of 4 bits"                () h-uint f-op-lbit4)
+(dnop lbit2   "gap of 2 bits"                () h-uint f-op-lbit2)
+(dnop bit8    "gap of 8 bits"               () h-uint f-op-bit8)
+(dnop u4      "gap of 4 bits"               () h-r0   f-uimm4)
+(dnop bitone  "field of 1 bit"              () h-uint f-op-onebit)
+(dnop bit01   "field of 1 bit"              () h-uint f-op-1bit)
+(dnop cond    "condition code"                      () h-cc   f-condcode)
+(dnop icond   "indirect condition code"      () h-cc   f-icondcode)
+(dnop extcond "extended condition code"      () h-ecc  f-extccode)
+(dnop memory  "16 bit memory"               () h-addr f-memory)
+(dnop memgr8  "16 bit memory"               () h-memgr8 f-memgr8)
+(dnop cbit    "carry bit"                    (SEM-ONLY) h-cbit  f-nil)
+(dnop qbit    "bit addr"                            (DOT-PREFIX) h-uint  f-qbit)
+(dnop qlobit  "bit addr"                     (DOT-PREFIX) h-uint  f-qlobit)
+(dnop qhibit  "bit addr"                     (DOT-PREFIX) h-uint  f-qhibit)
+(dnop mask8   "8 bit mask"                          (HASH-PREFIX) h-uint f-mask8)
+(dnop masklo8 "8 bit mask"                          (HASH-PREFIX) h-uint f-datahi8)
+(dnop pagenum "10 bit page number"                  (HASH-PREFIX) h-uint f-pagenum)
+(dnop data8   "8 bit data"                          (HASH-PREFIX) h-uint f-data8)
+(dnop datahi8 "8 bit data"                          (HASH-PREFIX) h-uint f-datahi8)
+(dnop sgtdisbit "segmentation enable bit"    (SEM-ONLY) h-sgtdis f-nil)
+(dnop upag16  "16 bit unsigned immediate"    (PAG-PREFIX) h-uint f-uimm16)
+(dnop useg8   "8 bit segment "              (SEG-PREFIX) h-uint f-seg8)
+(dnop useg16  "16 bit address offset"        (SEG-PREFIX) h-uint f-offset16)
+(dnop usof16  "16 bit address offset"        (SOF-PREFIX) h-uint f-offset16)
+
+; define hash operator
+(define-operand (name hash) (comment "# prefix") (attrs)
+  (type h-sint)  
+  (index f-nil)
+  (handlers (parse "hash") (print "hash"))
+)
+
+; define dot operator
+(define-operand (name dot) (comment ". prefix") (attrs)
+  (type h-sint)  
+  (index f-nil)
+  (handlers (parse "dot") (print "dot"))
+)
+
+; define pof operator
+(define-operand (name pof) (comment "pof: prefix") (attrs)
+  (type h-sint)  
+  (index f-nil)
+  (handlers (parse "pof") (print "pof"))
+)
+
+; define pag operator
+(define-operand (name pag) (comment "pag: prefix") (attrs)
+  (type h-sint)
+  (index f-nil)
+  (handlers (parse "pag") (print "pag"))
+)
+
+; define sof operator
+(define-operand (name sof) (comment "sof: prefix") (attrs)
+  (type h-sint)  
+  (index f-nil)
+  (handlers (parse "sof") (print "sof"))
+)
+
+; define seg operator
+(define-operand (name segm) (comment "seg: prefix") (attrs)
+  (type h-sint)
+  (index f-nil)
+  (handlers (parse "seg") (print "seg"))
+)
+
+; IDOC attribute for instruction documentation.
+(define-attr
+  (for insn)
+  (type enum)
+  (name IDOC)
+  (comment "insn kind for documentation")
+  (attrs META)
+  (values
+   (MOVE - () "Data Movement")
+   (ALU  - () "Arithmatic & logical")
+   (CMP  - () "Compare")
+   (JMP  - () "Jump & Call")
+   (MISC - () "Miscellaneous")
+   (SYSC - () "System control")
+  )
+)
+
+; Include the instruction set descriptions from their respective
+; source files.
+
+;Arithmatic insns
+;******************************************************************
+
+;add/sub register and immediate
+(define-pmacro (arithmetic16 name insn insn1 opc1 opc2 op1 op2 mode dir)
+  (dni name 
+       (.str name "arithmetic" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",$"dir"$"op2)
+       (+ opc1 opc2 op1 op2)
+       (set mode op1 (insn1 mode op1 (mem HI op2)))
+       ()
+  )
+)
+(arithmetic16 addrpof add add OP1_0 OP2_2 reg8 upof16 HI "pof")
+(arithmetic16 subrpof sub sub OP1_2 OP2_2 reg8 upof16 HI "pof")
+(arithmetic16 addbrpof addb add OP1_0 OP2_3 regb8 upof16 QI "pof")
+(arithmetic16 subbrpof subb sub OP1_2 OP2_3 regb8 upof16 QI "pof")
+(arithmetic16 addrpag add add OP1_0 OP2_2 reg8 upag16 HI "pag")
+(arithmetic16 subrpag sub sub OP1_2 OP2_2 reg8 upag16 HI "pag")
+(arithmetic16 addbrpag addb add OP1_0 OP2_3 regb8 upag16 QI "pag")
+(arithmetic16 subbrpag subb sub OP1_2 OP2_3 regb8 upag16 QI "pag")
+
+;add/sub register and immediate
+(define-pmacro (arithmetic17 name insn insn1 opc1 opc2 op1 op2 mode dir)
+  (dni name 
+       (.str name "arithmetic" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",$"dir"$"op2)
+       (+ opc1 opc2 op1 op2)
+       (set mode op1 (insn1 mode op1 (mem HI op2) cbit))
+       ()
+  )
+)
+(arithmetic17 addcrpof addc addc OP1_1 OP2_2 reg8 upof16 HI "pof")
+(arithmetic17 subcrpof subc subc OP1_3 OP2_2 reg8 upof16 HI "pof")
+(arithmetic17 addcbrpof addcb addc OP1_1 OP2_3 regb8 upof16 QI "pof")
+(arithmetic17 subcbrpof subcb subc OP1_3 OP2_3 regb8 upof16 QI "pof")
+(arithmetic17 addcrpag addc addc OP1_1 OP2_2 reg8 upag16 HI "pag")
+(arithmetic17 subcrpag subc subc OP1_3 OP2_2 reg8 upag16 HI "pag")
+(arithmetic17 addcbrpag addcb addc OP1_1 OP2_3 regb8 upag16 QI "pag")
+(arithmetic17 subcbrpag subcb subc OP1_3 OP2_3 regb8 upag16 QI "pag")
+
+;add/sub register and immediate
+(define-pmacro (arithmetic18 name insn insn1 opc1 opc2 op1 op2 mode dir)
+  (dni name 
+       (.str name "arithmetic" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"dir"$"op1 ",$"op2)
+       (+ opc1 opc2 op2 op1)
+       (set (mem HI op1) (insn1 (mem HI op1) op2 ))
+       ()
+  )
+)
+(arithmetic18 addrpofr add add OP1_0 OP2_4 upof16 reg8 HI "pof")
+(arithmetic18 subrpofr sub sub OP1_2 OP2_4 upof16 reg8 HI "pof")
+(arithmetic18 addbrpofr addb add OP1_0 OP2_5 upof16 regb8 QI "pof")
+(arithmetic18 subbrpofr subb sub OP1_2 OP2_5 upof16 regb8 QI "pof")
+
+;add/sub register and immediate
+(define-pmacro (arithmetic19 name insn insn1 opc1 opc2 op1 op2 mode dir)
+  (dni name 
+       (.str name "arithmetic" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"dir"$"op1 ",$"op2)
+       (+ opc1 opc2 op2 op1)
+       (set (mem HI op1) (insn1 mode (mem HI op1) op2 cbit))
+       ()
+  )
+)
+(arithmetic19 addcrpofr addc addc OP1_1 OP2_4 upof16 reg8 HI "pof")
+(arithmetic19 subcrpofr subc subc OP1_3 OP2_4 upof16 reg8 HI "pof")
+(arithmetic19 addcbrpofr addcb addc OP1_1 OP2_5 upof16 regb8 QI "pof")
+(arithmetic19 subcbrpofr subcb subc OP1_3 OP2_5 upof16 regb8 QI "pof")
+
+;add/sub register and immediate
+(define-pmacro (arithmetic20 name insn insn1 opc1 opc2 op1 op2 mode dir)
+  (dni name 
+       (.str name "arithmetic" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",$hash$"dir"$"op2)
+       (+ opc1 opc2 op1 op2)
+       (set mode op1 (insn1 mode op1 op2))
+       ()
+  )
+)
+(arithmetic20 addrhpof add add OP1_0 OP2_6 reg8 uimm16 HI "pof")
+(arithmetic20 subrhpof sub sub OP1_2 OP2_6 reg8 uimm16 HI "pof")
+(arithmetic20 addbrhpof add add OP1_0 OP2_6 reg8 uimm16 HI "pag")
+(arithmetic20 subbrhpof sub sub OP1_2 OP2_6 reg8 uimm16 HI "pag")
+
+;add/sub register and immediate
+(define-pmacro (arithmetic21 name insn insn1 opc1 opc2 op1 op2 mode dir)
+  (dni name 
+       (.str name "arithmetic" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",$hash$"dir"$"op2)
+       (+ opc1 opc2 op1 (f-op-bit1 0) op2)
+       (set mode op1 (insn1 mode op1 op2))
+       ()
+  )
+)
+(arithmetic21 addrhpof3 add add OP1_0 OP2_8 dr uimm3 HI "pof")
+(arithmetic21 subrhpof3 sub sub OP1_2 OP2_8 dr uimm3 HI "pof")
+(arithmetic21 addbrhpag3 addb add OP1_0 OP2_9 drb uimm3 QI "pag")
+(arithmetic21 subbrhpag3 subb sub OP1_2 OP2_9 drb uimm3 QI "pag")
+(arithmetic21 addrhpag3 add add OP1_0 OP2_8 dr uimm3 HI "pag")
+(arithmetic21 subrhpag3 sub sub OP1_2 OP2_8 dr uimm3 HI "pag")
+(arithmetic21 addbrhpof3 addb add OP1_0 OP2_9 drb uimm3 QI "pof")
+(arithmetic21 subbrhpof3 subb sub OP1_2 OP2_9 drb uimm3 QI "pof")
+
+;add/sub register and immediate
+(define-pmacro (arithmetic22 name insn insn1 opc1 opc2 op1 op2 mode dir)
+  (dni name 
+       (.str name "arithmetic" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",$hash$"dir"$"op2)
+       (+ opc1 opc2 op1 op2 (f-op-bit8 0))
+       (set mode op1 (insn1 mode op1 op2))
+       ()
+  )
+)
+(arithmetic22 addrbhpof addb add OP1_0 OP2_7 regb8 uimm8 QI "pof")
+(arithmetic22 subrbhpof subb sub OP1_2 OP2_7 regb8 uimm8 QI "pof")
+(arithmetic22 addbrhpag addb add OP1_0 OP2_7 regb8 uimm8 QI "pag")
+(arithmetic22 subbrhpag subb sub OP1_2 OP2_7 regb8 uimm8 QI "pag")
+
+;add/sub register and immediate
+(define-pmacro (arithmetic23 name insn insn1 opc1 opc2 op1 op2 mode dir)
+  (dni name 
+       (.str name "arithmetic" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",$hash$"dir"$"op2)
+       (+ opc1 opc2 op1 op2)
+       (set mode op1 (insn1 mode op1 op2 cbit))
+       ()
+  )
+)
+(arithmetic23 addcrhpof addc addc OP1_1 OP2_6 reg8 uimm16 HI "pof")
+(arithmetic23 subcrhpof subc subc OP1_3 OP2_6 reg8 uimm16 HI "pof")
+(arithmetic23 addcbrhpof addc addc OP1_1 OP2_6 reg8 uimm16 HI "pag")
+(arithmetic23 subcbrhpof subc subc OP1_3 OP2_6 reg8 uimm16 HI "pag")
+
+;add/sub register and immediate
+(define-pmacro (arithmetic24 name insn insn1 opc1 opc2 op1 op2 mode dir)
+  (dni name 
+       (.str name "arithmetic" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",$hash$"dir"$"op2)
+       (+ opc1 opc2 op1 (f-op-bit1 0) op2)
+       (set mode op1 (insn1 mode op1 op2 cbit))
+       ()
+  )
+)
+(arithmetic24 addcrhpof3 addc addc OP1_1 OP2_8 dr uimm3 HI "pof")
+(arithmetic24 subcrhpof3 subc subc OP1_3 OP2_8 dr uimm3 HI "pof")
+(arithmetic24 addcbrhpag3 addcb addc OP1_1 OP2_9 drb uimm3 QI "pag")
+(arithmetic24 subcbrhpag3 subcb subc OP1_3 OP2_9 drb uimm3 QI "pag")
+(arithmetic24 addcrhpag3 addc addc OP1_1 OP2_8 dr uimm3 HI "pag")
+(arithmetic24 subcrhpag3 subc subc OP1_3 OP2_8 dr uimm3 HI "pag")
+(arithmetic24 addcbrhpof3 addcb addc OP1_1 OP2_9 drb uimm3 QI "pof")
+(arithmetic24 subcbrhpof3 subcb subc OP1_3 OP2_9 drb uimm3 QI "pof")
+
+;add/sub register and immediate
+(define-pmacro (arithmetic25 name insn insn1 opc1 opc2 op1 op2 mode dir)
+  (dni name 
+       (.str name "arithmetic" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",$hash$"dir"$"op2)
+       (+ opc1 opc2 op1 op2 (f-op-bit8 0))
+       (set mode op1 (insn1 mode op1 op2 cbit))
+       ()
+  )
+)
+(arithmetic25 addcrbhpof addcb addc OP1_1 OP2_7 regb8 uimm8 QI "pof")
+(arithmetic25 subcrbhpof subcb subc OP1_3 OP2_7 regb8 uimm8 QI "pof")
+(arithmetic25 addcbrhpag addcb addc OP1_1 OP2_7 regb8 uimm8 QI "pag")
+(arithmetic25 subcbrhpag subcb subc OP1_3 OP2_7 regb8 uimm8 QI "pag")
+
+;add/sub register and immediate
+(define-pmacro (arithmetic10 name insn insn1 opc1 opc2 op1 op2 mode)
+  (dni name 
+       (.str name "arithmetic" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",$hash$"op2)
+       (+ opc1 opc2 op1 (f-op-bit1 0) op2)
+       (set mode op1 (insn1 mode op1 op2))
+       ()
+  )
+)
+(arithmetic10 addri add add OP1_0 OP2_8 dr uimm3 HI)
+(arithmetic10 subri sub sub OP1_2 OP2_8 dr uimm3 HI)
+(arithmetic10 addbri addb add OP1_0 OP2_9 drb uimm3 QI)
+(arithmetic10 subbri subb sub OP1_2 OP2_9 drb uimm3 QI)
+
+;add/sub register and immediate
+(define-pmacro (arithmetic11 name insn insn1 opc1 opc2 op1 op2 mode)
+  (dni name 
+       (.str name "arithmetic" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",$hash$"op2)
+       (+ opc1 opc2 op1 op2)
+       (set mode op1 (insn1 mode op1 op2))
+       ()
+  )
+)
+(arithmetic11 addrim add add OP1_0 OP2_6 reg8 uimm16 HI)
+(arithmetic11 subrim sub sub OP1_2 OP2_6 reg8 uimm16 HI)
+
+;add/sub register and immediate
+(define-pmacro (arithmetic12 name insn insn1 opc1 opc2 op1 op2 mode)
+  (dni name 
+       (.str name "arithmetic" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",$hash$"op2)
+       (+ opc1 opc2 op1 op2 (f-op-bit8 0))
+       (set mode op1 (insn1 mode op1 op2))
+       ()
+  )
+)
+(arithmetic12 addbrim addb add OP1_0 OP2_7 regb8 uimm8 QI)
+(arithmetic12 subbrim subb sub OP1_2 OP2_7 regb8 uimm8 QI)
+
+;add/sub register and immediate with carry
+(define-pmacro (arithmetic13 name insn insn1 opc1 opc2 op1 op2 mode)
+  (dni name 
+       (.str name "arithmetic" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",$hash$"op2)
+       (+ opc1 opc2 op1 (f-op-bit1 0) op2)
+       (set mode op1 (insn1 mode op1 op2 cbit))
+       ()
+  )
+)
+(arithmetic13 addcri addc addc OP1_1 OP2_8 dr uimm3 HI)
+(arithmetic13 subcri subc subc OP1_3 OP2_8 dr uimm3 HI)
+(arithmetic13 addcbri addcb addc OP1_1 OP2_9 drb uimm3 QI)
+(arithmetic13 subcbri subcb subc OP1_3 OP2_9 drb uimm3 QI)
+
+;add/sub register and immediate with carry
+(define-pmacro (arithmetic14 name insn insn1 opc1 opc2 op1 op2 mode)
+  (dni name 
+       (.str name "arithmetic" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",$hash$"op2)
+       (+ opc1 opc2 op1 op2)
+       (set mode op1 (insn1 mode op1 op2 cbit))
+       ()
+  )
+)
+(arithmetic14 addcrim addc addc OP1_1 OP2_6 reg8 uimm16 HI)
+(arithmetic14 subcrim subc subc OP1_3 OP2_6 reg8 uimm16 HI)
+
+;add/sub register and immediate with carry
+(define-pmacro (arithmetic15 name insn insn1 opc1 opc2 op1 op2 mode)
+  (dni name 
+       (.str name "arithmetic" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",$hash$"op2)
+       (+ opc1 opc2 op1 op2 (f-op-bit8 0))
+       (set mode op1 (insn1 mode op1 op2 cbit))
+       ()
+  )
+)
+(arithmetic15 addcbrim addcb addc OP1_1 OP2_7 regb8 uimm8 QI)
+(arithmetic15 subcbrim subcb subc OP1_3 OP2_7 regb8 uimm8 QI)
+
+
+;add/sub registers
+(define-pmacro (arithmetic name insn insn1 opc1 opc2 op1 op2 mode)
+  (dni name 
+       (.str name "arithmetic" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",$"op2)
+       (+ opc1 opc2 op1 op2)
+       (set mode op1 (insn1 mode op1 op2))
+       ()
+  )
+)
+(arithmetic addr add add OP1_0 OP2_0 dr sr HI)
+(arithmetic subr sub sub OP1_2 OP2_0 dr sr HI)
+(arithmetic addbr addb add OP1_0 OP2_1 drb srb QI)
+(arithmetic subbr subb sub OP1_2 OP2_1 drb srb QI)
+
+;add/sub register and indirect memory
+(define-pmacro (arithmetic1 name insn insn1 opc1 opc2 op1 op2 mode)
+  (dni name
+       (.str name "arithmetic" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",[$"op2"]")
+       (+ opc1 opc2 op1 (f-op-bit2 2) op2)
+       (set mode op1 (insn1 mode op1 (mem HI op2)))
+       ()
+  )
+)
+(arithmetic1 add2 add add OP1_0 OP2_8 dr sr2 HI)
+(arithmetic1 sub2 sub sub OP1_2 OP2_8 dr sr2 HI)
+(arithmetic1 addb2 addb add OP1_0 OP2_9 drb sr2 QI)
+(arithmetic1 subb2 subb sub OP1_2 OP2_9 drb sr2 QI)
+
+;add/sub register and indirect memory post increment
+(define-pmacro (arithmetic2 name insn insn1 opc1 opc2 op1 op2 mode)
+  (dni name
+       (.str name "arithmetic" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",[$"op2"+]")
+       (+ opc1 opc2 op1 (f-op-bit2 3) op2)
+       (sequence ()
+          (set mode op1 (insn1 mode op1 (mem HI op2)))
+          (set HI op2 (add HI op2 (const 2)))
+       )
+       ()
+  )
+)
+(arithmetic2 add2i add add OP1_0 OP2_8 dr sr2 HI)
+(arithmetic2 sub2i sub sub OP1_2 OP2_8 dr sr2 HI)
+(arithmetic2 addb2i addb add OP1_0 OP2_9 drb sr2 QI)
+(arithmetic2 subb2i subb sub OP1_2 OP2_9 drb sr2 QI)
+
+;add/sub registers with carry
+(define-pmacro (arithmetic3 name insn insn1 opc1 opc2 op1 op2 mode)
+  (dni name 
+       (.str name "arithmetic" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",$"op2)
+       (+ opc1 opc2 op1 op2)
+       (set mode op1 (insn1 mode op1 op2 cbit))
+       ()
+  )
+)
+(arithmetic3 addcr addc addc OP1_1 OP2_0 dr sr HI)
+(arithmetic3 subcr subc subc OP1_3 OP2_0 dr sr HI)
+(arithmetic3 addbcr addcb addc OP1_1 OP2_1 drb srb QI) 
+(arithmetic3 subbcr subcb subc OP1_3 OP2_1 drb srb QI)
+
+
+;add/sub register and indirect memory
+(define-pmacro (arithmetic4 name insn insn1 opc1 opc2 op1 op2 mode)
+  (dni name
+       (.str name "arithmetic" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",[$"op2"]")
+       (+ opc1 opc2 op1 (f-op-bit2 2) op2)
+       (set mode op1 (insn1 mode op1 (mem HI op2) cbit))
+       ()
+  )
+)
+(arithmetic4 addcr2 addc addc OP1_1 OP2_8 dr sr2 HI)
+(arithmetic4 subcr2 subc subc OP1_3 OP2_8 dr sr2 HI)
+(arithmetic4 addbcr2 addcb addc OP1_1 OP2_9 drb sr2 QI)
+(arithmetic4 subbcr2 subcb subc OP1_3 OP2_9 drb sr2 QI)
+
+;add/sub register and indirect memory post increment
+(define-pmacro (arithmetic5 name insn insn1 opc1 opc2 op1 op2 mode)
+  (dni name
+       (.str name "arithmetic" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",[$"op2"+]")
+       (+ opc1 opc2 op1 (f-op-bit2 3) op2)
+       (sequence ()
+           (set mode op1 (insn1 mode op1 (mem HI op2) cbit))
+           (set HI op2 (add HI op2 (const 2)))
+       )
+       ()
+  )
+)
+(arithmetic5 addcr2i addc addc OP1_1 OP2_8 dr sr2 HI)
+(arithmetic5 subcr2i subc subc OP1_3 OP2_8 dr sr2 HI)
+(arithmetic5 addbcr2i addcb addc OP1_1 OP2_9 drb sr2 QI)
+(arithmetic5 subbcr2i subcb subc OP1_3 OP2_9 drb sr2 QI)
+
+;add/sub register and direct memory
+(define-pmacro (arithmetic6 name insn insn1 opc1 opc2 op1 op2 mode)
+  (dni name 
+       (.str name "arithmetic" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",$"op2)
+       (+ opc1 opc2 op1 op2)
+       (set mode op1 (insn1 mode op1 op2))
+       ()
+  )
+)
+
+;add/sub register and direct memory
+(define-pmacro (arithmetic7 name insn insn1 opc1 opc2 op1 op2 mode)
+  (dni name 
+       (.str name "arithmetic" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",$"op2)
+       (+ opc1 opc2 op2 op1)
+       (set (mem HI op1) (insn1 (mem HI op1) op2))
+       ()
+  )
+)
+(arithmetic6 addrm2 add add OP1_0 OP2_2 regmem8 memgr8 HI)
+(arithmetic7 addrm3 add add OP1_0 OP2_4 memgr8 regmem8 HI)
+(arithmetic6 addrm add add OP1_0 OP2_2 reg8 memory HI)
+(arithmetic7 addrm1 add add OP1_0 OP2_4 memory reg8 HI)
+(arithmetic6 subrm3 sub sub OP1_2 OP2_2 regmem8 memgr8 HI)
+(arithmetic7 subrm2 sub sub OP1_2 OP2_4 memgr8 regmem8 HI)
+(arithmetic6 subrm1 sub sub OP1_2 OP2_2 reg8 memory HI)
+(arithmetic7 subrm sub sub OP1_2 OP2_4 memory reg8 HI)
+(arithmetic6 addbrm2 addb add OP1_0 OP2_3 regbmem8 memgr8 QI)
+(arithmetic7 addbrm3 addb add OP1_0 OP2_5 memgr8 regbmem8 QI)
+(arithmetic6 addbrm addb add OP1_0 OP2_3 regb8 memory QI)
+(arithmetic7 addbrm1 addb add OP1_0 OP2_5 memory regb8 QI)
+(arithmetic6 subbrm3 subb sub OP1_2 OP2_3 regbmem8 memgr8 QI)
+(arithmetic7 subbrm2 subb sub OP1_2 OP2_5 memgr8 regbmem8 QI)
+(arithmetic6 subbrm1 subb sub OP1_2 OP2_3 regb8 memory QI)
+(arithmetic7 subbrm subb sub OP1_2 OP2_5 memory regb8 QI)
+
+;add/sub registers with carry
+(define-pmacro (arithmetic8 name insn insn1 opc1 opc2 op1 op2 mode)
+  (dni name 
+       (.str name "arithmetic" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",$"op2)
+       (+ opc1 opc2 op1 op2)
+       (set mode op1 (insn1 mode op1 op2 cbit))
+       ()
+  )
+)
+
+;add/sub registers with carry
+(define-pmacro (arithmetic9 name insn insn1 opc1 opc2 op1 op2 mode)
+  (dni name 
+       (.str name "arithmetic" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",$"op2)
+       (+ opc1 opc2 op2 op1)
+       (set (mem HI op1) (insn1 (mem HI op1) op2 cbit))
+       ()
+  )
+)
+(arithmetic8 addcrm2 addc addc OP1_1 OP2_2 regmem8 memgr8 HI)
+(arithmetic9 addcrm3 addc addc OP1_1 OP2_4  memgr8 regmem8 HI)
+(arithmetic8 addcrm addc addc OP1_1 OP2_2 reg8 memory HI)
+(arithmetic9 addcrm1 addc addc OP1_1 OP2_4  memory reg8 HI)
+(arithmetic8 subcrm3 subc subc OP1_3 OP2_2  regmem8 memgr8 HI)
+(arithmetic9 subcrm2 subc subc OP1_3 OP2_4 memgr8 regmem8 HI)
+(arithmetic8 subcrm1 subc subc OP1_3 OP2_2  reg8 memory HI)
+(arithmetic9 subcrm subc subc OP1_3 OP2_4 memory reg8 HI)
+(arithmetic8 addcbrm2 addcb addc OP1_1 OP2_3 regbmem8 memgr8 QI)
+(arithmetic9 addcbrm3 addcb addc OP1_1 OP2_5  memgr8 regbmem8 QI)
+(arithmetic8 addcbrm addcb addc OP1_1 OP2_3 regb8 memory QI)
+(arithmetic9 addcbrm1 addcb addc OP1_1 OP2_5  memory regb8 QI)
+(arithmetic8 subcbrm3 subcb subc OP1_3 OP2_3  regbmem8 memgr8 QI)
+(arithmetic9 subcbrm2 subcb subc OP1_3 OP2_5 memgr8 regbmem8 QI)
+(arithmetic8 subcbrm1 subcb subc OP1_3 OP2_3  regb8 memory QI)
+(arithmetic9 subcbrm subcb subc OP1_3 OP2_5 memory regb8 QI)
+
+; MUL Rwn,Rwm
+(dni muls "signed multiplication"
+     ((PIPE OS) (IDOC ALU))
+     "mul $src1,$src2"
+     (+ OP1_0 OP2_11 src1 src2)
+     (nop) ;; FIXME: (reg SI h-md 0)
+     ()
+)
+; MULU Rwn,Rwm
+(dni mulu "unsigned multiplication"
+     ((PIPE OS) (IDOC ALU))
+     "mulu $src1,$src2"
+     (+ OP1_1 OP2_11 src1 src2)
+     (nop) ;; FIXME: (reg SI h-md 0)
+     ()
+)
+; DIV Rwn
+(dni div "16-by-16 signed division"
+     ((PIPE OS) (IDOC ALU))
+     "div $srdiv"
+     (+ OP1_4 OP2_11 srdiv )
+     (sequence ()
+         (set HI (reg HI h-cr 6) (div HI (reg HI h-cr 6) srdiv))
+         (set HI (reg HI h-cr 7) (mod HI (reg HI h-cr 6) srdiv))
+     )
+     ()
+) 
+; DIVL Rwn
+(dni divl "32-by16 signed division"
+     ((PIPE OS) (IDOC ALU))
+     "divl $srdiv"
+     (+ OP1_6 OP2_11 srdiv )
+     (sequence ()
+         (set HI (reg HI h-cr 6) 0) ;; FIXME: (div SI (reg SI h-md 0) srdiv))
+        (set HI (reg HI h-cr 7) 0) ;; FIXME: (mod SI (reg SI h-md 0) srdiv))
+     )
+     ()
+)
+; DIVLU Rwn 
+(dni divlu "32-by16 unsigned division"
+     ((PIPE OS) (IDOC ALU))
+     "divlu $srdiv"
+     (+ OP1_7 OP2_11 srdiv )
+     (sequence ()
+         (set HI (reg HI h-cr 6) 0) ;; FIXME: (udiv SI (reg SI h-md 0) srdiv))
+        (set HI (reg HI h-cr 7) 0) ;; FIXME: (umod SI (reg SI h-md 0) srdiv))
+     )
+     ()
+)
+; DIVU Rwn
+(dni divu "16-by-16 unsigned division"
+     ((PIPE OS) (IDOC ALU))
+     "divu $srdiv"
+     (+ OP1_5 OP2_11 srdiv )
+     (sequence ()
+         (set HI (reg HI h-cr 6) (udiv HI (reg HI h-cr 6) srdiv))
+         (set HI (reg HI h-cr 7) (umod HI (reg HI h-cr 6) srdiv))
+     )
+     ()
+)
+
+;Integer one's complement
+; CPL Rwn
+(dni cpl "Integer Ones complement"
+     ((PIPE OS) (IDOC MISC))
+     "cpl $dr"
+     (+ OP1_9 OP2_1 dr (f-op-bit4 0))
+     (set dr (inv HI dr))
+     ()
+)
+
+;Bytes one's complement
+; CPLB Rbn
+(dni cplb "Byte Ones complement"
+     ((PIPE OS) (IDOC MISC))
+     "cplb $drb"
+     (+ OP1_11 OP2_1 drb (f-op-bit4 0))
+     (set drb (inv QI drb))
+     ()
+)
+;Integer two's complement
+; NEG Rwn
+(dni neg "Integer two's complement"
+     ((PIPE OS) (IDOC MISC))
+     "neg $dr"
+     (+ OP1_8 OP2_1 dr (f-op-bit4 0))
+     (set dr (neg HI dr))
+     ()
+)
+;Bytes two's complement
+; NEGB Rbn
+(dni negb "byte twos complement"
+     ((PIPE OS) (IDOC MISC))
+     "negb $drb"
+     (+ OP1_10 OP2_1 drb (f-op-bit4 0))
+     (set drb (neg QI drb))
+     ()
+)
+
+;****************************************************************
+;logical insn
+;****************************************************************
+;and/or/xor registers
+(define-pmacro (logical name insn insn1 opc1 opc2 op1 op2 mode)
+  (dni name 
+       (.str name "logical" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",$"op2)
+       (+ opc1 opc2 op1 op2)
+       (set mode op1 (insn1 mode op1 op2))
+       ()
+  )
+)
+
+(logical andr and and OP1_6 OP2_0 dr sr HI)
+(logical orr or or OP1_7 OP2_0 dr sr HI)
+(logical xorr xor xor OP1_5 OP2_0 dr sr HI)
+(logical andbr andb and OP1_6 OP2_1 drb srb QI)
+(logical orbr orb or OP1_7 OP2_1 drb srb QI)
+(logical xorbr xorb xor OP1_5 OP2_1 drb srb QI)
+
+;and/or/xor register and immediate
+(define-pmacro (logical1 name insn insn1 opc1 opc2 op1 op2 mode)
+  (dni name 
+       (.str name "logical" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",$hash$"op2)
+       (+ opc1 opc2 op1 (f-op-bit1 0) op2)
+       (set mode op1 (insn1 mode op1 op2))
+       ()
+  )
+)
+(logical1 andri and and OP1_6 OP2_8 dr uimm3 HI)
+(logical1 orri or or OP1_7 OP2_8 dr uimm3 HI)
+(logical1 xorri xor xor OP1_5 OP2_8 dr uimm3 HI)
+(logical1 andbri andb and OP1_6 OP2_9 drb uimm3 QI)
+(logical1 orbri orb or OP1_7 OP2_9 drb uimm3 QI)
+(logical1 xorbri xorb xor OP1_5 OP2_9 drb uimm3 QI)
+
+;and/or/xor register and immediate
+(define-pmacro (logical2 name insn insn1 opc1 opc2 op1 op2 mode)
+  (dni name 
+       (.str name "logical" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",$hash$"op2)
+       (+ opc1 opc2 op1 op2)
+       (set mode op1 (insn1 mode op1 op2))
+       ()
+  )
+)
+(logical2 andrim and and OP1_6 OP2_6 reg8 uimm16 HI)
+(logical2 orrim or or OP1_7 OP2_6 reg8 uimm16 HI)
+(logical2 xorrim xor xor OP1_5 OP2_6 reg8 uimm16 HI)
+
+;and/or/xor register and immediate
+(define-pmacro (logical3 name insn insn1 opc1 opc2 op1 op2 mode)
+  (dni name 
+       (.str name "logical" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",$hash$"op2)
+       (+ opc1 opc2 op1 op2 (f-op-bit8 0))
+       (set mode op1 (insn1 mode op1 op2))
+       ()
+  )
+)
+(logical3 andbrim andb and OP1_6 OP2_7 regb8 uimm8 QI)
+(logical3 orbrim orb or OP1_7 OP2_7 regb8 uimm8 QI)
+(logical3 xorbrim xorb xor OP1_5 OP2_7 regb8 uimm8 QI)
+
+;and/or/xor register and indirect memory
+(define-pmacro (logical4 name insn insn1 opc1 opc2 op1 op2 mode)
+  (dni name
+       (.str name "logical" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",[$"op2"]")
+       (+ opc1 opc2 op1 (f-op-bit2 2) op2)
+       (set mode op1 (insn1 mode op1 (mem HI op2)))
+       ()
+  )
+)
+(logical4 and2 and and OP1_6 OP2_8 dr sr2 HI)
+(logical4 or2 or or OP1_7 OP2_8 dr sr2 HI)
+(logical4 xor2 xor xor OP1_5 OP2_8 dr sr2 HI)
+(logical4 andb2 andb and OP1_6 OP2_9 drb sr2 QI)
+(logical4 orb2 orb or OP1_7 OP2_9 drb sr2 QI)
+(logical4 xorb2 xorb xor OP1_5 OP2_9 drb sr2 QI)
+
+;and/or/xor register and indirect memory post increment
+(define-pmacro (logical5 name insn insn1 opc1 opc2 op1 op2 mode)
+  (dni name
+       (.str name "logical" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",[$"op2"+]")
+       (+ opc1 opc2 op1 (f-op-bit2 3) op2)
+       (sequence ()
+          (set mode op1 (insn1 mode op1 (mem HI op2)))
+          (set HI op2 (add HI op2 (const 2)))
+       )
+       ()
+  )
+)
+(logical5 and2i and and OP1_6 OP2_8 dr sr2 HI)
+(logical5 or2i or or OP1_7 OP2_8 dr sr2 HI)
+(logical5 xor2i xor xor OP1_5 OP2_8 dr sr2 HI)
+(logical5 andb2i andb and OP1_6 OP2_9 drb sr2 QI)
+(logical5 orb2i orb or OP1_7 OP2_9 drb sr2 QI)
+(logical5 xorb2i xorb xor OP1_5 OP2_9 drb sr2 QI)
+
+;add/sub register and immediate
+(define-pmacro (logical7 name insn insn1 opc1 opc2 op1 op2 mode dir)
+  (dni name 
+       (.str name "arithmetic" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"dir"$"op1 ",$"op2)
+       (+ opc1 opc2 op1 op2)
+       (set (mem HI op1) (insn1 (mem HI op1) op2 ))
+       ()
+  )
+)
+(logical7 andpofr and and OP1_6 OP2_2 reg8 upof16 HI "pof")
+(logical7 orpofr or or OP1_7 OP2_2 reg8 upof16 HI "pof")
+(logical7 xorpofr xor xor OP1_5 OP2_2 reg8 upof16 HI "pof")
+(logical7 andbpofr andb and OP1_6 OP2_3 regb8 upof16 QI "pof")
+(logical7 orbpofr orb or OP1_7 OP2_3 regb8 upof16 QI "pof")
+(logical7 xorbpofr xorb xor OP1_5 OP2_3 regb8 upof16 QI "pof")
+
+;add/sub register and immediate
+(define-pmacro (logical8 name insn insn1 opc1 opc2 op1 op2 mode dir)
+  (dni name 
+       (.str name "arithmetic" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"dir"$"op1 ",$"op2)
+       (+ opc1 opc2 op1 op2)
+       (set (mem HI op1) (insn1 (mem HI op1) op2 ))
+       ()
+  )
+)
+(logical8 andrpofr and and OP1_6 OP2_4 upof16 reg8 HI "pof")
+(logical8 orrpofr or or OP1_7 OP2_4 upof16 reg8 HI "pof")
+(logical8 xorrpofr xor xor OP1_5 OP2_4 upof16 reg8 HI "pof")
+(logical8 andbrpofr andb and OP1_6 OP2_5 upof16 regb8 QI "pof")
+(logical8 orbrpofr orb or OP1_7 OP2_5 upof16 regb8 QI "pof")
+(logical8 xorbrpofr xorb xor OP1_5 OP2_5 upof16 regb8 QI "pof")
+
+;and/or/xor register and direct memory
+(define-pmacro (logical6 name insn insn1 opc1 opc2 op1 op2 mode)
+  (dni name 
+       (.str name "arithmetic" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",$"op2)
+       (+ opc1 opc2 op1 op2)
+       (set mode op1 (insn1 mode op1 op2))
+       ()
+  )
+)
+
+;and/or/xor register and direct memory
+(define-pmacro (logical7 name insn insn1 opc1 opc2 op1 op2 mode)
+  (dni name 
+       (.str name "arithmetic" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",$"op2)
+       (+ opc1 opc2 op2 op1)
+       (set (mem HI op1) (insn1 (mem HI op1) op2))
+       ()
+  )
+)
+(logical6 andrm2 and and OP1_6 OP2_2 regmem8 memgr8 HI)
+(logical7 andrm3 and and OP1_6 OP2_4 memgr8 regmem8 HI)
+(logical6 andrm and and OP1_6 OP2_2 reg8 memory HI)
+(logical7 andrm1 and and OP1_6 OP2_4 memory reg8 HI)
+(logical6 orrm3 or or OP1_7 OP2_2 regmem8 memgr8 HI)
+(logical7 orrm2 or or OP1_7 OP2_4 memgr8 regmem8 HI)
+(logical6 orrm1 or or OP1_7 OP2_2 reg8 memory HI)
+(logical7 orrm or or OP1_7 OP2_4 memory reg8 HI)
+(logical6 xorrm3 xor xor OP1_5 OP2_2 regmem8 memgr8 HI)
+(logical7 xorrm2 xor xor OP1_5 OP2_4 memgr8 regmem8 HI)
+(logical6 xorrm1 xor xor OP1_5 OP2_2 reg8 memory HI)
+(logical7 xorrm xor xor OP1_5 OP2_4 memory reg8 HI)
+(logical6 andbrm2 andb and OP1_6 OP2_3 regbmem8 memgr8 QI)
+(logical7 andbrm3 andb and OP1_6 OP2_5 memgr8 regbmem8 QI)
+(logical6 andbrm andb and OP1_6 OP2_3 regb8 memory QI)
+(logical7 andbrm1 andb and OP1_6 OP2_5 memory regb8 QI)
+(logical6 orbrm3 orb or OP1_7 OP2_3 regbmem8 memgr8 QI)
+(logical7 orbrm2 orb or OP1_7 OP2_5 memgr8 regbmem8 QI)
+(logical6 orbrm1 orb or OP1_7 OP2_3 regb8 memory QI)
+(logical7 orbrm orb or OP1_7 OP2_5 memory regb8 QI)
+(logical6 xorbrm3 xorb xor OP1_5 OP2_3 regbmem8 memgr8 QI)
+(logical7 xorbrm2 xorb xor OP1_5 OP2_5 memgr8 regbmem8 QI)
+(logical6 xorbrm1 xorb xor OP1_5 OP2_3 regb8 memory QI)
+(logical7 xorbrm xorb xor OP1_5 OP2_5 memory regb8 QI)
+
+;****************************************************************
+;logical insn
+;****************************************************************
+;mov registers
+(define-pmacro (move name insn opc1 opc2 op1 op2 mode)
+  (dni name 
+       (.str name "mov registers" )
+       ((PIPE OS) (IDOC MOVE))
+       (.str insn " $"op1 ",$"op2)
+       (+ opc1 opc2 op1 op2)
+       (set mode op1 op2)
+       ()
+  )
+)
+(move movr mov OP1_15 OP2_0 dr sr HI)
+(move movrb movb OP1_15 OP2_1 drb srb HI)
+
+;mov register and immediate
+(define-pmacro (move1 name insn opc1 opc2 op1 op2 mode)
+  (dni name 
+       (.str name "move" )
+       ((PIPE OS) (IDOC MOVE))
+       (.str insn " $"op1 ",$hash$"op2)
+       (+ opc1 opc2 op2 op1)
+       (set mode op1 op2)
+       ()
+  )
+)
+(move1 movri mov  OP1_14 OP2_0 dri u4 HI)
+(move1 movbri movb  OP1_14 OP2_1 srb u4 QI)
+
+; MOV Rwn,#data16
+(dni movi "move immediate to register"
+     ((PIPE OS) (IDOC MOVE))
+     "mov $reg8,$hash$uimm16"
+     (+ OP1_14 OP2_6 reg8 uimm16)
+     (set HI reg8 uimm16)
+     ()
+)
+
+; MOVB reg,#data8
+(dni movbi "move immediate to register"
+     ((PIPE OS) (IDOC MOVE))
+     "movb $regb8,$hash$uimm8"
+     (+ OP1_14 OP2_7 regb8 uimm8 (f-op-bit8 0))
+     (set QI regb8 uimm8)
+     ()
+)
+
+;move and indirect memory
+(define-pmacro (mov2 name insn opc1 opc2 op1 op2 mode)
+  (dni name
+       (.str name "move" )
+       ((PIPE OS) (IDOC MOVE))
+       (.str insn " $"op1 ",[$"op2"]")
+       (+ opc1 opc2 op1 op2)
+       (set mode op1 (mem HI op2))
+       ()
+  )
+)
+(mov2 movr2 mov OP1_10 OP2_8 dr sr HI)
+(mov2 movbr2 movb OP1_10 OP2_9 drb sr QI)
+
+;move and indirect memory
+(define-pmacro (mov3 name insn opc1 opc2 op1 op2 mode)
+  (dni name
+       (.str name "move" )
+       ((PIPE OS) (IDOC MOVE))
+       (.str insn " [$"op2 "],$"op1)
+       (+ opc1 opc2 op1 op2)
+       (set mode op1 (mem HI op2))
+       ()
+  )
+)
+(mov3 movri2 mov OP1_11 OP2_8 dr sr HI)
+(mov3 movbri2 movb OP1_11 OP2_9 drb sr QI)
+
+;move and indirect memory
+(define-pmacro (mov4 name insn opc1 opc2 op1 op2 mode)
+  (dni name
+       (.str name "move" )
+       ((PIPE OS) (IDOC MOVE))
+       (.str insn " [-$"op2 "],$"op1)
+       (+ opc1 opc2 op1 op2)
+       (sequence HI ()
+         (set op1 (sub op2 (const HI 2)))
+         (set HI (mem HI op2) op1)
+       )
+       ()
+  )
+)
+(mov4 movri3 mov OP1_8 OP2_8 dr sr HI)
+(mov4 movbri3 movb OP1_8 OP2_9 drb sr QI)
+
+;mov register and indirect memory post increment
+(define-pmacro (mov5 name insn opc1 opc2 op1 op2 mode)
+  (dni name
+       (.str name "move" )
+       ((PIPE OS) (IDOC MOVE))
+       (.str insn " $"op1 ",[$"op2"+]")
+       (+ opc1 opc2 op1 op2)
+       (sequence ()
+          (set mode op1 (mem HI op2))
+          (set HI op2 (add HI op2 (const 2)))
+       )
+       ()
+  )
+)
+(mov5 mov2i mov OP1_9 OP2_8 dr sr HI)
+(mov5 movb2i movb OP1_9 OP2_9 drb sr HI)
+
+;mov indirect memory
+(define-pmacro (mov6 name insn opc1 opc2 op1 op2 mode)
+  (dni name
+       (.str name "move" )
+       ((PIPE OS) (IDOC MOVE))
+       (.str insn " [$"op1 "],[$"op2"]")
+       (+ opc1 opc2 op1 op2)
+       (set HI (mem HI op1) (mem HI op2))
+       ()
+  )
+)
+(mov6 mov6i mov OP1_12 OP2_8 dr sr HI)
+(mov6 movb6i movb OP1_12 OP2_9 dr sr HI)
+
+;mov indirect memory
+(define-pmacro (mov7 name insn opc1 opc2 op1 op2 mode)
+  (dni name
+       (.str name "move" )
+       ((PIPE OS) (IDOC MOVE))
+       (.str insn " [$"op1 "+],[$"op2"]")
+       (+ opc1 opc2 op1 op2)
+       (sequence ()
+          (set mode (mem mode op1) (mem mode op2))
+          (set mode op1 (add mode op1 (const mode 2)))
+       )
+       ()
+  )
+)
+(mov7 mov7i mov OP1_13 OP2_8 dr sr HI)
+(mov7 movb7i movb OP1_13 OP2_9 dr sr HI)
+
+;mov indirect memory
+(define-pmacro (mov8 name insn opc1 opc2 op1 op2 mode)
+  (dni name
+       (.str name "move" )
+       ((PIPE OS) (IDOC MOVE))
+       (.str insn " [$"op1 "],[$"op2"+]")
+       (+ opc1 opc2 op1 op2)
+       (sequence ()
+          (set mode (mem mode op1) (mem mode op2))
+          (set mode op2 (add mode op2 (const mode 2)))
+       )
+       ()
+  )
+)
+(mov8 mov8i mov OP1_14 OP2_8 dr sr HI)
+(mov8 movb8i movb OP1_14 OP2_9 dr sr HI)
+
+;mov indirect memory
+(define-pmacro (mov9 name insn opc1 opc2 op1 op2 mode)
+  (dni name
+       (.str name "move" )
+       ((PIPE OS) (IDOC MOVE))
+       (.str insn " $"op1 ",[$"op2"+$hash$"uimm16"]")
+       (+ opc1 opc2 op1 op2 uimm16)
+       (sequence mode ((mode tmp1))
+          (set mode tmp1 (add HI op2 uimm16))
+          (set mode op1 (mem HI tmp1))
+       )
+       ()
+  )
+)
+(mov9 mov9i mov OP1_13 OP2_4 dr sr HI)
+(mov9 movb9i movb OP1_15 OP2_4 drb sr QI)
+
+;mov indirect memory
+(define-pmacro (mov10 name insn opc1 opc2 op1 op2 mode)
+  (dni name
+       (.str name "move" )
+       ((PIPE OS) (IDOC MOVE))
+       (.str insn " [$"op2"+$hash$"uimm16 "],$"op1)
+       (+ opc1 opc2 op1 op2 uimm16)
+       (sequence mode ((mode tmp1))
+          (set mode tmp1 (add HI op1 uimm16))
+          (set mode (mem HI tmp1) op1)
+       )
+       ()
+  )
+)
+(mov10 mov10i mov OP1_12 OP2_4 dr sr HI)
+(mov10 movb10i movb OP1_14 OP2_4 drb sr QI)
+
+;move and indirect memory
+(define-pmacro (mov11 name insn opc1 opc2 op1 op2 mode)
+  (dni name
+       (.str name "move" )
+       ((PIPE OS) (IDOC MOVE))
+       (.str insn " [$"op1 "],$"op2)
+       (+ opc1 opc2 (f-op-lbit4 0) op1 op2)
+       (set (mem mode op1) (mem HI op2))
+       ()
+  )
+)
+(mov11 movri11 mov OP1_8 OP2_4 src2 memory HI)
+(mov11 movbri11 movb OP1_10 OP2_4 src2 memory HI)
+
+;move and indirect memory
+(define-pmacro (mov12 name insn opc1 opc2 op1 op2 mode)
+  (dni name
+       (.str name "move" )
+       ((PIPE OS) (IDOC MOVE))
+       (.str insn " $"op2 ",[$"op1"]")
+       (+ opc1 opc2 (f-op-lbit4 0) op1 op2)
+       (set (mem HI op2) (mem mode op1))
+       ()
+  )
+)
+(mov12 movri12 mov OP1_9 OP2_4 src2 memory HI)
+(mov12 movbri12 movb OP1_11 OP2_4 src2 memory HI)
+
+(define-pmacro (movemem3 name insn opc1 opc2 op1 op2  dir)
+  (dni name 
+       (.str name "move" )
+       ((PIPE OS) (IDOC MOVE))
+       (.str insn " $"op1 ",$hash$"dir"$"op2)
+       (+ opc1 opc2 op1 op2)
+       (set HI op1 op2)
+       ()
+  )
+)
+(movemem3 movehm5 mov OP1_14 OP2_6 regoff8 upof16 "pof")
+(movemem3 movehm6 mov OP1_14 OP2_6 regoff8 upag16 "pag")
+(movemem3 movehm7 mov OP1_14 OP2_6 regoff8 useg16 "segm")
+(movemem3 movehm8 mov OP1_14 OP2_6 regoff8 usof16 "sof")
+
+(define-pmacro (movemem4 name insn opc1 opc2 op1 op2 dir)
+  (dni name 
+       (.str name "move" )
+       ((PIPE OS) (IDOC MOVE))
+       (.str insn " $"op1 ",$hash$"dir"$"op2)
+       (+ opc1 opc2 op1 op2 (f-op-bit8 0))
+       (set QI op1 op2)
+       ()
+  )
+)
+(movemem4 movehm9 movb OP1_14 OP2_7 regb8 uimm8 "pof")
+(movemem4 movehm10 movb OP1_14 OP2_7 regoff8 uimm8 "pag")
+
+(define-pmacro (movemem name insn opc1 opc2 op1 op2 mode dir)
+  (dni name 
+       (.str name "move" )
+       ((PIPE OS) (IDOC MOVE))
+       (.str insn " $"op1 ",$"dir"$"op2)
+       (+ opc1 opc2 op1 op2)
+       (set mode op1 (mem HI op2))
+       ()
+  )
+)
+(movemem movrmp mov OP1_15 OP2_2 regoff8 upof16 HI "pof")
+(movemem movrmp1 movb OP1_15 OP2_3 regb8 upof16 QI "pof")
+(movemem movrmp2 mov OP1_15 OP2_2 regoff8 upag16 HI "pag")
+(movemem movrmp3 movb OP1_15 OP2_3 regb8 upag16 QI "pag")
+
+(define-pmacro (movemem1 name insn opc1 opc2 op1 op2 dir)
+  (dni name 
+       (.str name "move" )
+       ((PIPE OS) (IDOC MOVE))
+       (.str insn " $"dir"$"op1 ",$"op2)
+       (+ opc1 opc2 op2 op1)
+       (set (mem HI op1) op2 )
+       ()
+  )
+)
+(movemem1 movrmp4 mov OP1_15 OP2_6  upof16 regoff8 "pof")
+(movemem1 movrmp5 movb OP1_15 OP2_7 upof16 regb8 "pof")
+
+(define-pmacro (movemem2 name insn opc1 opc2 op1 op2 mode dir)
+  (dni name 
+       (.str name "move" )
+       ((PIPE OS) (IDOC MOVE))
+       (.str insn " $"op1 ",$hash$"dir"$"op2)
+       (+ opc1 opc2 op2 op1)
+       (set mode op1 op2)
+       ()
+  )
+)
+(movemem2 movehm1 mov OP1_14 OP2_0 dri u4 HI "pof")
+(movemem2 movehm2 movb OP1_14 OP2_1 srb u4 QI "pof")
+(movemem2 movehm3 mov OP1_14 OP2_0 dri u4 HI "pag")
+(movemem2 movehm4 movb OP1_14 OP2_1 srb u4 QI "pag")
+
+;move register and direct memory
+(define-pmacro (move12 name insn opc1 opc2 op1 op2 mode)
+  (dni name 
+       (.str name "move" )
+       ((PIPE OS) (IDOC MOVE))
+       (.str insn " $"op1 ",$"op2)
+       (+ opc1 opc2 op1 op2)
+       (set mode op1 (mem HI op2))
+       ()
+  )
+)
+
+;move register and direct memory
+(define-pmacro (move13 name insn opc1 opc2 op1 op2 mode)
+  (dni name 
+       (.str name "move" )
+       ((PIPE OS) (IDOC MOVE))
+       (.str insn " $"op1 ",$"op2)
+       (+ opc1 opc2 op2 op1)
+       (set (mem HI op1) op2)
+       ()
+  )
+)
+(move12 mve12 mov OP1_15 OP2_2 regmem8 memgr8 HI)
+(move13 mve13 mov OP1_15 OP2_6 memgr8 regmem8 HI)
+(move12 mover12 mov OP1_15 OP2_2 reg8 memory HI)
+(move13 mvr13 mov OP1_15 OP2_6 memory reg8 HI)
+(move12 mver12 movb OP1_15 OP2_3 regbmem8 memgr8 QI)
+(move13 mver13 movb OP1_15 OP2_7 memgr8 regbmem8 QI)
+(move12 movr12 movb OP1_15 OP2_3 regb8 memory QI)
+(move13 movr13 movb OP1_15 OP2_7 memory regb8 QI)
+
+; MOVBS Rw,Rb
+(dni movbsrr "mov byte register with sign extension to word register"
+     ((PIPE OS) (IDOC MOVE))
+     "movbs $sr,$drb"
+     (+ OP1_13 OP2_0 drb sr)
+     (sequence ()
+         (if QI (and QI drb (const 128))
+                (set HI sr (or HI (const HI 65280) drb)))
+         (set HI sr (and HI (const HI 255) drb)) 
+     )
+     ()
+)
+
+; MOVBZ Rw,Rb
+(dni movbzrr "mov byte register with zero extension to word register"
+     ((PIPE OS) (IDOC MOVE))
+     "movbz $sr,$drb"
+     (+ OP1_12 OP2_0 drb sr)
+     (set HI sr (and HI (const HI 255) drb))
+     ()
+)
+
+; MOVBS reg,POF mem
+(dni movbsrpofm "mov memory to byte register"
+     ((PIPE OS) (IDOC MOVE))
+     "movbs $regmem8,$pof$upof16"
+     (+ OP1_13 OP2_2 regmem8 upof16)
+     (set QI regmem8 (mem HI upof16))
+     ()
+)
+
+; MOVBS pof,reg
+(dni movbspofmr "mov memory to byte register"
+     ((PIPE OS) (IDOC MOVE))
+     "movbs $pof$upof16,$regbmem8"
+     (+ OP1_13 OP2_5 upof16 regbmem8 )
+     (set QI  (mem HI upof16) regbmem8)
+     ()
+)
+
+; MOVBZ reg,POF mem
+(dni movbzrpofm "mov memory to byte register"
+     ((PIPE OS) (IDOC MOVE))
+     "movbz $reg8,$pof$upof16"
+     (+ OP1_12 OP2_2 reg8 upof16)
+     (set QI reg8 (mem HI upof16))
+     ()
+)
+
+; MOVBZ pof,reg
+(dni movbzpofmr "mov memory to byte register"
+     ((PIPE OS) (IDOC MOVE))
+     "movbz $pof$upof16,$regb8"
+     (+ OP1_12 OP2_5 upof16 regb8 )
+     (set QI  (mem HI upof16) regb8)
+     ()
+)
+
+;move register and direct memory
+(define-pmacro (move14 name insn opc1 opc2 op1 op2 )
+  (dni name 
+       (.str name "move" )
+       ((PIPE OS) (IDOC MOVE))
+       (.str insn " $"op1 ",$"op2)
+       (+ opc1 opc2 op1 op2)
+       (set HI op1 (and HI (const HI 255) (mem QI op2)))
+       ()
+  )
+)
+
+;move register and direct memory
+(define-pmacro (move15 name insn opc1 opc2 op1 op2 )
+  (dni name 
+       (.str name "move" )
+       ((PIPE OS) (IDOC MOVE))
+       (.str insn " $"op1 ",$"op2)
+       (+ opc1 opc2 op2 op1)
+       (set HI (mem HI op1) (and HI (const HI 255) op2))
+       ()
+  )
+)
+(move14 movebs14 movbs OP1_13 OP2_2 regmem8 memgr8 )
+(move15 movebs15 movbs OP1_13 OP2_5 memgr8 regbmem8 )
+(move14 moverbs14 movbs OP1_13 OP2_2 reg8 memory )
+(move15 movrbs15 movbs OP1_13 OP2_5 memory regb8 )
+(move14 movebz14 movbz OP1_12 OP2_2 regmem8 memgr8 )
+(move15 movebz15 movbz OP1_12 OP2_5 memgr8 regbmem8 )
+(move14 moverbz14 movbz OP1_12 OP2_2 reg8 memory )
+(move15 movrbz15 movbz OP1_12 OP2_5 memory regb8 )
+
+
+;mov registers
+(define-pmacro (moveb1 name insn opc1 opc2 op1 op2)
+  (dni name 
+       (.str name "move" )
+       ((PIPE OS) (IDOC MOVE))
+       (.str insn " $"op2 ",$"op1)
+       (+ opc1 opc2 op1 op2)
+       (sequence ()
+           (if QI (and QI op1 (const 128))
+                  (set HI op2 (or HI (const HI 65280) op1)))
+           (set HI op2 (and HI (const HI 255) op1)) 
+       )
+       ()
+  )
+)
+(moveb1 movrbs movbs OP1_13 OP2_0 drb sr )
+(moveb1 movrbz movbz OP1_12 OP2_0 drb sr )
+
+
+
+;jump and call insns
+;******************************************************************
+;Absolute conditional jump
+(define-pmacro (jmpabs name insn)
+  (dni name
+     (.str name "Absolute conditional jump" )
+     ((PIPE OS) (IDOC JMP))
+     (.str insn " $extcond,$caddr")
+     (+ OP1_14 OP2_10 extcond (f-op-bitone 0) bitone bit01 caddr)
+     (sequence ((HI tmp1) (HI tmp2))
+        (set tmp1 (mem HI caddr))
+        (set tmp2 (sub HI pc (mem HI caddr)))
+        (if (gt tmp2 (const 0)) ;; FIXME: (lt tmp2 (const 32)) (eq tmp2 (const 32))
+            (set bitone (const 1)))
+       (if (lt tmp2 (const 0)) ;; FIXME: (eq tmp2 (const 0)) (gt tmp2 (const 32))
+            (set bitone (const 0)))
+        (if (eq extcond (const 1)) ;; FIXME: (ne extcond cc_Z))
+             (set bit01 (const 0))    
+             (set HI pc (mem HI caddr)))
+       (if (ne extcond (const 1)) ;; FIXME: (eq extcond cc_Z))
+             (set bit01 (const 1))
+             (set HI pc (add HI pc (const 2))))
+     )
+     ()
+  )
+)
+
+(jmpabs jmpa0 jmpa+)
+(jmpabs jmpa1 jmpa)
+
+; JMPA- cc,caddr
+(dni jmpa- "Absolute conditional jump"
+     (COND-CTI (PIPE OS) (IDOC JMP))
+     "jmpa- $extcond,$caddr"
+     (+ OP1_14 OP2_10 extcond (f-op-bitone 0) bitone (f-op-1bit 1) caddr)
+     (sequence ((HI tmp1) (HI tmp2))
+        (set tmp1 (mem HI caddr))
+        (set tmp2 (sub HI pc (mem HI caddr)))
+        (if (gt tmp2 (const 0)) ;; FIXME: (lt tmp2 (const 32)) (eq tmp2 (const 32))
+            (set bitone (const 1)))
+       (if (lt tmp2 (const 0)) ;; FIXME: (eq tmp2 (const 0)) (gt tmp2 (const 32))
+            (set bitone (const 0)))
+        (set HI pc (add HI pc (const 2)))
+     )
+     ()
+)
+
+; JMPI cc,[Rwn]
+(dni jmpi "Indirect conditional jump"
+     (COND-CTI (PIPE OS) (IDOC JMP))
+     "jmpi $icond,[$sr]"
+     (+ OP1_9 OP2_12 icond sr)
+     (sequence ()
+        (if (eq icond (const 1))
+             (set HI pc (mem HI sr)))
+             (set HI pc (add HI pc (const 2)))
+     )
+     ()
+)
+
+(define-pmacro (jmprel name insn opc1)
+  (dni name
+       (.str name "conditional" )
+       (COND-CTI (PIPE OS) (IDOC JMP))
+       (.str insn " $cond,$rel")
+       (+ opc1 OP2_13 rel)
+       (sequence ()
+           (if (eq cond (const 1))
+               (sequence ()
+                   (if QI (lt QI rel (const 0))
+                           (sequence ()
+                                ;; FIXME: (neg QI rel)
+                                ;; FIXME: (add QI rel (const 1))
+                                ;; FIXME: (mul QI rel (const 2))
+                                (set HI pc (sub HI pc rel))
+                           ))
+                    (set HI pc (add HI pc (mul QI rel (const 2))))
+               )
+            )
+            (set HI pc pc)
+       )
+       ()
+  )
+)
+
+(jmprel jmpr_nenz jmpr  COND_NE_NZ )
+(jmprel jmpr_sgt jmpr  COND_SGT )
+(jmprel jmpr_z jmpr  COND_Z )
+(jmprel jmpr_v jmpr  COND_V )
+(jmprel jmpr_nv jmpr  COND_NV )
+(jmprel jmpr_n jmpr  COND_N )
+(jmprel jmpr_nn jmpr  COND_NN )
+(jmprel jmpr_c jmpr  COND_C )
+(jmprel jmpr_nc jmpr  COND_NC )
+(jmprel jmpr_eq jmpr  COND_EQ )
+(jmprel jmpr_ne jmpr  COND_NE )
+(jmprel jmpr_ult jmpr  COND_ULT )
+(jmprel jmpr_ule jmpr  COND_ULE )
+(jmprel jmpr_uge jmpr  COND_UGE )
+(jmprel jmpr_ugt jmpr  COND_UGT )
+(jmprel jmpr_sle jmpr  COND_SLE )
+(jmprel jmpr_sge jmpr  COND_SGE )
+(jmprel jmpr_net jmpr  COND_NET )
+(jmprel jmpr_uc jmpr  COND_UC )
+(jmprel jmpr_slt jmpr  COND_SLT )
+
+
+
+
+; JMPS seg,caddr
+(dni jmpseg "absolute inter-segment jump"
+     (UNCOND-CTI(PIPE OS) (IDOC JMP))
+     "jmps $hash$segm$useg8,$hash$sof$usof16"
+     (+ OP1_15 OP2_10 seg usof16)
+     (sequence ()
+          (if QI (eq BI sgtdisbit (const BI 0))
+                 (set QI (reg h-cr 10) useg8))
+                 (nop)
+          (set HI pc usof16)
+     )
+     ()
+)
+
+; JMPS seg,caddr
+(dni jmps "absolute inter-segment jump"
+     (UNCOND-CTI(PIPE OS) (IDOC JMP))
+     "jmps $seg,$caddr"
+     (+ OP1_15 OP2_10 seg caddr)
+     (sequence ()
+          (if QI (eq BI sgtdisbit (const BI 0))
+                 (set QI (reg h-cr 10) seg))
+                 (nop)
+          (set HI pc caddr)
+     )
+     ()
+)
+
+
+;relative jump if bit set
+;JB bitaddrQ.q,rel
+(dni jb "relative jump if bit set"
+     ((PIPE OS) (IDOC JMP))
+     "jb $genreg$dot$qlobit,$relhi"
+     (+ OP1_8 OP2_10 genreg relhi qlobit (f-qhibit 0))
+     (sequence ((HI tmp1) (HI tmp2))
+          (set HI tmp1 genreg)
+          (set HI tmp2 (const 1))
+          (sll HI tmp2 qlobit)
+          (set HI tmp2 (and tmp1 tmp2))
+          (if (eq tmp2 (const 1))
+             (sequence ()
+                (if QI (lt QI relhi (const 0))
+                       (set HI pc (add HI pc (mul QI relhi (const 2)))))
+             ))
+         (set HI pc (add HI pc (const 4))) 
+     )
+     ()
+)
+
+;relative jump if bit set and clear bit
+;JBC bitaddrQ.q,rel
+(dni jbc "relative jump if bit set and clear bit"
+     ((PIPE OS) (IDOC JMP))
+     "jbc $genreg$dot$qlobit,$relhi"
+     (+ OP1_10 OP2_10 genreg relhi qlobit (f-qhibit 0))
+     (sequence ((HI tmp1) (HI tmp2))
+          (set HI tmp1 genreg)
+          (set HI tmp2 (const 1))
+          (sll HI tmp2 qlobit)
+          (set HI tmp2 (and tmp1 tmp2))
+          (if (eq tmp2 (const 1))
+             (sequence ()
+                (if QI (lt QI relhi (const 0))
+                       (set tmp2 (const 1))
+                       (set tmp1 genreg)
+                       ;; FIXME: (sll tmp2 qlobit)
+                       ;; FIXME: (inv tmp2)
+                       (set HI tmp1(and tmp1 tmp2))
+                       (set HI genreg tmp1)
+                       (set HI pc (add HI pc (mul QI relhi (const 2)))))
+             ))
+          (set HI pc (add HI pc (const 4)))
+     )
+     ()
+)
+
+;relative jump if bit set
+;JNB bitaddrQ.q,rel
+(dni jnb "relative jump if bit not set"
+     ((PIPE OS) (IDOC JMP))
+     "jnb $genreg$dot$qlobit,$relhi"
+     (+ OP1_9 OP2_10 genreg relhi qlobit (f-qhibit 0))
+     (sequence ((HI tmp1) (HI tmp2))
+          (set HI tmp1 genreg)
+          (set HI tmp2 (const 1))
+          (sll HI tmp2 qlobit)
+          (set HI tmp2 (and tmp1 tmp2))
+          (if (eq tmp2 (const 0))
+             (sequence ()
+                (if QI (lt QI relhi (const 0))
+                       (set HI pc (add HI pc (mul QI relhi (const 2)))))
+             ))
+          (set HI pc (add HI pc (const 4)))
+     )
+     ()
+)
+
+;relative jump if bit not set and set bit
+;JNBS bitaddrQ.q,rel
+(dni jnbs "relative jump if bit not set and set bit"
+     ((PIPE OS) (IDOC JMP))
+     "jnbs $genreg$dot$qlobit,$relhi"
+     (+ OP1_11 OP2_10 genreg relhi qlobit (f-qhibit 0))
+     (sequence ((HI tmp1) (HI tmp2))
+          (set HI tmp1 genreg)
+          (set HI tmp2 (const 1))
+          (sll HI tmp2 qlobit)
+          (set HI tmp2 (and tmp1 tmp2))
+          (if (eq tmp2 (const 0))
+             (sequence ()
+                (if QI (lt QI relhi (const 0))
+                       (set tmp2 (const 1))
+                       (set tmp1 reg8)
+                       ;; FIXME: (sll tmp2 qbit)
+                       (set BI tmp1(or tmp1 tmp2))
+                       (set HI reg8 tmp1)
+                       (set HI pc (add HI pc (mul QI relhi (const 2)))))
+             ))
+          (set HI pc (add HI pc (const 4)))
+     )
+     ()
+)
+
+
+;Absolute conditional call
+(define-pmacro (callabs name insn)
+  (dni name
+     (.str name "Absolute conditional call" )
+     ((PIPE OS) (IDOC JMP))
+     (.str insn " $extcond,$caddr")
+     (+ OP1_12 OP2_10 extcond (f-op-2bit 0) bit01 caddr)
+     (sequence ()
+        (if (eq extcond (const 1))
+          (set bit01 (const 0))
+          (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
+         (set HI (mem HI (reg h-cr 9)) pc)
+         (set HI pc (mem HI caddr)))
+        (if (ne extcond (const 1))
+          (set bit01 (const 1))
+          (set HI pc (add HI pc (const 2))))
+     )
+     ()
+  )
+)
+
+(callabs calla0 calla+)
+(callabs calla1 calla)
+
+; CALLA- cc,caddr
+(dni calla- "Absolute conditional call"
+     (COND-CTI (PIPE OS) (IDOC JMP))
+     "calla- $extcond,$caddr"
+     (+ OP1_12 OP2_10 extcond (f-op-bit3 1) caddr)
+     (sequence ()
+        (if (eq extcond (const 1))
+          (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
+         (set HI (mem HI (reg h-cr 9)) pc)
+         (set HI pc (mem HI caddr)))
+        (set HI pc (add HI pc (const 2)))
+     )
+     ()
+)
+
+; CALLI cc,[Rwn]
+(dni calli "indirect subroutine call"
+     (COND-CTI (PIPE OS) (IDOC JMP))
+     "calli $icond,[$sr]"
+     (+ OP1_10 OP2_11 icond sr)
+     (sequence ()
+         (if (eq icond (const 1))
+             (sequence ()
+                    (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
+                    (set HI (mem HI (reg h-cr 9)) pc)
+                    (set HI pc (mem HI sr))
+             )
+         )
+         (set HI pc (add HI pc (const 2)))
+     )
+     ()
+)
+
+; CALLR rel
+(dni callr "Call subroutine with PC relative signed 8 bit offset"
+     ( COND-CTI (PIPE OS) (IDOC JMP))
+     "callr $rel"
+     (+ OP1_11 OP2_11 rel)
+     (sequence ()
+          (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
+         (set HI (mem HI (reg h-cr 9)) pc)
+          (sequence ()
+                (if QI (lt QI rel (const 0))
+                       (sequence ()
+                           ;; FIXME: (neg QI rel)
+                           ;; FIXME: (add QI rel (const 1))
+                           ;; FIXME: (mul QI rel (const 2))
+                           (set HI pc (sub HI pc rel))
+                       ))
+                (set HI pc (add HI pc (mul QI rel (const 2))))
+          )
+      )
+      ()
+)
+
+
+; CALLS seg,caddr
+(dni callseg "call inter-segment subroutine"
+     (UNCOND-CTI (PIPE OS) (IDOC JMP))
+     "calls $hash$segm$useg8,$hash$sof$usof16"
+     (+ OP1_13 OP2_10 useg8 usof16)
+     (sequence ()
+          (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
+          (set HI (mem HI (reg h-cr 9)) (reg h-cr 10))
+          (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
+          (set HI (mem HI (reg h-cr 9)) pc)
+          (if QI (eq BI sgtdisbit (const BI 0))
+                 (set QI (reg h-cr 10) useg8))
+                 (nop)
+          (set HI pc usof16)
+     )
+     ()
+)
+
+; CALLS seg,caddr
+(dni calls "call inter-segment subroutine"
+     (UNCOND-CTI (PIPE OS) (IDOC JMP))
+     "calls $seg,$caddr"
+     (+ OP1_13 OP2_10 seg caddr)
+     (sequence ()
+          (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
+          (set HI (mem HI (reg h-cr 9)) (reg h-cr 10))
+          (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
+          (set HI (mem HI (reg h-cr 9)) pc)
+          (if QI (eq BI sgtdisbit (const BI 0))
+                 (set QI (reg h-cr 10) seg))
+                 (nop)
+          (set HI pc caddr)
+     )
+     ()
+)
+
+; PCALL reg,caddr
+(dni pcall "push word and call absolute subroutine"
+       (UNCOND-CTI (PIPE OS) (IDOC JMP))
+       "pcall $reg8,$caddr"
+       (+ OP1_14 OP2_2 reg8 caddr)
+       (sequence ((HI tmp1))
+            (set HI tmp1 reg8)
+           (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
+           (set HI (mem HI (reg h-cr 9)) tmp1)
+           (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
+           (set HI (mem HI (reg h-cr 9)) pc)
+            (set HI pc caddr)
+       )
+       ()
+)
+
+; TRAP #uimm7
+(dni trap "software trap"
+       (UNCOND-CTI (PIPE OS) (IDOC JMP))
+       "trap $hash$uimm7"
+       (+ OP1_9 OP2_11 uimm7 (f-op-1bit 0))
+       (sequence ()
+           (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
+            (set HI (mem HI (reg h-cr 9)) (reg h-cr 4))
+              (if QI (eq BI sgtdisbit (const BI 0))
+                     (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
+                     (set HI (mem HI (reg h-cr 9)) (reg h-cr 10) )
+              )
+              (nop)
+            (set HI (reg h-cr 10) (reg h-cr 11))
+            (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
+            (set HI (mem HI (reg h-cr 9)) pc)
+            (set HI pc (mul QI uimm7 (const 4)))
+       )
+       ()
+)
+
+;Return insns
+; RET
+(dni ret "return from subroutine"
+       (UNCOND-CTI (PIPE OS) (IDOC JMP))
+       "ret"
+       (+ OP1_12 OP2_11 (f-op-bit8 0))
+       (sequence ()
+           (set HI pc (mem HI (reg h-cr 9)))
+           (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
+       )
+       ()
+)
+
+; RETS 
+(dni rets "return from inter-segment sunroutine"
+       (UNCOND-CTI (PIPE OS) (IDOC JMP))
+       "rets"
+       (+ OP1_13 OP2_11 (f-op-bit8 0))
+       (sequence ()
+           (set HI pc (mem HI (reg h-cr 9)))
+           (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
+              (if QI (eq BI sgtdisbit (const BI 0))
+                     (set HI (reg h-cr 10) (mem HI (reg h-cr 9)))
+              )
+              (nop)
+          (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
+       )
+       ()
+)
+
+; RETP reg
+(dni retp "return from subroutine and pop word register"
+       (UNCOND-CTI (PIPE OS) (IDOC JMP))
+       "retp $reg8"
+       (+ OP1_14 OP2_11 reg8)
+       (sequence ((HI tmp1))
+            (set HI pc (mem HI (reg h-cr 9)))
+            (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
+           (set HI tmp1 (mem HI (reg h-cr 9)))
+            (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
+            (set HI reg8 tmp1)
+       )
+       ()
+)
+
+; RETI
+(dni reti "return from ISR"
+       (UNCOND-CTI (PIPE OS) (IDOC JMP))
+       "reti"
+       (+ OP1_15 OP2_11 (f-op-lbit4 8) (f-op-bit4 8))
+       (sequence ()
+           (set HI pc (mem HI (reg h-cr 9)))
+           (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
+              (if QI (eq BI sgtdisbit (const BI 0))
+                  (sequence ()
+                       (set HI (reg h-cr 10) (mem HI (reg h-cr 9)))
+                       (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
+                  )
+              )
+              (nop)
+           (set HI (reg h-cr 4) (mem HI (reg h-cr 9)))
+          (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
+       )
+       ()
+)
+
+;stack operation insn
+;******************************************************************
+; POP reg
+(dni pop "restore register from system stack"
+     ((PIPE OS) (IDOC MISC))
+     "pop $reg8"
+     (+ OP1_15 OP2_12 reg8)
+     (sequence ((HI tmp1))
+          (set HI tmp1 (mem HI (reg h-cr 9)))
+          (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))         
+           (set HI reg8 tmp1)
+     )
+     ()
+)
+
+; PUSH reg
+(dni push "save register on system stack"
+     ((PIPE OS) (IDOC MISC))
+     "push $reg8"
+     (+ OP1_14 OP2_12 reg8)
+     (sequence ((HI tmp1))
+          (set HI tmp1 reg8)
+          (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))         
+           (set HI (mem HI (reg h-cr 9)) tmp1)
+     )
+     ()
+)
+
+;context switching insns
+; SCXT reg,#data16
+(dni scxti "Push word register on stack and update same with immediate data"
+     ((PIPE OS) (IDOC MISC))
+     "scxt $reg8,$hash$uimm16"
+     (+ OP1_12 OP2_6 reg8 uimm16)
+     (sequence ((HI tmp1) (HI tmp2))
+         (set HI tmp1 reg8)
+         (set HI tmp2 uimm16)
+         ;; FIXME: (sub HI (reg HI h-cr 9) (const 2))
+         (set HI (reg HI h-cr 9) tmp1)
+         (set HI reg8 tmp2)
+     )
+     ()
+)
+
+; SCXT reg,POF mem
+(dni scxtrpofm "mov memory to byte register"
+     ((PIPE OS) (IDOC MOVE))
+     "scxt $reg8,$pof$upof16"
+     (+ OP1_13 OP2_6 reg8 upof16)
+     (set QI reg8 (mem HI upof16))
+     ()
+)
+
+; SCXT regmem8,memgr8
+(dni scxtmg "Push word register on stack and update same with direct memory"
+     ((PIPE OS) (IDOC MISC))
+     "scxt $regmem8,$memgr8"
+     (+ OP1_13 OP2_6 regmem8 memgr8)
+     (sequence ((HI tmp1) (HI tmp2))
+         (set HI tmp1 regmem8)
+         (set HI tmp2 memgr8)
+         ;; FIXME: (sub HI (reg HI h-cr 9) (const 2))
+         (set HI (reg HI h-cr 9) tmp1)
+         (set HI regmem8 tmp2)
+     )
+     ()
+)
+
+; SCXT reg,mem
+(dni scxtm "Push word register on stack and update same with direct memory"
+     ((PIPE OS) (IDOC MISC))
+     "scxt $reg8,$memory"
+     (+ OP1_13 OP2_6 reg8 memory)
+     (sequence ((HI tmp1) (HI tmp2))
+         (set HI tmp1 reg8)
+         (set HI tmp2 memory)
+         ;; FIXME: (sub HI (reg HI h-cr 9) (const 2))
+         (set HI (reg HI h-cr 9) tmp1)
+         (set HI reg8 tmp2)
+     )
+     ()
+)
+
+;No operation
+; NOP 
+(dni nop "nop"
+     ((PIPE OS) (IDOC MISC))
+     "nop"
+     (+ OP1_12 OP2_12 (f-op-bit8 0))
+     ()
+     ()
+)
+
+;*********system control instructions *********************/
+
+(define-pmacro (sysctrl name insn opc1 opc2 op1 op2 op3)
+  (dni name 
+       (.str name "miscellaneous" )
+       ((PIPE OS) (IDOC MISC))
+       (.str insn )
+       (+ opc1 opc2 (f-op-lbit4 op1) (f-op-bit4 op2) (f-data8 op3) (f-op-bit8 op3))
+       ()
+       ()
+  )
+)
+(sysctrl srstm srst  OP1_11 OP2_7 4 8 183 )
+(sysctrl idlem idle  OP1_8 OP2_7 7 8 135)
+(sysctrl pwrdnm pwrdn  OP1_9 OP2_7 6 8 151)
+(sysctrl diswdtm diswdt  OP1_10 OP2_5 5 10 165)
+(sysctrl enwdtm enwdt  OP1_8 OP2_5 7 10 133)
+(sysctrl einitm einit  OP1_11 OP2_5 4 10 181)
+(sysctrl srvwdtm srvwdt  OP1_10 OP2_7 5 8 167 )
+
+;s/w brk
+; SBRK 
+(dni sbrk "sbrk"
+     ((PIPE OS) (IDOC MISC))
+     "sbrk"
+     (+ OP1_8 OP2_12 (f-op-bit8 0))
+     ()
+     ()
+)
+
+; atomic sequence
+; ATOMIC #irang2
+(dni atomic "begin atomic sequence"
+     ((PIPE OS) (IDOC SYSC))
+     "atomic $hash$uimm2"
+     (+ OP1_13 OP2_1 (f-op-lbit2 0) uimm2 (f-op-bit4 0))
+     (sequence ((HI count))
+         (set HI count uimm2)
+          (cond HI
+           ((ne HI count (const 0))
+           (sequence ()
+              (set HI pc (add HI pc (const 2)))
+               (set HI count (sub HI count (const 1)))
+            ))
+          )
+          (set HI count (const 0))
+      )
+      ()
+)
+
+;extended register sequence
+; EXTR #irang2
+(dni extr "begin extended register sequence"
+     ((PIPE OS) (IDOC SYSC))
+     "extr $hash$uimm2"
+     (+ OP1_13 OP2_1 (f-op-lbit2 2) uimm2 (f-op-bit4 0))
+     (sequence ((HI count))
+         (set HI count uimm2)
+          (cond HI
+           ((ne HI count (const 0))
+           (sequence ()
+              (set HI pc (add HI pc (const 2)))
+               (set HI count (sub HI count (const 1)))
+            ))
+          )
+          (set HI count (const 0))
+      )
+      ()
+)
+
+;extended page sequence
+; EXTP Rw,#irang2
+(dni extp "begin extended page sequence"
+     ((PIPE OS) (IDOC SYSC))
+     "extp $sr,$hash$uimm2"
+     (+ OP1_13 OP2_12 (f-op-lbit2 1) uimm2 sr)
+     (sequence ((HI count))
+         (set HI count uimm2)
+          (cond HI
+           ((ne HI count (const 0))
+           (sequence ()
+              (set HI pc (add HI pc (const 2)))
+               (set HI count (sub HI count (const 1)))
+            ))
+          )
+          (set HI count (const 0))
+      )
+      ()
+)
+
+;extended page sequence
+; EXTP #pag10,#irang2
+(dni extp1 "begin extended page sequence"
+     ((PIPE OS) (IDOC SYSC))
+     "extp $hash$pagenum,$hash$uimm2"
+     (+ OP1_13 OP2_7 (f-op-lbit2 1) uimm2 (f-op-bit4 0) pagenum (f-qlobit 0) (f-qlobit2 0))
+     (sequence ((HI count))
+         (set HI count uimm2)
+          (cond HI
+           ((ne HI count (const 0))
+           (sequence ()
+              (set HI pc (add HI pc (const 2)))
+               (set HI count (sub HI count (const 1)))
+            ))
+          )
+          (set HI count (const 0))
+      )
+      ()
+)
+
+; EXTP #pag10,#irang2
+(dni extpg1 "begin extended page sequence"
+     ((PIPE OS) (IDOC SYSC))
+     "extp $hash$pag$upag16,$hash$uimm2"
+     (+ OP1_13 OP2_7 (f-op-lbit2 1) uimm2 (f-op-bit4 0) upag16 )
+     (sequence ((HI count))
+         (set HI count uimm2)
+          (cond HI
+           ((ne HI count (const 0))
+           (sequence ()
+              (set HI pc (add HI pc (const 2)))
+               (set HI count (sub HI count (const 1)))
+            ))
+          )
+          (set HI count (const 0))
+      )
+      ()
+)
+
+;extended page and register sequence
+; EXTPR Rw,#irang2
+(dni extpr "begin extended page and register sequence"
+     ((PIPE OS) (IDOC SYSC))
+     "extpr $sr,$hash$uimm2"
+     (+ OP1_13 OP2_12 (f-op-lbit2 3) uimm2 sr)
+     (sequence ((HI count))
+         (set HI count uimm2)
+          (cond HI
+           ((ne HI count (const 0))
+           (sequence ()
+              (set HI pc (add HI pc (const 2)))
+               (set HI count (sub HI count (const 1)))
+            ))
+          )
+          (set HI count (const 0))
+      )
+      ()
+)
+
+;extended page and register sequence
+; EXTPR #pag10,#irang2
+(dni extpr1 "begin extended page sequence"
+     ((PIPE OS) (IDOC SYSC))
+     "extpr $hash$pagenum,$hash$uimm2"
+     (+ OP1_13 OP2_7 (f-op-lbit2 3) uimm2 (f-op-bit4 0) pagenum (f-qlobit 0) (f-qlobit2 0))
+     (sequence ((HI count))
+         (set HI count uimm2)
+          (cond HI
+           ((ne HI count (const 0))
+           (sequence ()
+              (set HI pc (add HI pc (const 2)))
+               (set HI count (sub HI count (const 1)))
+            ))
+          )
+          (set HI count (const 0))
+      )
+      ()
+)
+
+;extended segment sequence
+; EXTS Rw,#irang2
+(dni exts "begin extended segment sequence"
+     ((PIPE OS) (IDOC SYSC))
+     "exts $sr,$hash$uimm2"
+     (+ OP1_13 OP2_12 (f-op-lbit2 0) uimm2 sr)
+     (sequence ((HI count))
+         (set HI count uimm2)
+          (cond HI
+           ((ne HI count (const 0))
+           (sequence ()
+              (set HI pc (add HI pc (const 2)))
+               (set HI count (sub HI count (const 1)))
+            ))
+          )
+          (set HI count (const 0))
+      )
+      ()
+)
+
+;extended segment sequence
+; EXTS #seg8,#irang2
+(dni exts1 "begin extended segment sequence"
+     ((PIPE OS) (IDOC SYSC))
+     "exts $hash$seghi8,$hash$uimm2"
+     (+ OP1_13 OP2_7 (f-op-lbit2 0) uimm2 (f-op-bit4 0) seghi8 (f-op-bit8 0))
+     (sequence ((HI count))
+         (set HI count uimm2)
+          (cond HI
+           ((ne HI count (const 0))
+           (sequence ()
+              (set HI pc (add HI pc (const 2)))
+               (set HI count (sub HI count (const 1)))
+            ))
+          )
+          (set HI count (const 0))
+      )
+      ()
+)
+
+;extended segment register sequence
+; EXTSR Rwm,#irang2
+(dni extsr "begin extended segment and register sequence"
+     ((PIPE OS) (IDOC SYSC))
+     "extsr $sr,$hash$uimm2"
+     (+ OP1_13 OP2_12 (f-op-lbit2 2) uimm2 sr)
+     (sequence ((HI count))
+         (set HI count uimm2)
+          (cond HI
+           ((ne HI count (const 0))
+           (sequence ()
+              (set HI pc (add HI pc (const 2)))
+               (set HI count (sub HI count (const 1)))
+            ))
+          )
+          (set HI count (const 0))
+      )
+      ()
+)
+
+;extended segment register sequence
+; EXTSR #pag10,#irang2
+(dni extsr1 "begin extended segment and register sequence"
+     ((PIPE OS) (IDOC SYSC))
+     "extsr $hash$seghi8,$hash$uimm2"
+     (+ OP1_13 OP2_7 (f-op-lbit2 2) uimm2 (f-op-bit4 0) seghi8 (f-op-bit8 0))
+     (sequence ((HI count))
+         (set HI count uimm2)
+          (cond HI
+           ((ne HI count (const 0))
+           (sequence ()
+              (set HI pc (add HI pc (const 2)))
+               (set HI count (sub HI count (const 1)))
+            ))
+          )
+          (set HI count (const 0))
+      )
+      ()
+)
+
+;prioritize register
+;PRIOR Rwn,Rwm
+(dni prior "add registers"
+     ((PIPE OS) (IDOC ALU))
+     "prior $dr,$sr"
+     (+ OP1_2 OP2_11 dr sr)
+     (sequence ((HI count) (HI tmp1) (HI tmp2))
+         (set HI count (const 0))
+         (set HI tmp1 sr)
+         (set HI tmp2 (and tmp1 (const 32768)))
+          (cond HI
+           ((ne HI tmp2 (const 1)) (ne HI sr (const 0))
+              (sll HI tmp1 (const 1))
+               (set HI tmp2 (and tmp1 (const 32768)))
+               (set HI count (add HI count (const 1)))
+            )
+           )        
+           (set HI dr count)
+      )
+      ()
+)
+
+
+;bit instructions
+;******************************************************************
+;bit clear
+(define-pmacro (bclear name insn opc1)
+  (dni name
+     (.str name "bit clear" )
+     ((PIPE OS) (IDOC ALU))
+     (.str insn " $reg8$dot$qbit")
+     (+ opc1 OP2_14 reg8)
+     (sequence ((HI tmp1) (HI tmp2))
+     (set tmp2 (const 1))
+     (set tmp1 reg8)
+     ;; FIXME: (sll tmp2 qbit)
+     ;; FIXME: (inv tmp2)
+     (set BI tmp1(and tmp1 tmp2))
+     (set HI reg8 tmp1))
+     ()
+  )
+)
+
+;clear direct bit
+(dni bclr18 "bit logical MOVN"
+     ((PIPE OS) (IDOC ALU))
+     "bclr $RegNam"
+     (+ OP1_11 OP2_14 RegNam)
+     (sequence ((HI tmp1) (HI tmp2))
+     (set tmp2 (const 1))
+     (set tmp1 reg8)
+     ;; FIXME: (sll tmp2 qbit)
+     ;; FIXME: (inv tmp2)
+     (set BI tmp1(and tmp1 tmp2))
+     (set HI reg8 tmp1))
+     ()
+)
+
+
+(bclear bclr0 bclr  QBIT_0 )
+(bclear bclr1 bclr  QBIT_1 )
+(bclear bclr2 bclr  QBIT_2 )
+(bclear bclr3 bclr  QBIT_3 )
+(bclear bclr4 bclr  QBIT_4 )
+(bclear bclr5 bclr  QBIT_5 )
+(bclear bclr6 bclr  QBIT_6 )
+(bclear bclr7 bclr  QBIT_7 )
+(bclear bclr8 bclr  QBIT_8 )
+(bclear bclr9 bclr  QBIT_9 )
+(bclear bclr10 bclr  QBIT_10 )
+(bclear bclr11 bclr  QBIT_11 )
+(bclear bclr12 bclr  QBIT_12 )
+(bclear bclr13 bclr  QBIT_13 )
+(bclear bclr14 bclr  QBIT_14 )
+(bclear bclr15 bclr  QBIT_15 )
+
+;set direct bit
+(dni bset19 "bit logical MOVN"
+     ((PIPE OS) (IDOC ALU))
+     "bset $RegNam"
+     (+ OP1_11 OP2_15 RegNam)
+     (sequence ((HI tmp1) (HI tmp2))
+     (set tmp2 (const 1))
+     (set tmp1 reg8)
+     ;; FIXME: (sll tmp2 qbit)
+     (set BI tmp1(or tmp1 tmp2))
+     (set HI reg8 tmp1))
+     ()
+)
+
+;bit set
+(define-pmacro (bitset name insn opc1)
+  (dni name
+     (.str name "bit set" )
+     ((PIPE OS) (IDOC ALU))
+     (.str insn " $reg8$dot$qbit")
+     (+ opc1 OP2_15 reg8)
+     (sequence ((HI tmp1) (HI tmp2))
+     (set tmp2 (const 1))
+     (set tmp1 reg8)
+     ;; FIXME: (sll tmp2 qbit)
+     (set BI tmp1(or tmp1 tmp2))
+     (set HI reg8 tmp1))
+     ()
+  )
+)
+
+
+(bitset bset0 bset  QBIT_0 )
+(bitset bset1 bset  QBIT_1 )
+(bitset bset2 bset  QBIT_2 )
+(bitset bset3 bset  QBIT_3 )
+(bitset bset4 bset  QBIT_4 )
+(bitset bset5 bset  QBIT_5 )
+(bitset bset6 bset  QBIT_6 )
+(bitset bset7 bset  QBIT_7 )
+(bitset bset8 bset  QBIT_8 )
+(bitset bset9 bset  QBIT_9 )
+(bitset bset10 bset  QBIT_10 )
+(bitset bset11 bset  QBIT_11 )
+(bitset bset12 bset  QBIT_12 )
+(bitset bset13 bset  QBIT_13 )
+(bitset bset14 bset  QBIT_14 )
+(bitset bset15 bset  QBIT_15 )
+
+;mov direct bit
+;BMOV bitaddrZ.z,bitaddrQ.q
+(dni bmov "bit logical MOV"
+     ((PIPE OS) (IDOC ALU))
+     "bmov $reghi8$dot$qhibit,$reg8$dot$qlobit"
+     (+ OP1_4 OP2_10 reg8 reghi8 qhibit qlobit)
+     (sequence ((HI tmp1) (HI tmp2) (HI tmp3) (HI tmp4))
+     (set HI tmp1 reghi8)
+     (set HI tmp2 reg8)
+     (set tmp3 (const 1))
+     (set tmp4 (const 1))
+     ;; FIXME: (sll tmp3 qlobit)
+     ;; FIXME: (sll tmp4 qhibit)
+     ;; FIXME: (and tmp1 tmp3)
+     ;; FIXME: (and tmp2 tmp4)
+     (set BI tmp1 tmp2)
+     (set HI reghi8 tmp1)
+     (set HI reg8 tmp2))
+     ()
+)
+
+;movn direct bit
+;BMOVN bitaddrZ.z,bitaddrQ.q
+(dni bmovn "bit logical MOVN"
+     ((PIPE OS) (IDOC ALU))
+     "bmovn $reghi8$dot$qhibit,$reg8$dot$qlobit"
+     (+ OP1_3 OP2_10 reg8 reghi8 qhibit qlobit)
+     (sequence ((HI tmp1) (HI tmp2) (HI tmp3) (HI tmp4))
+     (set HI tmp1 reghi8)
+     (set HI tmp2 reg8)
+     (set tmp3 (const 1))
+     (set tmp4 (const 1))
+     ;; FIXME: (sll tmp3 qlobit)
+     ;; FIXME: (sll tmp4 qhibit)
+     ;; FIXME: (and tmp1 tmp3)
+     ;; FIXME: (and tmp2 tmp4)
+     ;; FIXME: (inv HI tmp2)
+     (set BI tmp1 tmp2)
+     (set HI reghi8 tmp1)
+     (set HI reg8 tmp2))
+     ()
+)
+
+;and direct bit
+;BAND bitaddrZ.z,bitaddrQ.q
+(dni band "bit logical AND"
+     ((PIPE OS) (IDOC ALU))
+     "band $reghi8$dot$qhibit,$reg8$dot$qlobit"
+     (+ OP1_6 OP2_10 reg8 reghi8 qhibit qlobit)
+     (sequence ((HI tmp1) (HI tmp2) (HI tmp3) (HI tmp4))
+     (set HI tmp1 reghi8)
+     (set HI tmp2 reg8)
+     (set tmp3 (const 1))
+     (set tmp4 (const 1))
+     ;; FIXME: (sll tmp3 qlobit)
+     ;; FIXME: (sll tmp4 qhibit)
+     ;; FIXME: (and tmp1 tmp3)
+     ;; FIXME: (and tmp2 tmp4)
+     (set BI tmp1(and tmp1 tmp2))
+     (set HI reghi8 tmp1)
+     (set HI reg8 tmp2))
+     ()
+)
+
+;or direct bit
+;BOR bitaddrZ.z,bitaddrQ.q
+(dni bor "bit logical OR"
+     ((PIPE OS) (IDOC ALU))
+     "bor $reghi8$dot$qhibit,$reg8$dot$qlobit"
+     (+ OP1_5 OP2_10 reg8 reghi8 qhibit qlobit)
+     (sequence ((HI tmp1) (HI tmp2) (HI tmp3) (HI tmp4))
+     (set HI tmp1 reghi8)
+     (set HI tmp2 reg8)
+     (set tmp3 (const 1))
+     (set tmp4 (const 1))
+     ;; FIXME: (sll tmp3 qlobit)
+     ;; FIXME: (sll tmp4 qhibit)
+     ;; FIXME: (and tmp1 tmp3)
+     ;; FIXME: (and tmp2 tmp4)
+     (set BI tmp1(or tmp1 tmp2))
+     (set HI reghi8 tmp1)
+     (set HI reg8 tmp2))
+     ()
+)
+
+;xor direct bit
+;BXOR bitaddrZ.z,bitaddrQ.q
+(dni bxor "bit logical XOR"
+     ((PIPE OS) (IDOC ALU))
+     "bxor $reghi8$dot$qhibit,$reg8$dot$qlobit"
+     (+ OP1_7 OP2_10 reg8 reghi8 qhibit qlobit)
+     (sequence ((HI tmp1) (HI tmp2) (HI tmp3) (HI tmp4))
+     (set HI tmp1 reghi8)
+     (set HI tmp2 reg8)
+     (set tmp3 (const 1))
+     (set tmp4 (const 1))
+     ;; FIXME: (sll tmp3 qlobit)
+     ;; FIXME: (sll tmp4 qhibit)
+     ;; FIXME: (and tmp1 tmp3)
+     ;; FIXME: (and tmp2 tmp4)
+     (set BI tmp1(xor tmp1 tmp2))
+     (set HI reghi8 tmp1)
+     (set HI reg8 tmp2))
+     ()
+)
+
+;cmp direct bit to bit
+;BCMP bitaddrZ.z,bitaddrQ.q
+(dni bcmp "bit to bit compare"
+     ((PIPE OS) (IDOC ALU))
+     "bcmp $reghi8$dot$qhibit,$reg8$dot$qlobit"
+     (+ OP1_2 OP2_10 reg8 reghi8 qhibit qlobit)
+     (sequence ((HI tmp1) (HI tmp2) (HI tmp3) (HI tmp4))
+     (set HI tmp1 reghi8)
+     (set HI tmp2 reg8)
+     (set tmp3 (const 1))
+     (set tmp4 (const 1))
+     ;; FIXME: (sll tmp3 qlobit)
+     ;; FIXME: (sll tmp4 qhibit)
+     ;; FIXME: (and tmp1 tmp3)
+     ;; FIXME: (and tmp2 tmp4)
+     (set BI tmp1(xor tmp1 tmp2))
+     (set HI reghi8 tmp1)
+     (set HI reg8 tmp2))
+     ()
+)
+
+;bit field low byte
+;BFLDL op1,op2,op3
+(dni bfldl "bit field low byte"
+     ((PIPE OS) (IDOC MOVE))
+     "bfldl $reg8,$hash$mask8,$hash$datahi8"
+     (+ OP1_0 OP2_10 reg8 mask8 datahi8)
+     (sequence ((HI tmp1) (QI tmp2) (QI tmp3))
+     (set HI tmp1 reg8)
+     (set QI tmp2 mask8)
+     (set QI tmp3 datahi8)
+     ;; FIXME: (inv QI tmp2)
+     (set HI tmp1 (and tmp1 tmp2))
+     (set HI tmp1 (or tmp1 tmp3))
+     (set HI reg8 tmp1)
+     )
+     ()
+)
+
+;bit field high byte
+;BFLDH op1,op2,op3
+(dni bfldh "bit field high byte"
+     ((PIPE OS) (IDOC MOVE))
+     "bfldh $reg8,$hash$masklo8,$hash$data8"
+     (+ OP1_1 OP2_10 reg8 masklo8 data8)
+     (sequence ((HI tmp1) (HI tmp2) (HI tmp3))
+            (set HI tmp1 reg8)
+            (set QI tmp2 masklo8)
+            (set HI tmp3 data8)
+            ;; FIXME: (sll tmp2 (const 8))
+            ;; FIXME: (inv HI tmp2)
+            ;; FIXME: (sll tmp3 (const 8))
+            (set HI tmp1 (and tmp1 tmp2))
+            (set HI tmp1 (or tmp1 tmp3))
+            (set HI reg8 tmp1)
+     )
+     ()
+)
+
+;/**********compare instructions******************
+
+;Compare register
+;CMP Rwn,Rwm
+(dni cmpr "compare two registers"
+     ((PIPE OS) (IDOC CMP))
+     "cmp $src1,$src2"
+     (+ OP1_4 OP2_0 src1 src2)
+     (set condbit (lt HI src1 src2))
+     ()
+)
+
+;Compare byte register
+;CMPB Rbn,Rbm
+(dni cmpbr "compare two byte registers"
+     ((PIPE OS) (IDOC CMP))
+     "cmpb $drb,$srb"
+     (+ OP1_4 OP2_1 drb srb)
+     (set condbit (lt QI drb srb))
+     ()
+)
+
+(define-pmacro (cmp1 name insn opc1 opc2 op1 op2 mode)
+  (dni name 
+       (.str name "compare" )
+       ((PIPE OS) (IDOC CMP))
+       (.str insn " $"op1 ",$hash$"op2)
+       (+ opc1 opc2 op1 (f-op-bit1 0) op2)
+       (set condbit (lt mode op1 op2))
+       ()
+  )
+)
+(cmp1 cmpri cmp OP1_4 OP2_8 src1 uimm3 HI)
+(cmp1 cmpbri cmpb OP1_4 OP2_9 drb uimm3 QI)
+
+; CMP Rwn,#data16
+(dni cmpi "compare"
+     ((PIPE OS) (IDOC CMP))
+     "cmp $reg8,$hash$uimm16"
+     (+ OP1_4 OP2_6 reg8 uimm16)
+     (set condbit (lt HI reg8 uimm16))
+     ()
+)
+
+; CMPB reg,#data8
+(dni cmpbi "compare"
+     ((PIPE OS) (IDOC CMP))
+     "cmpb $regb8,$hash$uimm8"
+     (+ OP1_4 OP2_7 regb8 uimm8 (f-op-bit8 0))
+     (set condbit (lt QI regb8 uimm8))
+     ()
+)
+
+;compare reg and indirect memory
+(define-pmacro (cmp2 name insn opc1 opc2 op1 op2 mode)
+  (dni name
+       (.str name "compare" )
+       ((PIPE OS) (IDOC CMP))
+       (.str insn " $"op1 ",[$"op2"]")
+       (+ opc1 opc2 op1 (f-op-bit2 2) op2)
+       (set condbit (lt mode op1 op2))
+       ()
+  )
+)
+(cmp2 cmpr2 cmp OP1_4 OP2_8 dr sr2 HI)
+(cmp2 cmpbr2 cmpb OP1_4 OP2_9 drb sr2 QI)
+
+;compare register and indirect memory post increment
+(define-pmacro (cmp3 name insn opc1 opc2 op1 op2 mode)
+  (dni name
+       (.str name "compare" )
+       ((PIPE OS) (IDOC CMP))
+       (.str insn " $"op1 ",[$"op2"+]")
+       (+ opc1 opc2 op1 (f-op-bit2 3) op2)
+       (sequence ()
+          (set condbit (lt mode op1 op2))
+         (set HI op2 (add HI op2 (const 2)))
+       )
+       ()
+  )
+)
+(cmp3 cmp2i cmp OP1_4 OP2_8 dr sr2 HI)
+(cmp3 cmpb2i cmpb OP1_4 OP2_9 drb sr2 QI)
+
+;compare register and direct memory
+(define-pmacro (cmp4 name insn opc1 opc2 op1 op2 mode)
+  (dni name 
+       (.str name "compare" )
+       ((PIPE OS) (IDOC CMP))
+       (.str insn " $"op1 ",$pof$"op2)
+       (+ opc1 opc2 op1 op2)
+       (set condbit (lt HI op1 (mem HI op2)))
+       ()
+  )
+)
+(cmp4 cmp04 cmp OP1_4 OP2_2 reg8 upof16 HI)
+(cmp4 cmpb4 cmpb OP1_4 OP2_3 regb8 upof16 QI)
+
+;compare register and direct memory
+(define-pmacro (cmp4 name insn opc1 opc2 op1 op2 mode)
+  (dni name 
+       (.str name "compare" )
+       ((PIPE OS) (IDOC CMP))
+       (.str insn " $"op1 ",$"op2)
+       (+ opc1 opc2 op1 op2)
+       (set condbit (lt HI op1 (mem HI op2)))
+       ()
+  )
+)
+(cmp4 cmp004 cmp OP1_4 OP2_2 regmem8 memgr8 HI)
+(cmp4 cmp0004 cmp OP1_4 OP2_2 reg8 memory HI)
+(cmp4 cmpb04 cmpb OP1_4 OP2_3 regbmem8 memgr8 QI)
+(cmp4 cmpb004 cmpb OP1_4 OP2_3 regb8 memory QI)
+
+;compare register and immediate
+(define-pmacro (cmp5 name insn opc1 opc2 op1 op2 mode)
+  (dni name 
+       (.str name "compare" )
+       ((PIPE OS) (IDOC CMP))
+       (.str insn " $"op1 ",$hash$"op2)
+       (+ opc1 opc2 op2 op1)
+       (sequence ()
+            (set condbit (lt HI op1 op2))
+           (set mode op1 (sub HI op1 (const 1)))
+       )     
+       ()
+  )
+)
+(cmp5 cmpd1ri cmpd1  OP1_10 OP2_0 sr uimm4 HI)
+(cmp5 cmpd2ri cmpd2  OP1_11 OP2_0 sr uimm4 HI)
+(cmp5 cmpi1ri cmpi1  OP1_8 OP2_0 sr uimm4 HI)
+(cmp5 cmpi2ri cmpi2  OP1_9 OP2_0 sr uimm4 HI)
+(cmp5 cmpd1rim cmpd1  OP1_10 OP2_6 reg8 uimm16 HI)
+(cmp5 cmpd2rim cmpd2  OP1_11 OP2_6 reg8 uimm16 HI)
+(cmp5 cmpi1rim cmpi1  OP1_8 OP2_6 reg8 uimm16 HI)
+(cmp5 cmpi2rim cmpi2  OP1_9 OP2_6 reg8 uimm16 HI)
+
+;compare register and direct memory
+(define-pmacro (cmp6 name insn opc1 opc2 op1 op2 mode )
+  (dni name 
+       (.str name "compare" )
+       ((PIPE OS) (IDOC CMP))
+       (.str insn " $"op1 ",$pof$"op2)
+       (+ opc1 opc2 op1 op2)
+       (sequence ()
+            (set condbit (lt HI op1 (mem HI op2)))
+           (set mode op1 (sub HI op1 (const 1)))
+       )    
+       ()
+  )
+)
+(cmp6 cmpd1rp cmpd1  OP1_10 OP2_2 reg8 upof16 HI )
+(cmp6 cmpd2rp cmpd2  OP1_11 OP2_2 reg8 upof16 HI )
+(cmp6 cmpi1rp cmpi1  OP1_8 OP2_2 reg8 upof16 HI )
+(cmp6 cmpi2rp cmpi2  OP1_9 OP2_2 reg8 upof16 HI )
+
+;compare register and direct memory
+(define-pmacro (cmp7 name insn opc1 opc2 op1 op2 mode)
+  (dni name 
+       (.str name "compare" )
+       ((PIPE OS) (IDOC CMP))
+       (.str insn " $"op1 ",$"op2)
+       (+ opc1 opc2 op1 op2)
+       (sequence ()
+            (set condbit (lt HI op1 (mem HI op2)))
+           (set mode op1 (sub HI op1 (const 1)))
+       )    
+       ()
+  )
+)
+(cmp7 cmpd1rm cmpd1  OP1_10 OP2_2 regmem8 memgr8 HI)
+(cmp7 cmpd2rm cmpd2  OP1_11 OP2_2 regmem8 memgr8 HI)
+(cmp7 cmpi1rm cmpi1  OP1_8 OP2_2 regmem8 memgr8 HI)
+(cmp7 cmpi2rm cmpi2  OP1_9 OP2_2 regmem8 memgr8 HI)
+(cmp7 cmpd1rmi cmpd1  OP1_10 OP2_2 reg8 memory HI)
+(cmp7 cmpd2rmi cmpd2  OP1_11 OP2_2 reg8 memory HI)
+(cmp7 cmpi1rmi cmpi1  OP1_8 OP2_2 reg8 memory HI)
+(cmp7 cmpi2rmi cmpi2  OP1_9 OP2_2 reg8 memory HI)
+
+
+;Shift and rotate insns
+;****************************************************************
+(define-pmacro (shift name insn insn1 opc1 opc2 op1 op2 mode)
+  (dni name 
+       (.str name "shift" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",$"op2)
+       (+ opc1 opc2 op1 op2)
+       (set mode op1 (insn1 mode op1 op2))
+       ()
+  )
+)
+(shift shlr shl sll OP1_4 OP2_12 dr sr HI)
+(shift shrr shr srl OP1_6 OP2_12 dr sr HI)
+(shift rolr rol rol OP1_0 OP2_12 dr sr HI)
+(shift rorr ror ror OP1_2 OP2_12 dr sr HI)
+(shift ashrr ashr sra OP1_10 OP2_12 dr sr HI)
+
+(define-pmacro (shift1 name insn insn1 opc1 opc2 op1 op2 mode)
+  (dni name 
+       (.str name "shift" )
+       ((PIPE OS) (IDOC ALU))
+       (.str insn " $"op1 ",$hash$"op2)
+       (+ opc1 opc2 op2 op1)
+       (set mode op1 (insn1 mode op1 op2))
+       ()
+  )
+)
+(shift1 shlri shl sll OP1_5 OP2_12 sr uimm4 HI)
+(shift1 shrri shr srl OP1_7 OP2_12 sr uimm4 HI)
+(shift1 rolri rol rol OP1_1 OP2_12 sr uimm4 HI)
+(shift1 rorri ror ror OP1_3 OP2_12 sr uimm4 HI)
+(shift1 ashrri ashr sra OP1_11 OP2_12 sr uimm4 HI)

diff --git a/cpu/xc16x.opc b/cpu/xc16x.opc
new file mode 100644 (file)
index 0000000..455f3fb
--- /dev/null
+++ b/cpu/xc16x.opc
@@ -0,0 +1,245 @@
+/* XC16X opcode support.  -*- C -*-
+
+   Copyright 2006, 2007, 2009 Free Software Foundation, Inc.
+
+   Contributed by KPIT Cummins Infosystems Ltd.; developed under contract 
+   from Infineon Systems, GMBH , Germany.
+
+   This file is part of the GNU Binutils.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+
+/* This file is an addendum to xc16x.cpu.  Heavy use of C code isn't
+   appropriate in .cpu files, so it resides here.  This especially applies
+   to assembly/disassembly where parsing/printing can be quite involved.
+   Such things aren't really part of the specification of the cpu, per se,
+   so .cpu files provide the general framework and .opc files handle the
+   nitty-gritty details as necessary.
+
+   Each section is delimited with start and end markers.
+
+   <arch>-opc.h additions use: "-- opc.h"
+   <arch>-opc.c additions use: "-- opc.c"
+   <arch>-asm.c additions use: "-- asm.c"
+   <arch>-dis.c additions use: "-- dis.c"
+   <arch>-ibd.h additions use: "-- ibd.h"  */
+\f
+/* -- opc.h */
+
+#define CGEN_DIS_HASH_SIZE 8
+#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 3) % CGEN_DIS_HASH_SIZE)
+
+/* -- */
+\f
+/* -- opc.c */
+                                                                                
+/* -- */
+\f
+/* -- asm.c */
+/* Handle '#' prefixes (i.e. skip over them).  */
+
+static const char *
+parse_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+           const char **strp,
+           int opindex ATTRIBUTE_UNUSED,
+           long *valuep ATTRIBUTE_UNUSED)
+{
+  if (**strp == '#')
+    {
+      ++*strp;
+      return NULL;
+    }
+  return _("Missing '#' prefix");
+}
+
+/* Handle '.' prefixes (i.e. skip over them).  */
+
+static const char *
+parse_dot (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+          const char **strp,
+          int opindex ATTRIBUTE_UNUSED,
+          long *valuep ATTRIBUTE_UNUSED)
+{
+  if (**strp == '.')
+    {
+      ++*strp;
+      return NULL;
+    }
+  return _("Missing '.' prefix");
+}
+
+/* Handle 'pof:' prefixes (i.e. skip over them).  */
+
+static const char *
+parse_pof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+          const char **strp,
+          int opindex ATTRIBUTE_UNUSED,
+          long *valuep ATTRIBUTE_UNUSED)
+{
+  if (strncasecmp (*strp, "pof:", 4) == 0)
+    {
+      *strp += 4;
+      return NULL;
+    }
+  return _("Missing 'pof:' prefix");  
+}
+
+/* Handle 'pag:' prefixes (i.e. skip over them).  */
+
+static const char *
+parse_pag (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+          const char **strp,
+          int opindex ATTRIBUTE_UNUSED,
+          long *valuep ATTRIBUTE_UNUSED)
+{
+  if (strncasecmp (*strp, "pag:", 4) == 0)
+    {
+      *strp += 4;
+      return NULL;
+    }
+  return _("Missing 'pag:' prefix");
+}
+
+/* Handle 'sof' prefixes (i.e. skip over them).  */
+
+static const char *
+parse_sof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+          const char **strp,
+          int opindex ATTRIBUTE_UNUSED,
+          long *valuep ATTRIBUTE_UNUSED)
+{
+  if (strncasecmp (*strp, "sof:", 4) == 0)
+    {
+      *strp += 4;
+      return NULL;
+    }
+  return _("Missing 'sof:' prefix");
+}
+
+/* Handle 'seg' prefixes (i.e. skip over them).  */
+
+static const char *
+parse_seg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+          const char **strp,
+          int opindex ATTRIBUTE_UNUSED,
+          long *valuep ATTRIBUTE_UNUSED)
+{
+  if (strncasecmp (*strp, "seg:", 4) == 0)
+    {
+      *strp += 4;
+      return NULL;
+    }
+  return _("Missing 'seg:' prefix");
+}
+/* -- */
+\f
+/* -- dis.c */
+
+#define CGEN_PRINT_NORMAL(cd, info, value, attrs, pc, length)  \
+  do                                                           \
+    {                                                          \
+      if (CGEN_BOOL_ATTR ((attrs), CGEN_OPERAND_DOT_PREFIX))   \
+        info->fprintf_func (info->stream, ".");                        \
+      if (CGEN_BOOL_ATTR ((attrs), CGEN_OPERAND_POF_PREFIX))   \
+        info->fprintf_func (info->stream, "#pof:");            \
+      if (CGEN_BOOL_ATTR ((attrs), CGEN_OPERAND_PAG_PREFIX))   \
+        info->fprintf_func (info->stream, "#pag:");            \
+    }                                                          \
+  while (0)
+
+/* Print a 'pof:' prefix to an operand.  */
+
+static void
+print_pof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+          void * dis_info ATTRIBUTE_UNUSED,
+          long value ATTRIBUTE_UNUSED,
+          unsigned int attrs ATTRIBUTE_UNUSED,
+          bfd_vma pc ATTRIBUTE_UNUSED,
+          int length ATTRIBUTE_UNUSED)
+{
+}
+
+/* Print a 'pag:' prefix to an operand.  */
+
+static void
+print_pag (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+          void * dis_info ATTRIBUTE_UNUSED,
+          long value ATTRIBUTE_UNUSED,
+          unsigned int attrs ATTRIBUTE_UNUSED,
+          bfd_vma pc ATTRIBUTE_UNUSED,
+          int length ATTRIBUTE_UNUSED)
+{
+}
+
+/* Print a 'sof:' prefix to an operand.  */
+
+static void
+print_sof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+          void * dis_info,
+          long value ATTRIBUTE_UNUSED,
+          unsigned int attrs ATTRIBUTE_UNUSED,
+          bfd_vma pc ATTRIBUTE_UNUSED,
+          int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+
+  info->fprintf_func (info->stream, "sof:");
+}
+
+/* Print a 'seg:' prefix to an operand.  */
+
+static void
+print_seg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+          void * dis_info,
+          long value ATTRIBUTE_UNUSED,
+          unsigned int attrs ATTRIBUTE_UNUSED,
+          bfd_vma pc ATTRIBUTE_UNUSED,
+          int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+
+  info->fprintf_func (info->stream, "seg:");
+}
+
+/* Print a '#' prefix to an operand.  */
+
+static void
+print_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+           void * dis_info,
+           long value ATTRIBUTE_UNUSED,
+           unsigned int attrs ATTRIBUTE_UNUSED,
+           bfd_vma pc ATTRIBUTE_UNUSED,
+           int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+
+  info->fprintf_func (info->stream, "#");
+}
+
+/* Print a '.' prefix to an operand.  */
+
+static void
+print_dot (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+          void * dis_info ATTRIBUTE_UNUSED,
+          long value ATTRIBUTE_UNUSED,
+          unsigned int attrs ATTRIBUTE_UNUSED,
+          bfd_vma pc ATTRIBUTE_UNUSED,
+          int length ATTRIBUTE_UNUSED)
+{
+}
+
+/* -- */

diff --git a/gdb/README b/gdb/README
index e11d182..57f600a 100644 (file)
--- a/gdb/README
+++ b/gdb/README
@@ -1,5 +1,5 @@
-                    README for gdb-6.8.92 release
-                    Updated 30, September, 2009
+                    README for gdb-6.3 release
+                    Updated 20, November, 2006
 
 This is GDB, the GNU source-level debugger.
 
@@ -20,7 +20,7 @@ Unpacking and Installation -- quick overview
    In this release, the GDB debugger sources, the generic GNU include
 files, the BFD ("binary file description") library, the readline
 library, and other libraries all have directories of their own
-underneath the gdb-6.8.92 directory.  The idea is that a variety of GNU
+underneath the gdb-6.3 directory.  The idea is that a variety of GNU
 tools can share a common copy of these things.  Be aware of variation
 over time--for example don't try to build gdb with a copy of bfd from
 a release other than the gdb release (such as a binutils release),
@@ -29,8 +29,8 @@ Configuration scripts and makefiles exist to cruise up and down this
 directory tree and automatically build all the pieces in the right
 order.
 
-   When you unpack the gdb-6.8.92.tar.gz file, you'll find a directory
-called `gdb-6.8.92', which contains:
+   When you unpack the gdb-6.3.tar.gz file, you'll find a directory
+called `gdb-6.3', which contains:
 
   COPYING       config-ml.in  gettext.m4   ltconfig        sim
   COPYING.LIB   config.guess  include      ltmain.sh       src-release
@@ -43,7 +43,7 @@ called `gdb-6.8.92', which contains:
 
 You can build GDB right in the source directory:
 
-      cd gdb-6.8.92
+      cd gdb-6.3
       ./configure
       make
       cp gdb/gdb /usr/local/bin/gdb    (or wherever you want)
@@ -57,25 +57,25 @@ You can build GDB in any empty build directory:
 
       mkdir build
       cd build
-      <full path to your sources>/gdb-6.8.92/configure
+      <full path to your sources>/gdb-6.3/configure
       make
       cp gdb/gdb /usr/local/bin/gdb    (or wherever you want)
 
 (Building GDB with DJGPP tools for MS-DOS/MS-Windows is slightly
-different; see the file gdb-6.8.92/gdb/config/djgpp/README for details.)
+different; see the file gdb-6.3/gdb/config/djgpp/README for details.)
 
    This will configure and build all the libraries as well as GDB.  If
 `configure' can't determine your system type, specify one as its
 argument, e.g., `./configure sun4' or `./configure decstation'.
 
-   Make sure that your 'configure' line ends in 'gdb-6.8.92/configure':
+   Make sure that your 'configure' line ends in 'gdb-6.3/configure':
 
-      /berman/migchain/source/gdb-6.8.92/configure      # RIGHT
-      /berman/migchain/source/gdb-6.8.92/gdb/configure  # WRONG
+      /berman/migchain/source/gdb-6.3/configure      # RIGHT
+      /berman/migchain/source/gdb-6.3/gdb/configure  # WRONG
 
    The gdb package contains several subdirectories, such as 'gdb',
 'bfd', and 'readline'.  If your 'configure' line ends in
-'gdb-6.8.92/gdb/configure', then you are configuring only the gdb
+'gdb-6.3/gdb/configure', then you are configuring only the gdb
 subdirectory, not the whole gdb package.  This leads to build errors
 such as:
 
@@ -113,7 +113,7 @@ documentation and TeX (or `texi2roff') to typeset the printed version.
 
    GDB includes an already formatted copy of the on-line Info version
 of this manual in the `gdb/doc' subdirectory.  The main Info file is
-`gdb-6.8.92/gdb/doc/gdb.info', and it refers to subordinate files
+`gdb-6.3/gdb/doc/gdb.info', and it refers to subordinate files
 matching `gdb.info*' in the same directory.  If necessary, you can
 print out these files, or read them with any editor; but they are
 easier to read using the `info' subsystem in GNU Emacs or the
@@ -125,7 +125,7 @@ Info formatting programs, such as `texinfo-format-buffer' or
 `makeinfo'.
 
    If you have `makeinfo' installed, and are in the top level GDB
-source directory (`gdb-6.8.92', in the case of version 6.8.92), you can make
+source directory (`gdb-6.3', in the case of version 6.3), you can make
 the Info file by typing:
 
       cd gdb/doc
@@ -134,7 +134,7 @@ the Info file by typing:
    If you want to typeset and print copies of this manual, you need
 TeX, a program to print its DVI output files, and `texinfo.tex', the
 Texinfo definitions file.  This file is included in the GDB
-distribution, in the directory `gdb-6.8.92/texinfo'.
+distribution, in the directory `gdb-6.3/texinfo'.
 
    TeX is a typesetting program; it does not print files directly, but
 produces output files called DVI files.  To print a typeset document,
@@ -148,11 +148,11 @@ without any extension or a `.dvi' extension.
 This file tells TeX how to typeset a document written in Texinfo
 format.  On its own, TeX cannot read, much less typeset a Texinfo file.
  `texinfo.tex' is distributed with GDB and is located in the
-`gdb-6.8.92/texinfo' directory.
+`gdb-6.3/texinfo' directory.
 
    If you have TeX and a DVI printer program installed, you can typeset
 and print this manual.  First switch to the the `gdb' subdirectory of
-the main source directory (for example, to `gdb-6.8.92/gdb') and then type:
+the main source directory (for example, to `gdb-6.3/gdb') and then type:
 
       make doc/gdb.dvi
 
@@ -175,43 +175,43 @@ preparing GDB for installation; you can then use `make' to build the
 a single directory, whose name is usually composed by appending the
 version number to `gdb'.
 
-   For example, the GDB version 6.8.92 distribution is in the `gdb-6.8.92'
+   For example, the GDB version 6.3 distribution is in the `gdb-6.3'
 directory.  That directory contains:
 
-`gdb-6.8.92/{COPYING,COPYING.LIB}'
+`gdb-6.3/{COPYING,COPYING.LIB}'
      Standard GNU license files.  Please read them.
 
-`gdb-6.8.92/bfd'
+`gdb-6.3/bfd'
      source for the Binary File Descriptor library
 
-`gdb-6.8.92/config*'
+`gdb-6.3/config*'
      script for configuring GDB, along with other support files
 
-`gdb-6.8.92/gdb'
+`gdb-6.3/gdb'
      the source specific to GDB itself
 
-`gdb-6.8.92/include'
+`gdb-6.3/include'
      GNU include files
 
-`gdb-6.8.92/libiberty'
+`gdb-6.3/libiberty'
      source for the `-liberty' free software library
 
-`gdb-6.8.92/opcodes'
+`gdb-6.3/opcodes'
      source for the library of opcode tables and disassemblers
 
-`gdb-6.8.92/readline'
+`gdb-6.3/readline'
      source for the GNU command-line interface
      NOTE:  The readline library is compiled for use by GDB, but will
      not be installed on your system when "make install" is issued.
 
-`gdb-6.8.92/sim'
+`gdb-6.3/sim'
      source for some simulators (ARM, D10V, SPARC, M32R, MIPS, PPC, V850, etc)
 
-`gdb-6.8.92/texinfo'
+`gdb-6.3/texinfo'
      The `texinfo.tex' file, which you need in order to make a printed
      manual using TeX.
 
-`gdb-6.8.92/etc'
+`gdb-6.3/etc'
      Coding standards, useful files for editing GDB, and other
      miscellanea.
 
@@ -221,14 +221,14 @@ MS-DOS/MS-Windows are in the file gdb/config/djgpp/README.
 
    The simplest way to configure and build GDB is to run `configure'
 from the `gdb-VERSION-NUMBER' source directory, which in this example
-is the `gdb-6.8.92' directory.
+is the `gdb-6.3' directory.
 
    First switch to the `gdb-VERSION-NUMBER' source directory if you are
 not already in it; then run `configure'.
 
    For example:
 
-      cd gdb-6.8.92
+      cd gdb-6.3
       ./configure
       make
 
@@ -244,8 +244,8 @@ you may need to run `sh' on it explicitly:
       sh configure
 
    If you run `configure' from a directory that contains source
-directories for multiple libraries or programs, such as the `gdb-6.8.92'
-source directory for version 6.8.92, `configure' creates configuration
+directories for multiple libraries or programs, such as the `gdb-6.3'
+source directory for version 6.3, `configure' creates configuration
 files for every directory level underneath (unless you tell it not to,
 with the `--norecursion' option).
 
@@ -253,10 +253,10 @@ with the `--norecursion' option).
 directories in the GDB distribution, if you only want to configure that
 subdirectory; but be sure to specify a path to it.
 
-   For example, with version 6.8.92, type the following to configure only
+   For example, with version 6.3, type the following to configure only
 the `bfd' subdirectory:
 
-      cd gdb-6.8.92/bfd
+      cd gdb-6.3/bfd
       ../configure
 
    You can install `gdb' anywhere; it has no hardwired paths. However,
@@ -285,13 +285,13 @@ directory.  If the path to `configure' would be the same as the
 argument to `--srcdir', you can leave out the `--srcdir' option; it
 will be assumed.)
 
-   For example, with version 6.8.92, you can build GDB in a separate
+   For example, with version 6.3, you can build GDB in a separate
 directory for a Sun 4 like this:
 
-     cd gdb-6.8.92
+     cd gdb-6.3
      mkdir ../gdb-sun4
      cd ../gdb-sun4
-     ../gdb-6.8.92/configure
+     ../gdb-6.3/configure
      make
 
    When `configure' builds a configuration using a remote source
@@ -312,8 +312,8 @@ called `configure' (or one of its subdirectories).
 
    The `Makefile' that `configure' generates in each source directory
 also runs recursively.  If you type `make' in a source directory such
-as `gdb-6.8.92' (or in a separate configured directory configured with
-`--srcdir=PATH/gdb-6.8.92'), you will build all the required libraries,
+as `gdb-6.3' (or in a separate configured directory configured with
+`--srcdir=PATH/gdb-6.3'), you will build all the required libraries,
 and then build GDB.
 
    When you have multiple hosts or targets configured in separate
@@ -356,7 +356,7 @@ you can use it to test your guesses on abbreviations--for example:
      Invalid configuration `i786v': machine `i786v' not recognized
 
 `config.sub' is also distributed in the GDB source directory
-(`gdb-6.8.92', for version 6.8.92).
+(`gdb-6.3', for version 6.3).
 
 
 `configure' options
@@ -573,7 +573,7 @@ As an alternative, the bug report can be submitted, via e-mail, to the
 address "bug-gdb@gnu.org".
 
    When submitting a bug, please include the GDB version number (e.g.,
-gdb-6.8.92), and how you configured it (e.g., "sun4" or "mach386 host,
+gdb-6.3), and how you configured it (e.g., "sun4" or "mach386 host,
 i586-intel-synopsys target").  Since GDB now supports so many
 different configurations, it is important that you be precise about
 this.  If at all possible, you should include the actual banner that
@@ -628,17 +628,17 @@ ftp://sources.redhat.com/pub/dejagnu/ will contain a recent snapshot.
 Once DejaGNU is installed, you can run the tests in one of the
 following ways:
 
-  (1)  cd gdb-6.8.92
+  (1)  cd gdb-6.3
        make check-gdb
 
 or
 
-  (2)  cd gdb-6.8.92/gdb
+  (2)  cd gdb-6.3/gdb
        make check
 
 or
 
-  (3)  cd gdb-6.8.92/gdb/testsuite
+  (3)  cd gdb-6.3/gdb/testsuite
        make site.exp   (builds the site specific file)
        runtest -tool gdb GDB=../gdb    (or GDB=<somepath> as appropriate)
 

diff --git a/gdb/c-lang.c b/gdb/c-lang.c
index d01490c..405c489 100644 (file)
--- a/gdb/c-lang.c
+++ b/gdb/c-lang.c
@@ -52,17 +52,17 @@ charset_for_string_type (enum c_string_type str_type,
     case C_WIDE_STRING:
       return target_wide_charset (byte_order);
     case C_STRING_16:
-      /* FIXME: UCS-2 is not always correct.  */
+      /* FIXME: UTF-16 is not always correct.  */
       if (byte_order == BFD_ENDIAN_BIG)
-       return "UCS-2BE";
+       return "UTF-16BE";
       else
-       return "UCS-2LE";
+       return "UTF-16LE";
     case C_STRING_32:
-      /* FIXME: UCS-4 is not always correct.  */
+      /* FIXME: UTF-32 is not always correct.  */
       if (byte_order == BFD_ENDIAN_BIG)
-       return "UCS-4BE";
+       return "UTF-32BE";
       else
-       return "UCS-4LE";
+       return "UTF-32LE";
     }
   internal_error (__FILE__, __LINE__, "unhandled c_string_type");
 }
@@ -618,7 +618,7 @@ c_printstr (struct ui_file *stream, struct type *type, const gdb_byte *string,
 
 void
 c_get_string (struct value *value, gdb_byte **buffer, int *length,
-             const char **charset)
+             struct type **char_type, const char **charset)
 {
   int err, width;
   unsigned int fetchlimit;
@@ -626,6 +626,7 @@ c_get_string (struct value *value, gdb_byte **buffer, int *length,
   struct type *element_type = TYPE_TARGET_TYPE (type);
   int req_length = *length;
   enum bfd_endian byte_order = gdbarch_byte_order (get_type_arch (type));
+  enum c_string_type kind;
 
   if (element_type == NULL)
     goto error;
@@ -652,13 +653,11 @@ c_get_string (struct value *value, gdb_byte **buffer, int *length,
     /* We work only with arrays and pointers.  */
     goto error;
 
-  element_type = check_typedef (element_type);
-  if (TYPE_CODE (element_type) != TYPE_CODE_INT
-      && TYPE_CODE (element_type) != TYPE_CODE_CHAR)
-    /* If the elements are not integers or characters, we don't consider it
-       a string.  */
+  if (! c_textual_element_type (element_type, 0))
     goto error;
-
+  kind = classify_type (element_type,
+                       gdbarch_byte_order (get_type_arch (element_type)),
+                       charset);
   width = TYPE_LENGTH (element_type);
 
   /* If the string lives in GDB's memory instead of the inferior's, then we
@@ -717,7 +716,7 @@ c_get_string (struct value *value, gdb_byte **buffer, int *length,
   if (*length != 0)
      *length = *length / width;
 
-  *charset = target_charset ();
+  *char_type = element_type;
 
   return;
 
@@ -763,7 +762,7 @@ convert_ucn (char *p, char *limit, const char *dest_charset,
       result >>= 8;
     }
 
-  convert_between_encodings ("UCS-4BE", dest_charset, data, 4, 4, output,
+  convert_between_encodings ("UTF-32BE", dest_charset, data, 4, 4, output,
                             translit_none);
 
   return p;

diff --git a/gdb/c-lang.h b/gdb/c-lang.h
index ba9d996..afafc9b 100644 (file)
--- a/gdb/c-lang.h
+++ b/gdb/c-lang.h
@@ -106,5 +106,9 @@ extern int cp_is_vtbl_ptr_type (struct type *);
 
 extern int cp_is_vtbl_member (struct type *);
 
+/* These are in c-valprint.c.  */
+
+extern int c_textual_element_type (struct type *, char);
+
 
 #endif /* !defined (C_LANG_H) */

diff --git a/gdb/charset.c b/gdb/charset.c
index a59d9c6..f5281ed 100644 (file)
--- a/gdb/charset.c
+++ b/gdb/charset.c
@@ -102,17 +102,17 @@
 iconv_t
 iconv_open (const char *to, const char *from)
 {
-  /* We allow conversions from UCS-4BE, wchar_t, and the host charset.
+  /* We allow conversions from UTF-32BE, wchar_t, and the host charset.
      We allow conversions to wchar_t and the host charset.  */
-  if (strcmp (from, "UCS-4BE") && strcmp (from, "wchar_t")
+  if (strcmp (from, "UTF-32BE") && strcmp (from, "wchar_t")
       && strcmp (from, GDB_DEFAULT_HOST_CHARSET))
     return -1;
   if (strcmp (to, "wchar_t") && strcmp (to, GDB_DEFAULT_HOST_CHARSET))
     return -1;
 
-  /* Return 1 if we are converting from UCS-4BE, 0 otherwise.  This is
+  /* Return 1 if we are converting from UTF-32BE, 0 otherwise.  This is
      used as a flag in calls to iconv.  */
-  return !strcmp (from, "UCS-4BE");
+  return !strcmp (from, "UTF-32BE");
 }
 
 int
@@ -122,10 +122,10 @@ iconv_close (iconv_t arg)
 }
 
 size_t
-iconv (iconv_t ucs_flag, const char **inbuf, size_t *inbytesleft,
+iconv (iconv_t utf_flag, const char **inbuf, size_t *inbytesleft,
        char **outbuf, size_t *outbytesleft)
 {
-  if (ucs_flag)
+  if (utf_flag)
     {
       while (*inbytesleft >= 4)
        {
@@ -193,7 +193,7 @@ iconv (iconv_t ucs_flag, const char **inbuf, size_t *inbytesleft,
 #endif
 
 #ifndef GDB_DEFAULT_TARGET_WIDE_CHARSET
-#define GDB_DEFAULT_TARGET_WIDE_CHARSET "UCS-4"
+#define GDB_DEFAULT_TARGET_WIDE_CHARSET "UTF-32"
 #endif
 
 static const char *auto_host_charset_name = GDB_DEFAULT_HOST_CHARSET;

diff --git a/gdb/config.in b/gdb/config.in
index 4716524..74522ae 100644 (file)
--- a/gdb/config.in
+++ b/gdb/config.in
@@ -792,6 +792,9 @@
 /* Define to `int' if <sys/types.h> does not define. */
 #undef pid_t
 
+/* readline-6.0 started to use different name. */
+#undef readline_echoing_p
+
 /* Define to the equivalent of the C99 'restrict' keyword, or to
    nothing if this is not supported.  Do not define if restrict is
    supported directly.  */

diff --git a/gdb/configure b/gdb/configure
index 46e7bfe..40fb803 100755 (executable)
--- a/gdb/configure
+++ b/gdb/configure
@@ -8431,6 +8431,39 @@ if test "$with_system_readline" = yes; then
   READLINE=-lreadline
   READLINE_DEPS=
   READLINE_CFLAGS=
+
+  # readline-6.0 started to use the name `_rl_echoing_p'.
+  # `$(READLINE_DIR)/' of bundled readline would not resolve in configure.
+
+  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for readline_echoing_p" >&5
+$as_echo_n "checking for readline_echoing_p... " >&6; }
+  save_LIBS=$LIBS
+  LIBS="$LIBS $READLINE"
+  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+int
+main ()
+{
+extern int readline_echoing_p;
+                                   return readline_echoing_p;
+  ;
+  return 0;
+}
+_ACEOF
+if ac_fn_c_try_link "$LINENO"; then :
+  READLINE_ECHOING_P=yes
+else
+  READLINE_ECHOING_P=no
+
+$as_echo "#define readline_echoing_p _rl_echoing_p" >>confdefs.h
+
+fi
+rm -f core conftest.err conftest.$ac_objext \
+    conftest$ac_exeext conftest.$ac_ext
+  LIBS="$save_LIBS"
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $READLINE_ECHOING_P" >&5
+$as_echo "$READLINE_ECHOING_P" >&6; }
 else
   READLINE='$(READLINE_DIR)/libreadline.a'
   READLINE_DEPS='$(READLINE)'
@@ -13067,6 +13100,11 @@ if test "${enable_werror+set}" = set; then :
 fi
 
 
+# Enable -Werror by default when using gcc
+if test "${GCC}" = yes -a -z "${ERROR_ON_WARNING}" ; then
+    ERROR_ON_WARNING=yes
+fi
+
 WERROR_CFLAGS=""
 if test "${ERROR_ON_WARNING}" = yes ; then
     WERROR_CFLAGS="-Werror"

diff --git a/gdb/configure.ac b/gdb/configure.ac
index 0e42182..f9c17fd 100644 (file)
--- a/gdb/configure.ac
+++ b/gdb/configure.ac
@@ -534,6 +534,21 @@ if test "$with_system_readline" = yes; then
   READLINE=-lreadline
   READLINE_DEPS=
   READLINE_CFLAGS=
+
+  # readline-6.0 started to use the name `_rl_echoing_p'.
+  # `$(READLINE_DIR)/' of bundled readline would not resolve in configure.
+
+  AC_MSG_CHECKING([for readline_echoing_p])
+  save_LIBS=$LIBS
+  LIBS="$LIBS $READLINE"
+  AC_LINK_IFELSE(AC_LANG_PROGRAM(,[[extern int readline_echoing_p;
+                                   return readline_echoing_p;]]),
+                [READLINE_ECHOING_P=yes],
+                [READLINE_ECHOING_P=no
+                 AC_DEFINE([readline_echoing_p], [_rl_echoing_p],
+                           [readline-6.0 started to use different name.])])
+  LIBS="$save_LIBS"
+  AC_MSG_RESULT([$READLINE_ECHOING_P])
 else
   READLINE='$(READLINE_DIR)/libreadline.a'
   READLINE_DEPS='$(READLINE)'
@@ -1510,6 +1525,11 @@ AC_ARG_ENABLE(werror,
      *) AC_MSG_ERROR(bad value ${enableval} for --enable-werror) ;;
    esac])
 
+# Enable -Werror by default when using gcc
+if test "${GCC}" = yes -a -z "${ERROR_ON_WARNING}" ; then
+    ERROR_ON_WARNING=yes
+fi
+
 WERROR_CFLAGS=""
 if test "${ERROR_ON_WARNING}" = yes ; then
     WERROR_CFLAGS="-Werror"

diff --git a/gdb/configure.tgt b/gdb/configure.tgt
index 24331c3..20b739e 100644 (file)
--- a/gdb/configure.tgt
+++ b/gdb/configure.tgt
@@ -376,7 +376,7 @@ powerpc-*-linux* | powerpc64-*-linux*)
        # Target: PowerPC running Linux
        gdb_target_obs="rs6000-tdep.o ppc-linux-tdep.o ppc-sysv-tdep.o \
                        solib.o solib-svr4.o solib-spu.o spu-multiarch.o \
-                       corelow.o symfile-mem.o"
+                       corelow.o symfile-mem.o linux-tdep.o"
        gdb_sim=../sim/ppc/libsim.a
        build_gdbserver=yes
        ;;
@@ -391,7 +391,7 @@ powerpc*-*-*)
 
 s390*-*-*)
        # Target: S390 running Linux
-       gdb_target_obs="s390-tdep.o solib.o solib-svr4.o"
+       gdb_target_obs="s390-tdep.o solib.o solib-svr4.o linux-tdep.o"
        build_gdbserver=yes
        ;;
 

diff --git a/gdb/cp-support.c b/gdb/cp-support.c
index f12d785..684943b 100644 (file)
--- a/gdb/cp-support.c
+++ b/gdb/cp-support.c
@@ -32,6 +32,9 @@
 #include "block.h"
 #include "complaints.h"
 #include "gdbtypes.h"
+#include "exceptions.h"
+#include "expression.h"
+#include "value.h"
 
 #include "safe-ctype.h"
 
@@ -70,6 +73,18 @@ struct cmd_list_element *maint_cplus_cmd_list = NULL;
 static void maint_cplus_command (char *arg, int from_tty);
 static void first_component_command (char *arg, int from_tty);
 
+/* Operator validation.
+   NOTE: Multi-byte operators (usually the assignment variety operator)
+   must appear before the single byte version, i.e., "+=" before "+".  */
+static const char *operator_tokens[] =
+  {
+    "++", "+=", "+", "->*", "->", "--", "-=", "-", "*=", "*", "/=", "/",
+    "%=", "%", "!=", "==", "!", "&&", "<<=", "<<", ">>=", ">>",
+    "<=", "<", ">=", ">", "~", "&=", "&", "|=", "||", "|", "^=", "^",
+    "=", "()", "[]", ",", "new", "delete"
+    /* new[] and delete[] require special whitespace handling */
+  };
+
 /* Return 1 if STRING is clearly already in canonical form.  This
    function is conservative; things which it does not recognize are
    assumed to be non-canonical, and the parser will sort them out
@@ -909,6 +924,107 @@ first_component_command (char *arg, int from_tty)
 
 extern initialize_file_ftype _initialize_cp_support; /* -Wmissing-prototypes */
 
+#define SKIP_SPACE(P)                          \
+  do                                           \
+  {                                            \
+    while (*(P) == ' ' || *(P) == '\t')                \
+      ++(P);                                   \
+  }                                            \
+  while (0)
+
+/* Returns the length of the operator name or 0 if INPUT does not
+   point to a valid C++ operator.  INPUT should start with "operator".  */
+int
+cp_validate_operator (const char *input)
+{
+  int i;
+  char *copy;
+  const char *p;
+  struct expression *expr;
+  struct value *val;
+  struct gdb_exception except;
+  struct cleanup *old_chain;
+
+  p = input;
+
+  if (strncmp (p, "operator", 8) == 0)
+    {
+      int valid = 0;
+      p += 8;
+
+      SKIP_SPACE (p);
+      for (i = 0; i < sizeof (operator_tokens) / sizeof (operator_tokens[0]);
+          ++i)
+       {
+         int length = strlen (operator_tokens[i]);
+         /* By using strncmp here, we MUST have operator_tokens ordered!
+            See additional notes where operator_tokens is defined above.  */
+         if (strncmp (p, operator_tokens[i], length) == 0)
+           {
+             const char *op = p;
+             valid = 1;
+             p += length;
+
+             if (strncmp (op, "new", 3) == 0
+                 || strncmp (op, "delete", 6) == 0)
+               {
+
+                 /* Special case: new[] and delete[].  We must be careful
+                    to swallow whitespace before/in "[]".  */
+                 SKIP_SPACE (p);
+
+                 if (*p == '[')
+                   {
+                     ++p;
+                     SKIP_SPACE (p);
+                     if (*p == ']')
+                       ++p;
+                     else
+                       valid = 0;
+                   }
+               }
+
+             if (valid)
+               return (p - input);
+           }
+       }
+
+      /* Check input for a conversion operator.  */
+
+      /* Skip past base typename */
+      while (*p != '*' && *p != '&' && *p != 0 && *p != ' ')
+       ++p;
+      SKIP_SPACE (p);
+
+      /* Add modifiers '*'/'&' */
+      while (*p == '*' || *p == '&')
+       {
+         ++p;
+         SKIP_SPACE (p);
+       }
+
+      /* Check for valid type.  [Remember: input starts with 
+        "operator".]  */
+      copy = savestring (input + 8, p - input - 8);
+      expr = NULL;
+      val = NULL;
+      TRY_CATCH (except, RETURN_MASK_ALL)
+       {
+         expr = parse_expression (copy);
+         val = evaluate_type (expr);
+       }
+
+      xfree (copy);
+      if (expr)
+       xfree (expr);
+
+      if (val != NULL && value_type (val) != NULL)
+       return (p - input);
+    }
+
+  return 0;
+}
+
 void
 _initialize_cp_support (void)
 {

diff --git a/gdb/cp-support.h b/gdb/cp-support.h
index b5a5c5f..7ecd201 100644 (file)
--- a/gdb/cp-support.h
+++ b/gdb/cp-support.h
@@ -72,6 +72,8 @@ extern struct symbol **make_symbol_overload_list (const char *,
 extern struct type *cp_lookup_rtti_type (const char *name,
                                         struct block *block);
 
+extern int cp_validate_operator (const char *input);
+
 /* Functions/variables from cp-namespace.c.  */
 
 extern int cp_is_anonymous (const char *namespace);

diff --git a/gdb/doc/observer.texi b/gdb/doc/observer.texi
index 4984f31..77d6b47 100644 (file)
--- a/gdb/doc/observer.texi
+++ b/gdb/doc/observer.texi
@@ -122,6 +122,8 @@ haven't been loaded yet.
 
 @deftypefun void solib_unloaded (struct so_list *@var{solib})
 The shared library specified by @var{solib} has been unloaded.
+Note that when @value{GDBN} calls this observer, the library's
+symbols have not been unloaded yet, and thus are still available.
 @end deftypefun
 
 @deftypefun void new_objfile (struct objfile *@var{objfile})

diff --git a/gdb/doc/stabs.texinfo b/gdb/doc/stabs.texinfo
index fcd30ce..d28c93d 100644 (file)
--- a/gdb/doc/stabs.texinfo
+++ b/gdb/doc/stabs.texinfo
@@ -39,7 +39,7 @@ This document describes the stabs debugging symbol tables.
 @page
 @tex
 \def\$#1${{#1}}  % Kluge: collect RCS revision info without $...$
-\xdef\manvers{\$Revision$}  % For use in headers, footers too
+\xdef\manvers{\$Revision: 2.130 $}  % For use in headers, footers too
 {\parskip=0pt
 \hfill Cygnus Support\par
 \hfill \manvers\par

diff --git a/gdb/gdbserver/ChangeLog b/gdb/gdbserver/ChangeLog
index 6adede6..a85f26b 100644 (file)
--- a/gdb/gdbserver/ChangeLog
+++ b/gdb/gdbserver/ChangeLog
@@ -1,4 +1,4 @@
-2009-09-28  Ulrich Weigand  <uweigand@de.ibm.com>
+2009-09-27  Ulrich Weigand  <uweigand@de.ibm.com>
 
        * spu-low.c (spu_kill): Wait for inferior to terminate.
        Call clear_inferiors.

diff --git a/gdb/infcall.c b/gdb/infcall.c
index c9d98cf..277399a 100644 (file)
--- a/gdb/infcall.c
+++ b/gdb/infcall.c
@@ -441,6 +441,7 @@ call_function_by_hand (struct value *function, int nargs, struct value **args)
   struct gdbarch *gdbarch;
   struct breakpoint *terminate_bp = NULL;
   struct minimal_symbol *tm;
+  struct cleanup *terminate_bp_cleanup = NULL;
   ptid_t call_thread_ptid;
   struct gdb_exception e;
   const char *name;
@@ -772,7 +773,7 @@ call_function_by_hand (struct value *function, int nargs, struct value **args)
 
   /* Register a clean-up for unwind_on_terminating_exception_breakpoint.  */
   if (terminate_bp)
-    make_cleanup_delete_breakpoint (terminate_bp);
+    terminate_bp_cleanup = make_cleanup_delete_breakpoint (terminate_bp);
 
   /* - SNIP - SNIP - SNIP - SNIP - SNIP - SNIP - SNIP - SNIP - SNIP -
      If you're looking to implement asynchronous dummy-frames, then
@@ -987,6 +988,11 @@ When the function is done executing, GDB will silently stop."),
       internal_error (__FILE__, __LINE__, _("... should not be here"));
     }
 
+  /* If we get here and the std::terminate() breakpoint has been set,
+     it has to be cleaned manually.  */
+  if (terminate_bp)
+    do_cleanups (terminate_bp_cleanup);
+
   /* If we get here the called FUNCTION ran to completion,
      and the dummy frame has already been popped.  */
 

diff --git a/gdb/infrun.c b/gdb/infrun.c
index ff7c6b9..4ce07d9 100644 (file)
--- a/gdb/infrun.c
+++ b/gdb/infrun.c
@@ -2386,13 +2386,22 @@ stepped_in_from (struct frame_info *frame, struct frame_id step_frame_id)
    It returns 1 if the inferior should keep going (and GDB
    should ignore the event), or 0 if the event deserves to be
    processed.  */
+
 static int
-deal_with_syscall_event (struct execution_control_state *ecs)
+handle_syscall_event (struct execution_control_state *ecs)
 {
-  struct regcache *regcache = get_thread_regcache (ecs->ptid);
-  struct gdbarch *gdbarch = get_regcache_arch (regcache);
-  int syscall_number = gdbarch_get_syscall_number (gdbarch,
-                                                   ecs->ptid);
+  struct regcache *regcache;
+  struct gdbarch *gdbarch;
+  int syscall_number;
+
+  if (!ptid_equal (ecs->ptid, inferior_ptid))
+    context_switch (ecs->ptid);
+
+  regcache = get_thread_regcache (ecs->ptid);
+  gdbarch = get_regcache_arch (regcache);
+  syscall_number = gdbarch_get_syscall_number (gdbarch, ecs->ptid);
+  stop_pc = regcache_read_pc (regcache);
+
   target_last_waitstatus.value.syscall_number = syscall_number;
 
   if (catch_syscall_enabled () > 0
@@ -2401,35 +2410,22 @@ deal_with_syscall_event (struct execution_control_state *ecs)
       if (debug_infrun)
         fprintf_unfiltered (gdb_stdlog, "infrun: syscall number = '%d'\n",
                             syscall_number);
-      ecs->event_thread->stop_signal = TARGET_SIGNAL_TRAP;
-
-      if (!ptid_equal (ecs->ptid, inferior_ptid))
-        {
-          context_switch (ecs->ptid);
-          reinit_frame_cache ();
-        }
-
-      stop_pc = regcache_read_pc (get_thread_regcache (ecs->ptid));
 
       ecs->event_thread->stop_bpstat = bpstat_stop_status (stop_pc, ecs->ptid);
-
       ecs->random_signal = !bpstat_explains_signal (ecs->event_thread->stop_bpstat);
 
-      /* If no catchpoint triggered for this, then keep going.  */
-      if (ecs->random_signal)
-        {
-          ecs->event_thread->stop_signal = TARGET_SIGNAL_0;
-          keep_going (ecs);
-          return 1;
-        }
-      return 0;
-    }
-  else
-    {
-      resume (0, TARGET_SIGNAL_0);
-      prepare_to_wait (ecs);
-      return 1;
+      if (!ecs->random_signal)
+       {
+         /* Catchpoint hit.  */
+         ecs->event_thread->stop_signal = TARGET_SIGNAL_TRAP;
+         return 0;
+       }
     }
+
+  /* If no catchpoint triggered for this, then keep going.  */
+  ecs->event_thread->stop_signal = TARGET_SIGNAL_0;
+  keep_going (ecs);
+  return 1;
 }
 
 /* Given an execution control state that has been freshly filled in
@@ -2753,10 +2749,9 @@ handle_inferior_event (struct execution_control_state *ecs)
       if (debug_infrun)
         fprintf_unfiltered (gdb_stdlog, "infrun: TARGET_WAITKIND_SYSCALL_ENTRY\n");
       /* Getting the current syscall number */
-      if (deal_with_syscall_event (ecs) != 0)
+      if (handle_syscall_event (ecs) != 0)
         return;
       goto process_event_stop_test;
-      break;
 
       /* Before examining the threads further, step this thread to
          get it entirely out of the syscall.  (We get notice of the
@@ -2766,10 +2761,9 @@ handle_inferior_event (struct execution_control_state *ecs)
     case TARGET_WAITKIND_SYSCALL_RETURN:
       if (debug_infrun)
         fprintf_unfiltered (gdb_stdlog, "infrun: TARGET_WAITKIND_SYSCALL_RETURN\n");
-      if (deal_with_syscall_event (ecs) != 0)
+      if (handle_syscall_event (ecs) != 0)
         return;
       goto process_event_stop_test;
-      break;
 
     case TARGET_WAITKIND_STOPPED:
       if (debug_infrun)

diff --git a/gdb/language.c b/gdb/language.c
index 51a49f8..5dbe81c 100644 (file)
--- a/gdb/language.c
+++ b/gdb/language.c
@@ -1045,7 +1045,7 @@ default_print_array_index (struct value *index_value, struct ui_file *stream,
 
 void
 default_get_string (struct value *value, gdb_byte **buffer, int *length,
-                   const char **charset)
+                   struct type **char_type, const char **charset)
 {
   error (_("Getting a string is unsupported in this language."));
 }

diff --git a/gdb/language.h b/gdb/language.h
index c650e07..241fb01 100644 (file)
--- a/gdb/language.h
+++ b/gdb/language.h
@@ -294,7 +294,7 @@ struct language_defn
        Otherwise *LENGTH will include all characters - including any nulls.
        CHARSET will hold the encoding used in the string.  */
     void (*la_get_string) (struct value *value, gdb_byte **buffer, int *length,
-                         const char **charset);
+                          struct type **chartype, const char **charset);
 
     /* Add fields above this point, so the magic number is always last. */
     /* Magic number for compat checking */
@@ -394,8 +394,8 @@ extern enum language set_language (enum language);
                                 force_ellipses,options))
 #define LA_EMIT_CHAR(ch, type, stream, quoter) \
   (current_language->la_emitchar(ch, type, stream, quoter))
-#define LA_GET_STRING(value, buffer, length, encoding) \
-  (current_language->la_get_string(value, buffer, length, encoding))
+#define LA_GET_STRING(value, buffer, length, chartype, encoding) \
+  (current_language->la_get_string(value, buffer, length, chartype, encoding))
 
 #define LA_PRINT_ARRAY_INDEX(index_value, stream, optins) \
   (current_language->la_print_array_index(index_value, stream, options))
@@ -497,9 +497,9 @@ void default_print_typedef (struct type *type, struct symbol *new_symbol,
                            struct ui_file *stream);
 
 void default_get_string (struct value *value, gdb_byte **buffer, int *length,
-                        const char **charset);
+                        struct type **char_type, const char **charset);
 
 void c_get_string (struct value *value, gdb_byte **buffer, int *length,
-                  const char **charset);
+                  struct type **char_type, const char **charset);
 
 #endif /* defined (LANGUAGE_H) */

diff --git a/gdb/linespec.c b/gdb/linespec.c
index 3e943a1..19df329 100644 (file)
--- a/gdb/linespec.c
+++ b/gdb/linespec.c
@@ -30,6 +30,7 @@
 #include "value.h"
 #include "completer.h"
 #include "cp-abi.h"
+#include "cp-support.h"
 #include "parser-defs.h"
 #include "block.h"
 #include "objc-lang.h"
@@ -1171,11 +1172,19 @@ decode_objc (char **argptr, int funfirstline, struct symtab *file_symtab,
        }
       else
        {
-         /* The only match was a non-debuggable symbol.  */
-         values.sals[0].symtab = NULL;
-         values.sals[0].line = 0;
-         values.sals[0].end = 0;
-         values.sals[0].pc = SYMBOL_VALUE_ADDRESS (sym_arr[0]);
+         /* The only match was a non-debuggable symbol, which might point
+            to a function descriptor; resolve it to the actual code address
+            instead.  */
+         struct minimal_symbol *msymbol = (struct minimal_symbol *)sym_arr[0];
+         struct objfile *objfile = msymbol_objfile (msymbol);
+         struct gdbarch *gdbarch = get_objfile_arch (objfile);
+         CORE_ADDR pc = SYMBOL_VALUE_ADDRESS (msymbol);
+
+         pc = gdbarch_convert_from_func_ptr_addr (gdbarch, pc,
+                                                  &current_target);
+
+         init_sal (&values.sals[0]);
+         values.sals[0].pc = pc;
        }
       return values;
     }
@@ -1257,6 +1266,9 @@ decode_compound (char **argptr, int funfirstline, char ***canonical,
       /* Move pointer ahead to next double-colon.  */
       while (*p && (p[0] != ' ') && (p[0] != '\t') && (p[0] != '\''))
        {
+         if (current_language->la_language == language_cplus)
+           p += cp_validate_operator (p);
+
          if (p[0] == '<')
            {
              temp_end = find_template_name_end (p);
@@ -1334,6 +1346,15 @@ decode_compound (char **argptr, int funfirstline, char ***canonical,
          while (*p && *p != ' ' && *p != '\t' && *p != ',' && *p != ':')
            p++;
          /* At this point p->"".  String ended.  */
+         /* Nope, C++ operators could have spaces in them
+            ("foo::operator <" or "foo::operator delete []").
+            I apologize, this is a bit hacky...  */
+         if (current_language->la_language == language_cplus
+             && *p == ' ' && p - 8 - *argptr + 1 > 0)
+           {
+             /* The above loop has already swallowed "operator".  */
+             p += cp_validate_operator (p - 8) - 8;
+           }
        }
 
       /* Allocate our own copy of the substring between argptr and
@@ -1474,26 +1495,16 @@ find_method (int funfirstline, char ***canonical, char *saved_arg,
     }
   else
     {
-      char *tmp;
-
-      if (is_operator_name (copy))
-       {
-         tmp = (char *) alloca (strlen (copy + 3) + 9);
-         strcpy (tmp, "operator ");
-         strcat (tmp, copy + 3);
-       }
-      else
-       tmp = copy;
       if (not_found_ptr)
         *not_found_ptr = 1;
-      if (tmp[0] == '~')
+      if (copy[0] == '~')
        cplusplus_error (saved_arg,
                         "the class `%s' does not have destructor defined\n",
                         SYMBOL_PRINT_NAME (sym_class));
       else
        cplusplus_error (saved_arg,
                         "the class %s does not have any method named %s\n",
-                        SYMBOL_PRINT_NAME (sym_class), tmp);
+                        SYMBOL_PRINT_NAME (sym_class), copy);
     }
 }
 

diff --git a/gdb/linux-nat.c b/gdb/linux-nat.c
index 98f6347..f4f843b 100644 (file)
--- a/gdb/linux-nat.c
+++ b/gdb/linux-nat.c
@@ -67,10 +67,6 @@
 # endif
 #endif /* HAVE_PERSONALITY */
 
-/* To be used when one needs to know wether a
-   WSTOPSIG (status) is a syscall */
-#define TRAP_IS_SYSCALL (SIGTRAP | 0x80)
-
 /* This comment documents high-level logic of this file. 
 
 Waiting for events in sync mode
@@ -188,6 +184,11 @@ blocked.  */
 
 #endif /* PTRACE_EVENT_FORK */
 
+/* Unlike other extended result codes, WSTOPSIG (status) on
+   PTRACE_O_TRACESYSGOOD syscall events doesn't return SIGTRAP, but
+   instead SIGTRAP with bit 7 set.  */
+#define SYSCALL_SIGTRAP (SIGTRAP | 0x80)
+
 /* We can't always assume that this flag is available, but all systems
    with the ptrace event handlers also have __WALL, so it's safe to use
    here.  */
@@ -980,8 +981,14 @@ status_to_str (int status)
   static char buf[64];
 
   if (WIFSTOPPED (status))
-    snprintf (buf, sizeof (buf), "%s (stopped)",
-             strsignal (WSTOPSIG (status)));
+    {
+      if (WSTOPSIG (status) == SYSCALL_SIGTRAP)
+       snprintf (buf, sizeof (buf), "%s (stopped at syscall)",
+                 strsignal (SIGTRAP));
+      else
+       snprintf (buf, sizeof (buf), "%s (stopped)",
+                 strsignal (WSTOPSIG (status)));
+    }
   else if (WIFSIGNALED (status))
     snprintf (buf, sizeof (buf), "%s (terminated)",
              strsignal (WSTOPSIG (status)));
@@ -1507,74 +1514,78 @@ linux_nat_attach (struct target_ops *ops, char *args, int from_tty)
 static int
 get_pending_status (struct lwp_info *lp, int *status)
 {
-  struct target_waitstatus last;
-  ptid_t last_ptid;
-
-  get_last_target_status (&last_ptid, &last);
+  enum target_signal signo = TARGET_SIGNAL_0;
+
+  /* If we paused threads momentarily, we may have stored pending
+     events in lp->status or lp->waitstatus (see stop_wait_callback),
+     and GDB core hasn't seen any signal for those threads.
+     Otherwise, the last signal reported to the core is found in the
+     thread object's stop_signal.
+
+     There's a corner case that isn't handled here at present.  Only
+     if the thread stopped with a TARGET_WAITKIND_STOPPED does
+     stop_signal make sense as a real signal to pass to the inferior.
+     Some catchpoint related events, like
+     TARGET_WAITKIND_(V)FORK|EXEC|SYSCALL, have their stop_signal set
+     to TARGET_SIGNAL_SIGTRAP when the catchpoint triggers.  But,
+     those traps are debug API (ptrace in our case) related and
+     induced; the inferior wouldn't see them if it wasn't being
+     traced.  Hence, we should never pass them to the inferior, even
+     when set to pass state.  Since this corner case isn't handled by
+     infrun.c when proceeding with a signal, for consistency, neither
+     do we handle it here (or elsewhere in the file we check for
+     signal pass state).  Normally SIGTRAP isn't set to pass state, so
+     this is really a corner case.  */
 
-  /* If this lwp is the ptid that GDB is processing an event from, the
-     signal will be in stop_signal.  Otherwise, we may cache pending
-     events in lp->status while trying to stop all threads (see
-     stop_wait_callback).  */
-
-  *status = 0;
-
-  if (non_stop)
+  if (lp->waitstatus.kind != TARGET_WAITKIND_IGNORE)
+    signo = TARGET_SIGNAL_0; /* a pending ptrace event, not a real signal.  */
+  else if (lp->status)
+    signo = target_signal_from_host (WSTOPSIG (lp->status));
+  else if (non_stop && !is_executing (lp->ptid))
     {
-      enum target_signal signo = TARGET_SIGNAL_0;
+      struct thread_info *tp = find_thread_ptid (lp->ptid);
+      signo = tp->stop_signal;
+    }
+  else if (!non_stop)
+    {
+      struct target_waitstatus last;
+      ptid_t last_ptid;
 
-      if (is_executing (lp->ptid))
-       {
-         /* If the core thought this lwp was executing --- e.g., the
-            executing property hasn't been updated yet, but the
-            thread has been stopped with a stop_callback /
-            stop_wait_callback sequence (see linux_nat_detach for
-            example) --- we can only have pending events in the local
-            queue.  */
-         signo = target_signal_from_host (WSTOPSIG (lp->status));
-       }
-      else
-       {
-         /* If the core knows the thread is not executing, then we
-            have the last signal recorded in
-            thread_info->stop_signal.  */
+      get_last_target_status (&last_ptid, &last);
 
+      if (GET_LWP (lp->ptid) == GET_LWP (last_ptid))
+       {
          struct thread_info *tp = find_thread_ptid (lp->ptid);
          signo = tp->stop_signal;
        }
+    }
 
-      if (signo != TARGET_SIGNAL_0
-         && !signal_pass_state (signo))
-       {
-         if (debug_linux_nat)
-           fprintf_unfiltered (gdb_stdlog, "\
-GPT: lwp %s had signal %s, but it is in no pass state\n",
-                               target_pid_to_str (lp->ptid),
-                               target_signal_to_string (signo));
-       }
-      else
-       {
-         if (signo != TARGET_SIGNAL_0)
-           *status = W_STOPCODE (target_signal_to_host (signo));
+  *status = 0;
 
-         if (debug_linux_nat)
-           fprintf_unfiltered (gdb_stdlog,
-                               "GPT: lwp %s as pending signal %s\n",
-                               target_pid_to_str (lp->ptid),
-                               target_signal_to_string (signo));
-       }
+  if (signo == TARGET_SIGNAL_0)
+    {
+      if (debug_linux_nat)
+       fprintf_unfiltered (gdb_stdlog,
+                           "GPT: lwp %s has no pending signal\n",
+                           target_pid_to_str (lp->ptid));
+    }
+  else if (!signal_pass_state (signo))
+    {
+      if (debug_linux_nat)
+       fprintf_unfiltered (gdb_stdlog, "\
+GPT: lwp %s had signal %s, but it is in no pass state\n",
+                           target_pid_to_str (lp->ptid),
+                           target_signal_to_string (signo));
     }
   else
     {
-      if (GET_LWP (lp->ptid) == GET_LWP (last_ptid))
-       {
-         struct thread_info *tp = find_thread_ptid (lp->ptid);
-         if (tp->stop_signal != TARGET_SIGNAL_0
-             && signal_pass_state (tp->stop_signal))
-           *status = W_STOPCODE (target_signal_to_host (tp->stop_signal));
-       }
-      else
-       *status = lp->status;
+      *status = W_STOPCODE (target_signal_to_host (signo));
+
+      if (debug_linux_nat)
+       fprintf_unfiltered (gdb_stdlog,
+                           "GPT: lwp %s has pending signal %s\n",
+                           target_pid_to_str (lp->ptid),
+                           target_signal_to_string (signo));
     }
 
   return 0;
@@ -1886,6 +1897,133 @@ kill_lwp (int lwpid, int signo)
   return kill (lwpid, signo);
 }
 
+/* Handle a GNU/Linux syscall trap wait response.  If we see a syscall
+   event, check if the core is interested in it: if not, ignore the
+   event, and keep waiting; otherwise, we need to toggle the LWP's
+   syscall entry/exit status, since the ptrace event itself doesn't
+   indicate it, and report the trap to higher layers.  */
+
+static int
+linux_handle_syscall_trap (struct lwp_info *lp, int stopping)
+{
+  struct target_waitstatus *ourstatus = &lp->waitstatus;
+  struct gdbarch *gdbarch = target_thread_architecture (lp->ptid);
+  int syscall_number = (int) gdbarch_get_syscall_number (gdbarch, lp->ptid);
+
+  if (stopping)
+    {
+      /* If we're stopping threads, there's a SIGSTOP pending, which
+        makes it so that the LWP reports an immediate syscall return,
+        followed by the SIGSTOP.  Skip seeing that "return" using
+        PTRACE_CONT directly, and let stop_wait_callback collect the
+        SIGSTOP.  Later when the thread is resumed, a new syscall
+        entry event.  If we didn't do this (and returned 0), we'd
+        leave a syscall entry pending, and our caller, by using
+        PTRACE_CONT to collect the SIGSTOP, skips the syscall return
+        itself.  Later, when the user re-resumes this LWP, we'd see
+        another syscall entry event and we'd mistake it for a return.
+
+        If stop_wait_callback didn't force the SIGSTOP out of the LWP
+        (leaving immediately with LWP->signalled set, without issuing
+        a PTRACE_CONT), it would still be problematic to leave this
+        syscall enter pending, as later when the thread is resumed,
+        it would then see the same syscall exit mentioned above,
+        followed by the delayed SIGSTOP, while the syscall didn't
+        actually get to execute.  It seems it would be even more
+        confusing to the user.  */
+
+      if (debug_linux_nat)
+       fprintf_unfiltered (gdb_stdlog,
+                           "LHST: ignoring syscall %d "
+                           "for LWP %ld (stopping threads), "
+                           "resuming with PTRACE_CONT for SIGSTOP\n",
+                           syscall_number,
+                           GET_LWP (lp->ptid));
+
+      lp->syscall_state = TARGET_WAITKIND_IGNORE;
+      ptrace (PTRACE_CONT, GET_LWP (lp->ptid), 0, 0);
+      return 1;
+    }
+
+  if (catch_syscall_enabled ())
+    {
+      /* Always update the entry/return state, even if this particular
+        syscall isn't interesting to the core now.  In async mode,
+        the user could install a new catchpoint for this syscall
+        between syscall enter/return, and we'll need to know to
+        report a syscall return if that happens.  */
+      lp->syscall_state = (lp->syscall_state == TARGET_WAITKIND_SYSCALL_ENTRY
+                          ? TARGET_WAITKIND_SYSCALL_RETURN
+                          : TARGET_WAITKIND_SYSCALL_ENTRY);
+
+      if (catching_syscall_number (syscall_number))
+       {
+         /* Alright, an event to report.  */
+         ourstatus->kind = lp->syscall_state;
+         ourstatus->value.syscall_number = syscall_number;
+
+         if (debug_linux_nat)
+           fprintf_unfiltered (gdb_stdlog,
+                               "LHST: stopping for %s of syscall %d"
+                               " for LWP %ld\n",
+                               lp->syscall_state == TARGET_WAITKIND_SYSCALL_ENTRY
+                               ? "entry" : "return",
+                               syscall_number,
+                               GET_LWP (lp->ptid));
+         return 0;
+       }
+
+      if (debug_linux_nat)
+       fprintf_unfiltered (gdb_stdlog,
+                           "LHST: ignoring %s of syscall %d "
+                           "for LWP %ld\n",
+                           lp->syscall_state == TARGET_WAITKIND_SYSCALL_ENTRY
+                           ? "entry" : "return",
+                           syscall_number,
+                           GET_LWP (lp->ptid));
+    }
+  else
+    {
+      /* If we had been syscall tracing, and hence used PT_SYSCALL
+        before on this LWP, it could happen that the user removes all
+        syscall catchpoints before we get to process this event.
+        There are two noteworthy issues here:
+
+        - When stopped at a syscall entry event, resuming with
+          PT_STEP still resumes executing the syscall and reports a
+          syscall return.
+
+        - Only PT_SYSCALL catches syscall enters.  If we last
+          single-stepped this thread, then this event can't be a
+          syscall enter.  If we last single-stepped this thread, this
+          has to be a syscall exit.
+
+        The points above mean that the next resume, be it PT_STEP or
+        PT_CONTINUE, can not trigger a syscall trace event.  */
+      if (debug_linux_nat)
+       fprintf_unfiltered (gdb_stdlog,
+                           "LHST: caught syscall event with no syscall catchpoints."
+                           " %d for LWP %ld, ignoring\n",
+                           syscall_number,
+                           GET_LWP (lp->ptid));
+      lp->syscall_state = TARGET_WAITKIND_IGNORE;
+    }
+
+  /* The core isn't interested in this event.  For efficiency, avoid
+     stopping all threads only to have the core resume them all again.
+     Since we're not stopping threads, if we're still syscall tracing
+     and not stepping, we can't use PTRACE_CONT here, as we'd miss any
+     subsequent syscall.  Simply resume using the inf-ptrace layer,
+     which knows when to use PT_SYSCALL or PT_CONTINUE.  */
+
+  /* Note that gdbarch_get_syscall_number may access registers, hence
+     fill a regcache.  */
+  registers_changed ();
+  linux_ops->to_resume (linux_ops, pid_to_ptid (GET_LWP (lp->ptid)),
+                       lp->step, TARGET_SIGNAL_0);
+  return 1;
+}
+
 /* Handle a GNU/Linux extended wait response.  If we see a clone
    event, we need to add the new LWP to our list (and not report the
    trap to higher layers).  This function returns non-zero if the
@@ -2011,19 +2149,30 @@ linux_handle_extended_wait (struct lwp_info *lp, int status,
                }
            }
 
+         /* Note the need to use the low target ops to resume, to
+            handle resuming with PT_SYSCALL if we have syscall
+            catchpoints.  */
          if (!stopping)
            {
+             int signo;
+
              new_lp->stopped = 0;
              new_lp->resumed = 1;
-             ptrace (PTRACE_CONT, new_pid, 0,
-                     status ? WSTOPSIG (status) : 0);
+
+             signo = (status
+                      ? target_signal_from_host (WSTOPSIG (status))
+                      : TARGET_SIGNAL_0);
+
+             linux_ops->to_resume (linux_ops, pid_to_ptid (new_pid),
+                                   0, signo);
            }
 
          if (debug_linux_nat)
            fprintf_unfiltered (gdb_stdlog,
                                "LHEW: Got clone event from LWP %ld, resuming\n",
                                GET_LWP (lp->ptid));
-         ptrace (PTRACE_CONT, GET_LWP (lp->ptid), 0, 0);
+         linux_ops->to_resume (linux_ops, pid_to_ptid (GET_LWP (lp->ptid)),
+                               0, TARGET_SIGNAL_0);
 
          return 1;
        }
@@ -2063,47 +2212,6 @@ linux_handle_extended_wait (struct lwp_info *lp, int status,
       return 0;
     }
 
-  /* Used for 'catch syscall' feature.  */
-  if (WSTOPSIG (status) == TRAP_IS_SYSCALL)
-    {
-      if (catch_syscall_enabled () == 0)
-         ourstatus->kind = TARGET_WAITKIND_IGNORE;
-      else
-       {
-         struct regcache *regcache = get_thread_regcache (lp->ptid);
-         struct gdbarch *gdbarch = get_regcache_arch (regcache);
-
-         ourstatus->value.syscall_number =
-           (int) gdbarch_get_syscall_number (gdbarch, lp->ptid);
-
-         /* If we are catching this specific syscall number, then we
-            should update the target_status to reflect which event
-            has occurred.  But if this syscall is not to be caught,
-            then we can safely mark the event as a SYSCALL_RETURN.
-
-            This is particularly needed if:
-
-              - We are catching any syscalls, or
-              - We are catching the syscall "exit"
-
-            In this case, as the syscall "exit" *doesn't* return,
-            then GDB would be confused because it would mark the last
-            syscall event as a SYSCALL_ENTRY.  After that, if we re-ran the
-            inferior GDB will think that the first syscall event is
-            the opposite of a SYSCALL_ENTRY, which is the SYSCALL_RETURN.
-            Therefore, GDB would report inverted syscall events.  */
-         if (catching_syscall_number (ourstatus->value.syscall_number))
-           ourstatus->kind = 
-             (lp->syscall_state == TARGET_WAITKIND_SYSCALL_ENTRY) ?
-             TARGET_WAITKIND_SYSCALL_RETURN : TARGET_WAITKIND_SYSCALL_ENTRY;
-         else
-           ourstatus->kind = TARGET_WAITKIND_SYSCALL_RETURN;
-
-         lp->syscall_state = ourstatus->kind;
-       }
-      return 0;
-    }
-
   internal_error (__FILE__, __LINE__,
                  _("unknown ptrace event %d"), event);
 }
@@ -2169,6 +2277,18 @@ wait_lwp (struct lwp_info *lp)
 
   gdb_assert (WIFSTOPPED (status));
 
+  /* Handle GNU/Linux's syscall SIGTRAPs.  */
+  if (WIFSTOPPED (status) && WSTOPSIG (status) == SYSCALL_SIGTRAP)
+    {
+      /* No longer need the sysgood bit.  The ptrace event ends up
+        recorded in lp->waitstatus if we care for it.  We can carry
+        on handling the event like a regular SIGTRAP from here
+        on.  */
+      status = W_STOPCODE (SIGTRAP);
+      if (linux_handle_syscall_trap (lp, 1))
+       return wait_lwp (lp);
+    }
+
   /* Handle GNU/Linux's extended waitstatus for trace events.  */
   if (WIFSTOPPED (status) && WSTOPSIG (status) == SIGTRAP && status >> 16 != 0)
     {
@@ -2435,12 +2555,23 @@ status_callback (struct lwp_info *lp, void *data)
 {
   /* Only report a pending wait status if we pretend that this has
      indeed been resumed.  */
-  /* We check for lp->waitstatus in addition to lp->status, because we
-     can have pending process exits recorded in lp->waitstatus, and
-     W_EXITCODE(0,0) == 0.  */
-  return ((lp->status != 0
-          || lp->waitstatus.kind != TARGET_WAITKIND_IGNORE)
-         && lp->resumed);
+  if (!lp->resumed)
+    return 0;
+
+  if (lp->waitstatus.kind != TARGET_WAITKIND_IGNORE)
+    {
+      /* A ptrace event, like PTRACE_FORK|VFORK|EXEC, syscall event,
+        or a a pending process exit.  Note that `W_EXITCODE(0,0) ==
+        0', so a clean process exit can not be stored pending in
+        lp->status, it is indistinguishable from
+        no-pending-status.  */
+      return 1;
+    }
+
+  if (lp->status != 0)
+    return 1;
+
+  return 0;
 }
 
 /* Return non-zero if LP isn't stopped.  */
@@ -2550,7 +2681,8 @@ cancel_breakpoints_callback (struct lwp_info *lp, void *data)
      delete or disable the breakpoint, but the LWP will have already
      tripped on it.  */
 
-  if (lp->status != 0
+  if (lp->waitstatus.kind == TARGET_WAITKIND_IGNORE
+      && lp->status != 0
       && WIFSTOPPED (lp->status) && WSTOPSIG (lp->status) == SIGTRAP
       && cancel_breakpoint (lp))
     /* Throw away the SIGTRAP.  */
@@ -2701,17 +2833,20 @@ linux_nat_filter_event (int lwpid, int status, int options)
       add_thread (lp->ptid);
     }
 
-  /* Save the trap's siginfo in case we need it later.  */
-  if (WIFSTOPPED (status)
-      && (WSTOPSIG (status) == SIGTRAP || WSTOPSIG (status) == TRAP_IS_SYSCALL))
-    save_siginfo (lp);
+  /* Handle GNU/Linux's syscall SIGTRAPs.  */
+  if (WIFSTOPPED (status) && WSTOPSIG (status) == SYSCALL_SIGTRAP)
+    {
+      /* No longer need the sysgood bit.  The ptrace event ends up
+        recorded in lp->waitstatus if we care for it.  We can carry
+        on handling the event like a regular SIGTRAP from here
+        on.  */
+      status = W_STOPCODE (SIGTRAP);
+      if (linux_handle_syscall_trap (lp, 0))
+       return NULL;
+    }
 
-  /* Handle GNU/Linux's extended waitstatus for trace events.
-     It is necessary to check if WSTOPSIG is signaling that
-     the inferior is entering/exiting a system call.  */
-  if (WIFSTOPPED (status)
-      && ((WSTOPSIG (status) == TRAP_IS_SYSCALL)
-          || (WSTOPSIG (status) == SIGTRAP && status >> 16 != 0)))
+  /* Handle GNU/Linux's extended waitstatus for trace events.  */
+  if (WIFSTOPPED (status) && WSTOPSIG (status) == SIGTRAP && status >> 16 != 0)
     {
       if (debug_linux_nat)
        fprintf_unfiltered (gdb_stdlog,
@@ -2721,6 +2856,10 @@ linux_nat_filter_event (int lwpid, int status, int options)
        return NULL;
     }
 
+  /* Save the trap's siginfo in case we need it later.  */
+  if (WIFSTOPPED (status) && WSTOPSIG (status) == SIGTRAP)
+    save_siginfo (lp);
+
   /* Check if the thread has exited.  */
   if ((WIFEXITED (status) || WIFSIGNALED (status))
       && num_lwps (GET_PID (lp->ptid)) > 1)
@@ -2842,6 +2981,7 @@ linux_nat_filter_event (int lwpid, int status, int options)
 
   /* An interesting event.  */
   gdb_assert (lp);
+  lp->status = status;
   return lp;
 }
 
@@ -2901,13 +3041,10 @@ retry:
       lp = iterate_over_lwps (ptid, status_callback, NULL);
       if (lp)
        {
-         status = lp->status;
-         lp->status = 0;
-
-         if (debug_linux_nat && status)
+         if (debug_linux_nat && lp->status)
            fprintf_unfiltered (gdb_stdlog,
                                "LLW: Using pending wait status %s for %s.\n",
-                               status_to_str (status),
+                               status_to_str (lp->status),
                                target_pid_to_str (lp->ptid));
        }
 
@@ -2926,13 +3063,11 @@ retry:
       /* We have a specific LWP to check.  */
       lp = find_lwp_pid (ptid);
       gdb_assert (lp);
-      status = lp->status;
-      lp->status = 0;
 
-      if (debug_linux_nat && status)
+      if (debug_linux_nat && lp->status)
        fprintf_unfiltered (gdb_stdlog,
                            "LLW: Using pending wait status %s for %s.\n",
-                           status_to_str (status),
+                           status_to_str (lp->status),
                            target_pid_to_str (lp->ptid));
 
       /* If we have to wait, take into account whether PID is a cloned
@@ -2945,7 +3080,7 @@ retry:
         because we can have pending process exits recorded in
         lp->status and W_EXITCODE(0,0) == 0.  We should probably have
         an additional lp->status_p flag.  */
-      if (status == 0 && lp->waitstatus.kind == TARGET_WAITKIND_IGNORE)
+      if (lp->status == 0 && lp->waitstatus.kind == TARGET_WAITKIND_IGNORE)
        lp = NULL;
     }
 
@@ -2973,8 +3108,26 @@ retry:
       lp->stopped = 0;
       gdb_assert (lp->resumed);
 
-      /* This should catch the pending SIGSTOP.  */
+      /* Catch the pending SIGSTOP.  */
+      status = lp->status;
+      lp->status = 0;
+
       stop_wait_callback (lp, NULL);
+
+      /* If the lp->status field isn't empty, we caught another signal
+        while flushing the SIGSTOP.  Return it back to the event
+        queue of the LWP, as we already have an event to handle.  */
+      if (lp->status)
+       {
+         if (debug_linux_nat)
+           fprintf_unfiltered (gdb_stdlog,
+                               "LLW: kill %s, %s\n",
+                               target_pid_to_str (lp->ptid),
+                               status_to_str (lp->status));
+         kill_lwp (GET_LWP (lp->ptid), WSTOPSIG (lp->status));
+       }
+
+      lp->status = status;
     }
 
   if (!target_can_async_p ())
@@ -3014,12 +3167,10 @@ retry:
                fprintf (stderr, "LWP %ld got an event %06x, leaving pending.\n",
                         ptid_get_lwp (lp->ptid), status);
 
-             if (WIFSTOPPED (status))
+             if (WIFSTOPPED (lp->status))
                {
-                 if (WSTOPSIG (status) != SIGSTOP)
+                 if (WSTOPSIG (lp->status) != SIGSTOP)
                    {
-                     lp->status = status;
-
                      stop_callback (lp, NULL);
 
                      /* Resume in order to collect the sigstop.  */
@@ -3046,7 +3197,6 @@ retry:
                     about the exit code/signal, leave the status
                     pending for the next time we're able to report
                     it.  */
-                 lp->status = status;
 
                  /* Prevent trying to stop this thread again.  We'll
                     never try to resume it because it has a pending
@@ -3059,7 +3209,7 @@ retry:
 
                  /* Store the pending event in the waitstatus as
                     well, because W_EXITCODE(0,0) == 0.  */
-                 store_waitstatus (&lp->waitstatus, status);
+                 store_waitstatus (&lp->waitstatus, lp->status);
                }
 
              /* Keep looking.  */
@@ -3115,6 +3265,9 @@ retry:
 
   gdb_assert (lp);
 
+  status = lp->status;
+  lp->status = 0;
+
   /* Don't report signals that GDB isn't interested in, such as
      signals that are neither printed nor stopped upon.  Stopping all
      threads can be a bit time-consuming so if we want decent

diff --git a/gdb/mi/gdb-mi.el b/gdb/mi/gdb-mi.el
deleted file mode 100644 (file)
index 031de00..0000000
--- a/gdb/mi/gdb-mi.el
+++ /dev/null
@@ -1,609 +0,0 @@
-;;; gdb-mi.el
-
-;; Author: Nick Roberts <nickrob@gnu.org>
-;; Maintainer: Nick Roberts <nickrob@gnu.org>
-;; Keywords: unix, tools
-
-;; Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009
-;; Free Software Foundation, Inc.
-
-;; This file is part of GNU GDB.
-
-;; GNU GDB is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; This program is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;;; Commentary:
-
-;; This mode acts as a graphical user interface to GDB and works with Emacs
-;; 22.x and the version of GDB with which it is distributed.  You can interact
-;; with GDB through the GUD buffer in the usual way, but there are also
-;; buffers which control the execution and describe the state of your program.
-;; It separates the input/output of your program from that of GDB and displays
-;; expressions and their current values in their own buffers.  It also uses
-;; features of Emacs 21 such as the fringe/display margin for breakpoints, and
-;; the toolbar (see the GDB Graphical Interface section in the Emacs info
-;; manual).
-
-;; Start the debugger with M-x gdbmi.
-
-;; This file uses GDB/MI as the primary interface to GDB. It is still under
-;; development and is part of a process to migrate Emacs from annotations (as
-;; used in gdb-ui.el) to GDB/MI.  It runs gdb with GDB/MI (-interp=mi) and
-;; access CLI using "-interpreter-exec console cli-command".
-
-;; This mode acts on top of gdb-ui.el.  After the release of 22.1,
-;; mainline Emacs in the CVS repository will have a file also called gdb-mi.el
-;; which will *replace* gdb-ui.el.  If you are interested in developing
-;; this mode you should get this version.
-;;
-;; Known Bugs:
-;;
-;; 1) To handle program input, if required, and to avoid extra output in the
-;; GUD buffer you must not use run, step, next or continue etc but their MI
-;; counterparts through gud-run, gud-step etc, e.g clicking on the appropriate
-;; icon in the toolbar.
-;; 2) Some commands send extra prompts to the GUD buffer.
-;; 3) Doesn't list catchpoints in breakpoints buffer.
-;;
-;; TODO:
-;; 1) Prefix MI commands with a token instead of queueing commands.
-;; 2) Use MI command -data-read-memory for memory window.
-;; 3) Use MI command -data-disassemble for disassembly window.
-;; 4) Allow separate buffers for Inferior IO and GDB IO.
-;; 5) Watch windows to work with threads.
-;;
-;;; Code:
-
-(require 'gud)
-(require 'gdb-ui)
-
-(defvar gdb-last-command nil)
-(defvar gdb-prompt-name nil)
-
-;;;###autoload
-(defun gdbmi (command-line)
-  "Run gdb on program FILE in buffer *gud-FILE*.
-The directory containing FILE becomes the initial working directory
-and source-file directory for your debugger.
-
-If `gdb-many-windows' is nil (the default value) then gdb just
-pops up the GUD buffer unless `gdb-show-main' is t. In this case
-it starts with two windows: one displaying the GUD buffer and the
-other with the source file with the main routine of the inferior.
-
-If `gdb-many-windows' is t, regardless of the value of
-`gdb-show-main', the layout below will appear. Keybindings are
-given in relevant buffer.
-
-Watch expressions appear in the speedbar/slowbar.
-
-The following commands help control operation :
-
-`gdb-many-windows'    - Toggle the number of windows gdb uses.
-`gdb-restore-windows' - To restore the window layout.
-
-See Info node `(emacs)GDB Graphical Interface' for a more
-detailed description of this mode.
-
-
-+--------------------------------------------------------------+
-|                           GDB Toolbar                        |
-+-------------------------------+------------------------------+
-| GUD buffer (I/O of GDB)       | Locals buffer                |
-|                               |                              |
-|                               |                              |
-|                               |                              |
-+-------------------------------+------------------------------+
-| Source buffer                                                |
-|                                                              |
-|                                                              |
-|                                                              |
-|                                                              |
-|                                                              |
-|                                                              |
-|                                                              |
-+-------------------------------+------------------------------+
-| Stack buffer                  | Breakpoints buffer           |
-| RET      gdb-frames-select    | SPC    gdb-toggle-breakpoint |
-|                               | RET    gdb-goto-breakpoint   |
-|                               | d      gdb-delete-breakpoint |
-+-------------------------------+------------------------------+"
-  ;;
-  (interactive (list (gud-query-cmdline 'gdbmi)))
-  ;;
-  ;; Let's start with a basic gud-gdb buffer and then modify it a bit.
-  (gdb command-line)
-  ;;
-  (setq gdb-debug-ring nil)
-  (set (make-local-variable 'gud-minor-mode) 'gdbmi)
-  (set (make-local-variable 'gud-marker-filter) 'gud-gdbmi-marker-filter)
-  ;;
-  (gud-def gud-step   "-exec-step %p"              "\C-s" 
-          "Step one source line with display.")
-  (gud-def gud-stepi  "-exec-step-instruction %p"  "\C-i"
-          "Step one instruction with display.")
-  (gud-def gud-next   "-exec-next %p"              "\C-n"
-          "Step one line (skip functions).")
-  (gud-def gud-cont   "-exec-continue"             "\C-r"
-          "Continue with display.")
-  (gud-def gud-finish "-exec-finish"               "\C-f"
-          "Finish executing current function.")
-  (gud-def gud-run    "-exec-run"           nil    "Run the program.")
-  (gud-def gud-break (if (not (string-equal mode-name "Machine"))
-                        (gud-call "break %f:%l" arg)
-                      (save-excursion
-                        (beginning-of-line)
-                        (forward-char 2)
-                        (gud-call "break *%a" arg)))
-          "\C-b" "Set breakpoint at current line or address.")
-  ;;
-  (gud-def gud-remove (if (not (string-equal mode-name "Machine"))
-                         (gud-call "clear %f:%l" arg)
-                       (save-excursion
-                         (beginning-of-line)
-                         (forward-char 2)
-                         (gud-call "clear *%a" arg)))
-          "\C-d" "Remove breakpoint at current line or address.")
-  ;;
-  (gud-def gud-until  (if (not (string-equal mode-name "Machine"))
-                         (gud-call "-exec-until %f:%l" arg)
-                       (save-excursion
-                         (beginning-of-line)
-                         (forward-char 2)
-                         (gud-call "-exec-until *%a" arg)))
-          "\C-u" "Continue to current line or address.")
-
-  (define-key gud-minor-mode-map [left-margin mouse-1]
-    'gdb-mouse-set-clear-breakpoint)
-  (define-key gud-minor-mode-map [left-fringe mouse-1]
-    'gdb-mouse-set-clear-breakpoint)
-  (define-key gud-minor-mode-map [left-fringe mouse-2]
-    'gdb-mouse-until)
-  (define-key gud-minor-mode-map [left-fringe drag-mouse-1]
-    'gdb-mouse-until)
-  (define-key gud-minor-mode-map [left-margin mouse-3]
-    'gdb-mouse-toggle-breakpoint-margin)
-  (define-key gud-minor-mode-map [left-fringe mouse-3]
-    'gdb-mouse-toggle-breakpoint-fringe)
-
-  (setq comint-input-sender 'gdbmi-send)
-  ;;
-  ;; (re-)initialise
-  (setq gdb-pc-address (if gdb-show-main "main" nil)
-        gdb-previous-frame-address nil
-        gdb-memory-address "main"
-        gdb-previous-frame nil
-        gdb-selected-frame nil
-        gdb-frame-number nil
-        gdb-var-list nil
-        gdb-prompting nil
-        gdb-input-queue nil
-        gdb-current-item nil
-        gdb-pending-triggers nil
-        gdb-output-sink 'user
-        gdb-server-prefix nil
-        gdb-flush-pending-output nil
-        gdb-location-alist nil
-        gdb-source-file-list nil
-        gdb-last-command nil
-       gdb-prompt-name nil
-       gdb-buffer-fringe-width (car (window-fringes)))
-       gdb-debug-ring nil
-       gdb-source-window nil
-       gdb-inferior-status nil
-       gdb-continuation nil
-  ;;
-  (setq gdb-buffer-type 'gdbmi)
-  ;;
-  ;; FIXME: use tty command to separate io.
-  ;;(gdb-clear-inferior-io)
-  ;;
-  (if (eq window-system 'w32)
-      (gdb-enqueue-input (list "-gdb-set new-console off\n" 'ignore)))
-  (gdb-enqueue-input (list "-gdb-set height 0\n" 'ignore))
-  ;; find source file and compilation directory here
-  (gdb-enqueue-input
-   ; Needs GDB 6.2 onwards.
-   (list "-file-list-exec-source-files\n"
-        'gdb-set-gud-minor-mode-existing-buffers-1))
-  (gdb-enqueue-input
-   ; Needs GDB 6.0 onwards.
-   (list "-file-list-exec-source-file\n" 'gdb-get-source-file))
-  (gdb-enqueue-input
-   (list "-data-list-register-names\n" 'gdb-get-register-names))
-  (gdb-enqueue-input
-   (list "-gdb-show prompt\n" 'gdb-get-prompt))
-  ;;
-  (setq gdb-locals-font-lock-keywords gdb-locals-font-lock-keywords-2)
-  (run-hooks 'gdbmi-mode-hook))
-
-\f
-(defun gdbmi-send (proc string)
-  "A comint send filter for gdb."
-  (if gud-running
-      (process-send-string proc (concat string "\n"))
-    (with-current-buffer gud-comint-buffer
-      (let ((inhibit-read-only t))
-       (remove-text-properties (point-min) (point-max) '(face))))
-    (setq gdb-output-sink 'user)
-    (setq gdb-prompting nil)
-    ;; mimic <RET> key to repeat previous command in GDB
-    (if (not (string-match "^\\s+$" string))
-        (setq gdb-last-command string)
-      (if gdb-last-command (setq string gdb-last-command)))
-    (if gdb-enable-debug
-       (push (cons 'mi-send (concat string "\n")) gdb-debug-ring))
-     (if (string-match "^-" string)
-        ;; MI command
-        (process-send-string proc (concat string "\n"))
-       ;; CLI command
-    (if (string-match "\\\\$" string)
-       (setq gdb-continuation (concat gdb-continuation string "\n"))
-      (process-send-string proc
-                          (concat "-interpreter-exec console \""
-                                  gdb-continuation string "\"\n"))
-      (setq gdb-continuation nil)))))
-
-(defcustom gud-gdbmi-command-name "gdb -interp=mi"
-  "Default command to execute an executable under the GDB-UI debugger."
-  :type 'string
-  :group 'gud)
-
-(defconst gdb-gdb-regexp "(gdb) \n")
-
-(defconst gdb-running-regexp (concat "\\^running\n" gdb-gdb-regexp))
-
-;; fullname added GDB 6.4+.
-;; Probably not needed. -stack-info-frame computes filename and line.
-(defconst gdb-stopped-regexp
-  "\\*stopped,reason=.*?,file=\".*?\"\
-,fullname=\"\\(.*?\\)\",line=\"\\(.*?\\)\"}\n")
-
-(defconst gdb-error-regexp "\\^error,msg=\\(\".+\"\\)\n")
-
-(defconst gdb-done-regexp "\\^done,*\n*")
-
-(defconst gdb-console-regexp "~\\(\".*?[^\\]\"\\)\n")
-
-(defconst gdb-internals-regexp "&\\(\".*?\\n\"\\)\n")
-
-(defun gdbmi-prompt1 ()
-  "Queue any GDB commands that the user interface needs."
-  (unless gdb-pending-triggers
-    (gdbmi-get-selected-frame)
-    (gdbmi-invalidate-frames)
-    (gdbmi-invalidate-breakpoints)
-    (gdb-get-changed-registers)
-    (gdb-invalidate-registers-1)
-    (gdb-invalidate-locals-1)
-    (if (and (boundp 'speedbar-frame) (frame-live-p speedbar-frame))
-       (gdb-var-update-1))))
-
-(defun gdbmi-prompt2 ()
-  "Handle any output and send next GDB command."
-  (let ((sink gdb-output-sink))
-    (when (eq sink 'emacs)
-      (let ((handler
-            (car (cdr gdb-current-item))))
-       (with-current-buffer (gdb-get-buffer-create 'gdb-partial-output-buffer)
-         (funcall handler)))))
-  (let ((input (gdb-dequeue-input)))
-    (if input
-       (gdb-send-item input)
-      (progn
-       (setq gud-running nil)
-       (setq gdb-prompting t)
-       (gud-display-frame)))))
-
-(defun gud-gdbmi-marker-filter (string)
-  "Filter GDB/MI output."
-  (if gdb-flush-pending-output
-      nil
-    (if gdb-enable-debug (push (cons 'recv (list string gdb-output-sink))
-                                        gdb-debug-ring))
-    ;; Recall the left over gud-marker-acc from last time
-    (setq gud-marker-acc (concat gud-marker-acc string))
-    ;; Start accumulating output for the GUD buffer
-    (let ((output "") running)
-
-      (if (string-match gdb-running-regexp gud-marker-acc) 
-         (setq
-          gud-marker-acc
-          (concat (substring gud-marker-acc 0 (match-beginning 0))
-                  (substring gud-marker-acc (match-end 0)))
-          running t))
-
-      (if (string-match gdb-stopped-regexp gud-marker-acc)
-         (setq
-
-          ;; Extract the frame position from the marker.
-          gud-last-frame (cons (match-string 1 gud-marker-acc)
-                               (string-to-number
-                                (match-string 2 gud-marker-acc)))
-
-          gud-marker-acc
-          (concat (substring gud-marker-acc 0 (match-beginning 0))
-                  (substring gud-marker-acc (match-end 0)))))
-
-      ;; Filter error messages going to GUD buffer and
-      ;; display in minibuffer.
-      (when (eq gdb-output-sink 'user)
-       (while (string-match gdb-error-regexp gud-marker-acc)
-         (message (read (match-string 1 gud-marker-acc)))
-         (setq 
-          gud-marker-acc
-          (concat (substring gud-marker-acc 0 (match-beginning 0))
-                  (substring gud-marker-acc (match-end 0)))))
-
-       (if (string-match gdb-done-regexp gud-marker-acc)
-           (setq 
-            gud-marker-acc
-            (concat (substring gud-marker-acc 0 (match-beginning 0))
-                    (substring gud-marker-acc (match-end 0))))))
-
-      (when (string-match gdb-gdb-regexp gud-marker-acc)
-       (setq 
-        gud-marker-acc
-        (concat (substring gud-marker-acc 0 (match-beginning 0))
-                  (substring gud-marker-acc (match-end 0))))
-
-       ;; Remove the trimmings from the console stream.
-       (while (string-match gdb-console-regexp gud-marker-acc) 
-         (setq 
-          gud-marker-acc (concat
-                          (substring gud-marker-acc 0 (match-beginning 0))
-                          (read (match-string 1 gud-marker-acc))
-                          (substring gud-marker-acc (match-end 0)))))
-
-       ;; Remove the trimmings from log stream containing debugging messages
-       ;; being produced by GDB's internals and use warning face.
-       (while (string-match gdb-internals-regexp gud-marker-acc) 
-         (setq 
-          gud-marker-acc
-          (concat (substring gud-marker-acc 0 (match-beginning 0))
-                  (let ((error-message
-                         (read (match-string 1 gud-marker-acc))))
-                    (put-text-property
-                     0 (length error-message)
-                     'face font-lock-warning-face
-                     error-message)
-                    error-message)
-                  (substring gud-marker-acc (match-end 0)))))
-
-       (setq output (gdbmi-concat-output output gud-marker-acc))
-       (setq gud-marker-acc "")
-       (gdbmi-prompt1)
-       (unless gdb-input-queue
-         (setq output (concat output gdb-prompt-name)))
-       (gdbmi-prompt2)
-       (setq gud-running running))
-
-      (when gud-running
-       (setq output (gdbmi-concat-output output gud-marker-acc))
-       (setq gud-marker-acc ""))
-
-       output)))
-
-(defun gdbmi-concat-output (so-far new)
-  (let ((sink gdb-output-sink))
-    (cond
-     ((eq sink 'user) (concat so-far new))
-     ((eq sink 'emacs)
-      (gdb-append-to-partial-output new)
-      so-far)
-     ((eq sink 'inferior)
-      (gdb-append-to-inferior-io new)
-      so-far))))
-\f
-
-;; Breakpoint buffer : This displays the output of `-break-list'.
-;;
-(def-gdb-auto-update-trigger gdbmi-invalidate-breakpoints
-  (gdb-get-buffer 'gdb-breakpoints-buffer)
-  "-break-list\n"
-  gdb-break-list-handler)
-
-(defconst gdb-break-list-regexp
-"bkpt={.*?number=\"\\(.*?\\)\",.*?type=\"\\(.*?\\)\",.*?disp=\"\\(.*?\\)\",.*?\
-enabled=\"\\(.\\)\",.*?addr=\"\\(.*?\\)\",\\(?:.*?func=\"\\(.*?\\)\",.*?\
-file=\"\\(.*?\\)\",.*?fullname=\".*?\",.*?line=\"\\(.*?\\)\",\
-\\|\\(?:.*?what=\"\\(.*?\\)\",\\)*\\).*?times=\"\\(.*?\\)\".*?}")
-
-(defun gdb-break-list-handler ()
-  (setq gdb-pending-triggers (delq 'gdbmi-invalidate-breakpoints
-                                 gdb-pending-triggers))
-  (let ((breakpoint) (breakpoints-list))
-    (with-current-buffer (gdb-get-buffer-create 'gdb-partial-output-buffer)
-      (goto-char (point-min))
-      (while (re-search-forward gdb-break-list-regexp nil t)
-       (let ((breakpoint (list (match-string 1)
-                               (match-string 2)
-                               (match-string 3)
-                               (match-string 4)
-                               (match-string 5)
-                               (match-string 6)
-                               (match-string 7)
-                               (match-string 8)
-                               (match-string 9)
-                               (match-string 10))))
-         (push breakpoint breakpoints-list))))
-    (let ((buf (gdb-get-buffer 'gdb-breakpoints-buffer)))
-      (and buf (with-current-buffer buf
-                (let ((p (point))
-                      (buffer-read-only nil))
-                  (erase-buffer)
-                  (insert "Num Type           Disp Enb Hits Addr       What\n")
-                  (dolist (breakpoint breakpoints-list)
-                    (insert
-                     (concat
-                      (nth 0 breakpoint) "   "
-                      (nth 1 breakpoint) "     "
-                      (nth 2 breakpoint) " "
-                      (nth 3 breakpoint) "   "
-                      (nth 9 breakpoint) " "
-                      (nth 4 breakpoint) " "
-                      (if (nth 5 breakpoint)
-                          (concat "in " (nth 5 breakpoint) " at " (nth 6 breakpoint) ":" (nth 7 breakpoint) "\n")
-                        (concat (nth 8 breakpoint) "\n")))))
-                  (goto-char p))))))
-  (gdb-info-breakpoints-custom))
-
-(defun gdbmi-get-location (bptno line flag)
-  "Find the directory containing the relevant source file.
-Put in buffer and place breakpoint icon."
-  (goto-char (point-min))
-  (catch 'file-not-found
-    (if (re-search-forward gdb-source-file-regexp-1 nil t)
-       (delete (cons bptno "File not found") gdb-location-alist)
-       (push (cons bptno (match-string 1)) gdb-location-alist)
-      (gdb-resync)
-      (unless (assoc bptno gdb-location-alist)
-       (push (cons bptno "File not found") gdb-location-alist)
-       (message-box "Cannot find source file for breakpoint location.
-Add directory to search path for source files using the GDB command, dir."))
-      (throw 'file-not-found nil))
-    (with-current-buffer
-       (find-file-noselect (match-string 1))
-      (save-current-buffer
-       (set (make-local-variable 'gud-minor-mode) 'gdbmi)
-       (set (make-local-variable 'tool-bar-map) gud-tool-bar-map))
-      ;; only want one breakpoint icon at each location
-      (save-excursion
-       (goto-line (string-to-number line))
-       (gdb-put-breakpoint-icon (eq flag ?y) bptno)))))
-
-;; Frames buffer.  This displays a perpetually correct bactrack trace.
-;;
-(def-gdb-auto-update-trigger gdbmi-invalidate-frames
-  (gdb-get-buffer 'gdb-stack-buffer)
-  "-stack-list-frames\n"
-  gdb-stack-list-frames-handler)
-
-(defconst gdb-stack-list-frames-regexp
-"{.*?level=\"\\(.*?\\)\",.*?addr=\"\\(.*?\\)\",.*?func=\"\\(.*?\\)\",\
-\\(?:.*?file=\".*?\",.*?fullname=\"\\(.*?\\)\",.*?line=\"\\(.*?\\)\".*?}\\|\
-from=\"\\(.*?\\)\"\\)")
-
-(defun gdb-stack-list-frames-handler ()
-  (setq gdb-pending-triggers (delq 'gdbmi-invalidate-frames
-                                 gdb-pending-triggers))
-  (let ((frame nil)
-       (call-stack nil))
-    (with-current-buffer (gdb-get-buffer-create 'gdb-partial-output-buffer)
-      (goto-char (point-min))
-      (while (re-search-forward gdb-stack-list-frames-regexp nil t)
-       (let ((frame (list (match-string 1)
-                          (match-string 2)
-                          (match-string 3)
-                          (match-string 4)
-                          (match-string 5)
-                          (match-string 6))))
-         (push frame call-stack))))
-    (let ((buf (gdb-get-buffer 'gdb-stack-buffer)))
-      (and buf (with-current-buffer buf
-                (let ((p (point))
-                      (buffer-read-only nil))
-                  (erase-buffer)
-                  (insert "Level\tAddr\tFunc\tFile:Line\n")
-                  (dolist (frame (nreverse call-stack))
-                    (insert
-                     (concat
-                      (nth 0 frame) "\t"
-                      (nth 1 frame) "\t"
-                      (propertize (nth 2 frame)
-                                  'face font-lock-function-name-face) "\t"
-                      (if (nth 3 frame)
-                          (concat "at "(nth 3 frame) ":" (nth 4 frame) "\n")
-                        (concat "from " (nth 5 frame) "\n")))))
-                  (goto-char p))))))
-  (gdb-stack-list-frames-custom))
-
-(defun gdb-stack-list-frames-custom ()
-  (with-current-buffer (gdb-get-buffer 'gdb-stack-buffer)
-    (save-excursion
-      (let ((buffer-read-only nil))
-       (goto-char (point-min))
-       (forward-line 1)
-       (while (< (point) (point-max))
-         (add-text-properties (point-at-bol) (point-at-eol)
-                            '(mouse-face highlight
-                              help-echo "mouse-2, RET: Select frame"))
-         (beginning-of-line)
-         (when (and (looking-at "^[0-9]+\\s-+\\(\\S-+\\)")
-                    (equal (match-string 1) gdb-selected-frame))
-           (put-text-property (point-at-bol) (point-at-eol)
-                              'face '(:inverse-video t)))
-         (forward-line 1))))))
-
-\f
-;; gdb-ui.el uses "info source" to find out if macro information is present.
-(defun gdb-get-source-file ()
-  "Find the source file where the program starts and display it with related
-buffers, if required."
-  (goto-char (point-min))
-  (if (re-search-forward gdb-source-file-regexp-1 nil t)
-      (setq gdb-main-file (match-string 1)))
- (if gdb-many-windows
-      (gdb-setup-windows)
-   (gdb-get-buffer-create 'gdb-breakpoints-buffer)
-   (if gdb-show-main
-       (let ((pop-up-windows t))
-        (display-buffer (gud-find-file gdb-main-file))))))
-
-(defun gdbmi-get-selected-frame ()
-  (if (not (member 'gdbmi-get-selected-frame gdb-pending-triggers))
-      (progn
-       (gdb-enqueue-input
-        (list "-stack-info-frame\n" 'gdbmi-frame-handler))
-       (push 'gdbmi-get-selected-frame
-              gdb-pending-triggers))))
-
-(defun gdbmi-frame-handler ()
-  (setq gdb-pending-triggers
-       (delq 'gdbmi-get-selected-frame gdb-pending-triggers))
-  (with-current-buffer (gdb-get-buffer-create 'gdb-partial-output-buffer)
-    (goto-char (point-min))
-    (when (re-search-forward gdb-stack-list-frames-regexp nil t)
-      (setq gdb-frame-number (match-string 1))
-      (setq gdb-pc-address (match-string 2))
-      (setq gdb-selected-frame (match-string 3))
-      (when (match-string 4)
-       (setq gud-last-frame
-             (cons (match-string 4) (string-to-number (match-string 5))))
-       (gud-display-frame)
-       (if gud-overlay-arrow-position
-           (let ((buffer (marker-buffer gud-overlay-arrow-position))
-                 (position (marker-position gud-overlay-arrow-position)))
-             (when buffer
-               (with-current-buffer buffer
-                 (setq fringe-indicator-alist
-                       (if (string-equal gdb-frame-number "0")
-                           nil
-                         '((overlay-arrow . hollow-right-triangle))))
-                 (setq gud-overlay-arrow-position (make-marker))
-                 (set-marker gud-overlay-arrow-position position))))))
-      (if (gdb-get-buffer 'gdb-locals-buffer)
-         (with-current-buffer (gdb-get-buffer 'gdb-locals-buffer)
-           (setq mode-name (concat "Locals:" gdb-selected-frame))))
-      (if (gdb-get-buffer 'gdb-assembler-buffer)
-         (with-current-buffer (gdb-get-buffer 'gdb-assembler-buffer)
-           (setq mode-name (concat "Machine:" gdb-selected-frame)))))))
-
-(defvar gdb-prompt-name-regexp "value=\"\\(.*?\\)\"")
-
-(defun gdb-get-prompt ()
-  "Find prompt for GDB session."
-  (goto-char (point-min))
-  (setq gdb-prompt-name nil)
-  (re-search-forward gdb-prompt-name-regexp nil t)
-  (setq gdb-prompt-name (match-string 1)))
-              
-(provide 'gdb-mi)
-;;; gdbmi.el ends here

diff --git a/gdb/mi/mi-cmd-stack.c b/gdb/mi/mi-cmd-stack.c
index dd06269..3dad54f 100644 (file)
--- a/gdb/mi/mi-cmd-stack.c
+++ b/gdb/mi/mi-cmd-stack.c
@@ -32,7 +32,11 @@
 #include "language.h"
 #include "valprint.h"
 
-static void list_args_or_locals (int locals, int values, struct frame_info *fi);
+
+enum what_to_list { locals, arguments, all };
+
+static void list_args_or_locals (enum what_to_list what, 
+                                int values, struct frame_info *fi);
 
 /* Print a list of the stack frames. Args can be none, in which case
    we want to print the whole backtrace, or a pair of numbers
@@ -148,7 +152,7 @@ mi_cmd_stack_list_locals (char *command, char **argv, int argc)
 
    frame = get_selected_frame (NULL);
 
-   list_args_or_locals (1, parse_print_values (argv[0]), frame);
+   list_args_or_locals (locals, parse_print_values (argv[0]), frame);
 }
 
 /* Print a list of the arguments for the current frame. With argument
@@ -204,19 +208,37 @@ mi_cmd_stack_list_args (char *command, char **argv, int argc)
       QUIT;
       cleanup_frame = make_cleanup_ui_out_tuple_begin_end (uiout, "frame");
       ui_out_field_int (uiout, "level", i);
-      list_args_or_locals (0, print_values, fi);
+      list_args_or_locals (arguments, print_values, fi);
       do_cleanups (cleanup_frame);
     }
 
   do_cleanups (cleanup_stack_args);
 }
 
+/* Print a list of the local variables (including arguments) for the 
+   current frame. With argument of 0, print only the names, with 
+   argument of 1 print also the values. */
+void
+mi_cmd_stack_list_variables (char *command, char **argv, int argc)
+{
+  struct frame_info *frame;
+  enum print_values print_values;
+
+  if (argc != 1)
+    error (_("Usage: PRINT_VALUES"));
+
+   frame = get_selected_frame (NULL);
+
+   list_args_or_locals (all, parse_print_values (argv[0]), frame);
+}
+
+
 /* Print a list of the locals or the arguments for the currently
    selected frame.  If the argument passed is 0, printonly the names
    of the variables, if an argument of 1 is passed, print the values
    as well. */
 static void
-list_args_or_locals (int locals, int values, struct frame_info *fi)
+list_args_or_locals (enum what_to_list what, int values, struct frame_info *fi)
 {
   struct block *block;
   struct symbol *sym;
@@ -225,12 +247,25 @@ list_args_or_locals (int locals, int values, struct frame_info *fi)
   struct cleanup *cleanup_list;
   static struct ui_stream *stb = NULL;
   struct type *type;
+  char *name_of_result;
 
   stb = ui_out_stream_new (uiout);
 
   block = get_frame_block (fi, 0);
 
-  cleanup_list = make_cleanup_ui_out_list_begin_end (uiout, locals ? "locals" : "args");
+  switch (what)
+    {
+    case locals:
+      name_of_result = "locals"; break;
+    case arguments:
+      name_of_result = "args"; break;
+    case all:
+      name_of_result = "variables"; break;
+    default:
+      gdb_assert (("unexpected value", 0));
+    }
+
+  cleanup_list = make_cleanup_ui_out_list_begin_end (uiout, name_of_result);
 
   while (block != 0)
     {
@@ -259,8 +294,12 @@ list_args_or_locals (int locals, int values, struct frame_info *fi)
            case LOC_STATIC:    /* static                */
            case LOC_REGISTER:  /* register              */
            case LOC_COMPUTED:  /* computed location     */
-             if (SYMBOL_IS_ARGUMENT (sym) ? !locals : locals)
+             if (what == all)
                print_me = 1;
+             else if (what == locals)
+               print_me = !SYMBOL_IS_ARGUMENT (sym);
+             else
+               print_me = SYMBOL_IS_ARGUMENT (sym);
              break;
            }
          if (print_me)
@@ -273,7 +312,7 @@ list_args_or_locals (int locals, int values, struct frame_info *fi)
                  make_cleanup_ui_out_tuple_begin_end (uiout, NULL);
              ui_out_field_string (uiout, "name", SYMBOL_PRINT_NAME (sym));
 
-             if (!locals)
+             if (SYMBOL_IS_ARGUMENT (sym))
                sym2 = lookup_symbol (SYMBOL_NATURAL_NAME (sym),
                                      block, VAR_DOMAIN,
                                      (int *) NULL);

diff --git a/gdb/mi/mi-cmds.c b/gdb/mi/mi-cmds.c
index 8ba086c..2c425b7 100644 (file)
--- a/gdb/mi/mi-cmds.c
+++ b/gdb/mi/mi-cmds.c
@@ -89,6 +89,7 @@ struct mi_cmd mi_cmds[] =
   { "stack-list-arguments", { NULL, 0 }, mi_cmd_stack_list_args},
   { "stack-list-frames", { NULL, 0 }, mi_cmd_stack_list_frames},
   { "stack-list-locals", { NULL, 0 }, mi_cmd_stack_list_locals},
+  { "stack-list-variables", { NULL, 0 }, mi_cmd_stack_list_variables},
   { "stack-select-frame", { NULL, 0 }, mi_cmd_stack_select_frame},
   { "symbol-list-lines", { NULL, 0 }, mi_cmd_symbol_list_lines},
   { "target-attach", { "attach", 1 }, NULL },

diff --git a/gdb/mi/mi-cmds.h b/gdb/mi/mi-cmds.h
index dfab411..491c1f2 100644 (file)
--- a/gdb/mi/mi-cmds.h
+++ b/gdb/mi/mi-cmds.h
@@ -75,6 +75,7 @@ extern mi_cmd_argv_ftype mi_cmd_stack_info_frame;
 extern mi_cmd_argv_ftype mi_cmd_stack_list_args;
 extern mi_cmd_argv_ftype mi_cmd_stack_list_frames;
 extern mi_cmd_argv_ftype mi_cmd_stack_list_locals;
+extern mi_cmd_argv_ftype mi_cmd_stack_list_variables;
 extern mi_cmd_argv_ftype mi_cmd_stack_select_frame;
 extern mi_cmd_argv_ftype mi_cmd_symbol_list_lines;
 extern mi_cmd_argv_ftype mi_cmd_target_detach;

diff --git a/gdb/objc-lang.c b/gdb/objc-lang.c
index 0e4fb71..f3a8b73 100644 (file)
--- a/gdb/objc-lang.c
+++ b/gdb/objc-lang.c
@@ -1173,16 +1173,18 @@ find_methods (struct symtab *symtab, char type,
 
       ALL_OBJFILE_MSYMBOLS (objfile, msymbol)
        {
+         struct gdbarch *gdbarch = get_objfile_arch (objfile);
+         CORE_ADDR pc = SYMBOL_VALUE_ADDRESS (msymbol);
+
          QUIT;
 
-         if ((MSYMBOL_TYPE (msymbol) != mst_text)
-             && (MSYMBOL_TYPE (msymbol) != mst_file_text))
-           /* Not a function or method.  */
-           continue;
+         /* The minimal symbol might point to a function descriptor;
+            resolve it to the actual code address instead.  */
+         pc = gdbarch_convert_from_func_ptr_addr (gdbarch, pc,
+                                                  &current_target);
 
          if (symtab)
-           if ((SYMBOL_VALUE_ADDRESS (msymbol) <  BLOCK_START (block)) ||
-               (SYMBOL_VALUE_ADDRESS (msymbol) >= BLOCK_END (block)))
+           if (pc < BLOCK_START (block) || pc >= BLOCK_END (block))
              /* Not in the specified symtab.  */
              continue;
 
@@ -1221,7 +1223,7 @@ find_methods (struct symtab *symtab, char type,
              ((nselector == NULL) || (strcmp (selector, nselector) != 0)))
            continue;
 
-         sym = find_pc_function (SYMBOL_VALUE_ADDRESS (msymbol));
+         sym = find_pc_function (pc);
          if (sym != NULL)
            {
              const char *newsymname = SYMBOL_NATURAL_NAME (sym);

diff --git a/gdb/ppc-sysv-tdep.c b/gdb/ppc-sysv-tdep.c
index 703ca4d..031ec52 100644 (file)
--- a/gdb/ppc-sysv-tdep.c
+++ b/gdb/ppc-sysv-tdep.c
@@ -1326,10 +1326,14 @@ ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
   regcache_cooked_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
 
   /* Use the func_addr to find the descriptor, and use that to find
-     the TOC.  */
+     the TOC.  If we're calling via a function pointer, the pointer
+     itself identifies the descriptor.  */
   {
-    CORE_ADDR desc_addr;
-    if (convert_code_addr_to_desc_addr (func_addr, &desc_addr))
+    struct type *ftype = check_typedef (value_type (function));
+    CORE_ADDR desc_addr = value_as_address (function);
+
+    if (TYPE_CODE (ftype) == TYPE_CODE_PTR
+       || convert_code_addr_to_desc_addr (func_addr, &desc_addr))
       {
        /* The TOC is the second double word in the descriptor.  */
        CORE_ADDR toc =

diff --git a/gdb/python/py-value.c b/gdb/python/py-value.c
index 0146593..fc1b71a 100644 (file)
--- a/gdb/python/py-value.c
+++ b/gdb/python/py-value.c
@@ -238,6 +238,7 @@ valpy_string (PyObject *self, PyObject *args, PyObject *kw)
   const char *errors = NULL;
   const char *user_encoding = NULL;
   const char *la_encoding = NULL;
+  struct type *char_type;
   static char *keywords[] = { "encoding", "errors", "length", NULL };
 
   if (!PyArg_ParseTupleAndKeywords (args, kw, "|ssi", keywords,
@@ -246,12 +247,13 @@ valpy_string (PyObject *self, PyObject *args, PyObject *kw)
 
   TRY_CATCH (except, RETURN_MASK_ALL)
     {
-      LA_GET_STRING (value, &buffer, &length, &la_encoding);
+      LA_GET_STRING (value, &buffer, &length, &char_type, &la_encoding);
     }
   GDB_PY_HANDLE_EXCEPTION (except);
 
   encoding = (user_encoding && *user_encoding) ? user_encoding : la_encoding;
-  unicode = PyUnicode_Decode (buffer, length, encoding, errors);
+  unicode = PyUnicode_Decode (buffer, length * TYPE_LENGTH (char_type),
+                             encoding, errors);
   xfree (buffer);
 
   return unicode;

diff --git a/gdb/record.c b/gdb/record.c
index f71f3ff..8b56010 100644 (file)
--- a/gdb/record.c
+++ b/gdb/record.c
@@ -496,8 +496,8 @@ record_open (char *name, int from_tty)
 
   /* Check if record target is already running.  */
   if (current_target.to_stratum == record_stratum)
-     error (_("Process record target already running.  Use \"record stop\" to "
-            "stop record target first."));
+    error (_("Process record target already running.  Use \"record stop\" to "
+             "stop record target first."));
 
   /*Reset the beneath function pointers.  */
   record_beneath_to_resume = NULL;

diff --git a/gdb/score-tdep.c b/gdb/score-tdep.c
index 47da1c8..ccbcc3a 100644 (file)
--- a/gdb/score-tdep.c
+++ b/gdb/score-tdep.c
@@ -56,7 +56,7 @@ struct score_frame_cache
 
 static int target_mach = bfd_mach_score7;
 
-#if WITH_SIM
+#if 0
 int
 score_target_can_use_watch (int type, int cnt, int othertype)
 {

diff --git a/gdb/score-tdep.h b/gdb/score-tdep.h
index 792f277..2434722 100644 (file)
--- a/gdb/score-tdep.h
+++ b/gdb/score-tdep.h
@@ -85,68 +85,4 @@ struct pt_regs {
 
 typedef struct pt_regs elf_gregset_t;
 
-#ifdef WITH_SIM
-
-#include <breakpoint.h>
-
-int soc_gh_can_use_watch(int type, int cnt);
-int soc_gh_add_watch(unsigned int addr, int len, int type);
-int soc_gh_del_watch(unsigned int addr, int len, int type);
-int soc_gh_stopped_by_watch(void);
-int soc_gh_add_hardbp(unsigned int addr); 
-int soc_gh_del_hardbp(unsigned int addr); 
-
-int score_target_can_use_watch(int type, int cnt, int ot);
-int score_stopped_by_watch(void);
-int score_target_insert_watchpoint (CORE_ADDR addr, int len, int type);
-int score_target_remove_watchpoint (CORE_ADDR addr, int len, int type);
-int score_target_insert_hw_breakpoint (struct gdbarch *gdbarch, struct bp_target_info * bp_tgt);
-int score_target_remove_hw_breakpoint (struct gdbarch *gdbarch, struct bp_target_info * bp_tgt);
-
-#define TARGET_HAS_HARDWARE_WATCHPOINTS
-
-#ifdef TARGET_CAN_USE_HARDWARE_WATCHPOINT
-#undef TARGET_CAN_USE_HARDWARE_WATCHPOINT
-
-#define TARGET_CAN_USE_HARDWARE_WATCHPOINT(type, cnt, ot) \
-    score_target_can_use_watch(type, cnt, ot)
-#endif
-
-#ifdef STOPPED_BY_WATCHPOINT
-#undef STOPPED_BY_WATCHPOINT
-
-#define STOPPED_BY_WATCHPOINT(w) \
-    score_stopped_by_watch()
-#endif
-
-#ifdef target_insert_watchpoint
-#undef target_insert_watchpoint
-
-#define target_insert_watchpoint(addr, len, type) \
-    score_target_insert_watchpoint (addr, len, type)
-#endif
-
-#ifdef target_remove_watchpoint
-#undef target_remove_watchpoint
-
-#define target_remove_watchpoint(addr, len, type) \
-    score_target_remove_watchpoint (addr, len, type)
-#endif
-
-#ifdef target_insert_hw_breakpoint
-#undef target_insert_hw_breakpoint
-
-#define target_insert_hw_breakpoint(gdbarch, bp_tgt) \
-    score_target_insert_hw_breakpoint (gdbarch, bp_tgt)
-#endif
-
-#ifdef target_remove_hw_breakpoint
-#undef target_remove_hw_breakpoint
-
-#define target_remove_hw_breakpoint(gdbarch, bp_tgt) \
-    score_target_remove_hw_breakpoint (gdbarch, bp_tgt)
-#endif
-
-#endif /* WITH_SIM */
-
 #endif /* SCORE_TDEP_H */

diff --git a/gdb/testsuite/gdb.base/charset.c b/gdb/testsuite/gdb.base/charset.c
index b61e047..5f07c9e 100644 (file)
--- a/gdb/testsuite/gdb.base/charset.c
+++ b/gdb/testsuite/gdb.base/charset.c
@@ -50,10 +50,10 @@ char ebcdic_us_string[NUM_CHARS];
 char ibm1047_string[NUM_CHARS];
 
 /* We make a phony wchar_t and then pretend that this platform uses
-   UCS-4 (or UCS-2, depending on the size -- same difference for the
+   UTF-32 (or UTF-16, depending on the size -- same difference for the
    purposes of this test).  */
 typedef unsigned int wchar_t;
-wchar_t ucs_4_string[NUM_CHARS];
+wchar_t utf_32_string[NUM_CHARS];
 
 /* We also define a couple phony types for testing the u'' and U''
    support.  It is ok if these have the wrong size on some platforms
@@ -103,12 +103,12 @@ fill_run (char string[], int start, int len, int first)
 
 
 void
-init_ucs4 ()
+init_utf32 ()
 {
   int i;
 
   for (i = 0; i < NUM_CHARS; ++i)
-    ucs_4_string[i] = iso_8859_1_string[i] & 0xff;
+    utf_32_string[i] = iso_8859_1_string[i] & 0xff;
 }
 
 int main ()
@@ -171,9 +171,9 @@ int main ()
   /* The digits, at least, are contiguous.  */
   fill_run (ibm1047_string, 59, 10, 240);
 
-  init_ucs4 ();
+  init_utf32 ();
 
-  myvar = ucs_4_string[7];
+  myvar = utf_32_string[7];
 
   return 0;            /* all strings initialized */
 }

diff --git a/gdb/testsuite/gdb.base/charset.exp b/gdb/testsuite/gdb.base/charset.exp
index fe1fbb0..8ef217a 100644 (file)
--- a/gdb/testsuite/gdb.base/charset.exp
+++ b/gdb/testsuite/gdb.base/charset.exp
@@ -375,10 +375,10 @@ gdb_expect {
 set wchar_size [get_sizeof wchar_t 99]
 set wchar_ok 0
 if {$wchar_size == 2} {
-    lappend charset_subset UCS-2
+    lappend charset_subset UTF-16
     set wchar_ok 1
 } elseif {$wchar_size == 4} {
-    lappend charset_subset UCS-4
+    lappend charset_subset UTF-32
     set wchar_ok 1
 }
 
@@ -388,7 +388,7 @@ foreach target_charset $charset_subset {
        continue
     }
 
-    if {$target_charset == "UCS-4" || $target_charset == "UCS-2"} {
+    if {$target_charset == "UTF-32" || $target_charset == "UTF-16"} {
        set param target-wide-charset
        set L L
     } else {
@@ -424,10 +424,10 @@ foreach target_charset $charset_subset {
     # a string in $target_charset.  The variable's name is the
     # character set's name, in lower-case, with all non-identifier
     # characters replaced with '_', with "_string" stuck on the end.
-    if {$target_charset == "UCS-2"} {
-       # We still use the ucs_4_string variable -- but the size is
-       # correct for UCS-2.
-       set var_name ucs_4_string
+    if {$target_charset == "UTF-16"} {
+       # We still use the utf_32_string variable -- but the size is
+       # correct for UTF-16.
+       set var_name utf_32_string
     } else {
        set var_name [string tolower "${target_charset}_string"]
        regsub -all -- "\[^a-z0-9_\]" $var_name "_" var_name
@@ -556,7 +556,7 @@ gdb_test "print '\\9'" " = \[0-9\]+ '9'"
 gdb_test "print \"\\1011\"" " = \"A1\""
 
 # Tests for wide- or unicode- strings.  L is the prefix letter to use,
-# either "L" (for wide strings), "u" (for UCS-2), or "U" (for UCS-4).
+# either "L" (for wide strings), "u" (for UTF-16), or "U" (for UTF-32).
 # NAME is used in the test names and should be related to the prefix
 # letter in some easy-to-undestand way.
 proc test_wide_or_unicode {L name} {
@@ -582,12 +582,12 @@ if {$wchar_ok} {
 
 set ucs2_ok [expr {[get_sizeof char16_t 99] == 2}]
 if {$ucs2_ok} {
-    test_wide_or_unicode u UCS-2
+    test_wide_or_unicode u UTF-16
 }
 
 set ucs4_ok [expr {[get_sizeof char32_t 99] == 4}]
 if {$ucs4_ok} {
-    test_wide_or_unicode U UCS-4
+    test_wide_or_unicode U UTF-32
 }
 
 # Test an invalid string combination.
@@ -598,16 +598,36 @@ proc test_combination {L1 name1 L2 name2} {
 }
 
 if {$wchar_ok && $ucs2_ok} {
-    test_combination L wide u UCS-2
+    test_combination L wide u UTF-16
 }
 if {$wchar_ok && $ucs4_ok} {
-    test_combination L wide U UCS-4
+    test_combination L wide U UTF-32
   # Regression test for a typedef to a typedef.
   gdb_test "print myvar" "= \[0-9\]+ L'A'" \
       "typedef to wchar_t"
 }
 if {$ucs2_ok && $ucs4_ok} {
-    test_combination u UCS-2 U UCS-4
+    test_combination u UTF-16 U UTF-32
+}
+
+if {$ucs2_ok} {
+    set go 1
+    gdb_test_multiple "python print 'hello, world!'" \
+       "verify python support for charset tests" {
+           -re "not supported.*$gdb_prompt $"  {
+               unsupported "python support is disabled"
+               set go 0
+           }
+           -re "$gdb_prompt $" {}
+       }
+
+    if {$go} {
+       gdb_test "print u\"abcdef\"" " = u\"abcdef\"" \
+           "set up for python printing of utf-16 string"
+
+       gdb_test "python print gdb.history(0).string()" "abcdef" \
+           "extract utf-16 string using python"
+    }
 }
 
 # Regression test for a cleanup bug in the charset code.

diff --git a/gdb/testsuite/gdb.base/checkpoint.c b/gdb/testsuite/gdb.base/checkpoint.c
index 4a41268..2d44a74 100644 (file)
--- a/gdb/testsuite/gdb.base/checkpoint.c
+++ b/gdb/testsuite/gdb.base/checkpoint.c
@@ -40,9 +40,9 @@ main()
   for (i = 0; ; i++)
     {
       if (ftell (in) != i)
-       fprintf (stderr, "Input error at %d\n", i);
+       fprintf (stderr, "Input error at %ld\n", i);
       if (ftell (out) != i)
-       fprintf (stderr, "Output error at %d\n", i);
+       fprintf (stderr, "Output error at %ld\n", i);
       c = fgetc (in);
       if (c == '\n')
        lines++;        /* breakpoint 1 */

diff --git a/gdb/testsuite/gdb.base/default.exp b/gdb/testsuite/gdb.base/default.exp
index a223982..a0cb11e 100644 (file)
--- a/gdb/testsuite/gdb.base/default.exp
+++ b/gdb/testsuite/gdb.base/default.exp
@@ -598,7 +598,7 @@ gdb_test "show complaints" "Max number of complaints about incorrect symbols is
 #test show confirm
 gdb_test "show confirm" "Whether to confirm potentially dangerous operations is o\[a-z\]*." "show confirm"
 #test show convenience
-gdb_test "show convenience" "No debugger convenience variables now defined.(\[^\r\n\]*\[\r\n\])+Convenience variables have names starting with \".\";(\[^\r\n\]*\[\r\n\])+use \"set\" as in \"set .foo = 5\" to define them." "show convenience"
+gdb_test "show convenience" "\\\$_siginfo = void" "show convenience"
 #test show directories
 gdb_test "show directories" "Source directories searched: .cdir\[:;\].cwd" "show directories"
 #test show editing

diff --git a/gdb/testsuite/gdb.base/fileio.c b/gdb/testsuite/gdb.base/fileio.c
index 3910da5..329522f 100644 (file)
--- a/gdb/testsuite/gdb.base/fileio.c
+++ b/gdb/testsuite/gdb.base/fileio.c
@@ -231,13 +231,13 @@ test_lseek ()
     }
   else
     {
-      printf ("lseek 1: ret = %d, errno = %d %s\n", ret, errno,
+      printf ("lseek 1: ret = %ld, errno = %d %s\n", (long) ret, errno,
              strerrno (errno));
       stop ();
-      printf ("lseek 2: ret = %d, errno = %d %s\n", ret, errno,
+      printf ("lseek 2: ret = %ld, errno = %d %s\n", (long) ret, errno,
              strerrno (errno));
       stop ();
-      printf ("lseek 3: ret = %d, errno = %d %s\n", ret, errno,
+      printf ("lseek 3: ret = %ld, errno = %d %s\n", (long) ret, errno,
              strerrno (errno));
     }
   /* Seeking on an invalid file descriptor */
@@ -473,7 +473,7 @@ test_unlink ()
                  strerrno (errno));
         }
       else
-       printf ("unlink 2: ret = %d chmod failed\n", ret, errno);
+       printf ("unlink 2: ret = %d chmod failed, errno= %d\n", ret, errno);
     }
   else
     printf ("unlink 2: ret = %d, errno = %d\n", ret, errno);

diff --git a/gdb/testsuite/gdb.base/shr1.c b/gdb/testsuite/gdb.base/shr1.c
index a0257e4..117119a 100644 (file)
--- a/gdb/testsuite/gdb.base/shr1.c
+++ b/gdb/testsuite/gdb.base/shr1.c
@@ -25,7 +25,7 @@ int x;
   sg = 6.6;
   sgi++;
   sgs = 8;
-  printf("address of sgs is 0x%x\n", &sgs);
+  printf("address of sgs is %p\n", &sgs);
   return 2*x;
 }
 

diff --git a/gdb/testsuite/gdb.base/unload.c b/gdb/testsuite/gdb.base/unload.c
index a470849..b8434cd 100644 (file)
--- a/gdb/testsuite/gdb.base/unload.c
+++ b/gdb/testsuite/gdb.base/unload.c
@@ -27,7 +27,6 @@
 # define dlsym(handle, func) GetProcAddress (handle, func)
 #endif
 #define dlclose(handle) FreeLibrary (handle)
-#define dlerror() "error %d occurred", GetLastError ()
 #else
 #include <dlfcn.h>
 #endif
@@ -53,7 +52,11 @@ int main()
 
   if (!unloadshr)
     {
-      fprintf (stderr, dlerror ());
+#ifdef __WIN32__
+      fprintf (stderr, "error %d occurred", GetLastError ());
+#else
+      fprintf (stderr, "%s", dlerror ());
+#endif
       exit (1);
     }
 

diff --git a/gdb/testsuite/gdb.base/watchpoint-solib.c b/gdb/testsuite/gdb.base/watchpoint-solib.c
index 86fc253..96cc4dc 100644 (file)
--- a/gdb/testsuite/gdb.base/watchpoint-solib.c
+++ b/gdb/testsuite/gdb.base/watchpoint-solib.c
@@ -27,7 +27,6 @@
 # define dlsym(handle, func) GetProcAddress (handle, func)
 #endif
 #define dlclose(handle) FreeLibrary (handle)
-#define dlerror() "error %d occurred", GetLastError ()
 #else
 #include <dlfcn.h>
 #endif
@@ -42,7 +41,11 @@ void open_shlib ()
   
   if (!handle)
     {
-      fprintf (stderr, dlerror ());
+#ifdef __WIN32__
+      fprintf (stderr, "error %d occurred", GetLastError ());
+#else
+      fprintf (stderr, "%s", dlerror ());
+#endif
       exit (1);
     }
 

diff --git a/gdb/testsuite/gdb.cp/classes.cc b/gdb/testsuite/gdb.cp/classes.cc
index 927aad3..913627f 100644 (file)
--- a/gdb/testsuite/gdb.cp/classes.cc
+++ b/gdb/testsuite/gdb.cp/classes.cc
@@ -400,8 +400,11 @@ class Base1 {
  public:
   int x;
   Base1(int i) { x = i; }
+  ~Base1 () { }
 };
 
+typedef Base1 base1;
+
 class Foo
 {
  public:
@@ -564,6 +567,8 @@ void use_methods ()
   i = class_param.Aref_x (g_A);
   i = class_param.Aval_a (g_A);
   i = class_param.Aval_x (g_A);
+
+  base1 b (3);
 }
 
 

diff --git a/gdb/testsuite/gdb.cp/classes.exp b/gdb/testsuite/gdb.cp/classes.exp
index bd980b2..87e993c 100644 (file)
--- a/gdb/testsuite/gdb.cp/classes.exp
+++ b/gdb/testsuite/gdb.cp/classes.exp
@@ -632,6 +632,10 @@ proc do_tests {} {
            fail "calling method for small class"
        }
     }
+
+    gdb_test "print base1::Base1" "<.*Base1.*>" "print ctor of typedef class"
+    gdb_test "print base1::~Base1" "<.*~Base1(\\(\\))?>" \
+       "print dtor of typedef class"
 }
 
 do_tests

diff --git a/gdb/testsuite/gdb.cp/cplusfuncs.exp b/gdb/testsuite/gdb.cp/cplusfuncs.exp
index 5e08768..56702ed 100644 (file)
--- a/gdb/testsuite/gdb.cp/cplusfuncs.exp
+++ b/gdb/testsuite/gdb.cp/cplusfuncs.exp
@@ -534,6 +534,7 @@ proc do_tests {} {
     global srcdir
     global binfile
     global gdb_prompt
+    global dm_type_int_star
 
     set prms_id 0
     set bug_id 0
@@ -557,6 +558,10 @@ proc do_tests {} {
     test_paddr_operator_functions
     test_paddr_hairy_functions
     test_lookup_operator_functions
+
+    # A regression test on errors involving operators
+    gdb_test "list foo::operator $dm_type_int_star" \
+       ".*the class foo does not have any method named operator $dm_type_int_star.*"
 }
 
 do_tests

diff --git a/gdb/testsuite/gdb.cp/templates.cc b/gdb/testsuite/gdb.cp/templates.cc
index a04d768..dfb6f8e 100644 (file)
--- a/gdb/testsuite/gdb.cp/templates.cc
+++ b/gdb/testsuite/gdb.cp/templates.cc
@@ -630,6 +630,7 @@ T Spec<T, T*>::spec (T * tp)
 template<class T, char sz>
 class Baz {
 public:
+  ~Baz () { };
   int x;
   T t;
   T baz (int, T);
@@ -643,6 +644,8 @@ template<class T, char sz> T Baz<T, sz>::baz (int i, T tt)
     return 0;
 }
 
+typedef Baz<int, 1> intBazOne;
+
 // Template with char * parameter
 template<class T, char * sz>
 class Qux {
@@ -777,6 +780,8 @@ int main()
   i=GetMax<int>(x,y);
   n=GetMax<long>(l,m);
 
+  intBazOne ibo;
+  z = ibo.baz (2, 21);
   return 0;
     
 }

diff --git a/gdb/testsuite/gdb.cp/templates.exp b/gdb/testsuite/gdb.cp/templates.exp
index 541bdcb..487186a 100644 (file)
--- a/gdb/testsuite/gdb.cp/templates.exp
+++ b/gdb/testsuite/gdb.cp/templates.exp
@@ -195,6 +195,14 @@ proc test_template_calls {} {
     }
 }
 
+proc test_template_typedef {} {
+
+    gdb_test "print intBazOne::baz" ".*baz\\(int, int\\)>" \
+       "print method of template typedef"
+
+    gdb_test "print intBazOne::~Baz" ".*~Baz(\\(\\))?>" \
+       "print destructor of template typedef"
+}
 
 proc do_tests {} {
     global prms_id
@@ -223,6 +231,7 @@ proc do_tests {} {
 
     test_ptype_of_templates
     test_template_breakpoints
+    test_template_typedef
 
     if [ runto_main] {
        test_template_calls

diff --git a/gdb/testsuite/gdb.gdbtk/ChangeLog b/gdb/testsuite/gdb.gdbtk/ChangeLog
deleted file mode 100644 (file)
index 446e5f3..0000000
--- a/gdb/testsuite/gdb.gdbtk/ChangeLog
+++ /dev/null
@@ -1,358 +0,0 @@
-2008-09-19  Denis Pilat  <denis.pilat@st.com>
-
-       * insight-support.exp (gdbtk_start): test TCL_LIBRARY env. variable
-       before being unset.
-
-2008-03-28  Maciej W. Rozycki  <macro@mips.com>
-
-       * README: Fix a few typos throughout.
-
-2008-02-20  Keith Seitz  <keiths@redhat.com>
-
-       * stack1.c: Include stdlib.h
-       * simple.c: Likewise.
-       Include string.h.
-
-2007-06-27  Maciej W. Rozycki  <macro@mips.com>
-
-       * c_variable.c: Include <stdlib.h> for a declaration of exit().
-
-2007-02-08  Andreas Schwab  <schwab@suse.de>
-
-       * insight-support.exp (gdbtk_start): Return error status instead
-       of aborting the whole testsuite run.
-
-2006-09-19  Keith Seitz  <keiths@redhat.com>
-
-       * Makefile.in: Change all instances of configure.in to refer to
-       configure.ac.
-
-2005-01-27  Keith Seitz  <keiths@redhat.com>
-
-       * configure.in: Rename to ...
-       * configure.ac: ... this.
-       * configure: Regnerate.
-
-2004-07-19  Martin Hunt  <hunt@redhat.com>
-
-       * All: Updated load_lib calls to find new location
-       of insight-support.exp.
-
-2004-07-16  Andrew Cagney  <cagney@redhat.com>
-
-       * insight-support.exp: Moved to here from ../lib.
-
-2003-02-28  Martin M. Hunt  <hunt@redhat.com>
-
-       * c_variable.test: Fix result for 6.22.
-
-2003-02-27  Martin M. Hunt  <hunt@redhat.com>
-
-       * cpp_variable.test: Major changes required because varobj_update
-       now returns "-1" if a variable is out of scope.
-
-       * c_variable.test: Major changes required because varobj_update
-       now returns "-1" if a variable is out of scope. This fixes a bunch 
-       of XFAILS. Change bug reporting address.
-       
-       * windows.test: Remove HtmlViewer from list of windows.
-
-       * srcwin.test: Use "list get" instead of "listget" to
-       get contents of comboboxes. 
-       (2.1): Be less sensitive. 
-
-       * srcwin2.test: Use "list get" instead of "listget" to
-       get contents of comboboxes
-       (2-1.3): Accept assembly == mixed
-       for no source tests.
-
-       * srcwin3.test:  Use "list get" instead of "listget" to
-       get contents of comboboxes
-
-2002-09-09  Fred Fish  <fnf@intrinsity.com>
-
-       * simple.c:  Pass addresses to strncpy, not chars.
-
-2002-04-26  Martin M. Hunt  <hunt@redhat.com>
-
-       * defs (gdbtk_test_done): Call gdbtk_force_quit. 
-
-2002-04-26  Martin M. Hunt  <hunt@redhat.com>
-
-       * srcwin.test (click): Take a button number as an arg.
-       Generate a ButtonPress event then a ButtonRelease event
-       for that button number.
-       (4.4): Fix args for click().
-       (5.1): Fix results again.
-
-2002-03-07  Martin M. Hunt  <hunt@redhat.com>
-
-       * srcwin.test (5.1): Adjust line numbers to
-       test now runs correctly.
-
-2002-01-18  Keith Seitz  <keiths@redhat.com>
-
-       * console.test: Don't rely on "event generate" to do
-       keystrokes. It just doesn't work. Use the console window's
-       "test" method instead.
-       Use Console::test instead of Console::get_text.
-
-2002-01-15  Keith Seitz  <keiths@redhat.com>
-
-       * c_variable.test (1.4,2.14): Remove test for local frame
-       variables. Varobj now forces evaluation in the current frame
-       by default.
-       (2.15): Ignore any changes and only check for out of scope
-       locals (which is still unsupported).
-       * cpp_variable.test (1.1): Support alternative names for
-       local scope.
-       (1.6a): Catch call to gdb_cmd to prevent an error from
-       throwing testsuite into la-la land. Add to test.
-       (1.7): Ignore results from children during step, since
-       they may or may not change value when the parent changes.
-       (2.2a): New test incorperating gdb_cmd (also wrapped in
-       catch).
-       (2.22a): Likewise.
-       (2.71a): Likewise.
-
-2001-12-20  Keith Seitz  <keiths@redhat.com>
-
-       * cpp_variable.test: Catch non-test calls in case we
-       could not run.
-
-2001-10-25  Keith Seitz  <keiths@redhat.com>
-
-       * defs (_report_error): Fix typo.
-       (show_warning): Redefine the standard warning handler
-       so that we don't end up stalling tests with a warning dialog.
-
-       * windows.exp: New file.
-       * windows.test: New file.
-
-2001-10-08  Keith Seitz  <keiths@redhat.com>
-
-       * c_variable.test (check_update): Forget about returning
-       the "unchanged" list. It unneccessarily complicates things.
-       Update all callers.
-       * cpp_variable.test: Likewise.
-
-2001-08-30  Keith Seitz  <keiths@redhat.com>
-
-       * README: Update documentation to reflect recent changes.
-       * browser.exp: Load the insight testsuite support library.
-       * c_variable.exp: Likewise.
-       * console.exp: Likewise.
-       * cpp_variable.exp: Likewise.
-       * srcwin.exp: Likewise.
-
-2001-08-16  Keith Seitz  <keiths@redhat.com>
-
-       * cpp_variable.test (2.29, 2.30, 2.43, 2.63, 2.72): Char
-       pointers can now be dereferenced. Update test to reflect
-       this change in varobj.
-       * c_variable.test (4.9, 4.10, 4.47, 4.48, 5.1, 5.2, 5.3,
-       5.4, 5.5, 5.6, 5.7, 5.8, 5.9, 5.17, 5.18, 5.43, 5.44, 5.47,
-       5.48, 5.49, 5.50, 5.51, 5.53, 6.30): Likewise.
-
-2001-08-13  Jeff Holcomb  <jeffh@redhat.com>
-
-       * cpp_variable.test: Use gdbtk_test_run to start the test
-       program.
-
-2001-05-07  Keith Seitz  <keiths@cygnus.com>
-
-       * README: New file.
-
-        * configure.in: Check for executable filename extension.
-       * Makefile.in: Add filename extensions.
-        * configure: Regenerated.
-
-        * defs: Fix typo setting _test(verbose).
-        (gdbtk_test_file): New proc to load executables into gdbtk.
-        (gdbtk_test_run): New proc to run executables on gdbtk.
-        * browser.exp: Don't check if DISPLAY is set: let
-        gdbtk_initialize_display do it all for us.
-        Call gdbtk_done when finished with tests.
-        * c_variable.exp: Ditto.
-        * console.exp: Ditto.
-        * cpp_variable.exp: Ditto.
-        Only run tests if c++ is supported in the configuration.
-        * srcwin.exp: Ditto the DISPLAY stuff.
-        Accumulate all test results for the end and report them then.
-
-        * browser.test: Use gdbtk_test_file and gdbtk_test_run
-        to load and run an executable.
-        * c_variable.test: Use gdbtk_test_file and gdbtk_test_run
-        to load and run an executable.
-        * srcwin.test: Ditto.
-        * srcwin1.test: Ditto.
-        * srcwin2.test: Ditto.
-
-        * browser.test: (set_search_mode): Use "configure
-        -value" not "entryset" to set the combobox's value. We need
-        to have the command fired.
-        (browser-3.5): Remove trailing whitespace which causes test to
-        fail.
-        (browser-4.4): Expect something rational. Regexp "\_1$" cannot
-        match "func_10"!
-        (browser-4.5): Ditto.
-        (browser-5.12): Select all files for search to make test
-        match description.
-        (browser-6.2): Renamed from another test also calledd 6.1.
-        (browser-7.1): Delete all breakpoints at once without from_tty.
-        Select all entries in the comobox before invoking BP set/delete
-        button.
-        (browser-7.2): Ditto.
-
-        * list0.c, list1.c, list0.h: New files. Grabbed from gdb.base.
-        * srcwin.exp: Use these local files instead of those in gdb.base.
-
-1999-09-17  Fernando Nasser  <fnasser@totem.to.cygnus.com>
-
-       * cpp_variable.test: Add test (2.75) to verify
-       that a baseclass member value was effectively changed.
-
-1999-09-17  Fernando Nasser  <fnasser@totem.to.cygnus.com>
-
-       * cpp_variable.test: Update for new variable
-       code.
-
-1999-09-17  Fernando Nasser  <fnasser@totem.to.cygnus.com>
-
-       * c_variable.test: Update for new variable code.
-
-1999-09-17  Fernando Nasser  <fnasser@totem.to.cygnus.com>
-
-       * cpp_variable.h (class V): Add type to virtual function
-       declaration.
-
-1999-06-08  Fernando Nasser  <fnasser@totem.to.cygnus.com>
-
-       * browser.exp: Use untested and not warning when DISPLAY is
-       not found.
-       * c_variable.exp: Same.
-       * console.exp: Same.
-       * cpp_variable.exp: Same.
-       * srcwin.exp: Same.
-
-1999-04-12  Keith Seitz  <keiths@cygnus.com>
-
-       * cpp_variable.exp: Pass the "c++" flag to gdb_compile so
-       that it can grab the right compiler.
-
-1999-03-16  Martin Hunt  <hunt@cygnus.com>
-
-       * srcwin.test (srcwin-4.5): Change variable name
-       to $b so test will run again.
-
-1999-03-03  James Ingham  <jingham@cygnus.com>
-
-       * browser.test: Fixed up to match the new function browser.
-       This is not done yet...
-
-       * srcwin.test: Check for errors when the bbox is called for a text 
-       item that is not on screen (so bbox is "").  Return something more 
-       useful.
-
-1999-03-01  James Ingham  <jingham@cygnus.com>
-
-       Changelog entries merged over from gdb development branch.
-
-       1999-01-12  Martin Hunt  <hunt@cygnus.com>
-       * srcwin.test: Add a bunch of tests for the source
-       window filename and function comboboxes.  Add in stack tests.
-
-       1999-01-11  Martin Hunt  <hunt@cygnus.com>
-       * srcwin.test: New file. Source Window tests.
-       * srcwin.exp: New file. Source Window tests.
-
-       Wed Jan  6 09:22:52 1999  Keith Seitz  <keiths@cygnus.com>
-       * c_variable.test (c_variable-1.9): Add new
-       test to check for creation of a variable that is really a type.
-       (c_variable-7.81): Use "output" instead of "print" to get PC.
-       Include missing bits of test.
-
-       * cpp_variable.test (cpp_variable-1.6): Default format
-       is now "natural", not "hexadecimal"
-       (cpp_variable-2.22): Ditto.
-       (cpp_variable-2.24): Force format to hex before getting value.
-
-       * cpp_variable.exp: Supply missing arg to gdbtk_analyze_results.
-
-       Tue Jan  5 12:40:52 1999  Keith Seitz  <keiths@cygnus.com>
-       * gdb.gdbtk/c_variable.c, c_variable.test, c_variable.exp: New C
-       language tests for variable object interface.
-       
-       * gdb.gdbtk/cpp_variable.h, cpp_variable.cc, cpp_variable.test,
-       cpp_variable.exp: New C++ language tests for variable object
-       interface.
-       
-       * gdb.gdbtk/Makefile.in (EXECUTABLES): Add c_variable and cpp_variable.
-
-       Tue Jan  5 12:33:47 1999  Keith Seitz  <keiths@cygnus.com>
-       lib/gdb.exp (gdbtk_analyze_results): Generic function
-       for outputting results of test run.
-       
-       * gdb.gdbtk/defs (gdbtk_test): Handle xpass and xfail.
-       (gdbtk_test_error): New proc which handles error aborts.
-       
-       * gdb.gdbtk/console.exp: Use gdbtk_analyze_results.
-       Check if we have a valid DISPLAY before running.
-       * gdb.gdbtk/browser.exp: Ditto.
-
-       1998-12-07  Martin M. Hunt  <hunt@cygnus.com>
-       * lib/gdb.exp (gdbtk_start): Fix path for itcl library.
-       * gdb.gdbtk/browser.test: Change "manage open" to ManagedWin::open.
-       * gdb.gdbtk/console.test: Same.
-       * gdb.gdbtk/*: Update from devo.
-
-       Fri Jul 24 14:57:19 1998  Keith Seitz  <keiths@cygnus.com>
-       * gdb.gdbtk/Makefile.in: Add new example program "stack".
-       * gdb.gdbtk/browser.test,browser.exp: Add browser window
-         tests.
-       * gdb.gdbtk/stack1.c,stack2.c: Test case for browser window.
-
-1999-02-22  Martin Hunt  <hunt@cygnus.com>
-
-       * srcwin.test (move_mouse_to): Fix typo.
-
-1999-02-03  Martin Hunt  <hunt@cygnus.com>
-
-       * console.test (clear_command_line): Add tests 1.5 - 1.8,
-       which test the new Shift-Up and Shift-Down bindings.
-
-1999-02-01  Martin Hunt  <hunt@cygnus.com>
-
-       * srcwin.test (srcwin-4.3): Fix bp test.
-
-1999-01-29  Martin Hunt  <hunt@cygnus.com>
-
-       * srcwin.test (click): New function that generates an event
-       at a location.
-       (srcwin-4.4): New test. Simulate a click on a line and
-       check for breakpoint set.
-       (srcwin-4.5): New test. Right-click on a line and select "Continue
-       to Here" from popup.
-
-       * srcwin.exp: Source srcwin3.test, which will test source window
-       assembly debugging on executables built without "-g".
-       
-1999-01-29  Martin Hunt  <hunt@cygnus.com>     
-
-       * srcwin.exp: Add srcwin2.test, which are basically the same
-       tests as srcwin.test, but run with a missing source file.
-
-       * srcwin2.test: New file.
-
-       * srcwin.test: Add tests for setting breakpoints in the source window,
-       testing BP balloons, variable balloons, and mixed-mode disassembly
-       of include files.
-
-Sun Jun 28 22:34:34 1998  Martin M. Hunt  <hunt@cygnus.com>
-
-       * gdb.gdbtk/simple.c (main): Make main return an
-       int so compiler will stop complaining.
-
-Fri Jun 26 14:27:13 1998  Keith Seitz  <keiths@cygnus.com>
-
-       * gdb.gdbtk/console.{exp, test}: New console window tests.

diff --git a/gdb/testsuite/gdb.gdbtk/Makefile.in b/gdb/testsuite/gdb.gdbtk/Makefile.in
deleted file mode 100644 (file)
index 4df262a..0000000
--- a/gdb/testsuite/gdb.gdbtk/Makefile.in
+++ /dev/null
@@ -1,36 +0,0 @@
-VPATH = @srcdir@
-srcdir = @srcdir@
-
-EXEEXT = @EXEEXT@
-
-EXECUTABLES = simple$(EXEEXT) stack$(EXEEXT) c_variable$(EXEEXT) \
-               cpp_variable$(EXEEXT)
-
-# uuencoded format to avoid SCCS/RCS problems with binary files.
-CROSS_EXECUTABLES =
-
-all:
-       @echo "Nothing to be done for all..."
-
-info:
-install-info:
-dvi:
-install:
-uninstall: force
-installcheck:
-check:
-
-clean mostlyclean:
-       -rm -f *~ *.o a.out xgdb *.x $(CROSS_EXECUTABLES) *.ci *.tmp
-       -rm -f core core.coremaker coremaker.core corefile $(EXECUTABLES)
-       -rm -f twice-tmp.c
-
-distclean maintainer-clean realclean: clean
-       -rm -f *~ core
-       -rm -f Makefile config.status config.log
-       -rm -f arch.inc
-       -rm -f *-init.exp
-       -rm -fr *.log summary detail *.plog *.sum *.psum site.*
-
-Makefile : $(srcdir)/Makefile.in $(srcdir)/configure.ac
-       $(SHELL) ./config.status --recheck

diff --git a/gdb/testsuite/gdb.gdbtk/README b/gdb/testsuite/gdb.gdbtk/README
deleted file mode 100644 (file)
index 20d7a7c..0000000
--- a/gdb/testsuite/gdb.gdbtk/README
+++ /dev/null
@@ -1,421 +0,0 @@
-                       The Insight Testsuite
-                       ---------------------
-                  Keith Seitz (keiths@cygnus.com)
-                            May 1, 2001
-
-RUNNING THE TESTSUITE
-
-The Insight testsuite is run in much the same way that gdb's testsuites
-are run. The one big difference is the environment variable GDB_DISPLAY,
-which governs what display should be used for the tests.
-
-When GDB_DISPLAY is not set in the user's environment, the Insight testsuite
-will attempt to run Xvfb, an X server with a virtual frame buffer. Using
-Xvfb, the testsuite can run without interuppting the user.
-
-When Xvfb is not available, the testsuite will mark the Insight tests
-"untested" and print out some appropriate warning to the testsuite log
-file.
-
-If GDB_DISPLAY is set in the user's environment, the testsuite will attempt
-to use this display for the tests. If this display is a desktop display,
-it is very likely that any interaction between the user and his desktop
-will interfere with the tests. Some tests warp the cursor, i.e., they
-force the mouse to move on the screen. If you don't want this to happen to
-you, put Xvfb in your path.
-
-On Cygwin systems, Xvfb is not supported. Only two choices are available in
-this environment: run the testsuites using the desktop or do not run the
-testsuite. To run the testsuite on Cygwin, just define the environment
-variable GDB_DISPLAY to anything.
-
-The examples below summarize the usage of the environment variable GDB_DISPLAY
-on unix/X-Windows hosts and Cygwin hosts. In all examples, assume that DISPLAY
-set to the local workstation's main display (:0).
-
-To run the testsuite using Xvfb -- unix only (Xvfb must be in PATH):
-$ make check
-
-To run the testsuite using a given display (either the desktop or a peviously
-started Xvfb):
-$ GDB_DISPLAY=$DISPLAY make check
-
-To run the testsuite on Cygwin:
-$ GDB_DISPLAY=foo make check
-
-
-TESTSUITE INFRASTRUCTURE
-
-The rest of this document deals with writing tests for Insight. This reading
-is only noteworthy for developers and contributors.
-
-The Insight testsuite consists of two large portions of code: code which is
-run in dejagnu and code which runs in Insight's built-in Tcl interpreter. Files
-containing dejagnu code (those files ending in ".exp" in the testsuite directory)
-are "glue code" between gdb's dejagnu testsuite and Insight's Tcl testsuite.
-
-Dejagnu testsuite files are considered "drivers" for any particular set of
-tests, since they allow dejagnu to control Insight's Tcl testsuite.
-
-
-Dejagnu Testsuite Infrastructure
-
-The dejagnu code is responsible for doing several things. Some of the more
-important responsibilities include:
-
-o Initializing the display
-o Determining if tests should be run
-o Results accounting
-o Compiling testcases in various languages
-o Reporting results to gdb's testsuite
-
-There are various functions defined to facilitate the writing of tests. These
-functions currently reside in gdb's gdb.exp (src/gdb/testsuite/lib/gdb.exp) and
-include:
-
-Public functions:
-proc gdbtk_initialize_display {}
-
-  gdbtk_initialize_display should be the first function called from the
-  (dejagnu) test file. It initializes the DISPLAY variable on unix systems
-  and determines (for all host systems) whether or not the testsuite should
-  run. It returns 1 if the test should run. If tests should not run, it
-  marks the test as "untested" and leaves a suitable message about why
-  the test should not run. If gdbtk_initialize_display returns zero, a test
-  should simply exit.
-
-proc gdbtk_start {test}
-
-  This function marks the start of a test and will execute Insight for
-  testing. The TEST parameter should be the file name of the Tcl test
-  file to load into Insight's Tcl interpreter. It returns a list of
-  test results suitable for passing to gdbtk_done or gdbtk_analyze_results.
-  See gdbtk_analyze_results for more information on the format of results.
-
-  gdbtk_start is responsible for communicating target startup information
-  to Insight, so that Insight's testsuite may be run on any target supported
-  by gdb. It does this by setting several environment variables just before
-  it starts Insight. These environment variables are:
-
-  OBJDIR
-    The object directory of the dejagnu testsuite (i.e.,
-    objdir/gdb/testsuite).
-  SRCDIR
-    The dejagnu source directory in which the tests are located (i.e,
-    src/gdb/testsuite)
-  SUBDIR
-    The dejagnu testsuite subdirectory for the test (i.e., gdb.gdbtk)
-  DEFS
-    The location of the testsuite definitions file (i.e.,
-    src/gdb/testsuite/gdb.gdbtk/defs)
-
-  Note that DEFS is converted to absolute tcl-style paths. On unix,
-  this means that DEFS would point to, for example,
-  /home/keiths/insight/src/gdb/testsuite/gdb.gdbtk/defs. On Cygwin it
-  would point to C:/cygwin/home/keiths/insight/src/gdb/testsuite/gdb.gdbtk/defs.
-  This is because of a descrepency between Cygwin's posix paths and Tcl's
-  not-quite-posix paths.
-
-proc gdbtk_analyze_results {results}
-  This function translates the list of results in RESULTS into dejagnu
-  results, reporting the number of failures, errors, passes, and expected
-  failures and passes. It currently does not deal with "untested" and other
-  test statuses from dejagnu since Insight's tcl testsuite does not
-  issue such results.
-
-  The format of the results expected by gdbtk_analyze_results is simple:
-  it is a list of {status name description msg}. "status" is the execution
-  status of one of the tcl tests run. This can be "PASS", "FAIL", "ERROR",
-  "XFAIL", or "XPASS".
-
-  "name" is the name of the test, and it is reported in all testsuite
-  results in dejagnu. This speeds location of the failing test. This
-  "name" may also be given to Insight's testsuite, telling it to
-  only run this test. See "do_tests" in Tcl Testsuite Infrastructure
-  for more information.
-
-  "description" is a textual description of the test given by "name".
-
-  "msg" is currently not used.
-
-proc gdbtk_done {{results {}}}
-  gdbtk_done takes any RESULTS and passes it gdbtk_analyze_results for
-  outputting to the dejagnu part of the testsuite. It may be called
-  without an argument, in which case it will only terminate Xvfb if it
-  was started. Tests must call gdbtk_done _once_ at the end of their
-  test drivers.
-
-Private functions:
-proc _gdbtk_export_target_info
-  This function exports information about the target into the environment
-  so that Insight's testsuite may run programs on any supported gdb
-  target. This target information is passed into the Tcl testsuite
-  via an environment variable, TARGET_INFO, which is really a Tcl array,
-  i.e., the array is constructed in tcl and exported into the environment
-  with Tcl's "array get" command).
-
-  There are four elements to the array:
-  TARGET_INFO(init)   - (optional) A list of commands to execute in gdb
-                        to initialize the session. This usually includes
-                        setting baud rates and remote protocol options.
-  TARGET_INFO(target) - (required) The complete "target" command to connect
-                        to the given target.
-  TARGET_INFO(load)   - (optional) The complete "load" command to load an
-                        executable into a target.
-  TARGET_INFO(run)    - (required) The complete "run" command, sans arguments,
-                       to start a process on the target. For remote targets,
-                        this is usually just "continue".
-  
-proc _gdbtk_xvfb_init
-  This procedure actually determines whether the an Insight test should
-  run and what DISPLAY it should use for that test. It is called by
-  gdbtk_initialize_display to do most of the dirty work.
-
-  It has a simple heuristic: If GDB_DISPLAY is not set and Xvfb is available
-  (on unix), it starts Xvfb, using the current process id as the screen number.
-  If Xvfb is not available and GDB_DISPLAY was not set, it skips the tests.
-
-proc _gdbtk_xvfb_exit
-  _gdbtk_xvfb_exit will kill any previously started Xvfb.
-
-Private globals:
-global _xvfb_spawn_id
-  This variable holds the spawn_id of any Xvfb process started
-  by the testsuite (or it is left undefined).
-
-global _using_windows
-  A global variable which indicates whether the testsuite is running
-  on cygwin. Unfortunately, as of writing, the global variable
-  tcl_platform(platform) is "unix" on Cygwin, so it is not possible
-  to rely on this for platform-dependent operations.
-
-  Instead, this variable is set by gdbtk_initialize_display. The test
-  it uses to determine if Cygwin is being used: it looks for the program
-  cygpath in the PATH. Therefore, cygpath is REQUIRED to run the testsuite
-  on Cygwin. (gdbtk_start also uses cygpath to determine Windows
-  pathnames for Cygwin.)
-
-
-Testsuite Driver Basics
-
-Given the above interfaces for connecting Insight's Tcl testsuite and
-gdb's dejagnu testsuite, the basic testsuite driver file should look
-(minimally) like this:
-
-File: mytest.exp
-1   load_lib "insight-support.exp"
-2   if {[gdbtk_initialize_display]} {
-3     # We found a display to use
-4     gdb_exit;   # Make sure any previous gdb is gone
-5     set results [gdbtk_start mytest.test]
-6
-7     # Done!
-8     gdbtk_done [split $results \n]
-9   }
-
-Line 1 loads the insight testsuite support library which contains definitions
-for all the procedures used in dejagnu to initialize and run the Insight testsuite.
-Line 2 calls gdbtk_initialize_display to ascertain whether there is a display
-to use for the test. This could use an existing display (if GDB_DISPLAY is
-set in the environment) or gdbk_initialize_display could startup an Xvfb
-for use by the testsuite.
-
-Line 4 forces any previously executing gdb to terminate.
-
-Line 5 signals the start of the test run. "mytest.test" is the name of the
-Tcl test file to execute in Insight's built-in Tcl interpreter. The output
-of gdbtk_start_test is all of the results of the Tcl test from Insight, which
-is subsequently passed to gdbk_analyze_results via gdbtk_done on Line 8.
-
-Note how nothing happens if gdbtk_initialize_display returns false.
-
-
-Tcl Testsuite Infrastructure
-
-The heart of Insight's testsuite is its Tcl testsuite. It is these tests
-which run directly in Insight's Tcl interpreter and allow test writers
-access to Insight's internals. Tcl testsuite files have the filename suffix
-".test" to distinguish them from their driver files, which end in ".exp".
-
-The design of the Insight Tcl testsuite parallels Tcl's testsuite. It has
-many powerful features, including the ability to run ANY test in a given
-Tcl test file. See the description of utility routines below for more
-information about running any set of tests from a file.
-
-The bulk of the code implementing the Tcl testsuite infrastructure in
-Insight is contained in the testsuite definitions file, "defs", located
-in src/gdb/testsuite/gdb.gdbtk. This file contains routines necessary
-to write tests for Insight.
-
-Public functions:
-proc gdbtk_read_defs {}
-  This function, located in Insight's core Tcl library, attempts to load
-  the testsuite definitions file. If it fails, it will either pop up
-  a dialog box with the error (if running interactively) or it will
-  print the error to stderr and exit (if running non-interactively).
-
-  If successful, it will return true.
-
-proc gdbtk_test_file {filename}
-  This function is used to load the file given by FILENAME into
-  Insight. It will automatically append ".exe" to any FILENAME
-  on Cygwin-hosted systems.
-
-  If successful, it will load the given file into Insight and
-  return the output of gdb's file command. It will call "error"
-  if it was succesful, therefore all calls to "gdbtk_test_file"
-  should be called using "catch".
-
-  Test authors should not use "gdb_cmd {file FILENAME}" to load
-  files into gdb unless they are testing interface code between
-  gdb and Insight.
-
-proc gdbtk_test_run {{prog_args {}}}
-  gdbtk_test_run runs the previously loaded executable, passing
-  the given arguments to the inferior. Like Insight's Run button,
-  it will do whatever is necessary to get the executable running,
-  including any target initialization (setting baud rate and remote
-  protocol options), downloading the executable to the target, and
-  finally starting execution.
-
-  Test authors should NEVER use "gdb_cmd {run ARGUMENTS}" to run an
-  executable. Doing so will insure that your tests will only run on
-  a native debugger.
-
-  It returns true if successful or false otherwise. It will report
-  the error in a dialog box (if running interactively) or it will
-  print the error to stderr.
-
-proc gdbtk_test {name description script answer}
-  This is Tcl testsuite equivalent of "expect". "name" is a canonical
-  name of the test, usually of the form "shortname-major.minor". This is
-  the name that is used when running selected tests from a given file.
-  If "name" starts with an asterisk (*), it designates that the test
-  is expected to fail.
-
-  "description" is a short textual description of the test to help
-  humans understand what it does.
-
-  "script" is the actual test script to run. The result of this script
-  will be compared against "answer" to determine if the test passed
-  or failed.
-
-  It calls gdbtk_print_verbose to print out the results to the terminal
-  (if running interactively) or to the log file.
-
-proc gdbtk_test_done {}
-  gdbtk_test_done is called at the very end of all tcl tests. It is used
-  to exit Insight and return control back to the dejagnu driver which
-  started the tests.
-  
-proc gdbtk_dotests {file args}
-  Obsolete.
-
-proc do_test {{file {}} {verbose {}} {tests {}}}
-  This procedure is used to invoke the Insight test(s) given in FILE
-  which match the regular expression(s) in TESTS. This is invoked
-  from Insight's console window to run tests interactively.
-
-  VERBOSE sets the verbosity of the test run. When set to one,
-  the testsuite will report all results in human readable form.
-  When set  greater than one, it will print out results as a list,
-  i.e., for passing to gdbtk_analyze_results. If zero, it will only
-  print errors and failures in human readable form.
-
-Public global variables:
-objdir   - The objdir from dejagnu. See gdbtk_start for more information.
-srcdir   - The srcdir from dejagnu. See gdbtk_start for more information.
-test_ran - Indicates whether the last test ran or not. See example below.
-
-Private functions:
-proc gdbtk_test_error {desc}
-  An internal function used to report a framework error in the testsuite.
-  "desc" is a description of the error. It calls gdbtk_test_done.
-
-proc gdbtk_print_verbose {status name description script code answer}
-  A helper procedure to gdbtk_test which prints out results to the terminal
-  or the logfile (or both or none).
-
-Private global variables:
-_test - An array used by the testsuite internals.
-
-
-Tcl Test Basics
-
-Armed with the basic interface described above, it is possible to test Insight's
-GUI. Please do not write tests which attempt to imitate a user (moving the
-mouse and clicking buttons), unless there is no other way to test the functionality.
-
-The basic test file (with one test) looks like this (nonsensical one):
-File: mytest.test
-1  if {![gdbtk_read_defs]} {
-2    break
-3  }
-4  
-5  global objdir test_ran
-6  set program [file join $objdir mytest]
-7  if {[catch {gdbtk_test_file $program} t]} {
-8    gdbtk_test_error "loading \"$program\": $t"
-9  }
-10 if {![gdbtk_test_run]} { exit 1 }
-11
-12 global foo
-13 set foo 1
-14
-15 # Test:  mytest-1.1
-16 # Desc:  check if a source window was created
-17 gdbtk_test mytest-1.1 {source window created} {
-18   set window [ManagedWin::find SrcWin]
-19   llength $window
-20   set foo 13
-21 } {1}
-22
-23 if {$test_ran} {
-24   set foo 1
-25 }
-26
-27 # Done
-28 gdbtk_test_done
-
-Line 1 calls the Inisght function gdbtk_read_defs to read in the testsuite
-definitions file.
-
-Line 6 then specifies the name of a file (mytest) in the object directory
-which is loaded into gdb on Line 7. If loading the file into Insight
-failed, gdbtk_test_error is called to publish the error (and terminate the
-test run for this file).
-
-Line 10 runs the executable on the target, and exits if it was unable
-to do so.
-
-Line 13 simply sets a global variable foo to illustrate the purpose
-of the global "test_ran". Before the test "mytest-1.1" runs, foo is set to
-one. In order to support running specific tests, the state of the debugger
-cannot be altered INSIDE gdbtk_test scripts, since the contents of the
-script may not be run if the user requested only a specific test to run.
-
-Line 20 in the middle of the test modifies the global foo. If subsequent
-test relied on foo being one, we would have a state violation, since
-mytest-1.1 may have (or may have not) run.
-
-Therefore, we can check if a test ran and reset foo by checking the
-global "test_ran". If set, we know that the previous test (mytest-1.1)
-was run, and that foo is now thirteen. We reset the result back to one.
-
-(Aside: Some tests do not follow this rule explicitly: they can assume
-that all tests run sequentially. In these cases, running a specific
-test in the file will probably fail, since the debugger is not brought
-to a known state along the way.)
-
-Lines 17-21 contain the actual test. The test's name is "mytest-1.1". It
-is this name that may be referred to when asking the testsuite to run
-a specific test. The description of this test is "source window created",
-indicating that mytest-1.1's purpose is to check whether a source window
-was created.
-
-If gdbtk_test determines that this test is to run, it will execute the
-next part, lines 18-20, and compare the output of that script (llength
-$window) with "1". If the result is not "1", a failure is recorded. If
-it is "1", a pass is recorded.
-
-Finally, the test file is done and exits on line 28.

diff --git a/gdb/testsuite/gdb.gdbtk/browser.exp b/gdb/testsuite/gdb.gdbtk/browser.exp
deleted file mode 100644 (file)
index 475bdb5..0000000
--- a/gdb/testsuite/gdb.gdbtk/browser.exp
+++ /dev/null
@@ -1,41 +0,0 @@
-# Copyright 1998, 1999, 2001, 2004 Red Hat, Inc.
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms of the GNU General Public License (GPL) as published by
-# the Free Software Foundation; either version 2 of the License, or (at
-# your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-
-load_lib ../gdb.gdbtk/insight-support.exp
-
-if {[gdbtk_initialize_display]} {
-  if {$tracelevel} {
-    strace $tracelevel
-  }
-
-  #
-  # test browser window
-  #
-  set prms_id 0
-  set bug_id 0
-
-  set testfile "stack"
-  set binfile ${objdir}/${subdir}/${testfile}
-  set r [gdb_compile "${srcdir}/${subdir}/stack1.c ${srcdir}/${subdir}/stack2.c" "${binfile}" executable {debug}]
-  if  { $r != "" } {
-    gdb_suppress_entire_file \
-      "Testcase compile failed, so some tests in this file will automatically fail."
-  }
-
-  # Start with a fresh gdbtk
-  gdb_exit
-  set results [gdbtk_start [file join $srcdir $subdir browser.test]]
-  set results [split $results \n]
-
-  # Analyze results
-  gdbtk_done $results
-}

diff --git a/gdb/testsuite/gdb.gdbtk/browser.test b/gdb/testsuite/gdb.gdbtk/browser.test
deleted file mode 100644 (file)
index a714644..0000000
--- a/gdb/testsuite/gdb.gdbtk/browser.test
+++ /dev/null
@@ -1,683 +0,0 @@
-# Browser Window Tests
-# Copyright 1998, 2001 Red Hat, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-# This file was written by Keith Seitz (keiths@cygnus.com)
-
-# Read in the standard defs file
-
-if {![gdbtk_read_defs]} {
-  break
-}
-
-global objdir test_ran
-set _files(stupid_initializer) -100
-
-#####                            #####
-#                                    #
-#  Helper functions for this module  #
-#                                    #
-#####                            #####
-
-# Set the search expression
-proc set_regexp {exp} {
-  global browser
-
-  $browser component filt_entry delete 0 end
-  $browser component filt_entry insert 0 $exp
-}
-
-# Do the search
-proc do_search {} {
-  global browser
-  $browser search
-  set m [$browser component func_box get 0 end]
-
-  return $m
-}
-
-# Set search to use regular expressions.
-proc set_search_mode {val} {
-  global browser
-  pref set gdb/search/filter_mode $val
-
-  # Use configure instead of entryset: need to have
-  # combobox's command fire
-  $browser component filt_type configure -value $val
-}
-
-# Highlight a file
-proc select {filename} {
-  global browser _files
-
-  if {[info exists _files($filename)]} {
-    $browser component file_box selection set $_files($filename)
-  } else {
-    set files [$browser component file_box get 0 end]
-    set i [lsearch $files $filename]
-    set _files($filename) $i
-    $browser component file_box selection set $i
-  }
-  $browser search
-}
-
-proc select_all {} {
-  global browser
-  
-  $browser component file_all invoke
-
-}
-
-# clear all files
-proc clear {} {
-  global browser
-
-  $browser component file_box selection clear 0 end
-  $browser search
-}
-
-#####         #####
-#                 #
-#  BROWSER TESTS  #
-#                 #
-#####         #####
-
-# Load the test executable
-set program [file join $objdir stack]
-if {[catch {gdbtk_test_file $program} t]} {
-  # This isn't a test case, since if this fails, we're hosed.
-  gdbtk_test_error "loading \"$program\": $t"
-}
-
-# Open a browser
-set browser [ManagedWin::open BrowserWin]
-
-# Test:  browser-1.1
-# Desc:  Check file listbox contents
-gdbtk_test browser-1.1 {file listbox contents} {
-  set m [$browser component file_box get 0 end]
-  set f {}
-  if {[lsearch $m stack1.c] == -1} {
-    lappend f 0
-  } else {
-    lappend f 1
-  }
-  if {[lsearch $m stack2.c] == -1} {
-    lappend f 0
-  } else {
-    lappend f 1
-  }
-
-  join $f \ 
-} {1 1}
-
-# Tests 2.* test starts with search mode.
-# Test:  browser-2.1
-# Desc:  Check all files/all funcs
-gdbtk_test browser-2.1 {all files/all funcs} {
-  set_search_mode "starts with"
-  set_regexp ""
-  select_all
-  set m [do_search]
-  set r 0
-  foreach f {extern_func1_1 extern_func1_10 extern_func1_11 extern_func1_12 \
-              extern_func1_13 extern_func1_14 extern_func1_15 extern_func1_2 \
-              extern_func1_3 extern_func1_4 extern_func1_5 extern_func1_6 \
-              extern_func1_7 extern_func1_8 extern_func1_9 func_1 \
-              func_10 func_11 func_12 func_13 \
-              func_14 func_15 func_2 func_3 \
-              func_4 func_5 func_6 func_7 \
-              func_8 func_9 main static_func_1 \
-              static_func_10 static_func_11 static_func_12 static_func_13 \
-              static_func_14 static_func_15 static_func_2 static_func_3 \
-              static_func_4 static_func_5 static_func_6 static_func_7 \
-              static_func_8 static_func_9} {
-    if {[lsearch $m $f] != -1} {
-      incr r
-    }
-  }
-
-  set r
-} {46}
-
-# Test:  browser-2.2
-# Desc:  Check all functions in stack1.c
-gdbtk_test browser-2.2 {all functions in stack1.c} {
-  set_regexp ""
-  clear
-  select stack1.c
-  set m [do_search]
-
-  set r 0
-  foreach f {func_1 func_10 func_11 func_12 \
-              func_13 func_14 func_15 func_2 \
-              func_3 func_4 func_5 func_6 \
-              func_7 func_8 func_9 main \
-              static_func_1 static_func_10 static_func_11 static_func_12 \
-              static_func_13 static_func_14 static_func_15 static_func_2 \
-              static_func_3 static_func_4 static_func_5 static_func_6 \
-              static_func_7 static_func_8 static_func_9} {
-    if {[lsearch $m $f] != -1} {
-      incr r
-    }
-  }
-
-  set r
-} {31}
-if {$test_ran} {
-  clear
-}
-
-# Test:  browser-2.3
-# Desc:  Check all functions in stack2.c
-gdbtk_test browser-2.3 {all functions in stack2.c} {
-  set_regexp ""
-  clear
-  select stack2.c
-  set m [do_search]
-
-  set r 0
-  foreach f {extern_func1_1 extern_func1_10 extern_func1_11 \
-              extern_func1_12 extern_func1_13 extern_func1_14 extern_func1_15 \
-              extern_func1_2 extern_func1_3 extern_func1_4 extern_func1_5 \
-              extern_func1_6 extern_func1_7 extern_func1_8 extern_func1_9} {
-    if {[lsearch $m $f] != -1} {
-      incr r
-    }
-  }
-
-  set r
-} {15}
-if {$test_ran} {
-  clear
-}
-
-# Test:  browser-2.4
-# Desc:  Check for all functions matching "func" - mode starts with
-gdbtk_test browser-2.4 {all functions matching "func" - "mode starts with"} {
-  set_search_mode "starts with"
-  select_all
-  set_regexp func
-  do_search
-} {func_1 func_10 func_11 func_12 func_13 func_14 func_15 func_2 func_3 func_4 func_5 func_6 func_7 func_8 func_9}
-
-# Test:  browser-2.5
-# Desc:  Check all functions matching "func" in stack1.c - mode starts with
-gdbtk_test browser-2.5 {all functions matching "func" in stack1.c - "mode starts with"} {
-  set_search_mode "starts with"
-  set_regexp func
-  clear
-  select stack1.c
-  do_search
-} {func_1 func_10 func_11 func_12 func_13 func_14 func_15 func_2 func_3 func_4 func_5 func_6 func_7 func_8 func_9}
-
-# Test:  browser-2.6
-# Desc:  Check all functions matching "funcs" in stack2.c - mode starts with
-gdbtk_test browser-2.6 {all functions matching "func" in stack2.c - mode "starts with"} {
-  set_search_mode "starts with"
-  set_regexp func
-  clear
-  select stack2.c
-  do_search
-} {}
-if {$test_ran} {
-  clear
-}
-
-# Test:  browser-2.7
-# Desc:  Check all functions matching "foobar"
-gdbtk_test browser-2.7 {all functions matching "foobar"} {
-  set_search_mode "starts with"
-  select_all
-  set_regexp foobar
-  do_search
-} {}
-
-# Test:  browser-2.8
-# Desc:  Check all functions matching "foobar" in stack1.c
-gdbtk_test browser-2.8 {functions matching "foobar" in stack1.c} {
-  set_search_mode "starts with"
-  set_regexp foobar
-  clear
-  select stack1.c
-  do_search
-} {}
-
-# Tests 3.* test "contains" search mode.
-# Test:  browser-3.1
-# Desc:  Check all files/all funcs
-gdbtk_test browser-3.1 {all files/all funcs} {
-  set_search_mode "contains"
-  set_regexp ""
-  select_all
-  set m [do_search]
-  set r 0
-  foreach f {extern_func1_1 extern_func1_10 extern_func1_11 extern_func1_12 \
-              extern_func1_13 extern_func1_14 extern_func1_15 extern_func1_2 \
-              extern_func1_3 extern_func1_4 extern_func1_5 extern_func1_6 \
-              extern_func1_7 extern_func1_8 extern_func1_9 func_1 \
-              func_10 func_11 func_12 func_13 \
-              func_14 func_15 func_2 func_3 \
-              func_4 func_5 func_6 func_7 \
-              func_8 func_9 main static_func_1 \
-              static_func_10 static_func_11 static_func_12 static_func_13 \
-              static_func_14 static_func_15 static_func_2 static_func_3 \
-              static_func_4 static_func_5 static_func_6 static_func_7 \
-              static_func_8 static_func_9} {
-    if {[lsearch $m $f] != -1} {
-      incr r
-    }
-  }
-
-  set r
-} {46}
-
-# Test:  browser-3.2
-# Desc:  Check all functions in stack1.c
-gdbtk_test browser-3.2 {all functions in stack1.c} {
-  set_regexp ""
-  set_search_mode "contains"
-  clear
-  select stack1.c
-  set m [do_search]
-
-  set r 0
-  foreach f {func_1 func_10 func_11 func_12 \
-              func_13 func_14 func_15 func_2 \
-              func_3 func_4 func_5 func_6 \
-              func_7 func_8 func_9 main \
-              static_func_1 static_func_10 static_func_11 static_func_12 \
-              static_func_13 static_func_14 static_func_15 static_func_2 \
-              static_func_3 static_func_4 static_func_5 static_func_6 \
-              static_func_7 static_func_8 static_func_9} {
-    if {[lsearch $m $f] != -1} {
-      incr r
-    }
-  }
-
-  set r
-} {31}
-
-if {$test_ran} {
-  clear
-}
-
-# Test:  browser-3.3
-# Desc:  Check all functions in stack2.c
-gdbtk_test browser-3.3 {all functions in stack2.c} {
-  set_regexp ""
-  set_search_mode "contains"
-  clear
-  select stack2.c
-  set m [do_search]
-
-  set r 0
-  foreach f {extern_func1_1 extern_func1_10 extern_func1_11 \
-              extern_func1_12 extern_func1_13 extern_func1_14 extern_func1_15 \
-              extern_func1_2 extern_func1_3 extern_func1_4 extern_func1_5 \
-              extern_func1_6 extern_func1_7 extern_func1_8 extern_func1_9} {
-    if {[lsearch $m $f] != -1} {
-      incr r
-    }
-  }
-
-  set r
-} {15}
-if {$test_ran} {
-  clear
-}
-
-# Test:  browser-3.4
-# Desc:  Check for all functions matching "func" - mode contains
-gdbtk_test browser-3.4 {all functions matching "func_1" - "mode contains"} {
-  set_search_mode "contains"
-  set_regexp "func_1"
-  select_all
-  do_search
-} {func_1 func_10 func_11 func_12 func_13 func_14 func_15 static_func_1 static_func_10 static_func_11 static_func_12 static_func_13 static_func_14 static_func_15}
-
-# Test:  browser-3.5
-# Desc:  Check all functions matching "func_1" in stack1.c - mode contains
-gdbtk_test browser-3.5 {all functions matching "func_1" in stack1.c - "mode contains"} {
-  set_search_mode "contains"
-  set_regexp "func_1"
-  clear
-  select stack1.c
-  do_search
-} {func_1 func_10 func_11 func_12 func_13 func_14 func_15 static_func_1 static_func_10 static_func_11 static_func_12 static_func_13 static_func_14 static_func_15}
-
-# Test:  browser-3.6
-# Desc:  Check all functions matching "func_1" in stack2.c - mode contains
-gdbtk_test browser-3.6 {all functions matching "func" in stack2.c - mode "contains"} {
-  set_search_mode "contains"
-  set_regexp func_1
-  clear
-  select stack2.c
-  do_search
-} {}
-
-# Test:  browser-3.7
-# Desc:  Check all functions matching "foobar"
-gdbtk_test browser-3.7 {all functions matching "foobar"} {
-  set_search_mode "contains"
-  select_all
-  set_regexp foobar
-  do_search
-} {}
-
-# Test:  browser-3.8
-# Desc:  Check all functions matching "foobar" in stack1.c
-gdbtk_test browser-3.8 {functions matching "foobar" in stack1.c} {
-  set_search_mode "contains"
-  set_regexp foobar
-  clear
-  select stack1.c
-  do_search
-} {}
-
-# Tests 4.* test "ends with" search mode.
-# Test:  browser-4.1
-# Desc:  Check all files/all funcs
-gdbtk_test browser-4.1 {all files/all funcs} {
-  set_search_mode "ends with"
-  set_regexp ""
-  select_all
-  set m [do_search]
-  set r 0
-  foreach f {extern_func1_1 extern_func1_10 extern_func1_11 extern_func1_12 \
-              extern_func1_13 extern_func1_14 extern_func1_15 extern_func1_2 \
-              extern_func1_3 extern_func1_4 extern_func1_5 extern_func1_6 \
-              extern_func1_7 extern_func1_8 extern_func1_9 func_1 \
-              func_10 func_11 func_12 func_13 \
-              func_14 func_15 func_2 func_3 \
-              func_4 func_5 func_6 func_7 \
-              func_8 func_9 main static_func_1 \
-              static_func_10 static_func_11 static_func_12 static_func_13 \
-              static_func_14 static_func_15 static_func_2 static_func_3 \
-              static_func_4 static_func_5 static_func_6 static_func_7 \
-              static_func_8 static_func_9} {
-    if {[lsearch $m $f] > -1} {
-      incr r
-    }
-  }
-
-  set r
-} {46}
-
-# Test:  browser-4.2
-# Desc:  Check all functions in stack1.c
-gdbtk_test browser-4.2 {all functions in stack1.c} {
-  set_regexp ""
-  set_search_mode "ends with"
-  clear
-  select stack1.c
-  set m [do_search]
-
-  set r 0
-  foreach f {func_1 func_10 func_11 func_12 \
-              func_13 func_14 func_15 func_2 \
-              func_3 func_4 func_5 func_6 \
-              func_7 func_8 func_9 main \
-              static_func_1 static_func_10 static_func_11 static_func_12 \
-              static_func_13 static_func_14 static_func_15 static_func_2 \
-              static_func_3 static_func_4 static_func_5 static_func_6 \
-              static_func_7 static_func_8 static_func_9} {
-    if {[lsearch $m $f] != -1} {
-      incr r
-    }
-  }
-
-  set r
-} {31}
-
-if {$test_ran} {
-  clear
-}
-
-# Test:  browser-4.3
-# Desc:  Check all functions in stack2.c
-gdbtk_test browser-4.3 {all functions in stack2.c} {
-  set_regexp ""
-  set_search_mode "ends with"
-  clear
-  select stack2.c
-  set m [do_search]
-
-  set r 0
-  foreach f {extern_func1_1 extern_func1_10 extern_func1_11 \
-              extern_func1_12 extern_func1_13 extern_func1_14 extern_func1_15 \
-              extern_func1_2 extern_func1_3 extern_func1_4 extern_func1_5 \
-              extern_func1_6 extern_func1_7 extern_func1_8 extern_func1_9} {
-    if {[lsearch $m $f] != -1} {
-      incr r
-    }
-  }
-
-  set r
-} {15}
-if {$test_ran} {
-  clear
-}
-
-# Test:  browser-4.4
-# Desc:  Check for all functions matching "func_1" - mode ends with
-gdbtk_test browser-4.4 {all functions matching "func_1" - "mode ends with"} {
-  set_search_mode "ends with"
-  set_regexp "func_1"
-  select_all
-  do_search
-} {func_1 static_func_1}
-
-# Test:  browser-4.5
-# Desc:  Check all functions matching "func_1" in stack1.c - mode ends with
-gdbtk_test browser-4.5 {all functions matching "func_1" in stack1.c - "mode ends with"} {
-  set_search_mode "ends with"
-  set_regexp "func_1"
-  clear
-  select stack1.c
-  do_search
-} {func_1 static_func_1}
-if {$test_ran} {
-  clear
-}
-
-# Test:  browser-4.6
-# Desc:  Check all functions matching "func_1" in stack2.c - mode ends with
-gdbtk_test browser-4.6 {all functions matching "func" in stack2.c - mode "ends with"} {
-  set_search_mode "ends with"
-  set_regexp func_1
-  clear
-  select stack2.c
-  do_search
-} {}
-
-# Test:  browser-4.7
-# Desc:  Check all functions matching "foobar"
-gdbtk_test browser-4.7 {all functions matching "foobar"} {
-  set_search_mode "ends with"
-  select_all
-  set_regexp foobar
-  do_search
-} {}
-
-# Test:  browser-4.8
-# Desc:  Check all functions matching "foobar" in stack1.c
-gdbtk_test browser-4.8 {functions matching "foobar" in stack1.c} {
-  set_search_mode "ends with"
-  set_regexp foobar
-  clear
-  select stack1.c
-  do_search
-} {}
-if {$test_ran} {
-  clear
-}
-
-# Test:  browser-5.10
-# Desc:  Check all functions matching regexp "func"
-gdbtk_test browser-5.10 {all functions matching regexp "func"} {
-  set_search_mode "matches regexp"
-  set_regexp func
-  select_all
-  do_search
-} {extern_func1_1 extern_func1_10 extern_func1_11 extern_func1_12 extern_func1_13 extern_func1_14 extern_func1_15 extern_func1_2 extern_func1_3 extern_func1_4 extern_func1_5 extern_func1_6 extern_func1_7 extern_func1_8 extern_func1_9 func_1 func_10 func_11 func_12 func_13 func_14 func_15 func_2 func_3 func_4 func_5 func_6 func_7 func_8 func_9 static_func_1 static_func_10 static_func_11 static_func_12 static_func_13 static_func_14 static_func_15 static_func_2 static_func_3 static_func_4 static_func_5 static_func_6 static_func_7 static_func_8 static_func_9}
-
-# Test:  browser-5.11
-# Desc:  Check all functions matching regexp "func" in stack1.c
-gdbtk_test browser-5.11 {all functions matching regexp "func" in stack1.c} {
-  set_search_mode "matches regexp"
-  set_regexp func
-  clear
-  select stack1.c
-  do_search
-} {func_1 func_10 func_11 func_12 func_13 func_14 func_15 func_2 func_3 func_4 func_5 func_6 func_7 func_8 func_9 static_func_1 static_func_10 static_func_11 static_func_12 static_func_13 static_func_14 static_func_15 static_func_2 static_func_3 static_func_4 static_func_5 static_func_6 static_func_7 static_func_8 static_func_9}
-
-# Test:  browser-5.12
-# Desc:  Check all functions matching regexp "func" in stack2.c
-gdbtk_test browser-5.12 {all functions matching regexp "func" in stack2.c} {
-  set_regexp func
-  clear
-  select stack2.c
-  do_search
-} {extern_func1_1 extern_func1_10 extern_func1_11 extern_func1_12 extern_func1_13 extern_func1_14 extern_func1_15 extern_func1_2 extern_func1_3 extern_func1_4 extern_func1_5 extern_func1_6 extern_func1_7 extern_func1_8 extern_func1_9}
-
-# Test:  browser-5.13
-# Desc:  Check all functions matching regexp "\_1$"
-gdbtk_test browser-5.13 {all functions matching regexp "\_1$"} {
-  set_search_mode "matches regexp"
-  set_regexp {\_1$}
-  select_all
-  do_search
-} {extern_func1_1 func_1 static_func_1}
-
-# Test:  browser-5.14
-# Desc:  Check all functions matching regexp "\_1$" in stack1.c
-gdbtk_test browser-5.14 {all functions matching regexp "\_1$" in stack1.c} {
-  set_search_mode "matches regexp"
-  set_regexp {\_1$}
-  clear
-  select stack1.c
-  do_search
-} {func_1 static_func_1}
-
-# Test:  browser-5.15
-# Desc:  Check all functions matching regexp "\_1$" in stack2.c
-gdbtk_test browser-5.15 {all functions matching regexp "\_1$" in stack2.c} {
-  set_search_mode "matches regexp"
-  set_regexp {\_1$}
-  clear
-  select stack2.c
-  do_search
-} {extern_func1_1}
-
-# Test:  browser-5.16
-# Desc:  Check all functions matching regexp "foobar"
-gdbtk_test browser-5.16 {all functions matching regexp "foobar"} {
-  set_search_mode "matches regexp"
-  set_regexp foobar
-  select_all
-  do_search
-} {}
-
-# Test:  browser-5.17
-# Desc:  Check all functions matching regexp "foobar" in stack1.c
-gdbtk_test browser-5.17 {all functions matching regexp "foobar" in stack1.c} {
-  set_search_mode "matches regexp"
-  set_regexp foobar
-  clear
-  select stack1.c
-  do_search
-} {}
-
-
-# Test:  browser-6.1
-# Desc:  Check select button function
-gdbtk_test browser-6.1 {select button - select all} {
-  clear
-  select_all
-  set m [$browser component file_box curselection]
-
-  expr {[llength $m] >= 2}
-} {1}
-
-# Test:  browser-6.2
-# Desc:  Check that search expressions are saved
-gdbtk_test browser-6.2 {save last search expression} {
-  set_regexp hello
-  select_all
-  do_search
-  pref get gdb/search/last_symbol
-} {hello}
-
-# Test:  browser-7.1
-# Desc:  Toggle all bps on
-gdbtk_test browser-7.1 {toggle_all_bp on} {
-  set_regexp {\_1$}
-  set_search_mode "matches regexp"
-  select_all
-  set funcs [do_search]
-
-  # select all to set bp on
-  $browser component func_box selection set 0 end
-  $browser component func_add_bp invoke
-
-  set bps {}
-  foreach f $funcs {
-    if {![catch {gdb_loc $f} ls]} {
-      if {[bp_exists $ls] != -1} {
-       lappend bps $f
-      }
-    }
-  }
-
-  catch {gdb_cmd "delete" 0}
-  join [lsort $bps]
-} {extern_func1_1 func_1 static_func_1}
-
-# Test:  browser-7.2
-# Desc:  Toggle some bps off
-gdbtk_test browser-7.2 {toggle_some_bp off} {
-  set_regexp {\_1$}
-  set_search_mode "matches regexp"
-  select_all
-  set funcs [do_search]
-
-  $browser component func_box selection set 0 end
-  $browser component func_add_bp invoke
-
-  # Turn off all the "static_func_*" bps
-  set_regexp {^static.*_1$}
-  do_search
-  $browser component func_box selection set 0 end
-  $browser component func_remove_bp invoke
-  set bps {}
-  foreach f $funcs {
-    if {![catch {gdb_loc $f} ls]} {
-      if {[bp_exists $ls] != -1} {
-       lappend bps $f
-      }
-    }
-  }
-
-  catch {gdb_cmd "delete" 0}
-
-  join [lsort $bps]
-} {extern_func1_1 func_1}
-
-#
-#  Exit
-#
-gdbtk_test_done

diff --git a/gdb/testsuite/gdb.gdbtk/c_variable.c b/gdb/testsuite/gdb.gdbtk/c_variable.c
deleted file mode 100644 (file)
index 0c0efc2..0000000
--- a/gdb/testsuite/gdb.gdbtk/c_variable.c
+++ /dev/null
@@ -1,298 +0,0 @@
-#include <stdlib.h>
-
-struct _simple_struct {
-  int integer;
-  unsigned int unsigned_integer;
-  char character;
-  signed char signed_character;
-  char *char_ptr;
-  int array_of_10[10];
-};
-
-typedef struct _simple_struct simpleton;
-
-simpleton global_simple;
-
-enum foo {
-  bar = 1,
-  baz
-};
-
-typedef enum foo efoo;
-
-union named_union
-{
-  int integer;
-  char *char_ptr;
-};
-
-typedef struct _struct_decl {
-  int   integer;
-  char  character;
-  char *char_ptr;
-  long  long_int;
-  int  **int_ptr_ptr;
-  long  long_array[10];
-
-  void (*func_ptr) (void);
-  struct _struct_decl (*func_ptr_struct) (int, char *, long);
-  struct _struct_decl *(*func_ptr_ptr) (int, char *, long);
-  union {
-    int   a;
-    char *b;
-    long  c;
-    enum foo d;
-  } u1;
-
-  struct {
-    union {
-      struct {
-        int d;
-        char e[10];
-        int *(*func) (void);
-        efoo foo;
-      } u1s1;
-
-      long f;
-      struct {
-        char array_ptr[2];
-        int (*func) (int, char *);
-      } u1s2;
-    } u2;
-
-    int g;
-    char h;
-    long i[10];
-  } s2;
-} weird_struct;
-
-struct _struct_n_pointer {
-  char ****char_ptr;
-  long ****long_ptr;
-  struct _struct_n_pointer *ptrs[3];
-  struct _struct_n_pointer *next;
-};
-
-void do_locals_tests (void);
-void do_block_tests (void);
-void subroutine1 (int, long *);
-void nothing (void);
-void do_children_tests (void);
-void do_special_tests (void);
-void incr_a (int);
-
-void incr_a (int a)
-{
-  int b;
-  b = a;
-}
-
-void
-do_locals_tests ()
-{
-  int linteger;
-  int *lpinteger;
-  char lcharacter;
-  char *lpcharacter;
-  long llong;
-  long *lplong;
-  float lfloat;
-  float *lpfloat;
-  double ldouble;
-  double *lpdouble;
-  struct _simple_struct lsimple;
-  struct _simple_struct *lpsimple;
-  void (*func) (void);
-
-  /* Simple assignments */
-  linteger = 1234;
-  lpinteger = &linteger;
-  lcharacter = 'a';
-  lpcharacter = &lcharacter;
-  llong = 2121L;
-  lplong = &llong;
-  lfloat = 2.1;
-  lpfloat = &lfloat;
-  ldouble = 2.718281828459045;
-  lpdouble = &ldouble;
-  lsimple.integer = 1234;
-  lsimple.unsigned_integer = 255;
-  lsimple.character = 'a';
-  lsimple.signed_character = 21;
-  lsimple.char_ptr = &lcharacter;
-  lpsimple = &lsimple;
-  func = nothing;
-
-  /* Check pointers */
-  linteger = 4321;
-  lcharacter = 'b';
-  llong = 1212L;
-  lfloat = 1.2;
-  ldouble = 5.498548281828172;
-  lsimple.integer = 255;
-  lsimple.unsigned_integer = 4321;
-  lsimple.character = 'b';
-  lsimple.signed_character = 0;
-
-  subroutine1 (linteger, &llong);
-}
-
-void
-nothing ()
-{
-}
-
-void
-subroutine1 (int i, long *l)
-{
-  global_simple.integer = i + 3;
-  i = 212;
-  *l = 12;
-}
-
-void
-do_block_tests ()
-{
-  int cb = 12;
-
-  {
-    int foo;
-    foo = 123;
-    {
-      int foo2;
-      foo2 = 123;
-      {
-        int foo;
-        foo = 321;
-      }
-      foo2 = 0;
-    }
-    foo = 0;
-  }
-
-  cb = 21;
-}
-
-void
-do_children_tests (void)
-{
-  weird_struct *weird;
-  struct _struct_n_pointer *psnp;
-  struct _struct_n_pointer snp0, snp1, snp2;
-  char a0, *a1, **a2, ***a3;
-  char b0, *b1, **b2, ***b3;
-  char c0, *c1, **c2, ***c3;
-  long z0, *z1, **z2, ***z3;
-  long y0, *y1, **y2, ***y3;
-  long x0, *x1, **x2, ***x3;
-  int *foo;
-  int bar;
-
-  struct _struct_decl struct_declarations;
-  weird = &struct_declarations;
-
-  struct_declarations.integer = 123;
-  weird->char_ptr = "hello";
-  bar = 2121;
-  foo = &bar;
-  struct_declarations.int_ptr_ptr = &foo;
-  weird->long_array[0] = 1234;
-  struct_declarations.long_array[1] = 2345;
-  weird->long_array[2] = 3456;
-  struct_declarations.long_array[3] = 4567;
-  weird->long_array[4] = 5678;
-  struct_declarations.long_array[5] = 6789;
-  weird->long_array[6] = 7890;
-  struct_declarations.long_array[7] = 8901;
-  weird->long_array[8] = 9012;
-  struct_declarations.long_array[9] = 1234;
-
-  weird->func_ptr = nothing;
-
-  /* Struct/pointer/array tests */
-  a0 = '0';
-  a1 = &a0;
-  a2 = &a1;
-  a3 = &a2;
-  b0 = '1';
-  b1 = &b0;
-  b2 = &b1;
-  b3 = &b2;
-  c0 = '2';
-  c1 = &c0;
-  c2 = &c1;
-  c3 = &c2;
-  z0 = 0xdead + 0;
-  z1 = &z0;
-  z2 = &z1;
-  z3 = &z2;
-  y0 = 0xdead + 1;
-  y1 = &y0;
-  y2 = &y1;
-  y3 = &y2;
-  x0 = 0xdead + 2;
-  x1 = &x0;
-  x2 = &x1;
-  x3 = &x2;
-  snp0.char_ptr = &a3;
-  snp0.long_ptr = &z3;
-  snp0.ptrs[0] = &snp0;
-  snp0.ptrs[1] = &snp1;
-  snp0.ptrs[2] = &snp2;
-  snp0.next = &snp1;
-  snp1.char_ptr = &b3;
-  snp1.long_ptr = &y3;
-  snp1.ptrs[0] = &snp0;
-  snp1.ptrs[1] = &snp1;
-  snp1.ptrs[2] = &snp2;
-  snp1.next = &snp2;
-  snp2.char_ptr = &c3;
-  snp2.long_ptr = &x3;
-  snp2.ptrs[0] = &snp0;
-  snp2.ptrs[1] = &snp1;
-  snp2.ptrs[2] = &snp2;
-  snp2.next = 0x0;
-  psnp = &snp0;
-  snp0.char_ptr = &b3;
-  snp1.char_ptr = &c3;
-  snp2.char_ptr = &a3;
-  snp0.long_ptr = &y3;
-  snp1.long_ptr = &x3;
-  snp2.long_ptr = &z3;
-}
-
-void
-do_special_tests (void)
-{
-  union named_union u;
-  union {
-    int a;
-    char b;
-    long c;
-  } anonu;
-  struct _simple_struct s;
-  struct {
-    int a;
-    char b;
-    long c;
-  } anons;
-  enum foo e;
-  enum { A, B, C } anone;
-  int array[21];
-  int a;
-
-  a = 1;   
-  incr_a(2);
-}
-
-int
-main (int argc, char *argv [])
-{
-  do_locals_tests ();
-  do_block_tests ();
-  do_children_tests ();
-  do_special_tests ();
-  exit (0);
-}
-
-  

diff --git a/gdb/testsuite/gdb.gdbtk/c_variable.exp b/gdb/testsuite/gdb.gdbtk/c_variable.exp
deleted file mode 100644 (file)
index 0fcd652..0000000
--- a/gdb/testsuite/gdb.gdbtk/c_variable.exp
+++ /dev/null
@@ -1,42 +0,0 @@
-# Copyright 1999, 2001, 2004 Red Hat, Inc.
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms of the GNU General Public License (GPL) as published by
-# the Free Software Foundation; either version 2 of the License, or (at
-# your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-
-load_lib ../gdb.gdbtk/insight-support.exp
-
-if {[gdbtk_initialize_display]} {
-  if {$tracelevel} {
-    strace $tracelevel
-  }
-
-  #
-  # test variable API
-  #
-  set prms_id 0
-  set bug_id 0
-
-  set testfile "c_variable"
-  set srcfile ${testfile}.c
-  set binfile ${objdir}/${subdir}/${testfile}
-  set r [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug}]
-  if  { $r != "" } {
-    gdb_suppress_entire_file \
-      "Testcase compile failed, so some tests in this file will automatically fail."
-  }
-
-  # Start with a fresh gdbtk
-  gdb_exit
-  set results [gdbtk_start [file join $srcdir $subdir ${testfile}.test]]
-  set results [split $results \n]
-
-  # Analyze results
-  gdbtk_done $results
-}

diff --git a/gdb/testsuite/gdb.gdbtk/c_variable.test b/gdb/testsuite/gdb.gdbtk/c_variable.test
deleted file mode 100644 (file)
index 625ac7c..0000000
--- a/gdb/testsuite/gdb.gdbtk/c_variable.test
+++ /dev/null
@@ -1,2071 +0,0 @@
-# Varobj Tests (C language)
-# Copyright 1998, 2001, 2003 Red Hat, Inc.
-#
-# This Program Is Free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-# Please email any bugs, comments, and/or additions to this file to:
-# insight@sources.redhat.com
-
-# This file was written by Keith Seitz (keiths@cygnus.com)
-
-# Read in the standard defs file
-if {![gdbtk_read_defs]} {
-  break
-}
-
-global objdir test_ran
-
-# Load in a file
-set program [file join $objdir c_variable]
-if {[catch {gdbtk_test_file $program} t]} {
-  # This isn't a test case, since if this fails, we're hosed.
-  gdbtk_test_error "loading \"$program\": $t"
-}
-
-# The variables that are created are stored in an array called "var".
-
-# proc to tell us which of the variables are changed/out of scope
-proc check_update {} {
-  global var
-
-  set out {}
-  set changed {}
-  foreach ind [array names var] {
-    set ret [$var($ind) update]
-    if {$ret == -1} {
-       lappend out $ind
-    } elseif {$ret != ""} {
-        lappend changed $ret
-    }
-  }
-  return [list $changed $out]
-}
-
-# proc to create a variable
-proc create_variable {expr} {
-  global var
-
-  set err [catch {gdb_variable create "$expr" -expr $expr} v]
-  if {!$err} {
-    set var($expr) $v
-  }
-
-  return $err
-}
-
-# proc to get the children
-# Children are stored in the global "var" as
-# PARENT.child. So for struct _foo {int a; int b} bar;,
-# the children returned are {a b} and var(bar.a) and var(bar.b)
-# map the actual objects to their names.
-proc get_children {parent} {
-  global var
-
-  set kiddies [$var($parent) children]
-  set children {}
-  foreach child $kiddies {
-    set name [lindex [split $child .] end]
-    lappend children $name
-    set var($parent.$name) $child
-  }
-
-  return $children
-}
-
-proc delete_variable {varname} {
-  global var
-
-  if {[info exists var($varname)]} {
-    # This has to be caught, since deleting a parent
-    # will erase all children.
-    $var($varname) delete
-    set vars [array names var $varname*]
-    foreach v $vars {
-      if {[info exists var($v)]} {
-       unset var($v)
-      }
-    }
-  }
-}
-
-# Compare the values of variable V in format FMT
-# with gdb's value.
-proc value {v fmt} {
-  global var
-  global _test
-
-  set value [$var($v) value]
-  set gdb [gdb_cmd "output/$fmt $v"]
-  if {$value == $gdb} {
-    set result ok
-  } else {
-    set result $v
-    puts $_test(logfile) "output/$fmt $v"
-    puts $_test(logfile) "gdbtk: $value <> gdb: $gdb"
-  }
-
-  return $result
-}
-
-proc delete_all_variables {} {
-  global var
-
-  foreach variable [array names var] {
-    delete_variable $variable
-  }
-}
-
-proc editable_variables {} {
-  global var
-
-  set yes {}
-  set no {}
-  foreach name [array names var] {
-    if {[$var($name) editable]} {
-      lappend yes $name
-    } else {
-      lappend no $name
-    }
-  }
-
-  return [list $yes $no]
-}
-
-
-#####                   #####
-#                           #
-#  Variable Creation tests  #
-#                           #
-#####                   #####
-
-# Test:  c_variable-1.1
-# Desc:  Create global variable
-gdbtk_test c_variable-1.1 {create global variable} {
-  create_variable global_simple
-} {0}
-
-# Test: c_variable-1.2
-# Desc: Create non-existent variable
-gdbtk_test c_variable-1.2 {create non-existent variable} {
-  create_variable bogus_unknown_variable
-} {1}
-
-# Test: c_variable-1.3
-# Desc: Create out of scope variable
-gdbtk_test c_variable-1.3 {create out of scope variable} {
-  create_variable argc
-} {1}
-
-# Break in main and run
-gdb_cmd "break do_locals_tests"
-gdbtk_test_run
-
-# Test: c_variable-1.4
-# Desc: create local variables
-gdbtk_test c_variable-1.4 {create local variables} {
-  set results {}
-  foreach v {linteger lpinteger lcharacter lpcharacter llong lplong lfloat lpfloat ldouble lpdouble lsimple lpsimple func} {
-    lappend results [create_variable $v]
-  }
-  set results
-} {0 0 0 0 0 0 0 0 0 0 0 0 0}
-
-# Test: c_variable-1.5
-# Desc: create lsimple.character
-gdbtk_test c_variable-1.5 {create lsimple.character} {
-  create_variable lsimple.character
-} {0}
-
-# Test: c_variable-1.6
-# Desc: create lpsimple->integer
-gdbtk_test c_variable-1.6 {create lpsimple->integer} {
-  create_variable lpsimple->integer
-} {0}
-
-# Test: c_variable-1.7
-# Desc: create lsimple.integer
-gdbtk_test c_variable-1.7 {create lsimple.integer} {
-  create_variable lsimple.integer
-} {0}
-
-# Test: c_variable-1.8
-# Desc: names of editable variables
-gdbtk_test c_variable-1.8 {names of editable variables} {
-  editable_variables
-} {{lsimple.character lsimple.integer lpsimple lcharacter lpcharacter linteger lpinteger lfloat lpfloat func llong lplong lpsimple->integer ldouble lpdouble} {lsimple global_simple}}
-
-# Test: c_variable-1.9
-# Desc: create type name
-#    Type names (like int, long, etc..) are all proper expressions to gdb.
-#    make sure variable code does not allow users to create variables, though.
-gdbtk_test c_variable-1.9 {create type name} {
-  create_variable int
-} {1}
-
-#####             #####
-#                     #
-# Value changed tests #
-#                     #
-#####             #####
-
-# Test: c_variable-2.1
-# Desc: check whether values changed at do_block_tests
-gdbtk_test c_variable-2.1 {check whether values changed at do_block_tests} {
-  check_update
-} {{} {}}
-
-# Step over "linteger = 1234;"
-gdb_cmd "step"
-
-# Test: c_variable-2.2
-# Desc: check whether only linteger changed values
-gdbtk_test c_variable-2.2 {check whether only linteger changed values} {
-  check_update
-} {linteger {}}
-
-# Step over "lpinteger = &linteger;"
-gdb_cmd "step"
-
-# Test: c_variable-2.3
-# Desc: check whether only lpinteger changed
-gdbtk_test c_variable-2.3 {check whether only lpinteger changed} {
-  check_update
-} {lpinteger {}}
-
-# Step over "lcharacter = 'a';"
-gdb_cmd "step"
-
-# Test: c_variable-2.4
-# Desc: check whether only lcharacter changed
-gdbtk_test c_variable-2.4 {check whether only lcharacter changed} {
-  check_update
-} {lcharacter {}}
-
-# Step over "lpcharacter = &lcharacter;"
-gdb_cmd "step"
-
-# Test: c_variable-2.5
-# Desc: check whether only lpcharacter changed
-gdbtk_test c_variable-2.5 {check whether only lpcharacter changed} {
-  check_update
-} {lpcharacter {}}
-
-# Step over:
-#  llong = 2121L;
-#  lplong = &llong;
-#  lfloat = 2.1;
-#  lpfloat = &lfloat;
-#  ldouble = 2.718281828459045;
-#  lpdouble = &ldouble;
-#  lsimple.integer = 1234;
-#  lsimple.unsigned_integer = 255;
-#  lsimple.character = 'a';
-for {set i 0} {$i < 9} {incr i} {
-  gdb_cmd "step"
-}
-
-# Test: c_variable-2.6
-# Desc: check whether llong, lplong, lfloat, lpfloat, ldouble, lpdouble, lsimple.integer,
-#       lsimple.unsigned_character lsimple.integer lsimple.character changed
-gdbtk_test c_variable-2.6 {check whether llong -- lsimple.character changed} {
-  check_update
-} {{lsimple.character lsimple.integer lfloat lpfloat llong lplong ldouble lpdouble} {}}
-
-# Step over:
-#  lsimple.signed_character = 21;
-#  lsimple.char_ptr = &lcharacter;
-#  lpsimple = &lsimple;
-#  func = nothing;
-for {set i 0} {$i < 4} {incr i} {
-  gdb_cmd "step"
-}
-
-# Test: c_variable-2.7
-# Desc: check whether lsimple.signed_character, lsimple.char_ptr, lpsimple, func changed
-gdbtk_test c_variable-2.7 {check whether lsimple.signed_character, lsimple.char_ptr, lpsimple, func changed} {
-  check_update
-} {{lpsimple func lpsimple->integer} {}}
-
-# Step over
-#  linteger = 4321;
-#  lcharacter = 'b';
-#  llong = 1212L;
-#  lfloat = 1.2;
-#  ldouble = 5.498548281828172;
-#  lsimple.integer = 255;
-#  lsimple.unsigned_integer = 4321;
-#  lsimple.character = 'b';
-for {set i 0} {$i < 8} {incr i} {
-  gdb_cmd "step"
-}
-
-# Test: c_variable-2.8
-# Desc: check whether linteger, lcharacter, llong, lfoat, ldouble, lsimple.integer,
-#       lpsimple.integer lsimple.character changed
-# Note: this test also checks that lpsimple->integer and lsimple.integer have
-#       changed (they are the same)
-gdbtk_test c_variable-2.8 {check whether linteger -- lsimple.integer changed} {
-  check_update
-} {{lsimple.character lsimple.integer lcharacter linteger lfloat llong lpsimple->integer ldouble} {}}
-
-gdb_cmd "break subroutine1"
-gdb_cmd "continue"
-
-# Test: c_variable-2.9
-# Desc: stop in subroutine1
-gdbtk_test c_variable-2.9 {stop in subroutine1} {
-  lindex [gdb_loc] 1
-} {subroutine1}
-
-# Test: c_variable-2.10
-# Desc: create variable for locals i,l in subroutine1
-gdbtk_test c_variable-2.10 {create variable for locals i,l in subroutine1} {
-  set r [create_variable i]
-  lappend r [create_variable l]  
-} {0 0}
-
-# Test: c_variable-2.11
-# Desc: create do_locals_tests local in subroutine1
-gdbtk_test c_variable-2.11 {create do_locals_tests local in subroutine1} {
-  create_variable linteger
-} {1}
-
-# Step over
-#  global_simple.integer = i + 3;
-gdb_cmd "step"
-
-# Test: c_variable-2.12
-# Desc: change global_simple.integer
-# Note: This also tests whether we are reporting changes in structs properly.
-#       gdb normally would say that global_simple has changed, but we
-#       special case that, since it is not what a human expects to see.
-gdbtk_test c_variable-2.12 {change global_simple.integer} {
-  check_update
-} {{} {lsimple.character lsimple.integer lpsimple lsimple lcharacter lpcharacter linteger lpinteger lfloat lpfloat func llong lplong lpsimple->integer ldouble lpdouble}}
-
-# Step over
-#  i = 212;
-gdb_cmd "step"
-
-# Test: c_variable-2.13
-# Desc: change subroutine1 local i
-gdbtk_test c_variable-2.13 {change subroutine1 local i} {
-  check_update
-} {i {lsimple.character lsimple.integer lpsimple lsimple lcharacter lpcharacter linteger lpinteger lfloat lpfloat func llong lplong lpsimple->integer ldouble lpdouble}}
-
-# Step over
-#  *l = 12
-gdb_cmd "step"
-
-# This test is no longer valid, since varobj now forces
-# re-evaluation in the current frame by default.
-# Test: c_variable-2.14
-# Desc: change do_locals_tests local llong
-#gdbtk_test c_variable-2.14 {change do_locals_tests local llong} {
-#  check_update
-#} {llong {}}
-
-# Leave subroutine1
-gdb_cmd "next"
-
-# Test: c_variable-2.15
-# Desc: check for out of scope subroutine1 locals
-gdbtk_test c_variable-2.15 {check for out of scope subroutine1 locals} {
-  lindex [check_update] 1
-} {i l}
-
-# Test: c_variable-2.16
-# Desc: names of all editable variables
-gdbtk_test c_variable-2.16 {names of all editable variables} {
-  editable_variables
-} {{lsimple.character lsimple.integer lpsimple i lcharacter lpcharacter linteger lpinteger lfloat lpfloat l func llong lplong lpsimple->integer ldouble lpdouble} {lsimple global_simple}}
-
-# Done with locals/globals tests. Erase all variables
-delete_all_variables
-
-#####     #####
-#             #
-# Block tests #
-#             #
-#####     #####
-gdb_cmd "break do_block_tests"
-gdb_cmd "continue"
-
-# Test: c_variable-3.1
-# Desc: stop in do_block_tests
-gdbtk_test c_variable-3.1 {stop in do_block_tests} {
-  lindex [gdb_loc] 1
-} {do_block_tests}
-
-# Test: c_variable-3.2
-# Desc: create cb and foo
-gdbtk_test c_variable-3.2 {create cb and foo} {
-  set r [create_variable cb]
-  lappend r [create_variable foo]
-} {0 1}
-
-# step to "foo = 123;"
-gdb_cmd "step"
-
-# Be paranoid and assume 3.2 created foo
-delete_variable foo
-
-# Test: c_variable-3.3
-# Desc: create foo
-gdbtk_test c_variable-3.3 {create foo} {
-  create_variable foo
-} {0}
-
-# step to "foo2 = 123;"
-gdb_cmd "step"
-
-# Test: c_variable-3.4
-# Desc: check foo, cb changed
-gdbtk_test c_variable-3.4 {check foo,cb changed} {
-  check_update
-} {{foo cb} {}}
-
-# step to "foo = 321;"
-gdb_cmd "step"
-
-# Test: c_variable-3.5
-# Desc: create inner block foo
-gdbtk_test c_variable-3.5 {create inner block foo} {
-  global var
-  set err [catch {gdb_variable create inner_foo -expr foo} v]
-  if {!$err} {
-    set var(inner_foo) $v
-  }
-  
-  set err
-} {0}
-
-# step to "foo2 = 0;"
-gdb_cmd "step"
-
-# Test: c_variable-3.6
-# Desc: create foo2
-gdbtk_test c_variable-3.6 {create foo2} { 
-  create_variable foo2
-} {0}
-
-# Test: c_variable-3.7
-# Desc: check that outer foo in scope and inner foo out of scope
-
-# Disabled for now because varobjs don't work this way.  If you create a varobj named "foo"
-# it will display the correct value for any variable named "foo" in scope. So inner_foo 
-# is not out of scope because there is another variable named "foo" in scope. It is
-# instead marked as changed.
-
-#gdbtk_test *c_variable-3.7 {check that outer foo in scope and inner foo out of scope} {
-#  check_update
-#} {{} inner_foo}
-
-delete_variable inner_foo
-
-# step to "foo = 0;"
-gdb_cmd "step"
-
-# Test: c_variable-3.8
-# Desc: check that foo2 out of scope
-gdbtk_test c_variable-3.8 {check that foo2 out of scope} {
-  check_update
-} {{} foo2}
-
-# step to "cb = 21;"
-gdb_cmd "step"
-
-# Test: c_variable-3.9
-# Desc: check that only cb is in scope
-gdbtk_test c_variable-3.9 {check that only cb is in scope} {
-  check_update
-} {{} {foo foo2}}
-
-# Test: c_variable-3.10
-# Desc: names of editable variables
-gdbtk_test c_variable-3.10 {names of editable variables} {
-  editable_variables
-} {{foo cb foo2} {}}
-
-# Done with block tests
-delete_all_variables
-
-#####        #####
-#                #
-# children tests #
-#                #
-#####        #####
-
-gdb_cmd "break do_children_tests"
-gdb_cmd "continue"
-
-# Test: c_variable-4.1
-# Desc: stopped in do_children_tests
-gdbtk_test c_variable-4.1 {stopped in do_children_tests} {
-  lindex [gdb_loc] 1
-} {do_children_tests}
-
-# Test: c_variable-4.2
-# Desc: create variable "struct_declarations"
-gdbtk_test c_variable-4.2 {create variable "struct_declarations"} {
-  create_variable struct_declarations
-} {0}
-
-# Test: c_variable-4.3
-# Desc: children of struct_declarations
-gdbtk_test c_variable-4.3 {children of struct_declarations} {
-  get_children  struct_declarations
-} {integer character char_ptr long_int int_ptr_ptr long_array func_ptr func_ptr_struct func_ptr_ptr u1 s2}
-
-# Test: c_variable-4.4
-# Desc: number of children of struct_declarations
-gdbtk_test c_variable-4.4 {number of children of struct_declarations} {
-  $var(struct_declarations) numChildren
-} {11}
-
-# Test: c_variable-4.5
-# Desc: children of struct_declarations.integer
-gdbtk_test c_variable-4.5 {children of struct_declarations.integer} {
-  get_children struct_declarations.integer
-} {}
-
-# Test: c_variable-4.6
-# Desc: number of children of struct_declarations.integer
-gdbtk_test c_variable-4.6 {number of children of struct_declarations.integer} {
-  $var(struct_declarations.integer) numChildren
-} {0}
-
-# Test: c_variable-4.7
-# Desc: children of struct_declarations.character
-gdbtk_test c_variable-4.7 {children of struct_declarations.character} {
-  get_children struct_declarations.character
-} {}
-
-# Test: c_variable-4.8
-# Desc: number of children of struct_declarations.character
-gdbtk_test c_variable-4.8 {number of children of struct_declarations.character} {
-  $var(struct_declarations.character) numChildren
-} {0}
-
-# Test: c_variable-4.9
-# Desc: children of struct_declarations.char_ptr
-gdbtk_test c_variable-4.9 {children of struct_declarations.char_ptr} {
-  get_children struct_declarations.char_ptr
-} {*char_ptr}
-
-# Test: c_variable-4.10
-# Desc: number of children of struct_declarations.char_ptr
-gdbtk_test c_variable-4.10 {number of children of struct_declarations.char_ptr} {
-  $var(struct_declarations.char_ptr) numChildren
-} {1}
-
-# Test: c_variable-4.11
-# Desc: children of struct_declarations.long_int
-gdbtk_test c_variable-4.11 {children of struct_declarations.long_int} {
-
-  get_children struct_declarations.long_int
-} {}
-
-# Test: c_variable-4.12
-# Desc: number of children of struct_declarations.long_int
-gdbtk_test c_variable-4.12 {number of children of struct_declarations.long_int} {
-  $var(struct_declarations.long_int) numChildren
-} {0}
-
-# Test: c_variable-4.13
-# Desc: children of int_ptr_ptr
-gdbtk_test c_variable-4.13 {children of int_ptr_ptr} {
-  get_children struct_declarations.int_ptr_ptr
-} {*int_ptr_ptr}
-
-# Test: c_variable-4.14
-# Desc: number of children of int_ptr_ptr
-gdbtk_test c_variable-4.14 {number of children of int_ptr_ptr} {
-  $var(struct_declarations.int_ptr_ptr) numChildren
-} {1}
-
-# Test: c_variable-4.15
-# Desc: children of struct_declarations.long_array
-gdbtk_test c_variable-4.15 {children of struct_declarations.long_array} {
-  get_children struct_declarations.long_array
-} {0 1 2 3 4 5 6 7 8 9}
-
-# Test: c_variable-4.16
-# Desc: number of children of struct_declarations.long_array
-gdbtk_test c_variable-4.16 {number of children of struct_declarations.long_array} {
-  $var(struct_declarations.long_array) numChildren
-} {10}
-
-# Test: c_variable-4.17
-# Desc: children of struct_declarations.func_ptr
-gdbtk_test c_variable-4.17 {children of struct_declarations.func_ptr} {
-  get_children struct_declarations.func_ptr
-} {}
-
-# Test: c_variable-4.18
-# Desc: number of children of struct_declarations.func_ptr
-gdbtk_test c_variable-4.18 {number of children of struct_declarations.func_ptr} {
-  $var(struct_declarations.func_ptr) numChildren
-} {0}
-
-# Test: c_variable-4.19
-# Desc: children of struct_declarations.func_ptr_struct
-gdbtk_test c_variable-4.19 {children of struct_declarations.func_ptr_struct} {
-  get_children struct_declarations.func_ptr_struct
-} {}
-
-# Test: c_variable-4.20
-# Desc: number of children of struct_declarations.func_ptr_struct
-gdbtk_test c_variable-4.20 {number of children of struct_declarations.func_ptr_struct} {
-  $var(struct_declarations.func_ptr_struct) numChildren
-} {0}
-
-# Test: c_variable-4.21
-# Desc: children of struct_declarations.func_ptr_ptr
-gdbtk_test c_variable-4.21 {children of struct_declarations.func_ptr_ptr} {
-  get_children struct_declarations.func_ptr_ptr
-} {}
-
-# Test: c_variable-4.22
-# Desc: number of children of struct_declarations.func_ptr_ptr
-gdbtk_test c_variable-4.22 {number of children of struct_declarations.func_ptr_ptr} {
-  $var(struct_declarations.func_ptr_ptr) numChildren
-} {0}
-
-# Test: c_variable-4.23
-# Desc: children of struct_declarations.u1
-gdbtk_test c_variable-4.23 {children of struct_declarations.u1} {
-  get_children struct_declarations.u1
-} {a b c d}
-
-# Test: c_variable-4.24
-# Desc: number of children of struct_declarations.u1
-gdbtk_test c_variable-4.24 {number of children of struct_declarations.u1} {
-  $var(struct_declarations.u1) numChildren
-} {4}
-
-# Test: c_variable-4.25
-# Desc: children of struct_declarations.s2
-gdbtk_test c_variable-4.25 {children of struct_declarations.s2} {
-  get_children struct_declarations.s2
-} {u2 g h i}
-
-# Test: c_variable-4.26
-# Desc: number of children of struct_declarations.s2
-gdbtk_test c_variable-4.26 {number of children of struct_declarations.s2} {
-  $var(struct_declarations.s2) numChildren
-} {4}
-
-# Test: c_variable-4.27
-# Desc: children of struct_declarations.long_array.1
-gdbtk_test c_variable-4.27 {children of struct_declarations.long_array.1} {
-  get_children struct_declarations.long_array.1
-} {}
-
-# Test: c_variable-4.28
-# Desc: number of children of struct_declarations.long_array.1
-gdbtk_test c_variable-4.28 {number of children of struct_declarations.long_array.1} {
-  $var(struct_declarations.long_array.1) numChildren
-} {0}
-
-# Test: c_variable-4.29
-# Desc: children of struct_declarations.long_array.2
-gdbtk_test c_variable-4.29 {children of struct_declarations.long_array.2} {
-  get_children struct_declarations.long_array.2
-} {}
-
-# Test: c_variable-4.30
-# Desc: number of children of struct_declarations.long_array.2
-gdbtk_test c_variable-4.30 {number of children of struct_declarations.long_array.2} {
-  $var(struct_declarations.long_array.2) numChildren
-} {0}
-
-# Test: c_variable-4.31
-# Desc: children of struct_declarations.long_array.3
-gdbtk_test c_variable-4.31 {children of struct_declarations.long_array.3} {
-  get_children struct_declarations.long_array.3
-} {}
-
-# Test: c_variable-4.32
-# Desc: number of children of struct_declarations.long_array.3
-gdbtk_test c_variable-4.32 {number of children of struct_declarations.long_array.3} {
-  $var(struct_declarations.long_array.3) numChildren
-} {0}
-
-# Test: c_variable-4.33 
-# Desc: children of struct_declarations.long_array.4
-gdbtk_test c_variable-4.33 {children of struct_declarations.long_array.4} {
-  get_children struct_declarations.long_array.4
-} {}
-
-# Test: c_variable-4.34
-# Desc: number of children of struct_declarations.long_array.4
-gdbtk_test c_variable-4.34 {number of children of struct_declarations.long_array.4} {
-  $var(struct_declarations.long_array.4) numChildren
-} {0}
-
-# Test: c_variable-4.35
-# Desc: children of struct_declarations.long_array.5
-gdbtk_test c_variable-4.35 {children of struct_declarations.long_array.5} {
-  get_children struct_declarations.long_array.5
-} {}
-
-# Test: c_variable-4.36
-# Desc: number of children of struct_declarations.long_array.5
-gdbtk_test c_variable-4.36 {number of children of struct_declarations.long_array.5} {
-  $var(struct_declarations.long_array.5) numChildren
-} {0}
-
-# Test: c_variable-4.37
-# Desc: children of struct_declarations.long_array.6
-gdbtk_test c_variable-4.37 {children of struct_declarations.long_array.6} {
-  get_children struct_declarations.long_array.6
-} {}
-
-# Test: c_variable-4.38
-# Desc: number of children of struct_declarations.long_array.6
-gdbtk_test c_variable-4.38 {number of children of struct_declarations.long_array.6} {
-  $var(struct_declarations.long_array.6) numChildren
-} {0}
-
-# Test: c_variable-4.39
-# Desc: children of struct_declarations.long_array.7
-gdbtk_test c_variable-4.39 {children of struct_declarations.long_array.7} {
-  get_children struct_declarations.long_array.7
-} {}
-
-# Test: c_variable-4.40
-# Desc: number of children of struct_declarations.long_array.7
-gdbtk_test c_variable-4.40 {number of children of struct_declarations.long_array.7} {
-  $var(struct_declarations.long_array.7) numChildren
-} {0}
-
-# Test: c_variable-4.41
-# Desc: children of struct_declarations.long_array.8
-gdbtk_test c_variable-4.41 {children of struct_declarations.long_array.8} {
-  get_children struct_declarations.long_array.8
-} {}
-
-# Test: c_variable-4.42
-# Desc: number of children of struct_declarations.long_array.8
-gdbtk_test c_variable-4.42 {number of children of struct_declarations.long_array.8} {
-  $var(struct_declarations.long_array.8) numChildren
-} {0}
-
-# Test: c_variable-4.43
-# Desc: children of struct_declarations.long_array.9
-gdbtk_test c_variable-4.43 {children of struct_declarations.long_array.9} {
-  get_children struct_declarations.long_array.9
-} {}
-
-# Test: c_variable-4.44
-# Desc: number of children of struct_declarations.long_array.9
-gdbtk_test c_variable-4.44 {number of children of struct_declarations.long_array.9} {
-  $var(struct_declarations.long_array.9) numChildren
-} {0}
-
-# Test: c_variable-4.45
-# Desc: children of struct_declarations.u1.a
-gdbtk_test c_variable-4.45 {children of struct_declarations.u1.a} {
-  get_children struct_declarations.u1.a
-} {}
-
-# Test: c_variable-4.46
-# Desc: number of children of struct_declarations.u1.a
-gdbtk_test c_variable-4.46 {number of children of struct_declarations.u1.a} {
-  $var(struct_declarations.u1.a) numChildren
-} {0}
-
-# Test: c_variable-4.47
-# Desc: children of struct_declarations.u1.b
-gdbtk_test c_variable-4.47 {children of struct_declarations.u1.b} {
-  get_children struct_declarations.u1.b
-} {*b}
-
-# Test: c_variable-4.48
-# Desc: number of children of struct_declarations.u1.b
-gdbtk_test c_variable-4.48 {number of children of struct_declarations.u1.b} {
-  $var(struct_declarations.u1.b) numChildren
-} {1}
-
-# Test: c_variable-4.49
-# Desc: children of struct_declarations.u1.c
-gdbtk_test c_variable-4.49 {children of struct_declarations.u1.c} {
-  get_children struct_declarations.u1.c
-} {}
-
-# Test: c_variable-4.50
-# Desc: number of children of struct_declarations.u1.c
-gdbtk_test c_variable-4.50 {number of children of struct_declarations.u1.c} {
-  $var(struct_declarations.u1.c) numChildren
-} {0}
-
-# Test: c_variable-4.51
-# Desc: children of struct_declarations.u1.d
-gdbtk_test c_variable-4.51 {children of struct_declarations.u1.d} {
-  get_children struct_declarations.u1.d
-} {}
-
-# Test: c_variable-4.52
-# Desc: number of children of struct_declarations.u1.d
-gdbtk_test c_variable-4.52 {number of children of struct_declarations.u1.d} {
-  $var(struct_declarations.u1.d) numChildren
-} {0}
-
-# Test: c_variable-4.53
-# Desc: children of struct_declarations.s2.u2
-gdbtk_test c_variable-4.53 {children of struct_declarations.s2.u2} {
-  get_children struct_declarations.s2.u2
-} {u1s1 f u1s2}
-
-# Test: c_variable-4.54
-# Desc: number of children of struct_declarations.s2.u2
-gdbtk_test c_variable-4.54 {number of children of struct_declarations.s2.u2} {
-  $var(struct_declarations.s2.u2) numChildren
-} {3}
-
-# Test: c_variable-4.55
-# Desc: children of struct_declarations.s2.g
-gdbtk_test c_variable-4.55 {children of struct_declarations.s2.g} {
-  get_children struct_declarations.s2.g
-} {}
-
-# Test: c_variable-4.56
-# Desc: number of children of struct_declarations.s2.g
-gdbtk_test c_variable-4.56 {number of children of struct_declarations.s2.g} {
-  $var(struct_declarations.s2.g) numChildren
-} {0}
-
-# Test: c_variable-4.57
-# Desc: children of struct_declarations.s2.h
-gdbtk_test c_variable-4.57 {children of struct_declarations.s2.h} {
-  get_children struct_declarations.s2.h
-} {}
-
-# Test: c_variable-4.58
-# Desc: number of children of struct_declarations.s2.h
-gdbtk_test c_variable-4.58 {number of children of struct_declarations.s2.h} {
-  $var(struct_declarations.s2.h) numChildren
-} {0}
-
-# Test: c_variable-4.59
-# Desc: children of struct_declarations.s2.i
-gdbtk_test c_variable-4.59 {children of struct_declarations.s2.i} {
-  get_children struct_declarations.s2.i
-} {0 1 2 3 4 5 6 7 8 9}
-
-# Test: c_variable-4.60
-# Desc: number of children of struct_declarations.s2.i
-gdbtk_test c_variable-4.60 {number of children of struct_declarations.s2.i} {
-  $var(struct_declarations.s2.i) numChildren
-} {10}
-
-# Test: c_variable-4.61
-# Desc: children of struct_declarations.s2.u2.u1s1
-gdbtk_test c_variable-4.61 {children of struct_declarations.s2.u2.u1s1} {
-  get_children struct_declarations.s2.u2.u1s1
-} {d e func foo}
-
-# Test: c_variable-4.62
-# Desc: number of children of struct_declarations.s2.u2.u1s1
-gdbtk_test c_variable-4.62 {number of children of struct_declarations.s2.u2.u1s1} {
-  $var(struct_declarations.s2.u2.u1s1) numChildren
-} {4}
-
-# Test: c_variable-4.63
-# Desc: children of struct_declarations.s2.u2.f
-gdbtk_test c_variable-4.63 {children of struct_declarations.s2.u2.f} {
-  get_children struct_declarations.s2.u2.f
-} {}
-
-# Test: c_variable-4.64
-# Desc: number of children of struct_declarations.s2.u2.f
-gdbtk_test c_variable-4.64 {number of children of struct_declarations.s2.u2.f} {
-  $var(struct_declarations.s2.u2.f) numChildren
-} {0}
-
-# Test: c_variable-4.65
-# Desc: children of struct_declarations.s2.u2.u1s2
-gdbtk_test c_variable-4.65 {children of struct_declarations.s2.u2.u1s2} {
-  get_children struct_declarations.s2.u2.u1s2
-} {array_ptr func}
-
-# Test: c_variable-4.66
-# Desc: number of children of struct_declarations.s2.u2.u1s2
-gdbtk_test c_variable-4.66 {number of children of struct_declarations.s2.u2.u1s2} {
-  $var(struct_declarations.s2.u2.u1s2) numChildren
-} {2}
-
-# Test: c_variable-4.67
-# Desc: children of struct_declarations.s2.u2.u1s1.d
-gdbtk_test c_variable-4.67 {children of struct_declarations.s2.u2.u1s1.d} {
-  get_children struct_declarations.s2.u2.u1s1.d
-} {}
-
-# Test: c_variable-4.68
-# Desc: number of children of struct_declarations.s2.u2.u1s1.d
-gdbtk_test c_variable-4.68 {number of children of struct_declarations.s2.u2.u1s1.d} {
-  $var(struct_declarations.s2.u2.u1s1.d) numChildren
-} {0}
-
-# Test: c_variable-4.69
-# Desc: children of struct_declarations.s2.u2.u1s1.e
-gdbtk_test c_variable-4.69 {children of struct_declarations.s2.u2.u1s1.e} {
-  get_children struct_declarations.s2.u2.u1s1.e
-} {0 1 2 3 4 5 6 7 8 9}
-
-# Test: c_variable-4.70
-# Desc: number of children of struct_declarations.s2.u2.u1s1.e
-gdbtk_test c_variable-4.70 {number of children of struct_declarations.s2.u2.u1s1.e} {
-  $var(struct_declarations.s2.u2.u1s1.e) numChildren
-} {10}
-
-# Test: c_variable-4.71
-# Desc: children of struct_declarations.s2.u2.u1s1.func
-gdbtk_test c_variable-4.71 {children of struct_declarations.s2.u2.u1s1.func} {
-  get_children struct_declarations.s2.u2.u1s1.func
-} {}
-
-# Test: c_variable-4.72
-# Desc: number of children of struct_declarations.s2.u2.u1s1.func
-gdbtk_test c_variable-4.72 {number of children of struct_declarations.s2.u2.u1s1.func} {
-  $var(struct_declarations.s2.u2.u1s1.func) numChildren
-} {0}
-
-# Test: c_variable-4.73
-# Desc: children of struct_declarations.s2.u2.u1s1.foo
-gdbtk_test c_variable-4.73 {children of struct_declarations.s2.u2.u1s1.foo} {
-  get_children struct_declarations.s2.u2.u1s1.foo
-} {}
-
-# Test: c_variable-4.74
-# Desc: number of children of struct_declarations.s2.u2.u1s1.foo
-gdbtk_test c_variable-4.74 {number of children of struct_declarations.s2.u2.u1s1.foo} {
-  $var(struct_declarations.s2.u2.u1s1.foo) numChildren
-} {0}
-
-# Test: c_variable-4.75
-# Desc: children of struct_declarations.s2.u2.u1s2.array_ptr
-gdbtk_test c_variable-4.75 {children of struct_declarations.s2.u2.u1s2.array_ptr} {
-  get_children struct_declarations.s2.u2.u1s2.array_ptr
-} {0 1}
-
-# Test: c_variable-4.76
-# Desc: number of children of struct_declarations.s2.u2.u1s2.array_ptr
-gdbtk_test c_variable-4.76 {number of children of struct_declarations.s2.u2.u1s2.array_ptr} {
-  $var(struct_declarations.s2.u2.u1s2.array_ptr) numChildren
-} {2}
-
-# Test: c_variable-4.77
-# Desc: children of struct_declarations.s2.u2.u1s2.func
-gdbtk_test c_variable-4.77 {children of struct_declarations.s2.u2.u1s2.func} {
-  get_children struct_declarations.s2.u2.u1s2.func
-} {}
-
-# Test: c_variable-4.78
-# Desc: number of children of struct_declarations.s2.u2.u1s2.func
-gdbtk_test c_variable-4.78 {number of children of struct_declarations.s2.u2.u1s2.func} {
-  $var(struct_declarations.s2.u2.u1s2.func) numChildren
-} {0}
-
-# Test: c_variable-4.79
-# Desc: children of struct_declarations.*int_ptr_ptr
-gdbtk_test c_variable-4.79 {children of struct_declarations.*int_ptr_ptr} {
-  get_children struct_declarations.int_ptr_ptr.*int_ptr_ptr
-} {**int_ptr_ptr}
-
-# Test: c_variable-4.80
-# Desc: Number of children of struct_declarations.*int_ptr_ptr
-gdbtk_test c_variable-4.80 {Number of children of struct_declarations.*int_ptr_ptr} {
-  $var(struct_declarations.int_ptr_ptr.*int_ptr_ptr) numChildren
-} {1}
-
-# Step to "struct_declarations.integer = 123;"
-gdb_cmd "step"
-
-# Test: c_variable-4.81
-# Desc: create local variable "weird"
-gdbtk_test c_variable-4.81 {create local variable "weird"} {
-  create_variable weird
-} {0}
-
-# Test: c_variable-4.82
-# Desc: children of weird
-gdbtk_test c_variable-4.82 {children of weird} {
-  get_children weird
-} {integer character char_ptr long_int int_ptr_ptr long_array func_ptr func_ptr_struct func_ptr_ptr u1 s2}
-
-# Test: c_variable-4.83
-# Desc: number of children of weird
-gdbtk_test c_variable-4.83 {number of children of weird} {
-  $var(weird) numChildren
-} {11}
-
-# Test: c_variable-4.84
-# Desc: children of weird->long_array
-gdbtk_test c_variable-4.84 {children of weird->long_array} {
-  get_children weird.long_array
-} {0 1 2 3 4 5 6 7 8 9}
-
-# Test: c_variable-4.85
-# Desc: number of children of weird->long_array
-gdbtk_test c_variable-4.85 {number of children of weird->long_array} {
-  $var(weird.long_array) numChildren
-} {10}
-
-# Test: c_variable-4.86
-# Desc: children of weird->int_ptr_ptr
-gdbtk_test c_variable-4.86 {children of weird->int_ptr_ptr} {
-  get_children weird.int_ptr_ptr
-} {*int_ptr_ptr}
-
-# Test: c_variable-4.87
-# Desc: number of children of weird->int_ptr_ptr
-gdbtk_test c_variable-4.87 {number of children of weird->int_ptr_ptr} {
-  $var(weird.int_ptr_ptr) numChildren
-} {1}
-
-# Test: c_variable-4.88
-# Desc: children of *weird->int_ptr_ptr
-gdbtk_test c_variable-4.88 {children of *weird->int_ptr_ptr} {
-  get_children weird.int_ptr_ptr.*int_ptr_ptr
-} {**int_ptr_ptr}
-
-# Test: c_variable-4.89
-# Desc: number of children *weird->int_ptr_ptr
-gdbtk_test c_variable-4.89 {number of children *weird->int_ptr_ptr} {
-  $var(weird.int_ptr_ptr.*int_ptr_ptr) numChildren
-} {1}
-
-# Test: c_variable-4.90
-# Desc: create weird->int_ptr_ptr
-gdbtk_test c_variable-4.90 {create weird->int_ptr_ptr} {
-  create_variable weird->int_ptr_ptr
-} {0}
-
-# Test: c_variable-4.91
-# Desc: children of weird->int_ptr_ptr
-gdbtk_test c_variable-4.91 {children of weird->int_ptr_ptr} {
-  get_children weird->int_ptr_ptr
-} {*weird->int_ptr_ptr}
-
-# Test: c_variable-4.92
-# Desc: number of children of (weird->int_ptr_ptr)
-gdbtk_test c_variable-4.92 {number of children of (weird->int_ptr_ptr)} {
-  $var(weird->int_ptr_ptr) numChildren
-} {1}
-
-# Test: c_variable-4.93
-# Desc: children of *(weird->int_ptr_ptr)
-gdbtk_test c_variable-4.93 {children of *(weird->int_ptr_ptr)} {
-  get_children weird->int_ptr_ptr.*weird->int_ptr_ptr
-} {**weird->int_ptr_ptr}
-
-# Test: c_variable-4.94
-# Desc: number of children of *(weird->int_ptr_ptr)
-gdbtk_test c_variable-4.94 {number of children of *(weird->int_ptr_ptr)} {
-  $var(weird->int_ptr_ptr.*weird->int_ptr_ptr) numChildren
-} {1}
-
-# Test: c_variable-4.95
-# Desc: children of *(*(weird->int_ptr_ptr))
-gdbtk_test c_variable-4.95 {children of *(*(weird->int_ptr_ptr))} {
-  get_children weird->int_ptr_ptr.*weird->int_ptr_ptr.**weird->int_ptr_ptr
-} {}
-
-# Test: c_variable-4.96
-# Desc: number of children of *(*(weird->int_ptr_ptr))
-gdbtk_test c_variable-4.96 {number of children of **weird->int_ptr_ptr} {
-  $var(weird->int_ptr_ptr.*weird->int_ptr_ptr.**weird->int_ptr_ptr) numChildren
-} {0}
-
-# Test: c_variable-4.97
-# Desc: is weird editable
-gdbtk_test c_variable-4.97 {is weird editable} {
-  $var(weird) editable
-} {1}
-
-# Test: c_variable-4.98
-# Desc: is weird->int_ptr_ptr editable
-gdbtk_test c_variable-4.98 {is weird->int_ptr_ptr editable} {
-  $var(weird.int_ptr_ptr) editable
-} {1}
-
-# Test: c_variable-4.99
-# Desc: is *(weird->int_ptr_ptr) editable
-gdbtk_test c_variable-4.99 {is *(weird->int_ptr_ptr) editable} {
-  $var(weird.int_ptr_ptr.*int_ptr_ptr) editable
-} {1}
-
-# Test: c_variable-4.100
-# Desc: is *(*(weird->int_ptr_ptr)) editable
-gdbtk_test c_variable-4.100 {is *(*(weird->int_ptr_ptr)) editable} {
-  $var(weird.int_ptr_ptr.*int_ptr_ptr.**int_ptr_ptr) editable
-} {1}
-
-# Test: c_variable-4.101
-# Desc: is weird->u1 editable
-gdbtk_test c_variable-4.101 {is weird->u1 editable} {
-  $var(weird.u1) editable
-} {0}
-
-# Test: c_variable-4.102
-# Desc: is weird->s2 editable
-gdbtk_test c_variable-4.102 {is weird->s2 editable} {
-  $var(weird.s2) editable
-} {0}
-
-# Test: c_variable-4.103
-# Desc: is struct_declarations.u1.a editable
-gdbtk_test c_variable-4.103 {is struct_declarations.u1.a editable} {
-  $var(struct_declarations.u1.a) editable
-} {1}
-
-# Test: c_variable-4.104
-# Desc: is struct_declarations.u1.b editable
-gdbtk_test c_variable-4.104 {is struct_declarations.u1.b editable} {
-  $var(struct_declarations.u1.b) editable
-} {1}
-
-# Test: c_variable-4.105
-# Desc: is struct_declarations.u1.c editable
-gdbtk_test c_variable-4.105 {is struct_declarations.u1.c editable} {
-  $var(struct_declarations.u1.c) editable
-} {1}
-
-# Test: c_variable-4.106
-# Desc: is struct_declarations.long_array editable
-gdbtk_test c_variable-4.106 {is struct_declarations.long_array editable} {
-  $var(struct_declarations.long_array) editable
-} {0}
-
-# Test: c_variable-4.107
-# Desc: is struct_declarations.long_array[0] editable
-gdbtk_test c_variable-4.107 {is struct_declarations.long_array[0] editable} {
-  $var(struct_declarations.long_array.0) editable
-} {1}
-
-# Test: c_variable-4.108
-# Desc: is struct_declarations editable
-gdbtk_test c_variable-4.108 {is struct_declarations editable} {
-  $var(struct_declarations) editable
-} {0}
-
-delete_variable weird
-
-#####                         #####
-#                                 #
-# children and update tests #
-#                                 #
-#####                         #####
-
-# Test: c_variable-5.1
-# Desc: check that nothing changed
-gdbtk_test c_variable-5.1 {check that nothing changed} {
-  check_update
-} {{} {struct_declarations.s2.i.3 struct_declarations.func_ptr_ptr struct_declarations.s2.i.4 struct_declarations.s2.i.5 struct_declarations.s2.i.6 struct_declarations.func_ptr struct_declarations.s2.i.7 struct_declarations.s2.i.8 struct_declarations.s2.i.9 struct_declarations.s2.u2.u1s1.d struct_declarations.func_ptr_struct struct_declarations.s2.u2.u1s1.e struct_declarations.u1 struct_declarations.char_ptr.*char_ptr struct_declarations.long_int struct_declarations.s2.u2.u1s2.func struct_declarations.integer struct_declarations.s2.u2 struct_declarations.s2.u2.u1s1.e.0 struct_declarations.s2.u2.u1s1.e.1 struct_declarations.long_array.0 struct_declarations.s2.u2.u1s1.e.2 struct_declarations.long_array.1 struct_declarations.u1.a struct_declarations.s2.u2.u1s1.e.3 struct_declarations.long_array.2 struct_declarations.u1.b struct_declarations.s2.u2.u1s1.e.4 struct_declarations.long_array.3 struct_declarations.u1.c struct_declarations.s2.u2.u1s1.e.5 struct_declarations.long_array.4 struct_declarations.u1.d struct_declarations.u1.b.*b struct_declarations.int_ptr_ptr.*int_ptr_ptr.**int_ptr_ptr struct_declarations.s2.u2.u1s1.e.6 struct_declarations.long_array.5 struct_declarations.s2.u2.u1s1.e.7 struct_declarations.long_array.6 struct_declarations.s2.u2.u1s1.e.8 struct_declarations.long_array.7 struct_declarations.s2.u2.u1s1.e.9 struct_declarations.long_array.8 struct_declarations.character struct_declarations.long_array.9 struct_declarations.int_ptr_ptr.*int_ptr_ptr struct_declarations.s2.u2.u1s1.func struct_declarations.s2.u2.u1s2.array_ptr struct_declarations.s2.u2.f struct_declarations.s2.u2.u1s1.foo struct_declarations.s2.u2.u1s1 struct_declarations.s2.u2.u1s2.array_ptr.0 struct_declarations.char_ptr struct_declarations.s2.u2.u1s2 struct_declarations.s2.u2.u1s2.array_ptr.1 struct_declarations.int_ptr_ptr struct_declarations.s2 struct_declarations.long_array struct_declarations.s2.g struct_declarations.s2.i.0 struct_declarations.s2.h struct_declarations.s2.i.1 struct_declarations.s2.i struct_declarations.s2.i.2}}
-
-# Step over "struct_declarations.integer = 123;"
-gdb_cmd "step"
-
-# Test: c_variable-5.2
-# Desc: check that integer changed
-gdbtk_test c_variable-5.2 {check that integer changed} {
-  check_update
-} {struct_declarations.integer {struct_declarations.s2.i.3 struct_declarations.func_ptr_ptr struct_declarations.s2.i.4 struct_declarations.s2.i.5 struct_declarations.s2.i.6 struct_declarations.func_ptr struct_declarations.s2.i.7 struct_declarations.s2.i.8 struct_declarations.s2.i.9 struct_declarations.s2.u2.u1s1.d struct_declarations.func_ptr_struct struct_declarations.s2.u2.u1s1.e struct_declarations.u1 struct_declarations.char_ptr.*char_ptr struct_declarations.long_int struct_declarations.s2.u2.u1s2.func struct_declarations.integer struct_declarations.s2.u2 struct_declarations.s2.u2.u1s1.e.0 struct_declarations.s2.u2.u1s1.e.1 struct_declarations.long_array.0 struct_declarations.s2.u2.u1s1.e.2 struct_declarations.long_array.1 struct_declarations.u1.a struct_declarations.s2.u2.u1s1.e.3 struct_declarations.long_array.2 struct_declarations.u1.b struct_declarations.s2.u2.u1s1.e.4 struct_declarations.long_array.3 struct_declarations.u1.c struct_declarations.s2.u2.u1s1.e.5 struct_declarations.long_array.4 struct_declarations.u1.d struct_declarations.u1.b.*b struct_declarations.int_ptr_ptr.*int_ptr_ptr.**int_ptr_ptr struct_declarations.s2.u2.u1s1.e.6 struct_declarations.long_array.5 struct_declarations.s2.u2.u1s1.e.7 struct_declarations.long_array.6 struct_declarations.s2.u2.u1s1.e.8 struct_declarations.long_array.7 struct_declarations.s2.u2.u1s1.e.9 struct_declarations.long_array.8 struct_declarations.character struct_declarations.long_array.9 struct_declarations.int_ptr_ptr.*int_ptr_ptr struct_declarations.s2.u2.u1s1.func struct_declarations.s2.u2.u1s2.array_ptr struct_declarations.s2.u2.f struct_declarations.s2.u2.u1s1.foo struct_declarations.s2.u2.u1s1 struct_declarations.s2.u2.u1s2.array_ptr.0 struct_declarations.char_ptr struct_declarations.s2.u2.u1s2 struct_declarations.s2.u2.u1s2.array_ptr.1 struct_declarations.int_ptr_ptr struct_declarations.s2 struct_declarations.long_array struct_declarations.s2.g struct_declarations.s2.i.0 struct_declarations.s2.h struct_declarations.s2.i.1 struct_declarations.s2.i struct_declarations.s2.i.2}}
-
-# Step over:
-#    weird->char_ptr = "hello";
-#    bar = 2121;
-#    foo = &bar;
-for {set i 0} {$i < 3} {incr i} {
-  gdb_cmd "step"
-}
-
-# Test: c_variable-5.3
-# Desc: check that char_ptr changed
-gdbtk_test c_variable-5.3 {check that char_ptr changed} {
-  check_update
-} {{{struct_declarations.char_ptr struct_declarations.char_ptr.*char_ptr}} {struct_declarations.s2.i.3 struct_declarations.func_ptr_ptr struct_declarations.s2.i.4 struct_declarations.s2.i.5 struct_declarations.s2.i.6 struct_declarations.func_ptr struct_declarations.s2.i.7 struct_declarations.s2.i.8 struct_declarations.s2.i.9 struct_declarations.s2.u2.u1s1.d struct_declarations.func_ptr_struct struct_declarations.s2.u2.u1s1.e struct_declarations.u1 struct_declarations.char_ptr.*char_ptr struct_declarations.long_int struct_declarations.s2.u2.u1s2.func struct_declarations.integer struct_declarations.s2.u2 struct_declarations.s2.u2.u1s1.e.0 struct_declarations.s2.u2.u1s1.e.1 struct_declarations.long_array.0 struct_declarations.s2.u2.u1s1.e.2 struct_declarations.long_array.1 struct_declarations.u1.a struct_declarations.s2.u2.u1s1.e.3 struct_declarations.long_array.2 struct_declarations.u1.b struct_declarations.s2.u2.u1s1.e.4 struct_declarations.long_array.3 struct_declarations.u1.c struct_declarations.s2.u2.u1s1.e.5 struct_declarations.long_array.4 struct_declarations.u1.d struct_declarations.u1.b.*b struct_declarations.int_ptr_ptr.*int_ptr_ptr.**int_ptr_ptr struct_declarations.s2.u2.u1s1.e.6 struct_declarations.long_array.5 struct_declarations.s2.u2.u1s1.e.7 struct_declarations.long_array.6 struct_declarations.s2.u2.u1s1.e.8 struct_declarations.long_array.7 struct_declarations.s2.u2.u1s1.e.9 struct_declarations.long_array.8 struct_declarations.character struct_declarations.long_array.9 struct_declarations.int_ptr_ptr.*int_ptr_ptr struct_declarations.s2.u2.u1s1.func struct_declarations.s2.u2.u1s2.array_ptr struct_declarations.s2.u2.f struct_declarations.s2.u2.u1s1.foo struct_declarations.s2.u2.u1s1 struct_declarations.s2.u2.u1s2.array_ptr.0 struct_declarations.char_ptr struct_declarations.s2.u2.u1s2 struct_declarations.s2.u2.u1s2.array_ptr.1 struct_declarations.int_ptr_ptr struct_declarations.s2 struct_declarations.long_array struct_declarations.s2.g struct_declarations.s2.i.0 struct_declarations.s2.h struct_declarations.s2.i.1 struct_declarations.s2.i struct_declarations.s2.i.2}}
-
-# Step over "struct_declarations.int_ptr_ptr = &foo;"
-gdb_cmd "step"
-
-# Test: c_variable-5.4
-# Desc: check that int_ptr_ptr and children changed
-gdbtk_test c_variable-5.4 {check that int_ptr_ptr and children changed} {
-  check_update
-} {{{struct_declarations.int_ptr_ptr struct_declarations.int_ptr_ptr.*int_ptr_ptr struct_declarations.int_ptr_ptr.*int_ptr_ptr.**int_ptr_ptr}} {struct_declarations.s2.i.3 struct_declarations.func_ptr_ptr struct_declarations.s2.i.4 struct_declarations.s2.i.5 struct_declarations.s2.i.6 struct_declarations.func_ptr struct_declarations.s2.i.7 struct_declarations.s2.i.8 struct_declarations.s2.i.9 struct_declarations.s2.u2.u1s1.d struct_declarations.func_ptr_struct struct_declarations.s2.u2.u1s1.e struct_declarations.u1 struct_declarations.char_ptr.*char_ptr struct_declarations.long_int struct_declarations.s2.u2.u1s2.func struct_declarations.integer struct_declarations.s2.u2 struct_declarations.s2.u2.u1s1.e.0 struct_declarations.s2.u2.u1s1.e.1 struct_declarations.long_array.0 struct_declarations.s2.u2.u1s1.e.2 struct_declarations.long_array.1 struct_declarations.u1.a struct_declarations.s2.u2.u1s1.e.3 struct_declarations.long_array.2 struct_declarations.u1.b struct_declarations.s2.u2.u1s1.e.4 struct_declarations.long_array.3 struct_declarations.u1.c struct_declarations.s2.u2.u1s1.e.5 struct_declarations.long_array.4 struct_declarations.u1.d struct_declarations.u1.b.*b struct_declarations.int_ptr_ptr.*int_ptr_ptr.**int_ptr_ptr struct_declarations.s2.u2.u1s1.e.6 struct_declarations.long_array.5 struct_declarations.s2.u2.u1s1.e.7 struct_declarations.long_array.6 struct_declarations.s2.u2.u1s1.e.8 struct_declarations.long_array.7 struct_declarations.s2.u2.u1s1.e.9 struct_declarations.long_array.8 struct_declarations.character struct_declarations.long_array.9 struct_declarations.int_ptr_ptr.*int_ptr_ptr struct_declarations.s2.u2.u1s1.func struct_declarations.s2.u2.u1s2.array_ptr struct_declarations.s2.u2.f struct_declarations.s2.u2.u1s1.foo struct_declarations.s2.u2.u1s1 struct_declarations.s2.u2.u1s2.array_ptr.0 struct_declarations.char_ptr struct_declarations.s2.u2.u1s2 struct_declarations.s2.u2.u1s2.array_ptr.1 struct_declarations.int_ptr_ptr struct_declarations.s2 struct_declarations.long_array struct_declarations.s2.g struct_declarations.s2.i.0 struct_declarations.s2.h struct_declarations.s2.i.1 struct_declarations.s2.i struct_declarations.s2.i.2}}
-
-# Step over "weird->long_array[0] = 1234;"
-gdb_cmd "step"
-
-# Test: c_variable-5.5
-# Desc: check that long_array[0] changed
-gdbtk_test c_variable-5.5 {check that long_array[0] changed} {
-  check_update
-} {struct_declarations.long_array.0 {struct_declarations.s2.i.3 struct_declarations.func_ptr_ptr struct_declarations.s2.i.4 struct_declarations.s2.i.5 struct_declarations.s2.i.6 struct_declarations.func_ptr struct_declarations.s2.i.7 struct_declarations.s2.i.8 struct_declarations.s2.i.9 struct_declarations.s2.u2.u1s1.d struct_declarations.func_ptr_struct struct_declarations.s2.u2.u1s1.e struct_declarations.u1 struct_declarations.char_ptr.*char_ptr struct_declarations.long_int struct_declarations.s2.u2.u1s2.func struct_declarations.integer struct_declarations.s2.u2 struct_declarations.s2.u2.u1s1.e.0 struct_declarations.s2.u2.u1s1.e.1 struct_declarations.long_array.0 struct_declarations.s2.u2.u1s1.e.2 struct_declarations.long_array.1 struct_declarations.u1.a struct_declarations.s2.u2.u1s1.e.3 struct_declarations.long_array.2 struct_declarations.u1.b struct_declarations.s2.u2.u1s1.e.4 struct_declarations.long_array.3 struct_declarations.u1.c struct_declarations.s2.u2.u1s1.e.5 struct_declarations.long_array.4 struct_declarations.u1.d struct_declarations.u1.b.*b struct_declarations.int_ptr_ptr.*int_ptr_ptr.**int_ptr_ptr struct_declarations.s2.u2.u1s1.e.6 struct_declarations.long_array.5 struct_declarations.s2.u2.u1s1.e.7 struct_declarations.long_array.6 struct_declarations.s2.u2.u1s1.e.8 struct_declarations.long_array.7 struct_declarations.s2.u2.u1s1.e.9 struct_declarations.long_array.8 struct_declarations.character struct_declarations.long_array.9 struct_declarations.int_ptr_ptr.*int_ptr_ptr struct_declarations.s2.u2.u1s1.func struct_declarations.s2.u2.u1s2.array_ptr struct_declarations.s2.u2.f struct_declarations.s2.u2.u1s1.foo struct_declarations.s2.u2.u1s1 struct_declarations.s2.u2.u1s2.array_ptr.0 struct_declarations.char_ptr struct_declarations.s2.u2.u1s2 struct_declarations.s2.u2.u1s2.array_ptr.1 struct_declarations.int_ptr_ptr struct_declarations.s2 struct_declarations.long_array struct_declarations.s2.g struct_declarations.s2.i.0 struct_declarations.s2.h struct_declarations.s2.i.1 struct_declarations.s2.i struct_declarations.s2.i.2}}
-
-# Step over "struct_declarations.long_array[1] = 2345;"
-gdb_cmd "step"
-
-# Test: c_variable-5.6
-# Desc: check that long_array[1] changed
-gdbtk_test c_variable-5.6 {check that long_array[1] changed} {
-  check_update
-} {struct_declarations.long_array.1 {struct_declarations.s2.i.3 struct_declarations.func_ptr_ptr struct_declarations.s2.i.4 struct_declarations.s2.i.5 struct_declarations.s2.i.6 struct_declarations.func_ptr struct_declarations.s2.i.7 struct_declarations.s2.i.8 struct_declarations.s2.i.9 struct_declarations.s2.u2.u1s1.d struct_declarations.func_ptr_struct struct_declarations.s2.u2.u1s1.e struct_declarations.u1 struct_declarations.char_ptr.*char_ptr struct_declarations.long_int struct_declarations.s2.u2.u1s2.func struct_declarations.integer struct_declarations.s2.u2 struct_declarations.s2.u2.u1s1.e.0 struct_declarations.s2.u2.u1s1.e.1 struct_declarations.long_array.0 struct_declarations.s2.u2.u1s1.e.2 struct_declarations.long_array.1 struct_declarations.u1.a struct_declarations.s2.u2.u1s1.e.3 struct_declarations.long_array.2 struct_declarations.u1.b struct_declarations.s2.u2.u1s1.e.4 struct_declarations.long_array.3 struct_declarations.u1.c struct_declarations.s2.u2.u1s1.e.5 struct_declarations.long_array.4 struct_declarations.u1.d struct_declarations.u1.b.*b struct_declarations.int_ptr_ptr.*int_ptr_ptr.**int_ptr_ptr struct_declarations.s2.u2.u1s1.e.6 struct_declarations.long_array.5 struct_declarations.s2.u2.u1s1.e.7 struct_declarations.long_array.6 struct_declarations.s2.u2.u1s1.e.8 struct_declarations.long_array.7 struct_declarations.s2.u2.u1s1.e.9 struct_declarations.long_array.8 struct_declarations.character struct_declarations.long_array.9 struct_declarations.int_ptr_ptr.*int_ptr_ptr struct_declarations.s2.u2.u1s1.func struct_declarations.s2.u2.u1s2.array_ptr struct_declarations.s2.u2.f struct_declarations.s2.u2.u1s1.foo struct_declarations.s2.u2.u1s1 struct_declarations.s2.u2.u1s2.array_ptr.0 struct_declarations.char_ptr struct_declarations.s2.u2.u1s2 struct_declarations.s2.u2.u1s2.array_ptr.1 struct_declarations.int_ptr_ptr struct_declarations.s2 struct_declarations.long_array struct_declarations.s2.g struct_declarations.s2.i.0 struct_declarations.s2.h struct_declarations.s2.i.1 struct_declarations.s2.i struct_declarations.s2.i.2}}
-
-# Step over "weird->long_array[2] = 3456;"
-gdb_cmd "step"
-
-# Test: c_variable-5.7
-# Desc: check that long_array[2] changed
-gdbtk_test c_variable-5.7 {check that long_array[2] changed} {
-  check_update
-} {struct_declarations.long_array.2 {struct_declarations.s2.i.3 struct_declarations.func_ptr_ptr struct_declarations.s2.i.4 struct_declarations.s2.i.5 struct_declarations.s2.i.6 struct_declarations.func_ptr struct_declarations.s2.i.7 struct_declarations.s2.i.8 struct_declarations.s2.i.9 struct_declarations.s2.u2.u1s1.d struct_declarations.func_ptr_struct struct_declarations.s2.u2.u1s1.e struct_declarations.u1 struct_declarations.char_ptr.*char_ptr struct_declarations.long_int struct_declarations.s2.u2.u1s2.func struct_declarations.integer struct_declarations.s2.u2 struct_declarations.s2.u2.u1s1.e.0 struct_declarations.s2.u2.u1s1.e.1 struct_declarations.long_array.0 struct_declarations.s2.u2.u1s1.e.2 struct_declarations.long_array.1 struct_declarations.u1.a struct_declarations.s2.u2.u1s1.e.3 struct_declarations.long_array.2 struct_declarations.u1.b struct_declarations.s2.u2.u1s1.e.4 struct_declarations.long_array.3 struct_declarations.u1.c struct_declarations.s2.u2.u1s1.e.5 struct_declarations.long_array.4 struct_declarations.u1.d struct_declarations.u1.b.*b struct_declarations.int_ptr_ptr.*int_ptr_ptr.**int_ptr_ptr struct_declarations.s2.u2.u1s1.e.6 struct_declarations.long_array.5 struct_declarations.s2.u2.u1s1.e.7 struct_declarations.long_array.6 struct_declarations.s2.u2.u1s1.e.8 struct_declarations.long_array.7 struct_declarations.s2.u2.u1s1.e.9 struct_declarations.long_array.8 struct_declarations.character struct_declarations.long_array.9 struct_declarations.int_ptr_ptr.*int_ptr_ptr struct_declarations.s2.u2.u1s1.func struct_declarations.s2.u2.u1s2.array_ptr struct_declarations.s2.u2.f struct_declarations.s2.u2.u1s1.foo struct_declarations.s2.u2.u1s1 struct_declarations.s2.u2.u1s2.array_ptr.0 struct_declarations.char_ptr struct_declarations.s2.u2.u1s2 struct_declarations.s2.u2.u1s2.array_ptr.1 struct_declarations.int_ptr_ptr struct_declarations.s2 struct_declarations.long_array struct_declarations.s2.g struct_declarations.s2.i.0 struct_declarations.s2.h struct_declarations.s2.i.1 struct_declarations.s2.i struct_declarations.s2.i.2}}
-
-# Step over:
-#    struct_declarations.long_array[3] = 4567;
-#    weird->long_array[4] = 5678;
-#    struct_declarations.long_array[5] = 6789;
-#    weird->long_array[6] = 7890;
-#    struct_declarations.long_array[7] = 8901;
-#    weird->long_array[8] = 9012;
-#    struct_declarations.long_array[9] = 1234;
-for {set i 0} {$i < 7} {incr i} {
-  gdb_cmd "step"
-}
-
-# Test: c_variable-5.8
-# Desc: check that long_array[3-9] changed
-gdbtk_test c_variable-5.8 {check that long_array[3-9] changed} {
-  check_update
-} {{{struct_declarations.long_array.3 struct_declarations.long_array.4 struct_declarations.long_array.5 struct_declarations.long_array.6 struct_declarations.long_array.7 struct_declarations.long_array.8 struct_declarations.long_array.9}} {struct_declarations.s2.i.3 struct_declarations.func_ptr_ptr struct_declarations.s2.i.4 struct_declarations.s2.i.5 struct_declarations.s2.i.6 struct_declarations.func_ptr struct_declarations.s2.i.7 struct_declarations.s2.i.8 struct_declarations.s2.i.9 struct_declarations.s2.u2.u1s1.d struct_declarations.func_ptr_struct struct_declarations.s2.u2.u1s1.e struct_declarations.u1 struct_declarations.char_ptr.*char_ptr struct_declarations.long_int struct_declarations.s2.u2.u1s2.func struct_declarations.integer struct_declarations.s2.u2 struct_declarations.s2.u2.u1s1.e.0 struct_declarations.s2.u2.u1s1.e.1 struct_declarations.long_array.0 struct_declarations.s2.u2.u1s1.e.2 struct_declarations.long_array.1 struct_declarations.u1.a struct_declarations.s2.u2.u1s1.e.3 struct_declarations.long_array.2 struct_declarations.u1.b struct_declarations.s2.u2.u1s1.e.4 struct_declarations.long_array.3 struct_declarations.u1.c struct_declarations.s2.u2.u1s1.e.5 struct_declarations.long_array.4 struct_declarations.u1.d struct_declarations.u1.b.*b struct_declarations.int_ptr_ptr.*int_ptr_ptr.**int_ptr_ptr struct_declarations.s2.u2.u1s1.e.6 struct_declarations.long_array.5 struct_declarations.s2.u2.u1s1.e.7 struct_declarations.long_array.6 struct_declarations.s2.u2.u1s1.e.8 struct_declarations.long_array.7 struct_declarations.s2.u2.u1s1.e.9 struct_declarations.long_array.8 struct_declarations.character struct_declarations.long_array.9 struct_declarations.int_ptr_ptr.*int_ptr_ptr struct_declarations.s2.u2.u1s1.func struct_declarations.s2.u2.u1s2.array_ptr struct_declarations.s2.u2.f struct_declarations.s2.u2.u1s1.foo struct_declarations.s2.u2.u1s1 struct_declarations.s2.u2.u1s2.array_ptr.0 struct_declarations.char_ptr struct_declarations.s2.u2.u1s2 struct_declarations.s2.u2.u1s2.array_ptr.1 struct_declarations.int_ptr_ptr struct_declarations.s2 struct_declarations.long_array struct_declarations.s2.g struct_declarations.s2.i.0 struct_declarations.s2.h struct_declarations.s2.i.1 struct_declarations.s2.i struct_declarations.s2.i.2}}
-
-# Step over "weird->func_ptr = nothing;"
-gdb_cmd "step"
-
-# Test: c_variable-5.9
-# Desc: check that func_ptr changed
-gdbtk_test c_variable-5.9 {check that func_ptr changed} {
-  check_update
-} {struct_declarations.func_ptr {struct_declarations.s2.i.3 struct_declarations.func_ptr_ptr struct_declarations.s2.i.4 struct_declarations.s2.i.5 struct_declarations.s2.i.6 struct_declarations.func_ptr struct_declarations.s2.i.7 struct_declarations.s2.i.8 struct_declarations.s2.i.9 struct_declarations.s2.u2.u1s1.d struct_declarations.func_ptr_struct struct_declarations.s2.u2.u1s1.e struct_declarations.u1 struct_declarations.char_ptr.*char_ptr struct_declarations.long_int struct_declarations.s2.u2.u1s2.func struct_declarations.integer struct_declarations.s2.u2 struct_declarations.s2.u2.u1s1.e.0 struct_declarations.s2.u2.u1s1.e.1 struct_declarations.long_array.0 struct_declarations.s2.u2.u1s1.e.2 struct_declarations.long_array.1 struct_declarations.u1.a struct_declarations.s2.u2.u1s1.e.3 struct_declarations.long_array.2 struct_declarations.u1.b struct_declarations.s2.u2.u1s1.e.4 struct_declarations.long_array.3 struct_declarations.u1.c struct_declarations.s2.u2.u1s1.e.5 struct_declarations.long_array.4 struct_declarations.u1.d struct_declarations.u1.b.*b struct_declarations.int_ptr_ptr.*int_ptr_ptr.**int_ptr_ptr struct_declarations.s2.u2.u1s1.e.6 struct_declarations.long_array.5 struct_declarations.s2.u2.u1s1.e.7 struct_declarations.long_array.6 struct_declarations.s2.u2.u1s1.e.8 struct_declarations.long_array.7 struct_declarations.s2.u2.u1s1.e.9 struct_declarations.long_array.8 struct_declarations.character struct_declarations.long_array.9 struct_declarations.int_ptr_ptr.*int_ptr_ptr struct_declarations.s2.u2.u1s1.func struct_declarations.s2.u2.u1s2.array_ptr struct_declarations.s2.u2.f struct_declarations.s2.u2.u1s1.foo struct_declarations.s2.u2.u1s1 struct_declarations.s2.u2.u1s2.array_ptr.0 struct_declarations.char_ptr struct_declarations.s2.u2.u1s2 struct_declarations.s2.u2.u1s2.array_ptr.1 struct_declarations.int_ptr_ptr struct_declarations.s2 struct_declarations.long_array struct_declarations.s2.g struct_declarations.s2.i.0 struct_declarations.s2.h struct_declarations.s2.i.1 struct_declarations.s2.i struct_declarations.s2.i.2}}
-
-# Delete all variables
-delete_all_variables
-
-# Step over all lines:
-# ...
-#   psnp = &snp0;
-for {set i 0} {$i < 43} {incr i} {
-  gdb_cmd "step"
-}
-
-# Test: c_variable-5.10
-# Desc: create psnp->char_ptr
-gdbtk_test c_variable-5.10 {create psnp->char_ptr} {
-  create_variable psnp->char_ptr
-} {0}
-
-# Test: c_variable-5.11
-# Desc: children of psnp->char_ptr
-gdbtk_test c_variable-5.11 {children of psnp->char_ptr} {
-  get_children psnp->char_ptr
-} {*psnp->char_ptr}
-
-# Test: c_variable-5.12
-# Desc: number of children of psnp->char_ptr
-gdbtk_test c_variable-5.12 {number of children of psnp->char_ptr} {
-  $var(psnp->char_ptr) numChildren
-} {1}
-
-# Test: c_variable-5.13
-# Desc: children of *(psnp->char_ptr)
-gdbtk_test c_variable-5.13 {children of *(psnp->char_ptr)} {
-  get_children psnp->char_ptr.*psnp->char_ptr
-} {**psnp->char_ptr}
-
-# Test: c_variable-5.14
-# Desc: number of children of *(psnp->char_ptr)
-gdbtk_test c_variable-5.14 {number of children of *(psnp->char_ptr)} {
-  $var(psnp->char_ptr.*psnp->char_ptr) numChildren
-} {1}
-
-# Test: c_variable-5.15
-# Desc: children of *(*(psnp->char_ptr))
-gdbtk_test c_variable-5.15 {children of *(*(psnp->char_ptr))} {
-  get_children psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr
-} {***psnp->char_ptr}
-
-# Test: c_variable-5.16
-# Desc: number of children of *(*(psnp->char_ptr))
-gdbtk_test c_variable-5.16 {number of children of *(*(psnp->char_ptr))} {
-  $var(psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr) numChildren
-} {1}
-
-# Test: c_variable-5.17
-# Desc: children of *(*(*(psnp->char_ptr)))
-gdbtk_test c_variable-5.17 {children of *(*(*(psnp->char_ptr)))} {
-  get_children psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr.***psnp->char_ptr
-} {****psnp->char_ptr}
-
-# Test: c_variable-5.18
-# Desc: number of children of *(*(*(psnp->char_ptr)))
-gdbtk_test c_variable-5.18 {number of children of *(*(*(psnp->char_ptr)))} {
-  $var(psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr.***psnp->char_ptr) numChildren
-} {1}
-
-# Test: c_variable-5.19
-# Desc: create psnp->long_ptr
-gdbtk_test c_variable-5.19 {create psnp->long_ptr} {
-  create_variable psnp->long_ptr
-} {0}
-
-# Test: c_variable-5.20
-# Desc: children of psnp->long_ptr
-gdbtk_test c_variable-5.20 {children of psnp->long_ptr} {
-  get_children psnp->long_ptr
-} {*psnp->long_ptr}
-
-# Test: c_variable-5.21
-# Desc: number of children of psnp->long_ptr
-gdbtk_test c_variable-5.21 {number of children of psnp->long_ptr} {
-  $var(psnp->long_ptr) numChildren
-} {1}
-
-# Test: c_variable-5.22
-# Desc: children of *(psnp->long_ptr)
-gdbtk_test c_variable-5.22 {children of *(psnp->long_ptr)} {
-  get_children psnp->long_ptr.*psnp->long_ptr
-} {**psnp->long_ptr}
-
-# Test: c_variable-5.23
-# Desc: number of children of *(psnp->long_ptr)
-gdbtk_test c_variable-5.23 {number of children of *(psnp->long_ptr)} {
-  $var(psnp->long_ptr.*psnp->long_ptr) numChildren
-} {1}
-
-# Test: c_variable-5.24
-# Desc: children of *(*(psnp->long_ptr))
-gdbtk_test c_variable-5.24 {children of *(*(psnp->long_ptr))} {
-  get_children psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr
-} {***psnp->long_ptr}
-
-# Test: c_variable-5.25
-# Desc: number of children of *(*(psnp->long_ptr))
-gdbtk_test c_variable-5.25 {number of children of *(*(psnp->long_ptr))} {
-  $var(psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr) numChildren
-} {1}
-
-# Test: c_variable-5.26
-# Desc: children of *(*(*(psnp->long_ptr)))
-gdbtk_test c_variable-5.26 {children of *(*(*(psnp->long_ptr)))} {
-  get_children psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr.***psnp->long_ptr
-} {****psnp->long_ptr}
-
-# Test: c_variable-5.27
-# Desc: number of children of *(*(*(psnp->long_ptr)))
-gdbtk_test c_variable-5.27 {number of children of *(*(*(psnp->long_ptr)))} {
-  $var(psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr.***psnp->long_ptr) numChildren
-} {1}
-
-# Test: c_variable-5.28
-# Desc: children of *(*(*(*(psnp->long_ptr))))
-gdbtk_test c_variable-5.29 {children of *(*(*(*(psnp->long_ptr))))} {
-  get_children psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr.***psnp->long_ptr.****psnp->long_ptr
-} {}
-
-# Test: c_variable-5.29
-# Desc: number of children of *(*(*(*(psnp->long_ptr))))
-gdbtk_test c_variable-5.29 {number of children of *(*(*(*(psnp->long_ptr))))} {
-  $var(psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr.***psnp->long_ptr.****psnp->long_ptr) numChildren
-} {0}
-
-# Test: c_variable-5.30
-# Desc: create psnp->ptrs
-gdbtk_test c_variable-5.30 {create psnp->ptrs} {
-  create_variable psnp->ptrs
-} {0}
-
-# Test: c_variable-5.31
-# Desc: children of psnp->ptrs
-gdbtk_test c_variable-5.31 {children of psnp->ptrs} {
-  get_children psnp->ptrs
-} {0 1 2}
-
-# Test: c_variable-5.32
-# Desc: number of children of psnp->ptrs
-gdbtk_test c_variable-5.32 {number of children of psnp->ptrs} {
-  $var(psnp->ptrs) numChildren
-} {3}
-
-# Test: c_variable-5.33
-# Desc: children of psnp->ptrs[0]
-gdbtk_test c_variable-5.33 {children of psnp->ptrs[0]} {
-  get_children psnp->ptrs.0
-} {char_ptr long_ptr ptrs next}
-
-# Test: c_variable-5.34
-# Desc: number of children of psnp->ptrs[0]
-gdbtk_test c_variable-5.34 {number of children of psnp->ptrs[0]} {
-  $var(psnp->ptrs.0) numChildren
-} {4}
-
-# Test: c_variable-5.35
-# Desc: children of psnp->ptrs[0]->next
-gdbtk_test c_variable-5.35 {children of psnp->ptrs.0.next} {
-  get_children psnp->ptrs.0.next
-} {char_ptr long_ptr ptrs next}
-
-# Test: c_variable-5.36
-# Desc: number of children of psnp->ptrs[0]->next
-gdbtk_test c_variable-5.36 {number of children of psnp->ptrs[0]->next} {
-  $var(psnp->ptrs.0.next) numChildren
-} {4}
-
-# Test: c_variable-5.37
-# Desc: children of psnp->ptrs[0]->next->char_ptr
-gdbtk_test c_variable-5.37 {children of psnp->ptrs[0]->next->char_ptr} {
-  get_children psnp->ptrs.0.next.char_ptr
-} {*char_ptr}
-
-# Test: c_variable-5.38
-# Desc: number of children of psnp->ptrs[0]->next->char_ptr
-gdbtk_test c_variable-5.38 {number of children of psnp->ptrs[0]->next->char_ptr} {
-  $var(psnp->ptrs.0.next.char_ptr) numChildren
-} {1}
-
-# Test: c_variable-5.39
-# Desc: children of *psnp->ptrs[0]->next->char_ptr
-gdbtk_test c_variable-5.39 {children of *psnp->ptrs[0]->next->char_ptr} {
-  get_children psnp->ptrs.0.next.char_ptr.*char_ptr
-} {**char_ptr}
-
-# Test: c_variable-5.40
-# Desc: number of children of *psnp->ptrs[0]->next->char_ptr
-gdbtk_test c_variable-5.40 {number of children of *psnp->ptrs[0]->next->char_ptr} {
-  $var(psnp->ptrs.0.next.char_ptr.*char_ptr) numChildren
-} {1}
-
-# Test: c_variable-5.41
-# Desc: children of **psnp->ptrs[0]->next->char_ptr
-gdbtk_test c_variable-5.41 {children of **psnp->ptrs[0]->next->char_ptr} {
-  get_children psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr
-} {***char_ptr}
-
-# Test: c_variable-5.42
-# Desc: number of children of **psnp->ptrs[0]->next->char_ptr
-gdbtk_test c_variable-5.42 {number of children of **psnp->ptrs[0]->next->char_ptr} {
-  $var(psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr) numChildren
-} {1}
-
-# Test: c_variable-5.43
-# Desc: children of ***psnp->ptrs[0]->next->char_ptr
-gdbtk_test c_variable-5.43 {children of ***psnp->ptrs[0]->next->char_ptr} {
-  get_children psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr.***char_ptr
-} {****char_ptr}
-
-# Test: c_variable-5.44
-# Desc: number of children of ***psnp->ptrs[0]->next->char_ptr
-gdbtk_test c_variable-5.44 {number of children of ***psnp->ptrs[0]->next->char_ptr} {
-  $var(psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr.***char_ptr) numChildren
-} {1}
-
-# Test: c_variable-5.45
-# Desc: children of psnp->ptrs[0]->next->next
-gdbtk_test c_variable-5.45 {children of psnp->ptrs[0]->next->next} {
-  get_children psnp->ptrs.0.next.next
-} {char_ptr long_ptr ptrs next}
-
-# Test: c_variable-5.46
-# Desc: children of psnp->ptrs[0]->next->next->ptrs
-gdbtk_test c_variable-5.46 {children of psnp->ptrs[0]->next->next->ptrs} {
-  get_children psnp->ptrs.0.next.next.ptrs
-} {0 1 2}
-
-#  Step over "snp0.char_ptr = &b3;"
-gdb_cmd "step"
-
-# Test: c_variable-5.47
-# Desc: check that psnp->char_ptr (and [0].char_ptr) changed
-gdbtk_test c_variable-5.47 {check that psnp->char_ptr (and [0].char_ptr) changed} {
-  check_update
-} {{psnp->ptrs.0.char_ptr {psnp->char_ptr psnp->char_ptr.*psnp->char_ptr psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr.***psnp->char_ptr psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr.***psnp->char_ptr.****psnp->char_ptr}} {psnp->ptrs.0.next psnp->ptrs.0.next.ptrs psnp->ptrs.0.next.next psnp->ptrs.0.next.next.char_ptr psnp->ptrs.0.next.next.long_ptr psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr.***char_ptr psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr.***psnp->char_ptr.****psnp->char_ptr psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr psnp->ptrs.0.next.char_ptr psnp->ptrs.0.next.long_ptr psnp->ptrs.0.next.next.ptrs psnp->ptrs.0.next.char_ptr.*char_ptr psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr.***psnp->long_ptr.****psnp->long_ptr psnp->ptrs.0.next.next.next psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr.***psnp->char_ptr psnp->char_ptr.*psnp->char_ptr psnp->ptrs.0.next.next.ptrs.0 psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr.***psnp->long_ptr psnp->long_ptr.*psnp->long_ptr psnp->ptrs.0.next.next.ptrs.1 psnp->ptrs.0.next.next.ptrs.2 psnp->ptrs.0.char_ptr psnp->ptrs.0.long_ptr psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr.***char_ptr.****char_ptr psnp->ptrs.0.ptrs psnp->ptrs.0 psnp->ptrs.1 psnp->ptrs.2 psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr}}
-
-#  Step over "snp1.char_ptr = &c3;"
-gdb_cmd "step"
-
-# Test: c_variable-5.48
-# Desc: check that psnp->next->char_ptr (and [1].char_ptr) changed
-gdbtk_test c_variable-5.48 {check that psnp->next->char_ptr (and [1].char_ptr) changed} {
-  check_update
-} {{{psnp->ptrs.0.next.char_ptr psnp->ptrs.0.next.char_ptr.*char_ptr psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr.***char_ptr psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr.***char_ptr.****char_ptr}} {psnp->ptrs.0.next psnp->ptrs.0.next.ptrs psnp->ptrs.0.next.next psnp->ptrs.0.next.next.char_ptr psnp->ptrs.0.next.next.long_ptr psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr.***char_ptr psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr.***psnp->char_ptr.****psnp->char_ptr psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr psnp->ptrs.0.next.char_ptr psnp->ptrs.0.next.long_ptr psnp->ptrs.0.next.next.ptrs psnp->ptrs.0.next.char_ptr.*char_ptr psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr.***psnp->long_ptr.****psnp->long_ptr psnp->ptrs.0.next.next.next psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr.***psnp->char_ptr psnp->char_ptr.*psnp->char_ptr psnp->ptrs.0.next.next.ptrs.0 psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr.***psnp->long_ptr psnp->long_ptr.*psnp->long_ptr psnp->ptrs.0.next.next.ptrs.1 psnp->ptrs.0.next.next.ptrs.2 psnp->ptrs.0.char_ptr psnp->ptrs.0.long_ptr psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr.***char_ptr.****char_ptr psnp->ptrs.0.ptrs psnp->ptrs.0 psnp->ptrs.1 psnp->ptrs.2 psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr}}
-
-#  Step over "snp2.char_ptr = &a3;"
-gdb_cmd "step"
-
-# Test: c_variable-5.49
-# Desc: check that psnp->next->next->char_ptr (and [2].char_ptr) changed
-gdbtk_test c_variable-5.49 {heck that psnp->next->next->char_ptr (and [2].char_ptr) changed} {
-  check_update
-} {psnp->ptrs.0.next.next.char_ptr {psnp->ptrs.0.next psnp->ptrs.0.next.ptrs psnp->ptrs.0.next.next psnp->ptrs.0.next.next.char_ptr psnp->ptrs.0.next.next.long_ptr psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr.***char_ptr psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr.***psnp->char_ptr.****psnp->char_ptr psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr psnp->ptrs.0.next.char_ptr psnp->ptrs.0.next.long_ptr psnp->ptrs.0.next.next.ptrs psnp->ptrs.0.next.char_ptr.*char_ptr psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr.***psnp->long_ptr.****psnp->long_ptr psnp->ptrs.0.next.next.next psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr.***psnp->char_ptr psnp->char_ptr.*psnp->char_ptr psnp->ptrs.0.next.next.ptrs.0 psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr.***psnp->long_ptr psnp->long_ptr.*psnp->long_ptr psnp->ptrs.0.next.next.ptrs.1 psnp->ptrs.0.next.next.ptrs.2 psnp->ptrs.0.char_ptr psnp->ptrs.0.long_ptr psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr.***char_ptr.****char_ptr psnp->ptrs.0.ptrs psnp->ptrs.0 psnp->ptrs.1 psnp->ptrs.2 psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr}}
-
-#  Step over "snp0.long_ptr = &y3;"
-gdb_cmd "step"
-
-# Test: c_variable-5.50
-# Desc: check that psnp->long_ptr (and [0].long_ptr) changed
-gdbtk_test c_variable-5.50 {check that psnp->long_ptr (and [0].long_ptr) changed} {
-  check_update
-} {{psnp->ptrs.0.long_ptr {psnp->long_ptr psnp->long_ptr.*psnp->long_ptr psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr.***psnp->long_ptr psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr.***psnp->long_ptr.****psnp->long_ptr}} {psnp->ptrs.0.next psnp->ptrs.0.next.ptrs psnp->ptrs.0.next.next psnp->ptrs.0.next.next.char_ptr psnp->ptrs.0.next.next.long_ptr psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr.***char_ptr psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr.***psnp->char_ptr.****psnp->char_ptr psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr psnp->ptrs.0.next.char_ptr psnp->ptrs.0.next.long_ptr psnp->ptrs.0.next.next.ptrs psnp->ptrs.0.next.char_ptr.*char_ptr psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr.***psnp->long_ptr.****psnp->long_ptr psnp->ptrs.0.next.next.next psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr.***psnp->char_ptr psnp->char_ptr.*psnp->char_ptr psnp->ptrs.0.next.next.ptrs.0 psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr.***psnp->long_ptr psnp->long_ptr.*psnp->long_ptr psnp->ptrs.0.next.next.ptrs.1 psnp->ptrs.0.next.next.ptrs.2 psnp->ptrs.0.char_ptr psnp->ptrs.0.long_ptr psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr.***char_ptr.****char_ptr psnp->ptrs.0.ptrs psnp->ptrs.0 psnp->ptrs.1 psnp->ptrs.2 psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr}}
-
-#  Step over "snp1.long_ptr = &x3;"
-gdb_cmd "step"
-
-# Test: c_variable-5.51
-# Desc: check that psnp->next->long_ptr (and [1].long_ptr) changed
-gdbtk_test c_variable-5.51 {check that psnp->next->long_ptr (and [1].long_ptr) changed} {
-  check_update
-} {psnp->ptrs.0.next.long_ptr {psnp->ptrs.0.next psnp->ptrs.0.next.ptrs psnp->ptrs.0.next.next psnp->ptrs.0.next.next.char_ptr psnp->ptrs.0.next.next.long_ptr psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr.***char_ptr psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr.***psnp->char_ptr.****psnp->char_ptr psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr psnp->ptrs.0.next.char_ptr psnp->ptrs.0.next.long_ptr psnp->ptrs.0.next.next.ptrs psnp->ptrs.0.next.char_ptr.*char_ptr psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr.***psnp->long_ptr.****psnp->long_ptr psnp->ptrs.0.next.next.next psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr.***psnp->char_ptr psnp->char_ptr.*psnp->char_ptr psnp->ptrs.0.next.next.ptrs.0 psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr.***psnp->long_ptr psnp->long_ptr.*psnp->long_ptr psnp->ptrs.0.next.next.ptrs.1 psnp->ptrs.0.next.next.ptrs.2 psnp->ptrs.0.char_ptr psnp->ptrs.0.long_ptr psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr.***char_ptr.****char_ptr psnp->ptrs.0.ptrs psnp->ptrs.0 psnp->ptrs.1 psnp->ptrs.2 psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr}}
-
-#  Step over "snp2.long_ptr = &z3;"
-gdb_cmd "step"
-
-# Test: c_variable-5.52
-# Desc: check that psnp->next->next->long_ptr (and [2].long_ptr) changed
-gdbtk_test c_variable-5.52 {check that psnp->next->next->long_ptr (and [2].long_ptr) changed} {
-  check_update
-} {psnp->ptrs.0.next.next.long_ptr {psnp->ptrs.0.next psnp->ptrs.0.next.ptrs psnp->ptrs.0.next.next psnp->ptrs.0.next.next.char_ptr psnp->ptrs.0.next.next.long_ptr psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr.***char_ptr psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr.***psnp->char_ptr.****psnp->char_ptr psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr psnp->ptrs.0.next.char_ptr psnp->ptrs.0.next.long_ptr psnp->ptrs.0.next.next.ptrs psnp->ptrs.0.next.char_ptr.*char_ptr psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr.***psnp->long_ptr.****psnp->long_ptr psnp->ptrs.0.next.next.next psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr.***psnp->char_ptr psnp->char_ptr.*psnp->char_ptr psnp->ptrs.0.next.next.ptrs.0 psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr.***psnp->long_ptr psnp->long_ptr.*psnp->long_ptr psnp->ptrs.0.next.next.ptrs.1 psnp->ptrs.0.next.next.ptrs.2 psnp->ptrs.0.char_ptr psnp->ptrs.0.long_ptr psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr.***char_ptr.****char_ptr psnp->ptrs.0.ptrs psnp->ptrs.0 psnp->ptrs.1 psnp->ptrs.2 psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr}}
-
-# Test: c_variable-5.53
-# Desc: names of editable variables
-gdbtk_test c_variable-5.53 {names of editable variables} {
-  editable_variables
-} {{psnp->ptrs.0.next psnp->ptrs.0.next.next psnp->ptrs.0.next.next.char_ptr psnp->ptrs.0.next.next.long_ptr psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr.***char_ptr psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr.***psnp->char_ptr.****psnp->char_ptr psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr psnp->ptrs.0.next.char_ptr psnp->ptrs.0.next.long_ptr psnp->ptrs.0.next.char_ptr.*char_ptr psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr.***psnp->long_ptr.****psnp->long_ptr psnp->ptrs.0.next.next.next psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr.***psnp->char_ptr psnp->char_ptr.*psnp->char_ptr psnp->ptrs.0.next.next.ptrs.0 psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr.***psnp->long_ptr psnp->long_ptr.*psnp->long_ptr psnp->ptrs.0.next.next.ptrs.1 psnp->ptrs.0.next.next.ptrs.2 psnp->ptrs.0.char_ptr psnp->ptrs.0.long_ptr psnp->char_ptr psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr.***char_ptr.****char_ptr psnp->long_ptr psnp->ptrs.0 psnp->ptrs.1 psnp->ptrs.2 psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr} {psnp->ptrs.0.next.ptrs psnp->ptrs.0.next.next.ptrs psnp->ptrs psnp->ptrs.0.ptrs}}
-
-#####       #####
-#               #
-# Display tests #
-#               #
-#####       #####
-
-delete_all_variables
-
-# Test: c_variable-6.1
-# Desc: create variable bar
-gdbtk_test c_variable-6.1 {create variable bar} {
-  create_variable bar
-} {0}
-
-# Test: c_variable-6.2
-# Desc: type of variable bar
-gdbtk_test c_variable-6.2 {type of variable bar} {
-  $var(bar) type
-} {int}
-
-# Test: c_variable-6.3
-# Desc: format of variable bar
-gdbtk_test c_variable-6.3 {format of variable bar} {
-  $var(bar) format
-} {natural}
-
-# Test: c_variable-6.4
-# Desc: value of variable bar
-gdbtk_test c_variable-6.4 {value of variable bar} {
-  value bar d
-} {ok}
-
-# Test: c_variable-6.5
-# Desc: change format of bar to hex
-gdbtk_test c_variable-6.5 {change format of bar to hex} {
-  $var(bar) format hex
-  $var(bar) format
-} {hexadecimal}
-
-# Test: c_variable-6.6
-# Desc: value of bar with new format
-gdbtk_test c_variable-6.6 {value of bar with new format} {
-  value bar x
-} {ok}
-
-# Test: c_variable-6.7
-# Desc: change value of bar
-gdbtk_test c_variable-6.7 {change value of bar} {
-  $var(bar) value 3
-  value bar x
-} {ok}
-
-# Test: c_variable-6.8
-# Desc: check new value of bar
-gdbtk_test c_variable-6.8 {change value of bar} {
-  $var(bar) format decimal
-  $var(bar) value
-} {3}
-
-delete_variable bar
-
-# Test: c_variable-6.11
-# Desc: create variable foo
-gdbtk_test c_variable-6.11 {create variable foo} {
-  create_variable foo
-} {0}
-
-# Test: c_variable-6.12
-# Desc: type of variable foo
-gdbtk_test c_variable-6.12 {type of variable foo} {
-  $var(foo) type
-} {int *}
-
-# Test: c_variable-6.13
-# Desc: format of variable foo
-gdbtk_test c_variable-6.13 {format of variable foo} {
-  $var(foo) format
-} {natural}
-
-# Test: c_variable-6.14
-# Desc: value of variable foo
-gdbtk_test c_variable-6.14 {value of variable foo} {
-  value foo x
-} {ok}
-
-# Test: c_variable-6.15
-# Desc: change format of var to octal
-gdbtk_test c_variable-6.15 {change format of foo to octal} {
-  $var(foo) format octal
-  $var(foo) format
-} {octal}
-
-# Test: c_variable-6.16
-# Desc: value of foo with new format
-gdbtk_test c_variable-6.16 {value of foo with new format} {
-  value foo o
-} {ok}
-
-# Test: c_variable-6.17
-# Desc: change value of foo
-gdbtk_test c_variable-6.17 {change value of foo} {
-  $var(foo) value 3
-  value foo o
-} {ok}
-
-# Test: c_variable-6.18
-# Desc: check new value of foo
-gdbtk_test c_variable-6.18 {check new value of foo} {
-  $var(foo) format decimal
-  $var(foo) value
-} {3}
-
-delete_variable foo
-
-# Test: c_variable-6.21
-# Desc: create variable weird and children
-gdbtk_test c_variable-6.21 {create variable foo} {
-  if {![create_variable weird]} {
-    lsort [get_children weird]
-  }
-} {char_ptr character func_ptr func_ptr_ptr func_ptr_struct int_ptr_ptr integer long_array long_int s2 u1}
-
-# Test: c_variable-6.22
-# Desc: type of weird and children
-gdbtk_test c_variable-6.22 {type of weird and children} {
-  set types {}
-  foreach v [lsort [array names var]] {
-    lappend types [$var($v) type]
-  }
-
-  set types
-} {{weird_struct *} {char *} char {void (*)(void)} {struct _struct_decl *(*)(int, char *, long int)} {struct _struct_decl (*)(int, char *, long int)} {int **} int {long int [10]} {long int} struct union}
-
-# Test: c_variable-6.23
-# Desc: change format of weird.func_ptr and weird.func_ptr_ptr
-gdbtk_test c_variable-6.23 {change format of weird.func_ptr and weird.func_ptr_ptr} {
-  $var(weird.func_ptr) format hexadecimal
-  $var(weird.func_ptr_ptr) format hexadecimal
-  set result {}
-  lappend result [$var(weird.func_ptr) format]
-  lappend result [$var(weird.func_ptr_ptr) format]
-  set result
-} {hexadecimal hexadecimal}
-
-# Test: c_variable-6.24
-# Desc: format of weird and children
-gdbtk_test c_variable-6.24 {format of weird and children} {
-  set formats {}
-  foreach v [lsort [array names var]] {
-    lappend formats [$var($v) format]
-  }
-
-  set formats
-} {natural natural natural hexadecimal hexadecimal natural natural natural natural natural natural natural}
-
-# Test: c_variable-6.25
-# Desc: value of weird and children
-gdbtk_test c_variable-6.25 {value of weird and children} {
-  set values {}
-  foreach v [lsort [array names var]] f [list x "" "" x x x x d d d d d] {
-    lappend values [value $v $f]
-  }
-
-  set values
-} {ok ok ok ok ok ok ok ok weird.long_array ok weird.s2 weird.u1}
-
-# Test: c_variable-6.26
-# Desc: change format of weird and children to octal
-gdbtk_test c_variable-6.26 {change format of weird and children to octal} {
-  set formats {}
-  foreach v [lsort [array names var]] {
-    $var($v) format octal
-    lappend formats [$var($v) format]
-  }
-
-  set formats
-} {octal octal octal octal octal octal octal octal octal octal octal octal}
-
-# Test: c_variable-6.27
-# Desc: value of weird and children with new format
-gdbtk_test c_variable-6.27 {value of foo with new format} {
-  set values {}
-  foreach v [lsort [array names var]] {
-    lappend values [value $v o]
-  }
-
-  set values
-} {ok ok ok ok ok ok ok ok weird.long_array ok weird.s2 weird.u1}
-
-# Test: c_variable-6.30
-# Desc: create more children of weird
-gdbtk_test c_variable-6.30 {create more children of weird} {
-  foreach v [array names var] {
-    get_children $v
-  }
-
-  # Do it twice to get more children
-  foreach v [array names var] {
-    get_children $v
-  }
-
-  lsort [array names var]
-} {weird weird.char_ptr weird.char_ptr.*char_ptr weird.character weird.func_ptr weird.func_ptr_ptr weird.func_ptr_struct weird.int_ptr_ptr weird.int_ptr_ptr.*int_ptr_ptr weird.int_ptr_ptr.*int_ptr_ptr.**int_ptr_ptr weird.integer weird.long_array weird.long_array.0 weird.long_array.1 weird.long_array.2 weird.long_array.3 weird.long_array.4 weird.long_array.5 weird.long_array.6 weird.long_array.7 weird.long_array.8 weird.long_array.9 weird.long_int weird.s2 weird.s2.g weird.s2.h weird.s2.i weird.s2.i.0 weird.s2.i.1 weird.s2.i.2 weird.s2.i.3 weird.s2.i.4 weird.s2.i.5 weird.s2.i.6 weird.s2.i.7 weird.s2.i.8 weird.s2.i.9 weird.s2.u2 weird.s2.u2.f weird.s2.u2.u1s1 weird.s2.u2.u1s2 weird.u1 weird.u1.a weird.u1.b weird.u1.b.*b weird.u1.c weird.u1.d}
-
-# Test: c_variable-6.31
-# Desc: check that all children of weird change
-#       Ok, obviously things like weird.s2 and weird.u1 will not change!
-gdbtk_test c_variable-6.31 {check that all children of weird change (ops, we are now reporting array names as changed in this case - seems harmless though)} {
-  $var(weird) value 0x2121
-  check_update
-} {{{weird weird.integer weird.character weird.char_ptr weird.char_ptr.*char_ptr weird.long_int weird.int_ptr_ptr weird.int_ptr_ptr.*int_ptr_ptr weird.long_array.0 weird.long_array.1 weird.long_array.2 weird.long_array.3 weird.long_array.4 weird.long_array.5 weird.long_array.6 weird.long_array.7 weird.long_array.8 weird.long_array.9 weird.func_ptr weird.func_ptr_struct weird.func_ptr_ptr weird.u1.a weird.u1.b weird.u1.c weird.u1.d weird.s2.u2.f weird.s2.g weird.s2.h weird.s2.i.0 weird.s2.i.1 weird.s2.i.2 weird.s2.i.3 weird.s2.i.4 weird.s2.i.5 weird.s2.i.6 weird.s2.i.7 weird.s2.i.8 weird.s2.i.9}} {weird.char_ptr weird.s2.u2.f weird.int_ptr_ptr.*int_ptr_ptr.**int_ptr_ptr weird.s2.g weird.s2.h weird.s2.i weird.func_ptr_ptr weird.func_ptr weird.s2.u2 weird.int_ptr_ptr weird.long_int weird.character weird.s2.u2.u1s1 weird.s2.u2.u1s2 weird.long_array.0 weird.u1.a weird.long_array.1 weird.s2 weird.func_ptr_struct weird.u1.b weird.long_array.2 weird.long_array weird.u1.c weird.long_array.3 weird.u1.d weird.long_array.4 weird.long_array.5 weird.s2.i.0 weird.long_array.6 weird.s2.i.1 weird.long_array.7 weird.s2.i.2 weird.long_array.8 weird.s2.i.3 weird.long_array.9 weird.s2.i.4 weird.integer weird.s2.i.5 weird.s2.i.6 weird.s2.i.7 weird.s2.i.8 weird.int_ptr_ptr.*int_ptr_ptr weird.s2.i.9 weird.char_ptr.*char_ptr weird.u1 weird.u1.b.*b}}
-
-delete_variable weird
-
-#####               #####
-#                       #
-# Special Display Tests #
-#                       #
-#####               #####
-
-# Stop in "do_special_tests"
-gdb_cmd "break do_special_tests"
-gdb_cmd "continue"
-
-# Test: c_variable-7.1
-# Desc: stop in do_special_tests
-gdbtk_test c_variable-7.1 {stop in do_special_tests} {
-  lindex [gdb_loc] 1
-} {do_special_tests}
-
-# Test: c_variable-7.10
-# Desc: create union u
-gdbtk_test c_variable-7.10 {create union u} {
-  create_variable u
-} {0}
-
-# Test: c_variable-7.11
-# Desc: value of u
-gdbtk_test c_variable-7.11 {value of u} {
-  $var(u) value
-} {{...}}
-
-# Test: c_variable-7.12
-# Desc: type of u
-gdbtk_test c_variable-7.12 {type of u} {
-  $var(u) type
-} {union named_union}
-
-# Test: c_variable-7.13
-# Desc: is u editable
-gdbtk_test c_variable-7.13 {is u editable} {
-  $var(u) editable
-} {0}
-
-# Test: c_variable-7.14
-# Desc: number of children of u
-gdbtk_test c_variable-7.14 {number of children of u} {
-  $var(u) numChildren
-} {2}
-
-# Test: c_variable-7.15
-# Desc: children of u
-gdbtk_test c_variable-7.15 {children of u} {
-  get_children u
-} {integer char_ptr}
-
-# Test: c_variable-7.20
-# Desc: create anonu
-gdbtk_test c_variable-7.20 {create anonu} {
-  create_variable anonu
-} {0}
-
-# Test: c_variable-7.21
-# Desc: value of anonu
-gdbtk_test c_variable-7.21 {value of anonu} {
-  $var(anonu) value
-} {{...}}
-
-# Test: c_variable-7.22
-# Desc: type of anonu
-gdbtk_test c_variable-7.22 {type of anonu} {
-  $var(anonu) type
-} {union}
-
-# Test: c_variable-7.23
-# Desc: is anonu editable
-gdbtk_test c_variable-7.23 {is anonu editable} {
-  $var(anonu) editable
-} {0}
-
-# Test: c_variable-7.24
-# Desc: number of children of anonu
-gdbtk_test c_variable-7.24 {number of children of anonu} {
-  $var(anonu) numChildren
-} {3}
-
-# Test: c_variable-7.25
-# Desc: children of anonu
-gdbtk_test c_variable-7.25 {children of anonu} {
-  get_children anonu
-} {a b c}
-
-# Test: c_variable-7.30
-# Desc: create struct s
-gdbtk_test c_variable-7.30 {create struct s} {
-  create_variable s
-} {0}
-
-# Test: c_variable-7.31
-# Desc: value of s
-gdbtk_test c_variable-7.31 {value of s} {
-  $var(s) value
-} {{...}}
-
-# Test: c_variable-7.32
-# Desc: type of s
-gdbtk_test c_variable-7.32 {type of s} {
-  $var(s) type
-} {struct _simple_struct}
-
-# Test: c_variable-7.33
-# Desc: is s editable
-gdbtk_test c_variable-7.33 {is s editable} {
-  $var(s) editable
-} {0}
-
-# Test: c_variable-7.34
-# Desc: number of children of s
-gdbtk_test c_variable-7.34 {number of children of s} {
-  $var(s) numChildren
-} {6}
-
-# Test: c_variable-7.35
-# Desc: children of s
-gdbtk_test c_variable-7.35 {children of s} {
-  get_children s
-} {integer unsigned_integer character signed_character char_ptr array_of_10}
-
-# Test: c_variable-7.40
-# Desc: create anons
-gdbtk_test c_variable-7.40 {create anons} {
-  create_variable anons
-} {0}
-
-# Test: c_variable-7.41
-# Desc: value of anons
-gdbtk_test c_variable-7.41 {value of anons} {
-  $var(anons) value
-} {{...}}
-
-# Test: c_variable-7.42
-# Desc: type of anons
-gdbtk_test c_variable-7.42 {type of anons} {
-  $var(anons) type
-} {struct}
-
-# Test: c_variable-7.43
-# Desc: is anons editable
-gdbtk_test c_variable-7.43 {is anons editable} {
-  $var(anons) editable
-} {0}
-
-# Test: c_variable-7.44
-# Desc: number of children of anons
-gdbtk_test c_variable-7.44 {number of children of anons} {
-  $var(anons) numChildren
-} {3}
-
-# Test: c_variable-7.45
-# Desc: children of anons
-gdbtk_test c_variable-7.45 {children of anons} {
-  get_children anons
-} {a b c}
-
-# Test: c_variable-7.50
-# Desc: create enum e
-gdbtk_test c_variable-7.50 {create enum e} {
-  create_variable e
-} {0}
-
-# Test: c_variable-7.51
-# Desc: value of e
-gdbtk_test c_variable-7.51 {value of e} {
-  $var(e) value bar
-  $var(e) value
-} {bar}
-
-# Test: c_variable-7.52
-# Desc: type of e
-gdbtk_test c_variable-7.52 {type of e} {
-  $var(e) type
-} {enum foo}
-
-# Test: c_variable-7.53
-# Desc: is e editable
-gdbtk_test c_variable-7.53 {is e editable} {
-  $var(e) editable
-} {1}
-
-# Test: c_variable-7.54
-# Desc: number of children of e
-gdbtk_test c_variable-7.54 {number of children of e} {
-  $var(e) numChildren
-} {0}
-
-# Test: c_variable-7.55
-# Desc: children of e
-gdbtk_test c_variable-7.55 {children of e} {
-  get_children e
-} {}
-
-# Test: c_variable-7.60
-# Desc: create anone
-gdbtk_test c_variable-7.60 {create anone} {
-  create_variable anone
-} {0}
-
-# Test: c_variable-7.61
-# Desc: value of anone
-gdbtk_test c_variable-7.61 {value of e} {
-  $var(e) value bar
-  $var(e) value
-} {bar}
-
-# Test: c_variable-7.62
-# Desc: type of e
-gdbtk_test c_variable-7.62 {type of e} {
-  $var(e) type
-} {enum foo}
-
-# Test: c_variable-7.63
-# Desc: is e editable
-gdbtk_test c_variable-7.63 {is e editable} {
-  $var(e) editable
-} {1}
-
-# Test: c_variable-7.64
-# Desc: number of children of e
-gdbtk_test c_variable-7.64 {number of children of e} {
-  $var(e) numChildren
-} {0}
-
-# Test: c_variable-7.65
-# Desc: children of e
-gdbtk_test c_variable-7.65 {children of e} {
-  get_children e
-} {}
-
-# Test: c_variable-7.70
-# Desc: create anone
-gdbtk_test c_variable-7.70 {try to create anone again (duplicate obj name} {
-  create_variable anone
-} {1}
-
-# Test: c_variable-7.71
-# Desc: value of anone
-gdbtk_test c_variable-7.71 {value of anone} {
-  $var(anone) value A
-  $var(anone) value
-} {A}
-
-# Test: c_variable-7.72
-# Desc: type of anone
-gdbtk_test c_variable-7.72 {type of anone} {
-  $var(anone) type
-} {enum}
-
-# Test: c_variable-7.73
-# Desc: is anone editable
-gdbtk_test c_variable-7.73 {is anone editable} {
-  $var(anone) editable
-} {1}
-
-# Test: c_variable-7.74
-# Desc: number of children of anone
-gdbtk_test c_variable-7.74 {number of children of anone} {
-  $var(anone) numChildren
-} {0}
-
-# Test: c_variable-7.75
-# Desc: children of anone
-gdbtk_test c_variable-7.75 {children of anone} {
-  get_children anone
-} {}
-
-# Record fp
-set fp [gdb_cmd "output/x \$fp"]
-gdb_cmd {break incr_a}
-gdb_cmd {continue}
-
-# Test: c_variable-7.80
-# Desc: stop in incr_a
-gdbtk_test c_variable-7.80 {stop in incr_a} {
-  lindex [gdb_loc] 1
-} {incr_a}
-
-# Test: c_variable-7.81
-# Desc: Create variables in different scopes
-gdbtk_test c_variable-7.81 {create variables in different scopes} {
-  set a1 [gdb_variable create -expr a]
-  set a2 [gdb_variable create -expr a -frame $fp]
-
-  set vals {}
-  lappend vals [$a1 value]
-  lappend vals [$a2 value]
-  set vals
-} {2 1}
-
-#  Exit
-#
-gdbtk_test_done
-
-#Local Variables:
-#mode: tcl

diff --git a/gdb/testsuite/gdb.gdbtk/configure b/gdb/testsuite/gdb.gdbtk/configure
deleted file mode 100644 (file)
index 16dc537..0000000
--- a/gdb/testsuite/gdb.gdbtk/configure
+++ /dev/null
@@ -1,2248 +0,0 @@
-#! /bin/sh
-# Guess values for system-dependent variables and create Makefiles.
-# Generated by GNU Autoconf 2.59.
-#
-# Copyright (C) 2003 Free Software Foundation, Inc.
-# This configure script is free software; the Free Software Foundation
-# gives unlimited permission to copy, distribute and modify it.
-## --------------------- ##
-## M4sh Initialization.  ##
-## --------------------- ##
-
-# Be Bourne compatible
-if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then
-  emulate sh
-  NULLCMD=:
-  # Zsh 3.x and 4.x performs word splitting on ${1+"$@"}, which
-  # is contrary to our usage.  Disable this feature.
-  alias -g '${1+"$@"}'='"$@"'
-elif test -n "${BASH_VERSION+set}" && (set -o posix) >/dev/null 2>&1; then
-  set -o posix
-fi
-DUALCASE=1; export DUALCASE # for MKS sh
-
-# Support unset when possible.
-if ( (MAIL=60; unset MAIL) || exit) >/dev/null 2>&1; then
-  as_unset=unset
-else
-  as_unset=false
-fi
-
-
-# Work around bugs in pre-3.0 UWIN ksh.
-$as_unset ENV MAIL MAILPATH
-PS1='$ '
-PS2='> '
-PS4='+ '
-
-# NLS nuisances.
-for as_var in \
-  LANG LANGUAGE LC_ADDRESS LC_ALL LC_COLLATE LC_CTYPE LC_IDENTIFICATION \
-  LC_MEASUREMENT LC_MESSAGES LC_MONETARY LC_NAME LC_NUMERIC LC_PAPER \
-  LC_TELEPHONE LC_TIME
-do
-  if (set +x; test -z "`(eval $as_var=C; export $as_var) 2>&1`"); then
-    eval $as_var=C; export $as_var
-  else
-    $as_unset $as_var
-  fi
-done
-
-# Required to use basename.
-if expr a : '\(a\)' >/dev/null 2>&1; then
-  as_expr=expr
-else
-  as_expr=false
-fi
-
-if (basename /) >/dev/null 2>&1 && test "X`basename / 2>&1`" = "X/"; then
-  as_basename=basename
-else
-  as_basename=false
-fi
-
-
-# Name of the executable.
-as_me=`$as_basename "$0" ||
-$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \
-        X"$0" : 'X\(//\)$' \| \
-        X"$0" : 'X\(/\)$' \| \
-        .     : '\(.\)' 2>/dev/null ||
-echo X/"$0" |
-    sed '/^.*\/\([^/][^/]*\)\/*$/{ s//\1/; q; }
-         /^X\/\(\/\/\)$/{ s//\1/; q; }
-         /^X\/\(\/\).*/{ s//\1/; q; }
-         s/.*/./; q'`
-
-
-# PATH needs CR, and LINENO needs CR and PATH.
-# Avoid depending upon Character Ranges.
-as_cr_letters='abcdefghijklmnopqrstuvwxyz'
-as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
-as_cr_Letters=$as_cr_letters$as_cr_LETTERS
-as_cr_digits='0123456789'
-as_cr_alnum=$as_cr_Letters$as_cr_digits
-
-# The user is always right.
-if test "${PATH_SEPARATOR+set}" != set; then
-  echo "#! /bin/sh" >conf$$.sh
-  echo  "exit 0"   >>conf$$.sh
-  chmod +x conf$$.sh
-  if (PATH="/nonexistent;."; conf$$.sh) >/dev/null 2>&1; then
-    PATH_SEPARATOR=';'
-  else
-    PATH_SEPARATOR=:
-  fi
-  rm -f conf$$.sh
-fi
-
-
-  as_lineno_1=$LINENO
-  as_lineno_2=$LINENO
-  as_lineno_3=`(expr $as_lineno_1 + 1) 2>/dev/null`
-  test "x$as_lineno_1" != "x$as_lineno_2" &&
-  test "x$as_lineno_3"  = "x$as_lineno_2"  || {
-  # Find who we are.  Look in the path if we contain no path at all
-  # relative or not.
-  case $0 in
-    *[\\/]* ) as_myself=$0 ;;
-    *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break
-done
-
-       ;;
-  esac
-  # We did not find ourselves, most probably we were run as `sh COMMAND'
-  # in which case we are not to be found in the path.
-  if test "x$as_myself" = x; then
-    as_myself=$0
-  fi
-  if test ! -f "$as_myself"; then
-    { echo "$as_me: error: cannot find myself; rerun with an absolute path" >&2
-   { (exit 1); exit 1; }; }
-  fi
-  case $CONFIG_SHELL in
-  '')
-    as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for as_base in sh bash ksh sh5; do
-        case $as_dir in
-        /*)
-          if ("$as_dir/$as_base" -c '
-  as_lineno_1=$LINENO
-  as_lineno_2=$LINENO
-  as_lineno_3=`(expr $as_lineno_1 + 1) 2>/dev/null`
-  test "x$as_lineno_1" != "x$as_lineno_2" &&
-  test "x$as_lineno_3"  = "x$as_lineno_2" ') 2>/dev/null; then
-            $as_unset BASH_ENV || test "${BASH_ENV+set}" != set || { BASH_ENV=; export BASH_ENV; }
-            $as_unset ENV || test "${ENV+set}" != set || { ENV=; export ENV; }
-            CONFIG_SHELL=$as_dir/$as_base
-            export CONFIG_SHELL
-            exec "$CONFIG_SHELL" "$0" ${1+"$@"}
-          fi;;
-        esac
-       done
-done
-;;
-  esac
-
-  # Create $as_me.lineno as a copy of $as_myself, but with $LINENO
-  # uniformly replaced by the line number.  The first 'sed' inserts a
-  # line-number line before each line; the second 'sed' does the real
-  # work.  The second script uses 'N' to pair each line-number line
-  # with the numbered line, and appends trailing '-' during
-  # substitution so that $LINENO is not a special case at line end.
-  # (Raja R Harinath suggested sed '=', and Paul Eggert wrote the
-  # second 'sed' script.  Blame Lee E. McMahon for sed's syntax.  :-)
-  sed '=' <$as_myself |
-    sed '
-      N
-      s,$,-,
-      : loop
-      s,^\(['$as_cr_digits']*\)\(.*\)[$]LINENO\([^'$as_cr_alnum'_]\),\1\2\1\3,
-      t loop
-      s,-$,,
-      s,^['$as_cr_digits']*\n,,
-    ' >$as_me.lineno &&
-  chmod +x $as_me.lineno ||
-    { echo "$as_me: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&2
-   { (exit 1); exit 1; }; }
-
-  # Don't try to exec as it changes $[0], causing all sort of problems
-  # (the dirname of $[0] is not the place where we might find the
-  # original and so on.  Autoconf is especially sensible to this).
-  . ./$as_me.lineno
-  # Exit status is that of the last command.
-  exit
-}
-
-
-case `echo "testing\c"; echo 1,2,3`,`echo -n testing; echo 1,2,3` in
-  *c*,-n*) ECHO_N= ECHO_C='
-' ECHO_T='     ' ;;
-  *c*,*  ) ECHO_N=-n ECHO_C= ECHO_T= ;;
-  *)       ECHO_N= ECHO_C='\c' ECHO_T= ;;
-esac
-
-if expr a : '\(a\)' >/dev/null 2>&1; then
-  as_expr=expr
-else
-  as_expr=false
-fi
-
-rm -f conf$$ conf$$.exe conf$$.file
-echo >conf$$.file
-if ln -s conf$$.file conf$$ 2>/dev/null; then
-  # We could just check for DJGPP; but this test a) works b) is more generic
-  # and c) will remain valid once DJGPP supports symlinks (DJGPP 2.04).
-  if test -f conf$$.exe; then
-    # Don't use ln at all; we don't have any links
-    as_ln_s='cp -p'
-  else
-    as_ln_s='ln -s'
-  fi
-elif ln conf$$.file conf$$ 2>/dev/null; then
-  as_ln_s=ln
-else
-  as_ln_s='cp -p'
-fi
-rm -f conf$$ conf$$.exe conf$$.file
-
-if mkdir -p . 2>/dev/null; then
-  as_mkdir_p=:
-else
-  test -d ./-p && rmdir ./-p
-  as_mkdir_p=false
-fi
-
-as_executable_p="test -f"
-
-# Sed expression to map a string onto a valid CPP name.
-as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'"
-
-# Sed expression to map a string onto a valid variable name.
-as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'"
-
-
-# IFS
-# We need space, tab and new line, in precisely that order.
-as_nl='
-'
-IFS="  $as_nl"
-
-# CDPATH.
-$as_unset CDPATH
-
-
-# Name of the host.
-# hostname on some systems (SVR3.2, Linux) returns a bogus exit status,
-# so uname gets run too.
-ac_hostname=`(hostname || uname -n) 2>/dev/null | sed 1q`
-
-exec 6>&1
-
-#
-# Initializations.
-#
-ac_default_prefix=/usr/local
-ac_config_libobj_dir=.
-cross_compiling=no
-subdirs=
-MFLAGS=
-MAKEFLAGS=
-SHELL=${CONFIG_SHELL-/bin/sh}
-
-# Maximum number of lines to put in a shell here document.
-# This variable seems obsolete.  It should probably be removed, and
-# only ac_max_sed_lines should be used.
-: ${ac_max_here_lines=38}
-
-# Identity of this package.
-PACKAGE_NAME=
-PACKAGE_TARNAME=
-PACKAGE_VERSION=
-PACKAGE_STRING=
-PACKAGE_BUGREPORT=
-
-ac_unique_file="defs"
-ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS CC build build_cpu build_vendor build_os host host_cpu host_vendor host_os target target_cpu target_vendor target_os LIBOBJS LTLIBOBJS'
-ac_subst_files=''
-
-# Initialize some variables set by options.
-ac_init_help=
-ac_init_version=false
-# The variables have the same names as the options, with
-# dashes changed to underlines.
-cache_file=/dev/null
-exec_prefix=NONE
-no_create=
-no_recursion=
-prefix=NONE
-program_prefix=NONE
-program_suffix=NONE
-program_transform_name=s,x,x,
-silent=
-site=
-srcdir=
-verbose=
-x_includes=NONE
-x_libraries=NONE
-
-# Installation directory options.
-# These are left unexpanded so users can "make install exec_prefix=/foo"
-# and all the variables that are supposed to be based on exec_prefix
-# by default will actually change.
-# Use braces instead of parens because sh, perl, etc. also accept them.
-bindir='${exec_prefix}/bin'
-sbindir='${exec_prefix}/sbin'
-libexecdir='${exec_prefix}/libexec'
-datadir='${prefix}/share'
-sysconfdir='${prefix}/etc'
-sharedstatedir='${prefix}/com'
-localstatedir='${prefix}/var'
-libdir='${exec_prefix}/lib'
-includedir='${prefix}/include'
-oldincludedir='/usr/include'
-infodir='${prefix}/info'
-mandir='${prefix}/man'
-
-ac_prev=
-for ac_option
-do
-  # If the previous option needs an argument, assign it.
-  if test -n "$ac_prev"; then
-    eval "$ac_prev=\$ac_option"
-    ac_prev=
-    continue
-  fi
-
-  ac_optarg=`expr "x$ac_option" : 'x[^=]*=\(.*\)'`
-
-  # Accept the important Cygnus configure options, so we can diagnose typos.
-
-  case $ac_option in
-
-  -bindir | --bindir | --bindi | --bind | --bin | --bi)
-    ac_prev=bindir ;;
-  -bindir=* | --bindir=* | --bindi=* | --bind=* | --bin=* | --bi=*)
-    bindir=$ac_optarg ;;
-
-  -build | --build | --buil | --bui | --bu)
-    ac_prev=build_alias ;;
-  -build=* | --build=* | --buil=* | --bui=* | --bu=*)
-    build_alias=$ac_optarg ;;
-
-  -cache-file | --cache-file | --cache-fil | --cache-fi \
-  | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c)
-    ac_prev=cache_file ;;
-  -cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \
-  | --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* | --c=*)
-    cache_file=$ac_optarg ;;
-
-  --config-cache | -C)
-    cache_file=config.cache ;;
-
-  -datadir | --datadir | --datadi | --datad | --data | --dat | --da)
-    ac_prev=datadir ;;
-  -datadir=* | --datadir=* | --datadi=* | --datad=* | --data=* | --dat=* \
-  | --da=*)
-    datadir=$ac_optarg ;;
-
-  -disable-* | --disable-*)
-    ac_feature=`expr "x$ac_option" : 'x-*disable-\(.*\)'`
-    # Reject names that are not valid shell variable names.
-    expr "x$ac_feature" : ".*[^-_$as_cr_alnum]" >/dev/null &&
-      { echo "$as_me: error: invalid feature name: $ac_feature" >&2
-   { (exit 1); exit 1; }; }
-    ac_feature=`echo $ac_feature | sed 's/-/_/g'`
-    eval "enable_$ac_feature=no" ;;
-
-  -enable-* | --enable-*)
-    ac_feature=`expr "x$ac_option" : 'x-*enable-\([^=]*\)'`
-    # Reject names that are not valid shell variable names.
-    expr "x$ac_feature" : ".*[^-_$as_cr_alnum]" >/dev/null &&
-      { echo "$as_me: error: invalid feature name: $ac_feature" >&2
-   { (exit 1); exit 1; }; }
-    ac_feature=`echo $ac_feature | sed 's/-/_/g'`
-    case $ac_option in
-      *=*) ac_optarg=`echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"`;;
-      *) ac_optarg=yes ;;
-    esac
-    eval "enable_$ac_feature='$ac_optarg'" ;;
-
-  -exec-prefix | --exec_prefix | --exec-prefix | --exec-prefi \
-  | --exec-pref | --exec-pre | --exec-pr | --exec-p | --exec- \
-  | --exec | --exe | --ex)
-    ac_prev=exec_prefix ;;
-  -exec-prefix=* | --exec_prefix=* | --exec-prefix=* | --exec-prefi=* \
-  | --exec-pref=* | --exec-pre=* | --exec-pr=* | --exec-p=* | --exec-=* \
-  | --exec=* | --exe=* | --ex=*)
-    exec_prefix=$ac_optarg ;;
-
-  -gas | --gas | --ga | --g)
-    # Obsolete; use --with-gas.
-    with_gas=yes ;;
-
-  -help | --help | --hel | --he | -h)
-    ac_init_help=long ;;
-  -help=r* | --help=r* | --hel=r* | --he=r* | -hr*)
-    ac_init_help=recursive ;;
-  -help=s* | --help=s* | --hel=s* | --he=s* | -hs*)
-    ac_init_help=short ;;
-
-  -host | --host | --hos | --ho)
-    ac_prev=host_alias ;;
-  -host=* | --host=* | --hos=* | --ho=*)
-    host_alias=$ac_optarg ;;
-
-  -includedir | --includedir | --includedi | --included | --include \
-  | --includ | --inclu | --incl | --inc)
-    ac_prev=includedir ;;
-  -includedir=* | --includedir=* | --includedi=* | --included=* | --include=* \
-  | --includ=* | --inclu=* | --incl=* | --inc=*)
-    includedir=$ac_optarg ;;
-
-  -infodir | --infodir | --infodi | --infod | --info | --inf)
-    ac_prev=infodir ;;
-  -infodir=* | --infodir=* | --infodi=* | --infod=* | --info=* | --inf=*)
-    infodir=$ac_optarg ;;
-
-  -libdir | --libdir | --libdi | --libd)
-    ac_prev=libdir ;;
-  -libdir=* | --libdir=* | --libdi=* | --libd=*)
-    libdir=$ac_optarg ;;
-
-  -libexecdir | --libexecdir | --libexecdi | --libexecd | --libexec \
-  | --libexe | --libex | --libe)
-    ac_prev=libexecdir ;;
-  -libexecdir=* | --libexecdir=* | --libexecdi=* | --libexecd=* | --libexec=* \
-  | --libexe=* | --libex=* | --libe=*)
-    libexecdir=$ac_optarg ;;
-
-  -localstatedir | --localstatedir | --localstatedi | --localstated \
-  | --localstate | --localstat | --localsta | --localst \
-  | --locals | --local | --loca | --loc | --lo)
-    ac_prev=localstatedir ;;
-  -localstatedir=* | --localstatedir=* | --localstatedi=* | --localstated=* \
-  | --localstate=* | --localstat=* | --localsta=* | --localst=* \
-  | --locals=* | --local=* | --loca=* | --loc=* | --lo=*)
-    localstatedir=$ac_optarg ;;
-
-  -mandir | --mandir | --mandi | --mand | --man | --ma | --m)
-    ac_prev=mandir ;;
-  -mandir=* | --mandir=* | --mandi=* | --mand=* | --man=* | --ma=* | --m=*)
-    mandir=$ac_optarg ;;
-
-  -nfp | --nfp | --nf)
-    # Obsolete; use --without-fp.
-    with_fp=no ;;
-
-  -no-create | --no-create | --no-creat | --no-crea | --no-cre \
-  | --no-cr | --no-c | -n)
-    no_create=yes ;;
-
-  -no-recursion | --no-recursion | --no-recursio | --no-recursi \
-  | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r)
-    no_recursion=yes ;;
-
-  -oldincludedir | --oldincludedir | --oldincludedi | --oldincluded \
-  | --oldinclude | --oldinclud | --oldinclu | --oldincl | --oldinc \
-  | --oldin | --oldi | --old | --ol | --o)
-    ac_prev=oldincludedir ;;
-  -oldincludedir=* | --oldincludedir=* | --oldincludedi=* | --oldincluded=* \
-  | --oldinclude=* | --oldinclud=* | --oldinclu=* | --oldincl=* | --oldinc=* \
-  | --oldin=* | --oldi=* | --old=* | --ol=* | --o=*)
-    oldincludedir=$ac_optarg ;;
-
-  -prefix | --prefix | --prefi | --pref | --pre | --pr | --p)
-    ac_prev=prefix ;;
-  -prefix=* | --prefix=* | --prefi=* | --pref=* | --pre=* | --pr=* | --p=*)
-    prefix=$ac_optarg ;;
-
-  -program-prefix | --program-prefix | --program-prefi | --program-pref \
-  | --program-pre | --program-pr | --program-p)
-    ac_prev=program_prefix ;;
-  -program-prefix=* | --program-prefix=* | --program-prefi=* \
-  | --program-pref=* | --program-pre=* | --program-pr=* | --program-p=*)
-    program_prefix=$ac_optarg ;;
-
-  -program-suffix | --program-suffix | --program-suffi | --program-suff \
-  | --program-suf | --program-su | --program-s)
-    ac_prev=program_suffix ;;
-  -program-suffix=* | --program-suffix=* | --program-suffi=* \
-  | --program-suff=* | --program-suf=* | --program-su=* | --program-s=*)
-    program_suffix=$ac_optarg ;;
-
-  -program-transform-name | --program-transform-name \
-  | --program-transform-nam | --program-transform-na \
-  | --program-transform-n | --program-transform- \
-  | --program-transform | --program-transfor \
-  | --program-transfo | --program-transf \
-  | --program-trans | --program-tran \
-  | --progr-tra | --program-tr | --program-t)
-    ac_prev=program_transform_name ;;
-  -program-transform-name=* | --program-transform-name=* \
-  | --program-transform-nam=* | --program-transform-na=* \
-  | --program-transform-n=* | --program-transform-=* \
-  | --program-transform=* | --program-transfor=* \
-  | --program-transfo=* | --program-transf=* \
-  | --program-trans=* | --program-tran=* \
-  | --progr-tra=* | --program-tr=* | --program-t=*)
-    program_transform_name=$ac_optarg ;;
-
-  -q | -quiet | --quiet | --quie | --qui | --qu | --q \
-  | -silent | --silent | --silen | --sile | --sil)
-    silent=yes ;;
-
-  -sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb)
-    ac_prev=sbindir ;;
-  -sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \
-  | --sbi=* | --sb=*)
-    sbindir=$ac_optarg ;;
-
-  -sharedstatedir | --sharedstatedir | --sharedstatedi \
-  | --sharedstated | --sharedstate | --sharedstat | --sharedsta \
-  | --sharedst | --shareds | --shared | --share | --shar \
-  | --sha | --sh)
-    ac_prev=sharedstatedir ;;
-  -sharedstatedir=* | --sharedstatedir=* | --sharedstatedi=* \
-  | --sharedstated=* | --sharedstate=* | --sharedstat=* | --sharedsta=* \
-  | --sharedst=* | --shareds=* | --shared=* | --share=* | --shar=* \
-  | --sha=* | --sh=*)
-    sharedstatedir=$ac_optarg ;;
-
-  -site | --site | --sit)
-    ac_prev=site ;;
-  -site=* | --site=* | --sit=*)
-    site=$ac_optarg ;;
-
-  -srcdir | --srcdir | --srcdi | --srcd | --src | --sr)
-    ac_prev=srcdir ;;
-  -srcdir=* | --srcdir=* | --srcdi=* | --srcd=* | --src=* | --sr=*)
-    srcdir=$ac_optarg ;;
-
-  -sysconfdir | --sysconfdir | --sysconfdi | --sysconfd | --sysconf \
-  | --syscon | --sysco | --sysc | --sys | --sy)
-    ac_prev=sysconfdir ;;
-  -sysconfdir=* | --sysconfdir=* | --sysconfdi=* | --sysconfd=* | --sysconf=* \
-  | --syscon=* | --sysco=* | --sysc=* | --sys=* | --sy=*)
-    sysconfdir=$ac_optarg ;;
-
-  -target | --target | --targe | --targ | --tar | --ta | --t)
-    ac_prev=target_alias ;;
-  -target=* | --target=* | --targe=* | --targ=* | --tar=* | --ta=* | --t=*)
-    target_alias=$ac_optarg ;;
-
-  -v | -verbose | --verbose | --verbos | --verbo | --verb)
-    verbose=yes ;;
-
-  -version | --version | --versio | --versi | --vers | -V)
-    ac_init_version=: ;;
-
-  -with-* | --with-*)
-    ac_package=`expr "x$ac_option" : 'x-*with-\([^=]*\)'`
-    # Reject names that are not valid shell variable names.
-    expr "x$ac_package" : ".*[^-_$as_cr_alnum]" >/dev/null &&
-      { echo "$as_me: error: invalid package name: $ac_package" >&2
-   { (exit 1); exit 1; }; }
-    ac_package=`echo $ac_package| sed 's/-/_/g'`
-    case $ac_option in
-      *=*) ac_optarg=`echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"`;;
-      *) ac_optarg=yes ;;
-    esac
-    eval "with_$ac_package='$ac_optarg'" ;;
-
-  -without-* | --without-*)
-    ac_package=`expr "x$ac_option" : 'x-*without-\(.*\)'`
-    # Reject names that are not valid shell variable names.
-    expr "x$ac_package" : ".*[^-_$as_cr_alnum]" >/dev/null &&
-      { echo "$as_me: error: invalid package name: $ac_package" >&2
-   { (exit 1); exit 1; }; }
-    ac_package=`echo $ac_package | sed 's/-/_/g'`
-    eval "with_$ac_package=no" ;;
-
-  --x)
-    # Obsolete; use --with-x.
-    with_x=yes ;;
-
-  -x-includes | --x-includes | --x-include | --x-includ | --x-inclu \
-  | --x-incl | --x-inc | --x-in | --x-i)
-    ac_prev=x_includes ;;
-  -x-includes=* | --x-includes=* | --x-include=* | --x-includ=* | --x-inclu=* \
-  | --x-incl=* | --x-inc=* | --x-in=* | --x-i=*)
-    x_includes=$ac_optarg ;;
-
-  -x-libraries | --x-libraries | --x-librarie | --x-librari \
-  | --x-librar | --x-libra | --x-libr | --x-lib | --x-li | --x-l)
-    ac_prev=x_libraries ;;
-  -x-libraries=* | --x-libraries=* | --x-librarie=* | --x-librari=* \
-  | --x-librar=* | --x-libra=* | --x-libr=* | --x-lib=* | --x-li=* | --x-l=*)
-    x_libraries=$ac_optarg ;;
-
-  -*) { echo "$as_me: error: unrecognized option: $ac_option
-Try \`$0 --help' for more information." >&2
-   { (exit 1); exit 1; }; }
-    ;;
-
-  *=*)
-    ac_envvar=`expr "x$ac_option" : 'x\([^=]*\)='`
-    # Reject names that are not valid shell variable names.
-    expr "x$ac_envvar" : ".*[^_$as_cr_alnum]" >/dev/null &&
-      { echo "$as_me: error: invalid variable name: $ac_envvar" >&2
-   { (exit 1); exit 1; }; }
-    ac_optarg=`echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"`
-    eval "$ac_envvar='$ac_optarg'"
-    export $ac_envvar ;;
-
-  *)
-    # FIXME: should be removed in autoconf 3.0.
-    echo "$as_me: WARNING: you should use --build, --host, --target" >&2
-    expr "x$ac_option" : ".*[^-._$as_cr_alnum]" >/dev/null &&
-      echo "$as_me: WARNING: invalid host type: $ac_option" >&2
-    : ${build_alias=$ac_option} ${host_alias=$ac_option} ${target_alias=$ac_option}
-    ;;
-
-  esac
-done
-
-if test -n "$ac_prev"; then
-  ac_option=--`echo $ac_prev | sed 's/_/-/g'`
-  { echo "$as_me: error: missing argument to $ac_option" >&2
-   { (exit 1); exit 1; }; }
-fi
-
-# Be sure to have absolute paths.
-for ac_var in exec_prefix prefix
-do
-  eval ac_val=$`echo $ac_var`
-  case $ac_val in
-    [\\/$]* | ?:[\\/]* | NONE | '' ) ;;
-    *)  { echo "$as_me: error: expected an absolute directory name for --$ac_var: $ac_val" >&2
-   { (exit 1); exit 1; }; };;
-  esac
-done
-
-# Be sure to have absolute paths.
-for ac_var in bindir sbindir libexecdir datadir sysconfdir sharedstatedir \
-             localstatedir libdir includedir oldincludedir infodir mandir
-do
-  eval ac_val=$`echo $ac_var`
-  case $ac_val in
-    [\\/$]* | ?:[\\/]* ) ;;
-    *)  { echo "$as_me: error: expected an absolute directory name for --$ac_var: $ac_val" >&2
-   { (exit 1); exit 1; }; };;
-  esac
-done
-
-# There might be people who depend on the old broken behavior: `$host'
-# used to hold the argument of --host etc.
-# FIXME: To remove some day.
-build=$build_alias
-host=$host_alias
-target=$target_alias
-
-# FIXME: To remove some day.
-if test "x$host_alias" != x; then
-  if test "x$build_alias" = x; then
-    cross_compiling=maybe
-    echo "$as_me: WARNING: If you wanted to set the --build type, don't use --host.
-    If a cross compiler is detected then cross compile mode will be used." >&2
-  elif test "x$build_alias" != "x$host_alias"; then
-    cross_compiling=yes
-  fi
-fi
-
-ac_tool_prefix=
-test -n "$host_alias" && ac_tool_prefix=$host_alias-
-
-test "$silent" = yes && exec 6>/dev/null
-
-
-# Find the source files, if location was not specified.
-if test -z "$srcdir"; then
-  ac_srcdir_defaulted=yes
-  # Try the directory containing this script, then its parent.
-  ac_confdir=`(dirname "$0") 2>/dev/null ||
-$as_expr X"$0" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
-        X"$0" : 'X\(//\)[^/]' \| \
-        X"$0" : 'X\(//\)$' \| \
-        X"$0" : 'X\(/\)' \| \
-        .     : '\(.\)' 2>/dev/null ||
-echo X"$0" |
-    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
-         /^X\(\/\/\)[^/].*/{ s//\1/; q; }
-         /^X\(\/\/\)$/{ s//\1/; q; }
-         /^X\(\/\).*/{ s//\1/; q; }
-         s/.*/./; q'`
-  srcdir=$ac_confdir
-  if test ! -r $srcdir/$ac_unique_file; then
-    srcdir=..
-  fi
-else
-  ac_srcdir_defaulted=no
-fi
-if test ! -r $srcdir/$ac_unique_file; then
-  if test "$ac_srcdir_defaulted" = yes; then
-    { echo "$as_me: error: cannot find sources ($ac_unique_file) in $ac_confdir or .." >&2
-   { (exit 1); exit 1; }; }
-  else
-    { echo "$as_me: error: cannot find sources ($ac_unique_file) in $srcdir" >&2
-   { (exit 1); exit 1; }; }
-  fi
-fi
-(cd $srcdir && test -r ./$ac_unique_file) 2>/dev/null ||
-  { echo "$as_me: error: sources are in $srcdir, but \`cd $srcdir' does not work" >&2
-   { (exit 1); exit 1; }; }
-srcdir=`echo "$srcdir" | sed 's%\([^\\/]\)[\\/]*$%\1%'`
-ac_env_build_alias_set=${build_alias+set}
-ac_env_build_alias_value=$build_alias
-ac_cv_env_build_alias_set=${build_alias+set}
-ac_cv_env_build_alias_value=$build_alias
-ac_env_host_alias_set=${host_alias+set}
-ac_env_host_alias_value=$host_alias
-ac_cv_env_host_alias_set=${host_alias+set}
-ac_cv_env_host_alias_value=$host_alias
-ac_env_target_alias_set=${target_alias+set}
-ac_env_target_alias_value=$target_alias
-ac_cv_env_target_alias_set=${target_alias+set}
-ac_cv_env_target_alias_value=$target_alias
-
-#
-# Report the --help message.
-#
-if test "$ac_init_help" = "long"; then
-  # Omit some internal or obsolete options to make the list less imposing.
-  # This message is too long to be a string in the A/UX 3.1 sh.
-  cat <<_ACEOF
-\`configure' configures this package to adapt to many kinds of systems.
-
-Usage: $0 [OPTION]... [VAR=VALUE]...
-
-To assign environment variables (e.g., CC, CFLAGS...), specify them as
-VAR=VALUE.  See below for descriptions of some of the useful variables.
-
-Defaults for the options are specified in brackets.
-
-Configuration:
-  -h, --help              display this help and exit
-      --help=short        display options specific to this package
-      --help=recursive    display the short help of all the included packages
-  -V, --version           display version information and exit
-  -q, --quiet, --silent   do not print \`checking...' messages
-      --cache-file=FILE   cache test results in FILE [disabled]
-  -C, --config-cache      alias for \`--cache-file=config.cache'
-  -n, --no-create         do not create output files
-      --srcdir=DIR        find the sources in DIR [configure dir or \`..']
-
-_ACEOF
-
-  cat <<_ACEOF
-Installation directories:
-  --prefix=PREFIX         install architecture-independent files in PREFIX
-                         [$ac_default_prefix]
-  --exec-prefix=EPREFIX   install architecture-dependent files in EPREFIX
-                         [PREFIX]
-
-By default, \`make install' will install all the files in
-\`$ac_default_prefix/bin', \`$ac_default_prefix/lib' etc.  You can specify
-an installation prefix other than \`$ac_default_prefix' using \`--prefix',
-for instance \`--prefix=\$HOME'.
-
-For better control, use the options below.
-
-Fine tuning of the installation directories:
-  --bindir=DIR           user executables [EPREFIX/bin]
-  --sbindir=DIR          system admin executables [EPREFIX/sbin]
-  --libexecdir=DIR       program executables [EPREFIX/libexec]
-  --datadir=DIR          read-only architecture-independent data [PREFIX/share]
-  --sysconfdir=DIR       read-only single-machine data [PREFIX/etc]
-  --sharedstatedir=DIR   modifiable architecture-independent data [PREFIX/com]
-  --localstatedir=DIR    modifiable single-machine data [PREFIX/var]
-  --libdir=DIR           object code libraries [EPREFIX/lib]
-  --includedir=DIR       C header files [PREFIX/include]
-  --oldincludedir=DIR    C header files for non-gcc [/usr/include]
-  --infodir=DIR          info documentation [PREFIX/info]
-  --mandir=DIR           man documentation [PREFIX/man]
-_ACEOF
-
-  cat <<\_ACEOF
-
-System types:
-  --build=BUILD     configure for building on BUILD [guessed]
-  --host=HOST       cross-compile to build programs to run on HOST [BUILD]
-  --target=TARGET   configure for building compilers for TARGET [HOST]
-_ACEOF
-fi
-
-if test -n "$ac_init_help"; then
-
-  cat <<\_ACEOF
-
-_ACEOF
-fi
-
-if test "$ac_init_help" = "recursive"; then
-  # If there are subdirs, report their specific --help.
-  ac_popdir=`pwd`
-  for ac_dir in : $ac_subdirs_all; do test "x$ac_dir" = x: && continue
-    test -d $ac_dir || continue
-    ac_builddir=.
-
-if test "$ac_dir" != .; then
-  ac_dir_suffix=/`echo "$ac_dir" | sed 's,^\.[\\/],,'`
-  # A "../" for each directory in $ac_dir_suffix.
-  ac_top_builddir=`echo "$ac_dir_suffix" | sed 's,/[^\\/]*,../,g'`
-else
-  ac_dir_suffix= ac_top_builddir=
-fi
-
-case $srcdir in
-  .)  # No --srcdir option.  We are building in place.
-    ac_srcdir=.
-    if test -z "$ac_top_builddir"; then
-       ac_top_srcdir=.
-    else
-       ac_top_srcdir=`echo $ac_top_builddir | sed 's,/$,,'`
-    fi ;;
-  [\\/]* | ?:[\\/]* )  # Absolute path.
-    ac_srcdir=$srcdir$ac_dir_suffix;
-    ac_top_srcdir=$srcdir ;;
-  *) # Relative path.
-    ac_srcdir=$ac_top_builddir$srcdir$ac_dir_suffix
-    ac_top_srcdir=$ac_top_builddir$srcdir ;;
-esac
-
-# Do not use `cd foo && pwd` to compute absolute paths, because
-# the directories may not exist.
-case `pwd` in
-.) ac_abs_builddir="$ac_dir";;
-*)
-  case "$ac_dir" in
-  .) ac_abs_builddir=`pwd`;;
-  [\\/]* | ?:[\\/]* ) ac_abs_builddir="$ac_dir";;
-  *) ac_abs_builddir=`pwd`/"$ac_dir";;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_top_builddir=${ac_top_builddir}.;;
-*)
-  case ${ac_top_builddir}. in
-  .) ac_abs_top_builddir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_top_builddir=${ac_top_builddir}.;;
-  *) ac_abs_top_builddir=$ac_abs_builddir/${ac_top_builddir}.;;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_srcdir=$ac_srcdir;;
-*)
-  case $ac_srcdir in
-  .) ac_abs_srcdir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_srcdir=$ac_srcdir;;
-  *) ac_abs_srcdir=$ac_abs_builddir/$ac_srcdir;;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_top_srcdir=$ac_top_srcdir;;
-*)
-  case $ac_top_srcdir in
-  .) ac_abs_top_srcdir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_top_srcdir=$ac_top_srcdir;;
-  *) ac_abs_top_srcdir=$ac_abs_builddir/$ac_top_srcdir;;
-  esac;;
-esac
-
-    cd $ac_dir
-    # Check for guested configure; otherwise get Cygnus style configure.
-    if test -f $ac_srcdir/configure.gnu; then
-      echo
-      $SHELL $ac_srcdir/configure.gnu  --help=recursive
-    elif test -f $ac_srcdir/configure; then
-      echo
-      $SHELL $ac_srcdir/configure  --help=recursive
-    elif test -f $ac_srcdir/configure.ac ||
-          test -f $ac_srcdir/configure.in; then
-      echo
-      $ac_configure --help
-    else
-      echo "$as_me: WARNING: no configuration information is in $ac_dir" >&2
-    fi
-    cd $ac_popdir
-  done
-fi
-
-test -n "$ac_init_help" && exit 0
-if $ac_init_version; then
-  cat <<\_ACEOF
-
-Copyright (C) 2003 Free Software Foundation, Inc.
-This configure script is free software; the Free Software Foundation
-gives unlimited permission to copy, distribute and modify it.
-_ACEOF
-  exit 0
-fi
-exec 5>config.log
-cat >&5 <<_ACEOF
-This file contains any messages produced by compilers while
-running configure, to aid debugging if configure makes a mistake.
-
-It was created by $as_me, which was
-generated by GNU Autoconf 2.59.  Invocation command line was
-
-  $ $0 $@
-
-_ACEOF
-{
-cat <<_ASUNAME
-## --------- ##
-## Platform. ##
-## --------- ##
-
-hostname = `(hostname || uname -n) 2>/dev/null | sed 1q`
-uname -m = `(uname -m) 2>/dev/null || echo unknown`
-uname -r = `(uname -r) 2>/dev/null || echo unknown`
-uname -s = `(uname -s) 2>/dev/null || echo unknown`
-uname -v = `(uname -v) 2>/dev/null || echo unknown`
-
-/usr/bin/uname -p = `(/usr/bin/uname -p) 2>/dev/null || echo unknown`
-/bin/uname -X     = `(/bin/uname -X) 2>/dev/null     || echo unknown`
-
-/bin/arch              = `(/bin/arch) 2>/dev/null              || echo unknown`
-/usr/bin/arch -k       = `(/usr/bin/arch -k) 2>/dev/null       || echo unknown`
-/usr/convex/getsysinfo = `(/usr/convex/getsysinfo) 2>/dev/null || echo unknown`
-hostinfo               = `(hostinfo) 2>/dev/null               || echo unknown`
-/bin/machine           = `(/bin/machine) 2>/dev/null           || echo unknown`
-/usr/bin/oslevel       = `(/usr/bin/oslevel) 2>/dev/null       || echo unknown`
-/bin/universe          = `(/bin/universe) 2>/dev/null          || echo unknown`
-
-_ASUNAME
-
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  echo "PATH: $as_dir"
-done
-
-} >&5
-
-cat >&5 <<_ACEOF
-
-
-## ----------- ##
-## Core tests. ##
-## ----------- ##
-
-_ACEOF
-
-
-# Keep a trace of the command line.
-# Strip out --no-create and --no-recursion so they do not pile up.
-# Strip out --silent because we don't want to record it for future runs.
-# Also quote any args containing shell meta-characters.
-# Make two passes to allow for proper duplicate-argument suppression.
-ac_configure_args=
-ac_configure_args0=
-ac_configure_args1=
-ac_sep=
-ac_must_keep_next=false
-for ac_pass in 1 2
-do
-  for ac_arg
-  do
-    case $ac_arg in
-    -no-create | --no-c* | -n | -no-recursion | --no-r*) continue ;;
-    -q | -quiet | --quiet | --quie | --qui | --qu | --q \
-    | -silent | --silent | --silen | --sile | --sil)
-      continue ;;
-    *" "*|*"   "*|*[\[\]\~\#\$\^\&\*\(\)\{\}\\\|\;\<\>\?\"\']*)
-      ac_arg=`echo "$ac_arg" | sed "s/'/'\\\\\\\\''/g"` ;;
-    esac
-    case $ac_pass in
-    1) ac_configure_args0="$ac_configure_args0 '$ac_arg'" ;;
-    2)
-      ac_configure_args1="$ac_configure_args1 '$ac_arg'"
-      if test $ac_must_keep_next = true; then
-       ac_must_keep_next=false # Got value, back to normal.
-      else
-       case $ac_arg in
-         *=* | --config-cache | -C | -disable-* | --disable-* \
-         | -enable-* | --enable-* | -gas | --g* | -nfp | --nf* \
-         | -q | -quiet | --q* | -silent | --sil* | -v | -verb* \
-         | -with-* | --with-* | -without-* | --without-* | --x)
-           case "$ac_configure_args0 " in
-             "$ac_configure_args1"*" '$ac_arg' "* ) continue ;;
-           esac
-           ;;
-         -* ) ac_must_keep_next=true ;;
-       esac
-      fi
-      ac_configure_args="$ac_configure_args$ac_sep'$ac_arg'"
-      # Get rid of the leading space.
-      ac_sep=" "
-      ;;
-    esac
-  done
-done
-$as_unset ac_configure_args0 || test "${ac_configure_args0+set}" != set || { ac_configure_args0=; export ac_configure_args0; }
-$as_unset ac_configure_args1 || test "${ac_configure_args1+set}" != set || { ac_configure_args1=; export ac_configure_args1; }
-
-# When interrupted or exit'd, cleanup temporary files, and complete
-# config.log.  We remove comments because anyway the quotes in there
-# would cause problems or look ugly.
-# WARNING: Be sure not to use single quotes in there, as some shells,
-# such as our DU 5.0 friend, will then `close' the trap.
-trap 'exit_status=$?
-  # Save into config.log some information that might help in debugging.
-  {
-    echo
-
-    cat <<\_ASBOX
-## ---------------- ##
-## Cache variables. ##
-## ---------------- ##
-_ASBOX
-    echo
-    # The following way of writing the cache mishandles newlines in values,
-{
-  (set) 2>&1 |
-    case `(ac_space='"'"' '"'"'; set | grep ac_space) 2>&1` in
-    *ac_space=\ *)
-      sed -n \
-       "s/'"'"'/'"'"'\\\\'"'"''"'"'/g;
-         s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='"'"'\\2'"'"'/p"
-      ;;
-    *)
-      sed -n \
-       "s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1=\\2/p"
-      ;;
-    esac;
-}
-    echo
-
-    cat <<\_ASBOX
-## ----------------- ##
-## Output variables. ##
-## ----------------- ##
-_ASBOX
-    echo
-    for ac_var in $ac_subst_vars
-    do
-      eval ac_val=$`echo $ac_var`
-      echo "$ac_var='"'"'$ac_val'"'"'"
-    done | sort
-    echo
-
-    if test -n "$ac_subst_files"; then
-      cat <<\_ASBOX
-## ------------- ##
-## Output files. ##
-## ------------- ##
-_ASBOX
-      echo
-      for ac_var in $ac_subst_files
-      do
-       eval ac_val=$`echo $ac_var`
-       echo "$ac_var='"'"'$ac_val'"'"'"
-      done | sort
-      echo
-    fi
-
-    if test -s confdefs.h; then
-      cat <<\_ASBOX
-## ----------- ##
-## confdefs.h. ##
-## ----------- ##
-_ASBOX
-      echo
-      sed "/^$/d" confdefs.h | sort
-      echo
-    fi
-    test "$ac_signal" != 0 &&
-      echo "$as_me: caught signal $ac_signal"
-    echo "$as_me: exit $exit_status"
-  } >&5
-  rm -f core *.core &&
-  rm -rf conftest* confdefs* conf$$* $ac_clean_files &&
-    exit $exit_status
-     ' 0
-for ac_signal in 1 2 13 15; do
-  trap 'ac_signal='$ac_signal'; { (exit 1); exit 1; }' $ac_signal
-done
-ac_signal=0
-
-# confdefs.h avoids OS command line length limits that DEFS can exceed.
-rm -rf conftest* confdefs.h
-# AIX cpp loses on an empty file, so make sure it contains at least a newline.
-echo >confdefs.h
-
-# Predefined preprocessor variables.
-
-cat >>confdefs.h <<_ACEOF
-#define PACKAGE_NAME "$PACKAGE_NAME"
-_ACEOF
-
-
-cat >>confdefs.h <<_ACEOF
-#define PACKAGE_TARNAME "$PACKAGE_TARNAME"
-_ACEOF
-
-
-cat >>confdefs.h <<_ACEOF
-#define PACKAGE_VERSION "$PACKAGE_VERSION"
-_ACEOF
-
-
-cat >>confdefs.h <<_ACEOF
-#define PACKAGE_STRING "$PACKAGE_STRING"
-_ACEOF
-
-
-cat >>confdefs.h <<_ACEOF
-#define PACKAGE_BUGREPORT "$PACKAGE_BUGREPORT"
-_ACEOF
-
-
-# Let the site file select an alternate cache file if it wants to.
-# Prefer explicitly selected file to automatically selected ones.
-if test -z "$CONFIG_SITE"; then
-  if test "x$prefix" != xNONE; then
-    CONFIG_SITE="$prefix/share/config.site $prefix/etc/config.site"
-  else
-    CONFIG_SITE="$ac_default_prefix/share/config.site $ac_default_prefix/etc/config.site"
-  fi
-fi
-for ac_site_file in $CONFIG_SITE; do
-  if test -r "$ac_site_file"; then
-    { echo "$as_me:$LINENO: loading site script $ac_site_file" >&5
-echo "$as_me: loading site script $ac_site_file" >&6;}
-    sed 's/^/| /' "$ac_site_file" >&5
-    . "$ac_site_file"
-  fi
-done
-
-if test -r "$cache_file"; then
-  # Some versions of bash will fail to source /dev/null (special
-  # files actually), so we avoid doing that.
-  if test -f "$cache_file"; then
-    { echo "$as_me:$LINENO: loading cache $cache_file" >&5
-echo "$as_me: loading cache $cache_file" >&6;}
-    case $cache_file in
-      [\\/]* | ?:[\\/]* ) . $cache_file;;
-      *)                      . ./$cache_file;;
-    esac
-  fi
-else
-  { echo "$as_me:$LINENO: creating cache $cache_file" >&5
-echo "$as_me: creating cache $cache_file" >&6;}
-  >$cache_file
-fi
-
-# Check that the precious variables saved in the cache have kept the same
-# value.
-ac_cache_corrupted=false
-for ac_var in `(set) 2>&1 |
-              sed -n 's/^ac_env_\([a-zA-Z_0-9]*\)_set=.*/\1/p'`; do
-  eval ac_old_set=\$ac_cv_env_${ac_var}_set
-  eval ac_new_set=\$ac_env_${ac_var}_set
-  eval ac_old_val="\$ac_cv_env_${ac_var}_value"
-  eval ac_new_val="\$ac_env_${ac_var}_value"
-  case $ac_old_set,$ac_new_set in
-    set,)
-      { echo "$as_me:$LINENO: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&5
-echo "$as_me: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&2;}
-      ac_cache_corrupted=: ;;
-    ,set)
-      { echo "$as_me:$LINENO: error: \`$ac_var' was not set in the previous run" >&5
-echo "$as_me: error: \`$ac_var' was not set in the previous run" >&2;}
-      ac_cache_corrupted=: ;;
-    ,);;
-    *)
-      if test "x$ac_old_val" != "x$ac_new_val"; then
-       { echo "$as_me:$LINENO: error: \`$ac_var' has changed since the previous run:" >&5
-echo "$as_me: error: \`$ac_var' has changed since the previous run:" >&2;}
-       { echo "$as_me:$LINENO:   former value:  $ac_old_val" >&5
-echo "$as_me:   former value:  $ac_old_val" >&2;}
-       { echo "$as_me:$LINENO:   current value: $ac_new_val" >&5
-echo "$as_me:   current value: $ac_new_val" >&2;}
-       ac_cache_corrupted=:
-      fi;;
-  esac
-  # Pass precious variables to config.status.
-  if test "$ac_new_set" = set; then
-    case $ac_new_val in
-    *" "*|*"   "*|*[\[\]\~\#\$\^\&\*\(\)\{\}\\\|\;\<\>\?\"\']*)
-      ac_arg=$ac_var=`echo "$ac_new_val" | sed "s/'/'\\\\\\\\''/g"` ;;
-    *) ac_arg=$ac_var=$ac_new_val ;;
-    esac
-    case " $ac_configure_args " in
-      *" '$ac_arg' "*) ;; # Avoid dups.  Use of quotes ensures accuracy.
-      *) ac_configure_args="$ac_configure_args '$ac_arg'" ;;
-    esac
-  fi
-done
-if $ac_cache_corrupted; then
-  { echo "$as_me:$LINENO: error: changes in the environment can compromise the build" >&5
-echo "$as_me: error: changes in the environment can compromise the build" >&2;}
-  { { echo "$as_me:$LINENO: error: run \`make distclean' and/or \`rm $cache_file' and start over" >&5
-echo "$as_me: error: run \`make distclean' and/or \`rm $cache_file' and start over" >&2;}
-   { (exit 1); exit 1; }; }
-fi
-
-ac_ext=c
-ac_cpp='$CPP $CPPFLAGS'
-ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
-ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
-ac_compiler_gnu=$ac_cv_c_compiler_gnu
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-CC=${CC-cc}
-
-ac_aux_dir=
-for ac_dir in `cd $srcdir;pwd`/../../.. $srcdir/`cd $srcdir;pwd`/../../..; do
-  if test -f $ac_dir/install-sh; then
-    ac_aux_dir=$ac_dir
-    ac_install_sh="$ac_aux_dir/install-sh -c"
-    break
-  elif test -f $ac_dir/install.sh; then
-    ac_aux_dir=$ac_dir
-    ac_install_sh="$ac_aux_dir/install.sh -c"
-    break
-  elif test -f $ac_dir/shtool; then
-    ac_aux_dir=$ac_dir
-    ac_install_sh="$ac_aux_dir/shtool install -c"
-    break
-  fi
-done
-if test -z "$ac_aux_dir"; then
-  { { echo "$as_me:$LINENO: error: cannot find install-sh or install.sh in \`cd $srcdir;pwd\`/../../.. $srcdir/\`cd $srcdir;pwd\`/../../.." >&5
-echo "$as_me: error: cannot find install-sh or install.sh in \`cd $srcdir;pwd\`/../../.. $srcdir/\`cd $srcdir;pwd\`/../../.." >&2;}
-   { (exit 1); exit 1; }; }
-fi
-ac_config_guess="$SHELL $ac_aux_dir/config.guess"
-ac_config_sub="$SHELL $ac_aux_dir/config.sub"
-ac_configure="$SHELL $ac_aux_dir/configure" # This should be Cygnus configure.
-
-# Make sure we can run config.sub.
-$ac_config_sub sun4 >/dev/null 2>&1 ||
-  { { echo "$as_me:$LINENO: error: cannot run $ac_config_sub" >&5
-echo "$as_me: error: cannot run $ac_config_sub" >&2;}
-   { (exit 1); exit 1; }; }
-
-echo "$as_me:$LINENO: checking build system type" >&5
-echo $ECHO_N "checking build system type... $ECHO_C" >&6
-if test "${ac_cv_build+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_cv_build_alias=$build_alias
-test -z "$ac_cv_build_alias" &&
-  ac_cv_build_alias=`$ac_config_guess`
-test -z "$ac_cv_build_alias" &&
-  { { echo "$as_me:$LINENO: error: cannot guess build type; you must specify one" >&5
-echo "$as_me: error: cannot guess build type; you must specify one" >&2;}
-   { (exit 1); exit 1; }; }
-ac_cv_build=`$ac_config_sub $ac_cv_build_alias` ||
-  { { echo "$as_me:$LINENO: error: $ac_config_sub $ac_cv_build_alias failed" >&5
-echo "$as_me: error: $ac_config_sub $ac_cv_build_alias failed" >&2;}
-   { (exit 1); exit 1; }; }
-
-fi
-echo "$as_me:$LINENO: result: $ac_cv_build" >&5
-echo "${ECHO_T}$ac_cv_build" >&6
-build=$ac_cv_build
-build_cpu=`echo $ac_cv_build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
-build_vendor=`echo $ac_cv_build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
-build_os=`echo $ac_cv_build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
-
-
-echo "$as_me:$LINENO: checking host system type" >&5
-echo $ECHO_N "checking host system type... $ECHO_C" >&6
-if test "${ac_cv_host+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_cv_host_alias=$host_alias
-test -z "$ac_cv_host_alias" &&
-  ac_cv_host_alias=$ac_cv_build_alias
-ac_cv_host=`$ac_config_sub $ac_cv_host_alias` ||
-  { { echo "$as_me:$LINENO: error: $ac_config_sub $ac_cv_host_alias failed" >&5
-echo "$as_me: error: $ac_config_sub $ac_cv_host_alias failed" >&2;}
-   { (exit 1); exit 1; }; }
-
-fi
-echo "$as_me:$LINENO: result: $ac_cv_host" >&5
-echo "${ECHO_T}$ac_cv_host" >&6
-host=$ac_cv_host
-host_cpu=`echo $ac_cv_host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
-host_vendor=`echo $ac_cv_host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
-host_os=`echo $ac_cv_host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
-
-
-echo "$as_me:$LINENO: checking target system type" >&5
-echo $ECHO_N "checking target system type... $ECHO_C" >&6
-if test "${ac_cv_target+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_cv_target_alias=$target_alias
-test "x$ac_cv_target_alias" = "x" &&
-  ac_cv_target_alias=$ac_cv_host_alias
-ac_cv_target=`$ac_config_sub $ac_cv_target_alias` ||
-  { { echo "$as_me:$LINENO: error: $ac_config_sub $ac_cv_target_alias failed" >&5
-echo "$as_me: error: $ac_config_sub $ac_cv_target_alias failed" >&2;}
-   { (exit 1); exit 1; }; }
-
-fi
-echo "$as_me:$LINENO: result: $ac_cv_target" >&5
-echo "${ECHO_T}$ac_cv_target" >&6
-target=$ac_cv_target
-target_cpu=`echo $ac_cv_target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
-target_vendor=`echo $ac_cv_target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
-target_os=`echo $ac_cv_target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
-
-
-# The aliases save the names the user supplied, while $host etc.
-# will get canonicalized.
-test -n "$target_alias" &&
-  test "$program_prefix$program_suffix$program_transform_name" = \
-    NONENONEs,x,x, &&
-  program_prefix=${target_alias}-
-
-
-
-          ac_config_files="$ac_config_files Makefile"
-cat >confcache <<\_ACEOF
-# This file is a shell script that caches the results of configure
-# tests run on this system so they can be shared between configure
-# scripts and configure runs, see configure's option --config-cache.
-# It is not useful on other systems.  If it contains results you don't
-# want to keep, you may remove or edit it.
-#
-# config.status only pays attention to the cache file if you give it
-# the --recheck option to rerun configure.
-#
-# `ac_cv_env_foo' variables (set or unset) will be overridden when
-# loading this file, other *unset* `ac_cv_foo' will be assigned the
-# following values.
-
-_ACEOF
-
-# The following way of writing the cache mishandles newlines in values,
-# but we know of no workaround that is simple, portable, and efficient.
-# So, don't put newlines in cache variables' values.
-# Ultrix sh set writes to stderr and can't be redirected directly,
-# and sets the high bit in the cache file unless we assign to the vars.
-{
-  (set) 2>&1 |
-    case `(ac_space=' '; set | grep ac_space) 2>&1` in
-    *ac_space=\ *)
-      # `set' does not quote correctly, so add quotes (double-quote
-      # substitution turns \\\\ into \\, and sed turns \\ into \).
-      sed -n \
-       "s/'/'\\\\''/g;
-         s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p"
-      ;;
-    *)
-      # `set' quotes correctly as required by POSIX, so do not add quotes.
-      sed -n \
-       "s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1=\\2/p"
-      ;;
-    esac;
-} |
-  sed '
-     t clear
-     : clear
-     s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/
-     t end
-     /^ac_cv_env/!s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/
-     : end' >>confcache
-if diff $cache_file confcache >/dev/null 2>&1; then :; else
-  if test -w $cache_file; then
-    test "x$cache_file" != "x/dev/null" && echo "updating cache $cache_file"
-    cat confcache >$cache_file
-  else
-    echo "not updating unwritable cache $cache_file"
-  fi
-fi
-rm -f confcache
-
-test "x$prefix" = xNONE && prefix=$ac_default_prefix
-# Let make expand exec_prefix.
-test "x$exec_prefix" = xNONE && exec_prefix='${prefix}'
-
-# VPATH may cause trouble with some makes, so we remove $(srcdir),
-# ${srcdir} and @srcdir@ from VPATH if srcdir is ".", strip leading and
-# trailing colons and then remove the whole line if VPATH becomes empty
-# (actually we leave an empty line to preserve line numbers).
-if test "x$srcdir" = x.; then
-  ac_vpsub='/^[         ]*VPATH[        ]*=/{
-s/:*\$(srcdir):*/:/;
-s/:*\${srcdir}:*/:/;
-s/:*@srcdir@:*/:/;
-s/^\([^=]*=[    ]*\):*/\1/;
-s/:*$//;
-s/^[^=]*=[      ]*$//;
-}'
-fi
-
-# Transform confdefs.h into DEFS.
-# Protect against shell expansion while executing Makefile rules.
-# Protect against Makefile macro expansion.
-#
-# If the first sed substitution is executed (which looks for macros that
-# take arguments), then we branch to the quote section.  Otherwise,
-# look for a macro that doesn't take arguments.
-cat >confdef2opt.sed <<\_ACEOF
-t clear
-: clear
-s,^[    ]*#[    ]*define[       ][      ]*\([^  (][^    (]*([^)]*)\)[   ]*\(.*\),-D\1=\2,g
-t quote
-s,^[    ]*#[    ]*define[       ][      ]*\([^  ][^     ]*\)[   ]*\(.*\),-D\1=\2,g
-t quote
-d
-: quote
-s,[     `~#$^&*(){}\\|;'"<>?],\\&,g
-s,\[,\\&,g
-s,\],\\&,g
-s,\$,$$,g
-p
-_ACEOF
-# We use echo to avoid assuming a particular line-breaking character.
-# The extra dot is to prevent the shell from consuming trailing
-# line-breaks from the sub-command output.  A line-break within
-# single-quotes doesn't work because, if this script is created in a
-# platform that uses two characters for line-breaks (e.g., DOS), tr
-# would break.
-ac_LF_and_DOT=`echo; echo .`
-DEFS=`sed -n -f confdef2opt.sed confdefs.h | tr "$ac_LF_and_DOT" ' .'`
-rm -f confdef2opt.sed
-
-
-ac_libobjs=
-ac_ltlibobjs=
-for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue
-  # 1. Remove the extension, and $U if already installed.
-  ac_i=`echo "$ac_i" |
-        sed 's/\$U\././;s/\.o$//;s/\.obj$//'`
-  # 2. Add them.
-  ac_libobjs="$ac_libobjs $ac_i\$U.$ac_objext"
-  ac_ltlibobjs="$ac_ltlibobjs $ac_i"'$U.lo'
-done
-LIBOBJS=$ac_libobjs
-
-LTLIBOBJS=$ac_ltlibobjs
-
-
-
-: ${CONFIG_STATUS=./config.status}
-ac_clean_files_save=$ac_clean_files
-ac_clean_files="$ac_clean_files $CONFIG_STATUS"
-{ echo "$as_me:$LINENO: creating $CONFIG_STATUS" >&5
-echo "$as_me: creating $CONFIG_STATUS" >&6;}
-cat >$CONFIG_STATUS <<_ACEOF
-#! $SHELL
-# Generated by $as_me.
-# Run this file to recreate the current configuration.
-# Compiler output produced by configure, useful for debugging
-# configure, is in config.log if it exists.
-
-debug=false
-ac_cs_recheck=false
-ac_cs_silent=false
-SHELL=\${CONFIG_SHELL-$SHELL}
-_ACEOF
-
-cat >>$CONFIG_STATUS <<\_ACEOF
-## --------------------- ##
-## M4sh Initialization.  ##
-## --------------------- ##
-
-# Be Bourne compatible
-if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then
-  emulate sh
-  NULLCMD=:
-  # Zsh 3.x and 4.x performs word splitting on ${1+"$@"}, which
-  # is contrary to our usage.  Disable this feature.
-  alias -g '${1+"$@"}'='"$@"'
-elif test -n "${BASH_VERSION+set}" && (set -o posix) >/dev/null 2>&1; then
-  set -o posix
-fi
-DUALCASE=1; export DUALCASE # for MKS sh
-
-# Support unset when possible.
-if ( (MAIL=60; unset MAIL) || exit) >/dev/null 2>&1; then
-  as_unset=unset
-else
-  as_unset=false
-fi
-
-
-# Work around bugs in pre-3.0 UWIN ksh.
-$as_unset ENV MAIL MAILPATH
-PS1='$ '
-PS2='> '
-PS4='+ '
-
-# NLS nuisances.
-for as_var in \
-  LANG LANGUAGE LC_ADDRESS LC_ALL LC_COLLATE LC_CTYPE LC_IDENTIFICATION \
-  LC_MEASUREMENT LC_MESSAGES LC_MONETARY LC_NAME LC_NUMERIC LC_PAPER \
-  LC_TELEPHONE LC_TIME
-do
-  if (set +x; test -z "`(eval $as_var=C; export $as_var) 2>&1`"); then
-    eval $as_var=C; export $as_var
-  else
-    $as_unset $as_var
-  fi
-done
-
-# Required to use basename.
-if expr a : '\(a\)' >/dev/null 2>&1; then
-  as_expr=expr
-else
-  as_expr=false
-fi
-
-if (basename /) >/dev/null 2>&1 && test "X`basename / 2>&1`" = "X/"; then
-  as_basename=basename
-else
-  as_basename=false
-fi
-
-
-# Name of the executable.
-as_me=`$as_basename "$0" ||
-$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \
-        X"$0" : 'X\(//\)$' \| \
-        X"$0" : 'X\(/\)$' \| \
-        .     : '\(.\)' 2>/dev/null ||
-echo X/"$0" |
-    sed '/^.*\/\([^/][^/]*\)\/*$/{ s//\1/; q; }
-         /^X\/\(\/\/\)$/{ s//\1/; q; }
-         /^X\/\(\/\).*/{ s//\1/; q; }
-         s/.*/./; q'`
-
-
-# PATH needs CR, and LINENO needs CR and PATH.
-# Avoid depending upon Character Ranges.
-as_cr_letters='abcdefghijklmnopqrstuvwxyz'
-as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
-as_cr_Letters=$as_cr_letters$as_cr_LETTERS
-as_cr_digits='0123456789'
-as_cr_alnum=$as_cr_Letters$as_cr_digits
-
-# The user is always right.
-if test "${PATH_SEPARATOR+set}" != set; then
-  echo "#! /bin/sh" >conf$$.sh
-  echo  "exit 0"   >>conf$$.sh
-  chmod +x conf$$.sh
-  if (PATH="/nonexistent;."; conf$$.sh) >/dev/null 2>&1; then
-    PATH_SEPARATOR=';'
-  else
-    PATH_SEPARATOR=:
-  fi
-  rm -f conf$$.sh
-fi
-
-
-  as_lineno_1=$LINENO
-  as_lineno_2=$LINENO
-  as_lineno_3=`(expr $as_lineno_1 + 1) 2>/dev/null`
-  test "x$as_lineno_1" != "x$as_lineno_2" &&
-  test "x$as_lineno_3"  = "x$as_lineno_2"  || {
-  # Find who we are.  Look in the path if we contain no path at all
-  # relative or not.
-  case $0 in
-    *[\\/]* ) as_myself=$0 ;;
-    *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break
-done
-
-       ;;
-  esac
-  # We did not find ourselves, most probably we were run as `sh COMMAND'
-  # in which case we are not to be found in the path.
-  if test "x$as_myself" = x; then
-    as_myself=$0
-  fi
-  if test ! -f "$as_myself"; then
-    { { echo "$as_me:$LINENO: error: cannot find myself; rerun with an absolute path" >&5
-echo "$as_me: error: cannot find myself; rerun with an absolute path" >&2;}
-   { (exit 1); exit 1; }; }
-  fi
-  case $CONFIG_SHELL in
-  '')
-    as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for as_base in sh bash ksh sh5; do
-        case $as_dir in
-        /*)
-          if ("$as_dir/$as_base" -c '
-  as_lineno_1=$LINENO
-  as_lineno_2=$LINENO
-  as_lineno_3=`(expr $as_lineno_1 + 1) 2>/dev/null`
-  test "x$as_lineno_1" != "x$as_lineno_2" &&
-  test "x$as_lineno_3"  = "x$as_lineno_2" ') 2>/dev/null; then
-            $as_unset BASH_ENV || test "${BASH_ENV+set}" != set || { BASH_ENV=; export BASH_ENV; }
-            $as_unset ENV || test "${ENV+set}" != set || { ENV=; export ENV; }
-            CONFIG_SHELL=$as_dir/$as_base
-            export CONFIG_SHELL
-            exec "$CONFIG_SHELL" "$0" ${1+"$@"}
-          fi;;
-        esac
-       done
-done
-;;
-  esac
-
-  # Create $as_me.lineno as a copy of $as_myself, but with $LINENO
-  # uniformly replaced by the line number.  The first 'sed' inserts a
-  # line-number line before each line; the second 'sed' does the real
-  # work.  The second script uses 'N' to pair each line-number line
-  # with the numbered line, and appends trailing '-' during
-  # substitution so that $LINENO is not a special case at line end.
-  # (Raja R Harinath suggested sed '=', and Paul Eggert wrote the
-  # second 'sed' script.  Blame Lee E. McMahon for sed's syntax.  :-)
-  sed '=' <$as_myself |
-    sed '
-      N
-      s,$,-,
-      : loop
-      s,^\(['$as_cr_digits']*\)\(.*\)[$]LINENO\([^'$as_cr_alnum'_]\),\1\2\1\3,
-      t loop
-      s,-$,,
-      s,^['$as_cr_digits']*\n,,
-    ' >$as_me.lineno &&
-  chmod +x $as_me.lineno ||
-    { { echo "$as_me:$LINENO: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&5
-echo "$as_me: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&2;}
-   { (exit 1); exit 1; }; }
-
-  # Don't try to exec as it changes $[0], causing all sort of problems
-  # (the dirname of $[0] is not the place where we might find the
-  # original and so on.  Autoconf is especially sensible to this).
-  . ./$as_me.lineno
-  # Exit status is that of the last command.
-  exit
-}
-
-
-case `echo "testing\c"; echo 1,2,3`,`echo -n testing; echo 1,2,3` in
-  *c*,-n*) ECHO_N= ECHO_C='
-' ECHO_T='     ' ;;
-  *c*,*  ) ECHO_N=-n ECHO_C= ECHO_T= ;;
-  *)       ECHO_N= ECHO_C='\c' ECHO_T= ;;
-esac
-
-if expr a : '\(a\)' >/dev/null 2>&1; then
-  as_expr=expr
-else
-  as_expr=false
-fi
-
-rm -f conf$$ conf$$.exe conf$$.file
-echo >conf$$.file
-if ln -s conf$$.file conf$$ 2>/dev/null; then
-  # We could just check for DJGPP; but this test a) works b) is more generic
-  # and c) will remain valid once DJGPP supports symlinks (DJGPP 2.04).
-  if test -f conf$$.exe; then
-    # Don't use ln at all; we don't have any links
-    as_ln_s='cp -p'
-  else
-    as_ln_s='ln -s'
-  fi
-elif ln conf$$.file conf$$ 2>/dev/null; then
-  as_ln_s=ln
-else
-  as_ln_s='cp -p'
-fi
-rm -f conf$$ conf$$.exe conf$$.file
-
-if mkdir -p . 2>/dev/null; then
-  as_mkdir_p=:
-else
-  test -d ./-p && rmdir ./-p
-  as_mkdir_p=false
-fi
-
-as_executable_p="test -f"
-
-# Sed expression to map a string onto a valid CPP name.
-as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'"
-
-# Sed expression to map a string onto a valid variable name.
-as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'"
-
-
-# IFS
-# We need space, tab and new line, in precisely that order.
-as_nl='
-'
-IFS="  $as_nl"
-
-# CDPATH.
-$as_unset CDPATH
-
-exec 6>&1
-
-# Open the log real soon, to keep \$[0] and so on meaningful, and to
-# report actual input values of CONFIG_FILES etc. instead of their
-# values after options handling.  Logging --version etc. is OK.
-exec 5>>config.log
-{
-  echo
-  sed 'h;s/./-/g;s/^.../## /;s/...$/ ##/;p;x;p;x' <<_ASBOX
-## Running $as_me. ##
-_ASBOX
-} >&5
-cat >&5 <<_CSEOF
-
-This file was extended by $as_me, which was
-generated by GNU Autoconf 2.59.  Invocation command line was
-
-  CONFIG_FILES    = $CONFIG_FILES
-  CONFIG_HEADERS  = $CONFIG_HEADERS
-  CONFIG_LINKS    = $CONFIG_LINKS
-  CONFIG_COMMANDS = $CONFIG_COMMANDS
-  $ $0 $@
-
-_CSEOF
-echo "on `(hostname || uname -n) 2>/dev/null | sed 1q`" >&5
-echo >&5
-_ACEOF
-
-# Files that config.status was made for.
-if test -n "$ac_config_files"; then
-  echo "config_files=\"$ac_config_files\"" >>$CONFIG_STATUS
-fi
-
-if test -n "$ac_config_headers"; then
-  echo "config_headers=\"$ac_config_headers\"" >>$CONFIG_STATUS
-fi
-
-if test -n "$ac_config_links"; then
-  echo "config_links=\"$ac_config_links\"" >>$CONFIG_STATUS
-fi
-
-if test -n "$ac_config_commands"; then
-  echo "config_commands=\"$ac_config_commands\"" >>$CONFIG_STATUS
-fi
-
-cat >>$CONFIG_STATUS <<\_ACEOF
-
-ac_cs_usage="\
-\`$as_me' instantiates files from templates according to the
-current configuration.
-
-Usage: $0 [OPTIONS] [FILE]...
-
-  -h, --help       print this help, then exit
-  -V, --version    print version number, then exit
-  -q, --quiet      do not print progress messages
-  -d, --debug      don't remove temporary files
-      --recheck    update $as_me by reconfiguring in the same conditions
-  --file=FILE[:TEMPLATE]
-                  instantiate the configuration file FILE
-
-Configuration files:
-$config_files
-
-Report bugs to <bug-autoconf@gnu.org>."
-_ACEOF
-
-cat >>$CONFIG_STATUS <<_ACEOF
-ac_cs_version="\\
-config.status
-configured by $0, generated by GNU Autoconf 2.59,
-  with options \\"`echo "$ac_configure_args" | sed 's/[\\""\`\$]/\\\\&/g'`\\"
-
-Copyright (C) 2003 Free Software Foundation, Inc.
-This config.status script is free software; the Free Software Foundation
-gives unlimited permission to copy, distribute and modify it."
-srcdir=$srcdir
-_ACEOF
-
-cat >>$CONFIG_STATUS <<\_ACEOF
-# If no file are specified by the user, then we need to provide default
-# value.  By we need to know if files were specified by the user.
-ac_need_defaults=:
-while test $# != 0
-do
-  case $1 in
-  --*=*)
-    ac_option=`expr "x$1" : 'x\([^=]*\)='`
-    ac_optarg=`expr "x$1" : 'x[^=]*=\(.*\)'`
-    ac_shift=:
-    ;;
-  -*)
-    ac_option=$1
-    ac_optarg=$2
-    ac_shift=shift
-    ;;
-  *) # This is not an option, so the user has probably given explicit
-     # arguments.
-     ac_option=$1
-     ac_need_defaults=false;;
-  esac
-
-  case $ac_option in
-  # Handling of the options.
-_ACEOF
-cat >>$CONFIG_STATUS <<\_ACEOF
-  -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r)
-    ac_cs_recheck=: ;;
-  --version | --vers* | -V )
-    echo "$ac_cs_version"; exit 0 ;;
-  --he | --h)
-    # Conflict between --help and --header
-    { { echo "$as_me:$LINENO: error: ambiguous option: $1
-Try \`$0 --help' for more information." >&5
-echo "$as_me: error: ambiguous option: $1
-Try \`$0 --help' for more information." >&2;}
-   { (exit 1); exit 1; }; };;
-  --help | --hel | -h )
-    echo "$ac_cs_usage"; exit 0 ;;
-  --debug | --d* | -d )
-    debug=: ;;
-  --file | --fil | --fi | --f )
-    $ac_shift
-    CONFIG_FILES="$CONFIG_FILES $ac_optarg"
-    ac_need_defaults=false;;
-  --header | --heade | --head | --hea )
-    $ac_shift
-    CONFIG_HEADERS="$CONFIG_HEADERS $ac_optarg"
-    ac_need_defaults=false;;
-  -q | -quiet | --quiet | --quie | --qui | --qu | --q \
-  | -silent | --silent | --silen | --sile | --sil | --si | --s)
-    ac_cs_silent=: ;;
-
-  # This is an error.
-  -*) { { echo "$as_me:$LINENO: error: unrecognized option: $1
-Try \`$0 --help' for more information." >&5
-echo "$as_me: error: unrecognized option: $1
-Try \`$0 --help' for more information." >&2;}
-   { (exit 1); exit 1; }; } ;;
-
-  *) ac_config_targets="$ac_config_targets $1" ;;
-
-  esac
-  shift
-done
-
-ac_configure_extra_args=
-
-if $ac_cs_silent; then
-  exec 6>/dev/null
-  ac_configure_extra_args="$ac_configure_extra_args --silent"
-fi
-
-_ACEOF
-cat >>$CONFIG_STATUS <<_ACEOF
-if \$ac_cs_recheck; then
-  echo "running $SHELL $0 " $ac_configure_args \$ac_configure_extra_args " --no-create --no-recursion" >&6
-  exec $SHELL $0 $ac_configure_args \$ac_configure_extra_args --no-create --no-recursion
-fi
-
-_ACEOF
-
-
-
-
-
-cat >>$CONFIG_STATUS <<\_ACEOF
-for ac_config_target in $ac_config_targets
-do
-  case "$ac_config_target" in
-  # Handling of arguments.
-  "Makefile" ) CONFIG_FILES="$CONFIG_FILES Makefile" ;;
-  *) { { echo "$as_me:$LINENO: error: invalid argument: $ac_config_target" >&5
-echo "$as_me: error: invalid argument: $ac_config_target" >&2;}
-   { (exit 1); exit 1; }; };;
-  esac
-done
-
-# If the user did not use the arguments to specify the items to instantiate,
-# then the envvar interface is used.  Set only those that are not.
-# We use the long form for the default assignment because of an extremely
-# bizarre bug on SunOS 4.1.3.
-if $ac_need_defaults; then
-  test "${CONFIG_FILES+set}" = set || CONFIG_FILES=$config_files
-fi
-
-# Have a temporary directory for convenience.  Make it in the build tree
-# simply because there is no reason to put it here, and in addition,
-# creating and moving files from /tmp can sometimes cause problems.
-# Create a temporary directory, and hook for its removal unless debugging.
-$debug ||
-{
-  trap 'exit_status=$?; rm -rf $tmp && exit $exit_status' 0
-  trap '{ (exit 1); exit 1; }' 1 2 13 15
-}
-
-# Create a (secure) tmp directory for tmp files.
-
-{
-  tmp=`(umask 077 && mktemp -d -q "./confstatXXXXXX") 2>/dev/null` &&
-  test -n "$tmp" && test -d "$tmp"
-}  ||
-{
-  tmp=./confstat$$-$RANDOM
-  (umask 077 && mkdir $tmp)
-} ||
-{
-   echo "$me: cannot create a temporary directory in ." >&2
-   { (exit 1); exit 1; }
-}
-
-_ACEOF
-
-cat >>$CONFIG_STATUS <<_ACEOF
-
-#
-# CONFIG_FILES section.
-#
-
-# No need to generate the scripts if there are no CONFIG_FILES.
-# This happens for instance when ./config.status config.h
-if test -n "\$CONFIG_FILES"; then
-  # Protect against being on the right side of a sed subst in config.status.
-  sed 's/,@/@@/; s/@,/@@/; s/,;t t\$/@;t t/; /@;t t\$/s/[\\\\&,]/\\\\&/g;
-   s/@@/,@/; s/@@/@,/; s/@;t t\$/,;t t/' >\$tmp/subs.sed <<\\CEOF
-s,@SHELL@,$SHELL,;t t
-s,@PATH_SEPARATOR@,$PATH_SEPARATOR,;t t
-s,@PACKAGE_NAME@,$PACKAGE_NAME,;t t
-s,@PACKAGE_TARNAME@,$PACKAGE_TARNAME,;t t
-s,@PACKAGE_VERSION@,$PACKAGE_VERSION,;t t
-s,@PACKAGE_STRING@,$PACKAGE_STRING,;t t
-s,@PACKAGE_BUGREPORT@,$PACKAGE_BUGREPORT,;t t
-s,@exec_prefix@,$exec_prefix,;t t
-s,@prefix@,$prefix,;t t
-s,@program_transform_name@,$program_transform_name,;t t
-s,@bindir@,$bindir,;t t
-s,@sbindir@,$sbindir,;t t
-s,@libexecdir@,$libexecdir,;t t
-s,@datadir@,$datadir,;t t
-s,@sysconfdir@,$sysconfdir,;t t
-s,@sharedstatedir@,$sharedstatedir,;t t
-s,@localstatedir@,$localstatedir,;t t
-s,@libdir@,$libdir,;t t
-s,@includedir@,$includedir,;t t
-s,@oldincludedir@,$oldincludedir,;t t
-s,@infodir@,$infodir,;t t
-s,@mandir@,$mandir,;t t
-s,@build_alias@,$build_alias,;t t
-s,@host_alias@,$host_alias,;t t
-s,@target_alias@,$target_alias,;t t
-s,@DEFS@,$DEFS,;t t
-s,@ECHO_C@,$ECHO_C,;t t
-s,@ECHO_N@,$ECHO_N,;t t
-s,@ECHO_T@,$ECHO_T,;t t
-s,@LIBS@,$LIBS,;t t
-s,@CC@,$CC,;t t
-s,@build@,$build,;t t
-s,@build_cpu@,$build_cpu,;t t
-s,@build_vendor@,$build_vendor,;t t
-s,@build_os@,$build_os,;t t
-s,@host@,$host,;t t
-s,@host_cpu@,$host_cpu,;t t
-s,@host_vendor@,$host_vendor,;t t
-s,@host_os@,$host_os,;t t
-s,@target@,$target,;t t
-s,@target_cpu@,$target_cpu,;t t
-s,@target_vendor@,$target_vendor,;t t
-s,@target_os@,$target_os,;t t
-s,@LIBOBJS@,$LIBOBJS,;t t
-s,@LTLIBOBJS@,$LTLIBOBJS,;t t
-CEOF
-
-_ACEOF
-
-  cat >>$CONFIG_STATUS <<\_ACEOF
-  # Split the substitutions into bite-sized pieces for seds with
-  # small command number limits, like on Digital OSF/1 and HP-UX.
-  ac_max_sed_lines=48
-  ac_sed_frag=1 # Number of current file.
-  ac_beg=1 # First line for current file.
-  ac_end=$ac_max_sed_lines # Line after last line for current file.
-  ac_more_lines=:
-  ac_sed_cmds=
-  while $ac_more_lines; do
-    if test $ac_beg -gt 1; then
-      sed "1,${ac_beg}d; ${ac_end}q" $tmp/subs.sed >$tmp/subs.frag
-    else
-      sed "${ac_end}q" $tmp/subs.sed >$tmp/subs.frag
-    fi
-    if test ! -s $tmp/subs.frag; then
-      ac_more_lines=false
-    else
-      # The purpose of the label and of the branching condition is to
-      # speed up the sed processing (if there are no `@' at all, there
-      # is no need to browse any of the substitutions).
-      # These are the two extra sed commands mentioned above.
-      (echo ':t
-  /@[a-zA-Z_][a-zA-Z_0-9]*@/!b' && cat $tmp/subs.frag) >$tmp/subs-$ac_sed_frag.sed
-      if test -z "$ac_sed_cmds"; then
-       ac_sed_cmds="sed -f $tmp/subs-$ac_sed_frag.sed"
-      else
-       ac_sed_cmds="$ac_sed_cmds | sed -f $tmp/subs-$ac_sed_frag.sed"
-      fi
-      ac_sed_frag=`expr $ac_sed_frag + 1`
-      ac_beg=$ac_end
-      ac_end=`expr $ac_end + $ac_max_sed_lines`
-    fi
-  done
-  if test -z "$ac_sed_cmds"; then
-    ac_sed_cmds=cat
-  fi
-fi # test -n "$CONFIG_FILES"
-
-_ACEOF
-cat >>$CONFIG_STATUS <<\_ACEOF
-for ac_file in : $CONFIG_FILES; do test "x$ac_file" = x: && continue
-  # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
-  case $ac_file in
-  - | *:- | *:-:* ) # input from stdin
-       cat >$tmp/stdin
-       ac_file_in=`echo "$ac_file" | sed 's,[^:]*:,,'`
-       ac_file=`echo "$ac_file" | sed 's,:.*,,'` ;;
-  *:* ) ac_file_in=`echo "$ac_file" | sed 's,[^:]*:,,'`
-       ac_file=`echo "$ac_file" | sed 's,:.*,,'` ;;
-  * )   ac_file_in=$ac_file.in ;;
-  esac
-
-  # Compute @srcdir@, @top_srcdir@, and @INSTALL@ for subdirectories.
-  ac_dir=`(dirname "$ac_file") 2>/dev/null ||
-$as_expr X"$ac_file" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
-        X"$ac_file" : 'X\(//\)[^/]' \| \
-        X"$ac_file" : 'X\(//\)$' \| \
-        X"$ac_file" : 'X\(/\)' \| \
-        .     : '\(.\)' 2>/dev/null ||
-echo X"$ac_file" |
-    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
-         /^X\(\/\/\)[^/].*/{ s//\1/; q; }
-         /^X\(\/\/\)$/{ s//\1/; q; }
-         /^X\(\/\).*/{ s//\1/; q; }
-         s/.*/./; q'`
-  { if $as_mkdir_p; then
-    mkdir -p "$ac_dir"
-  else
-    as_dir="$ac_dir"
-    as_dirs=
-    while test ! -d "$as_dir"; do
-      as_dirs="$as_dir $as_dirs"
-      as_dir=`(dirname "$as_dir") 2>/dev/null ||
-$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
-        X"$as_dir" : 'X\(//\)[^/]' \| \
-        X"$as_dir" : 'X\(//\)$' \| \
-        X"$as_dir" : 'X\(/\)' \| \
-        .     : '\(.\)' 2>/dev/null ||
-echo X"$as_dir" |
-    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
-         /^X\(\/\/\)[^/].*/{ s//\1/; q; }
-         /^X\(\/\/\)$/{ s//\1/; q; }
-         /^X\(\/\).*/{ s//\1/; q; }
-         s/.*/./; q'`
-    done
-    test ! -n "$as_dirs" || mkdir $as_dirs
-  fi || { { echo "$as_me:$LINENO: error: cannot create directory \"$ac_dir\"" >&5
-echo "$as_me: error: cannot create directory \"$ac_dir\"" >&2;}
-   { (exit 1); exit 1; }; }; }
-
-  ac_builddir=.
-
-if test "$ac_dir" != .; then
-  ac_dir_suffix=/`echo "$ac_dir" | sed 's,^\.[\\/],,'`
-  # A "../" for each directory in $ac_dir_suffix.
-  ac_top_builddir=`echo "$ac_dir_suffix" | sed 's,/[^\\/]*,../,g'`
-else
-  ac_dir_suffix= ac_top_builddir=
-fi
-
-case $srcdir in
-  .)  # No --srcdir option.  We are building in place.
-    ac_srcdir=.
-    if test -z "$ac_top_builddir"; then
-       ac_top_srcdir=.
-    else
-       ac_top_srcdir=`echo $ac_top_builddir | sed 's,/$,,'`
-    fi ;;
-  [\\/]* | ?:[\\/]* )  # Absolute path.
-    ac_srcdir=$srcdir$ac_dir_suffix;
-    ac_top_srcdir=$srcdir ;;
-  *) # Relative path.
-    ac_srcdir=$ac_top_builddir$srcdir$ac_dir_suffix
-    ac_top_srcdir=$ac_top_builddir$srcdir ;;
-esac
-
-# Do not use `cd foo && pwd` to compute absolute paths, because
-# the directories may not exist.
-case `pwd` in
-.) ac_abs_builddir="$ac_dir";;
-*)
-  case "$ac_dir" in
-  .) ac_abs_builddir=`pwd`;;
-  [\\/]* | ?:[\\/]* ) ac_abs_builddir="$ac_dir";;
-  *) ac_abs_builddir=`pwd`/"$ac_dir";;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_top_builddir=${ac_top_builddir}.;;
-*)
-  case ${ac_top_builddir}. in
-  .) ac_abs_top_builddir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_top_builddir=${ac_top_builddir}.;;
-  *) ac_abs_top_builddir=$ac_abs_builddir/${ac_top_builddir}.;;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_srcdir=$ac_srcdir;;
-*)
-  case $ac_srcdir in
-  .) ac_abs_srcdir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_srcdir=$ac_srcdir;;
-  *) ac_abs_srcdir=$ac_abs_builddir/$ac_srcdir;;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_top_srcdir=$ac_top_srcdir;;
-*)
-  case $ac_top_srcdir in
-  .) ac_abs_top_srcdir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_top_srcdir=$ac_top_srcdir;;
-  *) ac_abs_top_srcdir=$ac_abs_builddir/$ac_top_srcdir;;
-  esac;;
-esac
-
-
-
-  if test x"$ac_file" != x-; then
-    { echo "$as_me:$LINENO: creating $ac_file" >&5
-echo "$as_me: creating $ac_file" >&6;}
-    rm -f "$ac_file"
-  fi
-  # Let's still pretend it is `configure' which instantiates (i.e., don't
-  # use $as_me), people would be surprised to read:
-  #    /* config.h.  Generated by config.status.  */
-  if test x"$ac_file" = x-; then
-    configure_input=
-  else
-    configure_input="$ac_file.  "
-  fi
-  configure_input=$configure_input"Generated from `echo $ac_file_in |
-                                    sed 's,.*/,,'` by configure."
-
-  # First look for the input files in the build tree, otherwise in the
-  # src tree.
-  ac_file_inputs=`IFS=:
-    for f in $ac_file_in; do
-      case $f in
-      -) echo $tmp/stdin ;;
-      [\\/$]*)
-        # Absolute (can't be DOS-style, as IFS=:)
-        test -f "$f" || { { echo "$as_me:$LINENO: error: cannot find input file: $f" >&5
-echo "$as_me: error: cannot find input file: $f" >&2;}
-   { (exit 1); exit 1; }; }
-        echo "$f";;
-      *) # Relative
-        if test -f "$f"; then
-          # Build tree
-          echo "$f"
-        elif test -f "$srcdir/$f"; then
-          # Source tree
-          echo "$srcdir/$f"
-        else
-          # /dev/null tree
-          { { echo "$as_me:$LINENO: error: cannot find input file: $f" >&5
-echo "$as_me: error: cannot find input file: $f" >&2;}
-   { (exit 1); exit 1; }; }
-        fi;;
-      esac
-    done` || { (exit 1); exit 1; }
-_ACEOF
-cat >>$CONFIG_STATUS <<_ACEOF
-  sed "$ac_vpsub
-$extrasub
-_ACEOF
-cat >>$CONFIG_STATUS <<\_ACEOF
-:t
-/@[a-zA-Z_][a-zA-Z_0-9]*@/!b
-s,@configure_input@,$configure_input,;t t
-s,@srcdir@,$ac_srcdir,;t t
-s,@abs_srcdir@,$ac_abs_srcdir,;t t
-s,@top_srcdir@,$ac_top_srcdir,;t t
-s,@abs_top_srcdir@,$ac_abs_top_srcdir,;t t
-s,@builddir@,$ac_builddir,;t t
-s,@abs_builddir@,$ac_abs_builddir,;t t
-s,@top_builddir@,$ac_top_builddir,;t t
-s,@abs_top_builddir@,$ac_abs_top_builddir,;t t
-" $ac_file_inputs | (eval "$ac_sed_cmds") >$tmp/out
-  rm -f $tmp/stdin
-  if test x"$ac_file" != x-; then
-    mv $tmp/out $ac_file
-  else
-    cat $tmp/out
-    rm -f $tmp/out
-  fi
-
-done
-_ACEOF
-
-cat >>$CONFIG_STATUS <<\_ACEOF
-
-{ (exit 0); exit 0; }
-_ACEOF
-chmod +x $CONFIG_STATUS
-ac_clean_files=$ac_clean_files_save
-
-
-# configure is writing to config.log, and then calls config.status.
-# config.status does its own redirection, appending to config.log.
-# Unfortunately, on DOS this fails, as config.log is still kept open
-# by configure, so config.status won't be able to write to it; its
-# output is simply discarded.  So we exec the FD to /dev/null,
-# effectively closing config.log, so it can be properly (re)opened and
-# appended to by config.status.  When coming back to configure, we
-# need to make the FD available again.
-if test "$no_create" != yes; then
-  ac_cs_success=:
-  ac_config_status_args=
-  test "$silent" = yes &&
-    ac_config_status_args="$ac_config_status_args --quiet"
-  exec 5>/dev/null
-  $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false
-  exec 5>>config.log
-  # Use ||, not &&, to avoid exiting from the if with $? = 1, which
-  # would make configure fail if this is the last instruction.
-  $ac_cs_success || { (exit 1); exit 1; }
-fi
-

diff --git a/gdb/testsuite/gdb.gdbtk/configure.ac b/gdb/testsuite/gdb.gdbtk/configure.ac
deleted file mode 100644 (file)
index 5ab12ed..0000000
--- a/gdb/testsuite/gdb.gdbtk/configure.ac
+++ /dev/null
@@ -1,18 +0,0 @@
-dnl Process this file file with autoconf to produce a configure script.
-dnl This file is a shell script fragment that supplies the information
-dnl necessary to tailor a template configure script into the configure
-dnl script appropriate for this directory.  For more information, check
-dnl any existing configure script.
-
-AC_PREREQ(2.5)
-AC_INIT(defs)
-
-CC=${CC-cc}
-AC_SUBST(CC)
-AC_CONFIG_AUX_DIR(`cd $srcdir;pwd`/../../..)
-AC_CANONICAL_SYSTEM
-
-dnl Check for exe extension set on certain hosts (e.g. Win32)
-AC_EXEEXT
-
-AC_OUTPUT(Makefile)

diff --git a/gdb/testsuite/gdb.gdbtk/console.exp b/gdb/testsuite/gdb.gdbtk/console.exp
deleted file mode 100644 (file)
index b17eaa1..0000000
--- a/gdb/testsuite/gdb.gdbtk/console.exp
+++ /dev/null
@@ -1,42 +0,0 @@
-# Copyright 1998, 1999, 2001, 2004 Red Hat, Inc.
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms of the GNU General Public License (GPL) as published by
-# the Free Software Foundation; either version 2 of the License, or (at
-# your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-
-load_lib ../gdb.gdbtk/insight-support.exp
-
-if {[gdbtk_initialize_display]} {
-  if {$tracelevel} {
-    strace $tracelevel
-  }
-
-  #
-  # test console window
-  #
-  set prms_id 0
-  set bug_id 0
-
-  set testfile "simple"
-  set srcfile ${testfile}.c
-  set binfile ${objdir}/${subdir}/${testfile}
-  set r [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug}]
-  if  { $r != "" } {
-    gdb_suppress_entire_file \
-      "Testcase compile failed, so some tests in this file will automatically fail."
-  }
-
-  # Start with a fresh gdbtk
-  gdb_exit
-  set results [gdbtk_start [file join $srcdir $subdir console.test]]
-  set results [split $results \n]
-
-  # Analyze results
-  gdbtk_done $results
-}

diff --git a/gdb/testsuite/gdb.gdbtk/console.test b/gdb/testsuite/gdb.gdbtk/console.test
deleted file mode 100644 (file)
index e75bf0f..0000000
--- a/gdb/testsuite/gdb.gdbtk/console.test
+++ /dev/null
@@ -1,488 +0,0 @@
-#   Copyright (C) 1998, 1999, 2002 Red Hat, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-# This file was written by Keith Seitz (keiths@cygnus.com)
-
-# Read in the standard defs file
-
-if {![gdbtk_read_defs]} {
-  break
-}
-
-global objdir test_ran
-global console text
-set console [ManagedWin::open Console]
-set text [$console test set _twin]
-
-#####                            #####
-#                                    #
-#  Helper functions for this module  #
-#                                    #
-#####                            #####
-
-# console_command --
-#      Invoke STRING as a command in the console window and
-#      return the result
-proc console_command {string} { 
-  global console text
-
-  # Save current position
-  set line [lindex [split [$text index cmdmark] .] 0]
-  incr line 1
-
-  # Insert and invoke command
-  $text insert end $string
-  $console invoke
-  update
-
-  # Get the result
-  set end [lindex [split [$text index cmdmark] .] 0]
-  incr end -1
-  return [$text get $line.0 [list $end.0 lineend]]
-} 
-
-# get_cmd_line --
-#     Return the command line
-proc get_cmd_line {} {
-  global text
-
-  update
-  set index [$text index cmdmark]
-  return [$text get [list $index linestart] [list $index lineend]]
-}
-
-# clear_command_line --
-#     Clear the command line
-proc clear_command_line {} {
-  global text
-  $text delete {cmdmark + 1 char} insert
-}
-
-#####         #####
-#                 #
-#  CONSOLE TESTS  #
-#                 #
-#####         #####
-
-#
-# Miscellaneous tests
-#
-
-# Test:  console-misc-1
-# Desc:  Change console prompt
-gdbtk_test console-misc-1 {change console prompt} {
-  # Insert the "set prompt" command into the text widget
-  console_command {set prompt (test) }
-
-  $text get {cmdmark linestart} {cmdmark lineend}
-} {(test) }
-if {$test_ran} {
-  console_command {set prompt (gdb) }
-}
-
-#
-# Paste tests
-#
-
-# Test:  console-paste-1
-# Desc:  Paste the X selection into console window
-gdbtk_test console-paste-1 {paste X text} {
-  # This is cheesy, but it works... Create a text widget
-  # which holds the current selection...
-  text .test_text
-  .test_text insert end "this is some pasted text"
-  .test_text tag add sel 1.0 {1.0 lineend}
-  event generate .test_text <<Copy>>
-  event generate $text <<Paste>>
-  get_cmd_line
-} {(gdb) this is some pasted text}
-if {$test_ran} {
-  destroy .test_text
-  clear_command_line
-}
-
-#
-# Test for errors
-#
-
-# Test:  console-error-1
-# Desc:  Check if console window reports internal gdb errors
-gdbtk_test console-error-1 {invoke unknown command} {
-  console_command {this_command_doesn't_exist}
-} {Error: Undefined command: "this".  Try "help".
-}
-
-#
-# History tests
-#
-
-# Test:  console-history-1.1
-# Desc:  Exercise the up-history functionality
-gdbtk_test console-history-1.1 {up history once} {
-  # Add some commands into the command buffer
-  console_command {show annotate}
-  console_command {show complaints}
-  console_command {show confirm}
-  console_command {show height}
-  console_command {show language}
-  console_command {show print demangle}
-  console_command {show remotebaud}
-  console_command {show remotebreak}
-  console_command {show remotecache}
-  console_command {show remotedebug}
-  console_command {show remotedevice}
-  console_command {show remotelogbase}
-  console_command {help quit}
-  console_command {help si}
-  # this doesn't seem to work reliably: event generate $text <Up>
-  $console test _previous
-  get_cmd_line
-} {(gdb) help si}
-if {$test_ran} {
-  clear_command_line
-}
-
-# Test:  console-history-1.2
-# Desc:  Exercise the up-history functionality
-gdbtk_test console-history-1.2 {up history twice} {
-  # Add some commands into the command buffer
-  console_command {show annotate}
-  console_command {show complaints}
-  console_command {show confirm}
-  console_command {show height}
-  console_command {show language}
-  console_command {show print demangle}
-  console_command {show remotebaud}
-  console_command {show remotebreak}
-  console_command {show remotecache}
-  console_command {show remotedebug}
-  console_command {show remotedevice}
-  console_command {show remotelogbase}
-  console_command {help quit}
-  console_command {help si}
-  # this doesn't seem to work reliably: event generate $text <Up>
-  # this doesn't seem to work reliably: event generate $text <Up>
-  $console test _previous
-  $console test _previous
-  get_cmd_line
-} {(gdb) help quit}
-if {$test_ran} {
-  clear_command_line
-}
-
-# Test:  console-history-1.3
-# Desc:  Exercise the up-history functionality
-gdbtk_test console-history-1.3 {up history four times} {
-  # Add some commands into the command buffer
-  console_command {show annotate}
-  console_command {show complaints}
-  console_command {show confirm}
-  console_command {show height}
-  console_command {show language}
-  console_command {show print demangle}
-  console_command {show remotebaud}
-  console_command {show remotebreak}
-  console_command {show remotecache}
-  console_command {show remotedebug}
-  console_command {show remotedevice}
-  console_command {show remotelogbase}
-  console_command {help quit}
-  console_command {help si}
-
-  for {set i 0} {$i < 4} {incr i} {
-    # this doesn't seem to work reliably: event generate $text <Up>
-    $console test _previous
-  }
-  get_cmd_line
-} {(gdb) show remotedevice}
-if {$test_ran} {
-  clear_command_line
-}
-
-# Test:  console-history-1.4
-# Desc:  Exercise the up-history functionality
-gdbtk_test console-history-1.4 {up fourteen times} {
-  # Add some commands into the command buffer
-  console_command {show annotate}
-  console_command {show complaints}
-  console_command {show confirm}
-  console_command {show height}
-  console_command {show language}
-  console_command {show print demangle}
-  console_command {show remotebaud}
-  console_command {show remotebreak}
-  console_command {show remotecache}
-  console_command {show remotedebug}
-  console_command {show remotedevice}
-  console_command {show remotelogbase}
-  console_command {help quit}
-  console_command {help si}
-  for {set i 0} {$i < 14} {incr i} {
-    # this doesn't seem to work reliably: event generate $text <Up>
-    $console test _previous
-  }
-  get_cmd_line
-} {(gdb) show annotate}
-if {$test_ran} {
-  clear_command_line
-}
-
-# Test:  console-history-1.5
-# Desc:  Exercise the up-history search functionality
-gdbtk_test console-history-1.5 {up search} {
- # Add some commands into the command buffer
-  console_command {show height}
-  console_command {show annotate}
-  console_command {show complaints}
-  console_command {print main}
-  console_command {show remotelogbase}
-  console_command {help quit}
-  console_command {help si}
-
-  $text insert end "sh"
-  # this doesn't seem to work reliably: event generate $text <Shift-Up>
-  # this doesn't seem to work reliably: event generate $text <Shift-Up>
-  # this doesn't seem to work reliably: event generate $text <Shift-Up>
-  $console test _search_history
-  $console test _search_history
-  $console test _search_history
-  get_cmd_line
-} {(gdb) show annotate}
-
-
-# Test:  console-history-1.6
-# Desc:  Exercise the down-history search functionality
-gdbtk_test console-history-1.6 {down search} {
-  # this doesn't seem to work reliably: event generate $text <Shift-Down>
-  # this doesn't seem to work reliably: event generate $text <Shift-Down>
-  $console test _rsearch_history
-  $console test _rsearch_history
-  get_cmd_line
-} {(gdb) show remotelogbase}
-
-# Test:  console-history-1.7
-# Desc:  Down-history search to bottom
-# We go back down until the original partialcommand is displayed
-gdbtk_test console-history-1.7 {down search to bottom} {
-  # this doesn't seem to work reliably: event generate $text <Shift-Down>
-  # this doesn't seem to work reliably: event generate $text <Shift-Down>
-  $console test _rsearch_history
-  $console test _rsearch_history
-  get_cmd_line
-} {(gdb) sh}
-
-# Test:  console-history-1.8
-# Desc:  Up-history search to top
-# We go up until there are no matches
-gdbtk_test console-history-1.8 {up search to top} {
-  for {set i 0} {$i < 100} {incr i} {
-    # this doesn't seem to work reliably: event generate $text <Shift-Up>
-    $console test _search_history
-  }
-  get_cmd_line
-} {(gdb) show annotate}
-
-if {$test_ran} {
-  clear_command_line
-}
-
-# Test:  console-history-2.1
-# Desc:  Exercise the down-history functionality
-gdbtk_test console-history-2.1 {down once} {
-  # Add some commands into the command buffer
-  console_command {show annotate}
-  console_command {show complaints}
-  console_command {show confirm}
-  console_command {show height}
-  console_command {show language}
-  console_command {show print demangle}
-  console_command {show remotebaud}
-  console_command {show remotebreak}
-  console_command {show remotecache}
-  console_command {show remotedebug}
-  console_command {show remotedevice}
-  console_command {show remotelogbase}
-  console_command {help quit}
-  console_command {help si}
-
-  for {set i 0} {$i < 14} {incr i} {
-    # this doesn't seem to work reliably: event generate $text <Up>
-    $console test _previous
-  }
-  # this doesn't seem to work reliably: event generate $text <Down>
-  $console test _next
-  get_cmd_line
-} {(gdb) show complaints}
-if {$test_ran} {
-  clear_command_line
-}
-
-# Test:  console-history-2.2
-# Desc:  Exercise the down-history functionality
-gdbtk_test console-history-2.2 {down twice} {
-  # Add some commands into the command buffer
-  console_command {show annotate}
-  console_command {show complaints}
-  console_command {show confirm}
-  console_command {show height}
-  console_command {show language}
-  console_command {show print demangle}
-  console_command {show remotebaud}
-  console_command {show remotebreak}
-  console_command {show remotecache}
-  console_command {show remotedebug}
-  console_command {show remotedevice}
-  console_command {show remotelogbase}
-  console_command {help quit}
-  console_command {help si}
-
-  for {set i 0} {$i < 14} {incr i} {
-    # this doesn't seem to work reliably: event generate $text <Up>
-    $console test _previous
-  }
-
-  # this doesn't seem to work reliably: event generate $text <Down>
-  # this doesn't seem to work reliably: event generate $text <Down>
-  $console test _next
-  $console test _next
-  get_cmd_line
-} {(gdb) show confirm}
-if {$test_ran} {
-  clear_command_line
-}
-
-# Test:  console-history-2.3
-# Desc:  Exercise the down-history functionality
-gdbtk_test console-history-2.3 {down four times} {
-  # Add some commands into the command buffer
-  console_command {show annotate}
-  console_command {show complaints}
-  console_command {show confirm}
-  console_command {show height}
-  console_command {show language}
-  console_command {show print demangle}
-  console_command {show remotebaud}
-  console_command {show remotebreak}
-  console_command {show remotecache}
-  console_command {show remotedebug}
-  console_command {show remotedevice}
-  console_command {show remotelogbase}
-  console_command {help quit}
-  console_command {help si}
-
-  for {set i 0} {$i < 14} {incr i} {
-    # this doesn't seem to work reliably: event generate $text <Up>
-    $console test _previous
-  }
-
-  for {set i 0} {$i < 4} {incr i} {
-    # this doesn't seem to work reliably: event generate $text <Down>
-    $console test _next
-  }
-  get_cmd_line
-} {(gdb) show language}
-if {$test_ran} {
-  clear_command_line
-}
-
-# Test:  console-history-2.4
-# Desc:  Exercise the down-history functionality
-gdbtk_test console-history-2.4 {down infinitely} {
-  # Add some commands into the command buffer
-  console_command {show annotate}
-  console_command {show complaints}
-  console_command {show confirm}
-  console_command {show height}
-  console_command {show language}
-  console_command {show print demangle}
-  console_command {show remotebaud}
-  console_command {show remotebreak}
-  console_command {show remotecache}
-  console_command {show remotedebug}
-  console_command {show remotedevice}
-  console_command {show remotelogbase}
-  console_command {help quit}
-  console_command {help si}
-  for {set i 0} {$i < 14} {incr i} {
-    # this doesn't seem to work reliably: event generate $text <Up>
-    $console test _previous
-  }
-
-  for {set i 0} {$i < 20} {incr i} {
-    # this doesn't seem to work reliably: event generate $text <Down>
-    $console test _next
-  }
-  get_cmd_line
-} {(gdb) }
-if {$test_ran} {
-  clear_command_line
-}
-
-#
-# gdb - gdbtk Interface Tests
-#
-
-# Test:  console-interface-1.1
-# Desc:  Verify that a "file" command in the console window causes
-#        gdb to invoke the pre-/post-add-symbol hooks
-set file_loaded 0
-gdbtk_test console-interface-1.1 {file command goes through hooks} {
-  global TEST1_RESULT TEST2_RESULT
-
-  # This is really ugly, but its the only way to do this...
-  rename gdbtk_tcl_pre_add_symbol pre_add
-  rename gdbtk_tcl_post_add_symbol post_add
-
-  proc gdbtk_tcl_pre_add_symbol {file} {
-    global TEST1_RESULT
-
-    set TEST1_RESULT $file
-    pre_add $file
-  }
-  proc gdbtk_tcl_post_add_symbol {} {
-    global TEST2_RESULT
-
-    set TEST2_RESULT ok
-    post_add
-  }
-
-  # load a file and make sure we went through the pre/post_add_symbol hooks
-  set TEST1_RESULT {}
-  set TEST2_RESULT {}
-  set file [file join $objdir simple]
-  console_command "file $file"
-  if {$TEST1_RESULT != $file} {
-    set result "did not go through gdbtk_tcl_pre_add_symbol ($TEST1_RESULT)"
-  } elseif {$TEST2_RESULT != "ok"} {
-    set result "did not go through gdbtk_tcl_post_add_symbol"
-  } else {
-    set result {}
-    set file_loaded 1
-  }
-
-  set result
-} {}
-if {$test_ran} {
-  rename gdbtk_tcl_pre_add_symbol {}
-  rename gdbtk_tcl_post_add_symbol {}
-  rename pre_add gdbtk_tcl_pre_add_symbol
-  rename post_add gdbtk_tcl_post_add_symbol
-}
-
-#
-#  Exit
-#
-gdbtk_test_done

diff --git a/gdb/testsuite/gdb.gdbtk/cpp_variable.cc b/gdb/testsuite/gdb.gdbtk/cpp_variable.cc
deleted file mode 100644 (file)
index deecc29..0000000
--- a/gdb/testsuite/gdb.gdbtk/cpp_variable.cc
+++ /dev/null
@@ -1,33 +0,0 @@
-#include "cpp_variable.h"
-
-static void do_simple_class_tests (void);
-
-int
-VB::fvb_pub () {return 300 + vb_pub_int;}
-
-int
-VB::vvb_pub () {return 400 + vb_pub_int;}
-
-int
-V::f () {return 600 + v_pub_int;}
-
-int
-V::vv () {return 400 + v_pub_int;}
-
-int
-VC::fvc () {return 300 + vc_pub_int;}
-
-int
-VC::vfvc () {return 100 + vc_pub_int;}
-
-main ()
-{
-  do_simple_class_tests ();
-}
-
-static void
-do_simple_class_tests (void)
-{
-  V *v = new V;
-  V vv;
-}

diff --git a/gdb/testsuite/gdb.gdbtk/cpp_variable.exp b/gdb/testsuite/gdb.gdbtk/cpp_variable.exp
deleted file mode 100644 (file)
index a7764f6..0000000
--- a/gdb/testsuite/gdb.gdbtk/cpp_variable.exp
+++ /dev/null
@@ -1,48 +0,0 @@
-# Copyright 1999, 2001, 2004 Red Hat, Inc.
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms of the GNU General Public License (GPL) as published by
-# the Free Software Foundation; either version 2 of the License, or (at
-# your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-
-load_lib ../gdb.gdbtk/insight-support.exp
-
-if {[gdbtk_initialize_display]} {
-  if {$tracelevel} {
-    strace $tracelevel
-  }
-
-  set results {}
-  if {[skip_cplus_tests]} {
-    # Target doesn't have c++ support
-    verbose "No C++ support -- skipping test"
-  } else {
-    #
-    # test variable API
-    #
-    set prms_id 0
-    set bug_id 0
-
-    set testfile "cpp_variable"
-    set srcfile ${testfile}.cc
-    set binfile ${objdir}/${subdir}/${testfile}
-    set r [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug c++}]
-    if  { $r != "" } {
-      gdb_suppress_entire_file \
-       "Testcase compile failed, so some tests in this file will automatically fail."
-    }
-
-    # Start with a fresh gdbtk
-    gdb_exit
-    set results [gdbtk_start [file join $srcdir $subdir ${testfile}.test]]
-    set results [split $results \n]
-  }
-
-  # Analyze results
-  gdbtk_done $results
-}

diff --git a/gdb/testsuite/gdb.gdbtk/cpp_variable.h b/gdb/testsuite/gdb.gdbtk/cpp_variable.h
deleted file mode 100644 (file)
index 40fda99..0000000
--- a/gdb/testsuite/gdb.gdbtk/cpp_variable.h
+++ /dev/null
@@ -1,54 +0,0 @@
-struct _foo
-{
-  int a[10];
-  char *p;
-};
-
-class VA
-{
- public:
-  int va_pub_int;
-  char *va_pub_charp;
-
- private:
-  int va_priv_int;
-  char *va_priv_charp;
-
- protected:
-  struct _foo bar;
-};
-
-class VB
-{
- public:
-  int vb_pub_int;
-
-  int fvb_pub ();
-  virtual int vvb_pub ();
-
- private:
-  int vb_priv_int;
-  char *vb_priv_charp;
-};
-
-class VC
-{
- public:
-  int vc_pub_int;
-
-  int fvc ();
-  virtual int vfvc ();
-};
-
-class V : public VA, public VB, public VC
-{
- public:
-  int f ();
-  virtual int vv ();
-  int v_pub_int;
-  char *v_pub_charp;
-
- private:
-  int v_priv_int;
-  char *v_priv_charp;
-};

diff --git a/gdb/testsuite/gdb.gdbtk/cpp_variable.test b/gdb/testsuite/gdb.gdbtk/cpp_variable.test
deleted file mode 100644 (file)
index d2de6f3..0000000
--- a/gdb/testsuite/gdb.gdbtk/cpp_variable.test
+++ /dev/null
@@ -1,594 +0,0 @@
-# Varobj Tests (C++ language)
-# Copyright (C) 1998, 2003 Red Hat, Inc.
-#
-# This Program Is Free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-# Please email any bugs, comments, and/or additions to this file to:
-# insight@sources.redhat.com
-
-# This file was written by Keith Seitz (keiths@cygnus.com)
-
-# Read in the standard defs file
-if {![gdbtk_read_defs]} {
-  break
-}
-
-global objdir test_ran
-
-# Load in a file
-set program [file join $objdir cpp_variable]
-if {[catch {gdbtk_test_file $program} t]} {
-  # This isn't a test case, since if this fails, we're hosed.
-  gdbtk_test_error "loading \"$program\": $t"
-}
-
-# The variables that are created are stored in an array called "var".
-
-# proc to tell us which of the variables are changed/out of scope
-proc check_update {} {
-  global var
-
-  set out {}
-  set changed {}
-  foreach ind [array names var] {
-    set ret [$var($ind) update]
-    if {$ret == -1} {
-       lappend out $ind
-    } elseif {$ret != ""} {
-        lappend changed $ret
-    }
-  }
-  return [list $changed $out]
-}
-
-
-# proc to create a variable
-proc create_variable {expr} {
-  global var
-
-  set err [catch {gdb_variable create "$expr" -expr $expr} v]
-  if {!$err} {
-    set var($expr) $v
-  }
-
-  return $err
-}
-
-# proc to get the children
-# Children are stored in the global "var" as
-# PARENT.child. So for struct _foo {int a; int b} bar;,
-# the children returned are {a b} and var(bar.a) and var(bar.b)
-# map the actual objects to their names.
-proc get_children {parent} {
-  global var
-
-  set kiddies [$var($parent) children]
-  set children {}
-  foreach child $kiddies {
-    set name [lindex [split $child .] end]
-    lappend children $name
-    set var($parent.$name) $child
-  }
-
-  return $children
-}
-
-proc delete_variable {varname} {
-  global var
-
-  if {[info exists var($varname)]} {
-    # This has to be caught, since deleting a parent
-    # will erase all children.
-    $var($varname) delete
-    set vars [array names var $varname*]
-    foreach v $vars {
-      if {[info exists var($v)]} {
-       unset var($v)
-      }
-    }
-  }
-}
-
-# Compare the values of variable V in format FMT with value of OBJ
-# with gdb's value.
-proc cppvalue {obj v fmt} {
-  global var
-  global _test
-
-  puts $_test(logfile) "obj=$obj v=$v fmt=$fmt"
-  puts $_test(logfile) "var(\$obj)=$var($obj)"
-
-  set value [$var($obj) value]
-  set gdb [gdb_cmd "output/$fmt $v"]
-  puts $_test(logfile) "output/$fmt $v"
-  if {$value == $gdb} {
-    puts $_test(logfile) "gdbtk: $value == gdb: $gdb"
-    set result ok
-  } else {
-    set result $v
-    puts $_test(logfile) "gdbtk: $value <> gdb: $gdb"
-  }
-
-  return $result
-}
-
-proc delete_all_variables {} {
-  global var
-
-  foreach variable [array names var] {
-    delete_variable $variable
-  }
-}
-
-#####            #####
-#                    #
-# Simple Class Tests #
-#                    #
-#####            #####
-
-# run to "do_simple_class_tests"
-gdb_cmd "break do_simple_class_tests"
-gdbtk_test_run
-
-# Test:  cpp_variable-1.1
-# Desc:  stopped in do_simple_class_tests
-gdbtk_test cpp_variable-1.1 {stopped in do_simple_class_tests} {
-  # G++ can output "do_simple_class_tests(void)". Strip the "(void)" part.
-  set loc [lindex [gdb_loc] 1]
-  set index [string first \( $loc]
-  if {$index > 0} {
-    set loc [string range $loc 0 [expr {$index-1}]]
-  }
-  set loc
-} {do_simple_class_tests}
-
-# Test: cpp_variable-1.2
-# Desc: create variable v
-gdbtk_test cpp_variable-1.2 {create variable v} {
-  create_variable v
-} {0}
-
-# Test: cpp_variable-1.3
-# Desc: number of children of v
-gdbtk_test cpp_variable-1.3 {number of children of v} {
-  $var(v) numChildren
-} {5}
-
-# Test: cpp_variable-1.4a
-# Desc: children of v
-gdbtk_test cpp_variable-1.4a {children of v} {
-  get_children v
-} {VA VB VC public private}
-
-# Test: cpp_variable-1.4b
-# Desc: public children of v
-gdbtk_test cpp_variable-1.4b {public children of v} {
-  get_children v.public
-} {v_pub_int v_pub_charp}
-
-# Test: cpp_variable-1.4c
-# Desc: private children of v
-gdbtk_test cpp_variable-1.4c {private children of v} {
-  get_children v.private
-} {v_priv_int v_priv_charp}
-
-# Test: cpp_variable-1.5
-# Desc: type of v
-gdbtk_test cpp_variable-1.5 {type of v} {
-  $var(v) type
-} {V *}
-
-# Test: cpp_variable-1.6
-# Desc: format of v
-gdbtk_test cpp_variable-1.6 {format of v} {
-  $var(v) format
-} {natural}
-
-set value {}
-catch {$var(v) value} value
-
-# Test: cpp_variable-1.6a
-# Desc: Step over "V *v = new V;"
-gdbtk_test cpp_variable-1.6a {step over "V *v = new V;"} {
-  catch {gdb_cmd "next"}
-} {0}
-
-# Test: cpp_variable-1.7
-# Desc: check value of v changed
-gdbtk_test cpp_variable-1.7 {check value of v changed} {
-  set changes [check_update]
-  # It is undefined whether the children will change values
-  # or not, so ignore them.
-  expr {[lsearch [lindex [lindex $changes 0] 0] v] != -1}
-} {1}
-
-# Test: cpp_variable-1.8
-# Desc: check values of v
-gdbtk_test cpp_variable-1.8 {check values of v} {
-  set new [$var(v) value]
-  expr {$new != $value}
-} {1}
-
-# Test: cpp_variable-1.9
-# Desc: v editable
-gdbtk_test cpp_variable-1.9 {v editable} {
-  $var(v) editable
-} {1}
-
-#####             #####
-#                     #
-# Children of v tests #
-#                     #
-#####             #####
-
-# Test: cpp_variable-2.1
-# Desc: type of v.v_pub_int
-gdbtk_test cpp_variable-2.1 {type of v.v_pub_int} {
-  $var(v.public.v_pub_int) type
-} {int}
-
-# Test: cpp_variable-2.2
-# Desc: format of v.v_pub_int
-gdbtk_test cpp_variable-2.2 {format of v.v_pub_int} {
-  $var(v.public.v_pub_int) format
-} {natural}
-
-# Test: cpp_variable-2.2a
-# Desc: set variable v->v_pub_int=2112 
-gdbtk_test cpp_variable-2.2a {set variable v.v_pub_int=2112} {
-  set err [catch {gdb_cmd "set variable v.v_pub_int=2112"} txt]
-  if {$err} {
-    set txt
-  } else {
-    set err
-  }
-} {0}
-
-# Test: cpp_variable-2.3
-# Desc: value of v.v_pub_int changed
-gdbtk_test cpp_variable-2.3 {value of v.v_pub_int changed} {
-  check_update
-} {v.public.v_pub_int {v.private.v_priv_charp v.VB v.private.v_priv_int v.VC v.public.v_pub_charp v.public.v_pub_int v.private v.public v.VA}}
-
-# Test: cpp_variable-2.4
-# Desc: value of v.v_pub_int
-gdbtk_test cpp_variable-2.4 {value of v.v_pub_int} {
-  $var(v.public.v_pub_int) value
-} {2112}
-
-# Test: cpp_variable-2.5
-# Desc: changed format of v.v_pub_int
-gdbtk_test cpp_variable-2.5 {changed format of v.v_pub_int} {
-  $var(v.public.v_pub_int) format octal
-  $var(v.public.v_pub_int) format
-} {octal}
-
-# Test: cpp_variable-2.6
-# Desc: value of v.v_pub_int with new format
-gdbtk_test cpp_variable-2.6 {value of v.v_pub_int with new format} {
-  $var(v.public.v_pub_int) value
-} {04100}
-
-# Test: cpp_variable-2.7
-# Desc: change value of v.v_pub_int (decimal)
-gdbtk_test cpp_variable-2.7 {change value of v.v_pub_int (decimal)} {
-  $var(v.public.v_pub_int) value 3
-  cppvalue v.public.v_pub_int v.v_pub_int o
-} {ok}
-
-# Test: cpp_variable-2.8
-# Desc: change value of v.v_pub_int (hexadecimal)
-gdbtk_test cpp_variable-2.8 {change value of v.v_pub_int (hexadecimal)} {
-  $var(v.public.v_pub_int) value 0x21
-  cppvalue v.public.v_pub_int v.v_pub_int o
-} {ok}
-
-# Test: cpp_variable-2.9
-# Desc: number of children of v_pub_int
-gdbtk_test cpp_variable-2.9 {number of children of v_pub_int} {
-  $var(v.public.v_pub_int) numChildren
-} {0}
-
-# Test: cpp_variable-2.10
-# Desc: children of v.v_pub_int
-gdbtk_test cpp_variable-2.10 {children of v.v_pub_int} {
-  get_children v.public.v_pub_int
-} {}
-
-# Test: cpp_variable-2.11
-# Desc: v.v_pub_int editable
-gdbtk_test cpp_variable-2.11 {v.v_pub_int editable} {
-  $var(v.public.v_pub_int) editable
-} {1}
-
-# Test: cpp_variable-2.21
-# Desc: type of v.v_priv_charp
-gdbtk_test cpp_variable-2.21 {type of v.v_priv_charp} {
-  $var(v.private.v_priv_charp) type
-} {char *}
-
-# Test: cpp_variable-2.22
-# Desc: format of v.v_priv_charp
-gdbtk_test cpp_variable-2.22 {format of v.v_priv_charp} {
-  $var(v.private.v_priv_charp) format
-} {natural}
-
-# Test: cpp_variable-2.22a
-# Desc: set variable v->v_priv_charp=2112
-gdbtk_test cpp_variable-2.22a {set variable v->v_priv_charp=2112} {
-  set err [catch {gdb_cmd "set variable v->v_priv_charp=2112"} txt]
-  if {$err} {
-    set txt
-  } else {
-    set err
-  }
-} {0}
-
-# Test: cpp_variable-2.23
-# Desc: value of v.v_priv_charp changed
-gdbtk_test cpp_variable-2.23 {value of v.v_priv_charp changed} {
-  check_update
-} {{{v.public.v_pub_int v.private.v_priv_charp}} {v.private.v_priv_charp v.VB v.private.v_priv_int v.VC v.public.v_pub_charp v.public.v_pub_int v.private v.public v.VA}}
-
-# Test: cpp_variable-2.24
-# Desc: value of v.v_priv_charp
-gdbtk_test cpp_variable-2.24 {value of v.v_priv_charp} {
-  $var(v.private.v_priv_charp) format hexadecimal
-  $var(v.private.v_priv_charp) value
-} {0x840}
-
-# Test: cpp_variable-2.25
-# Desc: changed format of v.v_priv_charp
-gdbtk_test cpp_variable-2.25 {changed format of v.v_priv_charp} {
-  $var(v.private.v_priv_charp) format octal
-  $var(v.private.v_priv_charp) format
-} {octal}
-
-# Test: cpp_variable-2.26
-# Desc: value of v.v_priv_charp with new format
-gdbtk_test cpp_variable-2.26 {value of v.v_priv_charp with new format} {
-  $var(v.private.v_priv_charp) value
-} {04100}
-
-# Test: cpp_variable-2.27
-# Desc: change value of v.v_priv_charp (decimal)
-gdbtk_test cpp_variable-2.27 {change value of v.v_priv_charp (decimal)} {
-  $var(v.private.v_priv_charp) value 3
-  cppvalue v.private.v_priv_charp v.v_priv_charp o
-} {ok}
-
-# Test: cpp_variable-2.28
-# Desc: change value of v.v_priv_charp (hexadecimal)
-gdbtk_test cpp_variable-2.28 {change value of v.v_priv_charp (hexadecimal)} {
-  $var(v.private.v_priv_charp) value 0x21
-  cppvalue v.private.v_priv_charp v.v_priv_charp o
-} {ok}
-
-# Test: cpp_variable-2.29
-# Desc: number of children of v_priv_charp
-gdbtk_test cpp_variable-2.29 {number of children of v_priv_charp} {
-  $var(v.private.v_priv_charp) numChildren
-} {1}
-
-# Test: cpp_variable-2.30
-# Desc: children of v.v_priv_charp
-gdbtk_test cpp_variable-2.30 {children of v.v_priv_charp} {
-  get_children v.private.v_priv_charp
-} {*v_priv_charp}
-
-# Test: cpp_variable-2.31
-# Desc: v.v_priv_int editable
-gdbtk_test cpp_variable-2.31 {v.v_priv_int editable} {
-  $var(v.private.v_priv_int) editable
-} {1}
-
-# Test: cpp_variable-2.41
-# Desc: type of v.VA
-gdbtk_test cpp_variable-2.41 {type of v.VA} {
-  $var(v.VA) type
-} {VA}
-
-# Test: cpp_variable-2.42
-# Desc: format of v.VA
-gdbtk_test cpp_variable-2.42 {format of v.VA} {
-  $var(v.VA) format
-} {natural}
-
-# Test: cpp_variable-2.43
-# Desc: value of v.VA changed
-gdbtk_test cpp_variable-2.43 {value of v.VA changed} {
-  check_update
-} {v.private.v_priv_charp {v.private.v_priv_charp v.VB v.private.v_priv_int v.VC v.public.v_pub_charp v.private.v_priv_charp.*v_priv_charp v.public.v_pub_int v.private v.public v.VA}}
-
-# Test: cpp_variable-2.44
-# Desc: value of v.VA
-gdbtk_test cpp_variable-2.44 {value of v.VA} {
-  $var(v.VA) value
-} {{...}}
-
-# Test: cpp_variable-2.45
-# Desc: changed format of v.VA
-gdbtk_test cpp_variable-2.45 {changed format of v.VA} {
-  $var(v.VA) format octal
-  $var(v.VA) format
-} {octal}
-
-# Test: cpp_variable-2.46
-# Desc: value of v.VA with new format
-gdbtk_test cpp_variable-2.46 {value of v.VA with new format} {
-  $var(v.VA) value
-} {{...}}
-
-# Test: cpp_variable-2.47
-# Desc: number of children of VA
-gdbtk_test cpp_variable-2.47 {number of children of VA} {
-  $var(v.VA) numChildren
-} {3}
-
-# Test: cpp_variable-2.48a
-# Desc: children of v.VA
-gdbtk_test cpp_variable-2.48a {children of v.VA} {
-  get_children v.VA
-} {public private protected}
-
-# Test: cpp_variable-2.48b
-# Desc: public children of v.VA
-gdbtk_test cpp_variable-2.48b {children of v.VA} {
-  get_children v.VA.public
-} {va_pub_int va_pub_charp}
-
-# Test: cpp_variable-2.48c
-# Desc: private children of v.VA
-gdbtk_test cpp_variable-2.48c {children of v.VA} {
-  get_children v.VA.private
-} {va_priv_int va_priv_charp}
-
-# Test: cpp_variable-2.48d
-# Desc: protected children of v.VA
-gdbtk_test cpp_variable-2.48d {children of v.VA} {
-  get_children v.VA.protected
-} {bar}
-
-# Test: cpp_variable-2.49
-# Desc: v.VA editable
-gdbtk_test cpp_variable-2.49 {v.VA editable} {
-  $var(v.VA) editable
-} {0}
-
-# Test: cpp_variable-2.61
-# Desc: type of v.VB
-gdbtk_test cpp_variable-2.61 {type of v.VB} {
-  $var(v.VB) type
-} {VB}
-
-# Test: cpp_variable-2.62
-# Desc: format of v.VB
-gdbtk_test cpp_variable-2.62 {format of v.VB} {
-  $var(v.VB) format
-} {natural}
-
-# Test: cpp_variable-2.63
-# Desc: value of v.VB changed
-gdbtk_test cpp_variable-2.63 {value of v.VB changed} {
-  check_update
-} {{} {v.VA.protected v.private.v_priv_charp.*v_priv_charp v.VA.private v.VA.public.va_pub_int v.private.v_priv_int v.public.v_pub_int v.VA.public.va_pub_charp v.private.v_priv_charp v.VA.public v.public.v_pub_charp v.VA.private.va_priv_int v.VA v.public v.VB v.VC v.VA.protected.bar v.VA.private.va_priv_charp v.private}}
-
-# Test: cpp_variable-2.64
- # Desc: value of v.VB
-gdbtk_test cpp_variable-2.64 {value of v.VB} {
-  $var(v.VB) value
-} {{...}}
-
-# Test: cpp_variable-2.65
-# Desc: changed format of v.VB
-gdbtk_test cpp_variable-2.65 {changed format of v.VB} {
-  $var(v.VB) format octal
-  $var(v.VB) format
-} {octal}
-
-# Test: cpp_variable-2.66
-# Desc: value of v.VB with new format
-gdbtk_test cpp_variable-2.66 {value of v.VB with new format} {
-  $var(v.VB) value
-} {{...}}
-
-# Note: The next two tests show whether or not the logic
-# concerning vptr tables is working.
-# Test: cpp_variable-2.67
-# Desc: number of children of VB
-gdbtk_test cpp_variable-2.67 {number of children of VB} {
-  $var(v.VB) numChildren
-} {2}
-
-# Test: cpp_variable-2.68a
-# Desc: children of v.VB
-gdbtk_test cpp_variable-2.68a {children of v.VB} {
-  get_children v.VB
-} {public private}
-
-# Test: cpp_variable-2.68b
-# Desc: public children of v.VB
-gdbtk_test cpp_variable-2.68b {children of v.VB} {
-  get_children v.VB.public
-} {vb_pub_int}
-
-# Test: cpp_variable-2.68c
-# Desc: private children of v.VB
-gdbtk_test cpp_variable-2.68c {children of v.VB} {
-  get_children v.VB.private
-} {vb_priv_int vb_priv_charp}
-
-# Test: cpp_variable-2.69
-# Desc: v.VB editable
-gdbtk_test cpp_variable-2.69 {v.VB editable} {
-  $var(v.VB) editable
-} {0}
-
-# Test: cpp_variable-2.70
-# Desc: v.VB.public editable
-gdbtk_test cpp_variable-2.70 {v.VB.public editable} {
-  $var(v.VB.public) editable
-} {0}
-
-# Test: cpp_variable-2.71
-# Desc: v.VB.vb_pub_int editable
-gdbtk_test cpp_variable-2.71 {v.VB.vb_pub_int editable} {
-  $var(v.VB.public.vb_pub_int) editable
-} {1}
-
-# Test: cpp_variable-2.71a
-# Desc: set variable v->vb_pub_int=2112
-gdbtk_test cpp_variable-2.71a {set variable v->v_pub_int=2112} {
-  set err [catch {gdb_cmd "set variable v->vb_pub_int=2112"} txt]
-  if {$err} {
-    set txt
-  } else {
-    set err
-  }
-} {0}
-
-# Test: cpp_variable-2.72
-# Desc: value of v.vb_pub_int changed
-gdbtk_test cpp_variable-2.72 {value of v.vb_pub_int changed} {
-  check_update
-} {v.VB.public.vb_pub_int {v.VB.public v.VA.protected v.private.v_priv_charp.*v_priv_charp v.VA.private v.VB.private.vb_priv_int v.VB.private v.VA.public.va_pub_int v.private.v_priv_int v.VB.public.vb_pub_int v.public.v_pub_int v.VB.private.vb_priv_charp v.VA.public.va_pub_charp v.private.v_priv_charp v.VA.public v.public.v_pub_charp v.VA.private.va_priv_int v.VA v.public v.VB v.VC v.VA.protected.bar v.VA.private.va_priv_charp v.private}}
-
-# Test: cpp_variable-2.73
-# Desc: value of v.VB.vb_pub_int
-gdbtk_test cpp_variable-2.73 {changed value of v.vb_pub_int} {
-  $var(v.VB.public.vb_pub_int) value
-} {2112}
-
-# Test: cpp_variable-2.74
-# Desc: change value of v.VB.vb_pub_int
-gdbtk_test cpp_variable-2.74 {change value of v.VB.public.vb_pub_int} {
-  $var(v.VB.public.vb_pub_int) value 3
-  cppvalue v.VB.public.vb_pub_int v.vb_pub_int d
-} {ok}
-
-# Test: cpp_variable-2.75
-# Desc: value of v.VB.vb_pub_int
-gdbtk_test cpp_variable-2.75 {changed value of v.VB.public.vb_pub_int} {
-  $var(v.VB.public.vb_pub_int) value
-} {3}
-
-
-#  Exit
-#
-gdbtk_test_done
-
-#Local Variables:
-#mode: tcl
-

diff --git a/gdb/testsuite/gdb.gdbtk/defs b/gdb/testsuite/gdb.gdbtk/defs
deleted file mode 100644 (file)
index 8e3fe5b..0000000
--- a/gdb/testsuite/gdb.gdbtk/defs
+++ /dev/null
@@ -1,306 +0,0 @@
-# This file contains support code for the gdbtk test suite.
-# Copyright 2001 Red Hat, Inc.
-#
-# Based on the Tcl testsuite support code, portions of this file
-# are Copyright (c) 1990-1994 The Regents of the University of California and
-# Copyright (c) 1994-1996 Sun Microsystems, Inc.
-#
-global _test env srcdir objdir
-
-if {![info exists srcdir]} {
-  if {[info exists env(SRCDIR)]} {
-    set srcdir $env(SRCDIR)
-  } else {
-    set srcdir .
-  }
-}
-
-if {![info exists objdir]} {
-  if {[info exists env(OBJDIR)]} {
-    set objdir $env(OBJDIR)
-  } elseif {$_test(interactive)} {
-    # If running interactively, assume that the objdir is
-    # relative to the executable's location
-    set objdir [file join [file dirname [info nameofexecutable]] testsuite gdb.gdbtk]
-  } else {
-    set objdir .
-  }
-}
-
-if {![info exists _test(verbose)]} {
-  if {[info exists env(GDBTK_VERBOSE)]} {
-    set _test(verbose) $env(GDBTK_VERBOSE)
-  } else {
-    set _test(verbose) 0
-  }
-}
-if {![info exists _test(tests)]} {
-
-  if {[info exists env(GDBTK_TESTS)]} {
-    set _test(tests) $env(GDBTK_TESTS)
-  } else {
-    set _test(tests) {}
-  }
-}
-
-if {[info exists env(GDBTK_LOGFILE)]} {
-  set _test(logfile) [open $env(GDBTK_LOGFILE) a+]
-  fconfigure $_test(logfile) -buffering none
-} else {
-  set _test(logfile) {}
-}
-
-# Informs gdbtk internals that testsuite is running. An example
-# where this is needed is the window manager, which must place
-# all windows at some place on the screen so that the system's
-# window manager does not interfere. This is reset in gdbtk_test_done.
-set env(GDBTK_TEST_RUNNING) 1
-
-# The gdb "file" command to use for gdbtk testing
-# NOTE: This proc appends ".exe" to all windows' programs
-proc gdbtk_test_file {filename} {
-  global tcl_platform
-
-  if {$tcl_platform(platform) == "windows"} {
-    append filename ".exe"
-  }
-
-  set err [catch {gdb_cmd "file $filename" 1} text]
-  if {$err} {
-    error $text
-  }
-
-  return $text
-}
-
-proc gdbtk_test_run {{prog_args {}}} {
-  global env
-
-  # Get the target_info array from the testsuite
-  array set target_info $env(TARGET_INFO)
-
-  # We get the target ready by:
-  # 1. Run all init commands
-  # 2. Issue target command
-  # 3. Issue load command
-  # 4. Issue run command
-  foreach cmd $target_info(init) {
-    set err [catch {gdb_cmd $cmd 0} txt]
-    if {$err} {
-      _report_error "Target initialization command \"$cmd\" failed: $txt"
-      return 0
-    }
-  }
-
-  if {$target_info(target) != ""} {
-    set err [catch {gdb_cmd $target_info(target) 0} txt]
-    if {$err} {
-      _report_error "Failed to connect to target: $txt"
-      return 0
-    }
-  }
-
-  if {$target_info(load) != ""} {
-    set err [catch {gdb_cmd $target_info(load) 0} txt]
-    if {$err} {
-      _report_error "Failed to load: $txt"
-      return 0
-    }
-  }
-
-  if {$target_info(run) != ""} {
-    set err [catch {gdb_cmd $target_info(run) 0} txt]
-    if {$err} {
-      _report_error "Could not run target with \"$target_info(run)\": $txt"
-      return 0
-    }
-  }
-
-  return 1
-}
-
-proc _report_error {msg} {
-  global _test
-
-  if {[info exists _test(interactive)] && $_test(interactive)} {
-    # Dialog
-    tk_messageBox -message $msg -icon error -type ok
-  } else {
-    # to stderr
-    puts stderr $msg
-  }
-}
-
-proc gdbtk_print_verbose {status name description script code answer} {
-  global _test
-
-  switch $code {
-    0 {
-      set code_words {}
-    }
-    1 {
-      set code_words "Test generated error: $answer"
-    }
-
-    2 {
-      set code_words "Test generated return exception;  result was: $answer"
-    }
-
-    3 {
-      set code_words "Test generated break exception"
-    }
-
-    4 {
-      set code_words "Test generated continue exception"
-    }
-
-    5 {
-      set code_words "Test generated exception $code;  message was:$answer"
-    }
-  }
-
-  if {$_test(verbose) > 1 \
-       || ($_test(verbose) != 1 && ($status == "ERROR" || $status == "FAIL"))} {
-    # Printed when user verbose mode (verbose > 1) or an error/failure occurs
-    # not running the testsuite (dejagnu)
-    puts stdout "\n"
-    puts stdout "==== $name $description"
-    puts stdout "==== Contents of test case:"
-    puts stdout "$script"
-    if {$code_words != ""} {
-      puts stdout $code_words
-    }
-    puts stdout "==== Result was:"
-    puts stdout "$answer"
-  } elseif {$_test(verbose)} {
-    # Printed for the testsuite (verbose = 1)
-    puts stdout "[list $status $name $description $code_words]"
-
-    if {$_test(logfile) != ""} {
-      puts $_test(logfile) "\n"
-      puts $_test(logfile) "==== $name $description"
-      puts $_test(logfile) "==== Contents of test case:"
-      puts $_test(logfile) "$script"
-      if {$code_words != ""} {
-       puts $_test(logfile) $code_words
-      }
-      puts $_test(logfile) "==== Result was:"
-      puts $_test(logfile) "$answer"
-    }
-  }
-}
-
-# gdbtk_test
-#
-# This procedure runs a test and prints an error message if the
-# test fails.
-#
-# Arguments:
-# name -               Name of test, in the form foo-1.2.
-# description -                Short textual description of the test, to
-#                      help humans understand what it does.
-# script -             Script to run to carry out the test.  It must
-#                      return a result that can be checked for
-#                      correctness.
-# answer -             Expected result from script.
-
-proc gdbtk_test {name description script answer} {
-  global _test test_ran
-
-  set test_ran 0
-  if {[string compare $_test(tests) ""] != 0} then {
-    set ok 0
-    foreach test $_test(tests) {
-      if [string match $test $name] then {
-       set ok 1
-       break
-      }
-    }
-    if !$ok then return
-  }
-
-  set code [catch {uplevel $script} result]
-  set test_ran 1
-  if {$code != 0} {
-    # Error
-    gdbtk_print_verbose ERROR $name $description $script \
-      $code $result
-  } elseif {[string compare $result $answer] == 0} { 
-    if {[string index $name 0] == "*"} {
-      # XPASS
-      set HOW XPASS
-    } else {
-      set HOW PASS
-    }
-
-    if {$_test(verbose)} {
-      gdbtk_print_verbose $HOW $name $description $script \
-       $code $result
-      if {$_test(verbose) != 1} {
-       puts stdout "++++ $name ${HOW}ED"
-      }
-    }
-    if {$_test(logfile) != ""} {
-      puts $_test(logfile) "++++ $name ${HOW}ED"
-    }
-  } else {
-    if {[string index $name 0] == "*"} {
-      # XFAIL
-      set HOW XFAIL
-    } else {
-      set HOW FAIL
-    }
-
-    gdbtk_print_verbose $HOW $name $description $script \
-      $code $result
-    if {$_test(verbose) != 1} {
-      puts stdout "---- Result should have been:"
-      puts stdout "$answer"
-      puts stdout "---- $name ${HOW}ED" 
-    }
-    if {$_test(logfile) != ""} {
-      puts $_test(logfile) "---- Result should have been:"
-      puts $_test(logfile) "$answer"
-      puts $_test(logfile) "---- $name ${HOW}ED" 
-    }
-  }
-}
-
-proc gdbtk_dotests {file args} {
-  global _test
-  set savedTests $_test(tests)
-  set _test(tests) $args
-  source $file
-  set _test(tests) $savedTests
-}
-
-proc gdbtk_test_done {} {
-  global _test env
-
-  if {$_test(logfile) != ""} {
-    close $_test(logfile)
-  }
-
-  set env(GDBTK_TEST_RUNNING) 0
-  if {![info exists _test(interactive)] || !$_test(interactive)} {
-    gdbtk_force_quit
-  }
-}
-
-proc gdbtk_test_error {desc} {
-  set desc [join [split $desc \n] |]
-  puts "ERROR \{$desc\} \{\} \{\}"
-  gdbtk_test_done
-}
-
-# Override the warning dialog. We don't want to see them.
-rename show_warning real_show_warning
-proc show_warning {msg} {
-  global _test
-
-  set str "INSIGHT TESTSUITE WARNING: $msg"
-  puts stdout $str
-  if {$_test(logfile) != ""} {
-    puts $_test(logfile) $str
-  }
-}

diff --git a/gdb/testsuite/gdb.gdbtk/insight-support.exp b/gdb/testsuite/gdb.gdbtk/insight-support.exp
deleted file mode 100644 (file)
index ef03922..0000000
--- a/gdb/testsuite/gdb.gdbtk/insight-support.exp
+++ /dev/null
@@ -1,321 +0,0 @@
-# GDB Testsuite Support for Insight.
-#
-# Copyright 2001, 2004 Red Hat, Inc.
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms of the GNU General Public License (GPL) as published by
-# the Free Software Foundation; either version 2 of the License, or (at
-# your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-
-# Initializes the display for gdbtk testing.
-# Returns 1 if tests should run, 0 otherwise.
-proc gdbtk_initialize_display {} {
-  global _using_windows
-
-  # This is hacky, but, we don't have much choice. When running
-  # expect under Windows, tcl_platform(platform) is "unix".
-  if {![info exists _using_windows]} {
-    set _using_windows [expr {![catch {exec cygpath --help}]}]
-  }
-
-  if {![_gdbtk_xvfb_init]} {
-    if {$_using_windows} {
-      untested "No GDB_DISPLAY -- skipping tests"
-    } else {
-      untested "No GDB_DISPLAY or Xvfb -- skipping tests"
-    }
-
-    return 0
-  }
-
-  return 1
-}
-
-# From dejagnu:
-# srcdir = testsuite src dir (e.g., devo/gdb/testsuite)
-# objdir = testsuite obj dir (e.g., gdb/testsuite)
-# subdir = subdir of testsuite (e.g., gdb.gdbtk)
-#
-# To gdbtk:
-# env(DEFS)=the "defs" files (e.g., devo/gdb/testsuite/gdb.gdbtk/defs)
-# env(SRCDIR)=directory containing the test code (e.g., *.test)
-# env(OBJDIR)=directory which contains any executables
-#            (e.g., gdb/testsuite/gdb.gdbtk)
-proc gdbtk_start {test} {
-  global verbose
-  global GDB
-  global GDBFLAGS
-  global env srcdir subdir objdir
-
-  gdb_stop_suppressing_tests;
-
-  # Need to convert ::GDB to use (-)?insight...
-  if {[regsub {gdb$} $GDB insight newGDB]} {
-    set INSIGHT $newGDB
-  } else {
-    perror "Cannot find Insight executable"
-    return "ERROR gdbtk_start"
-  }
-
-  verbose "Starting $INSIGHT -nx -q --tclcommand=$test"
-
-  set real_test [which $test]
-  if {$real_test == 0} {
-    perror "$test is not found"
-    return "ERROR gdbtk_start"
-  }
-
-  if {![is_remote host]} {
-    if { [which $INSIGHT] == 0 } {
-      perror "$INSIGHT does not exist."
-      return "ERROR gdbtk_start"
-    }
-  }
-
-  set wd [pwd]
-
-  # Find absolute path to test
-  set test [to_tcl_path -abs $test]
-
-  # Set some environment variables
-  cd $srcdir
-  set abs_srcdir [pwd]
-  set env(DEFS) [to_tcl_path -abs [file join $abs_srcdir $subdir defs]]
-
-  cd $wd
-  cd [file join $objdir $subdir]
-  set env(OBJDIR) [pwd]
-  cd $wd
-
-  # Set info about target into env
-  _gdbtk_export_target_info
-
-  set env(SRCDIR) $abs_srcdir
-  set env(GDBTK_VERBOSE) 1
-  set env(GDBTK_LOGFILE) [to_tcl_path [file join $objdir gdb.log]]
-  if {[info exists env(TCL_LIBRARY)]} {
-    unset -nocomplain env(TCL_LIBRARY)
-  }
-
-  set err [catch {exec $INSIGHT -nx -q --tclcommand=$test} res]
-  if { $err } {
-    perror "Execing $INSIGHT failed: $res"
-    append res "\nERROR gdb-crash"
-  }
-  return $res
-}
-
-# Start xvfb when using it.
-# The precedence is:
-#   1. If GDB_DISPLAY is set (and not ""), use it
-#   2. If Xvfb exists, use it (not on cygwin)
-#   3. Skip tests
-proc _gdbtk_xvfb_init {} {
-  global env spawn_id _xvfb_spawn_id _using_windows
-
-  if {[info exists env(GDB_DISPLAY)]} {
-    if {$env(GDB_DISPLAY) != ""} {
-      set env(DISPLAY) $env(GDB_DISPLAY)
-    } else {
-      # Suppress tests
-      return 0
-    }
-  } elseif {!$_using_windows && [which Xvfb] != 0} {
-    set screen ":[getpid]"
-    set pid [spawn  Xvfb $screen -ac]
-    set _xvfb_spawn_id $spawn_id
-    set env(DISPLAY) localhost$screen
-  } else {
-    # No Xvfb found -- skip test
-    return 0
-  }
-
-  return 1
-}
-
-# Kill xvfb
-proc _gdbtk_xvfb_exit {} {
-  global objdir subdir env _xvfb_spawn_id
-
-  if {[info exists _xvfb_spawn_id]} {
-    exec kill [exp_pid -i $_xvfb_spawn_id]
-    wait -i $_xvfb_spawn_id
-  }
-}
-
-# help proc for setting tcl-style paths from unix-style paths
-# pass "-abs" to make it an absolute path
-proc to_tcl_path {unix_path {arg {}}} {
-  global _using_windows
-
-  if {[string compare $unix_path "-abs"] == 0} {
-    set unix_path $arg
-    set wd [pwd]
-    cd [file dirname $unix_path]
-    set dirname [pwd]
-    set unix_name [file join $dirname [file tail $unix_path]]
-    cd $wd
-  }
-
-  if {$_using_windows} {
-    set unix_path [exec cygpath -aw $unix_path]
-    set unix_path [join [split $unix_path \\] /]
-  }
-
-  return $unix_path
-}
-  
-# Set information about the target into the environment
-# variable TARGET_INFO. This array will contain a list
-# of commands that are necessary to run a target.
-#
-# This is mostly devined from how dejagnu works, what
-# procs are defined, and analyzing unix.exp, monitor.exp,
-# and sim.exp.
-#
-# Array elements exported:
-# Index   Meaning
-# -----   -------
-# init    list of target/board initialization commands
-# target  target command for target/board
-# load    load command for target/board
-# run     run command for target_board
-proc _gdbtk_export_target_info {} {
-  global env
-
-  # Figure out what "target class" the testsuite is using,
-  # i.e., sim, monitor, native
-  if {[string compare [info proc gdb_target_monitor] gdb_target_monitor] == 0} {
-    # Using a monitor/remote target
-    set target monitor
-  } elseif {[string compare [info proc gdb_target_sim] gdb_target_sim] == 0} {
-    # Using a simulator target
-    set target simulator
-  } elseif {[string compare [info proc gdb_target_sid] gdb_target_sid] == 0} {
-    # Using sid
-    set target sid
-  } else {
-    # Assume native
-    set target native
-  }
-
-  # Now setup the array to be exported.
-  set info(init) {}
-  set info(target) {}
-  set info(load) {}
-  set info(run) {}
-
-  switch $target {
-    simulator {
-      set opts "[target_info gdb,target_sim_options]"
-      set info(target) "target sim $opts"
-      set info(load) "load"
-      set info(run) "run"
-    }
-
-    monitor {
-      # Setup options for the connection
-      if {[target_info exists baud]} {
-       lappend info(init) "set remotebaud [target_info baud]"
-      }
-      if {[target_info exists binarydownload]} {
-       lappend info(init) "set remotebinarydownload [target_info binarydownload]"
-      }
-      if {[target_info exists disable_x_packet]} {
-       lappend info(init) "set remote X-packet disable"
-      }
-      if {[target_info exists disable_z_packet]} {
-       lappend info(init) "set remote Z-packet disable"
-      }
-
-      # Get target name and connection info
-      if {[target_info exists gdb_protocol]} {
-       set targetname "[target_info gdb_protocol]"
-      } else {
-       set targetname "not_specified"
-      }
-      if {[target_info exists gdb_serial]} {
-       set serialport "[target_info gdb_serial]"
-      } elseif {[target_info exists netport]} {
-       set serialport "[target_info netport]"
-      } else {
-       set serialport "[target_info serial]"
-      }
-
-      set info(target) "target $targetname $serialport"
-      set info(load) "load"
-      set info(run) "continue"
-    }
-
-    sid {
-      # We must start sid first, since Insight won't have a clue
-      # about how to do this.
-      sid_start
-      set info(target) "target [target_info gdb_protocol] [target_info netport]"
-      set info(load) "load"
-      set info(run) "continue"
-    }
-
-    native {
-      set info(run) "run"
-    }
-  }
-
-  # Export the array to the environment
-  set env(TARGET_INFO) [array get info]
-}
-
-# gdbtk tests call this function to print out the results of the
-# tests. The argument is a proper list of lists of the form:
-# {status name description msg}. All of these things typically
-# come from the testsuite harness.
-proc gdbtk_analyze_results {results} {
-  foreach test $results {
-    set status [lindex $test 0]
-    set name [lindex $test 1]
-    set description [lindex $test 2]
-    set msg [lindex $test 3]
-
-    switch $status {
-      PASS {
-       pass "$description ($name)"
-      }
-
-      FAIL {
-       fail "$description ($name)"
-      }
-
-      ERROR {
-       perror "$name"
-      }
-
-      XFAIL {
-       xfail "$description ($name)"
-      }
-
-      XPASS {
-       xpass "$description ($name)"
-      }
-    }
-  }
-}
-
-proc gdbtk_done {{results {}}} {
-  global _xvfb_spawn_id
-  gdbtk_analyze_results $results
-
-  # Kill off xvfb if using it
-  if {[info exists _xvfb_spawn_id]} {
-    _gdbtk_xvfb_exit
-  }
-
-  # Yich. If we're using sid, we must kill it
-  if {[string compare [info proc gdb_target_sid] gdb_target_sid] == 0} {
-    sid_exit
-  }
-}

diff --git a/gdb/testsuite/gdb.gdbtk/list0.c b/gdb/testsuite/gdb.gdbtk/list0.c
deleted file mode 100644 (file)
index b50fdd4..0000000
--- a/gdb/testsuite/gdb.gdbtk/list0.c
+++ /dev/null
@@ -1,43 +0,0 @@
-#include "list0.h"
-
-int main ()
-{
-    int x;
-#ifdef usestubs
-    set_debug_traps();
-    breakpoint();
-#endif
-    x = 0;
-    foo (x++);
-    foo (x++);
-    foo (x++);
-    foo (x++);
-    foo (x++);
-    foo (x++);
-    foo (x++);
-    foo (x++);
-    foo (x++);
-    foo (x++);
-    foo (x++);
-    foo (x++);
-    foo (x++);
-    foo (x++);
-    foo (x++);
-    foo (x++);
-    foo (x++);
-    foo (x++);
-    foo (x++);
-    foo (x++);
-    foo (x++);
-    foo (x++);
-    foo (x++);
-    foo (x++);
-    foo (x++);
-    return 0;
-}
-
-static void
-unused ()
-{
-    /* Not used for anything */
-}

diff --git a/gdb/testsuite/gdb.gdbtk/list0.h b/gdb/testsuite/gdb.gdbtk/list0.h
deleted file mode 100644 (file)
index d468330..0000000
--- a/gdb/testsuite/gdb.gdbtk/list0.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* An include file that actually causes code to be generated in the including file.  This is known to cause problems on some systems. */
-#ifdef PROTOTYPES
-extern void bar(int);
-static void foo (int x)
-#else
-static void foo (x) int x;
-#endif
-{
-    bar (x++);
-    bar (x++);
-    bar (x++);
-    bar (x++);
-    bar (x++);
-    bar (x++);
-    bar (x++);
-    bar (x++);
-    bar (x++);
-    bar (x++);
-    bar (x++);
-    bar (x++);
-    bar (x++);
-    bar (x++);
-    bar (x++);
-    bar (x++);
-    bar (x++);
-    bar (x++);
-    bar (x++);
-    bar (x++);
-    bar (x++);
-    bar (x++);
-    bar (x++);
-    bar (x++);
-    bar (x++);
-    bar (x++);
-    bar (x++);
-    bar (x++);
-}

diff --git a/gdb/testsuite/gdb.gdbtk/list1.c b/gdb/testsuite/gdb.gdbtk/list1.c
deleted file mode 100644 (file)
index 6094104..0000000
--- a/gdb/testsuite/gdb.gdbtk/list1.c
+++ /dev/null
@@ -1,39 +0,0 @@
-#include <stdio.h>
-
-#ifdef PROTOTYPES
-void long_line (); int oof (int);
-void bar (int x)
-#else
-void bar (x) int x;
-#endif
-{
-    printf ("%d\n", x);
-
-    long_line ();
-}
-
-static void
-unused ()
-{
-    /* Not used for anything */
-}
-/* This routine has a very long line that will break searching in older versions of GDB.  */
-#ifdef PROTOTYPES
-void
-#endif
-long_line ()
-{
-  oof (67);
-
-  oof (6789);
-
-  oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*  5 */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /* 10 */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /* 15 */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /* 20 */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /* 25 */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /* 30 */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /* 35 */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /* 40 */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /* 45 */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /* 50 */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /* 55 */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /* 60 */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /* 65 */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (12); /*    */      oof (12);  oof (12);  oof (12);  oof (12);  oof (12);  oof (1234); /* 70 */
-}
-#ifdef PROTOTYPES
-int oof (int n)
-#else
-oof (n) int n;
-#endif
-{
-  return n + 1;
-}

diff --git a/gdb/testsuite/gdb.gdbtk/simple.c b/gdb/testsuite/gdb.gdbtk/simple.c
deleted file mode 100644 (file)
index c4d4ef5..0000000
--- a/gdb/testsuite/gdb.gdbtk/simple.c
+++ /dev/null
@@ -1,23 +0,0 @@
-#include <string.h>
-#include <stdlib.h>
-
-int
-main(int argc, char * argv[])
-{
-   int i;
-   char *a;
-   char *b = "abc";
-   long  foo;
-
-   a = (char *) malloc (300);
-
-   for (i=0; i < 50; i++)
-     {
-       int j = i % 3;
-       int k = 3 - j;
-       strncpy (&a[i], &b[k], j);
-       foo = (long) j * k / i + 2 * k * k * k;
-     }
-   return 0;
-}
-

diff --git a/gdb/testsuite/gdb.gdbtk/srcwin.exp b/gdb/testsuite/gdb.gdbtk/srcwin.exp
deleted file mode 100644 (file)
index c9267d8..0000000
--- a/gdb/testsuite/gdb.gdbtk/srcwin.exp
+++ /dev/null
@@ -1,71 +0,0 @@
-# Copyright 1999, 2001 Red Hat, Inc.
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms of the GNU General Public License (GPL) as published by
-# the Free Software Foundation; either version 2 of the License, or (at
-# your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-
-load_lib ../gdb.gdbtk/insight-support.exp
-
-if {[gdbtk_initialize_display]} {
-  if {$tracelevel} {
-    strace $tracelevel
-  }
-
-  #
-  # test source window
-  #
-  set prms_id 0
-  set bug_id 0
-  
-  set testfile "list"
-  set s1 "$srcdir/$subdir/list0.c"
-  set sources "$s1 $srcdir/$subdir/list1.c"
-  set binfile $objdir/$subdir/$testfile
-  if {[file exists $s1.save]} {
-    catch {file delete $s1}
-    file rename $s1.save $s1
-  }
-  set r [gdb_compile $sources "$binfile" executable debug]
-  if  { $r != "" } {
-    gdb_suppress_entire_file \
-      "Testcase compile failed, so some tests in this file will automatically fail."
-  }
-
-  # Start with a fresh gdbtk
-  gdb_exit
-  set results [gdbtk_start [file join $srcdir $subdir srcwin.test]]
-  set results [split $results \n]
-  set all_results $results
-
-  # move file with "main" out of the way
-  file rename $s1 $s1.save
-
-  # run slightly different set of tests
-  gdb_exit
-  set results [gdbtk_start [file join $srcdir $subdir srcwin2.test]]
-  set results [split $results \n]
-  set all_results [concat $all_results $results]
-
-  # restore file
-  file rename $s1.save $s1
-
-  set r [gdb_compile $sources "$binfile" executable ""]
-  if  { $r != "" } {
-    gdb_suppress_entire_file \
-      "Testcase compile failed, so some tests in this file will automatically fail."
-  }
-  # run slightly different set of tests
-  gdb_exit
-  set results [gdbtk_start [file join $srcdir $subdir srcwin3.test]]
-  set results [split $results \n]
-  set all_results [concat $all_results $results]
-
-  # Analyze results
-  gdbtk_done $all_results
-}

diff --git a/gdb/testsuite/gdb.gdbtk/srcwin.test b/gdb/testsuite/gdb.gdbtk/srcwin.test
deleted file mode 100644 (file)
index a1bae8c..0000000
--- a/gdb/testsuite/gdb.gdbtk/srcwin.test
+++ /dev/null
@@ -1,1189 +0,0 @@
-#   Copyright (C) 1999, 2001 Red Hat, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-# This file was written by Martin Hunt (hunt@cygnus.com)
-
-# Read in the standard defs file
-
-if {![gdbtk_read_defs]} {
-  break
-}
-
-global objdir srcdir
-
-
-# move the pointer to the center of the bbox relative to $win
-proc move_mouse_to {win bbox} {
-  if {[llength $bbox] != 4} {
-    return 0
-  }
-  set x [expr [lindex $bbox 0] + [lindex $bbox 2] / 2]
-  set y [expr [lindex $bbox 1] + [lindex $bbox 3] / 2]
-  warp_pointer . [winfo rootx $win] [winfo rooty $win]
-
-  set nx 0
-  set ny 0
-
-  while {$nx != $x || $ny != $y} {
-    if {$nx < $x} {incr nx}
-    if {$ny < $y} {incr ny}
-    warp_pointer $win $nx $ny
-  }
-  return 1
-}
-
-proc click {win bbox bnum} {
-  if {![move_mouse_to $win $bbox]} {
-    return 0
-  }
-  update
-
-  set x [expr [lindex $bbox 0] + [lindex $bbox 2] / 2]
-  set y [expr [lindex $bbox 1] + [lindex $bbox 3] / 2]
-
-  if {[catch {event generate $win <Button-$bnum> -x $x -y $y} result]} {
-    return 0
-  }
-  if {[catch {event generate $win <ButtonRelease-$bnum> -x $x -y $y} result]} {
-    return 0
-  }
-  return 1
-}
-
-
-#####                 #####
-#                         #
-#  SECTION 1: Mode Tests  #
-#                         #
-#####                 #####
-
-# Load the test executable
-set program [file join $objdir list]
-if {[catch {gdbtk_test_file $program} t]} {
-  # This isn't a test case, since if this fails, we're hosed.
-  gdbtk_test_error "loading \"$program\": $t"
-}
-
-set srcwin [ManagedWin::open SrcWin]
-set stw [$srcwin test_get twin]
-set twin [$stw test_get twin]
-
-# get things started
-gdb_cmd "break main"
-gdbtk_test_run
-
-# Test: srcwin-1.1
-# Desc: Check for something in source window
-gdbtk_test srcwin-1.1 "source window has contents" {
-  set file1(source) [$twin get 1.0 end]
-  expr {![string compare $file1(source) ""]}
-} {0}
-
-
-# Test: srcwin-1.2
-# Desc: source->assembly mode change
-gdbtk_test srcwin-1.2 "source->assembly mode change" {
-  $srcwin mode "" ASSEMBLY
-  set twin [$stw test_get twin]
-  set file1(assembly) [$twin get 1.0 end]
-  expr {![string compare $file1(source) $file1(assembly)]}
-} {0}
-
-# Test: srcwin-1.3
-# Desc: assembly->mixed mode change
-gdbtk_test srcwin-1.3 "assembly->mixed mode change" {
-  $srcwin mode "" MIXED
-  set twin [$stw test_get twin]
-  set file1(mixed) [$twin get 1.0 end]
-  expr {![string compare $file1(mixed) $file1(assembly)]}
-} {0}
-
-# Test: srcwin-1.4
-# Desc: mixed->src+asm mode change
-gdbtk_test srcwin-1.4 "mixed->src+asm mode change" {
-  $srcwin mode "" SRC+ASM
-  set twin [$stw test_get twin]
-  set bwin [$stw test_get bwin]
-  set s [$twin get 1.0 end]
-  set a [$bwin get 1.0 end]
-  list [string compare $a $file1(assembly)] [string compare $s $file1(source)] [winfo ismapped $bwin]
-} {0 0 1}
-
-# Test: srcwin-1.5
-# Desc: src+asm->source mode change
-gdbtk_test srcwin-1.5 "src+asm->source mode change" {
-  $srcwin mode "" SOURCE
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  set bwin [$stw test_get bwin]
-  list [string compare $file1(source) $a] [winfo ismapped $bwin]
-} {0 0}
-
-# Test: srcwin-1.6
-# Desc: source->mixed mode change
-gdbtk_test srcwin-1.6 "source->mixed mode change" {
-  $srcwin mode "" MIXED
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  string compare $file1(mixed) $a
-} {0}
-
-# Test: srcwin-1.7
-# Desc: mixed->source mode change
-gdbtk_test srcwin-1.7 "mixed->source mode change" {
-  $srcwin mode "" SOURCE
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  string compare $file1(source) $a
-} {0}
-
-# Test: srcwin-1.8
-# Desc: source->src+asm mode change
-gdbtk_test srcwin-1.8 "source->src+asm mode change" {
-  $srcwin mode "" SRC+ASM
-  set twin [$stw test_get twin]
-  set bwin [$stw test_get bwin]
-  set s [$twin get 1.0 end]
-  set a [$bwin get 1.0 end]
-  list [string compare $a $file1(assembly)] [string compare $s $file1(source)] [winfo ismapped $bwin]
-} {0 0 1}
-
-# Test: srcwin-1.9
-# Desc: src+asm->assembly mode change
-gdbtk_test srcwin-1.9 "src+asm->assembly mode change" {
-  $srcwin mode "" ASSEMBLY
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  string compare $file1(assembly) $a
-} {0}
-
-# Test: srcwin-1.10
-# Desc: assembly->src+asm mode change
-gdbtk_test srcwin-1.10 "assembly->src+asm mode change" {
-  $srcwin mode "" SRC+ASM
-  set twin [$stw test_get twin]
-  set bwin [$stw test_get bwin]
-  set s [$twin get 1.0 end]
-  set a [$bwin get 1.0 end]
-  list [string compare $a $file1(assembly)] [string compare $s $file1(source)] [winfo ismapped $bwin]
-} {0 0 1}
-
-# Test: srcwin-1.11
-# Desc: src+asm->mixed mode change
-gdbtk_test srcwin-1.11 "src+asm->mixed mode change" {
-  $srcwin mode "" MIXED
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  set bwin [$stw test_get bwin]
-  expr {[string compare $file1(mixed) $a] ||
-       [winfo ismapped $bwin]}
-} {0}
-
-# Test: srcwin-1.12
-# Desc: mixed->assembly mode change
-gdbtk_test srcwin-1.12 "mixed->assembly mode change" {
-  $srcwin mode "" ASSEMBLY
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  string compare $file1(assembly) $a
-} {0}
-
-# Test: srcwin-1.13
-# Desc: assembly->source mode change
-gdbtk_test srcwin-1.13 "assembly->source mode change" {
-  $srcwin mode "" SOURCE
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  string compare $file1(source) $a
-} {0}
-
-
-#####                       #####
-#                               #
-#  SECTION 2: Basic Operations  #
-#                               #
-#####                       #####
-
-# Test: srcwin-2.1
-# Desc: check contents of filename combobox
-gdbtk_test srcwin-2.1 "check contents of filename combobox" {
-  set statbar [$srcwin test_get _statbar]
-  set names [$statbar.name list get 0 end]
-  set r 0
-  foreach f {list0.c list1.c} {
-    if {[lsearch $names $f] != -1} {
-      incr r
-    }
-  }
-  set r
-} {2}
-
-# Test: srcwin-2.2
-# Desc: check contents of function combobox
-gdbtk_test srcwin-2.2 "check contents of function combobox" {
-  set names [$statbar.func list get 0 end]
-  set r 0
-  foreach f {main foo unused} {
-    if {[lsearch $names $f] != -1} {
-      incr r
-    }
-  }
-  set r
-} {3}
-
-# Test: srcwin-2.3
-# Desc: goto filename
-gdbtk_test srcwin-2.3 "goto filename" {
-  set func [$srcwin test_get _name 1]
-  $func "" list1.c
-  set twin [$stw test_get twin]
-  set file2(source) [$twin get 1.0 end]
-  expr {![string compare $file1(source) $file2(source)]}
-} {0}
-
-# Test: srcwin-2.4
-# Desc: check contents of function combobox
-gdbtk_test srcwin-2.4 "check contents of function combobox" {
-  set names [$statbar.func list get 0 end]
-  set r 0
-  foreach f {bar long_line oof unused} {
-    if {[lsearch $names $f] != -1} {
-      incr r
-    }
-  }
-  set r
-} {4}
-
-# Test: srcwin-2.5
-# Desc: function combobox entry field should be empty after switching to a new file
-gdbtk_test srcwin-2.5 "function combobox entry field should be empty" {
-  set names [$statbar.func get]
-  string length $names
-} {0}
-
-# Test: srcwin-2.6
-# Desc: goto function
-gdbtk_test srcwin-2.6 "goto function bar" {
-  $srcwin goto_func "" bar
-  set r 0
-
-  # now get a dump of all tags and check that only one line is
-  # marked BROWSE_TAG and no lines are STACK_TAG or PC_TAG.
-
-  # We know that list1.c should have BROWSE_TAG set at index 5.2
-  # for function "bar".  If list1.c is changed or the layout of the source
-  # window is changed, this must be updated.
-  if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-    foreach {k v i} $z {
-      if {$k == "tagon"} {
-       if {$v == "BROWSE_TAG"} {
-         if {$i == "10.2"} {
-           incr r
-         } else {
-           incr r 5
-         }
-       }
-       if {$v == "STACK_TAG"} { incr r 10}
-       if {$v == "PC_TAG"} { incr r 100}
-      }
-    }
-  } else {
-    set r -1
-  }
-
-  if {$r == 1} {
-    # things are OK so far, so just verify the function name is displayed
-    # in the combobox entry field.
-    set names [$statbar.func get]
-    if {[string compare $names "bar"]} {set r -2}
-  }
-  set r
-} {1}
-
-# Test: srcwin-2.7
-# Desc: goto function "oof". This tests that the correct line is highlighted
-# with BROWSE_TAG and no other lines are highlighted. It also checks that
-# the combobox has the correct function name in it.  Finally, list1.c
-# has an extremely long line, line 32, that breaks some functions.  We verify 
-# that the GDBtk has the correct line number.
-
-gdbtk_test srcwin-2.7 "goto function oof" {
-  $srcwin goto_func "" oof
-  set r 0
-
-  # now get a dump of all tags and check that only one line is
-  # marked BROWSE_TAG and no lines are STACK_TAG or PC_TAG.
-
-  # We know that list1.c should have BROWSE_TAG set at index 32.2
-  # for function "oof".  If list1.c is changed or the layout of the source
-  # window is changed, this must be updated.
-  if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-    foreach {k v i} $z {
-      if {$k == "tagon"} {
-       if {$v == "BROWSE_TAG"} {
-         if {$i == "38.2"} {
-           set line_number [$twin get "$i wordstart" "$i wordend"]
-           if {$line_number == "38"} {
-             incr r
-           } else {
-             incr r -100
-           }
-         } else {
-           incr r 5
-         }
-       }
-       if {$v == "STACK_TAG"} {incr r 10}
-       if {$v == "PC_TAG"} {incr r 100}
-      }
-    }
-  } else {
-    set r -1
-  }
-
-  if {$r == 1} {
-    # things are OK so far, so just verify the function name is displayed
-    # in the combobox entry field.
-    set names [$statbar.func get]
-    if {[string compare $names "oof"]} {set r -2}
-  }
-  set r
-} {1}
-
-# Test: srcwin-2.8
-# Desc: This test issues a next command while browsing list1.c.
-# It should display list0.c and highlight the correct line.
-gdbtk_test srcwin-2.8 "step while browsing" {
-  gdb_immediate "next" 1
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != "list0.c"} {set r -1}
-  if {$func != "main"} {set r -2}
-
-  # check that correct file is displayed
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  if {[string compare $file1(source) $a]} {set r -3}
-
-  # check for PC_TAG on correct line
-  if {$r == 0} {
-    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "PC_TAG"} {
-           if {$i == "11.2"} {
-             incr r
-           } else {
-             incr r 5
-           }
-         }
-         if {$v == "STACK_TAG"} {incr r 10}
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  set r
-} {1}
-
-# Test: srcwin-2.9
-# Desc: This test issues a next command while the current
-# PC is ready to call a function.  It should not go into the function and
-# should update the PC highlight correctly.
-gdbtk_test srcwin-2.9 "next" {
-  gdb_immediate "next" 1
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != "list0.c"} {set r -1}
-  if {$func != "main"} {set r -2}
-
-  # check that correct file is displayed
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  if {[string compare $file1(source) $a]} {set r -3}
-
-  # check for PC_TAG on correct line
-  if {$r == 0} {
-    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "PC_TAG"} {
-           if {$i == "12.2"} {
-             incr r
-           } else {
-             incr r 5
-           }
-         }
-         if {$v == "STACK_TAG"} {incr r 10}
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  set r
-} {1}
-
-# Test: srcwin-2.10
-# Desc: This test issues a step command while the current
-# PC is ready to call a function.  It should step into the function.
-gdbtk_test srcwin-2.10 "step" {
-  gdb_immediate "step" 1
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != "list0.h"} {set r -1}
-  if {$func != "foo"} {set r -2}
-
-  # check that a new file is displayed
-  set twin [$stw test_get twin]
-  set file3(source) [$twin get 1.0 end]
-  if {![string compare $file1(source) $file3(source)]} {set r -3}
-
-  # check for PC_TAG on correct line
-  if {$r == 0} {
-    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "PC_TAG"} {
-           if {$i == "9.2"} {
-             incr r
-           } else {
-             incr r 5
-           }
-         }
-         if {$v == "STACK_TAG"} {incr r 10}
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  set r
-} {1}
-
-# Test: srcwin-2.11
-# Desc: This test issues a break and a continue
-gdbtk_test srcwin-2.11 "set BP and continue" {
-  gdb_immediate "break oof" 1
-  gdb_immediate "continue" 1
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != "list1.c"} {set r -1}
-  if {$func != "oof"} {set r -2}
-
-  # check that the correct file is displayed
-  # we must clear the breakpoint first so it doesn't mess up the
-  # comparison...
-  gdb_immediate "clear oof" 1  
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  if {[string compare $file2(source) $a]} {set r -3}
-  
-  # check for PC_TAG on correct line
-  if {$r == 0} {
-    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "PC_TAG"} {
-           if {$i == "38.2"} {
-             incr r
-           } else {
-             incr r 5
-           }
-         }
-         if {$v == "STACK_TAG"} {incr r 10}
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  set r
-} {1}
-
-#####                       #####
-#                               #
-#  SECTION 3: Stack Operations  #
-#                               #
-#####                       #####
-
-# Test: srcwin-3.1
-# Desc: This tests "stack up" 
-gdbtk_test srcwin-3.1 "stack up (1)" {
-  $srcwin stack up
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != "list1.c"} {set r -1}
-  if {$func != "long_line"} {set r -2}
-
-  # check that the correct file is displayed
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  if {[string compare $file2(source) $a]} {set r -3}
-  
-  # check for PC_TAG and STACK_TAG on correct lines
-  if {$r == 0} {
-    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "PC_TAG"} {
-           # return n + 1;
-           if {$i == "38.2"} {
-             incr r
-           } else {
-             incr r 5
-           }
-         }
-         if {$v == "STACK_TAG"} {
-           # oof (67);
-           if {$i == "26.2"} {
-             incr r
-           } else {
-             incr r 10
-           }
-         }
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  set r
-} {2}
-
-# Test: srcwin-3.2
-# Desc: Another "stack up"  test
-gdbtk_test srcwin-3.2 "stack up (2)" {
-  $srcwin stack up
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != "list1.c"} {set r -1}
-  if {$func != "bar"} {set r -2}
-
-  # check that the correct file is displayed
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  if {[string compare $file2(source) $a]} {set r -3}
-  
-  # check for PC_TAG and STACK_TAG on correct lines
-  if {$r == 0} {
-    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "PC_TAG"} {
-           # return n + 1;
-           if {$i == "38.2"} {
-             incr r
-           } else {
-             incr r 5
-           }
-         }
-         if {$v == "STACK_TAG"} {
-           # long_line ();
-           if {$i == "12.2"} {
-             incr r
-           } else {
-             incr r 10
-           }
-         }
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  set r
-} {2}
-
-# Test: srcwin-3.3
-# Desc: Another "stack up"  test
-gdbtk_test srcwin-3.3 "stack up (3)" {
-  $srcwin stack up
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != "list0.h"} {set r -1}
-  if {$func != "foo"} {set r -2}
-
-  # check that the correct file is displayed
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  if {![string compare $file2(source) $a]} {set r -3}
-  
-  # check for PC_TAG and STACK_TAG on correct lines
-  if {$r == 0} {
-    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "STACK_TAG"} {
-           if {$i == "9.2"} {
-             incr r
-           } else {
-             incr r 5
-           }
-         }
-         if {$v == "PC_TAG"} {incr r 10}
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  set r
-} {1}
-
-# Test: srcwin-3.4
-# Desc: Another "stack up"  test
-gdbtk_test srcwin-3.4 "stack up (4)" {
-  $srcwin stack up
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != "list0.c"} {set r -1}
-  if {$func != "main"} {set r -2}
-
-  # check that the correct file is displayed
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  if {[string compare $file1(source) $a]} {set r -3}
-  
-  # check for PC_TAG and STACK_TAG on correct lines
-  if {$r == 0} {
-    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "STACK_TAG"} {
-           if {$i == "12.2"} {
-             incr r
-           } else {
-             incr r 5
-           }
-         }
-         if {$v == "PC_TAG"} {incr r 10}
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  set r
-} {1}
-
-# Disabled for now because there are different correct results.
-# Test should be rewritten to include those.
-# Test: srcwin-3.5
-# Desc: "stack up" when we are at the top
-#gdbtk_test srcwin-3.5 "stack up when at the top" {
-#  $srcwin stack up
-#  set r 0
-#  set name [$statbar.name get]
-#  set func [$statbar.func get]
-#
-  # check contents of name and function comboboxes
-#  if {$name != "list0.c"} {set r -1}
-#  if {$func != "main"} {set r -2}
-
-  # check that the correct file is displayed
-#  set twin [$stw test_get twin]
-#  set a [$twin get 1.0 end]
-#  if {[string compare $file1(source) $a]} {set r -3}
-  
-  # check for PC_TAG and STACK_TAG on correct lines
-#  if {$r == 0} {
-#    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-#      foreach {k v i} $z {
-#      if {$k == "tagon"} {
-#        if {$v == "STACK_TAG"} {
-#          if {$i == "12.2"} {
-#            incr r
-#          } else {
-#            incr r 5
-#          }
-#        }
-#        if {$v == "PC_TAG"} {incr r 10}
-#        if {$v == "BROWSE_TAG"} {incr r 100}
-#      }
-#      }
-#    } else {
-#      set r -4
-#    }
-#  }
-#  set r
-#} {1}
-
-# Test: srcwin-3.6
-# Desc: "stack down"  test
-gdbtk_test srcwin-3.6 "stack down" {
-  $srcwin stack down
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != "list0.h"} {set r -1}
-  if {$func != "foo"} {set r -2}
-
-  # check that the correct file is displayed
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  if {![string compare $file2(source) $a]} {set r -3}
-  
-  # check for PC_TAG and STACK_TAG on correct lines
-  if {$r == 0} {
-    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "STACK_TAG"} {
-           if {$i == "9.2"} {
-             incr r
-           } else {
-             incr r 5
-           }
-         }
-         if {$v == "PC_TAG"} {incr r 10}
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  set r
-} {1}
-
-# Test: srcwin-3.7
-# Desc: "stack bottom"  test
-gdbtk_test srcwin-3.7 "stack bottom" {
-  $srcwin stack bottom
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != "list1.c"} {set r -1}
-  if {$func != "oof"} {set r -2}
-
-  # check that the correct file is displayed
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  if {[string compare $file2(source) $a]} {set r -3}
-  
-  # check for PC_TAG on correct line
-  if {$r == 0} {
-    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "PC_TAG"} {
-           if {$i == "38.2"} {
-             incr r
-           } else {
-             incr r 5
-           }
-         }
-         if {$v == "STACK_TAG"} {incr r 10}
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  set r
-} {1}
-
-# Test: srcwin-3.8
-# Desc: "stack down" when at bottom
-gdbtk_test srcwin-3.8 "stack down when at bottom" {
-  $srcwin stack down
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != "list1.c"} {set r -1}
-  if {$func != "oof"} {set r -2}
-
-  # check that the correct file is displayed
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  if {[string compare $file2(source) $a]} {set r -3}
-  
-  # check for PC_TAG on correct line
-  if {$r == 0} {
-    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "PC_TAG"} {
-           if {$i == "38.2"} {
-             incr r
-           } else {
-             incr r 5
-           }
-         }
-         if {$v == "STACK_TAG"} {incr r 10}
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  set r
-} {1}
-
-# 4 -  BREAKPOINTS
-
-# Test: srcwin-4.1
-# Desc: Set BP in another file. Tests bp and cache functions
-gdbtk_test srcwin-4.1 "set BP in another file" {
-  gdb_immediate "break foo" 1
-  $srcwin goto_func "" foo
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != "list0.h"} {set r -1}
-  if {$func != "foo"} {set r -2}
-
-  set twin [$stw test_get twin]
-  
-  # check for BROWSE_TAG and BP image on correct line
-  if {$r == 0} {
-    if {![catch {set z [$twin dump 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "BROWSE_TAG"} {
-           if {$i == "9.2"} {
-             incr r
-           } else {
-             incr r 5
-           }
-         }
-         if {$v == "STACK_TAG"} {incr r 10}
-         if {$v == "PC_TAG"} {incr r 100}
-       } elseif {$k == "image"} {
-         if {$i == "9.0"} {
-           incr r
-         } else {
-           set r -200
-         }
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  
-  if {$r == 2} {
-    # clear BP and compare with previous contents. This should succeed,
-    gdb_immediate "clear foo" 1
-    set a [$twin get 1.0 end]
-    if {[string compare $file3(source) $a]} {set r -3}
-  }
-  
-  set r
-} {2}
-
-# Test: srcwin-4.2
-# Desc: Test temporary BP
-gdbtk_test srcwin-4.2 "temporary BP" {
-  set r 0
-  if {[catch {gdb_immediate "tbreak foo" 1} msg]} {
-    set r -500
-  }
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-  
-  # check contents of name and function comboboxes
-  if {$name != "list0.h"} {set r -1}
-  if {$func != "foo"} {set r -2}
-
-  set twin [$stw test_get twin]
-  
-  # check for BROWSE_TAG and BP image on correct line
-  if {$r == 0} {
-    if {![catch {set z [$twin dump 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "BROWSE_TAG"} {
-           if {$i == "9.2"} {
-             incr r
-           } else {
-             incr r 5
-           }
-         }
-         if {$v == "STACK_TAG"} {incr r 10}
-         if {$v == "PC_TAG"} {incr r 100}
-       } elseif {$k == "image"} {
-         if {$i == "9.0"} {
-           incr r
-         } else {
-           set r -200
-         }
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  
-  gdb_immediate "continue" 1
-  
-  # now check for PC_TAG and no image
-  if {$r == 2} {
-    if {![catch {set z [$twin dump 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "PC_TAG"} {
-           if {$i == "9.2"} {
-             incr r
-           } else {
-             incr r 5
-           }
-         }
-         if {$v == "STACK_TAG"} {incr r 10}
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       } elseif {$k == "image"} {
-         set r -200
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  
-  set r
-} {3}
-
-# Test: srcwin-4.3
-# Desc: Test BP balloons
-gdbtk_test srcwin-4.3 "BP Balloons" {
-  # move pointer out of the way
-  warp_pointer . 0 0 
-  set r 0
-  gdb_immediate "break 10" 1
-  gdb_immediate "tbreak 10" 1
-
-  set twin [$stw test_get twin]
-  
-  # check for BROWSE_TAG and BP image on correct line
-  if {$r == 0} {
-    if {![catch {set z [$twin dump 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "PC_TAG"} {
-           if {$i == "9.2"} {
-             incr r
-           } else {
-             incr r 5
-           }
-         }
-         if {$v == "STACK_TAG"} {incr r 10}
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       } elseif {$k == "image"} {
-         if {$i == "10.0"} {
-           incr r
-           # we found the bp image, now we will test the bp balloon messages
-           set balloon [winfo toplevel [namespace tail $srcwin]].__balloon
-           # shouldn't be mapped yet
-           if {[winfo ismapped $balloon]} {
-             set r -3000
-             break
-           }
-           move_mouse_to $twin [$twin bbox $i]
-           #wait a second for the balloon message to appear
-           sleep 1
-           if {![winfo ismapped $balloon]} {
-             set r -4000
-             break
-           }
-           # read the contents of the balloon and parse it into lines
-           set a [split [$balloon.label cget -text] \n]
-           set i 0
-           # foreach line parse it and check the type and make sure it is enabled
-           foreach line $a {
-             if {[lindex $line 0] == "breakpoint"} {continue}
-             incr i
-             set enabled [lindex $line 0]
-             set bptype [lindex $line 2]
-             switch $i {
-               1 {
-                 if {$bptype != "donttouch"} {set r -1000}
-               }
-               2 {
-                 if {$bptype != "delete"} {set r -2000}
-               }
-             }
-           }
-         } else {
-           set r -200
-         }
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  set r
-} {2}
-
-#ManagedWin::open DebugWin
-
-# Test: srcwin-4.4
-# Desc: Click on line to set BP
-gdbtk_test srcwin-4.4 "Click on line to set BP" {
-  set r 0
-
-  # click mouse button 1 at index 20.1
-  if {![click $twin [$twin bbox 20.1] 1]} {
-    set r "Click failed on line 20.1"
-  } else {
-
-    # now look for BP at line 20
-    foreach bpnum [gdb_get_breakpoint_list] {
-      set bpinfo [gdb_get_breakpoint_info $bpnum]
-      lassign $bpinfo file func line pc type enabled disposition \
-       ignore_count commands cond thread hit_count
-      set file [lindex [file split $file] end]
-      if {$file == "list0.h"} {
-       if {$line == "20"} {
-         if {$enabled == "1"} {incr r}
-         if {$func == "foo"} {incr r}
-         if {$type == "breakpoint"} {incr r}
-         if {$disposition == "donttouch"} {incr r}
-       }
-      }
-    }
-  }
-  set r
-} {4}
-
-
-# Test: srcwin-4.5
-# Desc: Continue till here popup
-gdbtk_test srcwin-4.5 "Continue till here popup" {
-  set twin [$stw test_get twin]
-
-  # Get coordinates of line 16
-  set b [$twin bbox 16.1]
-  set y [expr {[lindex $b 1] + ([lindex $b 3] / 2)}]
-
-  # Continue to here
-  $stw continue_to_here $twin $y
-
-  # Where is the PC_TAG?
-  set pcs {}
-  set tags [$twin tag ranges PC_TAG]
-  foreach {start end} $tags {
-    lappend pcs [expr {int($start)}]
-  }
-
-  # Where are breakpoints?
-  set bps {}
-  set imgs [$twin dump -image 1.0 end]
-  foreach {foo bar line} $imgs {
-    lappend bps $line
-  }
-
-  list $pcs $bps
-} {16 {10.0 20.0}}
-
-# 5.1 balloon variables
-# Test: srcwin-5.1
-# Desc: variable balloon test
-# continues to BP at line 20 and checks to see that value was updated
-gdbtk_test srcwin-5.1 "variable balloon test" {
-  # move pointer out of the way
-  warp_pointer . 0 0 
-  set r 0
-  set twin [$stw test_get twin]
-
-  # move pointer to variable "x" and check balloon
-  set index [string first "x++" [$twin get 20.0 20.end]]
-  move_mouse_to $twin [$twin bbox 20.$index]
-  sleep 1
-  if {[winfo ismapped $balloon]} {
-    if {![string compare "x=9" [$balloon.label cget -text]]} {incr r}
-    gdb_immediate "continue" 1
-    sleep 1
-    if {![string compare "x=13" [$balloon.label cget -text]]} {incr r}
-  } else {
-    set r -1
-  }
-
-  set r
-} {2}
-
-# 6.1 mixed mode disassembly of include file
-# Test: srcwin-6.1
-# Desc: Some versions of GDBtk can't do mixed-mode disassembly of a function
-# that is in an include file. PR# mi/1101
-
-gdbtk_test srcwin-6.1 "mixed mode disassembly of include file (mi/1101)" {
-  set r 0
-  $srcwin mode "" MIXED
-
-  # check contents of name and function comboboxes
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-  if {$name != "list0.h"} {set r -1}
-  if {$func != "foo"} {set r -2}
-  
-  # check contents of source window
-  set twin [$stw test_get twin]
-  set text [$twin get 1.0 end]
-  # Is it correct? I don't know.  Guess we look for some pieces of source...
-  if {[string first "static void" $text] != -1 &&
-      [string first "foo (x)" $text] != -1 &&
-      [string first "bar (x++);" $text] != -1} {
-    set r 1
-  }
-  
-  set r
-} {1}
-
-gdbtk_test_done

diff --git a/gdb/testsuite/gdb.gdbtk/srcwin2.test b/gdb/testsuite/gdb.gdbtk/srcwin2.test
deleted file mode 100644 (file)
index 926e0f5..0000000
--- a/gdb/testsuite/gdb.gdbtk/srcwin2.test
+++ /dev/null
@@ -1,896 +0,0 @@
-#   Copyright (C) 1999, 2001 Red Hat, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-# This file was written by Martin Hunt (hunt@cygnus.com)
-
-
-# same as srcwin.test, except test debugging executables
-# when source files are missing.
-
-# Read in the standard defs file
-
-if {![gdbtk_read_defs]} {
-  break
-}
-
-global objdir srcdir
-
-#####                 #####
-#                         #
-#  SECTION 1: Mode Tests  #
-#                         #
-#####                 #####
-
-# Load the test executable
-set program [file join $objdir list]
-if {[catch {gdbtk_test_file $program} t]} {
-  # This isn't a test case, since if this fails, we're hosed.
-  gdbtk_test_error "loading \"$program\": $t"
-}
-
-set srcwin [ManagedWin::open SrcWin]
-set stw [$srcwin test_get twin]
-set twin [$stw test_get twin]
-set statbar [$srcwin test_get _statbar]
-
-# get things started
-gdb_cmd "break main"
-gdbtk_test_run
-
-# Test: srcwin2-1.1
-# Desc: Check for something in source window
-gdbtk_test srcwin2-1.1 "source window has contents" {
-  set r 0
-  set file1(source) [$twin get 1.0 end]
-  if {$file1(source) == ""} {set r -1}
-  if {[$statbar.mode get] != "ASSEMBLY"} {set r -2}
-  set r
-} {0}
-
-# Test: srcwin2-1.2
-# Desc: source->assembly mode change
-gdbtk_test srcwin2-1.2 "source->assembly mode change" {
-  $srcwin mode "" ASSEMBLY
-  set twin [$stw test_get twin]
-  set file1(assembly) [$twin get 1.0 end]
-  # source == assembly because for there is no source
-  string compare $file1(source) $file1(assembly)
-} {0}
-
-# Test: srcwin2-1.3
-# Desc: assembly->mixed mode change
-gdbtk_test srcwin2-1.3 "assembly->mixed mode change" {
-  set r 0
-  $srcwin mode "" MIXED
-  set twin [$stw test_get twin]
-  set file1(mixed) [$twin get 1.0 end]
-  # mixed != assembly because the lines with source should
-  # be noted, even if source in unavailable. This behaviour is
-  # different for different debug formats, so we accept either.
-  if {$file1(mixed) == ""} {set r -1}
-  if {[$statbar.mode get] != "MIXED"} {set r -2}
-  set r        
-} {0}
-
-# Test: srcwin2-1.4
-# Desc: mixed->src+asm mode change
-gdbtk_test srcwin2-1.4 "mixed->src+asm mode change" {
-  set r 0
-  # mode change may fail if fallover to ASSEMBLY fails
-  if {[catch {$srcwin mode "" SRC+ASM}]} { set r -5 }
-  set twin [$stw test_get twin]
-  if {[$twin get 1.0 end] != $file1(assembly)} {set r -1}
-  if {[$statbar.mode get] != "ASSEMBLY"} {set r -2}
-  set r
-} {0}
-
-# Test: srcwin2-1.5
-# Desc: src+asm->source mode change
-gdbtk_test srcwin2-1.5 "src+asm->source mode change" {
-  set r 0
-  $srcwin mode "" SOURCE
-  set twin [$stw test_get twin]
-  if {[$stw test_get bwin] != ""} {set r -2}
-  if {[$twin get 1.0 end] != $file1(assembly)} {set r -1}
-  if {[$statbar.mode get] != "ASSEMBLY"} {set r -3}
-  set r
-} {0}
-
-# Test: srcwin2-1.6
-# Desc: source->mixed mode change
-gdbtk_test srcwin2-1.6 "source->mixed mode change" {
-  set r 0
-  $srcwin mode "" MIXED
-  set twin [$stw test_get twin]
-  if {[$twin get 1.0 end] != $file1(mixed)} {set r -1}
-  if {[$statbar.mode get] != "MIXED"} {set r -2}
-  set r
-} {0}
-
-# Test: srcwin2-1.7
-# Desc: mixed->source mode change
-gdbtk_test srcwin2-1.7 "mixed->source mode change" {
-  set r 0
-  $srcwin mode "" SOURCE
-  set twin [$stw test_get twin]
-  if {[$twin get 1.0 end] != $file1(source)} {set r -1}
-  if {[$statbar.mode get] != "ASSEMBLY"} {set r -2}
-  set r
-} {0}
-
-# Test: srcwin2-1.8
-# Desc: source->src+asm mode change
-gdbtk_test srcwin2-1.8 "source->src+asm mode change" {
-  set r 0
-  # mode change may fail if fallover to ASSEMBLY fails
-  if {[catch {$srcwin mode "" SRC+ASM}]} { set r -5 }
-  set twin [$stw test_get twin]
-  set bwin [$stw test_get bwin]
-  if {[$twin get 1.0 end] != $file1(assembly)} {set r -1}
-  if {$bwin != ""} {set r -2}
-  if {[$statbar.mode get] != "ASSEMBLY"} {set r -3}
-  set r
-} {0}
-
-# Test: srcwin2-1.9
-# Desc: src+asm->assembly mode change
-gdbtk_test srcwin2-1.9 "src+asm->assembly mode change" {
-  set r 0
-  $srcwin mode "" ASSEMBLY
-  set twin [$stw test_get twin]
-  if {[$twin get 1.0 end] != $file1(assembly)} {set r -1}
-  if {[$statbar.mode get] != "ASSEMBLY"} {set r -2}
-  set r
-} {0}
-
-# Test: srcwin2-1.10
-# Desc: assembly->src+asm mode change
-gdbtk_test srcwin2-1.10 "assembly->src+asm mode change" {
-  set r 0
-  # mode change may fail if fallover to ASSEMBLY fails
-  if {[catch {$srcwin mode "" SRC+ASM}]} { set r -5 }
-  set twin [$stw test_get twin]
-  set bwin [$stw test_get bwin]
-  if {[$twin get 1.0 end] != $file1(assembly)} {set r -1}
-  if {$bwin != ""} {set r -2}
-  if {[$statbar.mode get] != "ASSEMBLY"} {set r -3}
-  set r
-} {0}
-
-# Test: srcwin2-1.11
-# Desc: src+asm->mixed mode change
-gdbtk_test srcwin2-1.11 "src+asm->mixed mode change" {
-  set r 0
-  $srcwin mode "" MIXED
-  set twin [$stw test_get twin]
-  if {[$twin get 1.0 end] != $file1(mixed)} {set r -1}
-  if {[$statbar.mode get] != "MIXED"} {set r -2}
-  set r
-} {0}
-
-# Test: srcwin2-1.12
-# Desc: mixed->assembly mode change
-gdbtk_test srcwin2-1.12 "mixed->assembly mode change" {
-  set r 0
-  $srcwin mode "" ASSEMBLY
-  set twin [$stw test_get twin]
-  if {[$twin get 1.0 end] != $file1(assembly)} {set r -1}
-  if {[$statbar.mode get] != "ASSEMBLY"} {set r -2}
-  set r
-} {0}
-
-# Test: srcwin2-1.13
-# Desc: assembly->source mode change
-gdbtk_test srcwin2-1.13 "assembly->source mode change" {
-  set r 0
-  $srcwin mode "" SOURCE
-  set twin [$stw test_get twin]
-  if {[$twin get 1.0 end] != $file1(source)} {set r -1}
-  if {[$statbar.mode get] != "ASSEMBLY"} {set r -2}
-  set r
-} {0}
-
-
-#####                       #####
-#                               #
-#  SECTION 2: Basic Operations  #
-#                               #
-#####                       #####
-
-# Test: srcwin2-2.1
-# Desc: check contents of filename combobox
-gdbtk_test srcwin2-2.1 "check contents of filename combobox" {
-  set names [$statbar.name list get 0 end]
-  set r 0
-  foreach f {list0.c list1.c} {
-    if {[lsearch $names $f] != -1} {
-      incr r
-    }
-  }
-  set r
-} {2}
-
-# Test: srcwin2-2.2
-# Desc: check contents of function combobox
-gdbtk_test srcwin2-2.2 "check contents of function combobox" {
-  set names [$statbar.func list get 0 end]
-  set r 0
-  foreach f {main foo unused} {
-    if {[lsearch $names $f] != -1} {
-      incr r
-    }
-  }
-  set r
-} {3}
-
-# Test: srcwin2-2.3
-# Desc: goto filename
-gdbtk_test srcwin2-2.3 "goto filename" {
-  set func [$srcwin test_get _name 1]
-  $func "" list1.c
-  set twin [$stw test_get twin]
-  set file2(source) [$twin get 1.0 end]
-  expr {![string compare $file1(source) $file2(source)]}
-} {0}
-
-# Test: srcwin2-2.4
-# Desc: check contents of function combobox
-gdbtk_test srcwin2-2.4 "check contents of function combobox" {
-  set names [$statbar.func list get 0 end]
-  set r 0
-  foreach f {bar long_line oof unused} {
-    if {[lsearch $names $f] != -1} {
-      incr r
-    }
-  }
-  set r
-} {4}
-
-# Test: srcwin2-2.5
-# Desc: function combobox entry field should be empty after switching to a new file
-gdbtk_test srcwin2-2.5 "function combobox entry field should be empty" {
-  set names [$statbar.func get]
-  string length $names
-} {0}
-
-# Test: srcwin2-2.6
-# Desc: goto function
-gdbtk_test srcwin2-2.6 "goto function bar" {
-  $srcwin goto_func "" bar
-  set r 0
-
-  # now get a dump of all tags and check that only one line is
-  # marked BROWSE_TAG and no lines are STACK_TAG or PC_TAG.
-
-  # We know that list1.c should have BROWSE_TAG set at index 10.2
-  # for function "bar".  If list1.c is changed or the layout of the source
-  # window is changed, this must be updated.
-  if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-    foreach {k v i} $z {
-      if {$k == "tagon"} {
-       if {$v == "BROWSE_TAG"} {
-         if {$i == "10.2"} {
-           incr r
-         } else {
-           incr r 5
-         }
-       }
-       if {$v == "STACK_TAG"} { incr r 10}
-       if {$v == "PC_TAG"} { incr r 100}
-      }
-    }
-  } else {
-    set r -1
-  }
-
-  if {$r == 1} {
-    # things are OK so far, so just verify the function name is displayed
-    # in the combobox entry field.
-    set names [$statbar.func get]
-    if {[string compare $names "bar"]} {set r -2}
-  }
-  set r
-} {1}
-
-# Test: srcwin2-2.7
-# Desc: goto function "oof". This tests that the correct line is highlighted
-# with BROWSE_TAG and no other lines are highlighted. It also checks that
-# the combobox has the correct function name in it.  Finally, list1.c
-# has an extremely long line, line 32, that breaks some functions.  We verify 
-# that the GDBtk has the correct line number.
-
-gdbtk_test srcwin2-2.7 "goto function oof" {
-  $srcwin goto_func "" oof
-  set r 0
-
-  # now get a dump of all tags and check that only one line is
-  # marked BROWSE_TAG and no lines are STACK_TAG or PC_TAG.
-
-  # We know that list1.c should have BROWSE_TAG set at index 38.2
-  # for function "oof".  If list1.c is changed or the layout of the source
-  # window is changed, this must be updated.
-  if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-    foreach {k v i} $z {
-      if {$k == "tagon"} {
-       if {$v == "BROWSE_TAG"} {
-         if {$i == "38.2"} {
-           set line_number [$twin get "$i wordstart" "$i wordend"]
-           if {$line_number == "38"} {
-             incr r
-           } else {
-             incr r -100
-           }
-         } else {
-           incr r 5
-         }
-       }
-       if {$v == "STACK_TAG"} {incr r 10}
-       if {$v == "PC_TAG"} {incr r 100}
-      }
-    }
-  } else {
-    set r -1
-  }
-
-  if {$r == 1} {
-    # things are OK so far, so just verify the function name is displayed
-    # in the combobox entry field.
-    set names [$statbar.func get]
-    if {[string compare $names "oof"]} {set r -2}
-  }
-  set r
-} {1}
-
-# Test: srcwin2-2.8
-# Desc: This test issues a next command while browsing list1.c.
-# It should display list0.c and highlight the correct line.
-gdbtk_test srcwin2-2.8 "step while browsing" {
-  gdb_immediate "next" 1
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != "list0.c"} {set r -1}
-  if {$func != "main"} {set r -2}
-
-  # check that correct file is displayed
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  if {[string compare $file1(source) $a]} {set r -3}
-
-  # check for PC_TAG
-  if {$r == 0} {
-    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "PC_TAG"} {
-           incr r
-         }
-         if {$v == "STACK_TAG"} {incr r 10}
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  set r
-} {1}
-
-# Test: srcwin2-2.11
-# Desc: This test issues a break and a continue
-gdbtk_test srcwin2-2.11 "set BP and continue" {
-  gdb_immediate "break oof" 1
-  gdb_immediate "continue" 1
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != "list1.c"} {set r -1}
-  if {$func != "oof"} {set r -2}
-
-  # check that the correct file is displayed
-  # we must clear the breakpoint first so it doesn't mess up the
-  # comparison...
-  gdb_immediate "clear oof" 1  
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  if {[string compare $file2(source) $a]} {set r -3}
-  
-  # check for PC_TAG on correct line
-  if {$r == 0} {
-    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "PC_TAG"} {
-           if {$i == "38.2"} {
-             incr r
-           } else {
-             incr r 5
-           }
-         }
-         if {$v == "STACK_TAG"} {incr r 10}
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  set r
-} {1}
-
-#####                       #####
-#                               #
-#  SECTION 3: Stack Operations  #
-#                               #
-#####                       #####
-
-# Test: srcwin2-3.1
-# Desc: This tests "stack up" 
-gdbtk_test srcwin2-3.1 "stack up (1)" {
-  $srcwin stack up
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != "list1.c"} {set r -1}
-  if {$func != "long_line"} {set r -2}
-
-  # check that the correct file is displayed
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  if {[string compare $file2(source) $a]} {set r -3}
-  
-  # check for PC_TAG and STACK_TAG on correct lines
-  if {$r == 0} {
-    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "PC_TAG"} {
-           if {$i == "38.2"} {
-             incr r
-           } else {
-             incr r 5
-           }
-         }
-         if {$v == "STACK_TAG"} {
-           if {$i == "26.2"} {
-             incr r
-           } else {
-             incr r 10
-           }
-         }
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  set r
-} {2}
-
-# Test: srcwin2-3.2
-# Desc: Another "stack up"  test
-gdbtk_test srcwin2-3.2 "stack up (2)" {
-  $srcwin stack up
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != "list1.c"} {set r -1}
-  if {$func != "bar"} {set r -2}
-
-  # check that the correct file is displayed
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  if {[string compare $file2(source) $a]} {set r -3}
-  
-  # check for PC_TAG and STACK_TAG on correct lines
-  if {$r == 0} {
-    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "PC_TAG"} {
-           if {$i == "38.2"} {
-             incr r
-           } else {
-             incr r 5
-           }
-         }
-         if {$v == "STACK_TAG"} {
-           if {$i == "12.2"} {
-             incr r
-           } else {
-             incr r 10
-           }
-         }
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  set r
-} {2}
-
-# Test: srcwin2-3.3
-# Desc: Another "stack up"  test
-gdbtk_test srcwin2-3.3 "stack up (3)" {
-  $srcwin stack up
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != "list0.h"} {set r -1}
-  if {$func != "foo"} {set r -2}
-
-  # check that the correct file is displayed
-  set twin [$stw test_get twin]
-  set file3(source) [$twin get 1.0 end]
-  if {![string compare $file2(source) $file3(source)]} {set r -3}
-  
-  # check for PC_TAG and STACK_TAG on correct lines
-  if {$r == 0} {
-    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "STACK_TAG"} {
-           if {$i == "9.2"} {
-             incr r
-           } else {
-             incr r 5
-           }
-         }
-         if {$v == "PC_TAG"} {incr r 10}
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  set r
-} {1}
-
-# Test: srcwin2-3.4
-# Desc: Another "stack up"  test
-gdbtk_test srcwin2-3.4 "stack up (4)" {
-  $srcwin stack up
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != "list0.c"} {set r -1}
-  if {$func != "main"} {set r -2}
-
-  # check that the correct file is displayed
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  if {[string compare $file1(source) $a]} {set r -3}
-  
-  # check for STACK_TAG
-  if {$r == 0} {
-    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "STACK_TAG"} {
-           incr r
-         }
-         if {$v == "PC_TAG"} {incr r 10}
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  set r
-} {1}
-
-
-# Disabled for now because there are different correct results.
-# Test should be rewritten to include those.
-# Test: srcwin2-3.5
-# Desc: "stack up" when we are at the top
-#gdbtk_test srcwin2-3.5 "stack up when at the top" {
-# $srcwin stack up
-#  set r 0
-#  set name [$statbar.name get]
-#  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-#  if {$name != "list0.c"} {set r -1}
-#  if {$func != "main"} {set r -2}
-
-  # check that the correct file is displayed
-#  set twin [$stw test_get twin]
-#  set a [$twin get 1.0 end]
-#  if {[string compare $file1(source) $a]} {set r -3}
-  
-  # check for STACK_TAG
-#  if {$r == 0} {
-#    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-#      foreach {k v i} $z {
-#      if {$k == "tagon"} {
-#        if {$v == "STACK_TAG"} {
-#          incr r
-#        }
-#        if {$v == "PC_TAG"} {incr r 10}
-#        if {$v == "BROWSE_TAG"} {incr r 100}
-#      }
-#      }
-#    } else {
-#      set r -4
-#    }
-#  }
-#  set r
-#} {1}
-
-# Test: srcwin2-3.6
-# Desc: "stack down"  test
-gdbtk_test srcwin2-3.6 "stack down" {
-  $srcwin stack down
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != "list0.h"} {set r -1}
-  if {$func != "foo"} {set r -2}
-
-  # check that the correct file is displayed
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  if {![string compare $file2(source) $a]} {set r -3}
-  
-  # check for PC_TAG and STACK_TAG on correct lines
-  if {$r == 0} {
-    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "STACK_TAG"} {
-           if {$i == "9.2"} {
-             incr r
-           } else {
-             incr r 5
-           }
-         }
-         if {$v == "PC_TAG"} {incr r 10}
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  set r
-} {1}
-
-# Test: srcwin2-3.7
-# Desc: "stack bottom"  test
-gdbtk_test srcwin2-3.7 "stack bottom" {
-  $srcwin stack bottom
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != "list1.c"} {set r -1}
-  if {$func != "oof"} {set r -2}
-
-  # check that the correct file is displayed
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  if {[string compare $file2(source) $a]} {set r -3}
-  
-  # check for PC_TAG on correct line
-  if {$r == 0} {
-    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "PC_TAG"} {
-           if {$i == "38.2"} {
-             incr r
-           } else {
-             incr r 5
-           }
-         }
-         if {$v == "STACK_TAG"} {incr r 10}
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  set r
-} {1}
-
-# Test: srcwin2-3.8
-# Desc: "stack down" when at bottom
-gdbtk_test srcwin2-3.8 "stack down when at bottom" {
-  $srcwin stack down
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != "list1.c"} {set r -1}
-  if {$func != "oof"} {set r -2}
-
-  # check that the correct file is displayed
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  if {[string compare $file2(source) $a]} {set r -3}
-  
-  # check for PC_TAG on correct line
-  if {$r == 0} {
-    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "PC_TAG"} {
-           if {$i == "38.2"} {
-             incr r
-           } else {
-             incr r 5
-           }
-         }
-         if {$v == "STACK_TAG"} {incr r 10}
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  set r
-} {1}
-
-# 4.1 bp, multiple, balloon, etc
-
-# Test: srcwin2-4.1
-# Desc: Set BP in another file. Tests bp and cache functions
-gdbtk_test srcwin2-4.1 "set BP in another file" {
-  gdb_immediate "break foo" 1
-  $srcwin goto_func "" foo
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != "list0.h"} {set r -1}
-  if {$func != "foo"} {set r -2}
-
-  set twin [$stw test_get twin]
-  
-  # check for BROWSE_TAG and BP image on correct line
-  if {$r == 0} {
-    if {![catch {set z [$twin dump 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "BROWSE_TAG"} {
-           if {$i == "9.2"} {
-             incr r
-           } else {
-             incr r 5
-           }
-         }
-         if {$v == "STACK_TAG"} {incr r 10}
-         if {$v == "PC_TAG"} {incr r 100}
-       } elseif {$k == "image"} {
-         if {$i == "9.0"} {
-           incr r
-         } else {
-           set r -200
-         }
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  
-  if {$r == 2} {
-    # clear BP and compare with previous contents. This should succeed,
-    gdb_immediate "clear foo" 1
-    set a [$twin get 1.0 end]
-    if {[string compare $file3(source) $a]} {set r -3}
-  }
-  
-  set r
-} {2}
-
-# Test: srcwin2-4.2
-# Desc: Test temporary BP
-gdbtk_test srcwin2-4.2 "temporary BP" {
-  set r 0
-  if {[catch {gdb_immediate "tbreak foo" 1} msg]} {
-    set r -500
-  }
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-  
-  # check contents of name and function comboboxes
-  if {$name != "list0.h"} {set r -1}
-  if {$func != "foo"} {set r -2}
-
-  set twin [$stw test_get twin]
-  
-  # check for BROWSE_TAG and BP image on correct line
-  if {$r == 0} {
-    if {![catch {set z [$twin dump 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "BROWSE_TAG"} {
-           if {$i == "9.2"} {
-             incr r
-           } else {
-             incr r 5
-           }
-         }
-         if {$v == "STACK_TAG"} {incr r 10}
-         if {$v == "PC_TAG"} {incr r 100}
-       } elseif {$k == "image"} {
-         if {$i == "9.0"} {
-           incr r
-         } else {
-           set r -200
-         }
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  
-  gdb_immediate "continue" 1
-  
-  # now check for PC_TAG and no image
-  if {$r == 2} {
-    if {![catch {set z [$twin dump 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "PC_TAG"} {
-           if {$i == "9.2"} {
-             incr r
-           } else {
-             incr r 5
-           }
-         }
-         if {$v == "STACK_TAG"} {incr r 10}
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       } elseif {$k == "image"} {
-         set r -200
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  
-  set r
-} {3}
-
-gdbtk_test_done

diff --git a/gdb/testsuite/gdb.gdbtk/srcwin3.test b/gdb/testsuite/gdb.gdbtk/srcwin3.test
deleted file mode 100644 (file)
index c752a6b..0000000
--- a/gdb/testsuite/gdb.gdbtk/srcwin3.test
+++ /dev/null
@@ -1,786 +0,0 @@
-#   Copyright (C) 1999, 2001 Red Hat, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-# This file was written by Martin Hunt (hunt@cygnus.com)
-
-###########################################################
-# same as srcwin.test, except test debugging executables  #
-# build without "-g"                                      #
-###########################################################
-
-# Read in the standard defs file
-
-if {![gdbtk_read_defs]} {
-  break
-}
-
-global objdir srcdir
-
-#####                 #####
-#                         #
-#  SECTION 1: Mode Tests  #
-#                         #
-#####                 #####
-
-# Load the test executable
-set program [file join $objdir list]
-if {[catch {gdbtk_test_file $program} t]} {
-  # This isn't a test case, since if this fails, we're hosed.
-  gdbtk_test_error "loading \"$program\": $t"
-}
-
-set srcwin [ManagedWin::open SrcWin]
-set stw [$srcwin test_get twin]
-set twin [$stw test_get twin]
-set statbar [$srcwin test_get _statbar]
-
-# get things started
-gdb_cmd "break main"
-gdbtk_test_run
-
-# Test: srcwin3-1.1
-# Desc: Check for something in source window
-gdbtk_test srcwin3-1.1 "source window has contents" {
-  set r 0
-  set source(main) [$twin get 1.0 end]
-  if {$source(main) == ""} {set r -1}
-  if {[$statbar.mode get] != "ASSEMBLY"} {set r -2}
-  set r
-} {0}
-
-# Test: srcwin3-1.2
-# Desc: source->assembly mode change
-gdbtk_test srcwin3-1.2 "source->assembly mode change" {
-  set r 0
-  $srcwin mode "" ASSEMBLY
-  set twin [$stw test_get twin]
-  if {$source(main) != [$twin get 1.0 end]} {set r -1}
-  if {[$statbar.mode get] != "ASSEMBLY"} {set r -2}
-  set r
-} {0}
-
-# Test: srcwin3-1.3
-# Desc: assembly->mixed mode change
-gdbtk_test srcwin3-1.3 "assembly->mixed mode change" {
-  set r 0
-  $srcwin mode "" MIXED
-  set twin [$stw test_get twin]
-  if {$source(main) != [$twin get 1.0 end]} {set r -1}
-  if {[$statbar.mode get] != "MIXED"} {set r -2}
-  set r
-} {0}
-
-# Test: srcwin3-1.4
-# Desc: mixed->src+asm mode change
-gdbtk_test srcwin3-1.4 "mixed->src+asm mode change" {
-  set r 0
-  # mode change may fail if fallover to ASSEMBLY fails
-  if {[catch {$srcwin mode "" SRC+ASM}]} { set r -5 }
-  set twin [$stw test_get twin]
-  if {[$twin get 1.0 end] != $source(main)} {set r -1}
-  if {[$statbar.mode get] != "ASSEMBLY"} {set r -2}
-  set r
-} {0}
-
-# Test: srcwin3-1.5
-# Desc: src+asm->source mode change
-gdbtk_test srcwin3-1.5 "src+asm->source mode change" {
-  set r 0
-  $srcwin mode "" SOURCE
-  set twin [$stw test_get twin]
-  if {[$stw test_get bwin] != ""} {set r -2}
-  if {[$twin get 1.0 end] != $source(main)} {set r -1}
-  if {[$statbar.mode get] != "ASSEMBLY"} {set r -3}
-  set r
-} {0}
-
-# Test: srcwin3-1.6
-# Desc: source->mixed mode change
-gdbtk_test srcwin3-1.6 "source->mixed mode change" {
-  set r 0
-  $srcwin mode "" MIXED
-  set twin [$stw test_get twin]
-  if {[$twin get 1.0 end] != $source(main)} {set r -1}
-  if {[$statbar.mode get] != "MIXED"} {set r -2}
-  set r
-} {0}
-
-# Test: srcwin3-1.7
-# Desc: mixed->source mode change
-gdbtk_test srcwin3-1.7 "mixed->source mode change" {
-  set r 0
-  $srcwin mode "" SOURCE
-  set twin [$stw test_get twin]
-  if {[$twin get 1.0 end] != $source(main)} {set r -1}
-  if {[$statbar.mode get] != "ASSEMBLY"} {set r -2}
-  set r
-} {0}
-
-# Test: srcwin3-1.8
-# Desc: source->src+asm mode change
-gdbtk_test srcwin3-1.8 "source->src+asm mode change" {
-  set r 0
-  # mode change may fail if fallover to ASSEMBLY fails
-  if {[catch {$srcwin mode "" SRC+ASM}]} { set r -5 }
-  set twin [$stw test_get twin]
-  set bwin [$stw test_get bwin]
-  if {[$twin get 1.0 end] != $source(main)} {set r -1}
-  if {$bwin != ""} {set r -2}
-  if {[$statbar.mode get] != "ASSEMBLY"} {set r -3}
-  set r
-} {0}
-
-# Test: srcwin3-1.9
-# Desc: src+asm->assembly mode change
-gdbtk_test srcwin3-1.9 "src+asm->assembly mode change" {
-  set r 0
-  $srcwin mode "" ASSEMBLY
-  set twin [$stw test_get twin]
-  if {[$twin get 1.0 end] != $source(main)} {set r -1}
-  if {[$statbar.mode get] != "ASSEMBLY"} {set r -2}
-  set r
-} {0}
-
-# Test: srcwin3-1.10
-# Desc: assembly->src+asm mode change
-gdbtk_test srcwin3-1.10 "assembly->src+asm mode change" {
-  set r 0
-  # mode change may fail if fallover to ASSEMBLY fails
-  if {[catch {$srcwin mode "" SRC+ASM}]} { set r -5 }
-  set twin [$stw test_get twin]
-  set bwin [$stw test_get bwin]
-  if {[$twin get 1.0 end] != $source(main)} {set r -1}
-  if {$bwin != ""} {set r -2}
-  if {[$statbar.mode get] != "ASSEMBLY"} {set r -3}
-  set r
-} {0}
-
-# Test: srcwin3-1.11
-# Desc: src+asm->mixed mode change
-gdbtk_test srcwin3-1.11 "src+asm->mixed mode change" {
-  set r 0
-  $srcwin mode "" MIXED
-  set twin [$stw test_get twin]
-  if {[$twin get 1.0 end] != $source(main)} {set r -1}
-  if {[$statbar.mode get] != "MIXED"} {set r -2}
-  set r
-} {0}
-
-# Test: srcwin3-1.12
-# Desc: mixed->assembly mode change
-gdbtk_test srcwin3-1.12 "mixed->assembly mode change" {
-  set r 0
-  $srcwin mode "" ASSEMBLY
-  set twin [$stw test_get twin]
-  if {[$twin get 1.0 end] != $source(main)} {set r -1}
-  if {[$statbar.mode get] != "ASSEMBLY"} {set r -2}
-  set r
-} {0}
-
-# Test: srcwin3-1.13
-# Desc: assembly->source mode change
-gdbtk_test srcwin3-1.13 "assembly->source mode change" {
-  set r 0
-  $srcwin mode "" SOURCE
-  set twin [$stw test_get twin]
-  if {[$twin get 1.0 end] != $source(main)} {set r -1}
-  if {[$statbar.mode get] != "ASSEMBLY"} {set r -2}
-  set r
-} {0}
-
-
-#####                       #####
-#                               #
-#  SECTION 2: Basic Operations  #
-#                               #
-#####                       #####
-
-# Test: srcwin3-2.2
-# Desc: check contents of function combobox
-# There won't be any because we have no debug info
-gdbtk_test srcwin3-2.2 "check contents of function combobox" {
-  set names [$statbar.func list get 0 end]
-  llength $names
-} {0}
-
-# Test: srcwin3-2.3
-# Desc: goto filename - this won't work, but should leave things as they were
-gdbtk_test srcwin3-2.3 "goto filename" {
-  set func [$srcwin test_get _name 1]
-  $func "" list1.c
-  set twin [$stw test_get twin]
-  string compare $source(main) [$twin get 1.0 end]
-} {0}
-
-# Test: srcwin3-2.6
-# Desc: goto function
-gdbtk_test srcwin3-2.6 "goto function bar" {
-  $srcwin goto_func "" bar
-  set r 0
-  set twin [$stw test_get twin]
-  set source(bar) [$twin get 1.0 end]
-  
-  if {$source(bar) == $source(main)} {set r -1000}
-
-  # now get a dump of all tags and check that only one line is
-  # marked BROWSE_TAG and no lines are STACK_TAG or PC_TAG.
-
-  # We know that list1.c should have BROWSE_TAG set at index 5.2
-  # for function "bar".  If list1.c is changed or the layout of the source
-  # window is changed, this must be updated.
-  if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-    foreach {k v i} $z {
-      if {$k == "tagon"} {
-       if {$v == "BROWSE_TAG"} {
-         incr r
-       }
-       if {$v == "STACK_TAG"} { incr r 10}
-       if {$v == "PC_TAG"} { incr r 100}
-      }
-    }
-  } else {
-    set r -1
-  }
-
-  if {$r == 1} {
-    # things are OK so far, so just verify the function name is displayed
-    # in the combobox entry field.
-    set names [$statbar.func get]
-    if {[string compare $names "bar"]} {set r -2}
-  }
-  set r
-} {1}
-
-# Test: srcwin3-2.7
-# Desc: goto function "oof". This tests that the correct line is highlighted
-# with BROWSE_TAG and no other lines are highlighted. It also checks that
-# the combobox has the correct function name in it.  
-
-gdbtk_test srcwin3-2.7 "goto function oof" {
-  $srcwin goto_func "" oof
-  set r 0
-
-  set twin [$stw test_get twin]
-  set source(oof) [$twin get 1.0 end]
-  
-  if {$source(bar) == $source(oof)} {set r -1000}
-  if {$source(oof) == $source(main)} {set r -2000}
-
-  # now get a dump of all tags and check that only one line is
-  # marked BROWSE_TAG and no lines are STACK_TAG or PC_TAG.
-
-  if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-    foreach {k v i} $z {
-      if {$k == "tagon"} {
-       if {$v == "BROWSE_TAG"} {
-         incr r
-       }
-       if {$v == "STACK_TAG"} {incr r 10}
-       if {$v == "PC_TAG"} {incr r 100}
-      }
-    }
-  } else {
-    set r -1
-  }
-
-  if {$r == 1} {
-    # things are OK so far, so just verify the function name is displayed
-    # in the combobox entry field.
-    set names [$statbar.func get]
-    if {[string compare $names "oof"]} {set r -2}
-  }
-  set r
-} {1}
-
-# Test: srcwin3-2.8
-# Desc: This test issues a nexti command while browsing oof.
-# It should jump back to main
-gdbtk_test srcwin3-2.8 "nexti while browsing" {
-  gdb_immediate "nexti" 1
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of function combobox
-  if {$func != "main"} {set r -2}
-  if {$name != ""} {set r -1}
-
-  # check that correct file is displayed
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  if {[string compare $source(main) $a]} {set r -3}
-
-  # check for PC_TAG
-  if {$r == 0} {
-    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "PC_TAG"} {
-           incr r
-         }
-         if {$v == "STACK_TAG"} {incr r 10}
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  set r
-} {1}
-
-# Test: srcwin3-2.11
-# Desc: This test issues a break and a continue
-gdbtk_test srcwin3-2.11 "set BP and continue" {
-  gdb_immediate "break oof" 1
-  gdb_immediate "continue" 1
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != ""} {set r -1}
-  if {$func != "oof"} {set r -2}
-  
-  # check that the correct file is displayed
-  # we must clear the breakpoint first so it doesn't mess up the
-  # comparison...
-  gdb_immediate "clear oof" 1  
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  if {[string compare $source(oof) $a]} {set r -3}
-  
-  # check for PC_TAG
-  if {$r == 0} {
-    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "PC_TAG"} {
-           incr r
-         }
-         if {$v == "STACK_TAG"} {incr r 10}
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  set r
-} {1}
-
-#####                       #####
-#                               #
-#  SECTION 3: Stack Operations  #
-#                               #
-#####                       #####
-
-# Test: srcwin3-3.1
-# Desc: This tests "stack up" 
-gdbtk_test srcwin3-3.1 "stack up (1)" {
-  $srcwin stack up
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != ""} {set r -1}
-  if {$func != "long_line"} {set r -2}
-
-  # check that the correct file is displayed
-  set twin [$stw test_get twin]
-  set source(long_line) [$twin get 1.0 end]
-  if {![string compare $source(long_line) $source(oof)]} {set r -3}
-  
-  # check for PC_TAG and STACK_TAG on correct lines
-  if {$r == 0} {
-    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "PC_TAG"} {incr r 5}
-         if {$v == "STACK_TAG"} {incr r}
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  set r
-} {1}
-
-# Test: srcwin3-3.2
-# Desc: Another "stack up"  test
-gdbtk_test srcwin3-3.2 "stack up (2)" {
-  $srcwin stack up
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != ""} {set r -1}
-  if {$func != "bar"} {set r -2}
-
-  # check that the correct file is displayed
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  if {[string compare $source(bar) $a]} {set r -3}
-  
-  # check for PC_TAG and STACK_TAG on correct lines
-  if {$r == 0} {
-    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "PC_TAG"} {
-           set r -100
-         }
-         if {$v == "STACK_TAG"} {
-           incr r
-         }
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  set r
-} {1}
-
-# Test: srcwin3-3.3
-# Desc: Another "stack up"  test
-gdbtk_test srcwin3-3.3 "stack up (3)" {
-  $srcwin stack up
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != ""} {set r -1}
-  if {$func != "foo"} {set r -2}
-
-  # check that the correct file is displayed
-  set twin [$stw test_get twin]
-  set source(foo) [$twin get 1.0 end]
-  if {![string compare $source(foo) $source(bar)]} {set r -3}
-  
-  # check for PC_TAG and STACK_TAG on correct lines
-  if {$r == 0} {
-    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "STACK_TAG"} {
-           incr r
-         }
-         if {$v == "PC_TAG"} {incr r 10}
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  set r
-} {1}
-
-# Test: srcwin3-3.4
-# Desc: Another "stack up"  test
-gdbtk_test srcwin3-3.4 "stack up (4)" {
-  $srcwin stack up
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != ""} {set r -1}
-  if {$func != "main"} {set r -2}
-
-  # check that the correct file is displayed
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  if {[string compare $source(main) $a]} {set r -3}
-  
-  # check for STACK_TAG
-  if {$r == 0} {
-    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "STACK_TAG"} {
-           incr r
-         }
-         if {$v == "PC_TAG"} {incr r 10}
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  set r
-} {1}
-
-# Disabled for now because there are different correct results.
-# Test should be rewritten to include those.
-# Test: srcwin3-3.5
-# Desc: "stack up" when we are at the top
-#gdbtk_test srcwin3-3.5 "stack up when at the top" {
-#  $srcwin stack up
-#  set r 0
-#  set name [$statbar.name get]
-#  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-#  if {$name != ""} {set r -1}
-#  if {$func != "main"} {set r -2}
-
-  # check that the correct file is displayed
-#  set twin [$stw test_get twin]
-#  set a [$twin get 1.0 end]
-#  if {[string compare $source(main) $a]} {set r -3}
-  
-  # check for STACK_TAG
-#  if {$r == 0} {
-#    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-#      foreach {k v i} $z {
-#      if {$k == "tagon"} {
-#        if {$v == "STACK_TAG"} {
-#          incr r
-#        }
-#        if {$v == "PC_TAG"} {incr r 10}
-#        if {$v == "BROWSE_TAG"} {incr r 100}
-#      }
-#      }
-#    } else {
-#      set r -4
-#    }
-#  }
-#  set r
-#} {1}
-
-# Test: srcwin3-3.6
-# Desc: "stack down"  test
-gdbtk_test srcwin3-3.6 "stack down" {
-  $srcwin stack down
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != ""} {set r -1}
-  if {$func != "foo"} {set r -2}
-
-  # check that the correct file is displayed
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  if {[string compare $source(foo) $a]} {set r -3}
-  
-  # check for PC_TAG and STACK_TAG on correct lines
-  if {$r == 0} {
-    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "STACK_TAG"} {
-           incr r
-         }
-         if {$v == "PC_TAG"} {incr r 10}
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  set r
-} {1}
-
-# Test: srcwin3-3.7
-# Desc: "stack bottom"  test
-gdbtk_test srcwin3-3.7 "stack bottom" {
-  $srcwin stack bottom
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != ""} {set r -1}
-  if {$func != "oof"} {set r -2}
-
-  # check that the correct file is displayed
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  if {[string compare $source(oof) $a]} {set r -3}
-  
-  # check for PC_TAG on correct line
-  if {$r == 0} {
-    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "PC_TAG"} {
-           incr r
-         }
-         if {$v == "STACK_TAG"} {incr r 10}
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  set r
-} {1}
-
-# Test: srcwin3-3.8
-# Desc: "stack down" when at bottom
-gdbtk_test srcwin3-3.8 "stack down when at bottom" {
-  $srcwin stack down
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != ""} {set r -1}
-  if {$func != "oof"} {set r -2}
-
-  # check that the correct file is displayed
-  set twin [$stw test_get twin]
-  set a [$twin get 1.0 end]
-  if {[string compare $source(oof) $a]} {set r -3}
-  
-  # check for PC_TAG on correct line
-  if {$r == 0} {
-    if {![catch {set z [$twin dump -tag 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "PC_TAG"} {
-           incr r
-         }
-         if {$v == "STACK_TAG"} {incr r 10}
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  set r
-} {1}
-
-# 4.1 bp, multiple, balloon, etc
-
-# Test: srcwin3-4.1
-# Desc: Set BP in another file. Tests bp and cache functions
-gdbtk_test srcwin3-4.1 "set BP in another file" {
-  gdb_immediate "break foo" 1
-  $srcwin goto_func "" foo
-  set r 0
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-
-  # check contents of name and function comboboxes
-  if {$name != ""} {set r -1}
-  if {$func != "foo"} {set r -2}
-
-  set twin [$stw test_get twin]
-  
-  # check for BROWSE_TAG and BP image
-  if {$r == 0} {
-    if {![catch {set z [$twin dump 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "BROWSE_TAG"} {
-           incr r
-         }
-         if {$v == "STACK_TAG"} {incr r 10}
-         if {$v == "PC_TAG"} {incr r 100}
-       } elseif {$k == "image"} {
-         incr r
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  
-  if {$r == 2} {
-    # clear BP and compare with previous contents. This should succeed,
-    gdb_immediate "clear foo" 1
-    set a [$twin get 1.0 end]
-    if {[string compare $source(foo) $a]} {set r -3}
-  }
-  
-  set r
-} {2}
-
-# Test: srcwin3-4.2
-# Desc: Test temporary BP
-gdbtk_test srcwin3-4.2 "temporary BP" {
-  set r 0
-  if {[catch {gdb_immediate "tbreak foo" 1} msg]} {
-    set r -500
-  }
-  set name [$statbar.name get]
-  set func [$statbar.func get]
-  
-  # check contents of name and function comboboxes
-  if {$name != ""} {set r -1}
-  if {$func != "foo"} {set r -2}
-
-  set twin [$stw test_get twin]
-  
-  # check for BROWSE_TAG and BP image on correct line
-  if {$r == 0} {
-    if {![catch {set z [$twin dump 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "BROWSE_TAG"} {
-           incr r
-         }
-         if {$v == "STACK_TAG"} {incr r 10}
-         if {$v == "PC_TAG"} {incr r 100}
-       } elseif {$k == "image"} {
-         incr r
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  
-  gdb_immediate "continue" 1
-  
-  # now check for PC_TAG and no image
-  if {$r == 2} {
-    if {![catch {set z [$twin dump 1.0 end]}]} {
-      foreach {k v i} $z {
-       if {$k == "tagon"} {
-         if {$v == "PC_TAG"} {
-           incr r
-         }
-         if {$v == "STACK_TAG"} {incr r 10}
-         if {$v == "BROWSE_TAG"} {incr r 100}
-       } elseif {$k == "image"} {
-         set r -200
-       }
-      }
-    } else {
-      set r -4
-    }
-  }
-  
-  set r
-} {3}
-
-gdbtk_test_done

diff --git a/gdb/testsuite/gdb.gdbtk/stack1.c b/gdb/testsuite/gdb.gdbtk/stack1.c
deleted file mode 100644 (file)
index c6bff6a..0000000
--- a/gdb/testsuite/gdb.gdbtk/stack1.c
+++ /dev/null
@@ -1,233 +0,0 @@
-#include <stdlib.h>
-
-/* Functions defined in other files */
-extern void extern_func1_1 (int a, char *b, unsigned long c);
-
-/* Functions defined in this file */
-static void static_func_1  (int a, char *b, unsigned long c);
-static void static_func_2  (int a, char *b, unsigned long c);
-static void static_func_3  (int a, char *b, unsigned long c);
-static void static_func_4  (int a, char *b, unsigned long c);
-static void static_func_5  (int a, char *b, unsigned long c);
-static void static_func_6  (int a, char *b, unsigned long c);
-static void static_func_7  (int a, char *b, unsigned long c);
-static void static_func_8  (int a, char *b, unsigned long c);
-static void static_func_9  (int a, char *b, unsigned long c);
-static void static_func_10  (int a, char *b, unsigned long c);
-static void static_func_11  (int a, char *b, unsigned long c);
-static void static_func_12  (int a, char *b, unsigned long c);
-static void static_func_13  (int a, char *b, unsigned long c);
-static void static_func_14  (int a, char *b, unsigned long c);
-static void static_func_15  (int a, char *b, unsigned long c);
-
-void func_1  (int a, char *b, unsigned long c);
-void func_2  (int a, char *b, unsigned long c);
-void func_3  (int a, char *b, unsigned long c);
-void func_4  (int a, char *b, unsigned long c);
-void func_5  (int a, char *b, unsigned long c);
-void func_6  (int a, char *b, unsigned long c);
-void func_7  (int a, char *b, unsigned long c);
-void func_8  (int a, char *b, unsigned long c);
-void func_9  (int a, char *b, unsigned long c);
-void func_10  (int a, char *b, unsigned long c);
-void func_11  (int a, char *b, unsigned long c);
-void func_12  (int a, char *b, unsigned long c);
-void func_13  (int a, char *b, unsigned long c);
-void func_14  (int a, char *b, unsigned long c);
-void func_15  (int a, char *b, unsigned long c);
-
-int
-main (int argc, char *argv[])
-{
-  int a;
-  char *b;
-  unsigned long c;
-
-  a = 1;
-  b = "This is a string.";
-  c = 0xdeadL;
-
-  func_1 (a, b, c);
-
-  exit (0);
-}
-
-void
-func_1 (int a, char *b, unsigned long c)
-{
-  func_2 (a, b, c);
-}
-
-void
-func_2 (int a, char *b, unsigned long c)
-{
-  func_3 (a, b, c);
-}
-
-void
-func_3 (int a, char *b, unsigned long c)
-{
-  func_4 (a, b, c);
-}
-
-void
-func_4 (int a, char *b, unsigned long c)
-{
-  func_5 (a, b, c);
-}
-
-void
-func_5 (int a, char *b, unsigned long c)
-{
-  func_6 (a, b, c);
-}
-
-void
-func_6 (int a, char *b, unsigned long c)
-{
-  func_7 (a, b, c);
-}
-
-void
-func_7 (int a, char *b, unsigned long c)
-{
-  func_8 (a, b, c);
-}
-
-void
-func_8 (int a, char *b, unsigned long c)
-{
-  func_9 (a, b, c);
-}
-
-void
-func_9 (int a, char *b, unsigned long c)
-{
-  func_10 (a, b, c);
-}
-
-void
-func_10 (int a, char *b, unsigned long c)
-{
-  func_11 (a, b, c);
-}
-
-void
-func_11 (int a, char *b, unsigned long c)
-{
-  func_12 (a, b, c);
-}
-
-void
-func_12 (int a, char *b, unsigned long c)
-{
-  func_13 (a, b, c);
-}
-
-void
-func_13 (int a, char *b, unsigned long c)
-{
-  func_14 (a, b, c);
-}
-
-void
-func_14 (int a, char *b, unsigned long c)
-{
-  func_15 (a, b, c);
-}
-
-void
-func_15 (int a, char *b, unsigned long c)
-{
-  static_func_1 (a, b, c);
-}
-
-static void
-static_func_1 (int a, char *b, unsigned long c)
-{
-  static_func_2 (a, b, c);
-}
-
-static void
-static_func_2 (int a, char *b, unsigned long c)
-{
-  static_func_3 (a, b, c);
-}
-
-static void
-static_func_3 (int a, char *b, unsigned long c)
-{
-  static_func_4 (a, b, c);
-}
-
-static void
-static_func_4 (int a, char *b, unsigned long c)
-{
-  static_func_5 (a, b, c);
-}
-
-static void
-static_func_5 (int a, char *b, unsigned long c)
-{
-  static_func_6 (a, b, c);
-}
-
-static void
-static_func_6 (int a, char *b, unsigned long c)
-{
-  static_func_7 (a, b, c);
-}
-
-static void
-static_func_7 (int a, char *b, unsigned long c)
-{
-  static_func_8 (a, b, c);
-}
-
-static void
-static_func_8 (int a, char *b, unsigned long c)
-{
-  static_func_9 (a, b, c);
-}
-
-static void
-static_func_9 (int a, char *b, unsigned long c)
-{
-  static_func_10 (a, b, c);
-}
-
-static void
-static_func_10 (int a, char *b, unsigned long c)
-{
-  static_func_11 (a, b, c);
-}
-
-static void
-static_func_11 (int a, char *b, unsigned long c)
-{
-  static_func_12 (a, b, c);
-}
-
-static void
-static_func_12 (int a, char *b, unsigned long c)
-{
-  static_func_13 (a, b, c);
-}
-
-static void
-static_func_13 (int a, char *b, unsigned long c)
-{
-  static_func_14 (a, b, c);
-}
-
-static void
-static_func_14 (int a, char *b, unsigned long c)
-{
-  static_func_15 (a, b, c);
-}
-
-static void
-static_func_15 (int a, char *b, unsigned long c)
-{
-  extern_func1_1 (a, b, c);
-}

diff --git a/gdb/testsuite/gdb.gdbtk/stack2.c b/gdb/testsuite/gdb.gdbtk/stack2.c
deleted file mode 100644 (file)
index db47c46..0000000
--- a/gdb/testsuite/gdb.gdbtk/stack2.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* Functions defined in this file */
-void extern_func1_1 (int, char *, unsigned long);
-void extern_func1_2 (int, char *, unsigned long);
-void extern_func1_3 (int, char *, unsigned long);
-void extern_func1_4 (int, char *, unsigned long);
-void extern_func1_5 (int, char *, unsigned long);
-void extern_func1_6 (int, char *, unsigned long);
-void extern_func1_7 (int, char *, unsigned long);
-void extern_func1_8 (int, char *, unsigned long);
-void extern_func1_9 (int, char *, unsigned long);
-void extern_func1_10 (int, char *, unsigned long);
-void extern_func1_11 (int, char *, unsigned long);
-void extern_func1_12 (int, char *, unsigned long);
-void extern_func1_13 (int, char *, unsigned long);
-void extern_func1_14 (int, char *, unsigned long);
-void extern_func1_15 (int, char *, unsigned long);
-
-void
-extern_func1_1 (int a, char *b, unsigned long c)
-{
-  extern_func1_2 (a, b, c);
-}
-
-void
-extern_func1_2 (int a, char *b, unsigned long c)
-{
-  extern_func1_3 (a, b, c);
-}
-
-void
-extern_func1_3 (int a, char *b, unsigned long c)
-{
-  extern_func1_4 (a, b, c);
-}
-
-void
-extern_func1_4 (int a, char *b, unsigned long c)
-{
-  extern_func1_5 (a, b, c);
-}
-
-void
-extern_func1_5 (int a, char *b, unsigned long c)
-{
-  extern_func1_6 (a, b, c);
-}
-
-void
-extern_func1_6 (int a, char *b, unsigned long c)
-{
-  extern_func1_7 (a, b, c);
-}
-
-void
-extern_func1_7 (int a, char *b, unsigned long c)
-{
-  extern_func1_8 (a, b, c);
-}
-
-void
-extern_func1_8 (int a, char *b, unsigned long c)
-{
-  extern_func1_9 (a, b, c);
-}
-
-void
-extern_func1_9 (int a, char *b, unsigned long c)
-{
-  extern_func1_10 (a, b, c);
-}
-
-void
-extern_func1_10 (int a, char *b, unsigned long c)
-{
-  extern_func1_11 (a, b, c);
-}
-
-void
-extern_func1_11 (int a, char *b, unsigned long c)
-{
-  extern_func1_12 (a, b, c);
-}
-
-void
-extern_func1_12 (int a, char *b, unsigned long c)
-{
-  extern_func1_13 (a, b, c);
-}
-
-void
-extern_func1_13 (int a, char *b, unsigned long c)
-{
-  extern_func1_14 (a, b, c);
-}
-
-void
-extern_func1_14 (int a, char *b, unsigned long c)
-{
-  extern_func1_15 (a, b, c);
-}
-
-void
-extern_func1_15 (int a, char *b, unsigned long c)
-{
-  /* THE END */
-  return;
-}

diff --git a/gdb/testsuite/gdb.gdbtk/windows.exp b/gdb/testsuite/gdb.gdbtk/windows.exp
deleted file mode 100644 (file)
index c5613de..0000000
--- a/gdb/testsuite/gdb.gdbtk/windows.exp
+++ /dev/null
@@ -1,41 +0,0 @@
-# Copyright 2001, 2004 Red Hat, Inc.
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms of the GNU General Public License (GPL) as published by
-# the Free Software Foundation; either version 2 of the License, or (at
-# your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-
-load_lib ../gdb.gdbtk/insight-support.exp
-
-if {[gdbtk_initialize_display]} {
-  if {$tracelevel} {
-    strace $tracelevel
-  }
-
-  #
-  # Basic window tests (basic as in, "do they open")
-  #
-  set prms_id 0
-  set bug_id 0
-
-  set srcfile [file join $srcdir $subdir c_variable.c]
-  set binfile [file join $objdir $subdir c_variable]
-  set r [gdb_compile $srcfile $binfile executable {debug}]
-  if  { $r != "" } {
-    gdb_suppress_entire_file \
-      "Testcase compile failed, so some tests in this file will automatically fail."
-  }
-
-  # Start with a fresh gdbtk
-  gdb_exit
-  set results [gdbtk_start [file join $srcdir $subdir windows.test]]
-  set results [split $results \n]
-
-  # Analyze results
-  gdbtk_done $results
-}

diff --git a/gdb/testsuite/gdb.gdbtk/windows.test b/gdb/testsuite/gdb.gdbtk/windows.test
deleted file mode 100644 (file)
index 76dd7ea..0000000
--- a/gdb/testsuite/gdb.gdbtk/windows.test
+++ /dev/null
@@ -1,128 +0,0 @@
-# Basic window tests
-# Copyright 2001, 2003 Red Hat, Inc.
-#
-# This Program Is Free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-# This file was written by Keith Seitz (keiths@cygnus.com)
-
-# Read in the standard defs file
-if {![gdbtk_read_defs]} {
-  break
-}
-
-global objdir test_ran
-
-# Windows to test
-# FIXME: TfindArgs needs to be updated before it can go in the list...
-set windows [list BpWin BrowserWin Console DebugWin KodWin LocalsWin \
-            MemWin ProcessWin RegWin StackWin TdumpWin WatchWin]
-
-# Dialogs to test
-# FIXME: ActionhDlg,TraceDlg cannot be independently opened
-set dialogs [list About AttachDlg GlobalPref SrcPref TargetSelection]
-
-# Helper proc to do all the testing
-proc do_open_close {num winlist} {
-  set i 1
-  foreach win $winlist {
-
-    # Test: windows-$num.*
-    # Desc: Open each window before running
-    set win_obj ""
-    gdbtk_test windows-$num.$i "open $win before running" {
-      set err [catch {ManagedWin::open $win} txt]
-      if {$err} {
-       # display error
-       set txt
-      } else {
-       # display "0"
-       set win_obj $txt
-       set err
-      }
-    } {0}
-
-    # Update screen
-    update idletasks
-
-    # Test: windows-{$num+1}.*
-    # Desc: Close each window before running
-    gdbtk_test windows-[expr {$num+1}].$i "close $win before running" {
-      set err [catch {delete object $win_obj} txt]
-      if {$err} {
-       # display error
-       set txt
-      } else {
-       # display "0"
-       set err
-      }
-    } {0}
-
-    # Update screen
-    update idletasks
-    incr i
-  }
-}
-
-#
-# Tests start here
-#
-
-# Counter for tests. Increment by 2 after each call to do_open_close.
-set num 1
-
-#
-# Check if all windows open with no file loaded
-#
-do_open_close $num $windows
-incr num 2
-
-# Sadly, there is no good way to unpost dialogs (except for setting
-# an after callback). Until something better comes along, skip them.
-# do_open_close $num $dialogs
-# incr num 2
-
-#
-# Check if all windows open with file loaded
-#
-
-# Load in a file
-set program [file join $objdir c_variable]
-if {[catch {gdbtk_test_file $program} t]} {
-  # This isn't a test case, since if this fails, we're hosed.
-  gdbtk_test_error "loading \"$program\": $t"
-}
-
-do_open_close $num $windows
-incr num 2
-#do_open_close $num $dialogs
-incr num 2
-
-#
-# Check if all windows open after running
-#
-
-# Break in main and run
-gdb_cmd "break main"
-gdbtk_test_run
-
-do_open_close $num $windows
-incr num 2
-#do_open_close $num $dialogs
-#incr num 2
-
-#
-#  Exit
-#
-gdbtk_test_done

diff --git a/gdb/testsuite/gdb.threads/attachstop-mt.c b/gdb/testsuite/gdb.threads/attachstop-mt.c
index fa77c9a..061411a 100644 (file)
--- a/gdb/testsuite/gdb.threads/attachstop-mt.c
+++ b/gdb/testsuite/gdb.threads/attachstop-mt.c
@@ -21,6 +21,7 @@
 #include <unistd.h>
 #include <pthread.h>
 #include <stdio.h>
+#include <string.h>
 
 /* Red Hat BZ PR 197584.c */
 

diff --git a/gdb/windows-termcap.c b/gdb/windows-termcap.c
new file mode 100644 (file)
index 0000000..9034c17
--- /dev/null
+++ b/gdb/windows-termcap.c
@@ -0,0 +1,65 @@
+/* Win32 termcap emulation.
+
+   Copyright (C) 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
+
+   Contributed by CodeSourcery, LLC.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#include <stdlib.h>
+
+/* Each of the files below is a minimal implementation of the standard
+   termcap function with the same name, suitable for use in a Windows
+   console window.  */
+
+int
+tgetent (char *buffer, char *termtype)
+{
+  return -1;
+}
+
+int
+tgetnum (char *name)
+{
+  return -1;
+}
+
+int
+tgetflag (char *name)
+{
+  return -1;
+}
+
+char *
+tgetstr (char *name, char **area)
+{
+  return NULL;
+}
+
+int
+tputs (char *string, int nlines, int (*outfun) ())
+{
+  while (*string)
+    outfun (*string++);
+
+  return 0;
+}
+
+char *
+tgoto (const char *cap, int col, int row)
+{
+  return NULL;
+}

diff --git a/include/aout/ChangeLog b/include/aout/ChangeLog
index 493b215..c25e610 100644 (file)
--- a/include/aout/ChangeLog
+++ b/include/aout/ChangeLog
@@ -1,3 +1,9 @@
+2009-10-02  Alan Modra  <amodra@bigpond.net.au>
+
+       * aout64.h (N_SHARED_LIB): Define as zero if not already defined.
+       * sun4.h (N_SHARED_LIB): Define.
+       * hp300hpux.h (N_SHARED_LIB): Don't define.
+
 2008-08-28  Tristan Gingold  <gingold@adacore.com>
 
        * stab.def: Add BNSYM, ENSYM, OSO for darwin.

diff --git a/include/aout/aout64.h b/include/aout/aout64.h
index 2e289b3..f2330ca 100644 (file)
--- a/include/aout/aout64.h
+++ b/include/aout/aout64.h
@@ -1,6 +1,6 @@
 /* `a.out' object-file definitions, including extensions to 64-bit fields
 
-   Copyright 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
+   Copyright 1999, 2000, 2001, 2003, 2009 Free Software Foundation, Inc.
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
@@ -141,11 +141,7 @@ struct external_exec
 /* Sun shared libraries, not linux.  This macro is only relevant for ZMAGIC
    files.  */
 #ifndef N_SHARED_LIB
-#if defined (TEXT_START_ADDR) && TEXT_START_ADDR == 0
 #define N_SHARED_LIB(x) (0)
-#else
-#define N_SHARED_LIB(x) ((x).a_entry < TEXT_START_ADDR)
-#endif
 #endif
 
 /* Returning 0 not TEXT_START_ADDR for OMAGIC and NMAGIC is based on

diff --git a/include/aout/hp300hpux.h b/include/aout/hp300hpux.h
index 1174761..c63e3b8 100644 (file)
--- a/include/aout/hp300hpux.h
+++ b/include/aout/hp300hpux.h
@@ -1,5 +1,5 @@
 /* Special version of <a.out.h> for use under hp-ux.
-   Copyright 1988, 1993, 1995, 2001 Free Software Foundation, Inc. */
+   Copyright 1988, 1993, 1995, 2001, 2009 Free Software Foundation, Inc. */
 
 struct hp300hpux_exec_bytes
 {
@@ -114,6 +114,3 @@ struct hp300hpux_header_extension
 #define TARGET_PAGE_SIZE 0x1000
 #define SEGMENT_SIZE 0x1000
 #define TEXT_START_ADDR 0
-
-#undef N_SHARED_LIB
-#define N_SHARED_LIB(x)  ( 0 /* no shared libraries */ )

diff --git a/include/aout/sun4.h b/include/aout/sun4.h
index 8cf0517..213d44b 100644 (file)
--- a/include/aout/sun4.h
+++ b/include/aout/sun4.h
@@ -1,6 +1,6 @@
 /* SPARC-specific values for a.out files 
 
-   Copyright 2001 Free Software Foundation, Inc.
+   Copyright 2001, 2009 Free Software Foundation, Inc.
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
@@ -43,6 +43,9 @@
    expected text address.  These kludges have gotta go!
    For linked files, should reflect reality if we know it.  */
 
+#define N_SHARED_LIB(x) ((x).a_entry < TEXT_START_ADDR \
+                        && (x).a_text >= EXEC_BYTES_SIZE)
+
 /* This differs from the version in aout64.h (which we override by defining
    it here) only for NMAGIC (we return TEXT_START_ADDR+EXEC_BYTES_SIZE;
    they return 0).  */

diff --git a/include/demangle.h b/include/demangle.h
index 4b3565b..76fab0a 100644 (file)
--- a/include/demangle.h
+++ b/include/demangle.h
@@ -381,6 +381,12 @@ enum demangle_component_type
   DEMANGLE_COMPONENT_GLOBAL_CONSTRUCTORS,
   /* Global destructors keyed to name.  */
   DEMANGLE_COMPONENT_GLOBAL_DESTRUCTORS,
+  /* A lambda closure type.  */
+  DEMANGLE_COMPONENT_LAMBDA,
+  /* A default argument scope.  */
+  DEMANGLE_COMPONENT_DEFAULT_ARG,
+  /* An unnamed type.  */
+  DEMANGLE_COMPONENT_UNNAMED_TYPE,
   /* A pack expansion.  */
   DEMANGLE_COMPONENT_PACK_EXPANSION
 };
@@ -494,6 +500,14 @@ struct demangle_component
       struct demangle_component *right;
     } s_binary;
 
+    struct
+    {
+      /* subtree, same place as d_left.  */
+      struct demangle_component *sub;
+      /* integer.  */
+      int num;
+    } s_unary_num;
+
   } u;
 };
 

diff --git a/include/dis-asm.h b/include/dis-asm.h
index 47236a0..3d126be 100644 (file)
--- a/include/dis-asm.h
+++ b/include/dis-asm.h
@@ -296,6 +296,7 @@ extern int print_insn_xtensa                (bfd_vma, disassemble_info *);
 extern int print_insn_z80              (bfd_vma, disassemble_info *);
 extern int print_insn_z8001            (bfd_vma, disassemble_info *);
 extern int print_insn_z8002            (bfd_vma, disassemble_info *);
+extern int print_insn_rx               (bfd_vma, disassemble_info *);
 
 extern disassembler_ftype arc_get_disassembler (void *);
 extern disassembler_ftype cris_get_disassembler (bfd *);

diff --git a/include/dwarf2.h b/include/dwarf2.h
index befaceb..385ab22 100644 (file)
--- a/include/dwarf2.h
+++ b/include/dwarf2.h
@@ -196,6 +196,8 @@ enum dwarf_tag
     DW_TAG_shared_type = 0x40,
     /* DWARF 4.  */
     DW_TAG_type_unit = 0x41,
+    DW_TAG_rvalue_reference_type = 0x42,
+    DW_TAG_template_alias = 0x43,
 
     DW_TAG_lo_user = 0x4080,
     DW_TAG_hi_user = 0xffff,
@@ -213,6 +215,13 @@ enum dwarf_tag
     /* Template template parameter.
        See http://gcc.gnu.org/wiki/TemplateParmsDwarf .  */
     DW_TAG_GNU_template_template_param = 0x4106,
+
+    /* Template parameter pack extension, specified at
+       http://wiki.dwarfstd.org/index.php?title=C%2B%2B0x:_Variadic_templates
+       The values of these two TAGS are in the DW_TAG_GNU_* space until the tags
+       are properly part of DWARF 5.  */
+    DW_TAG_GNU_template_parameter_pack = 0x4107,
+    DW_TAG_GNU_formal_parameter_pack = 0x4108,
     /* Extensions for UPC.  See: http://upc.gwu.edu/~upc.  */
     DW_TAG_upc_shared_type = 0x8765,
     DW_TAG_upc_strict_type = 0x8766,
@@ -254,7 +263,8 @@ enum dwarf_form
     DW_FORM_sec_offset = 0x17,
     DW_FORM_exprloc = 0x18,
     DW_FORM_flag_present = 0x19,
-    DW_FORM_sig8 = 0x20
+    DW_FORM_ref_sig8 = 0x20
+#define DW_FORM_sig8  DW_FORM_ref_sig8  /* Note: The use of DW_FORM_sig8 is deprecated.  */
   };
 
 /* Attribute names and codes.  */
@@ -353,7 +363,12 @@ enum dwarf_attribute
     DW_AT_pure          = 0x67,
     DW_AT_recursive     = 0x68,
     /* DWARF 4.  */
-    DW_AT_signature     = 0x69,
+    DW_AT_signature       = 0x69,
+    DW_AT_main_subprogram = 0x6a,
+    DW_AT_data_bit_offset = 0x6b,
+    DW_AT_const_expr      = 0x6c,
+    DW_AT_enum_class      = 0x6d,
+    DW_AT_linkage_name    = 0x6e,
 
     DW_AT_lo_user = 0x2000,    /* Implementation-defined range start.  */
     DW_AT_hi_user = 0x3ff0,    /* Implementation-defined range end.  */
@@ -393,6 +408,18 @@ enum dwarf_attribute
     DW_AT_body_begin = 0x2105,
     DW_AT_body_end   = 0x2106,
     DW_AT_GNU_vector = 0x2107,
+    /* Thread-safety annotations.
+       See http://gcc.gnu.org/wiki/ThreadSafetyAnnotation .  */
+    DW_AT_GNU_guarded_by    = 0x2108,
+    DW_AT_GNU_pt_guarded_by = 0x2109,
+    DW_AT_GNU_guarded       = 0x210a,
+    DW_AT_GNU_pt_guarded    = 0x210b,
+    DW_AT_GNU_locks_excluded = 0x210c,
+    DW_AT_GNU_exclusive_locks_required = 0x210d,
+    DW_AT_GNU_shared_locks_required = 0x210e,
+    /* One-definition rule violation detection.
+       See http://gcc.gnu.org/wiki/DwarfSeparateTypeInfo .  */
+    DW_AT_GNU_odr_signature = 0x210f,
     /* Template template argument name.
        See http://gcc.gnu.org/wiki/TemplateParmsDwarf .  */
     DW_AT_GNU_template_name = 0x2110,
@@ -831,6 +858,7 @@ enum dwarf_source_language
     DW_LANG_ObjC_plus_plus = 0x0011,
     DW_LANG_UPC = 0x0012,
     DW_LANG_D = 0x0013,
+    DW_LANG_Python = 0x0014,
 
     DW_LANG_lo_user = 0x8000,  /* Implementation-defined range start.  */
     DW_LANG_hi_user = 0xffff,  /* Implementation-defined range start.  */

diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index b7df2ac..3841f35 100644 (file)
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,12 @@
+2009-09-29  DJ Delorie  <dj@redhat.com>
+
+       * rx.h: New file.
+
+2009-09-21  Alan Modra  <amodra@bigpond.net.au>
+
+       * ppc.h (DT_PPC_TLSOPT): Define.
+       * ppc64.h (DT_PPC64_TLSOPT): Define.
+
 2009-08-10  Daniel Gutson  <dgutson@codesourcery.com>
 
        * arm.h: (SHT_ARM_DEBUGOVERLAY): New define.

diff --git a/include/elf/ppc.h b/include/elf/ppc.h
index 14c643a..e2de0ad 100644 (file)
--- a/include/elf/ppc.h
+++ b/include/elf/ppc.h
@@ -153,7 +153,10 @@ END_RELOC_NUMBERS (R_PPC_max)
   ((R) >= R_PPC_TLS && (R) <= R_PPC_GOT_DTPREL16_HA)
 
 /* Specify the value of _GLOBAL_OFFSET_TABLE_.  */
-#define DT_PPC_GOT             DT_LOPROC
+#define DT_PPC_GOT             (DT_LOPROC)
+
+/* Specify that tls descriptors should be optimized.  */
+#define DT_PPC_TLSOPT          (DT_LOPROC + 1)
 
 /* Processor specific flags for the ELF header e_flags field.  */
 

diff --git a/include/elf/ppc64.h b/include/elf/ppc64.h
index da54f3f..04ddcd9 100644 (file)
--- a/include/elf/ppc64.h
+++ b/include/elf/ppc64.h
@@ -165,4 +165,7 @@ END_RELOC_NUMBERS (R_PPC64_max)
 #define DT_PPC64_OPD           (DT_LOPROC + 1)
 #define DT_PPC64_OPDSZ         (DT_LOPROC + 2)
 
+/* Specify that tls descriptors should be optimized.  */
+#define DT_PPC64_TLSOPT                (DT_LOPROC + 3)
+
 #endif /* _ELF_PPC64_H */

diff --git a/include/elf/rx.h b/include/elf/rx.h
new file mode 100644 (file)
index 0000000..1e04f3f
--- /dev/null
+++ b/include/elf/rx.h
@@ -0,0 +1,134 @@
+/* RX ELF support for BFD.
+   Copyright (C) 2008, 2009 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef _ELF_RX_H
+#define _ELF_RX_H
+
+#include "elf/reloc-macros.h"
+
+/* Note that there are a few internal relocation types used by the
+   linker to do link-time relaxation.  If you update this file, please
+   check elf32-rx.c to see if any of the internal relocations need to
+   be, er, relocated.  */
+
+/* Preliminary relocations.  */
+START_RELOC_NUMBERS (elf_rx_reloc_type)
+
+  RELOC_NUMBER (R_RX_NONE,         0x00)
+  /* These are for data, and are bi-endian.  */
+  RELOC_NUMBER (R_RX_DIR32,        0x01) /* Was: R_RX_32.  */
+  RELOC_NUMBER (R_RX_DIR24S,       0x02) /* Was: R_RX_24.  */
+  RELOC_NUMBER (R_RX_DIR16,        0x03)
+  RELOC_NUMBER (R_RX_DIR16U,       0x04) /* Was: R_RX_16_UNS.  */
+  RELOC_NUMBER (R_RX_DIR16S,       0x05) /* Was: R_RX_16.  */
+  RELOC_NUMBER (R_RX_DIR8,         0x06)
+  RELOC_NUMBER (R_RX_DIR8U,        0x07) /* Was: R_RX_8_UNS.  */
+  RELOC_NUMBER (R_RX_DIR8S,        0x08) /* Was: R_RX_8.  */
+
+  /* Signed pc-relative values.  */
+  RELOC_NUMBER (R_RX_DIR24S_PCREL, 0x09) /* Was: R_RX_24_PCREL.  */
+  RELOC_NUMBER (R_RX_DIR16S_PCREL, 0x0a) /* Was: R_RX_16_PCREL.  */
+  RELOC_NUMBER (R_RX_DIR8S_PCREL,  0x0b) /* Was: R_RX_8_PCREL.  */
+
+  /* These are for fields in the instructions.  */
+  RELOC_NUMBER (R_RX_DIR16UL,      0x0c)
+  RELOC_NUMBER (R_RX_DIR16UW,      0x0d)
+  RELOC_NUMBER (R_RX_DIR8UL,       0x0e)
+  RELOC_NUMBER (R_RX_DIR8UW,       0x0f)
+  RELOC_NUMBER (R_RX_DIR32_REV,    0x10)
+  RELOC_NUMBER (R_RX_DIR16_REV,    0x11)
+  RELOC_NUMBER (R_RX_DIR3U_PCREL,  0x12)
+
+  /* These are extensions added by Red Hat.  */
+  RELOC_NUMBER (R_RX_RH_3_PCREL,   0x20) /* Like R_RX_DIR8S_PCREL but only 3-bits.  */
+  RELOC_NUMBER (R_RX_RH_16_OP,     0x21) /* Like R_RX_DIR16 but for opcodes - always big endian.  */
+  RELOC_NUMBER (R_RX_RH_24_OP,     0x22) /* Like R_RX_DIR24S but for opcodes - always big endian.  */
+  RELOC_NUMBER (R_RX_RH_32_OP,     0x23) /* Like R_RX_DIR32 but for opcodes - always big endian.  */
+  RELOC_NUMBER (R_RX_RH_24_UNS,    0x24) /* Like R_RX_DIR24S but for unsigned values.  */
+  RELOC_NUMBER (R_RX_RH_8_NEG,     0x25) /* Like R_RX_DIR8 but -x is stored.  */
+  RELOC_NUMBER (R_RX_RH_16_NEG,    0x26) /* Like R_RX_DIR16 but -x is stored.  */
+  RELOC_NUMBER (R_RX_RH_24_NEG,    0x27) /* Like R_RX_DIR24S but -x is stored.  */
+  RELOC_NUMBER (R_RX_RH_32_NEG,    0x28) /* Like R_RX_DIR32 but -x is stored.  */
+  RELOC_NUMBER (R_RX_RH_DIFF,      0x29) /* Subtract from a previous relocation.  */
+  RELOC_NUMBER (R_RX_RH_GPRELB,    0x2a) /* Byte value, relative to __gp.  */
+  RELOC_NUMBER (R_RX_RH_GPRELW,    0x2b) /* Word value, relative to __gp.  */
+  RELOC_NUMBER (R_RX_RH_GPRELL,    0x2c) /* Long value, relative to __gp.  */
+  RELOC_NUMBER (R_RX_RH_RELAX,     0x2d) /* Marks opcodes suitable for linker relaxation.  */
+
+  /* These are for complex relocs.  */
+  RELOC_NUMBER (R_RX_ABS32,        0x41)
+  RELOC_NUMBER (R_RX_ABS24S,       0x42)
+  RELOC_NUMBER (R_RX_ABS16,        0x43)
+  RELOC_NUMBER (R_RX_ABS16U,       0x44)
+  RELOC_NUMBER (R_RX_ABS16S,       0x45)
+  RELOC_NUMBER (R_RX_ABS8,         0x46)
+  RELOC_NUMBER (R_RX_ABS8U,        0x47)
+  RELOC_NUMBER (R_RX_ABS8S,        0x48)
+  RELOC_NUMBER (R_RX_ABS24S_PCREL, 0x49)
+  RELOC_NUMBER (R_RX_ABS16S_PCREL, 0x4a)
+  RELOC_NUMBER (R_RX_ABS8S_PCREL,  0x4b)
+  RELOC_NUMBER (R_RX_ABS16UL,      0x4c)
+  RELOC_NUMBER (R_RX_ABS16UW,      0x4d)
+  RELOC_NUMBER (R_RX_ABS8UL,       0x4e)
+  RELOC_NUMBER (R_RX_ABS8UW,       0x4f)
+  RELOC_NUMBER (R_RX_ABS32_REV,    0x50)
+  RELOC_NUMBER (R_RX_ABS16_REV,    0x51)
+
+  RELOC_NUMBER (R_RX_SYM,          0x80)
+  RELOC_NUMBER (R_RX_OPneg,        0x81)
+  RELOC_NUMBER (R_RX_OPadd,        0x82)
+  RELOC_NUMBER (R_RX_OPsub,        0x83)
+  RELOC_NUMBER (R_RX_OPmul,        0x84)
+  RELOC_NUMBER (R_RX_OPdiv,        0x85)
+  RELOC_NUMBER (R_RX_OPshla,       0x86)
+  RELOC_NUMBER (R_RX_OPshra,       0x87)
+  RELOC_NUMBER (R_RX_OPsctsize,    0x88)
+  RELOC_NUMBER (R_RX_OPscttop,     0x8d)
+  RELOC_NUMBER (R_RX_OPand,        0x90)
+  RELOC_NUMBER (R_RX_OPor,         0x91)
+  RELOC_NUMBER (R_RX_OPxor,        0x92)
+  RELOC_NUMBER (R_RX_OPnot,        0x93)
+  RELOC_NUMBER (R_RX_OPmod,        0x94)
+  RELOC_NUMBER (R_RX_OPromtop,     0x95)
+  RELOC_NUMBER (R_RX_OPramtop,     0x96)
+
+END_RELOC_NUMBERS (R_RX_max)
+
+#define EF_RX_CPU_RX   0x00000079      /* FIXME: correct value?  */
+#define EF_RX_CPU_MASK 0x0000007F      /* specific cpu bits.  */
+#define EF_RX_ALL_FLAGS        (EF_RX_CPU_MASK)
+
+/* Values for the e_flags field in the ELF header.  */
+#define E_FLAG_RX_64BIT_DOUBLES                (1 << 0)
+#define E_FLAG_RX_DSP                  (1 << 1) /* Defined in the RX CPU Object file specification, but not explained.  */
+
+/* These define the addend field of R_RX_RH_RELAX relocations.  */
+#define        RX_RELAXA_IMM6  0x00000010      /* Imm8/16/24/32 at bit offset 6.  */
+#define        RX_RELAXA_IMM12 0x00000020      /* Imm8/16/24/32 at bit offset 12.  */
+#define        RX_RELAXA_DSP4  0x00000040      /* Dsp0/8/16 at bit offset 4.  */
+#define        RX_RELAXA_DSP6  0x00000080      /* Dsp0/8/16 at bit offset 6.  */
+#define        RX_RELAXA_DSP14 0x00000100      /* Dsp0/8/16 at bit offset 14.  */
+#define        RX_RELAXA_BRA   0x00000200      /* Any type of branch (must be decoded).  */
+#define RX_RELAXA_RNUM 0x0000000f      /* Number of associated relocations.  */
+/* These mark the place where alignment is requested, and the place where the filler bytes end.  */
+#define        RX_RELAXA_ALIGN 0x10000000      /* Start alignment; the remaining bits are the alignment value.  */
+#define        RX_RELAXA_ELIGN 0x20000000      /* End alignment; the remaining bits are the alignment value.  */
+#define        RX_RELAXA_ANUM  0x00ffffff      /* Alignment amount, in bytes (i.e. .balign).  */
+
+#endif /* _ELF_RX_H */

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 476fdcf..44d1432 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,23 @@
+2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
+
+       * ppc.h (PPC_OPCODE_476): Define.
+
+2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
+
+       * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
+
+2009-09-29  DJ Delorie  <dj@redhat.com>
+
+       * rx.h: New file.
+
+2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
+
+       * ppc.h (ppc_cpu_t): Typedef to uint64_t.
+
+2009-09-21  Ben Elliston  <bje@au.ibm.com>
+
+       * ppc.h (PPC_OPCODE_PPCA2): New.
+
 2009-09-05  Martin Thuresson  <martin@mtme.org>
 
        * ia64.h (struct ia64_operand): Renamed member class to op_class.

diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index dc9a7ba..1dc2f1d 100644 (file)
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -22,7 +22,9 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US
 #ifndef PPC_H
 #define PPC_H
 
-typedef unsigned long ppc_cpu_t;
+#include "bfd_stdint.h"
+
+typedef uint64_t ppc_cpu_t;
 
 /* The opcode table is an array of struct powerpc_opcode.  */
 
@@ -165,6 +167,12 @@ extern const int powerpc_num_opcodes;
 /* Opcode is supported by Vector-Scalar (VSX) Unit */
 #define PPC_OPCODE_VSX          0x80000000
 
+/* Opcode is supported by A2.  */
+#define PPC_OPCODE_A2          0x100000000ULL
+
+/* Opcode is supported by PowerPC 476 processor.  */
+#define PPC_OPCODE_476          0x200000000ULL
+
 /* A macro to extract the major opcode from an instruction.  */
 #define PPC_OP(i) (((i) >> 26) & 0x3f)
 \f

diff --git a/include/opcode/rx.h b/include/opcode/rx.h
new file mode 100644 (file)
index 0000000..7081ccc
--- /dev/null
+++ b/include/opcode/rx.h
@@ -0,0 +1,218 @@
+/* Opcode decoder for the Renesas RX
+   Copyright 2008, 2009
+   Free Software Foundation, Inc.
+   Written by DJ Delorie <dj@redhat.com>
+
+   This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+/* The RX decoder in libopcodes is used by the simulator, gdb's
+   analyzer, and the disassembler.  Given an opcode data source,
+   it decodes the next opcode into the following structures.  */
+
+typedef enum
+{
+  RX_AnySize = 0,
+  RX_Byte, /* undefined extension */
+  RX_UByte,
+  RX_SByte,
+  RX_Word, /* undefined extension */
+  RX_UWord,
+  RX_SWord,
+  RX_3Byte,
+  RX_Long,
+} RX_Size;
+
+typedef enum
+{
+  RX_Operand_None,
+  RX_Operand_Immediate,        /* #addend */
+  RX_Operand_Register, /* Rn */
+  RX_Operand_Indirect, /* [Rn + addend] */
+  RX_Operand_Postinc,  /* [Rn+] */
+  RX_Operand_Predec,   /* [-Rn] */
+  RX_Operand_Condition,        /* eq, gtu, etc */
+  RX_Operand_Flag,     /* [UIOSZC] */
+} RX_Operand_Type;
+
+typedef enum
+{
+  RXO_unknown,
+  RXO_mov,     /* d = s (signed) */
+  RXO_movbi,   /* d = [s,s2] (signed) */
+  RXO_movbir,  /* [s,s2] = d (signed) */
+  RXO_pushm,   /* s..s2 */
+  RXO_popm,    /* s..s2 */
+  RXO_pusha,   /* &s */
+  RXO_xchg,    /* s <-> d */
+  RXO_stcc,    /* d = s if cond(s2) */
+  RXO_rtsd,    /* rtsd, 1=imm, 2-0 = reg if reg type */
+
+  /* These are all either d OP= s or, if s2 is set, d = s OP s2.  Note
+     that d may be "None".  */
+  RXO_and,
+  RXO_or,
+  RXO_xor,
+  RXO_add,
+  RXO_sub,
+  RXO_mul,
+  RXO_div,
+  RXO_divu,
+  RXO_shll,
+  RXO_shar,
+  RXO_shlr,
+
+  RXO_adc,     /* d = d + s + carry */
+  RXO_sbb,     /* d = d - s - ~carry */
+  RXO_abs,     /* d = |s| */
+  RXO_max,     /* d = max(d,s) */
+  RXO_min,     /* d = min(d,s) */
+  RXO_emul,    /* d:64 = d:32 * s */
+  RXO_emulu,   /* d:64 = d:32 * s (unsigned) */
+  RXO_ediv,    /* d:64 / s; d = quot, d+1 = rem */
+  RXO_edivu,   /* d:64 / s; d = quot, d+1 = rem */
+
+  RXO_rolc,    /* d <<= 1 through carry */
+  RXO_rorc,    /* d >>= 1 through carry*/
+  RXO_rotl,    /* d <<= #s without carry */
+  RXO_rotr,    /* d >>= #s without carry*/
+  RXO_revw,    /* d = revw(s) */
+  RXO_revl,    /* d = revl(s) */
+  RXO_branch,  /* pc = d if cond(s) */
+  RXO_branchrel,/* pc += d if cond(s) */
+  RXO_jsr,     /* pc = d */
+  RXO_jsrrel,  /* pc += d */
+  RXO_rts,
+  RXO_nop,
+
+  RXO_scmpu,
+  RXO_smovu,
+  RXO_smovb,
+  RXO_suntil,
+  RXO_swhile,
+  RXO_smovf,
+  RXO_sstr,
+
+  RXO_rmpa,
+  RXO_mulhi,
+  RXO_mullo,
+  RXO_machi,
+  RXO_maclo,
+  RXO_mvtachi,
+  RXO_mvtaclo,
+  RXO_mvfachi,
+  RXO_mvfacmi,
+  RXO_mvfaclo,
+  RXO_racw,
+
+  RXO_sat,     /* sat(d) */
+  RXO_satr,
+
+  RXO_fadd,    /* d op= s */
+  RXO_fcmp,
+  RXO_fsub,
+  RXO_ftoi,
+  RXO_fmul,
+  RXO_fdiv,
+  RXO_round,
+  RXO_itof,
+
+  RXO_bset,    /* d |= (1<<s) */
+  RXO_bclr,    /* d &= ~(1<<s) */
+  RXO_btst,    /* s & (1<<s2) */
+  RXO_bnot,    /* d ^= (1<<s) */
+  RXO_bmcc,    /* d<s> = cond(s2) */
+
+  RXO_clrpsw,  /* flag index in d */
+  RXO_setpsw,  /* flag index in d */
+
+  RXO_mvtcp,   /* cop# in s2, cop[d] = s */
+  RXO_mvfcp,   /* cop# in s2, d = cop[s] */
+  RXO_opecp,   /* cop# in s2, do cop[s] */
+
+  RXO_rtfi,
+  RXO_rte,
+  RXO_rtd,     /* undocumented */
+  RXO_brk,
+  RXO_dbt,     /* undocumented */
+  RXO_int,     /* vector id in s */
+  RXO_stop,
+  RXO_wait,
+
+  RXO_sccnd,   /* d = cond(s) ? 1 : 0 */
+} RX_Opcode_ID;
+
+/* Condition bitpatterns, as registers.  */
+#define RXC_eq         0
+#define RXC_z          0
+#define RXC_ne         1
+#define RXC_nz         1
+#define RXC_c          2
+#define RXC_nc         3
+#define RXC_gtu                4
+#define RXC_leu                5
+#define RXC_pz         6
+#define RXC_n          7
+#define RXC_ge         8
+#define RXC_lt         9
+#define RXC_gt         10
+#define RXC_le         11
+#define RXC_o          12
+#define RXC_no         13
+#define RXC_always     14
+#define RXC_never      15
+
+typedef struct
+{
+  RX_Operand_Type  type;
+  int              reg;
+  int              addend;
+  RX_Size          size;
+} RX_Opcode_Operand;
+
+typedef struct
+{
+  RX_Opcode_ID      id;
+  int               n_bytes;
+  int               prefix;
+  char *            syntax;
+  RX_Size           size;
+  /* By convention, these are destination, source1, source2.  */
+  RX_Opcode_Operand op[3];
+
+  /* The logic here is:
+     newflags = (oldflags & ~(int)flags_0) | flags_1 | (op_flags & flags_s)
+     Only the O, S, Z, and C flags are affected.  */
+  char flags_0; /* This also clears out flags-to-be-set.  */
+  char flags_1;
+  char flags_s;
+} RX_Opcode_Decoded;
+
+/* Within the syntax, %c-style format specifiers are as follows:
+
+   %% = '%' character
+   %0 = operand[0] (destination)
+   %1 = operand[1] (source)
+   %2 = operand[2] (2nd source)
+   %s = operation size (b/w/l)
+   %SN = operand size [N] (N=0,1,2)
+   %aN = op[N] as an address (N=0,1,2)
+
+   Register numbers 0..15 are general registers.  16..31 are control
+   registers.  32..47 are condition codes.  */
+
+int rx_decode_opcode (unsigned long, RX_Opcode_Decoded *, int (*)(void *), void *);

diff --git a/libiberty/ChangeLog b/libiberty/ChangeLog
index c86cbc6..1b3a44c 100644 (file)
--- a/libiberty/ChangeLog
+++ b/libiberty/ChangeLog
@@ -1,3 +1,27 @@
+2009-09-30  Martin Thuresson  <martint@google.com>
+
+       * regex.c (byte_re_match_2_internal): Split declaration and
+       assignment to avoid -Wc++-compat warning due to goto.
+
+2009-09-29  Jason Merrill  <jason@redhat.com>
+
+       * Makefile.in: Enable demangle target.
+       * cp-demangle.c (d_lambda, d_unnamed_type, d_make_default_arg): New.
+       (d_name, d_prefix, d_unqualified_name, d_local_name): Handle lambdas.
+       (d_parmlist): Factor out from d_bare_function_type.
+       (d_compact_number): Factor out from d_template_param and d_expression.
+       (d_append_num): Factor out from d_print_comp.
+       (d_print_comp, d_print_mod_list): Handle lambdas.
+       * testsuite/demangle-expected: Add lambda tests.
+
+2009-09-23  Matthew Gingell  <gingell@adacore.com>
+
+       * cplus-dem.c (ada_demangle): Ensure demangled is freed.
+
+2009-09-22  Ozkan Sezer  <sezeroz@gmail.com>
+
+       * choose-temp.c: Include unistd.h for mingw targets.
+
 2009-09-16  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
 
        * hashtab.c [HAVE_INTTYPES_H]: Include <inttypes.h>.

diff --git a/libiberty/Makefile.in b/libiberty/Makefile.in
index 5d2adff..ba24c6d 100644 (file)
--- a/libiberty/Makefile.in
+++ b/libiberty/Makefile.in
@@ -371,10 +371,12 @@ TAGS: $(CFILES)
        etags `for i in $(CFILES); do echo $(srcdir)/$$i ; done`
 
 # The standalone demangler (c++filt) has been moved to binutils.
-demangle:
+# But make this target work anyway for demangler hacking.
+demangle: $(ALL) $(srcdir)/cp-demangle.c
        @echo "The standalone demangler, now named c++filt, is now"
        @echo "a part of binutils."
-       @false
+       $(CC) @DEFS@ $(CFLAGS) $(CPPFLAGS) -I. -I$(INCDIR) $(HDEFINES) \
+         $(srcdir)/cp-demangle.c -DSTANDALONE_DEMANGLER $(TARGETLIB) -o $@
 
 ls:
        @echo Makefile $(CFILES)

diff --git a/libiberty/choose-temp.c b/libiberty/choose-temp.c
index b1c2e5b..0a454cf 100644 (file)
--- a/libiberty/choose-temp.c
+++ b/libiberty/choose-temp.c
@@ -22,6 +22,10 @@ Boston, MA 02110-1301, USA.  */
 #endif
 
 #include <stdio.h>     /* May get P_tmpdir.  */
+#include <sys/types.h>
+#ifdef HAVE_UNISTD_H
+#include <unistd.h>
+#endif
 #ifdef HAVE_STDLIB_H
 #include <stdlib.h>
 #endif

diff --git a/libiberty/cp-demangle.c b/libiberty/cp-demangle.c
index 2c7296f..43cf34a 100644 (file)
--- a/libiberty/cp-demangle.c
+++ b/libiberty/cp-demangle.c
@@ -408,6 +408,10 @@ static struct demangle_component *d_local_name (struct d_info *);
 
 static int d_discriminator (struct d_info *);
 
+static struct demangle_component *d_lambda (struct d_info *);
+
+static struct demangle_component *d_unnamed_type (struct d_info *);
+
 static int
 d_add_substitution (struct d_info *, struct demangle_component *);
 
@@ -922,6 +926,20 @@ d_make_extended_operator (struct d_info *di, int args,
   return p;
 }
 
+static struct demangle_component *
+d_make_default_arg (struct d_info *di, int num,
+                   struct demangle_component *sub)
+{
+  struct demangle_component *p = d_make_empty (di);
+  if (p)
+    {
+      p->type = DEMANGLE_COMPONENT_DEFAULT_ARG;
+      p->u.s_unary_num.num = num;
+      p->u.s_unary_num.sub = sub;
+    }
+  return p;
+}
+
 /* Add a new constructor component.  */
 
 static struct demangle_component *
@@ -1153,8 +1171,9 @@ d_name (struct d_info *di)
       return d_local_name (di);
 
     case 'L':
+    case 'U':
       return d_unqualified_name (di);
-       
+
     case 'S':
       {
        int subst;
@@ -1276,6 +1295,7 @@ d_prefix (struct d_info *di)
          || IS_LOWER (peek)
          || peek == 'C'
          || peek == 'D'
+         || peek == 'U'
          || peek == 'L')
        dc = d_unqualified_name (di);
       else if (peek == 'S')
@@ -1291,6 +1311,16 @@ d_prefix (struct d_info *di)
        dc = d_template_param (di);
       else if (peek == 'E')
        return ret;
+      else if (peek == 'M')
+       {
+         /* Initializer scope for a lambda.  We don't need to represent
+            this; the normal code will just treat the variable as a type
+            scope, which gives appropriate output.  */
+         if (ret == NULL)
+           return NULL;
+         d_advance (di, 1);
+         continue;
+       }
       else
        return NULL;
 
@@ -1347,6 +1377,18 @@ d_unqualified_name (struct d_info *di)
        return NULL;
       return ret;
     }
+  else if (peek == 'U')
+    {
+      switch (d_peek_next_char (di))
+       {
+       case 'l':
+         return d_lambda (di);
+       case 't':
+         return d_unnamed_type (di);
+       default:
+         return NULL;
+       }
+    }
   else
     return NULL;
 }
@@ -2242,50 +2284,30 @@ d_function_type (struct d_info *di)
   return ret;
 }
 
-/* <bare-function-type> ::= [J]<type>+  */
+/* <type>+ */
 
 static struct demangle_component *
-d_bare_function_type (struct d_info *di, int has_return_type)
+d_parmlist (struct d_info *di)
 {
-  struct demangle_component *return_type;
   struct demangle_component *tl;
   struct demangle_component **ptl;
-  char peek;
 
-  /* Detect special qualifier indicating that the first argument
-     is the return type.  */
-  peek = d_peek_char (di);
-  if (peek == 'J')
-    {
-      d_advance (di, 1);
-      has_return_type = 1;
-    }
-
-  return_type = NULL;
   tl = NULL;
   ptl = &tl;
   while (1)
     {
       struct demangle_component *type;
 
-      peek = d_peek_char (di);
+      char peek = d_peek_char (di);
       if (peek == '\0' || peek == 'E')
        break;
       type = cplus_demangle_type (di);
       if (type == NULL)
        return NULL;
-      if (has_return_type)
-       {
-         return_type = type;
-         has_return_type = 0;
-       }
-      else
-       {
-         *ptl = d_make_comp (di, DEMANGLE_COMPONENT_ARGLIST, type, NULL);
-         if (*ptl == NULL)
-           return NULL;
-         ptl = &d_right (*ptl);
-       }
+      *ptl = d_make_comp (di, DEMANGLE_COMPONENT_ARGLIST, type, NULL);
+      if (*ptl == NULL)
+       return NULL;
+      ptl = &d_right (*ptl);
     }
 
   /* There should be at least one parameter type besides the optional
@@ -2300,10 +2322,45 @@ d_bare_function_type (struct d_info *di, int has_return_type)
       && d_left (tl)->u.s_builtin.type->print == D_PRINT_VOID)
     {
       di->expansion -= d_left (tl)->u.s_builtin.type->len;
-      tl = NULL;
+      d_left (tl) = NULL;
     }
 
-  return d_make_comp (di, DEMANGLE_COMPONENT_FUNCTION_TYPE, return_type, tl);
+  return tl;
+}
+
+/* <bare-function-type> ::= [J]<type>+  */
+
+static struct demangle_component *
+d_bare_function_type (struct d_info *di, int has_return_type)
+{
+  struct demangle_component *return_type;
+  struct demangle_component *tl;
+  char peek;
+
+  /* Detect special qualifier indicating that the first argument
+     is the return type.  */
+  peek = d_peek_char (di);
+  if (peek == 'J')
+    {
+      d_advance (di, 1);
+      has_return_type = 1;
+    }
+
+  if (has_return_type)
+    {
+      return_type = cplus_demangle_type (di);
+      if (return_type == NULL)
+       return NULL;
+    }
+  else
+    return_type = NULL;
+
+  tl = d_parmlist (di);
+  if (tl == NULL)
+    return NULL;
+
+  return d_make_comp (di, DEMANGLE_COMPONENT_FUNCTION_TYPE,
+                     return_type, tl);
 }
 
 /* <class-enum-type> ::= <name>  */
@@ -2405,6 +2462,24 @@ d_pointer_to_member_type (struct d_info *di)
   return d_make_comp (di, DEMANGLE_COMPONENT_PTRMEM_TYPE, cl, mem);
 }
 
+/* <non-negative number> _ */
+
+static long
+d_compact_number (struct d_info *di)
+{
+  long num;
+  if (d_peek_char (di) == '_')
+    num = 0;
+  else if (d_peek_char (di) == 'n')
+    return -1;
+  else
+    num = d_number (di) + 1;
+
+  if (! d_check_char (di, '_'))
+    return -1;
+  return num;
+}
+
 /* <template-param> ::= T_
                     ::= T <(parameter-2 non-negative) number> _
 */
@@ -2417,17 +2492,8 @@ d_template_param (struct d_info *di)
   if (! d_check_char (di, 'T'))
     return NULL;
 
-  if (d_peek_char (di) == '_')
-    param = 0;
-  else
-    {
-      param = d_number (di);
-      if (param < 0)
-       return NULL;
-      param += 1;
-    }
-
-  if (! d_check_char (di, '_'))
+  param = d_compact_number (di);
+  if (param < 0)
     return NULL;
 
   ++di->did_subs;
@@ -2599,17 +2665,8 @@ d_expression (struct d_info *di)
       /* Function parameter used in a late-specified return type.  */
       int index;
       d_advance (di, 2);
-      if (d_peek_char (di) == '_')
-       index = 1;
-      else
-       {
-         index = d_number (di);
-         if (index < 0)
-           return NULL;
-         index += 2;
-       }
-
-      if (! d_check_char (di, '_'))
+      index = d_compact_number (di);
+      if (index < 0)
        return NULL;
 
       return d_make_function_param (di, index);
@@ -2802,10 +2859,31 @@ d_local_name (struct d_info *di)
   else
     {
       struct demangle_component *name;
+      int num = -1;
+
+      if (d_peek_char (di) == 'd')
+       {
+         /* Default argument scope: d <number> _.  */
+         d_advance (di, 1);
+         num = d_compact_number (di);
+         if (num < 0)
+           return NULL;
+       }
 
       name = d_name (di);
-      if (! d_discriminator (di))
-       return NULL;
+      if (name)
+       switch (name->type)
+         {
+           /* Lambdas and unnamed types have internal discriminators.  */
+         case DEMANGLE_COMPONENT_LAMBDA:
+         case DEMANGLE_COMPONENT_UNNAMED_TYPE:
+           break;
+         default:
+           if (! d_discriminator (di))
+             return NULL;
+         }
+      if (num >= 0)
+       name = d_make_default_arg (di, num, name);
       return d_make_comp (di, DEMANGLE_COMPONENT_LOCAL_NAME, function, name);
     }
 }
@@ -2829,6 +2907,75 @@ d_discriminator (struct d_info *di)
   return 1;
 }
 
+/* <closure-type-name> ::= Ul <lambda-sig> E [ <nonnegative number> ] _ */
+
+static struct demangle_component *
+d_lambda (struct d_info *di)
+{
+  struct demangle_component *tl;
+  struct demangle_component *ret;
+  int num;
+
+  if (! d_check_char (di, 'U'))
+    return NULL;
+  if (! d_check_char (di, 'l'))
+    return NULL;
+
+  tl = d_parmlist (di);
+  if (tl == NULL)
+    return NULL;
+
+  if (! d_check_char (di, 'E'))
+    return NULL;
+
+  num = d_compact_number (di);
+  if (num < 0)
+    return NULL;
+
+  ret = d_make_empty (di);
+  if (ret)
+    {
+      ret->type = DEMANGLE_COMPONENT_LAMBDA;
+      ret->u.s_unary_num.sub = tl;
+      ret->u.s_unary_num.num = num;
+    }
+
+  if (! d_add_substitution (di, ret))
+    return NULL;
+
+  return ret;
+}
+
+/* <unnamed-type-name> ::= Ut [ <nonnegative number> ] _ */
+
+static struct demangle_component *
+d_unnamed_type (struct d_info *di)
+{
+  struct demangle_component *ret;
+  long num;
+
+  if (! d_check_char (di, 'U'))
+    return NULL;
+  if (! d_check_char (di, 't'))
+    return NULL;
+
+  num = d_compact_number (di);
+  if (num < 0)
+    return NULL;
+
+  ret = d_make_empty (di);
+  if (ret)
+    {
+      ret->type = DEMANGLE_COMPONENT_UNNAMED_TYPE;
+      ret->u.s_number.number = num;
+    }
+
+  if (! d_add_substitution (di, ret))
+    return NULL;
+
+  return ret;
+}
+
 /* Add a new substitution.  */
 
 static int
@@ -3122,6 +3269,14 @@ d_append_string (struct d_print_info *dpi, const char *s)
   d_append_buffer (dpi, s, strlen (s));
 }
 
+static inline void
+d_append_num (struct d_print_info *dpi, long l)
+{
+  char buf[25];
+  sprintf (buf,"%ld", l);
+  d_append_string (dpi, buf);
+}
+
 static inline char
 d_last_char (struct d_print_info *dpi)
 {
@@ -3398,6 +3553,8 @@ d_print_comp (struct d_print_info *dpi,
            struct demangle_component *local_name;
 
            local_name = d_right (typed_name);
+           if (local_name->type == DEMANGLE_COMPONENT_DEFAULT_ARG)
+             local_name = local_name->u.s_unary_num.sub;
            while (local_name->type == DEMANGLE_COMPONENT_RESTRICT_THIS
                   || local_name->type == DEMANGLE_COMPONENT_VOLATILE_THIS
                   || local_name->type == DEMANGLE_COMPONENT_CONST_THIS)
@@ -4048,13 +4205,10 @@ d_print_comp (struct d_print_info *dpi,
       return;
 
     case DEMANGLE_COMPONENT_FUNCTION_PARAM:
-      {
-       char buf[25];
-       d_append_string (dpi, "parm#");
-       sprintf(buf,"%ld", dc->u.s_number.number);
-       d_append_string (dpi, buf);
-       return;
-      }
+      d_append_string (dpi, "{parm#");
+      d_append_num (dpi, dc->u.s_number.number + 1);
+      d_append_char (dpi, '}');
+      return;
 
     case DEMANGLE_COMPONENT_GLOBAL_CONSTRUCTORS:
       d_append_string (dpi, "global constructors keyed to ");
@@ -4066,6 +4220,20 @@ d_print_comp (struct d_print_info *dpi,
       d_print_comp (dpi, dc->u.s_binary.left);
       return;
 
+    case DEMANGLE_COMPONENT_LAMBDA:
+      d_append_string (dpi, "{lambda(");
+      d_print_comp (dpi, dc->u.s_unary_num.sub);
+      d_append_string (dpi, ")#");
+      d_append_num (dpi, dc->u.s_unary_num.num + 1);
+      d_append_char (dpi, '}');
+      return;
+
+    case DEMANGLE_COMPONENT_UNNAMED_TYPE:
+      d_append_string (dpi, "{unnamed type#");
+      d_append_num (dpi, dc->u.s_number.number + 1);
+      d_append_char (dpi, '}');
+      return;
+
     default:
       d_print_error (dpi);
       return;
@@ -4184,6 +4352,15 @@ d_print_mod_list (struct d_print_info *dpi,
        d_append_char (dpi, '.');
 
       dc = d_right (mods->mod);
+
+      if (dc->type == DEMANGLE_COMPONENT_DEFAULT_ARG)
+       {
+         d_append_string (dpi, "{default arg#");
+         d_append_num (dpi, dc->u.s_unary_num.num + 1);
+         d_append_string (dpi, "}::");
+         dc = dc->u.s_unary_num.sub;
+       }
+
       while (dc->type == DEMANGLE_COMPONENT_RESTRICT_THIS
             || dc->type == DEMANGLE_COMPONENT_VOLATILE_THIS
             || dc->type == DEMANGLE_COMPONENT_CONST_THIS)

diff --git a/libiberty/cplus-dem.c b/libiberty/cplus-dem.c
index 4167467..6628514 100644 (file)
--- a/libiberty/cplus-dem.c
+++ b/libiberty/cplus-dem.c
@@ -984,7 +984,10 @@ ada_demangle (const char *mangled, int option ATTRIBUTE_UNUSED)
       goto Suppress;
 
   if (! changed)
-    return NULL;
+    {
+      free (demangled);
+      return NULL;
+    }
   else
     return demangled;
   

diff --git a/libiberty/regex.c b/libiberty/regex.c
index fa1df19..ad49684 100644 (file)
--- a/libiberty/regex.c
+++ b/libiberty/regex.c
@@ -5910,11 +5910,14 @@ byte_re_match_2_internal (struct re_pattern_buffer *bufp,
            {
              /* 1 if this match ends in the same string (string1 or string2)
                 as the best previous match.  */
-             boolean same_str_p = (FIRST_STRING_P (match_end)
-                                   == MATCHING_IN_FIRST_STRING);
+             boolean same_str_p;
+
              /* 1 if this match is the best seen so far.  */
              boolean best_match_p;
 
+              same_str_p = (FIRST_STRING_P (match_end)
+                            == MATCHING_IN_FIRST_STRING);
+
              /* AIX compiler got confused when this was combined
                 with the previous declaration.  */
              if (same_str_p)

diff --git a/libiberty/testsuite/demangle-expected b/libiberty/testsuite/demangle-expected
index 0c45118..6798154 100644 (file)
--- a/libiberty/testsuite/demangle-expected
+++ b/libiberty/testsuite/demangle-expected
@@ -3885,11 +3885,11 @@ java resource java/util/iso4217.properties
 # decltype/param placeholder test
 --format=gnu-v3
 _Z3addIidEDTplfp_fp0_ET_T0_
-decltype (parm#1+parm#2) add<int, double>(int, double)
+decltype ({parm#1}+{parm#2}) add<int, double>(int, double)
 # decltype/fn call test
 --format=gnu-v3
 _Z4add3IidEDTclL_Z1gEfp_fp0_EET_T0_
-decltype (g(parm#1, parm#2)) add3<int, double>(int, double)
+decltype (g({parm#1}, {parm#2})) add3<int, double>(int, double)
 # new (2008) built in types test
 --format=gnu-v3
 _Z1fDfDdDeDhDsDi
@@ -3901,12 +3901,28 @@ void f<int*, float*, double*>(int*, float*, double*)
 # '.' test
 --format=gnu-v3
 _Z1hI1AIiEdEDTcldtfp_1gIT0_EEET_S2_
-decltype ((parm#1.(g<double>))()) h<A<int>, double>(A<int>, double)
+decltype (({parm#1}.(g<double>))()) h<A<int>, double>(A<int>, double)
 # test for typed function in decltype
 --format=gnu-v3
 _ZN1AIiE1jIiEEDTplfp_clL_Z1xvEEET_
-decltype (parm#1+((x())())) A<int>::j<int>(int)
+decltype ({parm#1}+((x())())) A<int>::j<int>(int)
 # test for expansion of function parameter pack
 --format=gnu-v3
 _Z1gIIidEEDTclL_Z1fEspplfp_Li1EEEDpT_
-decltype (f((parm#1+(1))...)) g<int, double>(int, double)
+decltype (f(({parm#1}+(1))...)) g<int, double>(int, double)
+# lambda tests
+--format=gnu-v3
+_ZZ1giENKUlvE_clEv
+g(int)::{lambda()#1}::operator()() const
+--format=gnu-v3
+_Z4algoIZ1giEUlvE0_EiT_
+int algo<g(int)::{lambda()#2}>(g(int)::{lambda()#2})
+--format=gnu-v3
+_ZZN1S1fEiiEd0_NKUlvE0_clEv
+S::f(int, int)::{default arg#2}::{lambda()#2}::operator()() const
+--format=gnu-v3
+_ZNK1SIiE1xMUlvE1_clEv
+S<int>::x::{lambda()#3}::operator()() const
+--format=gnu-v3
+_Z1fN1SUt_E
+f(S::{unnamed type#1})

diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index b5eb8a5..ba67454 100644 (file)
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -1,5 +1,5 @@
 /* Instruction printing code for the ARC.
-   Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2005, 2007
+   Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2005, 2007, 2009
    Free Software Foundation, Inc.
    Contributed by Doug Evans (dje@cygnus.com).
 
@@ -1201,7 +1201,7 @@ decodeInstr (bfd_vma            address, /* Address of this instruction.  */
   s.instName = _instName;
 
   /* Disassemble.  */
-  bytes = dsmOneArcInst (address, (void *)& s);
+  bytes = dsmOneArcInst (address, & s);
 
   /* Display the disassembly instruction.  */
   (*func) (stream, "%08lx ", s.words[0]);
@@ -1228,6 +1228,6 @@ disassembler_ftype
 arc_get_disassembler (void *ptr)
 {
   if (ptr)
-    build_ARC_extmap (ptr);
+    build_ARC_extmap ((struct bfd *) ptr);
   return decodeInstr;
 }

diff --git a/opcodes/arc-ext.c b/opcodes/arc-ext.c
index 1e6c1f8..376cd03 100644 (file)
--- a/opcodes/arc-ext.c
+++ b/opcodes/arc-ext.c
@@ -1,5 +1,5 @@
 /* ARC target-dependent stuff. Extension structure access functions
-   Copyright 1995, 1997, 2000, 2001, 2004, 2005, 2007
+   Copyright 1995, 1997, 2000, 2001, 2004, 2005, 2007, 2009
    Free Software Foundation, Inc.
 
    This file is part of libopcodes.
@@ -148,8 +148,8 @@ cleanup_ext_map(void)
 int
 arcExtMap_add(void *base, unsigned long length)
 {
-  unsigned char *block = base;
-  unsigned char *p = block;
+  unsigned char *block = (unsigned char *) base;
+  unsigned char *p = (unsigned char *) block;
 
   /* Clean up and reset everything if needed.  */
   cleanup_ext_map();

diff --git a/opcodes/configure b/opcodes/configure
index 52da1c4..83b973c 100755 (executable)
--- a/opcodes/configure
+++ b/opcodes/configure
@@ -12332,6 +12332,7 @@ if test x${all_targets} = xfalse ; then
        bfd_pyramid_arch)       ;;
        bfd_romp_arch)          ;;
        bfd_rs6000_arch)        ta="$ta ppc-dis.lo ppc-opc.lo" ;;
+       bfd_rx_arch)            ta="$ta rx-dis.lo rx-decode.lo";;
        bfd_s390_arch)          ta="$ta s390-dis.lo s390-opc.lo" ;;
        bfd_score_arch)         ta="$ta score-dis.lo score7-dis.lo" ;;
        bfd_sh_arch)

diff --git a/opcodes/configure.in b/opcodes/configure.in
index 75414d7..dd9dabf 100644 (file)
--- a/opcodes/configure.in
+++ b/opcodes/configure.in
@@ -271,6 +271,7 @@ if test x${all_targets} = xfalse ; then
        bfd_pyramid_arch)       ;;
        bfd_romp_arch)          ;;
        bfd_rs6000_arch)        ta="$ta ppc-dis.lo ppc-opc.lo" ;;
+       bfd_rx_arch)            ta="$ta rx-dis.lo rx-decode.lo";;
        bfd_s390_arch)          ta="$ta s390-dis.lo s390-opc.lo" ;;
        bfd_score_arch)         ta="$ta score-dis.lo score7-dis.lo" ;;
        bfd_sh_arch)

diff --git a/opcodes/crx-dis.c b/opcodes/crx-dis.c
index 6675720..c752457 100644 (file)
--- a/opcodes/crx-dis.c
+++ b/opcodes/crx-dis.c
@@ -355,7 +355,7 @@ match_opcode (void)
   unsigned long mask;
 
   /* The instruction 'constant' opcode doewsn't exceed 32 bits.  */
-  unsigned long doubleWord = words[1] + (words[0] << 16);
+  unsigned long doubleWord = (words[1] + (words[0] << 16)) & 0xffffffff;
 
   /* Start searching from end of instruction table.  */
   instruction = &crx_instruction[NUMOPCODES - 2];

diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index 04d5d0c..267fcf5 100644 (file)
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -71,6 +71,7 @@
 #define ARCH_pj
 #define ARCH_powerpc
 #define ARCH_rs6000
+#define ARCH_rx
 #define ARCH_s390
 #define ARCH_score
 #define ARCH_sh
@@ -352,6 +353,11 @@ disassembler (abfd)
        disassemble = print_insn_rs6000;
       break;
 #endif
+#ifdef ARCH_rx
+    case bfd_arch_rx:
+      disassemble = print_insn_rx;
+      break;
+#endif
 #ifdef ARCH_s390
     case bfd_arch_s390:
       disassemble = print_insn_s390;

diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index fb1c78e..337f93c 100644 (file)
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -347,7 +347,6 @@ static bitfield opcode_modifiers[] =
   BITFIELD (Rex64),
   BITFIELD (Ugh),
   BITFIELD (Vex),
-  BITFIELD (Vex256),
   BITFIELD (VexNDS),
   BITFIELD (VexNDD),
   BITFIELD (VexW0),
@@ -540,6 +539,29 @@ set_bitfield (const char *f, bitfield *array, int value,
        return;
       }
 
+  if (value)
+    {
+      const char *v = strchr (f, '=');
+
+      if (v)
+       {
+         size_t n = v - f;
+         char *end;
+
+         for (i = 0; i < size; i++)
+           if (strncasecmp (array[i].name, f, n) == 0)
+             {
+               value = strtol (v + 1, &end, 0);
+               if (*end == '\0')
+                 {
+                   array[i].value = value;
+                   return;
+                 }
+               break;
+             }
+       }
+    }
+
   if (lineno != -1)
     fail (_("%s: %d: Unknown bitfield: %s\n"), filename, lineno, f);
   else

diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 2dd8eed..df71da7 100644 (file)
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -257,14 +257,15 @@ typedef union i386_cpu_flags
 #define Rex64                  (NoRex64 + 1)
 /* deprecated fp insn, gets a warning */
 #define Ugh                    (Rex64 + 1)
-/* insn has VEX prefix. */
+/* insn has VEX prefix:
+       1: 128bit VEX prefix.
+       2: 256bit VEX prefix.
+ */
 #define Vex                    (Ugh + 1)
-/* insn has 256bit VEX prefix. */
-#define Vex256                 (Vex + 1)
 /* insn has VEX NDS. Register-only source is encoded in Vex prefix.
    We use VexNDS on insns with VEX DDS since the register-only source
    is the second source register.  */
-#define VexNDS                 (Vex256 + 1)
+#define VexNDS                 (Vex + 1)
 /* insn has VEX NDD. Register destination is encoded in Vex
    prefix. */
 #define VexNDD                 (VexNDS + 1)
@@ -336,8 +337,7 @@ typedef struct i386_opcode_modifier
   unsigned int norex64:1;
   unsigned int rex64:1;
   unsigned int ugh:1;
-  unsigned int vex:1;
-  unsigned int vex256:1;
+  unsigned int vex:2;
   unsigned int vexnds:1;
   unsigned int vexndd:1;
   unsigned int vexw0:1;

diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 4cf07b6..fa35cba 100644 (file)
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -330,7 +330,7 @@ call, 1, 0xff, 0x3, 1, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q
 lcall, 2, 0x9a, None, 1, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
 lcall, 1, 0xff, 0x3, 1, 0, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute }
 
-jmp, 1, 0xeb, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
+jmp, 1, 0xeb, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
 jmp, 1, 0xff, 0x4, 1, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|JumpAbsolute }
 jmp, 1, 0xff, 0x4, 1, Cpu64, Modrm|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute }
 // Intel Syntax.
@@ -356,57 +356,57 @@ leave, 0, 0xc9, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_
 leave, 0, 0xc9, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { 0 }
 
 // Conditional jumps.
-jo, 1, 0x70, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
-jno, 1, 0x71, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
-jb, 1, 0x72, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
-jc, 1, 0x72, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
-jnae, 1, 0x72, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
-jnb, 1, 0x73, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
-jnc, 1, 0x73, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
-jae, 1, 0x73, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
-je, 1, 0x74, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
-jz, 1, 0x74, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
-jne, 1, 0x75, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
-jnz, 1, 0x75, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
-jbe, 1, 0x76, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
-jna, 1, 0x76, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
-jnbe, 1, 0x77, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
-ja, 1, 0x77, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
-js, 1, 0x78, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
-jns, 1, 0x79, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
-jp, 1, 0x7a, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
-jpe, 1, 0x7a, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
-jnp, 1, 0x7b, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
-jpo, 1, 0x7b, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
-jl, 1, 0x7c, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
-jnge, 1, 0x7c, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
-jnl, 1, 0x7d, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
-jge, 1, 0x7d, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
-jle, 1, 0x7e, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
-jng, 1, 0x7e, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
-jnle, 1, 0x7f, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
-jg, 1, 0x7f, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
+jo, 1, 0x70, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
+jno, 1, 0x71, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
+jb, 1, 0x72, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
+jc, 1, 0x72, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
+jnae, 1, 0x72, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
+jnb, 1, 0x73, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
+jnc, 1, 0x73, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
+jae, 1, 0x73, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
+je, 1, 0x74, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
+jz, 1, 0x74, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
+jne, 1, 0x75, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
+jnz, 1, 0x75, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
+jbe, 1, 0x76, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
+jna, 1, 0x76, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
+jnbe, 1, 0x77, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
+ja, 1, 0x77, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
+js, 1, 0x78, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
+jns, 1, 0x79, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
+jp, 1, 0x7a, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
+jpe, 1, 0x7a, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
+jnp, 1, 0x7b, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
+jpo, 1, 0x7b, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
+jl, 1, 0x7c, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
+jnge, 1, 0x7c, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
+jnl, 1, 0x7d, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
+jge, 1, 0x7d, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
+jle, 1, 0x7e, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
+jng, 1, 0x7e, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
+jnle, 1, 0x7f, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
+jg, 1, 0x7f, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
 
 // jcxz vs. jecxz is chosen on the basis of the address size prefix.
 jcxz, 1, 0xe3, None, 1, CpuNo64, JumpByte|Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 }
 jecxz, 1, 0xe3, None, 1, CpuNo64, JumpByte|Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 }
-jecxz, 1, 0x67e3, None, 2, Cpu64, JumpByte|Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp32|Disp32S|Disp64 }
-jrcxz, 1, 0xe3, None, 1, Cpu64, JumpByte|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S|Disp64 }
+jecxz, 1, 0x67e3, None, 2, Cpu64, JumpByte|Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp32|Disp32S }
+jrcxz, 1, 0xe3, None, 1, Cpu64, JumpByte|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S }
 
 // The loop instructions also use the address size prefix to select
 // %cx rather than %ecx for the loop count, so the `w' form of these
 // instructions emit an address size prefix rather than a data size
 //  prefix.
 loop, 1, 0xe2, None, 1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 }
-loop, 1, 0xe2, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S|Disp64 }
+loop, 1, 0xe2, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S }
 loopz, 1, 0xe1, None, 1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 }
-loopz, 1, 0xe1, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S|Disp64 }
+loopz, 1, 0xe1, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S }
 loope, 1, 0xe1, None, 1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 }
-loope, 1, 0xe1, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S|Disp64 }
+loope, 1, 0xe1, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S }
 loopnz, 1, 0xe0, None, 1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 }
-loopnz, 1, 0xe0, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S|Disp64 }
+loopnz, 1, 0xe0, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S }
 loopne, 1, 0xe0, None, 1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 }
-loopne, 1, 0xe0, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S|Disp64 }
+loopne, 1, 0xe0, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S }
 
 // Set byte on flag instructions.
 seto, 1, 0xf90, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
@@ -1781,255 +1781,255 @@ pclmulhqhqdq, 2, 0x660f3a44, 0x11, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSu
 // AVX instructions.
 
 vaddpd, 3, 0x6658, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vaddpd, 3, 0x6658, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vaddpd, 3, 0x6658, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vaddps, 3, 0x58, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vaddps, 3, 0x58, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vaddps, 3, 0x58, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vaddsd, 3, 0xf258, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vaddss, 3, 0xf358, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vaddsubpd, 3, 0x66d0, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vaddsubpd, 3, 0x66d0, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vaddsubpd, 3, 0x66d0, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vaddsubps, 3, 0xf2d0, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vaddsubps, 3, 0xf2d0, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vaddsubps, 3, 0xf2d0, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vandnpd, 3, 0x6655, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vandnpd, 3, 0x6655, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vandnpd, 3, 0x6655, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vandnps, 3, 0x55, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vandnps, 3, 0x55, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vandnps, 3, 0x55, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vandpd, 3, 0x6654, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vandpd, 3, 0x6654, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vandpd, 3, 0x6654, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vandps, 3, 0x54, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vandps, 3, 0x54, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vandps, 3, 0x54, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vblendpd, 4, 0x660d, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vblendpd, 4, 0x660d, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vblendpd, 4, 0x660d, None, 1, CpuAVX, Modrm|Vex=2|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vblendps, 4, 0x660c, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vblendps, 4, 0x660c, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vblendps, 4, 0x660c, None, 1, CpuAVX, Modrm|Vex=2|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vblendvpd, 4, 0x664b, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vblendvpd, 4, 0x664b, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|Vex3Sources|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vblendvpd, 4, 0x664b, None, 1, CpuAVX, Modrm|Vex=2|Vex0F3A|Vex3Sources|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vblendvps, 4, 0x664a, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vblendvps, 4, 0x664a, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|Vex3Sources|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
-vbroadcastf128, 2, 0x661a, None, 1, CpuAVX, Modrm|Vex|Vex0F38|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegYMM }
-vbroadcastsd, 2, 0x6619, None, 1, CpuAVX, Modrm|Vex|Vex0F38|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegYMM }
+vblendvps, 4, 0x664a, None, 1, CpuAVX, Modrm|Vex=2|Vex0F3A|Vex3Sources|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vbroadcastf128, 2, 0x661a, None, 1, CpuAVX, Modrm|Vex=2|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegYMM }
+vbroadcastsd, 2, 0x6619, None, 1, CpuAVX, Modrm|Vex=2|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegYMM }
 vbroadcastss, 2, 0x6618, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM }
-vbroadcastss, 2, 0x6618, None, 1, CpuAVX, Modrm|Vex|Vex0F38|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegYMM }
+vbroadcastss, 2, 0x6618, None, 1, CpuAVX, Modrm|Vex=2|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegYMM }
 vcmpeq_ospd, 3, 0x66c2, 0x10, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpeq_ospd, 3, 0x66c2, 0x10, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpeq_ospd, 3, 0x66c2, 0x10, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpeq_osps, 3, 0xc2, 0x10, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpeq_osps, 3, 0xc2, 0x10, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpeq_osps, 3, 0xc2, 0x10, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpeq_ossd, 3, 0xf2c2, 0x10, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpeq_osss, 3, 0xf3c2, 0x10, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpeqpd, 3, 0x66c2, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpeqpd, 3, 0x66c2, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpeqpd, 3, 0x66c2, 0x0, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpeqps, 3, 0xc2, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpeqps, 3, 0xc2, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpeqps, 3, 0xc2, 0x0, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpeqsd, 3, 0xf2c2, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpeqss, 3, 0xf3c2, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpeq_uqpd, 3, 0x66c2, 0x8, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpeq_uqpd, 3, 0x66c2, 0x8, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpeq_uqpd, 3, 0x66c2, 0x8, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpeq_uqps, 3, 0xc2, 0x8, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpeq_uqps, 3, 0xc2, 0x8, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpeq_uqps, 3, 0xc2, 0x8, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpeq_uqsd, 3, 0xf2c2, 0x8, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpeq_uqss, 3, 0xf3c2, 0x8, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpeq_uspd, 3, 0x66c2, 0x18, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpeq_uspd, 3, 0x66c2, 0x18, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpeq_uspd, 3, 0x66c2, 0x18, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpeq_usps, 3, 0xc2, 0x18, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpeq_usps, 3, 0xc2, 0x18, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpeq_usps, 3, 0xc2, 0x18, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpeq_ussd, 3, 0xf2c2, 0x18, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpeq_usss, 3, 0xf3c2, 0x18, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpfalse_ospd, 3, 0x66c2, 0x1b, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpfalse_ospd, 3, 0x66c2, 0x1b, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpfalse_ospd, 3, 0x66c2, 0x1b, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpfalse_osps, 3, 0xc2, 0x1b, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpfalse_osps, 3, 0xc2, 0x1b, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpfalse_osps, 3, 0xc2, 0x1b, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpfalse_ossd, 3, 0xf2c2, 0x1b, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpfalse_osss, 3, 0xf3c2, 0x1b, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpfalsepd, 3, 0x66c2, 0xb, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpfalsepd, 3, 0x66c2, 0xb, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpfalsepd, 3, 0x66c2, 0xb, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpfalseps, 3, 0xc2, 0xb, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpfalseps, 3, 0xc2, 0xb, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpfalseps, 3, 0xc2, 0xb, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpfalsesd, 3, 0xf2c2, 0xb, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpfalsess, 3, 0xf3c2, 0xb, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpge_oqpd, 3, 0x66c2, 0x1d, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpge_oqpd, 3, 0x66c2, 0x1d, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpge_oqpd, 3, 0x66c2, 0x1d, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpge_oqps, 3, 0xc2, 0x1d, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpge_oqps, 3, 0xc2, 0x1d, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpge_oqps, 3, 0xc2, 0x1d, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpge_oqsd, 3, 0xf2c2, 0x1d, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpge_oqss, 3, 0xf3c2, 0x1d, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpgepd, 3, 0x66c2, 0xd, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpgepd, 3, 0x66c2, 0xd, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpgepd, 3, 0x66c2, 0xd, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpgeps, 3, 0xc2, 0xd, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpgeps, 3, 0xc2, 0xd, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpgeps, 3, 0xc2, 0xd, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpgesd, 3, 0xf2c2, 0xd, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpgess, 3, 0xf3c2, 0xd, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpgt_oqpd, 3, 0x66c2, 0x1e, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpgt_oqpd, 3, 0x66c2, 0x1e, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpgt_oqpd, 3, 0x66c2, 0x1e, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpgt_oqps, 3, 0xc2, 0x1e, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpgt_oqps, 3, 0xc2, 0x1e, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpgt_oqps, 3, 0xc2, 0x1e, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpgt_oqsd, 3, 0xf2c2, 0x1e, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpgt_oqss, 3, 0xf3c2, 0x1e, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpgtpd, 3, 0x66c2, 0xe, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpgtpd, 3, 0x66c2, 0xe, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpgtpd, 3, 0x66c2, 0xe, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpgtps, 3, 0xc2, 0xe, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpgtps, 3, 0xc2, 0xe, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpgtps, 3, 0xc2, 0xe, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpgtsd, 3, 0xf2c2, 0xe, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpgtss, 3, 0xf3c2, 0xe, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmple_oqpd, 3, 0x66c2, 0x12, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmple_oqpd, 3, 0x66c2, 0x12, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmple_oqpd, 3, 0x66c2, 0x12, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmple_oqps, 3, 0xc2, 0x12, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmple_oqps, 3, 0xc2, 0x12, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmple_oqps, 3, 0xc2, 0x12, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmple_oqsd, 3, 0xf2c2, 0x12, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmple_oqss, 3, 0xf3c2, 0x12, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmplepd, 3, 0x66c2, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmplepd, 3, 0x66c2, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmplepd, 3, 0x66c2, 0x2, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpleps, 3, 0xc2, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpleps, 3, 0xc2, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpleps, 3, 0xc2, 0x2, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmplesd, 3, 0xf2c2, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpless, 3, 0xf3c2, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmplt_oqpd, 3, 0x66c2, 0x11, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmplt_oqpd, 3, 0x66c2, 0x11, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmplt_oqpd, 3, 0x66c2, 0x11, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmplt_oqps, 3, 0xc2, 0x11, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmplt_oqps, 3, 0xc2, 0x11, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmplt_oqps, 3, 0xc2, 0x11, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmplt_oqsd, 3, 0xf2c2, 0x11, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmplt_oqss, 3, 0xf3c2, 0x11, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpltpd, 3, 0x66c2, 0x1, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpltpd, 3, 0x66c2, 0x1, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpltpd, 3, 0x66c2, 0x1, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpltps, 3, 0xc2, 0x1, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpltps, 3, 0xc2, 0x1, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpltps, 3, 0xc2, 0x1, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpltsd, 3, 0xf2c2, 0x1, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpltss, 3, 0xf3c2, 0x1, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpneq_oqpd, 3, 0x66c2, 0xc, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpneq_oqpd, 3, 0x66c2, 0xc, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpneq_oqpd, 3, 0x66c2, 0xc, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpneq_oqps, 3, 0xc2, 0xc, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpneq_oqps, 3, 0xc2, 0xc, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpneq_oqps, 3, 0xc2, 0xc, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpneq_oqsd, 3, 0xf2c2, 0xc, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpneq_oqss, 3, 0xf3c2, 0xc, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpneq_ospd, 3, 0x66c2, 0x1c, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpneq_ospd, 3, 0x66c2, 0x1c, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpneq_ospd, 3, 0x66c2, 0x1c, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpneq_osps, 3, 0xc2, 0x1c, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpneq_osps, 3, 0xc2, 0x1c, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpneq_osps, 3, 0xc2, 0x1c, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpneq_ossd, 3, 0xf2c2, 0x1c, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpneq_osss, 3, 0xf3c2, 0x1c, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpneqpd, 3, 0x66c2, 0x4, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpneqpd, 3, 0x66c2, 0x4, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpneqpd, 3, 0x66c2, 0x4, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpneqps, 3, 0xc2, 0x4, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpneqps, 3, 0xc2, 0x4, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpneqps, 3, 0xc2, 0x4, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpneqsd, 3, 0xf2c2, 0x4, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpneqss, 3, 0xf3c2, 0x4, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpneq_uspd, 3, 0x66c2, 0x14, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpneq_uspd, 3, 0x66c2, 0x14, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpneq_uspd, 3, 0x66c2, 0x14, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpneq_usps, 3, 0xc2, 0x14, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpneq_usps, 3, 0xc2, 0x14, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpneq_usps, 3, 0xc2, 0x14, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpneq_ussd, 3, 0xf2c2, 0x14, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpneq_usss, 3, 0xf3c2, 0x14, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpngepd, 3, 0x66c2, 0x9, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpngepd, 3, 0x66c2, 0x9, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpngepd, 3, 0x66c2, 0x9, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpngeps, 3, 0xc2, 0x9, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpngeps, 3, 0xc2, 0x9, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpngeps, 3, 0xc2, 0x9, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpngesd, 3, 0xf2c2, 0x9, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpngess, 3, 0xf3c2, 0x9, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpnge_uqpd, 3, 0x66c2, 0x19, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpnge_uqpd, 3, 0x66c2, 0x19, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpnge_uqpd, 3, 0x66c2, 0x19, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpnge_uqps, 3, 0xc2, 0x19, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpnge_uqps, 3, 0xc2, 0x19, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpnge_uqps, 3, 0xc2, 0x19, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpnge_uqsd, 3, 0xf2c2, 0x19, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpnge_uqss, 3, 0xf3c2, 0x19, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpngtpd, 3, 0x66c2, 0xa, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpngtpd, 3, 0x66c2, 0xa, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpngtpd, 3, 0x66c2, 0xa, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpngtps, 3, 0xc2, 0xa, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpngtps, 3, 0xc2, 0xa, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpngtps, 3, 0xc2, 0xa, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpngtsd, 3, 0xf2c2, 0xa, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpngtss, 3, 0xf3c2, 0xa, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpngt_uqpd, 3, 0x66c2, 0x1a, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpngt_uqpd, 3, 0x66c2, 0x1a, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpngt_uqpd, 3, 0x66c2, 0x1a, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpngt_uqps, 3, 0xc2, 0x1a, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpngt_uqps, 3, 0xc2, 0x1a, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpngt_uqps, 3, 0xc2, 0x1a, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpngt_uqsd, 3, 0xf2c2, 0x1a, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpngt_uqss, 3, 0xf3c2, 0x1a, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpnlepd, 3, 0x66c2, 0x6, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpnlepd, 3, 0x66c2, 0x6, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpnlepd, 3, 0x66c2, 0x6, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpnleps, 3, 0xc2, 0x6, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpnleps, 3, 0xc2, 0x6, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpnleps, 3, 0xc2, 0x6, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpnlesd, 3, 0xf2c2, 0x6, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpnless, 3, 0xf3c2, 0x6, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpnle_uqpd, 3, 0x66c2, 0x16, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpnle_uqpd, 3, 0x66c2, 0x16, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpnle_uqpd, 3, 0x66c2, 0x16, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpnle_uqps, 3, 0xc2, 0x16, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpnle_uqps, 3, 0xc2, 0x16, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpnle_uqps, 3, 0xc2, 0x16, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpnle_uqsd, 3, 0xf2c2, 0x16, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpnle_uqss, 3, 0xf3c2, 0x16, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpnltpd, 3, 0x66c2, 0x5, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpnltpd, 3, 0x66c2, 0x5, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpnltpd, 3, 0x66c2, 0x5, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpnltps, 3, 0xc2, 0x5, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpnltps, 3, 0xc2, 0x5, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpnltps, 3, 0xc2, 0x5, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpnltsd, 3, 0xf2c2, 0x5, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpnltss, 3, 0xf3c2, 0x5, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpnlt_uqpd, 3, 0x66c2, 0x15, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpnlt_uqpd, 3, 0x66c2, 0x15, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpnlt_uqpd, 3, 0x66c2, 0x15, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpnlt_uqps, 3, 0xc2, 0x15, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpnlt_uqps, 3, 0xc2, 0x15, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpnlt_uqps, 3, 0xc2, 0x15, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpnlt_uqsd, 3, 0xf2c2, 0x15, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpnlt_uqss, 3, 0xf3c2, 0x15, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpordpd, 3, 0x66c2, 0x7, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpordpd, 3, 0x66c2, 0x7, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpordpd, 3, 0x66c2, 0x7, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpordps, 3, 0xc2, 0x7, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpordps, 3, 0xc2, 0x7, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpordps, 3, 0xc2, 0x7, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpordsd, 3, 0xf2c2, 0x7, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpord_spd, 3, 0x66c2, 0x17, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpord_spd, 3, 0x66c2, 0x17, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpord_spd, 3, 0x66c2, 0x17, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpord_sps, 3, 0xc2, 0x17, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpord_sps, 3, 0xc2, 0x17, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpord_sps, 3, 0xc2, 0x17, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpordss, 3, 0xf3c2, 0x7, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpord_ssd, 3, 0xf2c2, 0x17, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpord_sss, 3, 0xf3c2, 0x17, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmppd, 4, 0x66c2, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmppd, 4, 0x66c2, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmppd, 4, 0x66c2, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpps, 4, 0xc2, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpps, 4, 0xc2, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpps, 4, 0xc2, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpsd, 4, 0xf2c2, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpss, 4, 0xf3c2, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmptruepd, 3, 0x66c2, 0xf, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmptruepd, 3, 0x66c2, 0xf, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmptruepd, 3, 0x66c2, 0xf, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmptrueps, 3, 0xc2, 0xf, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmptrueps, 3, 0xc2, 0xf, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmptrueps, 3, 0xc2, 0xf, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmptruesd, 3, 0xf2c2, 0xf, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmptruess, 3, 0xf3c2, 0xf, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmptrue_uspd, 3, 0x66c2, 0x1f, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmptrue_uspd, 3, 0x66c2, 0x1f, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmptrue_uspd, 3, 0x66c2, 0x1f, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmptrue_usps, 3, 0xc2, 0x1f, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmptrue_usps, 3, 0xc2, 0x1f, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmptrue_usps, 3, 0xc2, 0x1f, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmptrue_ussd, 3, 0xf2c2, 0x1f, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmptrue_usss, 3, 0xf3c2, 0x1f, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpunordpd, 3, 0x66c2, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpunordpd, 3, 0x66c2, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpunordpd, 3, 0x66c2, 0x3, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpunordps, 3, 0xc2, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpunordps, 3, 0xc2, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpunordps, 3, 0xc2, 0x3, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpunordsd, 3, 0xf2c2, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpunord_spd, 3, 0x66c2, 0x13, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpunord_spd, 3, 0x66c2, 0x13, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpunord_spd, 3, 0x66c2, 0x13, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpunord_sps, 3, 0xc2, 0x13, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vcmpunord_sps, 3, 0xc2, 0x13, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vcmpunord_sps, 3, 0xc2, 0x13, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vcmpunordss, 3, 0xf3c2, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpunord_ssd, 3, 0xf2c2, 0x13, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcmpunord_sss, 3, 0xf3c2, 0x13, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcomisd, 2, 0x662f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 vcomiss, 2, 0x2f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 vcvtdq2pd, 2, 0xf3e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-vcvtdq2pd, 2, 0xf3e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegYMM }
+vcvtdq2pd, 2, 0xf3e6, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegYMM }
 vcvtdq2ps, 2, 0x5b, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-vcvtdq2ps, 2, 0x5b, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
+vcvtdq2ps, 2, 0x5b, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vcvtpd2dq, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM }
 vcvtpd2dq, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Xmmword|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM }
-vcvtpd2dq, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM }
-vcvtpd2dq, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Ymmword|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM }
+vcvtpd2dq, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM }
+vcvtpd2dq, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Ymmword|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM }
 vcvtpd2dqx, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-vcvtpd2dqy, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegXMM }
+vcvtpd2dqy, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegXMM }
 vcvtpd2ps, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM }
 vcvtpd2ps, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|Vex0F|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Xmmword|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM }
-vcvtpd2ps, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM }
-vcvtpd2ps, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Ymmword|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM }
+vcvtpd2ps, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM }
+vcvtpd2ps, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Ymmword|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM }
 vcvtpd2psx, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|Vex0F|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-vcvtpd2psy, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegXMM }
+vcvtpd2psy, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegXMM }
 vcvtps2dq, 2, 0x665b, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-vcvtps2dq, 2, 0x665b, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
+vcvtps2dq, 2, 0x665b, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vcvtps2pd, 2, 0x5a, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-vcvtps2pd, 2, 0x5a, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegYMM }
+vcvtps2pd, 2, 0x5a, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegYMM }
 vcvtsd2si, 2, 0xf22d, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToDword, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 }
 vcvtsd2ss, 3, 0xf25a, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vcvtsi2sd, 3, 0xf22a, None, 1, CpuAVX|CpuNo64, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM }
@@ -2040,67 +2040,67 @@ vcvtss2sd, 3, 0xf35a, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf
 vcvtss2si, 2, 0xf32d, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 }
 vcvttpd2dq, 2, 0x66e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM }
 vcvttpd2dq, 2, 0x66e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Intelsyntax, { Xmmword|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM }
-vcvttpd2dq, 2, 0x66e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM }
-vcvttpd2dq, 2, 0x66e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Intelsyntax, { Ymmword|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM }
+vcvttpd2dq, 2, 0x66e6, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM }
+vcvttpd2dq, 2, 0x66e6, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Intelsyntax, { Ymmword|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM }
 vcvttpd2dqx, 2, 0x66e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTsyntax, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-vcvttpd2dqy, 2, 0x66e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTsyntax, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegXMM }
+vcvttpd2dqy, 2, 0x66e6, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTsyntax, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegXMM }
 vcvttps2dq, 2, 0xf35b, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-vcvttps2dq, 2, 0xf35b, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
+vcvttps2dq, 2, 0xf35b, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vcvttsd2si, 2, 0xf22c, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToDword, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 }
 vcvttss2si, 2, 0xf32c, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 }
 vdivpd, 3, 0x665e, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vdivpd, 3, 0x665e, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vdivpd, 3, 0x665e, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vdivps, 3, 0x5e, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vdivps, 3, 0x5e, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vdivps, 3, 0x5e, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vdivsd, 3, 0xf25e, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vdivss, 3, 0xf35e, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vdppd, 4, 0x6641, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vdpps, 4, 0x6640, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vdpps, 4, 0x6640, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
-vextractf128, 3, 0x6619, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
+vdpps, 4, 0x6640, None, 1, CpuAVX, Modrm|Vex=2|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vextractf128, 3, 0x6619, None, 1, CpuAVX, Modrm|Vex=2|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
 vextractps, 3, 0x6617, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 vhaddpd, 3, 0x667c, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vhaddpd, 3, 0x667c, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vhaddpd, 3, 0x667c, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vhaddps, 3, 0xf27c, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vhaddps, 3, 0xf27c, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vhaddps, 3, 0xf27c, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vhsubpd, 3, 0x667d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vhsubpd, 3, 0x667d, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vhsubpd, 3, 0x667d, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vhsubps, 3, 0xf27d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vhsubps, 3, 0xf27d, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
-vinsertf128, 4, 0x6618, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegYMM, RegYMM }
+vhsubps, 3, 0xf27d, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vinsertf128, 4, 0x6618, None, 1, CpuAVX, Modrm|Vex=2|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegYMM, RegYMM }
 vinsertps, 4, 0x6621, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vlddqu, 2, 0xf2f0, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM }
-vlddqu, 2, 0xf2f0, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegYMM }
+vlddqu, 2, 0xf2f0, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegYMM }
 vldmxcsr, 1, 0xae, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 vmaskmovdqu, 2, 0x66f7, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM }
 vmaskmovpd, 3, 0x662f, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-vmaskmovpd, 3, 0x662f, None, 1, CpuAVX, Modrm|Vex|Vex0F38|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+vmaskmovpd, 3, 0x662f, None, 1, CpuAVX, Modrm|Vex=2|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 vmaskmovpd, 3, 0x662d, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM }
-vmaskmovpd, 3, 0x662d, None, 1, CpuAVX, Modrm|Vex|Vex0F38|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegYMM, RegYMM }
+vmaskmovpd, 3, 0x662d, None, 1, CpuAVX, Modrm|Vex=2|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegYMM, RegYMM }
 vmaskmovps, 3, 0x662e, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-vmaskmovps, 3, 0x662e, None, 1, CpuAVX, Modrm|Vex|Vex0F38|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+vmaskmovps, 3, 0x662e, None, 1, CpuAVX, Modrm|Vex=2|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 vmaskmovps, 3, 0x662c, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM }
-vmaskmovps, 3, 0x662c, None, 1, CpuAVX, Modrm|Vex|Vex0F38|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegYMM, RegYMM }
+vmaskmovps, 3, 0x662c, None, 1, CpuAVX, Modrm|Vex=2|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegYMM, RegYMM }
 vmaxpd, 3, 0x665f, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vmaxpd, 3, 0x665f, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vmaxpd, 3, 0x665f, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vmaxps, 3, 0x5f, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vmaxps, 3, 0x5f, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vmaxps, 3, 0x5f, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vmaxsd, 3, 0xf25f, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vmaxss, 3, 0xf35f, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vminpd, 3, 0x665d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vminpd, 3, 0x665d, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vminpd, 3, 0x665d, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vminps, 3, 0x5d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vminps, 3, 0x5d, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vminps, 3, 0x5d, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vminsd, 3, 0xf25d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vminss, 3, 0xf35d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vmovapd, 2, 0x6628, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 vmovapd, 2, 0x6629, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
-vmovapd, 2, 0x6628, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
-vmovapd, 2, 0x6629, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM }
+vmovapd, 2, 0x6628, None, 1, CpuAVX, S|Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
+vmovapd, 2, 0x6629, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM }
 vmovaps, 2, 0x28, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 vmovaps, 2, 0x29, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
-vmovaps, 2, 0x28, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
-vmovaps, 2, 0x29, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM }
+vmovaps, 2, 0x28, None, 1, CpuAVX, S|Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
+vmovaps, 2, 0x29, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM }
 // vmovd really shouldn't allow for 64bit operand (vmovq is the right
 // mnemonic for copying between Reg64/Mem64 and RegXMM, as is mandated
 // by Intel AVX spec).  To avoid extra template in gcc x86 backend and
@@ -2111,15 +2111,15 @@ vmovd, 2, 0x666e, None, 1, CpuAVX|Cpu64, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_w
 vmovd, 2, 0x667e, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 vmovd, 2, 0x667e, None, 1, CpuAVX|Cpu64, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { RegXMM, Qword|Reg64|BaseIndex|Disp8|Disp32|Disp32S }
 vmovddup, 2, 0xf212, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-vmovddup, 2, 0xf212, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
+vmovddup, 2, 0xf212, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vmovdqa, 2, 0x666f, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 vmovdqa, 2, 0x667f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
-vmovdqa, 2, 0x666f, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
-vmovdqa, 2, 0x667f, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM }
+vmovdqa, 2, 0x666f, None, 1, CpuAVX, S|Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
+vmovdqa, 2, 0x667f, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM }
 vmovdqu, 2, 0xf36f, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 vmovdqu, 2, 0xf37f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
-vmovdqu, 2, 0xf36f, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
-vmovdqu, 2, 0xf37f, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM }
+vmovdqu, 2, 0xf36f, None, 1, CpuAVX, S|Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
+vmovdqu, 2, 0xf37f, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM }
 vmovhlps, 3, 0x12, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
 vmovhpd, 3, 0x6616, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM }
 vmovhpd, 2, 0x6617, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
@@ -2131,16 +2131,16 @@ vmovlpd, 2, 0x6613, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|
 vmovlps, 3, 0x12, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM }
 vmovlps, 2, 0x13, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 vmovmskpd, 2, 0x6650, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 }
-vmovmskpd, 2, 0x6650, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegYMM, Reg32|Reg64 }
+vmovmskpd, 2, 0x6650, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegYMM, Reg32|Reg64 }
 vmovmskps, 2, 0x50, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 }
-vmovmskps, 2, 0x50, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegYMM, Reg32|Reg64 }
+vmovmskps, 2, 0x50, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegYMM, Reg32|Reg64 }
 vmovntdq, 2, 0x66e7, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-vmovntdq, 2, 0x66e7, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+vmovntdq, 2, 0x66e7, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 vmovntdqa, 2, 0x662a, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM }
 vmovntpd, 2, 0x662b, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-vmovntpd, 2, 0x662b, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+vmovntpd, 2, 0x662b, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 vmovntps, 2, 0x2b, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-vmovntps, 2, 0x2b, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+vmovntps, 2, 0x2b, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 vmovq, 2, 0xf37e, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 vmovq, 2, 0x66d6, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
 vmovq, 2, 0x666e, None, 1, CpuAVX|Cpu64, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, RegXMM }
@@ -2150,32 +2150,32 @@ vmovsd, 2, 0xf210, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|N
 vmovsd, 3, 0xf210, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
 vmovsd, 3, 0xf211, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM|RegMem }
 vmovshdup, 2, 0xf316, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-vmovshdup, 2, 0xf316, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
+vmovshdup, 2, 0xf316, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vmovsldup, 2, 0xf312, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-vmovsldup, 2, 0xf312, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
+vmovsldup, 2, 0xf312, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vmovss, 2, 0xf311, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 vmovss, 2, 0xf310, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM }
 vmovss, 3, 0xf310, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
 vmovss, 3, 0xf311, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM|RegMem }
 vmovupd, 2, 0x6610, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 vmovupd, 2, 0x6611, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
-vmovupd, 2, 0x6610, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
-vmovupd, 2, 0x6611, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM }
+vmovupd, 2, 0x6610, None, 1, CpuAVX, S|Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
+vmovupd, 2, 0x6611, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM }
 vmovups, 2, 0x10, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 vmovups, 2, 0x11, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
-vmovups, 2, 0x10, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
-vmovups, 2, 0x11, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM }
+vmovups, 2, 0x10, None, 1, CpuAVX, S|Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
+vmovups, 2, 0x11, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM }
 vmpsadbw, 4, 0x6642, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vmulpd, 3, 0x6659, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vmulpd, 3, 0x6659, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vmulpd, 3, 0x6659, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vmulps, 3, 0x59, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vmulps, 3, 0x59, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vmulps, 3, 0x59, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vmulsd, 3, 0xf259, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vmulss, 3, 0xf359, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vorpd, 3, 0x6656, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vorpd, 3, 0x6656, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vorpd, 3, 0x6656, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vorps, 3, 0x56, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vorps, 3, 0x56, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vorps, 3, 0x56, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vpabsb, 2, 0x661c, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 vpabsd, 2, 0x661e, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 vpabsw, 2, 0x661d, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
@@ -2210,15 +2210,15 @@ vpcmpgtq, 3, 0x6637, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSu
 vpcmpgtw, 3, 0x6665, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vpcmpistri, 3, 0x6663, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 vpcmpistrm, 3, 0x6662, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-vperm2f128, 4, 0x6606, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vperm2f128, 4, 0x6606, None, 1, CpuAVX, Modrm|Vex=2|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vpermilpd, 3, 0x660d, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vpermilpd, 3, 0x660d, None, 1, CpuAVX, Modrm|Vex|Vex0F38|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vpermilpd, 3, 0x660d, None, 1, CpuAVX, Modrm|Vex=2|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vpermilpd, 3, 0x6605, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-vpermilpd, 3, 0x6605, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
+vpermilpd, 3, 0x6605, None, 1, CpuAVX, Modrm|Vex=2|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vpermilps, 3, 0x660c, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vpermilps, 3, 0x660c, None, 1, CpuAVX, Modrm|Vex|Vex0F38|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vpermilps, 3, 0x660c, None, 1, CpuAVX, Modrm|Vex=2|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vpermilps, 3, 0x6604, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-vpermilps, 3, 0x6604, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
+vpermilps, 3, 0x6604, None, 1, CpuAVX, Modrm|Vex=2|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vpextrb, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ByteOkIntel|NoRex64, { Imm8, RegXMM, Reg32|Reg64|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 vpextrd, 3, 0x6616, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 vpextrq, 3, 0x6616, None, 1, CpuAVX|Cpu64, Modrm|Vex|Vex0F3A|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S }
@@ -2305,7 +2305,7 @@ vpsubusb, 3, 0x66d8, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|
 vpsubusw, 3, 0x66d9, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vpsubw, 3, 0x66f9, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vptest, 2, 0x6617, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-vptest, 2, 0x6617, None, 1, CpuAVX, Modrm|Vex|Vex0F38|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
+vptest, 2, 0x6617, None, 1, CpuAVX, Modrm|Vex=2|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vpunpckhbw, 3, 0x6668, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vpunpckhdq, 3, 0x666a, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vpunpckhqdq, 3, 0x666d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
@@ -2316,53 +2316,53 @@ vpunpcklqdq, 3, 0x666c, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bS
 vpunpcklwd, 3, 0x6661, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vpxor, 3, 0x66ef, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vrcpps, 2, 0x53, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-vrcpps, 2, 0x53, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
+vrcpps, 2, 0x53, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vrcpss, 3, 0xf353, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vroundpd, 3, 0x6609, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-vroundpd, 3, 0x6609, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
+vroundpd, 3, 0x6609, None, 1, CpuAVX, Modrm|Vex=2|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vroundps, 3, 0x6608, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-vroundps, 3, 0x6608, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
+vroundps, 3, 0x6608, None, 1, CpuAVX, Modrm|Vex=2|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vroundsd, 4, 0x660b, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vroundss, 4, 0x660a, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vrsqrtps, 2, 0x52, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-vrsqrtps, 2, 0x52, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
+vrsqrtps, 2, 0x52, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vrsqrtss, 3, 0xf352, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vshufpd, 4, 0x66c6, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vshufpd, 4, 0x66c6, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vshufpd, 4, 0x66c6, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vshufps, 4, 0xc6, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vshufps, 4, 0xc6, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vshufps, 4, 0xc6, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vsqrtpd, 2, 0x6651, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-vsqrtpd, 2, 0x6651, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
+vsqrtpd, 2, 0x6651, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vsqrtps, 2, 0x51, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-vsqrtps, 2, 0x51, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
+vsqrtps, 2, 0x51, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vsqrtsd, 3, 0xf251, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vsqrtss, 3, 0xf351, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vstmxcsr, 1, 0xae, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 vsubpd, 3, 0x665c, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vsubpd, 3, 0x665c, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vsubpd, 3, 0x665c, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vsubps, 3, 0x5c, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vsubps, 3, 0x5c, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vsubps, 3, 0x5c, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vsubsd, 3, 0xf25c, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vsubss, 3, 0xf35c, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vtestpd, 2, 0x660f, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-vtestpd, 2, 0x660f, None, 1, CpuAVX, Modrm|Vex|Vex0F38|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
+vtestpd, 2, 0x660f, None, 1, CpuAVX, Modrm|Vex=2|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vtestps, 2, 0x660e, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-vtestps, 2, 0x660e, None, 1, CpuAVX, Modrm|Vex|Vex0F38|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
+vtestps, 2, 0x660e, None, 1, CpuAVX, Modrm|Vex=2|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vucomisd, 2, 0x662e, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 vucomiss, 2, 0x2e, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 vunpckhpd, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vunpckhpd, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vunpckhpd, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vunpckhps, 3, 0x15, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vunpckhps, 3, 0x15, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vunpckhps, 3, 0x15, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vunpcklpd, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vunpcklpd, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vunpcklpd, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vunpcklps, 3, 0x14, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vunpcklps, 3, 0x14, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vunpcklps, 3, 0x14, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vxorpd, 3, 0x6657, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vxorpd, 3, 0x6657, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vxorpd, 3, 0x6657, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vxorps, 3, 0x57, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vxorps, 3, 0x57, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
-vzeroall, 0, 0x77, None, 1, CpuAVX, Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+vxorps, 3, 0x57, None, 1, CpuAVX, Modrm|Vex=2|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vzeroall, 0, 0x77, None, 1, CpuAVX, Vex=2|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 vzeroupper, 0, 0x77, None, 1, CpuAVX, Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 
 // AES + AVX
@@ -2385,17 +2385,17 @@ vpclmulhqhqdq, 3, 0x6644, 0x11, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|Vex0F3A|VexNDS|Ig
 // FMA instructions
 
 vfmadd132pd, 3, 0x6698, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmadd132pd, 3, 0x6698, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmadd132pd, 3, 0x6698, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmadd132ps, 3, 0x6698, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmadd132ps, 3, 0x6698, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmadd132ps, 3, 0x6698, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmadd213pd, 3, 0x66a8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmadd213pd, 3, 0x66a8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmadd213pd, 3, 0x66a8, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmadd213ps, 3, 0x66a8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmadd213ps, 3, 0x66a8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmadd213ps, 3, 0x66a8, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmadd231pd, 3, 0x66b8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmadd231pd, 3, 0x66b8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmadd231pd, 3, 0x66b8, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmadd231ps, 3, 0x66b8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmadd231ps, 3, 0x66b8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmadd231ps, 3, 0x66b8, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmadd132sd, 3, 0x6699, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vfmadd132ss, 3, 0x6699, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vfmadd213sd, 3, 0x66a9, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
@@ -2403,41 +2403,41 @@ vfmadd213ss, 3, 0x66a9, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSi
 vfmadd231sd, 3, 0x66b9, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vfmadd231ss, 3, 0x66b9, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vfmaddsub132pd, 3, 0x6696, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmaddsub132pd, 3, 0x6696, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmaddsub132pd, 3, 0x6696, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmaddsub132ps, 3, 0x6696, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmaddsub132ps, 3, 0x6696, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmaddsub132ps, 3, 0x6696, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmaddsub213pd, 3, 0x66a6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmaddsub213pd, 3, 0x66a6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmaddsub213pd, 3, 0x66a6, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmaddsub213ps, 3, 0x66a6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmaddsub213ps, 3, 0x66a6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmaddsub213ps, 3, 0x66a6, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmaddsub231pd, 3, 0x66b6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmaddsub231pd, 3, 0x66b6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmaddsub231pd, 3, 0x66b6, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmaddsub231ps, 3, 0x66b6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmaddsub231ps, 3, 0x66b6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmaddsub231ps, 3, 0x66b6, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmsubadd132pd, 3, 0x6697, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmsubadd132pd, 3, 0x6697, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmsubadd132pd, 3, 0x6697, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmsubadd132ps, 3, 0x6697, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmsubadd132ps, 3, 0x6697, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmsubadd132ps, 3, 0x6697, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmsubadd213pd, 3, 0x66a7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmsubadd213pd, 3, 0x66a7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmsubadd213pd, 3, 0x66a7, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmsubadd213ps, 3, 0x66a7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmsubadd213ps, 3, 0x66a7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmsubadd213ps, 3, 0x66a7, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmsubadd231pd, 3, 0x66b7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmsubadd231pd, 3, 0x66b7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmsubadd231pd, 3, 0x66b7, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmsubadd231ps, 3, 0x66b7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmsubadd231ps, 3, 0x66b7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmsubadd231ps, 3, 0x66b7, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmsub132pd, 3, 0x669a, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmsub132pd, 3, 0x669a, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmsub132pd, 3, 0x669a, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmsub132ps, 3, 0x669a, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmsub132ps, 3, 0x669a, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmsub132ps, 3, 0x669a, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmsub213pd, 3, 0x66aa, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmsub213pd, 3, 0x66aa, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmsub213pd, 3, 0x66aa, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmsub213ps, 3, 0x66aa, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmsub213ps, 3, 0x66aa, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmsub213ps, 3, 0x66aa, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmsub231pd, 3, 0x66ba, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmsub231pd, 3, 0x66ba, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmsub231pd, 3, 0x66ba, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmsub231ps, 3, 0x66ba, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmsub231ps, 3, 0x66ba, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmsub231ps, 3, 0x66ba, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmsub132sd, 3, 0x669b, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vfmsub132ss, 3, 0x669b, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vfmsub213sd, 3, 0x66ab, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
@@ -2445,17 +2445,17 @@ vfmsub213ss, 3, 0x66ab, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSi
 vfmsub231sd, 3, 0x66bb, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vfmsub231ss, 3, 0x66bb, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vfnmadd132pd, 3, 0x669c, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfnmadd132pd, 3, 0x669c, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfnmadd132pd, 3, 0x669c, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfnmadd132ps, 3, 0x669c, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfnmadd132ps, 3, 0x669c, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfnmadd132ps, 3, 0x669c, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfnmadd213pd, 3, 0x66ac, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfnmadd213pd, 3, 0x66ac, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfnmadd213pd, 3, 0x66ac, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfnmadd213ps, 3, 0x66ac, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfnmadd213ps, 3, 0x66ac, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfnmadd213ps, 3, 0x66ac, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfnmadd231pd, 3, 0x66bc, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfnmadd231pd, 3, 0x66bc, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfnmadd231pd, 3, 0x66bc, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfnmadd231ps, 3, 0x66bc, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfnmadd231ps, 3, 0x66bc, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfnmadd231ps, 3, 0x66bc, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfnmadd132sd, 3, 0x669d, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vfnmadd132ss, 3, 0x669d, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vfnmadd213sd, 3, 0x66ad, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
@@ -2463,17 +2463,17 @@ vfnmadd213ss, 3, 0x66ad, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreS
 vfnmadd231sd, 3, 0x66bd, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vfnmadd231ss, 3, 0x66bd, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vfnmsub132pd, 3, 0x669e, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfnmsub132pd, 3, 0x669e, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfnmsub132pd, 3, 0x669e, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfnmsub132ps, 3, 0x669e, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfnmsub132ps, 3, 0x669e, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfnmsub132ps, 3, 0x669e, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfnmsub213pd, 3, 0x66ae, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfnmsub213pd, 3, 0x66ae, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfnmsub213pd, 3, 0x66ae, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfnmsub213ps, 3, 0x66ae, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfnmsub213ps, 3, 0x66ae, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfnmsub213ps, 3, 0x66ae, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfnmsub231pd, 3, 0x66be, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfnmsub231pd, 3, 0x66be, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfnmsub231pd, 3, 0x66be, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfnmsub231ps, 3, 0x66be, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfnmsub231ps, 3, 0x66be, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfnmsub231ps, 3, 0x66be, None, 1, CpuFMA, Modrm|Vex=2|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfnmsub132sd, 3, 0x669f, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vfnmsub132ss, 3, 0x669f, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vfnmsub213sd, 3, 0x66af, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
@@ -2485,64 +2485,64 @@ vfnmsub231ss, 3, 0x66bf, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreS
 
 vfmaddpd, 4, 0x6669, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
 vfmaddpd, 4, 0x6669, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmaddpd, 4, 0x6669, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vfmaddpd, 4, 0x6669, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmaddpd, 4, 0x6669, None, 1, CpuFMA4, Modrm|Vex=2|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
+vfmaddpd, 4, 0x6669, None, 1, CpuFMA4, Modrm|Vex=2|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmaddps, 4, 0x6668, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
 vfmaddps, 4, 0x6668, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmaddps, 4, 0x6668, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vfmaddps, 4, 0x6668, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmaddps, 4, 0x6668, None, 1, CpuFMA4, Modrm|Vex=2|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
+vfmaddps, 4, 0x6668, None, 1, CpuFMA4, Modrm|Vex=2|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmaddsd, 4, 0x666b, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
 vfmaddsd, 4, 0x666b, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vfmaddss, 4, 0x666a, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
 vfmaddss, 4, 0x666a, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
 vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA4, Modrm|Vex=2|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
+vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA4, Modrm|Vex=2|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmaddsubps, 4, 0x665c, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
 vfmaddsubps, 4, 0x665c, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmaddsubps, 4, 0x665c, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vfmaddsubps, 4, 0x665c, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmaddsubps, 4, 0x665c, None, 1, CpuFMA4, Modrm|Vex=2|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
+vfmaddsubps, 4, 0x665c, None, 1, CpuFMA4, Modrm|Vex=2|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmsubaddpd, 4, 0x665f, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
 vfmsubaddpd, 4, 0x665f, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmsubaddpd, 4, 0x665f, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vfmsubaddpd, 4, 0x665f, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmsubaddpd, 4, 0x665f, None, 1, CpuFMA4, Modrm|Vex=2|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
+vfmsubaddpd, 4, 0x665f, None, 1, CpuFMA4, Modrm|Vex=2|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmsubaddps, 4, 0x665e, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
 vfmsubaddps, 4, 0x665e, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmsubaddps, 4, 0x665e, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vfmsubaddps, 4, 0x665e, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmsubaddps, 4, 0x665e, None, 1, CpuFMA4, Modrm|Vex=2|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
+vfmsubaddps, 4, 0x665e, None, 1, CpuFMA4, Modrm|Vex=2|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmsubpd, 4, 0x666d, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
 vfmsubpd, 4, 0x666d, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmsubpd, 4, 0x666d, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vfmsubpd, 4, 0x666d, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmsubpd, 4, 0x666d, None, 1, CpuFMA4, Modrm|Vex=2|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
+vfmsubpd, 4, 0x666d, None, 1, CpuFMA4, Modrm|Vex=2|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmsubps, 4, 0x666c, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
 vfmsubps, 4, 0x666c, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmsubps, 4, 0x666c, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vfmsubps, 4, 0x666c, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmsubps, 4, 0x666c, None, 1, CpuFMA4, Modrm|Vex=2|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
+vfmsubps, 4, 0x666c, None, 1, CpuFMA4, Modrm|Vex=2|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfmsubsd, 4, 0x666f, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
 vfmsubsd, 4, 0x666f, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vfmsubss, 4, 0x666e, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
 vfmsubss, 4, 0x666e, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vfnmaddpd, 4, 0x6679, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
 vfnmaddpd, 4, 0x6679, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfnmaddpd, 4, 0x6679, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vfnmaddpd, 4, 0x6679, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfnmaddpd, 4, 0x6679, None, 1, CpuFMA4, Modrm|Vex=2|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
+vfnmaddpd, 4, 0x6679, None, 1, CpuFMA4, Modrm|Vex=2|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfnmaddps, 4, 0x6678, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
 vfnmaddps, 4, 0x6678, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfnmaddps, 4, 0x6678, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vfnmaddps, 4, 0x6678, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfnmaddps, 4, 0x6678, None, 1, CpuFMA4, Modrm|Vex=2|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
+vfnmaddps, 4, 0x6678, None, 1, CpuFMA4, Modrm|Vex=2|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfnmaddsd, 4, 0x667b, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
 vfnmaddsd, 4, 0x667b, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vfnmaddss, 4, 0x667a, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
 vfnmaddss, 4, 0x667a, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vfnmsubpd, 4, 0x667d, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
 vfnmsubpd, 4, 0x667d, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfnmsubpd, 4, 0x667d, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vfnmsubpd, 4, 0x667d, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfnmsubpd, 4, 0x667d, None, 1, CpuFMA4, Modrm|Vex=2|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
+vfnmsubpd, 4, 0x667d, None, 1, CpuFMA4, Modrm|Vex=2|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfnmsubps, 4, 0x667c, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
 vfnmsubps, 4, 0x667c, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfnmsubps, 4, 0x667c, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vfnmsubps, 4, 0x667c, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfnmsubps, 4, 0x667c, None, 1, CpuFMA4, Modrm|Vex=2|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
+vfnmsubps, 4, 0x667c, None, 1, CpuFMA4, Modrm|Vex=2|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vfnmsubsd, 4, 0x667f, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
 vfnmsubsd, 4, 0x667f, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }

diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index aa24c53..fde29b4 100644 (file)
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -29,7 +29,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -42,7 +42,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -55,7 +55,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -68,7 +68,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -81,7 +81,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -94,7 +94,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -107,7 +107,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -120,7 +120,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -133,7 +133,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -146,7 +146,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -159,7 +159,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -172,7 +172,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -185,7 +185,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -198,7 +198,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -211,7 +211,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -224,7 +224,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -237,7 +237,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -250,7 +250,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -263,7 +263,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -276,7 +276,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -289,7 +289,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -302,7 +302,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -315,7 +315,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -328,7 +328,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -341,7 +341,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -354,7 +354,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -367,7 +367,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -380,7 +380,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -393,7 +393,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -406,7 +406,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -419,7 +419,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 },
     { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -432,7 +432,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 },
     { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -445,7 +445,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -458,7 +458,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 },
     { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -471,7 +471,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 },
     { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -484,7 +484,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -497,7 +497,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -510,7 +510,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -523,7 +523,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -536,7 +536,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -549,7 +549,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -562,7 +562,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -575,7 +575,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -588,7 +588,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 },
     { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -601,7 +601,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -614,7 +614,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 },
     { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -627,7 +627,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -637,7 +637,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -647,7 +647,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -657,7 +657,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -667,7 +667,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -677,7 +677,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -687,7 +687,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -697,7 +697,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -707,7 +707,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -717,7 +717,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -727,7 +727,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -737,7 +737,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -747,7 +747,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -757,7 +757,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -767,7 +767,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -777,7 +777,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -787,7 +787,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -797,7 +797,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -807,7 +807,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -817,7 +817,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -827,7 +827,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -840,7 +840,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 0, 0, 0 } },
@@ -853,7 +853,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -866,7 +866,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -879,7 +879,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -892,7 +892,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -905,7 +905,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -915,7 +915,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -925,7 +925,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -938,7 +938,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -951,7 +951,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -961,7 +961,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -971,7 +971,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 1, 0 } },
@@ -984,7 +984,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -997,7 +997,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -1010,7 +1010,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 
          0, 0, 1, 0, 0 } },
@@ -1023,7 +1023,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 
          0, 0, 1, 0, 0 } },
@@ -1036,7 +1036,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 
          0, 0, 1, 0, 0 } },
@@ -1049,7 +1049,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1059,7 +1059,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1069,7 +1069,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1079,7 +1079,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1089,7 +1089,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1099,7 +1099,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1109,7 +1109,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1119,7 +1119,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1129,7 +1129,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1139,7 +1139,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1149,7 +1149,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1159,7 +1159,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1169,7 +1169,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1179,7 +1179,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1189,7 +1189,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1202,7 +1202,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1215,7 +1215,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1228,7 +1228,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1241,7 +1241,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1251,7 +1251,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -1261,7 +1261,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1274,7 +1274,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1287,7 +1287,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1300,7 +1300,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1313,7 +1313,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1323,7 +1323,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -1333,7 +1333,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1346,7 +1346,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1359,7 +1359,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1372,7 +1372,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1385,7 +1385,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1398,7 +1398,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1411,7 +1411,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1424,7 +1424,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1437,7 +1437,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1450,7 +1450,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -1463,7 +1463,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1476,7 +1476,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1489,7 +1489,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1502,7 +1502,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1515,7 +1515,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1528,7 +1528,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1541,7 +1541,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1554,7 +1554,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1567,7 +1567,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1580,7 +1580,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1593,7 +1593,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1606,7 +1606,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1619,7 +1619,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1632,7 +1632,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1645,7 +1645,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1655,7 +1655,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1668,7 +1668,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1681,7 +1681,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1694,7 +1694,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1707,7 +1707,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -1717,7 +1717,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -1727,7 +1727,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1737,7 +1737,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1747,7 +1747,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1757,7 +1757,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1767,7 +1767,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1777,7 +1777,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1787,7 +1787,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1797,7 +1797,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1807,7 +1807,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1817,7 +1817,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1827,7 +1827,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1837,7 +1837,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1847,7 +1847,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1857,7 +1857,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1867,7 +1867,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1877,7 +1877,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1887,7 +1887,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1897,7 +1897,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1907,7 +1907,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1917,7 +1917,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -1927,7 +1927,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -1937,7 +1937,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -1947,7 +1947,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -1960,7 +1960,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1976,7 +1976,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -1992,7 +1992,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2005,7 +2005,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2018,7 +2018,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -2028,7 +2028,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -2041,7 +2041,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -2051,7 +2051,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -2064,7 +2064,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2077,7 +2077,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2090,7 +2090,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2103,7 +2103,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -2113,7 +2113,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2126,7 +2126,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2139,7 +2139,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2152,7 +2152,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -2162,7 +2162,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2175,7 +2175,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2188,7 +2188,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2201,7 +2201,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -2211,7 +2211,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2224,7 +2224,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2237,7 +2237,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2250,7 +2250,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -2260,7 +2260,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2273,7 +2273,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2286,7 +2286,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2299,7 +2299,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -2309,7 +2309,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2322,7 +2322,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2335,7 +2335,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2348,7 +2348,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -2358,7 +2358,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2371,7 +2371,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2384,7 +2384,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2397,7 +2397,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -2407,7 +2407,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2420,7 +2420,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2433,7 +2433,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2446,7 +2446,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -2456,7 +2456,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2472,7 +2472,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2488,7 +2488,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2501,7 +2501,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2517,7 +2517,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2533,7 +2533,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2546,7 +2546,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -2556,7 +2556,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -2566,7 +2566,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -2576,7 +2576,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -2586,7 +2586,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2599,7 +2599,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 
       1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -2609,7 +2609,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2622,7 +2622,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -2632,9 +2632,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "jmp", 1, 0xff, 0x4, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2642,7 +2642,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -2652,7 +2652,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -2662,7 +2662,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2675,7 +2675,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -2685,7 +2685,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2698,7 +2698,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -2708,7 +2708,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -2718,7 +2718,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -2728,7 +2728,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -2738,7 +2738,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -2748,7 +2748,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -2758,7 +2758,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -2768,7 +2768,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -2778,7 +2778,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -2788,7 +2788,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2801,7 +2801,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -2814,7 +2814,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -2824,7 +2824,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -2834,9 +2834,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "jno", 1, 0x71, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2844,9 +2844,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "jb", 1, 0x72, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2854,9 +2854,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "jc", 1, 0x72, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2864,9 +2864,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "jnae", 1, 0x72, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2874,9 +2874,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "jnb", 1, 0x73, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2884,9 +2884,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "jnc", 1, 0x73, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2894,9 +2894,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "jae", 1, 0x73, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2904,9 +2904,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "je", 1, 0x74, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2914,9 +2914,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "jz", 1, 0x74, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2924,9 +2924,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "jne", 1, 0x75, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2934,9 +2934,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "jnz", 1, 0x75, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2944,9 +2944,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "jbe", 1, 0x76, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2954,9 +2954,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "jna", 1, 0x76, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2964,9 +2964,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "jnbe", 1, 0x77, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2974,9 +2974,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "ja", 1, 0x77, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2984,9 +2984,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "js", 1, 0x78, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2994,9 +2994,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "jns", 1, 0x79, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -3004,9 +3004,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "jp", 1, 0x7a, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -3014,9 +3014,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "jpe", 1, 0x7a, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -3024,9 +3024,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "jnp", 1, 0x7b, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -3034,9 +3034,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "jpo", 1, 0x7b, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -3044,9 +3044,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "jl", 1, 0x7c, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -3054,9 +3054,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "jnge", 1, 0x7c, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -3064,9 +3064,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "jnl", 1, 0x7d, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -3074,9 +3074,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "jge", 1, 0x7d, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -3084,9 +3084,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "jle", 1, 0x7e, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -3094,9 +3094,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "jng", 1, 0x7e, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -3104,9 +3104,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "jnle", 1, 0x7f, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -3114,9 +3114,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "jg", 1, 0x7f, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -3124,9 +3124,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "jcxz", 1, 0xe3, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -3134,7 +3134,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -3144,7 +3144,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -3154,9 +3154,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "jrcxz", 1, 0xe3, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -3164,9 +3164,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "loop", 1, 0xe2, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -3174,7 +3174,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -3184,9 +3184,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "loopz", 1, 0xe1, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -3194,7 +3194,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -3204,9 +3204,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "loope", 1, 0xe1, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -3214,7 +3214,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -3224,9 +3224,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "loopnz", 1, 0xe0, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -3234,7 +3234,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -3244,9 +3244,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "loopne", 1, 0xe0, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -3254,7 +3254,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -3264,9 +3264,9 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
   { "seto", 1, 0xf90, 0x0, 2,
     { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -3274,7 +3274,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3284,7 +3284,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3294,7 +3294,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3304,7 +3304,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3314,7 +3314,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3324,7 +3324,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3334,7 +3334,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3344,7 +3344,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3354,7 +3354,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3364,7 +3364,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3374,7 +3374,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3384,7 +3384,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3394,7 +3394,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3404,7 +3404,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3414,7 +3414,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3424,7 +3424,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3434,7 +3434,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3444,7 +3444,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3454,7 +3454,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3464,7 +3464,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3474,7 +3474,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3484,7 +3484,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3494,7 +3494,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3504,7 +3504,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3514,7 +3514,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3524,7 +3524,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3534,7 +3534,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3544,7 +3544,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3554,7 +3554,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3564,7 +3564,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3574,7 +3574,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -3584,7 +3584,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -3597,7 +3597,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -3607,7 +3607,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -3620,7 +3620,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -3630,7 +3630,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -3643,7 +3643,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -3653,7 +3653,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -3666,7 +3666,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -3676,7 +3676,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3686,7 +3686,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -3699,7 +3699,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -3709,7 +3709,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3719,7 +3719,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -3732,7 +3732,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -3742,7 +3742,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -3755,7 +3755,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -3765,7 +3765,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -3778,7 +3778,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -3788,7 +3788,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3798,7 +3798,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -3811,7 +3811,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -3821,7 +3821,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3831,7 +3831,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -3844,7 +3844,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -3854,7 +3854,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3864,7 +3864,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 0, 0, 0 } },
@@ -3877,7 +3877,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -3887,7 +3887,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3897,7 +3897,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 
          0, 0, 0, 0, 0 } },
@@ -3910,7 +3910,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -3920,7 +3920,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -3930,7 +3930,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -3943,7 +3943,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -3956,7 +3956,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -3969,7 +3969,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -3982,7 +3982,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -3995,7 +3995,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -4008,7 +4008,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -4021,7 +4021,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -4034,7 +4034,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -4047,7 +4047,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -4060,7 +4060,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4070,7 +4070,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4080,7 +4080,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4090,7 +4090,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4100,7 +4100,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4110,7 +4110,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -4123,7 +4123,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4133,7 +4133,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -4143,7 +4143,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4153,7 +4153,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -4166,7 +4166,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -4179,7 +4179,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
          0, 0, 1, 0, 0 } } } },
@@ -4189,7 +4189,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 
          0, 0, 1, 0, 0 } } } },
@@ -4199,7 +4199,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -4209,7 +4209,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 
          0, 0, 1, 0, 0 } } } },
@@ -4219,7 +4219,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -4229,7 +4229,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -4239,7 +4239,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -4252,7 +4252,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -4262,7 +4262,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -4272,7 +4272,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 
          0, 0, 1, 0, 0 } } } },
@@ -4282,7 +4282,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -4292,7 +4292,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 
          0, 0, 1, 0, 0 } } } },
@@ -4302,7 +4302,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4312,7 +4312,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -4322,7 +4322,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4332,7 +4332,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -4342,7 +4342,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4352,7 +4352,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -4362,7 +4362,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -4372,7 +4372,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -4382,7 +4382,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4392,7 +4392,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -4402,7 +4402,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4412,7 +4412,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 
          0, 0, 1, 0, 0 } } } },
@@ -4422,7 +4422,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -4432,7 +4432,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -4442,7 +4442,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -4452,7 +4452,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 
          0, 0, 1, 0, 0 } } } },
@@ -4462,7 +4462,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 
          0, 0, 1, 0, 0 } } } },
@@ -4472,7 +4472,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4482,7 +4482,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -4492,7 +4492,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4502,7 +4502,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -4512,7 +4512,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4522,7 +4522,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -4532,7 +4532,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4542,7 +4542,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 
          0, 0, 1, 0, 0 } } } },
@@ -4552,7 +4552,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -4562,7 +4562,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -4572,7 +4572,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -4582,7 +4582,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 
          0, 0, 1, 0, 0 } } } },
@@ -4592,7 +4592,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 
          0, 0, 1, 0, 0 } } } },
@@ -4602,7 +4602,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4612,7 +4612,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4622,7 +4622,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4632,7 +4632,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4642,7 +4642,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -4652,7 +4652,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4662,7 +4662,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -4672,7 +4672,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4682,7 +4682,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4692,7 +4692,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -4702,7 +4702,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4712,7 +4712,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -4722,7 +4722,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4732,7 +4732,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4742,7 +4742,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4752,7 +4752,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4762,7 +4762,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4772,7 +4772,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4782,7 +4782,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4792,7 +4792,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4802,7 +4802,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4812,7 +4812,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4822,7 +4822,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4832,7 +4832,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4842,7 +4842,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4852,7 +4852,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4862,7 +4862,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4872,7 +4872,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -4885,7 +4885,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4895,7 +4895,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4905,7 +4905,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -4915,7 +4915,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -4925,7 +4925,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -4938,7 +4938,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4948,7 +4948,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4958,7 +4958,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -4971,7 +4971,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -4981,7 +4981,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -4994,7 +4994,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5004,7 +5004,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5014,7 +5014,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -5027,7 +5027,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -5037,7 +5037,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -5047,7 +5047,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -5060,7 +5060,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5070,7 +5070,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5080,7 +5080,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -5093,7 +5093,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -5106,7 +5106,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -5119,7 +5119,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5129,7 +5129,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5139,7 +5139,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5149,7 +5149,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -5162,7 +5162,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5172,7 +5172,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5182,7 +5182,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -5195,7 +5195,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -5205,7 +5205,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -5215,7 +5215,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -5228,7 +5228,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5238,7 +5238,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5248,7 +5248,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -5261,7 +5261,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -5274,7 +5274,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -5287,7 +5287,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5297,7 +5297,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5307,7 +5307,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -5320,7 +5320,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5330,7 +5330,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5340,7 +5340,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -5350,7 +5350,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -5360,7 +5360,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -5373,7 +5373,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5383,7 +5383,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5393,7 +5393,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -5406,7 +5406,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5416,7 +5416,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -5429,7 +5429,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5439,7 +5439,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5449,7 +5449,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -5462,7 +5462,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -5472,7 +5472,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -5482,7 +5482,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -5495,7 +5495,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5505,7 +5505,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5515,7 +5515,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -5528,7 +5528,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -5541,7 +5541,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -5554,7 +5554,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5564,7 +5564,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5574,7 +5574,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5584,7 +5584,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -5597,7 +5597,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5607,7 +5607,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5617,7 +5617,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -5630,7 +5630,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -5640,7 +5640,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -5650,7 +5650,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -5663,7 +5663,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5673,7 +5673,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5683,7 +5683,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -5696,7 +5696,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -5709,7 +5709,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -5722,7 +5722,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5732,7 +5732,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5742,7 +5742,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5752,7 +5752,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5762,7 +5762,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5772,7 +5772,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5782,7 +5782,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5792,7 +5792,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5802,7 +5802,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5812,7 +5812,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5822,7 +5822,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5832,7 +5832,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5842,7 +5842,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5852,7 +5852,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5862,7 +5862,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5872,7 +5872,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5882,7 +5882,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5892,7 +5892,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5902,7 +5902,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5912,7 +5912,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5922,7 +5922,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5932,7 +5932,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5942,7 +5942,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -5952,7 +5952,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -5962,7 +5962,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
       1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -5972,7 +5972,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -5982,7 +5982,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -5992,7 +5992,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6002,7 +6002,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6012,7 +6012,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
       1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -6022,7 +6022,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6032,7 +6032,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6042,7 +6042,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6052,7 +6052,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 
       0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -6062,7 +6062,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 
       0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -6072,7 +6072,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 
       0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -6082,7 +6082,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 
       0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -6092,7 +6092,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 
       0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -6102,7 +6102,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 
       0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -6112,7 +6112,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6122,7 +6122,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6132,7 +6132,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6142,7 +6142,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6152,7 +6152,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6162,7 +6162,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6172,7 +6172,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6182,7 +6182,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6192,7 +6192,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6202,7 +6202,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6212,7 +6212,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6222,7 +6222,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6232,7 +6232,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6242,7 +6242,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6252,7 +6252,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6262,7 +6262,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6272,7 +6272,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6282,7 +6282,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6292,7 +6292,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6302,7 +6302,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6312,7 +6312,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6322,7 +6322,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6332,7 +6332,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6342,7 +6342,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6352,7 +6352,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6362,7 +6362,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6372,7 +6372,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6382,7 +6382,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6392,7 +6392,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6402,7 +6402,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6412,7 +6412,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6422,7 +6422,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6432,7 +6432,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6442,7 +6442,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6452,7 +6452,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6462,7 +6462,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6472,7 +6472,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6482,7 +6482,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6492,7 +6492,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6502,7 +6502,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6512,7 +6512,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6522,7 +6522,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6532,7 +6532,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6542,7 +6542,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6552,7 +6552,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6562,7 +6562,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6572,7 +6572,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6582,7 +6582,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6592,7 +6592,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6602,7 +6602,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6612,7 +6612,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6622,7 +6622,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6632,7 +6632,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6642,7 +6642,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6652,7 +6652,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6662,7 +6662,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6672,7 +6672,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6682,7 +6682,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6692,7 +6692,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6702,7 +6702,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6712,7 +6712,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6722,7 +6722,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6732,7 +6732,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6742,7 +6742,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6752,7 +6752,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6762,7 +6762,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6772,7 +6772,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -6785,7 +6785,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -6798,7 +6798,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6808,7 +6808,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6818,7 +6818,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -6828,7 +6828,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6838,7 +6838,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6848,7 +6848,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6858,7 +6858,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6868,7 +6868,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -6878,7 +6878,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6888,7 +6888,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6898,7 +6898,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -6908,7 +6908,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -6918,7 +6918,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6928,7 +6928,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6938,7 +6938,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6948,7 +6948,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -6958,7 +6958,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -6971,7 +6971,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -6984,7 +6984,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -6997,7 +6997,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -7010,7 +7010,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -7023,7 +7023,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -7036,7 +7036,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -7049,7 +7049,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -7062,7 +7062,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -7075,7 +7075,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -7088,7 +7088,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -7101,7 +7101,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -7114,7 +7114,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -7127,7 +7127,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -7140,7 +7140,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -7153,7 +7153,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -7166,7 +7166,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -7179,7 +7179,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -7192,7 +7192,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -7205,7 +7205,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -7218,7 +7218,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -7231,7 +7231,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -7244,7 +7244,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -7257,7 +7257,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -7270,7 +7270,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -7283,7 +7283,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -7296,7 +7296,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -7309,7 +7309,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -7322,7 +7322,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -7335,7 +7335,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -7348,7 +7348,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -7361,7 +7361,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -7374,7 +7374,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -7387,7 +7387,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -7400,7 +7400,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -7413,7 +7413,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -7426,7 +7426,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -7439,7 +7439,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -7452,7 +7452,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -7465,7 +7465,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -7478,7 +7478,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -7491,7 +7491,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -7504,7 +7504,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -7517,7 +7517,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -7527,7 +7527,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -7537,7 +7537,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -7550,7 +7550,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -7560,7 +7560,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -7570,7 +7570,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -7583,7 +7583,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -7593,7 +7593,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -7603,7 +7603,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -7616,7 +7616,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -7626,7 +7626,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -7636,7 +7636,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -7649,7 +7649,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -7659,7 +7659,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -7669,7 +7669,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -7682,7 +7682,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -7692,7 +7692,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -7702,7 +7702,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -7715,7 +7715,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -7725,7 +7725,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -7735,7 +7735,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -7745,7 +7745,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -7755,7 +7755,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -7765,7 +7765,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -7778,7 +7778,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 0, 0, 0 } },
@@ -7791,7 +7791,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -7804,7 +7804,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -7817,7 +7817,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -7830,7 +7830,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 0, 0, 0 } },
@@ -7843,7 +7843,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -7856,7 +7856,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -7869,7 +7869,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -7882,7 +7882,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 0, 0, 0 } },
@@ -7895,7 +7895,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -7908,7 +7908,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -7921,7 +7921,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -7934,7 +7934,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -7947,7 +7947,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -7960,7 +7960,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -7973,7 +7973,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -7986,7 +7986,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -7999,7 +7999,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -8012,7 +8012,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -8025,7 +8025,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -8038,7 +8038,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -8051,7 +8051,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -8064,7 +8064,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -8077,7 +8077,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -8090,7 +8090,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -8103,7 +8103,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -8116,7 +8116,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -8129,7 +8129,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -8142,7 +8142,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -8155,7 +8155,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -8168,7 +8168,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -8180,8 +8180,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8194,7 +8194,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8207,7 +8207,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -8219,8 +8219,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8233,7 +8233,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8246,7 +8246,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -8258,8 +8258,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8272,7 +8272,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8285,7 +8285,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -8297,8 +8297,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8311,7 +8311,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8324,7 +8324,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -8336,8 +8336,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8350,7 +8350,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8363,7 +8363,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -8375,8 +8375,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8389,7 +8389,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8402,7 +8402,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -8414,8 +8414,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8428,7 +8428,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8441,7 +8441,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -8453,8 +8453,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8467,7 +8467,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8480,7 +8480,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -8492,8 +8492,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8506,7 +8506,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8519,7 +8519,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -8531,8 +8531,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8545,7 +8545,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8558,7 +8558,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -8570,8 +8570,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8584,7 +8584,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8597,7 +8597,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -8609,8 +8609,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8623,7 +8623,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8636,7 +8636,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -8648,8 +8648,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8662,7 +8662,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8675,7 +8675,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -8687,8 +8687,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8701,7 +8701,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8714,7 +8714,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -8726,8 +8726,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8740,7 +8740,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8753,7 +8753,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -8765,8 +8765,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8779,7 +8779,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8792,7 +8792,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -8804,8 +8804,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8818,7 +8818,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8831,7 +8831,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -8843,8 +8843,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8857,7 +8857,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8870,7 +8870,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -8882,8 +8882,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8896,7 +8896,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8909,7 +8909,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -8921,8 +8921,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8935,7 +8935,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8948,7 +8948,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -8960,8 +8960,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8974,7 +8974,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -8987,7 +8987,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -8999,8 +8999,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9013,7 +9013,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9026,7 +9026,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -9038,8 +9038,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9052,7 +9052,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9065,7 +9065,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -9077,8 +9077,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      1, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -9090,8 +9090,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9104,7 +9104,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -9117,7 +9117,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9130,7 +9130,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -9143,7 +9143,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -9155,8 +9155,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      1, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -9168,8 +9168,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9182,7 +9182,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -9195,7 +9195,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9208,7 +9208,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -9221,7 +9221,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -9233,8 +9233,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      1, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -9246,8 +9246,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9260,7 +9260,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -9273,7 +9273,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9286,7 +9286,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -9299,7 +9299,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -9311,8 +9311,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      1, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -9324,8 +9324,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9338,7 +9338,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -9351,7 +9351,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9364,7 +9364,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -9377,7 +9377,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -9389,8 +9389,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      1, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -9402,8 +9402,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9416,7 +9416,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -9429,7 +9429,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9442,7 +9442,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -9455,7 +9455,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -9467,8 +9467,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      1, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -9480,8 +9480,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9494,7 +9494,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -9507,7 +9507,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9520,7 +9520,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -9533,7 +9533,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -9545,8 +9545,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      1, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -9558,8 +9558,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9572,7 +9572,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -9585,7 +9585,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9598,7 +9598,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -9611,7 +9611,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -9623,8 +9623,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      1, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -9636,8 +9636,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9650,7 +9650,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -9663,7 +9663,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9676,7 +9676,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -9689,7 +9689,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -9701,8 +9701,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9715,7 +9715,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9728,7 +9728,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -9740,8 +9740,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9754,7 +9754,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9767,7 +9767,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -9779,8 +9779,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9793,7 +9793,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9806,7 +9806,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -9818,8 +9818,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9832,7 +9832,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9845,7 +9845,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -9857,8 +9857,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9871,7 +9871,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9884,7 +9884,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -9896,8 +9896,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9910,7 +9910,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9923,7 +9923,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -9935,8 +9935,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9949,7 +9949,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9962,7 +9962,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -9974,8 +9974,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -9988,7 +9988,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10001,7 +10001,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -10013,8 +10013,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10027,7 +10027,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10040,7 +10040,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -10052,8 +10052,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10066,7 +10066,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10079,7 +10079,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -10091,8 +10091,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10105,7 +10105,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10118,7 +10118,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -10130,8 +10130,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10144,7 +10144,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10157,7 +10157,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -10169,8 +10169,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10183,7 +10183,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10196,7 +10196,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -10208,8 +10208,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10222,7 +10222,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10235,7 +10235,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -10247,8 +10247,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10261,7 +10261,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10274,7 +10274,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -10286,8 +10286,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10300,7 +10300,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10312,8 +10312,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -10326,7 +10326,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -10338,8 +10338,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10352,7 +10352,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10364,8 +10364,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10378,7 +10378,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10390,8 +10390,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10404,7 +10404,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10416,8 +10416,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -10430,7 +10430,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -10442,8 +10442,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10456,7 +10456,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10468,8 +10468,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -10482,7 +10482,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -10494,8 +10494,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10508,7 +10508,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10520,8 +10520,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -10534,7 +10534,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -10546,8 +10546,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10560,7 +10560,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10572,8 +10572,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -10586,7 +10586,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -10598,8 +10598,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10612,7 +10612,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10624,8 +10624,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -10638,7 +10638,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -10650,8 +10650,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10664,7 +10664,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10676,8 +10676,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -10690,7 +10690,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -10702,8 +10702,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10716,7 +10716,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10728,8 +10728,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -10742,7 +10742,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -10754,8 +10754,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10768,7 +10768,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -10780,8 +10780,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -10794,7 +10794,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -10806,8 +10806,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -10823,7 +10823,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -10838,8 +10838,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -10855,7 +10855,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -10871,7 +10871,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -10884,7 +10884,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -10897,7 +10897,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -10910,7 +10910,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -10922,8 +10922,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         1, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -10935,8 +10935,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -10949,7 +10949,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -10962,7 +10962,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -10975,7 +10975,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -10988,7 +10988,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -11001,7 +11001,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -11014,7 +11014,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -11027,7 +11027,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -11039,8 +11039,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -11053,7 +11053,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -11065,8 +11065,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -11079,7 +11079,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -11092,7 +11092,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -11102,7 +11102,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -11112,7 +11112,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11124,8 +11124,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -11138,7 +11138,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -11150,8 +11150,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -11164,7 +11164,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -11176,8 +11176,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -11190,7 +11190,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -11202,8 +11202,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -11216,7 +11216,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -11229,7 +11229,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -11242,7 +11242,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11255,7 +11255,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -11268,7 +11268,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11280,8 +11280,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11294,7 +11294,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11306,8 +11306,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -11320,7 +11320,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11333,7 +11333,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -11346,7 +11346,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11358,8 +11358,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11372,7 +11372,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11384,8 +11384,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -11398,7 +11398,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11411,7 +11411,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -11424,7 +11424,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11437,7 +11437,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11450,7 +11450,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11463,7 +11463,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11476,7 +11476,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11489,7 +11489,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11502,7 +11502,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11515,7 +11515,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11528,7 +11528,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11541,7 +11541,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -11553,8 +11553,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11566,8 +11566,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11580,7 +11580,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -11593,7 +11593,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11606,7 +11606,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -11619,7 +11619,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11632,7 +11632,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -11645,7 +11645,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11657,8 +11657,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -11671,7 +11671,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -11683,8 +11683,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -11697,7 +11697,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -11709,8 +11709,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -11723,7 +11723,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -11736,7 +11736,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -11748,8 +11748,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -11762,7 +11762,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -11775,7 +11775,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -11787,8 +11787,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -11801,7 +11801,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -11814,7 +11814,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11830,7 +11830,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11846,7 +11846,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11862,7 +11862,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11878,7 +11878,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11893,8 +11893,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
-      1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11910,7 +11910,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11926,7 +11926,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -11941,8 +11941,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -11955,7 +11955,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -11968,7 +11968,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -11980,8 +11980,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -11994,7 +11994,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12007,7 +12007,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -12019,8 +12019,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12033,7 +12033,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12046,7 +12046,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -12058,8 +12058,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12072,7 +12072,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12085,7 +12085,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -12098,7 +12098,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -12111,7 +12111,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -12124,7 +12124,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -12136,8 +12136,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12150,7 +12150,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12163,7 +12163,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -12176,7 +12176,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -12186,7 +12186,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -12196,7 +12196,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -12206,7 +12206,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -12216,7 +12216,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -12228,8 +12228,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12242,7 +12242,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12255,7 +12255,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -12271,7 +12271,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12284,7 +12284,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12296,8 +12296,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -12310,7 +12310,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -12323,7 +12323,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12336,7 +12336,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12348,8 +12348,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -12362,7 +12362,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -12375,7 +12375,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -12384,8 +12384,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -12401,7 +12401,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -12417,7 +12417,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12430,7 +12430,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12442,8 +12442,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -12456,7 +12456,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -12469,7 +12469,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -12479,7 +12479,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -12488,8 +12488,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12502,7 +12502,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12514,8 +12514,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -12528,7 +12528,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -12541,7 +12541,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -12554,7 +12554,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -12566,8 +12566,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12580,7 +12580,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12592,8 +12592,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12606,7 +12606,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12618,8 +12618,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12632,7 +12632,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12644,8 +12644,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12658,7 +12658,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12670,8 +12670,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -12684,7 +12684,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -12696,8 +12696,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12710,7 +12710,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12722,8 +12722,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12736,7 +12736,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12748,8 +12748,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12762,7 +12762,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12774,8 +12774,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -12788,7 +12788,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -12800,8 +12800,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12814,7 +12814,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12826,8 +12826,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -12840,7 +12840,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -12852,8 +12852,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12866,7 +12866,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12878,8 +12878,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -12892,7 +12892,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -12904,8 +12904,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12918,7 +12918,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12930,8 +12930,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -12944,7 +12944,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -12956,8 +12956,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12970,7 +12970,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -12982,8 +12982,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -12996,7 +12996,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -13008,8 +13008,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -13022,7 +13022,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -13034,8 +13034,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -13048,7 +13048,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -13060,8 +13060,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -13074,7 +13074,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -13086,8 +13086,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -13100,7 +13100,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -13112,8 +13112,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -13126,7 +13126,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -13138,8 +13138,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -13152,7 +13152,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -13164,8 +13164,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -13181,7 +13181,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -13197,7 +13197,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -13207,7 +13207,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -13219,8 +13219,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -13236,7 +13236,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -13252,7 +13252,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -13265,7 +13265,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -13278,7 +13278,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -13290,8 +13290,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         1, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -13303,8 +13303,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -13317,7 +13317,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -13330,7 +13330,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -13342,8 +13342,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -13356,7 +13356,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -13368,8 +13368,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -13382,7 +13382,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -13394,8 +13394,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -13408,7 +13408,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -13420,8 +13420,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -13434,7 +13434,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -13446,8 +13446,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -13460,7 +13460,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -13472,8 +13472,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -13486,7 +13486,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -13499,7 +13499,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -13512,7 +13512,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -13525,7 +13525,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -13538,7 +13538,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -13550,8 +13550,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -13564,7 +13564,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -13577,7 +13577,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -13590,7 +13590,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -13602,8 +13602,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -13616,7 +13616,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -13629,7 +13629,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -13642,7 +13642,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -13655,7 +13655,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -13668,7 +13668,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -13681,7 +13681,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -13694,7 +13694,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -13707,7 +13707,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -13717,7 +13717,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -13730,7 +13730,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -13743,7 +13743,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -13755,8 +13755,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -13768,8 +13768,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -13782,7 +13782,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -13795,7 +13795,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -13808,7 +13808,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -13821,7 +13821,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -13834,7 +13834,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -13847,7 +13847,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -13859,8 +13859,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -13873,7 +13873,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -13885,8 +13885,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -13899,7 +13899,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -13911,8 +13911,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -13925,7 +13925,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -13937,8 +13937,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -13954,7 +13954,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -13970,7 +13970,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -13983,7 +13983,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -13995,8 +13995,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -14009,7 +14009,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -14021,8 +14021,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14035,7 +14035,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14047,8 +14047,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -14061,7 +14061,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -14074,7 +14074,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -14087,7 +14087,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -14099,8 +14099,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14113,7 +14113,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14125,8 +14125,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14139,7 +14139,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14151,8 +14151,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14165,7 +14165,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14178,7 +14178,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -14191,7 +14191,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -14204,7 +14204,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14217,7 +14217,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14230,7 +14230,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14243,7 +14243,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14256,7 +14256,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14269,7 +14269,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14282,7 +14282,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14295,7 +14295,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -14308,7 +14308,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -14321,7 +14321,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14334,7 +14334,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14347,7 +14347,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -14360,7 +14360,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -14372,8 +14372,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -14386,7 +14386,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -14398,8 +14398,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -14412,7 +14412,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -14425,7 +14425,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14438,7 +14438,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -14451,7 +14451,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -14464,7 +14464,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14477,7 +14477,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14490,7 +14490,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14503,7 +14503,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14516,7 +14516,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -14529,7 +14529,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -14542,7 +14542,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14555,7 +14555,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -14568,7 +14568,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14581,7 +14581,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -14594,7 +14594,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14607,7 +14607,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -14620,7 +14620,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14633,7 +14633,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -14646,7 +14646,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -14659,7 +14659,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -14671,8 +14671,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14685,7 +14685,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14698,7 +14698,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -14711,7 +14711,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -14727,7 +14727,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -14743,7 +14743,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -14759,7 +14759,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -14775,7 +14775,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -14791,7 +14791,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -14806,8 +14806,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      1, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -14820,7 +14820,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -14832,8 +14832,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      1, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -14846,7 +14846,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -14858,8 +14858,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14872,7 +14872,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14884,8 +14884,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14898,7 +14898,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14910,8 +14910,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14924,7 +14924,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14936,8 +14936,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14950,7 +14950,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -14963,7 +14963,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } } } },
@@ -14973,7 +14973,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -14983,7 +14983,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -14993,7 +14993,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -15002,8 +15002,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15016,7 +15016,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15028,8 +15028,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15042,7 +15042,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15054,8 +15054,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15068,7 +15068,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15080,8 +15080,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15094,7 +15094,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15107,7 +15107,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15120,7 +15120,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15133,7 +15133,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -15143,7 +15143,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -15159,7 +15159,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -15175,7 +15175,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -15188,7 +15188,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -15201,7 +15201,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15214,7 +15214,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15227,7 +15227,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15240,7 +15240,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15253,7 +15253,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -15263,7 +15263,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -15276,7 +15276,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -15289,7 +15289,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -15299,7 +15299,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -15309,7 +15309,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -15319,7 +15319,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -15329,7 +15329,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -15339,7 +15339,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -15349,7 +15349,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -15362,7 +15362,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -15375,7 +15375,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -15388,7 +15388,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -15401,7 +15401,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -15411,7 +15411,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -15421,7 +15421,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -15431,7 +15431,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15444,7 +15444,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15457,7 +15457,7 @@ const insn_template i386_optab[] =
         1, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15470,7 +15470,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15482,8 +15482,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15496,7 +15496,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15509,7 +15509,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -15521,8 +15521,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15535,7 +15535,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15548,7 +15548,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -15560,8 +15560,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15574,7 +15574,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15587,7 +15587,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -15599,8 +15599,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15613,7 +15613,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15626,7 +15626,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -15638,8 +15638,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15652,7 +15652,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15665,7 +15665,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -15677,8 +15677,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15691,7 +15691,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15704,7 +15704,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -15716,8 +15716,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15730,7 +15730,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15743,7 +15743,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -15755,8 +15755,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15769,7 +15769,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15782,7 +15782,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -15794,8 +15794,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15808,7 +15808,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15821,7 +15821,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -15833,8 +15833,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15847,7 +15847,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15860,7 +15860,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -15872,8 +15872,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15886,7 +15886,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15899,7 +15899,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -15911,8 +15911,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15925,7 +15925,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -15938,7 +15938,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -15950,8 +15950,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -15967,7 +15967,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -15983,7 +15983,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -15999,7 +15999,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16012,7 +16012,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16025,7 +16025,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -16038,7 +16038,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16051,7 +16051,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16064,7 +16064,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -16077,7 +16077,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16090,7 +16090,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16103,7 +16103,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -16115,8 +16115,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16132,7 +16132,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16147,8 +16147,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16164,7 +16164,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16179,8 +16179,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16195,8 +16195,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16209,7 +16209,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16225,7 +16225,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16237,8 +16237,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16253,8 +16253,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16267,7 +16267,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16283,7 +16283,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16295,8 +16295,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16312,7 +16312,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16327,8 +16327,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16344,7 +16344,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16360,7 +16360,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16376,7 +16376,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16391,8 +16391,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16408,7 +16408,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16424,7 +16424,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16437,7 +16437,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16449,8 +16449,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16466,7 +16466,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16481,8 +16481,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16495,7 +16495,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16507,8 +16507,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16523,8 +16523,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16537,7 +16537,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16553,7 +16553,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16565,8 +16565,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16582,7 +16582,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16597,8 +16597,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16611,7 +16611,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16624,7 +16624,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16640,7 +16640,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16656,7 +16656,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16672,7 +16672,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16688,7 +16688,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16704,7 +16704,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16720,7 +16720,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16733,7 +16733,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16745,8 +16745,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16762,7 +16762,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16777,8 +16777,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16794,7 +16794,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16809,8 +16809,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16826,7 +16826,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -16841,8 +16841,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16855,7 +16855,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16867,8 +16867,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16881,7 +16881,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16893,8 +16893,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16907,7 +16907,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16919,8 +16919,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16933,7 +16933,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16945,8 +16945,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16959,7 +16959,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16971,8 +16971,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16985,7 +16985,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -16997,8 +16997,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -17011,7 +17011,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -17023,8 +17023,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -17037,7 +17037,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -17050,7 +17050,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -17063,7 +17063,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -17076,7 +17076,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -17089,7 +17089,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -17102,7 +17102,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -17115,7 +17115,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -17128,7 +17128,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -17141,7 +17141,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -17154,7 +17154,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -17167,7 +17167,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -17180,7 +17180,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -17193,7 +17193,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -17206,7 +17206,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -17219,7 +17219,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -17232,7 +17232,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -17245,7 +17245,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -17258,7 +17258,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -17271,7 +17271,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -17284,7 +17284,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -17297,7 +17297,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -17310,7 +17310,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -17323,7 +17323,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -17336,7 +17336,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -17349,7 +17349,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -17361,8 +17361,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -17375,7 +17375,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -17387,8 +17387,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -17401,7 +17401,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -17414,7 +17414,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -17427,7 +17427,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -17440,7 +17440,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -17456,7 +17456,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -17472,7 +17472,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -17488,7 +17488,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -17503,8 +17503,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -17520,7 +17520,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -17535,8 +17535,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -17552,7 +17552,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -17567,8 +17567,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -17581,7 +17581,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -17594,7 +17594,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -17610,7 +17610,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -17626,7 +17626,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -17642,7 +17642,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -17658,7 +17658,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -17674,7 +17674,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -17690,7 +17690,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -17706,7 +17706,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -17722,7 +17722,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -17735,7 +17735,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -17748,7 +17748,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -17761,7 +17761,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -17774,7 +17774,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -17784,7 +17784,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -17794,7 +17794,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -17804,7 +17804,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -17813,8 +17813,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -17827,7 +17827,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -17839,8 +17839,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -17853,7 +17853,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -17865,8 +17865,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -17879,7 +17879,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -17891,8 +17891,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -17905,7 +17905,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -17918,7 +17918,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -17931,7 +17931,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -17944,7 +17944,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -17960,7 +17960,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -17975,8 +17975,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -17992,7 +17992,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -18007,8 +18007,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -18021,7 +18021,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -18033,8 +18033,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -18047,7 +18047,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -18059,8 +18059,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -18073,7 +18073,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -18085,8 +18085,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -18099,7 +18099,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -18111,8 +18111,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -18127,8 +18127,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -18143,8 +18143,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -18159,8 +18159,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -18175,8 +18175,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -18191,8 +18191,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -18207,8 +18207,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -18223,8 +18223,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -18239,8 +18239,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -18255,8 +18255,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -18271,8 +18271,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -18287,8 +18287,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -18303,8 +18303,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -18319,8 +18319,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -18335,8 +18335,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -18351,8 +18351,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -18367,8 +18367,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -18383,8 +18383,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -18399,8 +18399,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -18418,8 +18418,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -18437,8 +18437,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -18456,8 +18456,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -18475,8 +18475,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -18494,8 +18494,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -18513,8 +18513,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -18532,8 +18532,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -18551,8 +18551,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -18564,8 +18564,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -18578,7 +18578,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -18590,8 +18590,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -18603,8 +18603,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -18619,8 +18619,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -18635,8 +18635,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -18651,8 +18651,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -18667,8 +18667,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -18683,8 +18683,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -18699,8 +18699,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -18715,8 +18715,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -18731,8 +18731,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -18747,8 +18747,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -18763,8 +18763,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -18779,8 +18779,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -18795,8 +18795,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -18811,8 +18811,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -18827,8 +18827,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -18843,8 +18843,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -18859,8 +18859,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -18875,8 +18875,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -18891,8 +18891,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -18907,8 +18907,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -18923,8 +18923,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -18939,8 +18939,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -18955,8 +18955,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -18971,8 +18971,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -18987,8 +18987,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -19003,8 +19003,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -19019,8 +19019,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -19035,8 +19035,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -19051,8 +19051,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -19067,8 +19067,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -19083,8 +19083,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -19099,8 +19099,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -19115,8 +19115,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -19131,8 +19131,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -19147,8 +19147,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -19163,8 +19163,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -19179,8 +19179,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -19195,8 +19195,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -19211,8 +19211,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -19227,8 +19227,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -19243,8 +19243,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -19259,8 +19259,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -19275,8 +19275,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -19291,8 +19291,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -19307,8 +19307,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -19323,8 +19323,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -19339,8 +19339,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -19355,8 +19355,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -19371,8 +19371,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -19387,8 +19387,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -19403,8 +19403,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -19419,8 +19419,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -19435,8 +19435,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -19451,8 +19451,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -19467,8 +19467,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -19483,8 +19483,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -19499,8 +19499,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -19515,8 +19515,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -19531,8 +19531,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -19547,8 +19547,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -19563,8 +19563,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -19579,8 +19579,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -19595,8 +19595,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -19611,8 +19611,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -19627,8 +19627,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -19643,8 +19643,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -19659,8 +19659,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -19675,8 +19675,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -19691,8 +19691,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -19707,8 +19707,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -19723,8 +19723,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -19739,8 +19739,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -19755,8 +19755,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -19771,8 +19771,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -19787,8 +19787,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -19803,8 +19803,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -19819,8 +19819,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -19835,8 +19835,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -19851,8 +19851,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -19867,8 +19867,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -19883,8 +19883,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -19899,8 +19899,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -19915,8 +19915,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -19931,8 +19931,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -19947,8 +19947,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -19963,8 +19963,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -19979,8 +19979,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -19995,8 +19995,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -20011,8 +20011,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -20027,8 +20027,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -20043,8 +20043,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -20059,8 +20059,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -20075,8 +20075,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -20091,8 +20091,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -20107,8 +20107,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -20123,8 +20123,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -20139,8 +20139,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -20155,8 +20155,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -20171,8 +20171,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -20187,8 +20187,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -20203,8 +20203,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -20219,8 +20219,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -20235,8 +20235,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -20251,8 +20251,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -20267,8 +20267,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -20283,8 +20283,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -20299,8 +20299,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -20315,8 +20315,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -20331,8 +20331,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -20347,8 +20347,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -20363,8 +20363,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -20379,8 +20379,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -20395,8 +20395,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -20411,8 +20411,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -20427,8 +20427,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -20443,8 +20443,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -20459,8 +20459,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -20475,8 +20475,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -20491,8 +20491,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -20507,8 +20507,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -20523,8 +20523,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -20539,8 +20539,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -20555,8 +20555,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -20571,8 +20571,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -20587,8 +20587,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -20603,8 +20603,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -20619,8 +20619,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -20635,8 +20635,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -20651,8 +20651,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -20667,8 +20667,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -20683,8 +20683,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -20699,8 +20699,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -20715,8 +20715,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -20731,8 +20731,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -20747,8 +20747,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -20763,8 +20763,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -20779,8 +20779,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -20795,8 +20795,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -20811,8 +20811,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -20827,8 +20827,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -20843,8 +20843,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -20859,8 +20859,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -20875,8 +20875,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -20891,8 +20891,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -20907,8 +20907,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -20923,8 +20923,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -20939,8 +20939,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -20955,8 +20955,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -20971,8 +20971,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -20987,8 +20987,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -21003,8 +21003,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -21019,8 +21019,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -21035,8 +21035,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -21051,8 +21051,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -21067,8 +21067,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -21083,8 +21083,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -21099,8 +21099,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -21115,8 +21115,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -21131,8 +21131,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -21147,8 +21147,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -21163,8 +21163,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -21179,8 +21179,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -21195,8 +21195,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -21211,8 +21211,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -21227,8 +21227,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -21243,8 +21243,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -21259,8 +21259,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -21275,8 +21275,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -21291,8 +21291,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -21310,8 +21310,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -21329,8 +21329,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -21348,8 +21348,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -21367,8 +21367,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -21386,8 +21386,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -21405,8 +21405,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -21421,8 +21421,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -21437,8 +21437,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -21453,8 +21453,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -21469,8 +21469,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -21485,8 +21485,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -21501,8 +21501,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -21517,8 +21517,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -21533,8 +21533,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -21549,8 +21549,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -21565,8 +21565,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -21581,8 +21581,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -21597,8 +21597,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -21613,8 +21613,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -21629,8 +21629,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -21645,8 +21645,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -21661,8 +21661,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -21677,8 +21677,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -21693,8 +21693,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -21709,8 +21709,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -21725,8 +21725,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -21741,8 +21741,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -21757,8 +21757,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -21773,8 +21773,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -21790,7 +21790,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -21803,7 +21803,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -21816,7 +21816,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -21828,8 +21828,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -21842,7 +21842,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -21854,8 +21854,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -21868,7 +21868,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -21881,7 +21881,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 0, 0, 0 } },
@@ -21893,8 +21893,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -21906,8 +21906,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 0, 0, 0 } },
@@ -21920,7 +21920,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -21932,8 +21932,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -21946,7 +21946,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -21959,7 +21959,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 0, 0, 0 } },
@@ -21971,8 +21971,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -21984,8 +21984,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 0, 0, 0 } },
@@ -21998,7 +21998,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -22010,8 +22010,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -22024,7 +22024,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -22036,8 +22036,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -22050,7 +22050,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -22062,8 +22062,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -22076,7 +22076,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -22088,8 +22088,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -22104,8 +22104,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         1, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -22120,8 +22120,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -22136,8 +22136,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         1, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -22152,8 +22152,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -22168,8 +22168,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -22185,7 +22185,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -22198,7 +22198,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -22211,7 +22211,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 0, 0, 0 } },
@@ -22223,8 +22223,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -22236,8 +22236,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 0, 0, 0 } },
@@ -22250,7 +22250,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -22262,8 +22262,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -22276,7 +22276,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -22288,8 +22288,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -22302,7 +22302,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -22315,7 +22315,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -22327,8 +22327,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -22343,8 +22343,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -22359,8 +22359,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -22375,8 +22375,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -22391,8 +22391,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -22407,8 +22407,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -22423,8 +22423,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -22442,8 +22442,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -22461,8 +22461,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -22480,8 +22480,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -22497,7 +22497,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -22512,8 +22512,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -22528,8 +22528,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -22544,8 +22544,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -22560,8 +22560,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -22576,8 +22576,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -22592,8 +22592,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -22608,8 +22608,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -22624,8 +22624,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -22640,8 +22640,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -22659,8 +22659,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -22679,7 +22679,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -22691,8 +22691,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -22705,7 +22705,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -22715,7 +22715,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -22727,8 +22727,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -22743,8 +22743,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -22759,8 +22759,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -22775,8 +22775,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -22791,8 +22791,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -22807,8 +22807,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -22823,8 +22823,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -22839,8 +22839,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -22855,8 +22855,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -22871,8 +22871,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -22887,8 +22887,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -22903,8 +22903,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -22919,8 +22919,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -22935,8 +22935,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -22951,8 +22951,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -22967,8 +22967,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -22983,8 +22983,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -22999,8 +22999,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -23015,8 +23015,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -23031,8 +23031,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -23048,7 +23048,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -23061,7 +23061,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23073,8 +23073,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -23086,8 +23086,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23100,7 +23100,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -23113,7 +23113,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23125,8 +23125,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -23138,8 +23138,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23152,7 +23152,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -23165,7 +23165,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 0, 0, 0 } },
@@ -23178,7 +23178,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23191,7 +23191,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23204,7 +23204,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -23216,8 +23216,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -23230,7 +23230,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -23243,7 +23243,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23255,8 +23255,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -23268,8 +23268,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23282,7 +23282,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -23295,7 +23295,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23307,8 +23307,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -23320,8 +23320,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23333,8 +23333,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23349,8 +23349,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -23366,7 +23366,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23378,8 +23378,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -23395,7 +23395,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23407,8 +23407,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23423,8 +23423,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -23440,7 +23440,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23452,8 +23452,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -23469,7 +23469,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23482,7 +23482,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23494,8 +23494,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
-      1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23508,7 +23508,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23520,8 +23520,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
-      1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23534,7 +23534,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23546,8 +23546,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23560,7 +23560,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -23573,7 +23573,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23585,8 +23585,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23599,7 +23599,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23611,8 +23611,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23625,7 +23625,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -23638,7 +23638,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23651,7 +23651,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -23664,7 +23664,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23677,7 +23677,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23690,7 +23690,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -23702,8 +23702,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23718,8 +23718,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23735,7 +23735,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -23747,8 +23747,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -23761,7 +23761,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -23773,8 +23773,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -23787,7 +23787,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23800,7 +23800,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -23812,8 +23812,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23828,8 +23828,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23845,7 +23845,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -23858,7 +23858,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23870,8 +23870,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -23883,8 +23883,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23897,7 +23897,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -23910,7 +23910,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23922,8 +23922,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -23935,8 +23935,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23948,8 +23948,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -23967,8 +23967,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -23983,8 +23983,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -23999,8 +23999,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24015,8 +24015,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -24031,8 +24031,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -24047,8 +24047,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -24063,8 +24063,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24079,8 +24079,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -24095,8 +24095,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24111,8 +24111,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -24128,7 +24128,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24141,7 +24141,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24154,7 +24154,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24166,8 +24166,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24182,8 +24182,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24198,8 +24198,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24214,8 +24214,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24230,8 +24230,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24246,8 +24246,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24262,8 +24262,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24278,8 +24278,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24294,8 +24294,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24310,8 +24310,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24326,8 +24326,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24342,8 +24342,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24358,8 +24358,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -24377,8 +24377,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24393,8 +24393,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24409,8 +24409,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24425,8 +24425,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24441,8 +24441,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -24460,8 +24460,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -24479,8 +24479,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24495,8 +24495,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24511,8 +24511,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24527,8 +24527,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24544,7 +24544,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -24560,7 +24560,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -24575,8 +24575,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24591,8 +24591,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24607,8 +24607,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24623,8 +24623,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24640,7 +24640,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -24656,7 +24656,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -24671,8 +24671,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -24690,8 +24690,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24706,8 +24706,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -24723,7 +24723,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -24738,8 +24738,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -24754,8 +24754,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24770,8 +24770,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -24787,7 +24787,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -24802,8 +24802,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -24819,7 +24819,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -24835,7 +24835,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -24851,7 +24851,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -24867,7 +24867,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -24883,7 +24883,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -24898,8 +24898,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24914,8 +24914,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24930,8 +24930,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24947,7 +24947,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24959,8 +24959,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24975,8 +24975,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -24991,8 +24991,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25007,8 +25007,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -25026,8 +25026,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -25045,8 +25045,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -25064,8 +25064,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
-      1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -25083,8 +25083,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25099,8 +25099,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25115,8 +25115,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25131,8 +25131,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25147,8 +25147,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25163,8 +25163,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25179,8 +25179,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25195,8 +25195,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25211,8 +25211,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25227,8 +25227,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25243,8 +25243,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25259,8 +25259,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25275,8 +25275,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25291,8 +25291,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25308,7 +25308,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -25321,7 +25321,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -25334,7 +25334,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -25347,7 +25347,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -25360,7 +25360,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -25373,7 +25373,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -25386,7 +25386,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -25399,7 +25399,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -25412,7 +25412,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -25425,7 +25425,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -25438,7 +25438,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -25451,7 +25451,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -25464,7 +25464,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -25476,8 +25476,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25492,8 +25492,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25508,8 +25508,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25524,8 +25524,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25540,8 +25540,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25556,8 +25556,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25572,8 +25572,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25588,8 +25588,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25604,8 +25604,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25620,8 +25620,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25637,7 +25637,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -25653,7 +25653,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -25669,7 +25669,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -25684,8 +25684,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25700,8 +25700,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25716,8 +25716,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25732,8 +25732,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -25748,8 +25748,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25764,8 +25764,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -25780,8 +25780,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -25796,8 +25796,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25812,8 +25812,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -25828,8 +25828,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25844,8 +25844,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -25860,8 +25860,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25876,8 +25876,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -25892,8 +25892,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25908,8 +25908,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -25924,8 +25924,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25940,8 +25940,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -25956,8 +25956,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -25972,8 +25972,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -25988,8 +25988,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -26004,8 +26004,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26020,8 +26020,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26036,8 +26036,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26052,8 +26052,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26068,8 +26068,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26084,8 +26084,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26100,8 +26100,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26116,8 +26116,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26132,8 +26132,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26149,7 +26149,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26161,8 +26161,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -26174,8 +26174,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26190,8 +26190,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26206,8 +26206,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26222,8 +26222,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26238,8 +26238,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26254,8 +26254,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26270,8 +26270,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26286,8 +26286,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26302,8 +26302,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26319,7 +26319,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26331,8 +26331,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -26344,8 +26344,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -26361,7 +26361,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -26376,8 +26376,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -26393,7 +26393,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -26408,8 +26408,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -26424,8 +26424,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -26443,8 +26443,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -26463,7 +26463,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26475,8 +26475,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -26488,8 +26488,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -26504,8 +26504,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -26523,8 +26523,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -26542,8 +26542,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -26561,8 +26561,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -26581,7 +26581,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26593,8 +26593,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -26607,7 +26607,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26619,8 +26619,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -26632,8 +26632,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -26648,8 +26648,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -26665,7 +26665,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -26674,8 +26674,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26690,8 +26690,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -26706,8 +26706,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26722,8 +26722,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -26738,8 +26738,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -26754,8 +26754,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -26771,7 +26771,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26783,8 +26783,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -26797,7 +26797,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26809,8 +26809,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -26823,7 +26823,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -26836,7 +26836,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -26848,8 +26848,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26864,8 +26864,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -26880,8 +26880,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26896,8 +26896,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -26912,8 +26912,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26928,8 +26928,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -26944,8 +26944,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26960,8 +26960,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -26976,8 +26976,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -26992,8 +26992,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -27008,8 +27008,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27024,8 +27024,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -27040,8 +27040,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -27051,7 +27051,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -27060,8 +27060,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27076,8 +27076,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27092,8 +27092,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27108,8 +27108,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27125,7 +27125,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27138,7 +27138,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -27153,8 +27153,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -27172,8 +27172,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27188,8 +27188,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27204,8 +27204,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27220,8 +27220,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 
-      0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 
+      0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27236,8 +27236,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27252,8 +27252,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -27268,8 +27268,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27284,8 +27284,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -27300,8 +27300,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27316,8 +27316,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -27332,8 +27332,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27348,8 +27348,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -27364,8 +27364,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27380,8 +27380,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -27396,8 +27396,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27412,8 +27412,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -27428,8 +27428,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -27444,8 +27444,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -27460,8 +27460,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -27476,8 +27476,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -27492,8 +27492,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -27508,8 +27508,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -27524,8 +27524,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27540,8 +27540,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -27556,8 +27556,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27572,8 +27572,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -27588,8 +27588,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27604,8 +27604,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -27620,8 +27620,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27636,8 +27636,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -27652,8 +27652,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27668,8 +27668,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -27684,8 +27684,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27700,8 +27700,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -27716,8 +27716,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27732,8 +27732,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -27748,8 +27748,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27764,8 +27764,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -27780,8 +27780,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27796,8 +27796,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -27812,8 +27812,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27828,8 +27828,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -27844,8 +27844,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27860,8 +27860,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -27876,8 +27876,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27892,8 +27892,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -27908,8 +27908,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27924,8 +27924,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -27940,8 +27940,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27956,8 +27956,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -27972,8 +27972,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -27988,8 +27988,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -28004,8 +28004,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -28020,8 +28020,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -28036,8 +28036,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -28052,8 +28052,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -28068,8 +28068,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -28084,8 +28084,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -28100,8 +28100,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -28116,8 +28116,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -28132,8 +28132,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -28148,8 +28148,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -28164,8 +28164,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -28180,8 +28180,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -28196,8 +28196,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -28212,8 +28212,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -28228,8 +28228,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -28244,8 +28244,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -28260,8 +28260,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -28276,8 +28276,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -28292,8 +28292,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -28308,8 +28308,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -28324,8 +28324,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -28340,8 +28340,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -28356,8 +28356,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -28372,8 +28372,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -28388,8 +28388,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -28404,8 +28404,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -28420,8 +28420,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -28436,8 +28436,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -28452,8 +28452,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -28468,8 +28468,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -28484,8 +28484,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -28500,8 +28500,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -28516,8 +28516,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -28532,8 +28532,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -28548,8 +28548,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -28564,8 +28564,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -28580,8 +28580,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -28596,8 +28596,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -28612,8 +28612,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -28628,8 +28628,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -28644,8 +28644,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -28660,8 +28660,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -28676,8 +28676,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -28692,8 +28692,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -28708,8 +28708,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -28724,8 +28724,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -28740,8 +28740,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -28756,8 +28756,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -28772,8 +28772,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -28791,8 +28791,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -28810,8 +28810,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -28829,8 +28829,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -28848,8 +28848,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -28867,8 +28867,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -28886,8 +28886,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -28905,8 +28905,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -28924,8 +28924,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -28943,8 +28943,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -28962,8 +28962,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -28981,8 +28981,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -29000,8 +29000,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -29019,8 +29019,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -29038,8 +29038,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -29057,8 +29057,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -29076,8 +29076,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -29095,8 +29095,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -29114,8 +29114,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -29133,8 +29133,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -29152,8 +29152,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -29171,8 +29171,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -29190,8 +29190,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -29209,8 +29209,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -29228,8 +29228,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -29247,8 +29247,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -29266,8 +29266,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -29285,8 +29285,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -29304,8 +29304,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -29323,8 +29323,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -29342,8 +29342,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -29361,8 +29361,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -29380,8 +29380,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -29399,8 +29399,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -29418,8 +29418,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -29437,8 +29437,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -29456,8 +29456,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -29475,8 +29475,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -29494,8 +29494,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -29513,8 +29513,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -29532,8 +29532,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -29551,8 +29551,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -29570,8 +29570,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -29589,8 +29589,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -29608,8 +29608,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -29627,8 +29627,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -29646,8 +29646,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -29665,8 +29665,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -29684,8 +29684,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -29703,8 +29703,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -29722,8 +29722,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -29741,8 +29741,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -29760,8 +29760,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -29779,8 +29779,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -29798,8 +29798,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -29817,8 +29817,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -29836,8 +29836,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 0, 1, 0, 0 } },
@@ -29855,8 +29855,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -29874,8 +29874,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 1, 1, 0, 0 } },
@@ -29893,8 +29893,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -29912,8 +29912,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -29931,8 +29931,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -29950,8 +29950,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
          0, 0, 1, 0, 0 } },
@@ -29969,8 +29969,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
-      0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 
+      1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -29989,7 +29989,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -29999,7 +29999,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 1, 0, 0 } } } },
@@ -30009,7 +30009,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30019,7 +30019,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -30032,7 +30032,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -30045,7 +30045,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -30058,7 +30058,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -30071,7 +30071,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -30084,7 +30084,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -30097,7 +30097,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -30110,7 +30110,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -30123,7 +30123,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -30136,7 +30136,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -30149,7 +30149,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -30162,7 +30162,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -30175,7 +30175,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -30188,7 +30188,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -30201,7 +30201,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -30214,7 +30214,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -30227,7 +30227,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -30240,7 +30240,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -30253,7 +30253,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -30266,7 +30266,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -30279,7 +30279,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -30292,7 +30292,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -30305,7 +30305,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -30318,7 +30318,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -30331,7 +30331,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30341,7 +30341,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30351,7 +30351,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30361,7 +30361,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30371,7 +30371,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30381,7 +30381,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30391,7 +30391,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30401,7 +30401,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30411,7 +30411,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -30424,7 +30424,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30434,7 +30434,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30444,7 +30444,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30454,7 +30454,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30464,7 +30464,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30474,7 +30474,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30484,7 +30484,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30494,7 +30494,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30504,7 +30504,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30514,7 +30514,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30524,7 +30524,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -30537,7 +30537,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -30550,7 +30550,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -30566,7 +30566,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -30579,7 +30579,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -30592,7 +30592,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } },
@@ -30611,7 +30611,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -30624,7 +30624,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 
       1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 
          0, 0, 1, 0, 0 } },
@@ -30637,7 +30637,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30647,7 +30647,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30657,7 +30657,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30667,7 +30667,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30677,7 +30677,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30687,7 +30687,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30697,7 +30697,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30707,7 +30707,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30717,7 +30717,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30727,7 +30727,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30737,7 +30737,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30747,7 +30747,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30757,7 +30757,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30767,7 +30767,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30777,7 +30777,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30787,7 +30787,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 
       1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
@@ -30797,7 +30797,7 @@ const insn_template i386_optab[] =
         0, 0 } },
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } }

diff --git a/opcodes/po/es.po b/opcodes/po/es.po
index 40bea5c..f527d99 100644 (file)
--- a/opcodes/po/es.po
+++ b/opcodes/po/es.po
@@ -1,14 +1,14 @@
-# Mensajes en español para opcodes-2.18.90.
+# Mensajes en español para opcodes-2.19.90.
 # Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
 # This file is distributed under the same license as the binutils package.
 # Cristian Othón Martínez Vera <cfuga@itam.mx>, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009.
 #
 msgid ""
 msgstr ""
-"Project-Id-Version: opcodes 2.18.90\n"
+"Project-Id-Version: opcodes 2.19.90\n"
 "Report-Msgid-Bugs-To: bug-binutils@gnu.org\n"
-"POT-Creation-Date: 2008-09-09 15:56+0930\n"
-"PO-Revision-Date: 2009-03-03 21:46-0600\n"
+"POT-Creation-Date: 2009-09-07 14:08+0200\n"
+"PO-Revision-Date: 2009-09-17 17:13-0500\n"
 "Last-Translator: Cristian Othón Martínez Vera <cfuga@itam.mx>\n"
 "Language-Team: Spanish <es@li.org>\n"
 "MIME-Version: 1.0\n"
@@ -91,7 +91,7 @@ msgstr "opciones de salto, pero no hay una direcci
 
 #: arc-opc.c:949
 msgid "flag bits of jump address limm lost"
-msgstr "bits bandera de dirección de salto limm perdidos"
+msgstr "se perdieron los bits de opción de dirección de salto limm"
 
 #: arc-opc.c:952
 msgid "attempt to set HR bits"
@@ -109,23 +109,23 @@ msgstr "la direcci
 msgid "must specify .jd or no nullify suffix"
 msgstr "se debe especificar un sufijo .jd o no nullify"
 
-#: arm-dis.c:1808
+#: arm-dis.c:1915
 msgid "<illegal precision>"
 msgstr "<precisión ilegal>"
 
 #. XXX - should break 'option' at following delimiter.
-#: arm-dis.c:3818
+#: arm-dis.c:4014
 #, c-format
 msgid "Unrecognised register name set: %s\n"
 msgstr "No se reconoce el conjunto de nombres de registro: %s\n"
 
 #. XXX - should break 'option' at following delimiter.
-#: arm-dis.c:3826
+#: arm-dis.c:4022
 #, c-format
 msgid "Unrecognised disassembler option: %s\n"
 msgstr "No se reconoce la opción de desensamblador: %s\n"
 
-#: arm-dis.c:4238
+#: arm-dis.c:4519
 #, c-format
 msgid ""
 "\n"
@@ -152,8 +152,9 @@ msgid "unknown constraint `%c'"
 msgstr "restricción `%c' desconocida"
 
 #: cgen-asm.c:336 fr30-ibld.c:200 frv-ibld.c:200 ip2k-ibld.c:200
-#: iq2000-ibld.c:200 m32c-ibld.c:200 m32r-ibld.c:200 mep-ibld.c:200
-#: mt-ibld.c:200 openrisc-ibld.c:200 xc16x-ibld.c:200 xstormy16-ibld.c:200
+#: iq2000-ibld.c:200 lm32-ibld.c:200 m32c-ibld.c:200 m32r-ibld.c:200
+#: mep-ibld.c:200 mt-ibld.c:200 openrisc-ibld.c:200 xc16x-ibld.c:200
+#: xstormy16-ibld.c:200
 #, c-format
 msgid "operand out of range (%ld not between %ld and %ld)"
 msgstr "operando fuera de rango (%ld no está entre %ld y %ld)"
@@ -196,14 +197,14 @@ msgid "Register list is not valid"
 msgstr "La lista de registros no es válida"
 
 #: fr30-asm.c:310 frv-asm.c:1263 ip2k-asm.c:511 iq2000-asm.c:459
-#: m32c-asm.c:1589 m32r-asm.c:328 mep-asm.c:1001 mt-asm.c:595
+#: lm32-asm.c:349 m32c-asm.c:1589 m32r-asm.c:328 mep-asm.c:1287 mt-asm.c:595
 #: openrisc-asm.c:241 xc16x-asm.c:376 xstormy16-asm.c:276
 #, c-format
 msgid "Unrecognized field %d while parsing.\n"
-msgstr "No se reconoció el campo %d durante la decodificación.\n"
+msgstr "No se reconoció el campo %d al decodificar.\n"
 
 #: fr30-asm.c:361 frv-asm.c:1314 ip2k-asm.c:562 iq2000-asm.c:510
-#: m32c-asm.c:1640 m32r-asm.c:379 mep-asm.c:1052 mt-asm.c:646
+#: lm32-asm.c:400 m32c-asm.c:1640 m32r-asm.c:379 mep-asm.c:1338 mt-asm.c:646
 #: openrisc-asm.c:292 xc16x-asm.c:427 xstormy16-asm.c:327
 msgid "missing mnemonic in syntax string"
 msgstr "falta el mnemónico en la cadena sintáctica"
@@ -212,10 +213,11 @@ msgstr "falta el mnem
 #: fr30-asm.c:496 fr30-asm.c:500 fr30-asm.c:587 fr30-asm.c:688 frv-asm.c:1449
 #: frv-asm.c:1453 frv-asm.c:1540 frv-asm.c:1641 ip2k-asm.c:697 ip2k-asm.c:701
 #: ip2k-asm.c:788 ip2k-asm.c:889 iq2000-asm.c:645 iq2000-asm.c:649
-#: iq2000-asm.c:736 iq2000-asm.c:837 m32c-asm.c:1775 m32c-asm.c:1779
+#: iq2000-asm.c:736 iq2000-asm.c:837 lm32-asm.c:535 lm32-asm.c:539
+#: lm32-asm.c:626 lm32-asm.c:727 m32c-asm.c:1775 m32c-asm.c:1779
 #: m32c-asm.c:1866 m32c-asm.c:1967 m32r-asm.c:514 m32r-asm.c:518
-#: m32r-asm.c:605 m32r-asm.c:706 mep-asm.c:1187 mep-asm.c:1191 mep-asm.c:1278
-#: mep-asm.c:1379 mt-asm.c:781 mt-asm.c:785 mt-asm.c:872 mt-asm.c:973
+#: m32r-asm.c:605 m32r-asm.c:706 mep-asm.c:1473 mep-asm.c:1477 mep-asm.c:1564
+#: mep-asm.c:1665 mt-asm.c:781 mt-asm.c:785 mt-asm.c:872 mt-asm.c:973
 #: openrisc-asm.c:427 openrisc-asm.c:431 openrisc-asm.c:518 openrisc-asm.c:619
 #: xc16x-asm.c:562 xc16x-asm.c:566 xc16x-asm.c:653 xc16x-asm.c:754
 #: xstormy16-asm.c:462 xstormy16-asm.c:466 xstormy16-asm.c:553
@@ -224,111 +226,111 @@ msgid "unrecognized instruction"
 msgstr "no se reconoce la instrucción"
 
 #: fr30-asm.c:543 frv-asm.c:1496 ip2k-asm.c:744 iq2000-asm.c:692
-#: m32c-asm.c:1822 m32r-asm.c:561 mep-asm.c:1234 mt-asm.c:828
+#: lm32-asm.c:582 m32c-asm.c:1822 m32r-asm.c:561 mep-asm.c:1520 mt-asm.c:828
 #: openrisc-asm.c:474 xc16x-asm.c:609 xstormy16-asm.c:509
 #, c-format
 msgid "syntax error (expected char `%c', found `%c')"
 msgstr "error sintáctico (se esperaba el carácter `%c', se encontró `%c')"
 
 #: fr30-asm.c:553 frv-asm.c:1506 ip2k-asm.c:754 iq2000-asm.c:702
-#: m32c-asm.c:1832 m32r-asm.c:571 mep-asm.c:1244 mt-asm.c:838
+#: lm32-asm.c:592 m32c-asm.c:1832 m32r-asm.c:571 mep-asm.c:1530 mt-asm.c:838
 #: openrisc-asm.c:484 xc16x-asm.c:619 xstormy16-asm.c:519
 #, c-format
 msgid "syntax error (expected char `%c', found end of instruction)"
 msgstr "error sintáctico (se esperaba el carácter `%c', se encontró el final de la instrucción)"
 
 #: fr30-asm.c:581 frv-asm.c:1534 ip2k-asm.c:782 iq2000-asm.c:730
-#: m32c-asm.c:1860 m32r-asm.c:599 mep-asm.c:1272 mt-asm.c:866
+#: lm32-asm.c:620 m32c-asm.c:1860 m32r-asm.c:599 mep-asm.c:1558 mt-asm.c:866
 #: openrisc-asm.c:512 xc16x-asm.c:647 xstormy16-asm.c:547
 msgid "junk at end of line"
 msgstr "basura al final de la línea"
 
 #: fr30-asm.c:687 frv-asm.c:1640 ip2k-asm.c:888 iq2000-asm.c:836
-#: m32c-asm.c:1966 m32r-asm.c:705 mep-asm.c:1378 mt-asm.c:972
+#: lm32-asm.c:726 m32c-asm.c:1966 m32r-asm.c:705 mep-asm.c:1664 mt-asm.c:972
 #: openrisc-asm.c:618 xc16x-asm.c:753 xstormy16-asm.c:653
 msgid "unrecognized form of instruction"
 msgstr "no se reconoce la forma de instrucción"
 
 #: fr30-asm.c:699 frv-asm.c:1652 ip2k-asm.c:900 iq2000-asm.c:848
-#: m32c-asm.c:1978 m32r-asm.c:717 mep-asm.c:1390 mt-asm.c:984
+#: lm32-asm.c:738 m32c-asm.c:1978 m32r-asm.c:717 mep-asm.c:1676 mt-asm.c:984
 #: openrisc-asm.c:630 xc16x-asm.c:765 xstormy16-asm.c:665
 #, c-format
 msgid "bad instruction `%.50s...'"
 msgstr "instrucción errónea `%.50s...'"
 
 #: fr30-asm.c:702 frv-asm.c:1655 ip2k-asm.c:903 iq2000-asm.c:851
-#: m32c-asm.c:1981 m32r-asm.c:720 mep-asm.c:1393 mt-asm.c:987
+#: lm32-asm.c:741 m32c-asm.c:1981 m32r-asm.c:720 mep-asm.c:1679 mt-asm.c:987
 #: openrisc-asm.c:633 xc16x-asm.c:768 xstormy16-asm.c:668
 #, c-format
 msgid "bad instruction `%.50s'"
 msgstr "instrucción errónea `%.50s'"
 
 #. Default text to print if an instruction isn't recognized.
-#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 m32c-dis.c:41
-#: m32r-dis.c:41 mep-dis.c:41 mmix-dis.c:278 mt-dis.c:41 openrisc-dis.c:41
-#: xc16x-dis.c:41 xstormy16-dis.c:41
+#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 lm32-dis.c:41
+#: m32c-dis.c:41 m32r-dis.c:41 mep-dis.c:41 mmix-dis.c:278 mt-dis.c:41
+#: openrisc-dis.c:41 xc16x-dis.c:41 xstormy16-dis.c:41
 msgid "*unknown*"
 msgstr "*desconocida*"
 
-#: fr30-dis.c:299 frv-dis.c:396 ip2k-dis.c:288 iq2000-dis.c:189 m32c-dis.c:891
-#: m32r-dis.c:256 mep-dis.c:776 mt-dis.c:290 openrisc-dis.c:135
-#: xc16x-dis.c:375 xstormy16-dis.c:168
+#: fr30-dis.c:299 frv-dis.c:396 ip2k-dis.c:288 iq2000-dis.c:189 lm32-dis.c:147
+#: m32c-dis.c:891 m32r-dis.c:256 mep-dis.c:1192 mt-dis.c:290
+#: openrisc-dis.c:135 xc16x-dis.c:375 xstormy16-dis.c:168
 #, c-format
 msgid "Unrecognized field %d while printing insn.\n"
 msgstr "No se reconoció el campo %d al mostrar insn.\n"
 
 #: fr30-ibld.c:163 frv-ibld.c:163 ip2k-ibld.c:163 iq2000-ibld.c:163
-#: m32c-ibld.c:163 m32r-ibld.c:163 mep-ibld.c:163 mt-ibld.c:163
-#: openrisc-ibld.c:163 xc16x-ibld.c:163 xstormy16-ibld.c:163
+#: lm32-ibld.c:163 m32c-ibld.c:163 m32r-ibld.c:163 mep-ibld.c:163
+#: mt-ibld.c:163 openrisc-ibld.c:163 xc16x-ibld.c:163 xstormy16-ibld.c:163
 #, c-format
 msgid "operand out of range (%ld not between %ld and %lu)"
 msgstr "operando fuera de rango (%ld no está entre %ld y %lu)"
 
 #: fr30-ibld.c:184 frv-ibld.c:184 ip2k-ibld.c:184 iq2000-ibld.c:184
-#: m32c-ibld.c:184 m32r-ibld.c:184 mep-ibld.c:184 mt-ibld.c:184
-#: openrisc-ibld.c:184 xc16x-ibld.c:184 xstormy16-ibld.c:184
+#: lm32-ibld.c:184 m32c-ibld.c:184 m32r-ibld.c:184 mep-ibld.c:184
+#: mt-ibld.c:184 openrisc-ibld.c:184 xc16x-ibld.c:184 xstormy16-ibld.c:184
 #, c-format
 msgid "operand out of range (0x%lx not between 0 and 0x%lx)"
 msgstr "operando fuera de rango (0x%lu no está entre 0 y %lx)"
 
 #: fr30-ibld.c:726 frv-ibld.c:852 ip2k-ibld.c:603 iq2000-ibld.c:709
-#: m32c-ibld.c:1727 m32r-ibld.c:661 mep-ibld.c:1024 mt-ibld.c:745
-#: openrisc-ibld.c:629 xc16x-ibld.c:748 xstormy16-ibld.c:674
+#: lm32-ibld.c:630 m32c-ibld.c:1727 m32r-ibld.c:661 mep-ibld.c:1204
+#: mt-ibld.c:745 openrisc-ibld.c:629 xc16x-ibld.c:748 xstormy16-ibld.c:674
 #, c-format
 msgid "Unrecognized field %d while building insn.\n"
 msgstr "No se reconoció el campo %d al construir insn.\n"
 
 #: fr30-ibld.c:931 frv-ibld.c:1169 ip2k-ibld.c:678 iq2000-ibld.c:884
-#: m32c-ibld.c:2888 m32r-ibld.c:798 mep-ibld.c:1444 mt-ibld.c:965
-#: openrisc-ibld.c:729 xc16x-ibld.c:968 xstormy16-ibld.c:820
+#: lm32-ibld.c:734 m32c-ibld.c:2888 m32r-ibld.c:798 mep-ibld.c:1803
+#: mt-ibld.c:965 openrisc-ibld.c:729 xc16x-ibld.c:968 xstormy16-ibld.c:820
 #, c-format
 msgid "Unrecognized field %d while decoding insn.\n"
 msgstr "No se reconoció el campo %d al decodificar insn.\n"
 
 #: fr30-ibld.c:1077 frv-ibld.c:1447 ip2k-ibld.c:752 iq2000-ibld.c:1015
-#: m32c-ibld.c:3505 m32r-ibld.c:911 mep-ibld.c:1737 mt-ibld.c:1165
-#: openrisc-ibld.c:806 xc16x-ibld.c:1189 xstormy16-ibld.c:930
+#: lm32-ibld.c:823 m32c-ibld.c:3505 m32r-ibld.c:911 mep-ibld.c:2273
+#: mt-ibld.c:1165 openrisc-ibld.c:806 xc16x-ibld.c:1189 xstormy16-ibld.c:930
 #, c-format
 msgid "Unrecognized field %d while getting int operand.\n"
 msgstr "No se reconoció el campo %d al obtener el operando int.\n"
 
 #: fr30-ibld.c:1205 frv-ibld.c:1707 ip2k-ibld.c:808 iq2000-ibld.c:1128
-#: m32c-ibld.c:4104 m32r-ibld.c:1006 mep-ibld.c:2012 mt-ibld.c:1347
-#: openrisc-ibld.c:865 xc16x-ibld.c:1392 xstormy16-ibld.c:1022
+#: lm32-ibld.c:894 m32c-ibld.c:4104 m32r-ibld.c:1006 mep-ibld.c:2725
+#: mt-ibld.c:1347 openrisc-ibld.c:865 xc16x-ibld.c:1392 xstormy16-ibld.c:1022
 #, c-format
 msgid "Unrecognized field %d while getting vma operand.\n"
 msgstr "No se reconoció el campo %d al obtener el operando vma.\n"
 
 #: fr30-ibld.c:1336 frv-ibld.c:1974 ip2k-ibld.c:867 iq2000-ibld.c:1248
-#: m32c-ibld.c:4691 m32r-ibld.c:1107 mep-ibld.c:2271 mt-ibld.c:1536
-#: openrisc-ibld.c:931 xc16x-ibld.c:1596 xstormy16-ibld.c:1121
+#: lm32-ibld.c:972 m32c-ibld.c:4691 m32r-ibld.c:1107 mep-ibld.c:3138
+#: mt-ibld.c:1536 openrisc-ibld.c:931 xc16x-ibld.c:1596 xstormy16-ibld.c:1121
 #, c-format
 msgid "Unrecognized field %d while setting int operand.\n"
 msgstr "No se reconoció el campo %d al establecer el operando int.\n"
 
 #: fr30-ibld.c:1457 frv-ibld.c:2231 ip2k-ibld.c:916 iq2000-ibld.c:1358
-#: m32c-ibld.c:5268 m32r-ibld.c:1198 mep-ibld.c:2520 mt-ibld.c:1715
-#: openrisc-ibld.c:987 xc16x-ibld.c:1790 xstormy16-ibld.c:1210
+#: lm32-ibld.c:1040 m32c-ibld.c:5268 m32r-ibld.c:1198 mep-ibld.c:3541
+#: mt-ibld.c:1715 openrisc-ibld.c:987 xc16x-ibld.c:1790 xstormy16-ibld.c:1210
 #, c-format
 msgid "Unrecognized field %d while setting vma operand.\n"
 msgstr "No se reconoció el campo %d al establecer el operando vma.\n"
@@ -351,9 +353,10 @@ msgstr "el n
 
 #. -- assembler routines inserted here.
 #. -- asm.c
-#: frv-asm.c:972 iq2000-asm.c:56 m32c-asm.c:141 m32c-asm.c:237 m32c-asm.c:279
-#: m32c-asm.c:338 m32c-asm.c:360 m32r-asm.c:53 mep-asm.c:232 mep-asm.c:250
-#: mep-asm.c:265 mep-asm.c:280 mep-asm.c:292 openrisc-asm.c:54
+#: frv-asm.c:972 iq2000-asm.c:56 lm32-asm.c:95 lm32-asm.c:127 lm32-asm.c:157
+#: lm32-asm.c:187 lm32-asm.c:217 lm32-asm.c:247 m32c-asm.c:141 m32c-asm.c:237
+#: m32c-asm.c:279 m32c-asm.c:338 m32c-asm.c:360 m32r-asm.c:53 mep-asm.c:241
+#: mep-asm.c:259 mep-asm.c:274 mep-asm.c:289 mep-asm.c:301 openrisc-asm.c:54
 msgid "missing `)'"
 msgstr "falta un `)'"
 
@@ -378,11 +381,11 @@ msgstr "no se puede lidiar con insert %d\n"
 msgid "%02x\t\t*unknown*"
 msgstr "%02x\t\t*desconocido*"
 
-#: i386-dis.c:9545
+#: i386-dis.c:8924
 msgid "<internal disassembler error>"
 msgstr "<error interno del desensamblador>"
 
-#: i386-dis.c:9776
+#: i386-dis.c:9155
 #, c-format
 msgid ""
 "\n"
@@ -393,32 +396,32 @@ msgstr ""
 "Se admiten las siguientes opciones de desensamblador específicas de i386/x86-64\n"
 "con el interruptor -M (las opciones múltiples se deben separar con comas):\n"
 
-#: i386-dis.c:9780
+#: i386-dis.c:9159
 #, c-format
 msgid "  x86-64      Disassemble in 64bit mode\n"
 msgstr "  x86-64      Desensambla en modo 64bit\n"
 
-#: i386-dis.c:9781
+#: i386-dis.c:9160
 #, c-format
 msgid "  i386        Disassemble in 32bit mode\n"
 msgstr "  i386        Desensambla en modo 32bit\n"
 
-#: i386-dis.c:9782
+#: i386-dis.c:9161
 #, c-format
 msgid "  i8086       Disassemble in 16bit mode\n"
 msgstr "  i8086       Desensambla en modo 16bit\n"
 
-#: i386-dis.c:9783
+#: i386-dis.c:9162
 #, c-format
 msgid "  att         Display instruction in AT&T syntax\n"
 msgstr "  att         Muestra las instrucciones con sintaxis AT&T\n"
 
-#: i386-dis.c:9784
+#: i386-dis.c:9163
 #, c-format
 msgid "  intel       Display instruction in Intel syntax\n"
 msgstr "  intel       Muestra las instrucciones con sintaxis Intel\n"
 
-#: i386-dis.c:9785
+#: i386-dis.c:9164
 #, c-format
 msgid ""
 "  att-mnemonic\n"
@@ -427,7 +430,7 @@ msgstr ""
 "  att-mnemonic\n"
 "              Muestra las instrucciones con mnemónicos AT&T\n"
 
-#: i386-dis.c:9787
+#: i386-dis.c:9166
 #, c-format
 msgid ""
 "  intel-mnemonic\n"
@@ -436,77 +439,87 @@ msgstr ""
 "  intel-mnemonic\n"
 "              Muestra las instrucciones con mnemónicos Intel\n"
 
-#: i386-dis.c:9789
+#: i386-dis.c:9168
 #, c-format
 msgid "  addr64      Assume 64bit address size\n"
 msgstr "  addr64      Asume un tamaño de dirección de 64bit\n"
 
-#: i386-dis.c:9790
+#: i386-dis.c:9169
 #, c-format
 msgid "  addr32      Assume 32bit address size\n"
 msgstr "  addr32      Asume un tamaño de dirección de 32bit\n"
 
-#: i386-dis.c:9791
+#: i386-dis.c:9170
 #, c-format
 msgid "  addr16      Assume 16bit address size\n"
 msgstr "  addr16      Asume un tamaño de dirección de 16bit\n"
 
-#: i386-dis.c:9792
+#: i386-dis.c:9171
 #, c-format
 msgid "  data32      Assume 32bit data size\n"
 msgstr "  data32      Asume un tamaño de datos de 32bit\n"
 
-#: i386-dis.c:9793
+#: i386-dis.c:9172
 #, c-format
 msgid "  data16      Assume 16bit data size\n"
 msgstr "  data16      Asume un tamaño de datos de 16bit\n"
 
-#: i386-dis.c:9794
+#: i386-dis.c:9173
 #, c-format
 msgid "  suffix      Always display instruction suffix in AT&T syntax\n"
 msgstr "  suffix      Siempre muestra el sufijo de instrucción con sintaxis AT&T\n"
 
-#: i386-gen.c:411 ia64-gen.c:307
+#: i386-gen.c:435 ia64-gen.c:307
 #, c-format
 msgid "%s: Error: "
 msgstr "%s: Error: "
 
-#: i386-gen.c:510
+#: i386-gen.c:544
 #, c-format
 msgid "%s: %d: Unknown bitfield: %s\n"
 msgstr "%s: %d: Campo de bits desconocido: %s\n"
 
-#: i386-gen.c:674
+#: i386-gen.c:546
+#, c-format
+msgid "Unknown bitfield: %s\n"
+msgstr "Campo de bits desconocido: %s\n"
+
+#: i386-gen.c:602
+#, c-format
+msgid "%s: %d: Missing `)' in bitfield: %s\n"
+msgstr "%s: %d: Falta un `)' en el campo de bits: %s\n"
+
+#: i386-gen.c:867
 #, c-format
 msgid "can't find i386-opc.tbl for reading, errno = %s\n"
 msgstr "no se puede encontrar i386-opc.tbl para lectura, errno =%s\n"
 
-#: i386-gen.c:851
+#: i386-gen.c:998
 #, c-format
 msgid "can't find i386-reg.tbl for reading, errno = %s\n"
 msgstr "no se puede encontrar i386-reg.tbl para lectura, errno = %s\n"
 
-#: i386-gen.c:943
+#: i386-gen.c:1075
 #, c-format
 msgid "can't create i386-init.h, errno = %s\n"
 msgstr "no se puede crear i386-init.h, errno = %s\n"
 
-#: i386-gen.c:1032 ia64-gen.c:2850
+#: i386-gen.c:1164 ia64-gen.c:2820
 #, c-format
 msgid "unable to change directory to \"%s\", errno = %s\n"
 msgstr "no se puede cambiar el directorio a \"%s\", errno = %s\n"
 
-#: i386-gen.c:1039
+#: i386-gen.c:1171
 #, c-format
 msgid "%d unused bits in i386_cpu_flags.\n"
 msgstr "%d bits sin usar en i386_cpu_flags.\n"
 
-#: i386-gen.c:1046
+#: i386-gen.c:1178
 #, c-format
 msgid "%d unused bits in i386_operand_type.\n"
 msgstr "%d bits sin usar en i386_operand_type.\n"
 
-#: i386-gen.c:1060
+#: i386-gen.c:1192
 #, c-format
 msgid "can't create i386-tbl.h, errno = %s\n"
 msgstr "no se puede crear i386-tbl.h, errno = %s\n"
@@ -516,21 +529,21 @@ msgstr "no se puede crear i386-tbl.h, errno = %s\n"
 msgid "%s: Warning: "
 msgstr "%s: Aviso: "
 
-#: ia64-gen.c:506 ia64-gen.c:740
+#: ia64-gen.c:506 ia64-gen.c:737
 #, c-format
 msgid "multiple note %s not handled\n"
-msgstr "la nota múltiple %s no se maneja\n"
+msgstr "no se maneja la nota múltiple %s\n"
 
 #: ia64-gen.c:617
 msgid "can't find ia64-ic.tbl for reading\n"
 msgstr "no se puede encontrar ia64-ic.tbl para lectura\n"
 
-#: ia64-gen.c:822
+#: ia64-gen.c:819
 #, c-format
 msgid "can't find %s for reading\n"
 msgstr "no se puede encontrar %s para lectura\n"
 
-#: ia64-gen.c:1046
+#: ia64-gen.c:1043
 #, c-format
 msgid ""
 "most recent format '%s'\n"
@@ -539,77 +552,77 @@ msgstr ""
 "el formato más reciente '%s'\n"
 "parece más restrictivo que '%s'\n"
 
-#: ia64-gen.c:1057
+#: ia64-gen.c:1054
 #, c-format
 msgid "overlapping field %s->%s\n"
-msgstr "campo solapado %s->%s\n"
+msgstr "campo traslapado %s->%s\n"
 
-#: ia64-gen.c:1254
+#: ia64-gen.c:1251
 #, c-format
 msgid "overwriting note %d with note %d (IC:%s)\n"
 msgstr "se sobreescribe la nota %d con la nota %d (IC:%s)\n"
 
-#: ia64-gen.c:1459
+#: ia64-gen.c:1456
 #, c-format
 msgid "don't know how to specify %% dependency %s\n"
 msgstr "no se sabe cómo especificar la dependencia %% %s\n"
 
-#: ia64-gen.c:1481
+#: ia64-gen.c:1478
 #, c-format
 msgid "Don't know how to specify # dependency %s\n"
 msgstr "No se sabe cómo especificar la dependencia # %s\n"
 
-#: ia64-gen.c:1520
+#: ia64-gen.c:1517
 #, c-format
 msgid "IC:%s [%s] has no terminals or sub-classes\n"
 msgstr "IC:%s [%s] no tiene terminales o sub-clases\n"
 
-#: ia64-gen.c:1523
+#: ia64-gen.c:1520
 #, c-format
 msgid "IC:%s has no terminals or sub-classes\n"
 msgstr "IC:%s no tiene terminales o sub-clases\n"
 
-#: ia64-gen.c:1532
+#: ia64-gen.c:1529
 #, c-format
 msgid "no insns mapped directly to terminal IC %s [%s]"
 msgstr "no hay insns mapeadas directamente al IC terminal %s [%s]"
 
-#: ia64-gen.c:1535
+#: ia64-gen.c:1532
 #, c-format
 msgid "no insns mapped directly to terminal IC %s\n"
 msgstr "no hay insns mapeadas directamente al IC terminal %s\n"
 
-#: ia64-gen.c:1546
+#: ia64-gen.c:1543
 #, c-format
 msgid "class %s is defined but not used\n"
 msgstr "se define la clase %s pero no se utiliza\n"
 
-#: ia64-gen.c:1559
+#: ia64-gen.c:1556
 #, c-format
 msgid "Warning: rsrc %s (%s) has no chks\n"
 msgstr "Aviso: el rsrc %s (%s) no tiene chks\n"
 
-#: ia64-gen.c:1562
+#: ia64-gen.c:1559
 #, c-format
 msgid "Warning: rsrc %s (%s) has no chks or regs\n"
 msgstr "Aviso: el rsrc %s (%s) no tiene chks o regs\n"
 
-#: ia64-gen.c:1566
+#: ia64-gen.c:1563
 #, c-format
 msgid "rsrc %s (%s) has no regs\n"
 msgstr "el rsrc %s (%s) no tiene registros\n"
 
-#: ia64-gen.c:2478
+#: ia64-gen.c:2455
 #, c-format
 msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n"
 msgstr "la nota IC %d en el código de operación %s (IC:%s) tiene conflictos con el recurso %s nota %d\n"
 
-#: ia64-gen.c:2506
+#: ia64-gen.c:2483
 #, c-format
 msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n"
 msgstr "la nota IC %d para el código de operación %s (IC:%s) tiene conflictos con el recurso %s nota %d\n"
 
-#: ia64-gen.c:2520
+#: ia64-gen.c:2497
 #, c-format
 msgid "opcode %s has no class (ops %d %d %d)\n"
 msgstr "el código de operación %s no tiene clase (ops %d %d %d)\n"
@@ -623,7 +636,7 @@ msgstr "la palabra clave W es inv
 #. Invalid offset present.
 #: ip2k-asm.c:106
 msgid "offset(IP) is not a valid form"
-msgstr "el desplazamiento(IP) no es una forma válida"
+msgstr "offset(IP) no es una forma válida"
 
 #. Found something there in front of (DP) but it's out
 #. of range.
@@ -670,7 +683,7 @@ msgstr "Se intent
 msgid "immediate value cannot be register"
 msgstr "el valor inmediato no puede ser un registro"
 
-#: iq2000-asm.c:123 iq2000-asm.c:153
+#: iq2000-asm.c:123 iq2000-asm.c:153 lm32-asm.c:70
 msgid "immediate value out of range"
 msgstr "el valor inmediato está fuera de rango"
 
@@ -678,6 +691,22 @@ msgstr "el valor inmediato est
 msgid "21-bit offset out of range"
 msgstr "desplazamiento de 21-bit fuera de rango"
 
+#: lm32-asm.c:166
+msgid "expecting gp relative address: gp(symbol)"
+msgstr "se espera una dirección relativa a gp: gp(símbolo)"
+
+#: lm32-asm.c:196
+msgid "expecting got relative address: got(symbol)"
+msgstr "se espera una dirección relativa a got: got(símbolo)"
+
+#: lm32-asm.c:226
+msgid "expecting got relative address: gotoffhi16(symbol)"
+msgstr "se espera una dirección relativa a got: gotoffhi16(símbolo)"
+
+#: lm32-asm.c:256
+msgid "expecting got relative address: gotofflo16(symbol)"
+msgstr "se espera una dirección relativa a got: gotofflo16(símbolo)"
+
 #: m10200-dis.c:158 m10300-dis.c:582
 #, c-format
 msgid "unknown\t0x%04lx"
@@ -762,12 +791,12 @@ msgstr "no es un par r0l/r0h v
 msgid "Invalid size specifier"
 msgstr "Especificador de tamaño inválido"
 
-#: m68k-dis.c:1163
+#: m68k-dis.c:1278
 #, c-format
 msgid "<function code %d>"
 msgstr "<código de función %d>"
 
-#: m68k-dis.c:1320
+#: m68k-dis.c:1437
 #, c-format
 msgid "<internal error in opcode table: %s %s>\n"
 msgstr "<error interno en la tabla de códigos de operación: %s %s>\n"
@@ -777,39 +806,59 @@ msgstr "<error interno en la tabla de c
 msgid "# <dis error: %08lx>"
 msgstr "# <error de desensamblador: %08lx>"
 
-#: mep-asm.c:114
+#: mep-asm.c:129
 msgid "Only $tp or $13 allowed for this opcode"
 msgstr "Sólo se permite $tp o $13 para este código de operación"
 
-#: mep-asm.c:128
+#: mep-asm.c:143
 msgid "Only $sp or $15 allowed for this opcode"
 msgstr "Sólo se permite $sp o $15 para este código de operación"
 
-#: mep-asm.c:299 mep-asm.c:455
+#: mep-asm.c:308 mep-asm.c:504
 #, c-format
 msgid "invalid %function() here"
 msgstr "%funcion() inválida aquí"
 
-#: mips-dis.c:781
+#: mep-asm.c:336
+msgid "Immediate is out of range -32768 to 32767"
+msgstr "El inmediato está fuera del rango -32768 a 32767"
+
+#: mep-asm.c:356
+msgid "Immediate is out of range 0 to 65535"
+msgstr "El inmediato está fuera del rango 0 a 65535"
+
+#: mep-asm.c:549 mep-asm.c:562
+msgid "Immediate is out of range -512 to 511"
+msgstr "El inmediato está fuera del rango -512 a 511"
+
+#: mep-asm.c:554 mep-asm.c:563
+msgid "Immediate is out of range -128 to 127"
+msgstr "El inmediato está fuera del rango -128 a 127"
+
+#: mep-asm.c:558
+msgid "Value is not aligned enough"
+msgstr "El valor no está suficientemente alineado"
+
+#: mips-dis.c:841
 msgid "# internal error, incomplete extension sequence (+)"
 msgstr "# error interno, secuencia de extensión incompleta (+)"
 
-#: mips-dis.c:915
+#: mips-dis.c:975
 #, c-format
 msgid "# internal error, undefined extension sequence (+%c)"
 msgstr "# error interno, secuencia de extensión sin definir (+%c)"
 
-#: mips-dis.c:1274
+#: mips-dis.c:1335
 #, c-format
 msgid "# internal error, undefined modifier (%c)"
 msgstr "# error interno, modificador (%c) sin definir"
 
-#: mips-dis.c:1881
+#: mips-dis.c:1942
 #, c-format
 msgid "# internal disassembler error, unrecognised modifier (%c)"
 msgstr "# error interno del desensamblador, no se reconoce el modificador (%c)"
 
-#: mips-dis.c:2112
+#: mips-dis.c:2173
 #, c-format
 msgid ""
 "\n"
@@ -820,7 +869,7 @@ msgstr ""
 "Las siguientes opciones de desensamblador específicas de MIPS se admiten\n"
 "para usarse con el interruptor -M (las opciones múltiples se deben separar con comas):\n"
 
-#: mips-dis.c:2116
+#: mips-dis.c:2177
 #, c-format
 msgid ""
 "\n"
@@ -831,7 +880,7 @@ msgstr ""
 "  gpr-names=ABI            Muestra los nombres GPR de acuerdo a la ABI especificada.\n"
 "                           Por defecto: basado en el binario a desensamblar.\n"
 
-#: mips-dis.c:2120
+#: mips-dis.c:2181
 #, c-format
 msgid ""
 "\n"
@@ -842,7 +891,7 @@ msgstr ""
 "  fpr-names=ABI            Muestra los nombres FPR de acuerdo a la ABI especificada.\n"
 "                           Por defecto: numérico.\n"
 
-#: mips-dis.c:2124
+#: mips-dis.c:2185
 #, c-format
 msgid ""
 "\n"
@@ -855,7 +904,7 @@ msgstr ""
 "                           la arquitectura especificada.\n"
 "                           Por defecto: basado en el binario a desensamblar.\n"
 
-#: mips-dis.c:2129
+#: mips-dis.c:2190
 #, c-format
 msgid ""
 "\n"
@@ -868,7 +917,7 @@ msgstr ""
 "                           especificada.\n"
 "                           Por defecto: basado en el binario a desensamblar.\n"
 
-#: mips-dis.c:2134
+#: mips-dis.c:2195
 #, c-format
 msgid ""
 "\n"
@@ -879,7 +928,7 @@ msgstr ""
 "  reg-names=ABI            Muestra los nombres GPR y FPR de acuerdo a\n"
 "                           la ABI especificada.\n"
 
-#: mips-dis.c:2138
+#: mips-dis.c:2199
 #, c-format
 msgid ""
 "\n"
@@ -890,7 +939,7 @@ msgstr ""
 "  reg-names=ARCH           Muestra el registro CP0 y los nombres HWR de acuerdo a\n"
 "                           la arquitectura especificada.\n"
 
-#: mips-dis.c:2142
+#: mips-dis.c:2203
 #, c-format
 msgid ""
 "\n"
@@ -901,12 +950,12 @@ msgstr ""
 "  Para las opciones anteriores, se admiten los siguientes valores de \"ABI\":\n"
 "   "
 
-#: mips-dis.c:2147 mips-dis.c:2155 mips-dis.c:2157
+#: mips-dis.c:2208 mips-dis.c:2216 mips-dis.c:2218
 #, c-format
 msgid "\n"
 msgstr "\n"
 
-#: mips-dis.c:2149
+#: mips-dis.c:2210
 #, c-format
 msgid ""
 "\n"
@@ -936,6 +985,15 @@ msgstr "(desconocido)"
 msgid "*unknown operands type: %d*"
 msgstr "*tipo de operandos desconocido: %d*"
 
+#: msp430-dis.c:327
+msgid "Illegal as emulation instr"
+msgstr "Instrucción de emulación as ilegal"
+
+#. R2/R3 are illegal as dest: may be data section.
+#: msp430-dis.c:378
+msgid "Illegal as 2-op instr"
+msgstr "Instrucción 2-op as ilegal"
+
 #: mt-asm.c:110 mt-asm.c:190
 msgid "Operand out of range. Must be between -32768 and 32767."
 msgstr "Operando fuera de rango. Debe estar entre -32768 y 32767."
@@ -962,43 +1020,63 @@ msgstr "operando inv
 msgid "$<undefined>"
 msgstr "$<sin definir>"
 
-#: ppc-opc.c:862 ppc-opc.c:890
+#: ppc-dis.c:222
+#, c-format
+msgid "warning: ignoring unknown -M%s option\n"
+msgstr "aviso: se descarta la opción -M%s desconocida\n"
+
+#: ppc-dis.c:511
+#, c-format
+msgid ""
+"\n"
+"The following PPC specific disassembler options are supported for use with\n"
+"the -M switch:\n"
+msgstr ""
+"\n"
+"Las siguientes opciones de desensamblador específicas de PPC se admiten con\n"
+"el interruptor -M:\n"
+
+#: ppc-opc.c:870 ppc-opc.c:898
 msgid "invalid conditional option"
 msgstr "opción condicional inválida"
 
-#: ppc-opc.c:892
+#: ppc-opc.c:900
 msgid "attempt to set y bit when using + or - modifier"
-msgstr "intento de establecer el bit y cuando se usaba el modificador + ó -"
+msgstr "intento de establecer el bit y al usar el modificador + ó -"
 
-#: ppc-opc.c:924
+#: ppc-opc.c:932
 msgid "invalid mask field"
 msgstr "campo de máscara inválido"
 
-#: ppc-opc.c:950
+#: ppc-opc.c:958
 msgid "ignoring invalid mfcr mask"
 msgstr "se descarta la máscara mfcr inválida"
 
-#: ppc-opc.c:1000 ppc-opc.c:1035
+#: ppc-opc.c:1008 ppc-opc.c:1043
 msgid "illegal bitmask"
 msgstr "máscara de bits ilegal"
 
-#: ppc-opc.c:1155
+#: ppc-opc.c:1163
 msgid "index register in load range"
 msgstr "registro índice en el rango de carga"
 
-#: ppc-opc.c:1171
+#: ppc-opc.c:1179
 msgid "source and target register operands must be different"
 msgstr "los operandos de registros fuente y objetivo deben ser diferentes"
 
-#: ppc-opc.c:1186
+#: ppc-opc.c:1194
 msgid "invalid register operand when updating"
-msgstr "operando de registro inválido mientras se actualizaba"
+msgstr "operando de registro inválido al actualizar"
 
-#: ppc-opc.c:1265
+#: ppc-opc.c:1273
 msgid "invalid sprg number"
 msgstr "número sprg inválido"
 
-#: s390-dis.c:276
+#: ppc-opc.c:1443
+msgid "invalid constant"
+msgstr "constante inválida"
+
+#: s390-dis.c:277
 #, c-format
 msgid ""
 "\n"
@@ -1010,37 +1088,38 @@ msgstr ""
 "para usarse con el interruptor -M (las opciones múltiples se deben\n"
 "separar con comas):\n"
 
-#: s390-dis.c:280
+#: s390-dis.c:281
 #, c-format
 msgid "  esa         Disassemble in ESA architecture mode\n"
 msgstr "  esa         Desensambla en modo de arquitectura ESA\n"
 
-#: s390-dis.c:281
+#: s390-dis.c:282
 #, c-format
 msgid "  zarch       Disassemble in z/Architecture mode\n"
 msgstr "  zarch       Desensambla en modo de z/Architecture\n"
 
-#: score-dis.c:220 score-dis.c:383
+#: score-dis.c:662 score-dis.c:869 score-dis.c:1030 score-dis.c:1144
+#: score-dis.c:1151 score-dis.c:1158 score7-dis.c:694 score7-dis.c:857
 msgid "<illegal instruction>"
 msgstr "<instrucción ilegal>"
 
-#: sparc-dis.c:282
+#: sparc-dis.c:283
 #, c-format
 msgid "Internal error:  bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
 msgstr "Error interno:  sparc-opcode.h erróneo: \"%s\", %#.8lx, %#.8lx\n"
 
-#: sparc-dis.c:293
+#: sparc-dis.c:294
 #, c-format
 msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
 msgstr "Error interno: sparc-opcode.h erróneo: \"%s\", %#.8lx, %#.8lx\n"
 
-#: sparc-dis.c:343
+#: sparc-dis.c:344
 #, c-format
 msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"
 msgstr "Error interno: sparc-opcode.h erróneo: \"%s\" == \"%s\"\n"
 
 #. Mark as non-valid instruction.
-#: sparc-dis.c:1013
+#: sparc-dis.c:1014
 msgid "unknown"
 msgstr "desconocida"
 

diff --git a/opcodes/po/fr.po b/opcodes/po/fr.po
index 91a78b9..81b385f 100644 (file)
--- a/opcodes/po/fr.po
+++ b/opcodes/po/fr.po
@@ -2,14 +2,14 @@
 # Copyright (C) 2008 Free Software Foundation, Inc.
 # This file is distributed under the same license as the binutils package.
 # Michel Robitaille <robitail@IRO.UMontreal.CA>, traducteur depuis/since 1996.
-# Nicolas Provost <nprovost@quadriv.com>, 2008.
+# Nicolas Provost <nprovost@quadriv.com>, 2009.
 #
 msgid ""
 msgstr ""
-"Project-Id-Version: opcodes 2.18.90\n"
+"Project-Id-Version: opcodes 2.19.90\n"
 "Report-Msgid-Bugs-To: bug-binutils@gnu.org\n"
-"POT-Creation-Date: 2008-09-09 15:56+0930\n"
-"PO-Revision-Date: 2008-09-24 15:24+0100\n"
+"POT-Creation-Date: 2009-09-07 14:08+0200\n"
+"PO-Revision-Date: 2009-09-20 09:25+0100\n"
 "Last-Translator: Nicolas Provost <nprovost@quadriv.com>\n"
 "Language-Team: French <traduc@traduc.org>\n"
 "MIME-Version: 1.0\n"
@@ -111,23 +111,23 @@ msgstr "adresse de branchement non multiple de 16"
 msgid "must specify .jd or no nullify suffix"
 msgstr "suffixe .jd ou validant attendu"
 
-#: arm-dis.c:1808
+#: arm-dis.c:1915
 msgid "<illegal precision>"
 msgstr "<précision illégale>"
 
 #. XXX - should break 'option' at following delimiter.
-#: arm-dis.c:3818
+#: arm-dis.c:4014
 #, c-format
 msgid "Unrecognised register name set: %s\n"
 msgstr "Nom de jeu de registres inconnu : %s\n"
 
 #. XXX - should break 'option' at following delimiter.
-#: arm-dis.c:3826
+#: arm-dis.c:4022
 #, c-format
 msgid "Unrecognised disassembler option: %s\n"
 msgstr "Option du désassembleur non reconnue : %s\n"
 
-#: arm-dis.c:4238
+#: arm-dis.c:4519
 #, c-format
 msgid ""
 "\n"
@@ -154,8 +154,9 @@ msgid "unknown constraint `%c'"
 msgstr "contrainte inconnue « %c »"
 
 #: cgen-asm.c:336 fr30-ibld.c:200 frv-ibld.c:200 ip2k-ibld.c:200
-#: iq2000-ibld.c:200 m32c-ibld.c:200 m32r-ibld.c:200 mep-ibld.c:200
-#: mt-ibld.c:200 openrisc-ibld.c:200 xc16x-ibld.c:200 xstormy16-ibld.c:200
+#: iq2000-ibld.c:200 lm32-ibld.c:200 m32c-ibld.c:200 m32r-ibld.c:200
+#: mep-ibld.c:200 mt-ibld.c:200 openrisc-ibld.c:200 xc16x-ibld.c:200
+#: xstormy16-ibld.c:200
 #, c-format
 msgid "operand out of range (%ld not between %ld and %ld)"
 msgstr "opérande hors limites (%ld n'est pas entre %ld et %ld)"
@@ -198,14 +199,14 @@ msgid "Register list is not valid"
 msgstr "Liste de registres non valide"
 
 #: fr30-asm.c:310 frv-asm.c:1263 ip2k-asm.c:511 iq2000-asm.c:459
-#: m32c-asm.c:1589 m32r-asm.c:328 mep-asm.c:1001 mt-asm.c:595
+#: lm32-asm.c:349 m32c-asm.c:1589 m32r-asm.c:328 mep-asm.c:1287 mt-asm.c:595
 #: openrisc-asm.c:241 xc16x-asm.c:376 xstormy16-asm.c:276
 #, c-format
 msgid "Unrecognized field %d while parsing.\n"
 msgstr "Champ non reconnu %d lors de l'analyse.\n"
 
 #: fr30-asm.c:361 frv-asm.c:1314 ip2k-asm.c:562 iq2000-asm.c:510
-#: m32c-asm.c:1640 m32r-asm.c:379 mep-asm.c:1052 mt-asm.c:646
+#: lm32-asm.c:400 m32c-asm.c:1640 m32r-asm.c:379 mep-asm.c:1338 mt-asm.c:646
 #: openrisc-asm.c:292 xc16x-asm.c:427 xstormy16-asm.c:327
 msgid "missing mnemonic in syntax string"
 msgstr "mnémonique manquante dans la syntaxe de la chaîne"
@@ -214,10 +215,11 @@ msgstr "mn
 #: fr30-asm.c:496 fr30-asm.c:500 fr30-asm.c:587 fr30-asm.c:688 frv-asm.c:1449
 #: frv-asm.c:1453 frv-asm.c:1540 frv-asm.c:1641 ip2k-asm.c:697 ip2k-asm.c:701
 #: ip2k-asm.c:788 ip2k-asm.c:889 iq2000-asm.c:645 iq2000-asm.c:649
-#: iq2000-asm.c:736 iq2000-asm.c:837 m32c-asm.c:1775 m32c-asm.c:1779
+#: iq2000-asm.c:736 iq2000-asm.c:837 lm32-asm.c:535 lm32-asm.c:539
+#: lm32-asm.c:626 lm32-asm.c:727 m32c-asm.c:1775 m32c-asm.c:1779
 #: m32c-asm.c:1866 m32c-asm.c:1967 m32r-asm.c:514 m32r-asm.c:518
-#: m32r-asm.c:605 m32r-asm.c:706 mep-asm.c:1187 mep-asm.c:1191 mep-asm.c:1278
-#: mep-asm.c:1379 mt-asm.c:781 mt-asm.c:785 mt-asm.c:872 mt-asm.c:973
+#: m32r-asm.c:605 m32r-asm.c:706 mep-asm.c:1473 mep-asm.c:1477 mep-asm.c:1564
+#: mep-asm.c:1665 mt-asm.c:781 mt-asm.c:785 mt-asm.c:872 mt-asm.c:973
 #: openrisc-asm.c:427 openrisc-asm.c:431 openrisc-asm.c:518 openrisc-asm.c:619
 #: xc16x-asm.c:562 xc16x-asm.c:566 xc16x-asm.c:653 xc16x-asm.c:754
 #: xstormy16-asm.c:462 xstormy16-asm.c:466 xstormy16-asm.c:553
@@ -226,111 +228,111 @@ msgid "unrecognized instruction"
 msgstr "instruction non reconnue"
 
 #: fr30-asm.c:543 frv-asm.c:1496 ip2k-asm.c:744 iq2000-asm.c:692
-#: m32c-asm.c:1822 m32r-asm.c:561 mep-asm.c:1234 mt-asm.c:828
+#: lm32-asm.c:582 m32c-asm.c:1822 m32r-asm.c:561 mep-asm.c:1520 mt-asm.c:828
 #: openrisc-asm.c:474 xc16x-asm.c:609 xstormy16-asm.c:509
 #, c-format
 msgid "syntax error (expected char `%c', found `%c')"
 msgstr "erreur de syntaxe (caractère « %c » attendu,  « %c » obtenu)"
 
 #: fr30-asm.c:553 frv-asm.c:1506 ip2k-asm.c:754 iq2000-asm.c:702
-#: m32c-asm.c:1832 m32r-asm.c:571 mep-asm.c:1244 mt-asm.c:838
+#: lm32-asm.c:592 m32c-asm.c:1832 m32r-asm.c:571 mep-asm.c:1530 mt-asm.c:838
 #: openrisc-asm.c:484 xc16x-asm.c:619 xstormy16-asm.c:519
 #, c-format
 msgid "syntax error (expected char `%c', found end of instruction)"
 msgstr "erreur de syntaxe (caractère « %c » attendu, fin de l'instruction trouvée)"
 
 #: fr30-asm.c:581 frv-asm.c:1534 ip2k-asm.c:782 iq2000-asm.c:730
-#: m32c-asm.c:1860 m32r-asm.c:599 mep-asm.c:1272 mt-asm.c:866
+#: lm32-asm.c:620 m32c-asm.c:1860 m32r-asm.c:599 mep-asm.c:1558 mt-asm.c:866
 #: openrisc-asm.c:512 xc16x-asm.c:647 xstormy16-asm.c:547
 msgid "junk at end of line"
 msgstr "rebut à la fin de la ligne"
 
 #: fr30-asm.c:687 frv-asm.c:1640 ip2k-asm.c:888 iq2000-asm.c:836
-#: m32c-asm.c:1966 m32r-asm.c:705 mep-asm.c:1378 mt-asm.c:972
+#: lm32-asm.c:726 m32c-asm.c:1966 m32r-asm.c:705 mep-asm.c:1664 mt-asm.c:972
 #: openrisc-asm.c:618 xc16x-asm.c:753 xstormy16-asm.c:653
 msgid "unrecognized form of instruction"
 msgstr "forme d'instruction non reconnue"
 
 #: fr30-asm.c:699 frv-asm.c:1652 ip2k-asm.c:900 iq2000-asm.c:848
-#: m32c-asm.c:1978 m32r-asm.c:717 mep-asm.c:1390 mt-asm.c:984
+#: lm32-asm.c:738 m32c-asm.c:1978 m32r-asm.c:717 mep-asm.c:1676 mt-asm.c:984
 #: openrisc-asm.c:630 xc16x-asm.c:765 xstormy16-asm.c:665
 #, c-format
 msgid "bad instruction `%.50s...'"
 msgstr "instruction erronée « %.50s... »"
 
 #: fr30-asm.c:702 frv-asm.c:1655 ip2k-asm.c:903 iq2000-asm.c:851
-#: m32c-asm.c:1981 m32r-asm.c:720 mep-asm.c:1393 mt-asm.c:987
+#: lm32-asm.c:741 m32c-asm.c:1981 m32r-asm.c:720 mep-asm.c:1679 mt-asm.c:987
 #: openrisc-asm.c:633 xc16x-asm.c:768 xstormy16-asm.c:668
 #, c-format
 msgid "bad instruction `%.50s'"
 msgstr "instruction erronée « %.50s »"
 
 #. Default text to print if an instruction isn't recognized.
-#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 m32c-dis.c:41
-#: m32r-dis.c:41 mep-dis.c:41 mmix-dis.c:278 mt-dis.c:41 openrisc-dis.c:41
-#: xc16x-dis.c:41 xstormy16-dis.c:41
+#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 lm32-dis.c:41
+#: m32c-dis.c:41 m32r-dis.c:41 mep-dis.c:41 mmix-dis.c:278 mt-dis.c:41
+#: openrisc-dis.c:41 xc16x-dis.c:41 xstormy16-dis.c:41
 msgid "*unknown*"
 msgstr "*inconnu*"
 
-#: fr30-dis.c:299 frv-dis.c:396 ip2k-dis.c:288 iq2000-dis.c:189 m32c-dis.c:891
-#: m32r-dis.c:256 mep-dis.c:776 mt-dis.c:290 openrisc-dis.c:135
-#: xc16x-dis.c:375 xstormy16-dis.c:168
+#: fr30-dis.c:299 frv-dis.c:396 ip2k-dis.c:288 iq2000-dis.c:189 lm32-dis.c:147
+#: m32c-dis.c:891 m32r-dis.c:256 mep-dis.c:1192 mt-dis.c:290
+#: openrisc-dis.c:135 xc16x-dis.c:375 xstormy16-dis.c:168
 #, c-format
 msgid "Unrecognized field %d while printing insn.\n"
 msgstr "Champ non reconnu %d lors de l'affichage d'instructions.\n"
 
 #: fr30-ibld.c:163 frv-ibld.c:163 ip2k-ibld.c:163 iq2000-ibld.c:163
-#: m32c-ibld.c:163 m32r-ibld.c:163 mep-ibld.c:163 mt-ibld.c:163
-#: openrisc-ibld.c:163 xc16x-ibld.c:163 xstormy16-ibld.c:163
+#: lm32-ibld.c:163 m32c-ibld.c:163 m32r-ibld.c:163 mep-ibld.c:163
+#: mt-ibld.c:163 openrisc-ibld.c:163 xc16x-ibld.c:163 xstormy16-ibld.c:163
 #, c-format
 msgid "operand out of range (%ld not between %ld and %lu)"
 msgstr "opérande hors limites (%ld n'est pas entre %ld et %lu)"
 
 #: fr30-ibld.c:184 frv-ibld.c:184 ip2k-ibld.c:184 iq2000-ibld.c:184
-#: m32c-ibld.c:184 m32r-ibld.c:184 mep-ibld.c:184 mt-ibld.c:184
-#: openrisc-ibld.c:184 xc16x-ibld.c:184 xstormy16-ibld.c:184
+#: lm32-ibld.c:184 m32c-ibld.c:184 m32r-ibld.c:184 mep-ibld.c:184
+#: mt-ibld.c:184 openrisc-ibld.c:184 xc16x-ibld.c:184 xstormy16-ibld.c:184
 #, c-format
 msgid "operand out of range (0x%lx not between 0 and 0x%lx)"
 msgstr "opérande hors limite (0x%lx n'est pas entre 0 et 0x%lx)"
 
 #: fr30-ibld.c:726 frv-ibld.c:852 ip2k-ibld.c:603 iq2000-ibld.c:709
-#: m32c-ibld.c:1727 m32r-ibld.c:661 mep-ibld.c:1024 mt-ibld.c:745
-#: openrisc-ibld.c:629 xc16x-ibld.c:748 xstormy16-ibld.c:674
+#: lm32-ibld.c:630 m32c-ibld.c:1727 m32r-ibld.c:661 mep-ibld.c:1204
+#: mt-ibld.c:745 openrisc-ibld.c:629 xc16x-ibld.c:748 xstormy16-ibld.c:674
 #, c-format
 msgid "Unrecognized field %d while building insn.\n"
 msgstr "Champ non reconnu %d lors de la construction d'instruction.\n"
 
 #: fr30-ibld.c:931 frv-ibld.c:1169 ip2k-ibld.c:678 iq2000-ibld.c:884
-#: m32c-ibld.c:2888 m32r-ibld.c:798 mep-ibld.c:1444 mt-ibld.c:965
-#: openrisc-ibld.c:729 xc16x-ibld.c:968 xstormy16-ibld.c:820
+#: lm32-ibld.c:734 m32c-ibld.c:2888 m32r-ibld.c:798 mep-ibld.c:1803
+#: mt-ibld.c:965 openrisc-ibld.c:729 xc16x-ibld.c:968 xstormy16-ibld.c:820
 #, c-format
 msgid "Unrecognized field %d while decoding insn.\n"
 msgstr "Champ non reconnu %d lors du décodage d'instructions.\n"
 
 #: fr30-ibld.c:1077 frv-ibld.c:1447 ip2k-ibld.c:752 iq2000-ibld.c:1015
-#: m32c-ibld.c:3505 m32r-ibld.c:911 mep-ibld.c:1737 mt-ibld.c:1165
-#: openrisc-ibld.c:806 xc16x-ibld.c:1189 xstormy16-ibld.c:930
+#: lm32-ibld.c:823 m32c-ibld.c:3505 m32r-ibld.c:911 mep-ibld.c:2273
+#: mt-ibld.c:1165 openrisc-ibld.c:806 xc16x-ibld.c:1189 xstormy16-ibld.c:930
 #, c-format
 msgid "Unrecognized field %d while getting int operand.\n"
 msgstr "Champ non reconnu %d lors de l'obtention d'un opérande int.\n"
 
 #: fr30-ibld.c:1205 frv-ibld.c:1707 ip2k-ibld.c:808 iq2000-ibld.c:1128
-#: m32c-ibld.c:4104 m32r-ibld.c:1006 mep-ibld.c:2012 mt-ibld.c:1347
-#: openrisc-ibld.c:865 xc16x-ibld.c:1392 xstormy16-ibld.c:1022
+#: lm32-ibld.c:894 m32c-ibld.c:4104 m32r-ibld.c:1006 mep-ibld.c:2725
+#: mt-ibld.c:1347 openrisc-ibld.c:865 xc16x-ibld.c:1392 xstormy16-ibld.c:1022
 #, c-format
 msgid "Unrecognized field %d while getting vma operand.\n"
 msgstr "Champ non reconnu %d lors de l'obtention d'un opérande vma.\n"
 
 #: fr30-ibld.c:1336 frv-ibld.c:1974 ip2k-ibld.c:867 iq2000-ibld.c:1248
-#: m32c-ibld.c:4691 m32r-ibld.c:1107 mep-ibld.c:2271 mt-ibld.c:1536
-#: openrisc-ibld.c:931 xc16x-ibld.c:1596 xstormy16-ibld.c:1121
+#: lm32-ibld.c:972 m32c-ibld.c:4691 m32r-ibld.c:1107 mep-ibld.c:3138
+#: mt-ibld.c:1536 openrisc-ibld.c:931 xc16x-ibld.c:1596 xstormy16-ibld.c:1121
 #, c-format
 msgid "Unrecognized field %d while setting int operand.\n"
 msgstr "Champ non reconnu %d lors de l'initialisation d'un opérande int.\n"
 
 #: fr30-ibld.c:1457 frv-ibld.c:2231 ip2k-ibld.c:916 iq2000-ibld.c:1358
-#: m32c-ibld.c:5268 m32r-ibld.c:1198 mep-ibld.c:2520 mt-ibld.c:1715
-#: openrisc-ibld.c:987 xc16x-ibld.c:1790 xstormy16-ibld.c:1210
+#: lm32-ibld.c:1040 m32c-ibld.c:5268 m32r-ibld.c:1198 mep-ibld.c:3541
+#: mt-ibld.c:1715 openrisc-ibld.c:987 xc16x-ibld.c:1790 xstormy16-ibld.c:1210
 #, c-format
 msgid "Unrecognized field %d while setting vma operand.\n"
 msgstr "Champ non reconnu %d lors de l'initialisation d'un opérande vma.\n"
@@ -353,9 +355,10 @@ msgstr "Le num
 
 #. -- assembler routines inserted here.
 #. -- asm.c
-#: frv-asm.c:972 iq2000-asm.c:56 m32c-asm.c:141 m32c-asm.c:237 m32c-asm.c:279
-#: m32c-asm.c:338 m32c-asm.c:360 m32r-asm.c:53 mep-asm.c:232 mep-asm.c:250
-#: mep-asm.c:265 mep-asm.c:280 mep-asm.c:292 openrisc-asm.c:54
+#: frv-asm.c:972 iq2000-asm.c:56 lm32-asm.c:95 lm32-asm.c:127 lm32-asm.c:157
+#: lm32-asm.c:187 lm32-asm.c:217 lm32-asm.c:247 m32c-asm.c:141 m32c-asm.c:237
+#: m32c-asm.c:279 m32c-asm.c:338 m32c-asm.c:360 m32r-asm.c:53 mep-asm.c:241
+#: mep-asm.c:259 mep-asm.c:274 mep-asm.c:289 mep-asm.c:301 openrisc-asm.c:54
 msgid "missing `)'"
 msgstr "\")\" manquante"
 
@@ -381,11 +384,11 @@ msgstr "Impossible de g
 msgid "%02x\t\t*unknown*"
 msgstr "%02x\t\t*inconnu*"
 
-#: i386-dis.c:9545
+#: i386-dis.c:8924
 msgid "<internal disassembler error>"
 msgstr "<erreur interne du désassembleur>"
 
-#: i386-dis.c:9776
+#: i386-dis.c:9155
 #, c-format
 msgid ""
 "\n"
@@ -396,32 +399,32 @@ msgstr ""
 "Les options spécifiques i386/x86-64 du désassembleur sont supportées avec l'utilisation\n"
 "de l'option -M (les options multiples doivent être séparées par des virgules):\n"
 
-#: i386-dis.c:9780
+#: i386-dis.c:9159
 #, c-format
 msgid "  x86-64      Disassemble in 64bit mode\n"
 msgstr "  x86-64      Désassembler en mode 64 bits\n"
 
-#: i386-dis.c:9781
+#: i386-dis.c:9160
 #, c-format
 msgid "  i386        Disassemble in 32bit mode\n"
 msgstr "  i386        Désassembler en mode 32 bits\n"
 
-#: i386-dis.c:9782
+#: i386-dis.c:9161
 #, c-format
 msgid "  i8086       Disassemble in 16bit mode\n"
 msgstr "  i8086       Désassembler en mode 16 bits\n"
 
-#: i386-dis.c:9783
+#: i386-dis.c:9162
 #, c-format
 msgid "  att         Display instruction in AT&T syntax\n"
 msgstr "  att         Afficher les instructions en syntaxe AT&T\n"
 
-#: i386-dis.c:9784
+#: i386-dis.c:9163
 #, c-format
 msgid "  intel       Display instruction in Intel syntax\n"
 msgstr "  intel       Afficher les instructions en syntaxe Intel\n"
 
-#: i386-dis.c:9785
+#: i386-dis.c:9164
 #, c-format
 msgid ""
 "  att-mnemonic\n"
@@ -430,7 +433,7 @@ msgstr ""
 "  att-mnemonic\n"
 "              Afficher les instructions mnémoniques AT&T\n"
 
-#: i386-dis.c:9787
+#: i386-dis.c:9166
 #, c-format
 msgid ""
 "  intel-mnemonic\n"
@@ -439,77 +442,87 @@ msgstr ""
 "  intel-mnemonic\n"
 "              Afficher les instructions mnémoniques Intel\n"
 
-#: i386-dis.c:9789
+#: i386-dis.c:9168
 #, c-format
 msgid "  addr64      Assume 64bit address size\n"
 msgstr "  addr64      Taille des adresses : 64 bits\n"
 
-#: i386-dis.c:9790
+#: i386-dis.c:9169
 #, c-format
 msgid "  addr32      Assume 32bit address size\n"
 msgstr "  addr32      Taille des adresses : 32 bits\n"
 
-#: i386-dis.c:9791
+#: i386-dis.c:9170
 #, c-format
 msgid "  addr16      Assume 16bit address size\n"
 msgstr "  addr16      Taille des adresses : 16 bits\n"
 
-#: i386-dis.c:9792
+#: i386-dis.c:9171
 #, c-format
 msgid "  data32      Assume 32bit data size\n"
 msgstr "  data32       Taille de données : 32 bits\n"
 
-#: i386-dis.c:9793
+#: i386-dis.c:9172
 #, c-format
 msgid "  data16      Assume 16bit data size\n"
 msgstr "  data16      Taille de données : 16 bits\n"
 
-#: i386-dis.c:9794
+#: i386-dis.c:9173
 #, c-format
 msgid "  suffix      Always display instruction suffix in AT&T syntax\n"
 msgstr "  suffix      Toujours afficher les suffixes d'instruction en syntaxe AT&T\n"
 
-#: i386-gen.c:411 ia64-gen.c:307
+#: i386-gen.c:435 ia64-gen.c:307
 #, c-format
 msgid "%s: Error: "
 msgstr "%s : ERREUR : "
 
-#: i386-gen.c:510
+#: i386-gen.c:544
 #, c-format
 msgid "%s: %d: Unknown bitfield: %s\n"
 msgstr "%s: %d: champ de bits inconnu : %s\n"
 
-#: i386-gen.c:674
+#: i386-gen.c:546
+#, c-format
+msgid "Unknown bitfield: %s\n"
+msgstr "Champ de bits inconnu : %s\n"
+
+#: i386-gen.c:602
+#, c-format
+msgid "%s: %d: Missing `)' in bitfield: %s\n"
+msgstr "%s : %d : `)' manquante dans le champ de bits : %s\n"
+
+#: i386-gen.c:867
 #, c-format
 msgid "can't find i386-opc.tbl for reading, errno = %s\n"
 msgstr "impossible de lire i386-opc.tbl, errno = %s\n"
 
-#: i386-gen.c:851
+#: i386-gen.c:998
 #, c-format
 msgid "can't find i386-reg.tbl for reading, errno = %s\n"
 msgstr "impossible de lire i386-reg.tbl, errno = %s\n"
 
-#: i386-gen.c:943
+#: i386-gen.c:1075
 #, c-format
 msgid "can't create i386-init.h, errno = %s\n"
 msgstr "impossible de créer i386-init.h, errno = %s\n"
 
-#: i386-gen.c:1032 ia64-gen.c:2850
+#: i386-gen.c:1164 ia64-gen.c:2820
 #, c-format
 msgid "unable to change directory to \"%s\", errno = %s\n"
 msgstr "incapable de changer de répertoire vers \"%s\", errno = %s\n"
 
-#: i386-gen.c:1039
+#: i386-gen.c:1171
 #, c-format
 msgid "%d unused bits in i386_cpu_flags.\n"
 msgstr "%d bits inutilisés dans i386_cpu_flags.\n"
 
-#: i386-gen.c:1046
+#: i386-gen.c:1178
 #, c-format
 msgid "%d unused bits in i386_operand_type.\n"
 msgstr "%d bits inutilisés dans i386_operand_type.\n"
 
-#: i386-gen.c:1060
+#: i386-gen.c:1192
 #, c-format
 msgid "can't create i386-tbl.h, errno = %s\n"
 msgstr "impossible de créer i386-tbl.h, errno = %s\n"
@@ -519,7 +532,7 @@ msgstr "impossible de cr
 msgid "%s: Warning: "
 msgstr "%s : AVERTISSEMENT : "
 
-#: ia64-gen.c:506 ia64-gen.c:740
+#: ia64-gen.c:506 ia64-gen.c:737
 #, c-format
 msgid "multiple note %s not handled\n"
 msgstr "note multiple %s non gérée\n"
@@ -528,12 +541,12 @@ msgstr "note multiple %s non g
 msgid "can't find ia64-ic.tbl for reading\n"
 msgstr "impossible de trouver ia64-ic.tbl pour la lecture\n"
 
-#: ia64-gen.c:822
+#: ia64-gen.c:819
 #, c-format
 msgid "can't find %s for reading\n"
 msgstr "impossible de trouver %s pour la lecture\n"
 
-#: ia64-gen.c:1046
+#: ia64-gen.c:1043
 #, c-format
 msgid ""
 "most recent format '%s'\n"
@@ -542,77 +555,77 @@ msgstr ""
 "le plus récent format '%s'\n"
 "apparaît plus restrictif que '%s'\n"
 
-#: ia64-gen.c:1057
+#: ia64-gen.c:1054
 #, c-format
 msgid "overlapping field %s->%s\n"
 msgstr "chevauchement de champ %s->%s\n"
 
-#: ia64-gen.c:1254
+#: ia64-gen.c:1251
 #, c-format
 msgid "overwriting note %d with note %d (IC:%s)\n"
 msgstr "écrasement de la note %d par la note %d (IC :%s)\n"
 
-#: ia64-gen.c:1459
+#: ia64-gen.c:1456
 #, c-format
 msgid "don't know how to specify %% dependency %s\n"
 msgstr "Comment spécifier %% pour la dépendance %s ?\n"
 
-#: ia64-gen.c:1481
+#: ia64-gen.c:1478
 #, c-format
 msgid "Don't know how to specify # dependency %s\n"
 msgstr "Impossible de spécifier le n° de dépendance %s\n"
 
-#: ia64-gen.c:1520
+#: ia64-gen.c:1517
 #, c-format
 msgid "IC:%s [%s] has no terminals or sub-classes\n"
 msgstr "IC :%s [%s] n'a pas de terminal ou de sous-classe\n"
 
-#: ia64-gen.c:1523
+#: ia64-gen.c:1520
 #, c-format
 msgid "IC:%s has no terminals or sub-classes\n"
 msgstr "IC :%s n'a pas de terminal ou de sous-classe\n"
 
-#: ia64-gen.c:1532
+#: ia64-gen.c:1529
 #, c-format
 msgid "no insns mapped directly to terminal IC %s [%s]"
 msgstr "aucun instruction mappée directement à l'UC %s [%s]"
 
-#: ia64-gen.c:1535
+#: ia64-gen.c:1532
 #, c-format
 msgid "no insns mapped directly to terminal IC %s\n"
 msgstr "aucun instruction mappée directement à l'UC %s\n"
 
-#: ia64-gen.c:1546
+#: ia64-gen.c:1543
 #, c-format
 msgid "class %s is defined but not used\n"
 msgstr "classe %s définie mais non utilisée\n"
 
-#: ia64-gen.c:1559
+#: ia64-gen.c:1556
 #, c-format
 msgid "Warning: rsrc %s (%s) has no chks\n"
 msgstr "Attention : reg. source %s (%s) sans sélecteur \"chks\"\n"
 
-#: ia64-gen.c:1562
+#: ia64-gen.c:1559
 #, c-format
 msgid "Warning: rsrc %s (%s) has no chks or regs\n"
 msgstr "Attention : reg. source %s (%s) sans sélecteur \"chks\" ou \"regs\"\n"
 
-#: ia64-gen.c:1566
+#: ia64-gen.c:1563
 #, c-format
 msgid "rsrc %s (%s) has no regs\n"
 msgstr "rsrc %s (%s) n'a pas de registres\n"
 
-#: ia64-gen.c:2478
+#: ia64-gen.c:2455
 #, c-format
 msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n"
 msgstr "note IC %d dans l'opcode %s (IC : %s) entrant en conflit avec la ressource %s note %d\n"
 
-#: ia64-gen.c:2506
+#: ia64-gen.c:2483
 #, c-format
 msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n"
 msgstr "note IC %d pour l'opcode %s (IC : %s) entrant en conflit avec la ressource %s note %d\n"
 
-#: ia64-gen.c:2520
+#: ia64-gen.c:2497
 #, c-format
 msgid "opcode %s has no class (ops %d %d %d)\n"
 msgstr "L'opcode %s n'a pas de classe (ops %d %d %d)\n"
@@ -673,7 +686,7 @@ msgstr "Tentative de rep
 msgid "immediate value cannot be register"
 msgstr "La valeur immédiate ne doit pas être un registre"
 
-#: iq2000-asm.c:123 iq2000-asm.c:153
+#: iq2000-asm.c:123 iq2000-asm.c:153 lm32-asm.c:70
 msgid "immediate value out of range"
 msgstr "valeur immédiate hors limites"
 
@@ -681,6 +694,22 @@ msgstr "valeur imm
 msgid "21-bit offset out of range"
 msgstr "décalage de 21 bits hors limites"
 
+#: lm32-asm.c:166
+msgid "expecting gp relative address: gp(symbol)"
+msgstr "adresse relative GP attendue : gp(symbole)"
+
+#: lm32-asm.c:196
+msgid "expecting got relative address: got(symbol)"
+msgstr "adresse relative GOT attendue : got(symbole)"
+
+#: lm32-asm.c:226
+msgid "expecting got relative address: gotoffhi16(symbol)"
+msgstr "adresse relative GOT attendue : gotoffhi16(symbole)"
+
+#: lm32-asm.c:256
+msgid "expecting got relative address: gotofflo16(symbol)"
+msgstr "adresse relative GOT attendue : gotofflo16(symbole)"
+
 #: m10200-dis.c:158 m10300-dis.c:582
 #, c-format
 msgid "unknown\t0x%04lx"
@@ -765,12 +794,12 @@ msgstr "couple r0l/r0h non valide"
 msgid "Invalid size specifier"
 msgstr "Spécifieur de taille non valide"
 
-#: m68k-dis.c:1163
+#: m68k-dis.c:1278
 #, c-format
 msgid "<function code %d>"
 msgstr "<code de fonction %d>"
 
-#: m68k-dis.c:1320
+#: m68k-dis.c:1437
 #, c-format
 msgid "<internal error in opcode table: %s %s>\n"
 msgstr "<erreur interne dans la table des opcodes : %s %s>\n"
@@ -780,39 +809,59 @@ msgstr "<erreur interne dans la table des opcodes : %s %s>\n"
 msgid "# <dis error: %08lx>"
 msgstr "# <erreur désassemblage : %08lx>"
 
-#: mep-asm.c:114
+#: mep-asm.c:129
 msgid "Only $tp or $13 allowed for this opcode"
 msgstr "Seuls $tp ou $13 sont autorisés avec cet opcode"
 
-#: mep-asm.c:128
+#: mep-asm.c:143
 msgid "Only $sp or $15 allowed for this opcode"
 msgstr "Seuls $sp ou $15 sont autorisés avec cet opcode"
 
-#: mep-asm.c:299 mep-asm.c:455
+#: mep-asm.c:308 mep-asm.c:504
 #, c-format
 msgid "invalid %function() here"
 msgstr "%function() non valide ici"
 
-#: mips-dis.c:781
+#: mep-asm.c:336
+msgid "Immediate is out of range -32768 to 32767"
+msgstr "Valeur immédiate hors limites (-32768 à 32767)"
+
+#: mep-asm.c:356
+msgid "Immediate is out of range 0 to 65535"
+msgstr "Valeur immédiate hors limites (0 à 65535)"
+
+#: mep-asm.c:549 mep-asm.c:562
+msgid "Immediate is out of range -512 to 511"
+msgstr "Valeur immédiate hors limites (-512 à 511)"
+
+#: mep-asm.c:554 mep-asm.c:563
+msgid "Immediate is out of range -128 to 127"
+msgstr "Valeur immédiate hors limites (-128 à 127)"
+
+#: mep-asm.c:558
+msgid "Value is not aligned enough"
+msgstr "Valeur mal alignée"
+
+#: mips-dis.c:841
 msgid "# internal error, incomplete extension sequence (+)"
 msgstr "# erreur interne, séquence d'extension incomplète (+)"
 
-#: mips-dis.c:915
+#: mips-dis.c:975
 #, c-format
 msgid "# internal error, undefined extension sequence (+%c)"
 msgstr "# erreur interne, séquence d'extension indéfinie (+%c)"
 
-#: mips-dis.c:1274
+#: mips-dis.c:1335
 #, c-format
 msgid "# internal error, undefined modifier (%c)"
 msgstr "# erreur interne, modificateur non défini (%c)"
 
-#: mips-dis.c:1881
+#: mips-dis.c:1942
 #, c-format
 msgid "# internal disassembler error, unrecognised modifier (%c)"
 msgstr "# erreur interne du désassembleur, modificateur non reconnu (%c)"
 
-#: mips-dis.c:2112
+#: mips-dis.c:2173
 #, c-format
 msgid ""
 "\n"
@@ -823,7 +872,7 @@ msgstr ""
 "Les options spécifiques MIPS du désassembleur sont supportées avec l'utilisation de\n"
 "l'option -M (les options multiples doivent être séparées par des virgules):\n"
 
-#: mips-dis.c:2116
+#: mips-dis.c:2177
 #, c-format
 msgid ""
 "\n"
@@ -834,7 +883,7 @@ msgstr ""
 "  gpr-names=ABI            Afficher les noms GPR selon l'ABI spécifié.\n"
 "                           Par défaut : basé sur le binaire désassemblé.\n"
 
-#: mips-dis.c:2120
+#: mips-dis.c:2181
 #, c-format
 msgid ""
 "\n"
@@ -845,7 +894,7 @@ msgstr ""
 "  fpr-names=ABI            Afficher les noms FPR selon l'ABI spécifié.\n"
 "                           Par défaut : numérique.\n"
 
-#: mips-dis.c:2124
+#: mips-dis.c:2185
 #, c-format
 msgid ""
 "\n"
@@ -858,7 +907,7 @@ msgstr ""
 "                           l'architecture spécifiée.\n"
 "                           Par défaut : basé sur le binaire désassemblé.\n"
 
-#: mips-dis.c:2129
+#: mips-dis.c:2190
 #, c-format
 msgid ""
 "\n"
@@ -871,7 +920,7 @@ msgstr ""
 "\t\t\t   l'architecture spécifiée.\n"
 "                           Par défaut : basé sur le binaire désassemblé.\n"
 
-#: mips-dis.c:2134
+#: mips-dis.c:2195
 #, c-format
 msgid ""
 "\n"
@@ -882,7 +931,7 @@ msgstr ""
 "  reg-names=ABI            Afficher les noms GPR et FPR selon l'ABI\n"
 "                           spécifié.\n"
 
-#: mips-dis.c:2138
+#: mips-dis.c:2199
 #, c-format
 msgid ""
 "\n"
@@ -893,7 +942,7 @@ msgstr ""
 "  reg-names=ARCH           Afficher les noms des registres CP0 et HWR selon\n"
 "                           l'architecture spécifiée.\n"
 
-#: mips-dis.c:2142
+#: mips-dis.c:2203
 #, c-format
 msgid ""
 "\n"
@@ -904,12 +953,12 @@ msgstr ""
 "  Pour les options ci-dessus, les valeurs suivantes sont supportées pour l'\"ABI\":\n"
 "   "
 
-#: mips-dis.c:2147 mips-dis.c:2155 mips-dis.c:2157
+#: mips-dis.c:2208 mips-dis.c:2216 mips-dis.c:2218
 #, c-format
 msgid "\n"
 msgstr "\n"
 
-#: mips-dis.c:2149
+#: mips-dis.c:2210
 #, c-format
 msgid ""
 "\n"
@@ -939,6 +988,15 @@ msgstr "(inconnu)"
 msgid "*unknown operands type: %d*"
 msgstr "*type d'opérande inconnu : %d*"
 
+#: msp430-dis.c:327
+msgid "Illegal as emulation instr"
+msgstr "Non valable comme instr. d'émulation"
+
+#. R2/R3 are illegal as dest: may be data section.
+#: msp430-dis.c:378
+msgid "Illegal as 2-op instr"
+msgstr "Non valable comme instr. 2-op"
+
 #: mt-asm.c:110 mt-asm.c:190
 msgid "Operand out of range. Must be between -32768 and 32767."
 msgstr "Opérande hors limite. Doit être entre -32768 et 32767."
@@ -965,43 +1023,63 @@ msgstr "op
 msgid "$<undefined>"
 msgstr "$<non défini>"
 
-#: ppc-opc.c:862 ppc-opc.c:890
+#: ppc-dis.c:222
+#, c-format
+msgid "warning: ignoring unknown -M%s option\n"
+msgstr "avertissement : option -M%s inconnue ignorée\n"
+
+#: ppc-dis.c:511
+#, c-format
+msgid ""
+"\n"
+"The following PPC specific disassembler options are supported for use with\n"
+"the -M switch:\n"
+msgstr ""
+"\n"
+"Les options spécifiques PPC suivantes sont supportées avec l'utilisation de\n"
+"l'option -M :\n"
+
+#: ppc-opc.c:870 ppc-opc.c:898
 msgid "invalid conditional option"
 msgstr "option conditionnelle non valide"
 
-#: ppc-opc.c:892
+#: ppc-opc.c:900
 msgid "attempt to set y bit when using + or - modifier"
 msgstr "tentative d'initialisation du bit y lors de l'utilisation du modificateur + ou -"
 
-#: ppc-opc.c:924
+#: ppc-opc.c:932
 msgid "invalid mask field"
 msgstr "masque non valide"
 
-#: ppc-opc.c:950
+#: ppc-opc.c:958
 msgid "ignoring invalid mfcr mask"
 msgstr "masque mfcr non valide et ignoré"
 
-#: ppc-opc.c:1000 ppc-opc.c:1035
+#: ppc-opc.c:1008 ppc-opc.c:1043
 msgid "illegal bitmask"
 msgstr "masque de bits illégal"
 
-#: ppc-opc.c:1155
+#: ppc-opc.c:1163
 msgid "index register in load range"
 msgstr "Le registre index n'est pas dans la plage de chargement"
 
-#: ppc-opc.c:1171
+#: ppc-opc.c:1179
 msgid "source and target register operands must be different"
 msgstr "les opérandes des registres source et cible doivent être différents"
 
-#: ppc-opc.c:1186
+#: ppc-opc.c:1194
 msgid "invalid register operand when updating"
 msgstr "opérande registre invalide lors de la mise à jour"
 
-#: ppc-opc.c:1265
+#: ppc-opc.c:1273
 msgid "invalid sprg number"
 msgstr "n° de registre spécial non valide"
 
-#: s390-dis.c:276
+#: ppc-opc.c:1443
+msgid "invalid constant"
+msgstr "constante non valide"
+
+#: s390-dis.c:277
 #, c-format
 msgid ""
 "\n"
@@ -1012,37 +1090,38 @@ msgstr ""
 "Les options spécifiques S/390 du désassembleur sont supportées avec l'utilisation de\n"
 "l'option -M (les options multiples doivent être séparées par des virgules):\n"
 
-#: s390-dis.c:280
+#: s390-dis.c:281
 #, c-format
 msgid "  esa         Disassemble in ESA architecture mode\n"
 msgstr "  esa         Désassemble en mode architecture ESA\n"
 
-#: s390-dis.c:281
+#: s390-dis.c:282
 #, c-format
 msgid "  zarch       Disassemble in z/Architecture mode\n"
 msgstr "  zarch       Désassemble en mode z/Architecture\n"
 
-#: score-dis.c:220 score-dis.c:383
+#: score-dis.c:662 score-dis.c:869 score-dis.c:1030 score-dis.c:1144
+#: score-dis.c:1151 score-dis.c:1158 score7-dis.c:694 score7-dis.c:857
 msgid "<illegal instruction>"
 msgstr "<instruction illégale>"
 
-#: sparc-dis.c:282
+#: sparc-dis.c:283
 #, c-format
 msgid "Internal error:  bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
 msgstr "Erreur interne :  sparc-opcode.h erroné : « %s », %#.8lx, %#.8lx\n"
 
-#: sparc-dis.c:293
+#: sparc-dis.c:294
 #, c-format
 msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
 msgstr "Erreur interne : sparc-opcode.h erroné : « %s », %#.8lx, %#.8lx\n"
 
-#: sparc-dis.c:343
+#: sparc-dis.c:344
 #, c-format
 msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"
 msgstr "Erreur interne : sparc-opcode.h erroné : « %s » == « %s »\n"
 
 #. Mark as non-valid instruction.
-#: sparc-dis.c:1013
+#: sparc-dis.c:1014
 msgid "unknown"
 msgstr "inconnu"
 

diff --git a/opcodes/po/vi.po b/opcodes/po/vi.po
index 35021d2..d842d9d 100644 (file)
--- a/opcodes/po/vi.po
+++ b/opcodes/po/vi.po
@@ -1,21 +1,21 @@
 # Vietnamese Translation for Opcodes.
-# Copyright © 2008 Free Software Foundation, Inc.
+# Copyright © 2009 Free Software Foundation, Inc.
 # This file is distributed under the same license as the binutils package.
-# Clytie Siddall <clytie@riverland.net.au>, 2005-2008.
+# Clytie Siddall <clytie@riverland.net.au>, 2005-2009.
 #
 msgid ""
 msgstr ""
-"Project-Id-Version: opcodes 2.18.90\n"
+"Project-Id-Version: opcodes 2.19.90\n"
 "Report-Msgid-Bugs-To: bug-binutils@gnu.org\n"
-"POT-Creation-Date: 2008-09-09 15:56+0930\n"
-"PO-Revision-Date: 2008-09-23 22:07+0930\n"
+"POT-Creation-Date: 2009-09-07 14:08+0200\n"
+"PO-Revision-Date: 2009-09-17 23:43+0930\n"
 "Last-Translator: Clytie Siddall <clytie@riverland.net.au>\n"
 "Language-Team: Vietnamese <vi-VN@googlegroups.com>\n"
 "MIME-Version: 1.0\n"
 "Content-Type: text/plain; charset=utf-8\n"
 "Content-Transfer-Encoding: 8bit\n"
 "Plural-Forms: nplurals=1; plural=0;\n"
-"X-Generator: LocFactoryEditor 1.7b3\n"
+"X-Generator: LocFactoryEditor 1.8\n"
 
 #: alpha-opc.c:155
 msgid "branch operand unaligned"
@@ -111,23 +111,23 @@ msgstr "địa chỉ nhánh không phải nằm trên ranh giới 4 byte"
 msgid "must specify .jd or no nullify suffix"
 msgstr "phải xác định .jd, không thì không hủy bỏ hậu phương"
 
-#: arm-dis.c:1808
+#: arm-dis.c:1915
 msgid "<illegal precision>"
 msgstr "<độ chính xác cấm>"
 
 #. XXX - should break 'option' at following delimiter.
-#: arm-dis.c:3818
+#: arm-dis.c:4014
 #, c-format
 msgid "Unrecognised register name set: %s\n"
 msgstr "Không nhận ra tập hợp tên thanh ghi: %s\n"
 
 #. XXX - should break 'option' at following delimiter.
-#: arm-dis.c:3826
+#: arm-dis.c:4022
 #, c-format
 msgid "Unrecognised disassembler option: %s\n"
 msgstr "Không nhận ra tùy chọn rã: %s\n"
 
-#: arm-dis.c:4238
+#: arm-dis.c:4519
 #, c-format
 msgid ""
 "\n"
@@ -153,8 +153,9 @@ msgid "unknown constraint `%c'"
 msgstr "không rõ ràng buộc « %c »"
 
 #: cgen-asm.c:336 fr30-ibld.c:200 frv-ibld.c:200 ip2k-ibld.c:200
-#: iq2000-ibld.c:200 m32c-ibld.c:200 m32r-ibld.c:200 mep-ibld.c:200
-#: mt-ibld.c:200 openrisc-ibld.c:200 xc16x-ibld.c:200 xstormy16-ibld.c:200
+#: iq2000-ibld.c:200 lm32-ibld.c:200 m32c-ibld.c:200 m32r-ibld.c:200
+#: mep-ibld.c:200 mt-ibld.c:200 openrisc-ibld.c:200 xc16x-ibld.c:200
+#: xstormy16-ibld.c:200
 #, c-format
 msgid "operand out of range (%ld not between %ld and %ld)"
 msgstr "tác tử ở ngoại phạm vi (%ld không nằm giữa %ld và %ld)"
@@ -197,14 +198,14 @@ msgid "Register list is not valid"
 msgstr "Danh sách thanh ghi không hợp lệ"
 
 #: fr30-asm.c:310 frv-asm.c:1263 ip2k-asm.c:511 iq2000-asm.c:459
-#: m32c-asm.c:1589 m32r-asm.c:328 mep-asm.c:1001 mt-asm.c:595
+#: lm32-asm.c:349 m32c-asm.c:1589 m32r-asm.c:328 mep-asm.c:1287 mt-asm.c:595
 #: openrisc-asm.c:241 xc16x-asm.c:376 xstormy16-asm.c:276
 #, c-format
 msgid "Unrecognized field %d while parsing.\n"
 msgstr "Không nhận ra trường %d trong khi phân tách.\n"
 
 #: fr30-asm.c:361 frv-asm.c:1314 ip2k-asm.c:562 iq2000-asm.c:510
-#: m32c-asm.c:1640 m32r-asm.c:379 mep-asm.c:1052 mt-asm.c:646
+#: lm32-asm.c:400 m32c-asm.c:1640 m32r-asm.c:379 mep-asm.c:1338 mt-asm.c:646
 #: openrisc-asm.c:292 xc16x-asm.c:427 xstormy16-asm.c:327
 msgid "missing mnemonic in syntax string"
 msgstr "thiếu điều giúp trí nhớ trong chuỗi cú pháp"
@@ -213,10 +214,11 @@ msgstr "thiếu điều giúp trí nhớ trong chuỗi cú pháp"
 #: fr30-asm.c:496 fr30-asm.c:500 fr30-asm.c:587 fr30-asm.c:688 frv-asm.c:1449
 #: frv-asm.c:1453 frv-asm.c:1540 frv-asm.c:1641 ip2k-asm.c:697 ip2k-asm.c:701
 #: ip2k-asm.c:788 ip2k-asm.c:889 iq2000-asm.c:645 iq2000-asm.c:649
-#: iq2000-asm.c:736 iq2000-asm.c:837 m32c-asm.c:1775 m32c-asm.c:1779
+#: iq2000-asm.c:736 iq2000-asm.c:837 lm32-asm.c:535 lm32-asm.c:539
+#: lm32-asm.c:626 lm32-asm.c:727 m32c-asm.c:1775 m32c-asm.c:1779
 #: m32c-asm.c:1866 m32c-asm.c:1967 m32r-asm.c:514 m32r-asm.c:518
-#: m32r-asm.c:605 m32r-asm.c:706 mep-asm.c:1187 mep-asm.c:1191 mep-asm.c:1278
-#: mep-asm.c:1379 mt-asm.c:781 mt-asm.c:785 mt-asm.c:872 mt-asm.c:973
+#: m32r-asm.c:605 m32r-asm.c:706 mep-asm.c:1473 mep-asm.c:1477 mep-asm.c:1564
+#: mep-asm.c:1665 mt-asm.c:781 mt-asm.c:785 mt-asm.c:872 mt-asm.c:973
 #: openrisc-asm.c:427 openrisc-asm.c:431 openrisc-asm.c:518 openrisc-asm.c:619
 #: xc16x-asm.c:562 xc16x-asm.c:566 xc16x-asm.c:653 xc16x-asm.c:754
 #: xstormy16-asm.c:462 xstormy16-asm.c:466 xstormy16-asm.c:553
@@ -225,111 +227,111 @@ msgid "unrecognized instruction"
 msgstr "không nhận ra câu lệnh"
 
 #: fr30-asm.c:543 frv-asm.c:1496 ip2k-asm.c:744 iq2000-asm.c:692
-#: m32c-asm.c:1822 m32r-asm.c:561 mep-asm.c:1234 mt-asm.c:828
+#: lm32-asm.c:582 m32c-asm.c:1822 m32r-asm.c:561 mep-asm.c:1520 mt-asm.c:828
 #: openrisc-asm.c:474 xc16x-asm.c:609 xstormy16-asm.c:509
 #, c-format
 msgid "syntax error (expected char `%c', found `%c')"
 msgstr "gặp lỗi cú pháp (mong đợi ký tự « %c », còn tìm « %c »)"
 
 #: fr30-asm.c:553 frv-asm.c:1506 ip2k-asm.c:754 iq2000-asm.c:702
-#: m32c-asm.c:1832 m32r-asm.c:571 mep-asm.c:1244 mt-asm.c:838
+#: lm32-asm.c:592 m32c-asm.c:1832 m32r-asm.c:571 mep-asm.c:1530 mt-asm.c:838
 #: openrisc-asm.c:484 xc16x-asm.c:619 xstormy16-asm.c:519
 #, c-format
 msgid "syntax error (expected char `%c', found end of instruction)"
 msgstr "gặp lỗi cú pháp (ngờ ký tự « %c », còn tìm kết thúc câu lệnh)"
 
 #: fr30-asm.c:581 frv-asm.c:1534 ip2k-asm.c:782 iq2000-asm.c:730
-#: m32c-asm.c:1860 m32r-asm.c:599 mep-asm.c:1272 mt-asm.c:866
+#: lm32-asm.c:620 m32c-asm.c:1860 m32r-asm.c:599 mep-asm.c:1558 mt-asm.c:866
 #: openrisc-asm.c:512 xc16x-asm.c:647 xstormy16-asm.c:547
 msgid "junk at end of line"
 msgstr "gặp rác tại kết thúc dòng"
 
 #: fr30-asm.c:687 frv-asm.c:1640 ip2k-asm.c:888 iq2000-asm.c:836
-#: m32c-asm.c:1966 m32r-asm.c:705 mep-asm.c:1378 mt-asm.c:972
+#: lm32-asm.c:726 m32c-asm.c:1966 m32r-asm.c:705 mep-asm.c:1664 mt-asm.c:972
 #: openrisc-asm.c:618 xc16x-asm.c:753 xstormy16-asm.c:653
 msgid "unrecognized form of instruction"
 msgstr "không nhận ra dạng câu lệnh"
 
 #: fr30-asm.c:699 frv-asm.c:1652 ip2k-asm.c:900 iq2000-asm.c:848
-#: m32c-asm.c:1978 m32r-asm.c:717 mep-asm.c:1390 mt-asm.c:984
+#: lm32-asm.c:738 m32c-asm.c:1978 m32r-asm.c:717 mep-asm.c:1676 mt-asm.c:984
 #: openrisc-asm.c:630 xc16x-asm.c:765 xstormy16-asm.c:665
 #, c-format
 msgid "bad instruction `%.50s...'"
 msgstr "câu lệnh sai « %.50s »"
 
 #: fr30-asm.c:702 frv-asm.c:1655 ip2k-asm.c:903 iq2000-asm.c:851
-#: m32c-asm.c:1981 m32r-asm.c:720 mep-asm.c:1393 mt-asm.c:987
+#: lm32-asm.c:741 m32c-asm.c:1981 m32r-asm.c:720 mep-asm.c:1679 mt-asm.c:987
 #: openrisc-asm.c:633 xc16x-asm.c:768 xstormy16-asm.c:668
 #, c-format
 msgid "bad instruction `%.50s'"
 msgstr "câu lệnh sai « %.50s »"
 
 #. Default text to print if an instruction isn't recognized.
-#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 m32c-dis.c:41
-#: m32r-dis.c:41 mep-dis.c:41 mmix-dis.c:278 mt-dis.c:41 openrisc-dis.c:41
-#: xc16x-dis.c:41 xstormy16-dis.c:41
+#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 lm32-dis.c:41
+#: m32c-dis.c:41 m32r-dis.c:41 mep-dis.c:41 mmix-dis.c:278 mt-dis.c:41
+#: openrisc-dis.c:41 xc16x-dis.c:41 xstormy16-dis.c:41
 msgid "*unknown*"
 msgstr "• không rõ •"
 
-#: fr30-dis.c:299 frv-dis.c:396 ip2k-dis.c:288 iq2000-dis.c:189 m32c-dis.c:891
-#: m32r-dis.c:256 mep-dis.c:776 mt-dis.c:290 openrisc-dis.c:135
-#: xc16x-dis.c:375 xstormy16-dis.c:168
+#: fr30-dis.c:299 frv-dis.c:396 ip2k-dis.c:288 iq2000-dis.c:189 lm32-dis.c:147
+#: m32c-dis.c:891 m32r-dis.c:256 mep-dis.c:1192 mt-dis.c:290
+#: openrisc-dis.c:135 xc16x-dis.c:375 xstormy16-dis.c:168
 #, c-format
 msgid "Unrecognized field %d while printing insn.\n"
 msgstr "Không nhận ra trường %d trong khi in ra câu lệnh.\n"
 
 #: fr30-ibld.c:163 frv-ibld.c:163 ip2k-ibld.c:163 iq2000-ibld.c:163
-#: m32c-ibld.c:163 m32r-ibld.c:163 mep-ibld.c:163 mt-ibld.c:163
-#: openrisc-ibld.c:163 xc16x-ibld.c:163 xstormy16-ibld.c:163
+#: lm32-ibld.c:163 m32c-ibld.c:163 m32r-ibld.c:163 mep-ibld.c:163
+#: mt-ibld.c:163 openrisc-ibld.c:163 xc16x-ibld.c:163 xstormy16-ibld.c:163
 #, c-format
 msgid "operand out of range (%ld not between %ld and %lu)"
 msgstr "tác tử ở ngoại phạm vi (%ld không nằm giữa %ld và %lu)"
 
 #: fr30-ibld.c:184 frv-ibld.c:184 ip2k-ibld.c:184 iq2000-ibld.c:184
-#: m32c-ibld.c:184 m32r-ibld.c:184 mep-ibld.c:184 mt-ibld.c:184
-#: openrisc-ibld.c:184 xc16x-ibld.c:184 xstormy16-ibld.c:184
+#: lm32-ibld.c:184 m32c-ibld.c:184 m32r-ibld.c:184 mep-ibld.c:184
+#: mt-ibld.c:184 openrisc-ibld.c:184 xc16x-ibld.c:184 xstormy16-ibld.c:184
 #, c-format
 msgid "operand out of range (0x%lx not between 0 and 0x%lx)"
 msgstr "tác tử ở ngoại phạm vi (0x%lx không nằm giữa 0 và 0x%lx)"
 
 #: fr30-ibld.c:726 frv-ibld.c:852 ip2k-ibld.c:603 iq2000-ibld.c:709
-#: m32c-ibld.c:1727 m32r-ibld.c:661 mep-ibld.c:1024 mt-ibld.c:745
-#: openrisc-ibld.c:629 xc16x-ibld.c:748 xstormy16-ibld.c:674
+#: lm32-ibld.c:630 m32c-ibld.c:1727 m32r-ibld.c:661 mep-ibld.c:1204
+#: mt-ibld.c:745 openrisc-ibld.c:629 xc16x-ibld.c:748 xstormy16-ibld.c:674
 #, c-format
 msgid "Unrecognized field %d while building insn.\n"
 msgstr "Không nhận ra trường %d trong khi xây dựng câu lệnh.\n"
 
 #: fr30-ibld.c:931 frv-ibld.c:1169 ip2k-ibld.c:678 iq2000-ibld.c:884
-#: m32c-ibld.c:2888 m32r-ibld.c:798 mep-ibld.c:1444 mt-ibld.c:965
-#: openrisc-ibld.c:729 xc16x-ibld.c:968 xstormy16-ibld.c:820
+#: lm32-ibld.c:734 m32c-ibld.c:2888 m32r-ibld.c:798 mep-ibld.c:1803
+#: mt-ibld.c:965 openrisc-ibld.c:729 xc16x-ibld.c:968 xstormy16-ibld.c:820
 #, c-format
 msgid "Unrecognized field %d while decoding insn.\n"
 msgstr "Không nhận ra trường %d trong khi giải mã câu lệnh.\n"
 
 #: fr30-ibld.c:1077 frv-ibld.c:1447 ip2k-ibld.c:752 iq2000-ibld.c:1015
-#: m32c-ibld.c:3505 m32r-ibld.c:911 mep-ibld.c:1737 mt-ibld.c:1165
-#: openrisc-ibld.c:806 xc16x-ibld.c:1189 xstormy16-ibld.c:930
+#: lm32-ibld.c:823 m32c-ibld.c:3505 m32r-ibld.c:911 mep-ibld.c:2273
+#: mt-ibld.c:1165 openrisc-ibld.c:806 xc16x-ibld.c:1189 xstormy16-ibld.c:930
 #, c-format
 msgid "Unrecognized field %d while getting int operand.\n"
 msgstr "Không nhận ra trường %d trong khi lấy tác tử số nguyên.\n"
 
 #: fr30-ibld.c:1205 frv-ibld.c:1707 ip2k-ibld.c:808 iq2000-ibld.c:1128
-#: m32c-ibld.c:4104 m32r-ibld.c:1006 mep-ibld.c:2012 mt-ibld.c:1347
-#: openrisc-ibld.c:865 xc16x-ibld.c:1392 xstormy16-ibld.c:1022
+#: lm32-ibld.c:894 m32c-ibld.c:4104 m32r-ibld.c:1006 mep-ibld.c:2725
+#: mt-ibld.c:1347 openrisc-ibld.c:865 xc16x-ibld.c:1392 xstormy16-ibld.c:1022
 #, c-format
 msgid "Unrecognized field %d while getting vma operand.\n"
 msgstr "Không nhận ra trường %d trong khi lấy tác tử vma.\n"
 
 #: fr30-ibld.c:1336 frv-ibld.c:1974 ip2k-ibld.c:867 iq2000-ibld.c:1248
-#: m32c-ibld.c:4691 m32r-ibld.c:1107 mep-ibld.c:2271 mt-ibld.c:1536
-#: openrisc-ibld.c:931 xc16x-ibld.c:1596 xstormy16-ibld.c:1121
+#: lm32-ibld.c:972 m32c-ibld.c:4691 m32r-ibld.c:1107 mep-ibld.c:3138
+#: mt-ibld.c:1536 openrisc-ibld.c:931 xc16x-ibld.c:1596 xstormy16-ibld.c:1121
 #, c-format
 msgid "Unrecognized field %d while setting int operand.\n"
 msgstr "Không nhận ra trường %d trong khi đặt tác tử số nguyên.\n"
 
 #: fr30-ibld.c:1457 frv-ibld.c:2231 ip2k-ibld.c:916 iq2000-ibld.c:1358
-#: m32c-ibld.c:5268 m32r-ibld.c:1198 mep-ibld.c:2520 mt-ibld.c:1715
-#: openrisc-ibld.c:987 xc16x-ibld.c:1790 xstormy16-ibld.c:1210
+#: lm32-ibld.c:1040 m32c-ibld.c:5268 m32r-ibld.c:1198 mep-ibld.c:3541
+#: mt-ibld.c:1715 openrisc-ibld.c:987 xc16x-ibld.c:1790 xstormy16-ibld.c:1210
 #, c-format
 msgid "Unrecognized field %d while setting vma operand.\n"
 msgstr "Không nhận ra trường %d trong khi đặt tác tử vma.\n"
@@ -352,9 +354,10 @@ msgstr "số thanh ghi phải là số chẵn"
 
 #. -- assembler routines inserted here.
 #. -- asm.c
-#: frv-asm.c:972 iq2000-asm.c:56 m32c-asm.c:141 m32c-asm.c:237 m32c-asm.c:279
-#: m32c-asm.c:338 m32c-asm.c:360 m32r-asm.c:53 mep-asm.c:232 mep-asm.c:250
-#: mep-asm.c:265 mep-asm.c:280 mep-asm.c:292 openrisc-asm.c:54
+#: frv-asm.c:972 iq2000-asm.c:56 lm32-asm.c:95 lm32-asm.c:127 lm32-asm.c:157
+#: lm32-asm.c:187 lm32-asm.c:217 lm32-asm.c:247 m32c-asm.c:141 m32c-asm.c:237
+#: m32c-asm.c:279 m32c-asm.c:338 m32c-asm.c:360 m32r-asm.c:53 mep-asm.c:241
+#: mep-asm.c:259 mep-asm.c:274 mep-asm.c:289 mep-asm.c:301 openrisc-asm.c:54
 msgid "missing `)'"
 msgstr "thiếu dấu ngoặc đóng « ) »"
 
@@ -379,11 +382,11 @@ msgstr "không thể xử lý điều chèn %d\n"
 msgid "%02x\t\t*unknown*"
 msgstr "%02x\t\t • không rõ •"
 
-#: i386-dis.c:9545
+#: i386-dis.c:8924
 msgid "<internal disassembler error>"
 msgstr "<lỗi rã nội bộ>"
 
-#: i386-dis.c:9776
+#: i386-dis.c:9155
 #, c-format
 msgid ""
 "\n"
@@ -394,32 +397,32 @@ msgstr ""
 "Những tùy chọn rã đặc trưng cho i386/x86-64 theo đây được hỗ trợ\n"
 "để sử dụng với đối số « -M » (phân cách nhiều tùy chọn bằng dấu phẩy):\n"
 
-#: i386-dis.c:9780
+#: i386-dis.c:9159
 #, c-format
 msgid "  x86-64      Disassemble in 64bit mode\n"
 msgstr "  x86-64      Rã trong chế độ 64-bit\n"
 
-#: i386-dis.c:9781
+#: i386-dis.c:9160
 #, c-format
 msgid "  i386        Disassemble in 32bit mode\n"
 msgstr "  i386        Rã trong chế độ 32-bit\n"
 
-#: i386-dis.c:9782
+#: i386-dis.c:9161
 #, c-format
 msgid "  i8086       Disassemble in 16bit mode\n"
 msgstr "  i8086       Rã trong chế độ 16-bit\n"
 
-#: i386-dis.c:9783
+#: i386-dis.c:9162
 #, c-format
 msgid "  att         Display instruction in AT&T syntax\n"
 msgstr "  att         Hiển thị câu lệnh theo cú pháp AT&T\n"
 
-#: i386-dis.c:9784
+#: i386-dis.c:9163
 #, c-format
 msgid "  intel       Display instruction in Intel syntax\n"
 msgstr "  intel       Hiển thị câu lệnh theo cú pháp Intel\n"
 
-#: i386-dis.c:9785
+#: i386-dis.c:9164
 #, c-format
 msgid ""
 "  att-mnemonic\n"
@@ -428,7 +431,7 @@ msgstr ""
 "  att-mnemonic\n"
 "              Hiển thị câu lệnh theo điều giúp trí nhớ AT&T\n"
 
-#: i386-dis.c:9787
+#: i386-dis.c:9166
 #, c-format
 msgid ""
 "  intel-mnemonic\n"
@@ -437,77 +440,87 @@ msgstr ""
 "  intel-mnemonic\n"
 "              Hiển thị câu lệnh theo điều giúp trí nhớ Intel\n"
 
-#: i386-dis.c:9789
+#: i386-dis.c:9168
 #, c-format
 msgid "  addr64      Assume 64bit address size\n"
 msgstr "  addr64      Giả sử kích cỡ địa chỉ 64-bit\n"
 
-#: i386-dis.c:9790
+#: i386-dis.c:9169
 #, c-format
 msgid "  addr32      Assume 32bit address size\n"
 msgstr "  addr32      Giả sử kích cỡ địa chỉ 32-bit\n"
 
-#: i386-dis.c:9791
+#: i386-dis.c:9170
 #, c-format
 msgid "  addr16      Assume 16bit address size\n"
 msgstr "  addr16     Giả sử kích cỡ địa chỉ 16-bit\n"
 
-#: i386-dis.c:9792
+#: i386-dis.c:9171
 #, c-format
 msgid "  data32      Assume 32bit data size\n"
 msgstr "  data32      Giả sử kích cỡ dữ liệu 32-bit\n"
 
-#: i386-dis.c:9793
+#: i386-dis.c:9172
 #, c-format
 msgid "  data16      Assume 16bit data size\n"
 msgstr "  data16      Giả sử kích cỡ dữ liệu 16-bit\n"
 
-#: i386-dis.c:9794
+#: i386-dis.c:9173
 #, c-format
 msgid "  suffix      Always display instruction suffix in AT&T syntax\n"
 msgstr "  suffix      Luôn luôn hiển thị hậu tố câu lệnh theo cú pháp AT&T\n"
 
-#: i386-gen.c:411 ia64-gen.c:307
+#: i386-gen.c:435 ia64-gen.c:307
 #, c-format
 msgid "%s: Error: "
 msgstr "%s: Lỗi: "
 
-#: i386-gen.c:510
+#: i386-gen.c:544
 #, c-format
 msgid "%s: %d: Unknown bitfield: %s\n"
 msgstr "%s: %d: Không rõ trường bit: %s\n"
 
-#: i386-gen.c:674
+#: i386-gen.c:546
+#, c-format
+msgid "Unknown bitfield: %s\n"
+msgstr "Không rõ trường bit: %s\n"
+
+#: i386-gen.c:602
+#, c-format
+msgid "%s: %d: Missing `)' in bitfield: %s\n"
+msgstr "%s: %d: Thiếu « ) » trong trường bit: %s\n"
+
+#: i386-gen.c:867
 #, c-format
 msgid "can't find i386-opc.tbl for reading, errno = %s\n"
 msgstr "không tìm thấy i386-opc.tbl để đọc; số thứ tự lỗi = %s\n"
 
-#: i386-gen.c:851
+#: i386-gen.c:998
 #, c-format
 msgid "can't find i386-reg.tbl for reading, errno = %s\n"
 msgstr "không tìm thấy i386-reg.tbl để đọc; số thứ tự lỗi = %s\n"
 
-#: i386-gen.c:943
+#: i386-gen.c:1075
 #, c-format
 msgid "can't create i386-init.h, errno = %s\n"
 msgstr "không thể tạo i386-init.h, số thứ tự lỗi = %s\n"
 
-#: i386-gen.c:1032 ia64-gen.c:2850
+#: i386-gen.c:1164 ia64-gen.c:2820
 #, c-format
 msgid "unable to change directory to \"%s\", errno = %s\n"
 msgstr "không thể chuyển đổi thư mục sang « %s », số lỗi = %s\n"
 
-#: i386-gen.c:1039
+#: i386-gen.c:1171
 #, c-format
 msgid "%d unused bits in i386_cpu_flags.\n"
 msgstr "%d bit chưa dùng trong i386_cpu_flags.\n"
 
-#: i386-gen.c:1046
+#: i386-gen.c:1178
 #, c-format
 msgid "%d unused bits in i386_operand_type.\n"
 msgstr "%d bit chưa dùng trong i386_operand_type.\n"
 
-#: i386-gen.c:1060
+#: i386-gen.c:1192
 #, c-format
 msgid "can't create i386-tbl.h, errno = %s\n"
 msgstr "không thể tạo i386-tbl.h, số thứ tự lỗi = %s\n"
@@ -517,7 +530,7 @@ msgstr "không thể tạo i386-tbl.h, số thứ tự lỗi = %s\n"
 msgid "%s: Warning: "
 msgstr "%s: Cảnh báo : "
 
-#: ia64-gen.c:506 ia64-gen.c:740
+#: ia64-gen.c:506 ia64-gen.c:737
 #, c-format
 msgid "multiple note %s not handled\n"
 msgstr "không xử lý được đa ghi chú %s\n"
@@ -526,12 +539,12 @@ msgstr "không xử lý được đa ghi chú %s\n"
 msgid "can't find ia64-ic.tbl for reading\n"
 msgstr "không tìm thấy ia64-ic.tbl để đọc\n"
 
-#: ia64-gen.c:822
+#: ia64-gen.c:819
 #, c-format
 msgid "can't find %s for reading\n"
 msgstr "không tìm thấy %s để đọc\n"
 
-#: ia64-gen.c:1046
+#: ia64-gen.c:1043
 #, c-format
 msgid ""
 "most recent format '%s'\n"
@@ -540,77 +553,77 @@ msgstr ""
 "định dạng vừa nhất « %s »\n"
 "có vẻ hạn hẹp hơn « %s »\n"
 
-#: ia64-gen.c:1057
+#: ia64-gen.c:1054
 #, c-format
 msgid "overlapping field %s->%s\n"
 msgstr "trường chồng lấp %s -> %s\n"
 
-#: ia64-gen.c:1254
+#: ia64-gen.c:1251
 #, c-format
 msgid "overwriting note %d with note %d (IC:%s)\n"
 msgstr "đang ghi đè lên ghi chú %d bằng ghi chú %d (IC:%s)\n"
 
-#: ia64-gen.c:1459
+#: ia64-gen.c:1456
 #, c-format
 msgid "don't know how to specify %% dependency %s\n"
 msgstr "không biết cách ghi rõ %% quan hệ phụ thuộc %s\n"
 
-#: ia64-gen.c:1481
+#: ia64-gen.c:1478
 #, c-format
 msgid "Don't know how to specify # dependency %s\n"
 msgstr "Không biết cách ghi rõ # quan hệ phụ thuộc %s\n"
 
-#: ia64-gen.c:1520
+#: ia64-gen.c:1517
 #, c-format
 msgid "IC:%s [%s] has no terminals or sub-classes\n"
 msgstr "IC:%s [%s] không có điều mở rộng hoàn thành hay hạng con\n"
 
-#: ia64-gen.c:1523
+#: ia64-gen.c:1520
 #, c-format
 msgid "IC:%s has no terminals or sub-classes\n"
 msgstr "IC:%s không có điều mở rộng hoàn thành hay hạng con\n"
 
-#: ia64-gen.c:1532
+#: ia64-gen.c:1529
 #, c-format
 msgid "no insns mapped directly to terminal IC %s [%s]"
 msgstr "không có câu lệnh được ánh xạ trực tiếp vào IC mở rộng hoàn thành %s [%s]"
 
-#: ia64-gen.c:1535
+#: ia64-gen.c:1532
 #, c-format
 msgid "no insns mapped directly to terminal IC %s\n"
 msgstr "không có câu lệnh được ánh xạ trực tiếp vào IC mở rộng hoàn thành %s\n"
 
-#: ia64-gen.c:1546
+#: ia64-gen.c:1543
 #, c-format
 msgid "class %s is defined but not used\n"
 msgstr "hạng %s được xác định nhưng chưa được dùng\n"
 
-#: ia64-gen.c:1559
+#: ia64-gen.c:1556
 #, c-format
 msgid "Warning: rsrc %s (%s) has no chks\n"
 msgstr "Cảnh báo : rsrc %s (%s) không có chks\n"
 
-#: ia64-gen.c:1562
+#: ia64-gen.c:1559
 #, c-format
 msgid "Warning: rsrc %s (%s) has no chks or regs\n"
 msgstr "Cảnh báo : rsrc %s (%s) không có chks hay regs\n"
 
-#: ia64-gen.c:1566
+#: ia64-gen.c:1563
 #, c-format
 msgid "rsrc %s (%s) has no regs\n"
 msgstr "Tài nguyên %s (%s) không có regs\n"
 
-#: ia64-gen.c:2478
+#: ia64-gen.c:2455
 #, c-format
 msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n"
 msgstr "Ghi chú IC %d trong opcode (mã thao tác) %s (IC:%s) thì xung đột với tài nguyên %s ghi chú %d\n"
 
-#: ia64-gen.c:2506
+#: ia64-gen.c:2483
 #, c-format
 msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n"
 msgstr "Ghi chú IC %d cho opcode (mã thao tác) %s (IC:%s) thì xung đột với tài nguyên %s ghi chú %d\n"
 
-#: ia64-gen.c:2520
+#: ia64-gen.c:2497
 #, c-format
 msgid "opcode %s has no class (ops %d %d %d)\n"
 msgstr "opcode (mã thao tác) %s không có hạng (những tác tử %d %d %d)\n"
@@ -671,7 +684,7 @@ msgstr "Thử tìm ra chỉ mục bit của số 0"
 msgid "immediate value cannot be register"
 msgstr "giá trị trực tiếp không thể là thanh ghi"
 
-#: iq2000-asm.c:123 iq2000-asm.c:153
+#: iq2000-asm.c:123 iq2000-asm.c:153 lm32-asm.c:70
 msgid "immediate value out of range"
 msgstr "giá trị trực tiếp ở ngoại pham vi"
 
@@ -679,6 +692,22 @@ msgstr "giá trị trực tiếp ở ngoại pham vi"
 msgid "21-bit offset out of range"
 msgstr "hiệu 21-bit ở ngoại phạm vi"
 
+#: lm32-asm.c:166
+msgid "expecting gp relative address: gp(symbol)"
+msgstr "mong đợi địa chỉ tương đối với gp: gp(ký_hiệu)"
+
+#: lm32-asm.c:196
+msgid "expecting got relative address: got(symbol)"
+msgstr "mong đợi địa chỉ tương đối với got: got(ký_hiệu)"
+
+#: lm32-asm.c:226
+msgid "expecting got relative address: gotoffhi16(symbol)"
+msgstr "mong đợi địa chỉ tương đối với got: gotoffhi16(ký_hiệu)"
+
+#: lm32-asm.c:256
+msgid "expecting got relative address: gotofflo16(symbol)"
+msgstr "mong đợi địa chỉ tương đối với got: gotofflo16(ký_hiệu)"
+
 #: m10200-dis.c:158 m10300-dis.c:582
 #, c-format
 msgid "unknown\t0x%04lx"
@@ -763,12 +792,12 @@ msgstr "không phải là một cặp « r0l/r0h » hợp lệ"
 msgid "Invalid size specifier"
 msgstr "đặc tả kích cỡ không hợp lệ"
 
-#: m68k-dis.c:1163
+#: m68k-dis.c:1278
 #, c-format
 msgid "<function code %d>"
 msgstr "<mã hàm %d>"
 
-#: m68k-dis.c:1320
+#: m68k-dis.c:1437
 #, c-format
 msgid "<internal error in opcode table: %s %s>\n"
 msgstr "<lỗi nội bộ trong bảng opcode (mã thao tác): %s %s>\n"
@@ -778,39 +807,59 @@ msgstr "<lỗi nội bộ trong bảng opcode (mã thao tác): %s %s>\n"
 msgid "# <dis error: %08lx>"
 msgstr "# <lỗi dis: %08lx>"
 
-#: mep-asm.c:114
+#: mep-asm.c:129
 msgid "Only $tp or $13 allowed for this opcode"
 msgstr "Chỉ cho phép $tp hay $13 cho mã thao tác này"
 
-#: mep-asm.c:128
+#: mep-asm.c:143
 msgid "Only $sp or $15 allowed for this opcode"
 msgstr "Chỉ cho phép $sp hay $15 cho mã thao tác này"
 
-#: mep-asm.c:299 mep-asm.c:455
+#: mep-asm.c:308 mep-asm.c:504
 #, c-format
 msgid "invalid %function() here"
 msgstr "hàm %function() không hợp lệ ở đây"
 
-#: mips-dis.c:781
+#: mep-asm.c:336
+msgid "Immediate is out of range -32768 to 32767"
+msgstr "Điều ngay ở ngoại phạm vi -32768 đến 32767"
+
+#: mep-asm.c:356
+msgid "Immediate is out of range 0 to 65535"
+msgstr "Điều ngay ở ngoại phạm vi 0 đến 65535"
+
+#: mep-asm.c:549 mep-asm.c:562
+msgid "Immediate is out of range -512 to 511"
+msgstr "Điều ngay ở ngoại phạm vi -512 đến 511"
+
+#: mep-asm.c:554 mep-asm.c:563
+msgid "Immediate is out of range -128 to 127"
+msgstr "Điều ngay ở ngoại phạm vi -128 đến 127"
+
+#: mep-asm.c:558
+msgid "Value is not aligned enough"
+msgstr "Giá trị chưa đủ sắp hàng"
+
+#: mips-dis.c:841
 msgid "# internal error, incomplete extension sequence (+)"
 msgstr "# lỗi nội bộ, dãy mở rộng chưa hoàn thành (+)"
 
-#: mips-dis.c:915
+#: mips-dis.c:975
 #, c-format
 msgid "# internal error, undefined extension sequence (+%c)"
 msgstr "# lỗi nội bộ, chưa xác định dãy mở rộng (+%c)"
 
-#: mips-dis.c:1274
+#: mips-dis.c:1335
 #, c-format
 msgid "# internal error, undefined modifier (%c)"
 msgstr "# lỗi nội bộ, chưa xác định điều sửa đổi (%c)"
 
-#: mips-dis.c:1881
+#: mips-dis.c:1942
 #, c-format
 msgid "# internal disassembler error, unrecognised modifier (%c)"
 msgstr "# lỗi rã nội bộ, không nhận ra điều sửa đổi (%c)"
 
-#: mips-dis.c:2112
+#: mips-dis.c:2173
 #, c-format
 msgid ""
 "\n"
@@ -821,7 +870,7 @@ msgstr ""
 "Nững tùy chọn rã đặc trưng cho MIPS theo đây được hỗ trợ để sử dụng\n"
 "với đối số « -M » (phân cách nhiều tùy chọn bằng dấu phẩy):\n"
 
-#: mips-dis.c:2116
+#: mips-dis.c:2177
 #, c-format
 msgid ""
 "\n"
@@ -832,7 +881,7 @@ msgstr ""
 "  gpr-names=ABI            In ra các tên GPR theo ABI đã ghi rõ.\n"
 "                           Mặc định: dựa vào mã nhi phân đang bị rã\n"
 
-#: mips-dis.c:2120
+#: mips-dis.c:2181
 #, c-format
 msgid ""
 "\n"
@@ -843,7 +892,7 @@ msgstr ""
 "  fpr-names=ABI            In ra các tên FPR theo ABI đã ghi rõ.\n"
 "                           Mặc định: thuộc số\n"
 
-#: mips-dis.c:2124
+#: mips-dis.c:2185
 #, c-format
 msgid ""
 "\n"
@@ -855,7 +904,7 @@ msgstr ""
 "  cp0-names=ARCH           In ra các tên CP0 theo kiến trúc đã ghi rõ\n"
 "                           Mặc định: dựa vào mã nhi phân đang bị rã.\n"
 
-#: mips-dis.c:2129
+#: mips-dis.c:2190
 #, c-format
 msgid ""
 "\n"
@@ -867,7 +916,7 @@ msgstr ""
 "  hwr-names=ARCH           In ra các tên HWR theo kiến trúc đã ghi rõ.\n"
 "                           Mặc định: dựa vào mã nhi phân đang bị rã.\n"
 
-#: mips-dis.c:2134
+#: mips-dis.c:2195
 #, c-format
 msgid ""
 "\n"
@@ -877,7 +926,7 @@ msgstr ""
 "\n"
 "  reg-names=ABI            In ra các tên GPR và FPR theo ABI đã ghi rõ.\n"
 
-#: mips-dis.c:2138
+#: mips-dis.c:2199
 #, c-format
 msgid ""
 "\n"
@@ -888,7 +937,7 @@ msgstr ""
 "  reg-names=ARCH\n"
 "\t In ra các tên HWR và thanh ghi CP0 theo kiến trúc đã ghi rõ.\n"
 
-#: mips-dis.c:2142
+#: mips-dis.c:2203
 #, c-format
 msgid ""
 "\n"
@@ -899,12 +948,12 @@ msgstr ""
 "  Đối với các tùy chọn trên, những giá trị theo đây được hỗ trợ cho « ABI »:\n"
 "   "
 
-#: mips-dis.c:2147 mips-dis.c:2155 mips-dis.c:2157
+#: mips-dis.c:2208 mips-dis.c:2216 mips-dis.c:2218
 #, c-format
 msgid "\n"
 msgstr "\n"
 
-#: mips-dis.c:2149
+#: mips-dis.c:2210
 #, c-format
 msgid ""
 "\n"
@@ -934,6 +983,15 @@ msgstr "(không rõ)"
 msgid "*unknown operands type: %d*"
 msgstr "• không rõ kiểu tác tử : %d •"
 
+#: msp430-dis.c:327
+msgid "Illegal as emulation instr"
+msgstr "Không được phép dưới dạng chỉ dẫn mô phỏng"
+
+#. R2/R3 are illegal as dest: may be data section.
+#: msp430-dis.c:378
+msgid "Illegal as 2-op instr"
+msgstr "Không được phép dưới dạng chỉ dẫn 2-op"
+
 #: mt-asm.c:110 mt-asm.c:190
 msgid "Operand out of range. Must be between -32768 and 32767."
 msgstr "Tác tử ở ngoại phạm vi (phải nằm giữa -32768 và +32767."
@@ -960,43 +1018,62 @@ msgstr "tác tử không hợp lệ. kiểu chỉ có thể có giá trị 0,1,2
 msgid "$<undefined>"
 msgstr "$<chưa xác định>"
 
-#: ppc-opc.c:862 ppc-opc.c:890
+#: ppc-dis.c:222
+#, c-format
+msgid "warning: ignoring unknown -M%s option\n"
+msgstr "cảnh báo : đang bở qua tuỳ chọn « -M%s » không rõ\n"
+
+#: ppc-dis.c:511
+#, c-format
+msgid ""
+"\n"
+"The following PPC specific disassembler options are supported for use with\n"
+"the -M switch:\n"
+msgstr ""
+"\n"
+"Những tùy chọn rã đặc trưng cho PPC theo đây được hỗ trợ để sử dụng với đối số « -M »:\n"
+
+#: ppc-opc.c:870 ppc-opc.c:898
 msgid "invalid conditional option"
 msgstr "tùy chọn điều kiện không hợp lệ"
 
-#: ppc-opc.c:892
+#: ppc-opc.c:900
 msgid "attempt to set y bit when using + or - modifier"
 msgstr "thử đặt « bit y » khi sử dụng điều sửa đổi + hay -"
 
-#: ppc-opc.c:924
+#: ppc-opc.c:932
 msgid "invalid mask field"
 msgstr "trường mặt nạ không hợp lệ"
 
-#: ppc-opc.c:950
+#: ppc-opc.c:958
 msgid "ignoring invalid mfcr mask"
 msgstr "đang bỏ qua mặt nạ mfcr không hợp lệ"
 
-#: ppc-opc.c:1000 ppc-opc.c:1035
+#: ppc-opc.c:1008 ppc-opc.c:1043
 msgid "illegal bitmask"
 msgstr "gặp mặt nặ bit cấm"
 
-#: ppc-opc.c:1155
+#: ppc-opc.c:1163
 msgid "index register in load range"
 msgstr "thanh ghi cơ số trong phạm vi nạp"
 
-#: ppc-opc.c:1171
+#: ppc-opc.c:1179
 msgid "source and target register operands must be different"
 msgstr "tác tử thanh ghi kiểu nguồn và đích phải là khác nhau"
 
-#: ppc-opc.c:1186
+#: ppc-opc.c:1194
 msgid "invalid register operand when updating"
 msgstr "gặp tác tử thanh ghi không hợp lệ khi cập nhật"
 
-#: ppc-opc.c:1265
+#: ppc-opc.c:1273
 msgid "invalid sprg number"
 msgstr "số sprg không hợp lệ"
 
-#: s390-dis.c:276
+#: ppc-opc.c:1443
+msgid "invalid constant"
+msgstr "hằng không hợp lệ"
+
+#: s390-dis.c:277
 #, c-format
 msgid ""
 "\n"
@@ -1007,37 +1084,38 @@ msgstr ""
 "Theo đây có những tùy chọn rã đặc trưng cho S/390 được hỗ trợ để sử dụng\n"
 "với đối số « -M » (phân cách nhiều tùy chọn bằng dấu phẩy):\n"
 
-#: s390-dis.c:280
+#: s390-dis.c:281
 #, c-format
 msgid "  esa         Disassemble in ESA architecture mode\n"
 msgstr "  esa         Rã ở chế độ kiến trúc ESA\n"
 
-#: s390-dis.c:281
+#: s390-dis.c:282
 #, c-format
 msgid "  zarch       Disassemble in z/Architecture mode\n"
 msgstr "  zarch       Rã ở chế độ z/kiến trúc\n"
 
-#: score-dis.c:220 score-dis.c:383
+#: score-dis.c:662 score-dis.c:869 score-dis.c:1030 score-dis.c:1144
+#: score-dis.c:1151 score-dis.c:1158 score7-dis.c:694 score7-dis.c:857
 msgid "<illegal instruction>"
 msgstr "<độ chính xác cấm>"
 
-#: sparc-dis.c:282
+#: sparc-dis.c:283
 #, c-format
 msgid "Internal error:  bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
 msgstr "Lỗi nội bộ : sparc-opcode.h sai: « %s », %#.8lx, %#.8lx\n"
 
-#: sparc-dis.c:293
+#: sparc-dis.c:294
 #, c-format
 msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
 msgstr "Lỗi nội bộ : sparc-opcode.h sai: « %s », %#.8lx, %#.8lx\n"
 
-#: sparc-dis.c:343
+#: sparc-dis.c:344
 #, c-format
 msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"
 msgstr "Lỗi nội bộ : sparc-opcode.h sai: « %s » == \"%s\"\n"
 
 #. Mark as non-valid instruction.
-#: sparc-dis.c:1013
+#: sparc-dis.c:1014
 msgid "unknown"
 msgstr "không rõ"
 

diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index 8511345..ac88f76 100644 (file)
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -62,6 +62,10 @@ struct ppc_mopt ppc_opts[] = {
   { "464",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_32
                | PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
     0 },
+  { "476",     (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ISEL
+               | PPC_OPCODE_440 | PPC_OPCODE_476 | PPC_OPCODE_POWER4
+               | PPC_OPCODE_POWER5),
+    0 },
   { "601",     (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_601
                | PPC_OPCODE_32),
     0 },
@@ -141,6 +145,10 @@ struct ppc_mopt ppc_opts[] = {
   { "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64_BRIDGE
                    | PPC_OPCODE_64),
     0 },
+  { "a2",      (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ISEL
+               | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK
+               | PPC_OPCODE_64 | PPC_OPCODE_A2),
+    0 },
   { "ppcps",   (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS),
     0 },
   { "pwr",     (PPC_OPCODE_POWER | PPC_OPCODE_32),

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 1a69d33..123436c 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -638,6 +638,9 @@ const struct powerpc_operand powerpc_operands[] =
   /* The UIM field in an XX2 form instruction.  */
 #define UIM DMEX + 1
   { 0x3, 16, NULL, NULL, 0 },
+
+#define ERAT_T UIM + 1
+  { 0x7, 21, NULL, NULL, 0 },
 };
 
 const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@@ -1621,6 +1624,9 @@ extract_dm (unsigned long insn,
 /* The mask for an X form instruction.  */
 #define X_MASK XRC (0x3f, 0x3ff, 1)
 
+/* An X form wait instruction with everything filled in except the WC field.  */
+#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
+
 /* The mask for an XX1 form instruction.  */
 #define XX1_MASK X (0x3f, 0x3ff)
 
@@ -1683,6 +1689,9 @@ extract_dm (unsigned long insn,
 /* An X form instruction with the L bit specified.  */
 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
 
+/* An X form instruction with the L bits specified.  */
+#define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
+
 /* An X form instruction with RT fields specified */
 #define XRT(op, xop, rt) (X ((op), (xop)) \
         | ((((unsigned long)(rt)) & 0x1f) << 21))
@@ -1897,6 +1906,7 @@ extract_dm (unsigned long insn,
 #define PPC405 PPC_OPCODE_405
 #define PPC440 PPC_OPCODE_440
 #define PPC464 PPC440
+#define PPC476 PPC_OPCODE_476
 #define PPC750 PPC
 #define PPC7450 PPC
 #define PPC860 PPC
@@ -1924,6 +1934,7 @@ extract_dm (unsigned long insn,
 #define PPCCHLK PPC_OPCODE_CACHELCK
 #define PPCRFMCI       PPC_OPCODE_RFMCI
 #define E500MC  PPC_OPCODE_E500MC
+#define PPCA2  PPC_OPCODE_A2
 \f
 /* The opcode table.
 
@@ -1947,7 +1958,7 @@ extract_dm (unsigned long insn,
    constrained otherwise by disassembler operation.  */
 
 const struct powerpc_opcode powerpc_opcodes[] = {
-{"attn",       X(0,256),       X_MASK,      POWER4,    PPCNONE,        {0}},
+{"attn",       X(0,256),       X_MASK,   POWER4|PPCA2, PPC476,         {0}},
 {"tdlgti",     OPTO(2,TOLGT),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
 {"tdllti",     OPTO(2,TOLLT),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
 {"tdeqi",      OPTO(2,TOEQ),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
@@ -2373,8 +2384,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evmhessf",   VX (4,1027),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"vand",       VX (4,1028),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"vcmpequb.",  VXR(4,   6,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
-{"udi0fcm.",   APU(4, 515,0), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},
-{"udi0fcm",    APU(4, 515,1), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},
+{"udi0fcm.",   APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
+{"udi0fcm",    APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
 {"evmhossf",   VX (4,1031),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evmheumi",   VX (4,1032),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evmhesmi",   VX (4,1033),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
@@ -2400,8 +2411,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"vavguh",     VX (4,1090),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"vandc",      VX (4,1092),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"vcmpequh.",  VXR(4,  70,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
-{"udi1fcm.",   APU(4, 547,0), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},
-{"udi1fcm",    APU(4, 547,1), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},   
+{"udi1fcm.",   APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
+{"udi1fcm",    APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},   
 {"evmwhssf",   VX (4,1095),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evmwlumi",   VX (4,1096),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"vminfp",     VX (4,1098),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
@@ -2432,8 +2443,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"vavguw",     VX (4,1154),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"vor",                VX (4,1156),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"vcmpequw.",  VXR(4, 134,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
-{"udi2fcm.",   APU(4, 579,0), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},
-{"udi2fcm",    APU(4, 579,1), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},   
+{"udi2fcm.",   APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
+{"udi2fcm",    APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},   
 {"machhwsuo",  XO (4,  76,1,0),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
 {"machhwsuo.", XO (4,  76,1,1),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
 {"ps_merge10", XOPS(4,592,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
@@ -2446,8 +2457,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"vxor",       VX (4,1220),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"evdivws",    VX (4,1222),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"vcmpeqfp.",  VXR(4, 198,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
-{"udi3fcm.",   APU(4, 611,0), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},
-{"udi3fcm",    APU(4, 611,1), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},   
+{"udi3fcm.",   APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
+{"udi3fcm",    APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},   
 {"evdivwu",    VX (4,1223),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evaddumiaaw",        VX (4,1224),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
 {"evaddsmiaaw",        VX (4,1225),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
@@ -2466,8 +2477,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evmhousiaaw",        VX (4,1284),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"vnor",       VX (4,1284),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"evmhossiaaw",        VX (4,1285),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
-{"udi4fcm.",   APU(4, 643,0), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},
-{"udi4fcm",    APU(4, 643,1), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},
+{"udi4fcm.",   APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
+{"udi4fcm",    APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
 {"evmhossfaaw",        VX (4,1287),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evmheumiaaw",        VX (4,1288),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evmhesmiaaw",        VX (4,1289),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
@@ -2486,8 +2497,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evmwlusiaaw",        VX (4,1344),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evmwlssiaaw",        VX (4,1345),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"vavgsh",     VX (4,1346),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
-{"udi5fcm.",   APU(4, 675,0), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},
-{"udi5fcm",    APU(4, 675,1), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},
+{"udi5fcm.",   APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
+{"udi5fcm",    APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
 {"evmwlumiaaw",        VX (4,1352),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evmwlsmiaaw",        VX (4,1353),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evmwssfaa",  VX (4,1363),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
@@ -2505,8 +2516,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evmhessfanw",        VX (4,1411),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evmhousianw",        VX (4,1412),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evmhossianw",        VX (4,1413),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
-{"udi6fcm.",   APU(4, 707,0), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},
-{"udi6fcm",    APU(4, 707,1), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},
+{"udi6fcm.",   APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
+{"udi6fcm",    APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
 {"evmhossfanw",        VX (4,1415),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evmheumianw",        VX (4,1416),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evmhesmianw",        VX (4,1417),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
@@ -2525,8 +2536,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evmwlusianw",        VX (4,1472),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evmwlssianw",        VX (4,1473),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"vcmpgefp.",  VXR(4, 454,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
-{"udi7fcm.",   APU(4, 739,0), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},
-{"udi7fcm",    APU(4, 739,1), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},
+{"udi7fcm.",   APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
+{"udi7fcm",    APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
 {"evmwlumianw",        VX (4,1480),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evmwlsmianw",        VX (4,1481),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evmwssfan",  VX (4,1491),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
@@ -2540,48 +2551,48 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"vsububs",    VX (4,1536),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"mfvscr",     VX (4,1540),    VX_MASK,     PPCVEC,    PPCNONE,        {VD}},
 {"vcmpgtub.",  VXR(4, 518,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
-{"udi8fcm.",   APU(4, 771,0),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
-{"udi8fcm",    APU(4, 771,1),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
+{"udi8fcm.",   APU(4, 771,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
+{"udi8fcm",    APU(4, 771,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
 {"vsum4ubs",   VX (4,1544),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"vsubuhs",    VX (4,1600),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"mtvscr",     VX (4,1604),    VX_MASK,     PPCVEC,    PPCNONE,        {VB}},
 {"vcmpgtuh.",  VXR(4, 582,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"vsum4shs",   VX (4,1608),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
-{"udi9fcm.",   APU(4, 804,0),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
-{"udi9fcm",    APU(4, 804,1),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
+{"udi9fcm.",   APU(4, 804,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
+{"udi9fcm",    APU(4, 804,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
 {"vsubuws",    VX (4,1664),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"vcmpgtuw.",  VXR(4, 646,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
-{"udi10fcm.",  APU(4, 835,0),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
-{"udi10fcm",   APU(4, 835,1),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
+{"udi10fcm.",  APU(4, 835,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
+{"udi10fcm",   APU(4, 835,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
 {"vsum2sws",   VX (4,1672),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"vcmpgtfp.",  VXR(4, 710,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
-{"udi11fcm.",  APU(4, 867,0),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
-{"udi11fcm",   APU(4, 867,1),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
+{"udi11fcm.",  APU(4, 867,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
+{"udi11fcm",   APU(4, 867,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
 {"vsubsbs",    VX (4,1792),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"vcmpgtsb.",  VXR(4, 774,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
-{"udi12fcm.",  APU(4, 899,0),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
-{"udi12fcm",   APU(4, 899,1),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
+{"udi12fcm.",  APU(4, 899,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
+{"udi12fcm",   APU(4, 899,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
 {"vsum4sbs",   VX (4,1800),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"maclhwuo",   XO (4, 396,1,0),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
 {"maclhwuo.",  XO (4, 396,1,1),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
 {"vsubshs",    VX (4,1856),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"vcmpgtsh.",  VXR(4, 838,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
-{"udi13fcm.",  APU(4, 931,0),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
-{"udi13fcm",   APU(4, 931,1),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
+{"udi13fcm.",  APU(4, 931,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
+{"udi13fcm",   APU(4, 931,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
 {"maclhwo",    XO (4, 428,1,0),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
 {"maclhwo.",   XO (4, 428,1,1),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
 {"nmaclhwo",   XO (4, 430,1,0),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
 {"nmaclhwo.",  XO (4, 430,1,1),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
 {"vsubsws",    VX (4,1920),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"vcmpgtsw.",  VXR(4, 902,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
-{"udi14fcm.",  APU(4, 963,0),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
-{"udi14fcm",   APU(4, 963,1),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
+{"udi14fcm.",  APU(4, 963,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
+{"udi14fcm",   APU(4, 963,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
 {"vsumsws",    VX (4,1928),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"maclhwsuo",  XO (4, 460,1,0),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
 {"maclhwsuo.", XO (4, 460,1,1),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
 {"vcmpbfp.",   VXR(4, 966,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
-{"udi15fcm.",  APU(4, 995,0),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
-{"udi15fcm",   APU(4, 995,1),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
+{"udi15fcm.",  APU(4, 995,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
+{"udi15fcm",   APU(4, 995,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
 {"maclhwso",   XO (4, 492,1,0),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
 {"maclhwso.",  XO (4, 492,1,1),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
 {"nmaclhwso",  XO (4, 494,1,0),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
@@ -3140,15 +3151,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"crnot",      XL(19,33),      XL_MASK,     PPCCOM,    PPCNONE,        {BT, BA, BBA}},
 {"crnor",      XL(19,33),      XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
-{"rfmci",      X(19,38),       0xffffffff,  PPCRFMCI,  PPCNONE,        {0}},
+{"rfmci",      X(19,38),   0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCNONE, {0}},
 
 {"rfdi",       XL(19,39),      0xffffffff,  E500MC,    PPCNONE,        {0}},
 {"rfi",                XL(19,50),      0xffffffff,  COM,       PPCNONE,        {0}},
-{"rfci",       XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300, PPCNONE,   {0}},
+{"rfci",       XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCNONE, {0}},
 
 {"rfsvc",      XL(19,82),      0xffffffff,  POWER,     PPCNONE,        {0}},
 
-{"rfgi",       XL(19,102),     0xffffffff,  E500MC,    PPCNONE,        {0}},
+{"rfgi",       XL(19,102),   0xffffffff, E500MC|PPCA2, PPCNONE,        {0}},
 
 {"crandc",     XL(19,129),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
 
@@ -3164,7 +3175,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"crand",      XL(19,257),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
 
-{"hrfid",      XL(19,274),     0xffffffff, POWER5|CELL, PPCNONE,       {0}},
+{"hrfid",      XL(19,274),     0xffffffff, POWER5|CELL, PPC476,        {0}},
 
 {"crset",      XL(19,289),     XL_MASK,     PPCCOM,    PPCNONE,        {BT, BAT, BBA}},
 {"creqv",      XL(19,289),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
@@ -3464,10 +3475,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"isellt",     X(31,15),       X_MASK,      PPCISEL,   PPCNONE,        {RT, RA, RB}},
 
-{"tlbilxlpid", XTO(31,18,0),   XTO_MASK,    E500MC,    PPCNONE,        {0}},
-{"tlbilxpid",  XTO(31,18,1),   XTO_MASK,    E500MC,    PPCNONE,        {0}},
-{"tlbilxva",   XTO(31,18,3),   XTO_MASK,    E500MC,    PPCNONE,        {RA0, RB}},
-{"tlbilx",     X(31,18),       X_MASK,      E500MC,    PPCNONE,        {T, RA0, RB}},
+{"tlbilxlpid", XTO(31,18,0),   XTO_MASK, E500MC|PPCA2, PPCNONE,        {0}},
+{"tlbilxpid",  XTO(31,18,1),   XTO_MASK, E500MC|PPCA2, PPCNONE,        {0}},
+{"tlbilxva",   XTO(31,18,3),   XTO_MASK, E500MC|PPCA2, PPCNONE,        {RA0, RB}},
+{"tlbilx",     X(31,18),       X_MASK,   E500MC|PPCA2, PPCNONE,        {T, RA0, RB}},
 
 {"mfcr",       XFXM(31,19,0,0), XFXFXM_MASK, POWER4,   PPCNONE,        {RT, FXM4}},
 {"mfcr",       XFXM(31,19,0,0), XRARB_MASK, COM,       POWER4,         {RT}},
@@ -3477,7 +3488,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"ldx",                X(31,21),       X_MASK,      PPC64,     PPCNONE,        {RT, RA0, RB}},
 
-{"icbt",       X(31,22),       X_MASK,  BOOKE|PPCE300, PPCNONE,        {CT, RA, RB}},
+{"icbt",       X(31,22),       X_MASK, BOOKE|PPCE300|PPCA2|PPC476, PPCNONE, {CT, RA, RB}},
 
 {"lwzx",       X(31,23),       X_MASK,      PPCCOM,    PPCNONE,        {RT, RA0, RB}},
 {"lx",         X(31,23),       X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
@@ -3498,11 +3509,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"and",                XRC(31,28,0),   X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
 {"and.",       XRC(31,28,1),   X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
 
-{"maskg",      XRC(31,29,0),   X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
-{"maskg.",     XRC(31,29,1),   X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
+{"maskg",      XRC(31,29,0),   X_MASK,      M601,      PPCA2,          {RA, RS, RB}},
+{"maskg.",     XRC(31,29,1),   X_MASK,      M601,      PPCA2,          {RA, RS, RB}},
 
-{"ldepx",      X(31,29),       X_MASK,      E500MC,    PPCNONE,        {RT, RA, RB}},
-{"lwepx",      X(31,31),       X_MASK,      E500MC,    PPCNONE,        {RT, RA, RB}},
+{"ldepx",      X(31,29),       X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
+{"lwepx",      X(31,31),       X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
 
 {"cmplw",      XOPL(31,32,0),  XCMPL_MASK,  PPCCOM,    PPCNONE,        {OBF, RA, RB}},
 {"cmpld",      XOPL(31,32,1),  XCMPL_MASK,  PPC64,     PPCNONE,        {OBF, RA, RB}},
@@ -3528,6 +3539,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"subf.",      XO(31,40,0,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
 {"sub.",       XO(31,40,0,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
 
+{"eratilx",    X(31,51),       X_MASK,      PPCA2,     PPCNONE,        {ERAT_T, RA, RB}},
+
 {"lbarx",      X(31,52),       XEH_MASK,    POWER7,    PPCNONE,        {RT, RA0, RB, EH}},
 
 {"ldux",       X(31,53),       X_MASK,      PPC64,     PPCNONE,        {RT, RAL, RB}},
@@ -3543,11 +3556,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"andc",       XRC(31,60,0),   X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
 {"andc.",      XRC(31,60,1),   X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
 
-{"waitrsv",    X(31,62)|(1<<21), 0xffffffff, POWER7|E500MC, PPCNONE,   {0}},
-{"waitimpl",   X(31,62)|(2<<21), 0xffffffff, POWER7|E500MC, PPCNONE,   {0}},
-{"wait",       X(31,62),       XWC_MASK, POWER7|E500MC, PPCNONE,       {WC}},
+{"waitrsv",    X(31,62)|(1<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
+{"waitimpl",   X(31,62)|(2<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
+{"wait",       X(31,62),         XWC_MASK,   POWER7|E500MC|PPCA2, PPCNONE, {WC}},
 
-{"dcbstep",    XRT(31,63,0),   XRT_MASK,    E500MC,    PPCNONE,        {RA, RB}},
+{"dcbstep",    XRT(31,63,0),   XRT_MASK, E500MC|PPCA2, PPCNONE,        {RA, RB}},
 
 {"tdlgt",      XTO(31,68,TOLGT), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
 {"tdllt",      XTO(31,68,TOLLT), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
@@ -3581,12 +3594,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"ldarx",      X(31,84),       XEH_MASK,    PPC64,     PPCNONE,        {RT, RA0, RB, EH}},
 
-{"dcbfl",      XOPL(31,86,1),  XRT_MASK,    POWER5,    PPCNONE,        {RA, RB}},
+{"dcbfl",      XOPL(31,86,1),  XRT_MASK,    POWER5,    PPC476,         {RA, RB}},
 {"dcbf",       X(31,86),       XLRT_MASK,   PPC,       PPCNONE,        {RA, RB, L}},
 
 {"lbzx",       X(31,87),       X_MASK,      COM,       PPCNONE,        {RT, RA0, RB}},
 
-{"lbepx",      X(31,95),       X_MASK,      E500MC,    PPCNONE,        {RT, RA, RB}},
+{"lbepx",      X(31,95),       X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
 
 {"lvx",                X(31,103),      X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
 {"lqfcmx",     APU(31,103,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
@@ -3612,11 +3625,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"not.",       XRC(31,124,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RBS}},
 {"nor.",       XRC(31,124,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
 
-{"dcbfep",     XRT(31,127,0),  XRT_MASK,    E500MC,    PPCNONE,        {RA, RB}},
+{"dcbfep",     XRT(31,127,0),  XRT_MASK, E500MC|PPCA2, PPCNONE,        {RA, RB}},
 
-{"wrtee",      X(31,131),      XRARB_MASK, PPC403|BOOKE, PPCNONE,      {RS}},
+{"wrtee",      X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RS}},
 
-{"dcbtstls",   X(31,134),      X_MASK,      PPCCHLK,   PPCNONE,        {CT, RA, RB}},
+{"dcbtstls",   X(31,134),      X_MASK, PPCCHLK|PPC476, PPCNONE,        {CT, RA, RB}},
 
 {"stvebx",     X(31,135),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA, RB}},
 {"stbfcmx",    APU(31,135,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
@@ -3639,6 +3652,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"mtmsr",      X(31,146),      XRLARB_MASK, COM,       PPCNONE,        {RS, A_L}},
 
+{"eratsx",     XRC(31,147,0),  X_MASK,      PPCA2,     PPCNONE,        {RT, RA0, RB}},
+{"eratsx.",    XRC(31,147,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, RA0, RB}},
+
 {"stdx",       X(31,149),      X_MASK,      PPC64,     PPCNONE,        {RS, RA0, RB}},
 
 {"stwcx.",     XRC(31,150,1),  X_MASK,      PPC,       PPCNONE,        {RS, RA0, RB}},
@@ -3652,15 +3668,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"sle",                XRC(31,153,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
 {"sle.",       XRC(31,153,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
 
-{"prtyw",      X(31,154),      XRB_MASK,    POWER6,    PPCNONE,        {RA, RS}},
+{"prtyw",      X(31,154),      XRB_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS}},
 
-{"stdepx",     X(31,157),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
+{"stdepx",     X(31,157),      X_MASK,   E500MC|PPCA2, PPCNONE,        {RS, RA, RB}},
 
-{"stwepx",     X(31,159),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
+{"stwepx",     X(31,159),      X_MASK,   E500MC|PPCA2, PPCNONE,        {RS, RA, RB}},
 
-{"wrteei",     X(31,163),      XE_MASK,  PPC403|BOOKE, PPCNONE,        {E}},
+{"wrteei",     X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {E}},
 
-{"dcbtls",     X(31,166),      X_MASK,      PPCCHLK,   PPCNONE,        {CT, RA, RB}},
+{"dcbtls",     X(31,166),      X_MASK, PPCCHLK|PPC476, PPCNONE,        {CT, RA, RB}},
 
 {"stvehx",     X(31,167),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA, RB}},
 {"sthfcmx",    APU(31,167,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
@@ -3669,15 +3685,19 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"mtmsrd",     X(31,178),      XRLARB_MASK, PPC64,     PPCNONE,        {RS, A_L}},
 
+{"eratre",     X(31,179),      X_MASK,      PPCA2,     PPCNONE,        {RT, RA, WS}},
+
 {"stdux",      X(31,181),      X_MASK,      PPC64,     PPCNONE,        {RS, RAS, RB}},
 
+{"wchkall",    X(31,182),      X_MASK,      PPCA2,     PPCNONE,        {OBF}},
+
 {"stwux",      X(31,183),      X_MASK,      PPCCOM,    PPCNONE,        {RS, RAS, RB}},
 {"stux",       X(31,183),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, RB}},
 
 {"sliq",       XRC(31,184,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
 {"sliq.",      XRC(31,184,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
 
-{"prtyd",      X(31,186),      XRB_MASK,    POWER6,    PPCNONE,        {RA, RS}},
+{"prtyd",      X(31,186),      XRB_MASK, POWER6|PPCA2, PPCNONE,        {RA, RS}},
 
 {"stvewx",     X(31,199),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA, RB}},
 {"stwfcmx",    APU(31,199,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
@@ -3692,10 +3712,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"addze.",     XO(31,202,0,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
 {"aze.",       XO(31,202,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
 
-{"msgsnd",     XRTRA(31,206,0,0),XRTRA_MASK,E500MC,    PPCNONE,        {RB}},
+{"msgsnd",     XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2, PPCNONE,   {RB}},
 
 {"mtsr",       X(31,210), XRB_MASK|(1<<20), COM32,     PPCNONE,        {SR, RS}},
 
+{"eratwe",     X(31,211),      X_MASK,      PPCA2,     PPCNONE,        {RS, RA, WS}},
+
+{"ldawx.",     XRC(31,212,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, RA0, RB}},
+
 {"stdcx.",     XRC(31,214,1),  X_MASK,      PPC64,     PPCNONE,        {RS, RA0, RB}},
 
 {"stbx",       X(31,215),      X_MASK,      COM,       PPCNONE,        {RS, RA0, RB}},
@@ -3706,9 +3730,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"sleq",       XRC(31,217,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
 {"sleq.",      XRC(31,217,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
 
-{"stbepx",     X(31,223),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
+{"stbepx",     X(31,223),      X_MASK,   E500MC|PPCA2, PPCNONE,        {RS, RA, RB}},
 
-{"icblc",      X(31,230),      X_MASK,      PPCCHLK,   PPCNONE,        {CT, RA, RB}},
+{"icblc",      X(31,230),      X_MASK, PPCCHLK|PPC476, PPCNONE,        {CT, RA, RB}},
 
 {"stvx",       X(31,231),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA, RB}},
 {"stqfcmx",    APU(31,231,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
@@ -3731,8 +3755,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mullw.",     XO(31,235,0,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
 {"muls.",      XO(31,235,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
 
-{"icblce",     X(31,238),      X_MASK,      PPCCHLK,   E500MC,         {CT, RA, RB}},
-{"msgclr",     XRTRA(31,238,0,0),XRTRA_MASK,E500MC,    PPCNONE,        {RB}},
+{"icblce",     X(31,238),      X_MASK,      PPCCHLK,   E500MC|PPCA2,   {CT, RA, RB}},
+{"msgclr",     XRTRA(31,238,0,0),XRTRA_MASK,E500MC|PPCA2, PPCNONE,     {RB}},
 {"mtsrin",     X(31,242),      XRA_MASK,    PPC32,     PPCNONE,        {RS, RB}},
 {"mtsri",      X(31,242),      XRA_MASK,    POWER32,   PPCNONE,        {RS, RB}},
 
@@ -3745,11 +3769,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"slliq",      XRC(31,248,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
 {"slliq.",     XRC(31,248,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
 
-{"bpermd",     X(31,252),      X_MASK,      POWER7,    PPCNONE,        {RA, RS, RB}},
+{"bpermd",     X(31,252),      X_MASK,   POWER7|PPCA2, PPCNONE,        {RA, RS, RB}},
 
-{"dcbtstep",   XRT(31,255,0),  X_MASK,      E500MC,    PPCNONE,        {RT, RA, RB}},
+{"dcbtstep",   XRT(31,255,0),  X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
 
-{"mfdcrx",     X(31,259),      X_MASK,      BOOKE,     PPCNONE,        {RS, RA}},
+{"mfdcrx",     X(31,259),      X_MASK, BOOKE|PPCA2|PPC476, PPCNONE,    {RS, RA}},
+{"mfdcrx.",    XRC(31,259,1),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA}},
 
 {"icbt",       X(31,262),      XRT_MASK,    PPC403,    PPCNONE,        {RA, RB}},
 
@@ -3762,9 +3787,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"add.",       XO(31,266,0,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
 {"cax.",       XO(31,266,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
 
-{"ehpriv",     X(31,270),      0xffffffff,  E500MC,    PPCNONE,        {0}},
+{"ehpriv",     X(31,270),      0xffffffff, E500MC|PPCA2, PPCNONE,      {0}},
 
-{"tlbiel",     X(31,274),      XRTLRA_MASK, POWER4,    PPCNONE,        {RB, L}},
+{"tlbiel",     X(31,274),      XRTLRA_MASK, POWER4,    PPC476,         {RB, L}},
 
 {"mfapidi",    X(31,275),      X_MASK,      BOOKE,     PPCNONE,        {RT, RA}},
 
@@ -3782,7 +3807,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"eqv",                XRC(31,284,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
 {"eqv.",       XRC(31,284,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
 
-{"lhepx",      X(31,287),      X_MASK,      E500MC,    PPCNONE,        {RT, RA, RB}},
+{"lhepx",      X(31,287),      X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
 
 {"mfdcrux",    X(31,291),      X_MASK,      PPC464,    PPCNONE,        {RS, RA}},
 
@@ -3798,7 +3823,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"xor",                XRC(31,316,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
 {"xor.",       XRC(31,316,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
 
-{"dcbtep",     XRT(31,319,0),  X_MASK,      E500MC,    PPCNONE,        {RT, RA, RB}},
+{"dcbtep",     XRT(31,319,0),  X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
 
 {"mfexisr",    XSPR(31,323, 64), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
 {"mfexier",    XSPR(31,323, 66), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
@@ -3834,7 +3859,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mfdmasa3",   XSPR(31,323,219), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
 {"mfdmacc3",   XSPR(31,323,220), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
 {"mfdmasr",    XSPR(31,323,224), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfdcr",      X(31,323),      X_MASK,   PPC403|BOOKE, PPCNONE,        {RT, SPR}},
+{"mfdcr",      X(31,323),      X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RT, SPR}},
+{"mfdcr.",     XRC(31,323,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, SPR}},
+
+{"dcread",     X(31,326),      X_MASK,      PPC476,    PPCNONE,        {RT, RA, RB}},
 
 {"div",                XO(31,331,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
 {"div.",       XO(31,331,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
@@ -4047,7 +4075,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"mftbl",      XSPR(31,371,268), XSPR_MASK, CLASSIC,   PPCNONE,        {RT}},
 {"mftbu",      XSPR(31,371,269), XSPR_MASK, CLASSIC,   PPCNONE,        {RT}},
-{"mftb",       X(31,371),      X_MASK,      CLASSIC,   POWER7,         {RT, TBR}},
+{"mftb",       X(31,371),      X_MASK,  CLASSIC|PPCA2, POWER7,         {RT, TBR}},
 
 {"lwaux",      X(31,373),      X_MASK,      PPC64,     PPCNONE,        {RT, RAL, RB}},
 
@@ -4055,11 +4083,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"lhaux",      X(31,375),      X_MASK,      COM,       PPCNONE,        {RT, RAL, RB}},
 
-{"popcntw",    X(31,378),      XRB_MASK,    POWER7,    PPCNONE,        {RA, RS}},
+{"popcntw",    X(31,378),      XRB_MASK, POWER7|PPCA2, PPCNONE,        {RA, RS}},
 
-{"mtdcrx",     X(31,387),      X_MASK,      BOOKE,     PPCNONE,        {RA, RS}},
+{"mtdcrx",     X(31,387),      X_MASK, BOOKE|PPCA2|PPC476, PPCNONE,    {RA, RS}},
+{"mtdcrx.",    XRC(31,387,1),  X_MASK,      PPCA2,     PPCNONE,        {RA, RS}},
 
-{"dcblc",      X(31,390),      X_MASK,      PPCCHLK,   PPCNONE,        {CT, RA, RB}},
+{"dcblc",      X(31,390),      X_MASK, PPCCHLK|PPC476, PPCNONE,        {CT, RA, RB}},
 {"stdfcmx",    APU(31,391,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
 
 {"divdeu",     XO(31,393,0,0), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
@@ -4071,12 +4100,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"slbmte",     X(31,402),      XRA_MASK,    PPC64,     PPCNONE,        {RS, RB}},
 
+{"icswx",      XRC(31,406,0),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA, RB}},
+{"icswx.",     XRC(31,406,1),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA, RB}},
+
 {"sthx",       X(31,407),      X_MASK,      COM,       PPCNONE,        {RS, RA0, RB}},
 
 {"orc",                XRC(31,412,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
 {"orc.",       XRC(31,412,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
 
-{"sthepx",     X(31,415),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
+{"sthepx",     X(31,415),      X_MASK,   E500MC|PPCA2, PPCNONE,        {RS, RA, RB}},
 
 {"mtdcrux",    X(31,419),      X_MASK,      PPC464,    PPCNONE,        {RA, RS}},
 
@@ -4132,9 +4164,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mtdmasa3",   XSPR(31,451,219), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
 {"mtdmacc3",   XSPR(31,451,220), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
 {"mtdmasr",    XSPR(31,451,224), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtdcr",      X(31,451),      X_MASK,   PPC403|BOOKE, PPCNONE,        {SPR, RS}},
+{"mtdcr",      X(31,451),     X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {SPR, RS}},
+{"mtdcr.",     XRC(31,451,1), X_MASK,       PPCA2,     PPCNONE,        {SPR, RS}},
 
-{"dccci",      X(31,454),     XRT_MASK, PPC403|PPC440, PPCNONE,        {RA, RB}},
+{"dccci",      X(31,454),     XRT_MASK, PPC403|PPC440, PPCA2|PPC476,   {RA, RB}},
+{"dci",                X(31,454),      XRARB_MASK, PPCA2|PPC476, PPCNONE,      {CT}},
 
 {"divdu",      XO(31,457,0,0), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
 {"divdu.",     XO(31,457,0,1), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
@@ -4305,9 +4339,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"dsn",        X(31,483),      XRT_MASK,    E500MC,    PPCNONE,        {RA, RB}},
 
-{"dcread",     X(31,486),      X_MASK,  PPC403|PPC440, PPCNONE,        {RT, RA, RB}},
+{"dcread",     X(31,486),      X_MASK,  PPC403|PPC440, PPCA2|PPC476,   {RT, RA, RB}},
 
-{"icbtls",     X(31,486),      X_MASK,      PPCCHLK,   PPCNONE,        {CT, RA, RB}},
+{"icbtls",     X(31,486),      X_MASK, PPCCHLK|PPC476, PPCNONE,        {CT, RA, RB}},
 
 {"stvxl",      X(31,487),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA, RB}},
 
@@ -4326,9 +4360,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"cli",                X(31,502),      XRB_MASK,    POWER,     PPCNONE,        {RT, RA}},
 
-{"popcntd",    X(31,506),      XRB_MASK,    POWER7,    PPCNONE,        {RA, RS}},
+{"popcntd",    X(31,506),      XRB_MASK, POWER7|PPCA2, PPCNONE,        {RA, RS}},
 
-{"cmpb",       X(31,508),      X_MASK,      POWER6,    PPCNONE,        {RA, RS, RB}},
+{"cmpb",       X(31,508),      X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {RA, RS, RB}},
 
 {"mcrxr",      X(31,512), XRARB_MASK|(3<<21), COM,     POWER7,         {BF}},
 
@@ -4353,7 +4387,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"clcs",       X(31,531),      XRB_MASK,    M601,      PPCNONE,        {RT, RA}},
 
-{"ldbrx",      X(31,532),      X_MASK,    CELL|POWER7, PPCNONE,        {RT, RA0, RB}},
+{"ldbrx",      X(31,532),      X_MASK, CELL|POWER7|PPCA2, PPCNONE,     {RT, RA0, RB}},
 
 {"lswx",       X(31,533),      X_MASK,      PPCCOM,    PPCNONE,        {RT, RA0, RB}},
 {"lsx",                X(31,533),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
@@ -4406,14 +4440,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"lwsync",     XSYNC(31,598,1), 0xffffffff, PPC,       PPCNONE,        {0}},
 {"ptesync",    XSYNC(31,598,2), 0xffffffff, PPC64,     PPCNONE,        {0}},
-{"sync",       X(31,598),      XSYNC_MASK,  PPCCOM,    BOOKE,          {LS}},
-{"msync",      X(31,598),      0xffffffff,  BOOKE,     PPCNONE,        {0}},
+{"sync",       X(31,598),      XSYNC_MASK,  PPCCOM,    BOOKE|PPC476,   {LS}},
+{"msync",      X(31,598),      0xffffffff, BOOKE|PPCA2|PPC476, PPCNONE, {0}},
 {"dcs",                X(31,598),      0xffffffff,  PWRCOM,    PPCNONE,        {0}},
 
 {"lfdx",       X(31,599),      X_MASK,      COM,       PPCNONE,        {FRT, RA0, RB}},
 
 {"mffgpr",     XRC(31,607,0),  XRA_MASK,    POWER6,    POWER7,         {FRT, RB}},
-{"lfdepx",     X(31,607),      X_MASK,      E500MC,    PPCNONE,        {FRT, RA, RB}},
+{"lfdepx",     X(31,607),      X_MASK,   E500MC|PPCA2, PPCNONE,        {FRT, RA, RB}},
 
 {"lddx",       X(31,611),      X_MASK,      E500MC,    PPCNONE,        {RT, RA, RB}},
 
@@ -4425,8 +4459,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mulo",       XO(31,107,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
 {"mulo.",      XO(31,107,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
 
-{"lxsdux",     X(31,620),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA, RB}},
-
 {"mfsri",      X(31,627),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
 
 {"dclst",      X(31,630),      XRB_MASK,    PWRCOM,    PPCNONE,        {RS, RA}},
@@ -4450,7 +4482,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"mfsrin",     X(31,659),      XRA_MASK,    PPC32,     PPCNONE,        {RT, RB}},
 
-{"stdbrx",     X(31,660),      X_MASK,    CELL|POWER7, PPCNONE,        {RS, RA0, RB}},
+{"stdbrx",     X(31,660),      X_MASK, CELL|POWER7|PPCA2, PPCNONE,     {RS, RA0, RB}},
 
 {"stswx",      X(31,661),      X_MASK,      PPCCOM,    PPCNONE,        {RS, RA0, RB}},
 {"stsx",       X(31,661),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, RB}},
@@ -4471,6 +4503,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"stvrx",      X(31,679),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
 {"sthfcmux",   APU(31,679,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
 
+{"wclrone",    XOPL2(31,694,2),XRT_MASK,    PPCA2,     PPCNONE,        {RA0, RB}},
+{"wclrall",    X(31,694),      XRARB_MASK,  PPCA2,     PPCNONE,        {L}},
+{"wclr",       X(31,694),      X_MASK,      PPCA2,     PPCNONE,        {L, RA0, RB}},
+
 {"stbcx.",     XRC(31,694,1),  X_MASK,      POWER7,    PPCNONE,        {RS, RA0, RB}},
 
 {"stfsux",     X(31,695),      X_MASK,      COM,       PPCNONE,        {FRS, RAS, RB}},
@@ -4508,14 +4544,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"sreq.",      XRC(31,729,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
 
 {"mftgpr",     XRC(31,735,0),  XRA_MASK,    POWER6,    POWER7,         {RT, FRB}},
-{"stfdepx",    X(31,735),      X_MASK,      E500MC,    PPCNONE,        {FRS, RA, RB}},
+{"stfdepx",    X(31,735),      X_MASK,   E500MC|PPCA2, PPCNONE,        {FRS, RA, RB}},
 
 {"stddx",      X(31,739),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
 
 {"stqfcmux",   APU(31,743,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
 
-{"stxsdux",    X(31,748),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA, RB}},
-
 {"subfmeo",    XO(31,232,1,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
 {"sfmeo",      XO(31,232,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
 {"subfmeo.",   XO(31,232,1,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
@@ -4534,7 +4568,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mullwo.",    XO(31,235,1,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
 {"mulso.",     XO(31,235,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
 
-{"dcba",       X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE, PPCNONE,     {RA, RB}},
+{"dcba",       X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, PPCNONE, {RA, RB}},
 {"dcbal",      XOPL(31,758,1), XRT_MASK,    E500MC,    PPCNONE,        {RA, RB}},
 
 {"stfdux",     X(31,759),      X_MASK,      COM,       PPCNONE,        {FRS, RAS, RB}},
@@ -4555,7 +4589,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"lxvw4x",     X(31,780),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA, RB}},
 
-{"tlbivax",    X(31,786),      XRT_MASK,    BOOKE,     PPCNONE,        {RA, RB}},
+{"tlbivax",    X(31,786),      XRT_MASK,  BOOKE|PPCA2|PPC476, PPCNONE, {RA, RB}},
 
 {"lwzcix",     X(31,789),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
 
@@ -4576,10 +4610,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"lvrxl",      X(31,807),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
 
-{"lxvw4ux",    X(31,812),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA, RB}},
-
 {"rac",                X(31,818),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
 
+{"erativax",   X(31,819),      X_MASK,      PPCA2,     PPCNONE,        {RS, RA0, RB}},
+
 {"lhzcix",     X(31,821),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
 
 {"dss",                XDSS(31,822,0), XDSS_MASK,   PPCVEC,    PPCNONE,        {STRM}},
@@ -4599,14 +4633,17 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"lxvd2x",     X(31,844),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA, RB}},
 
+{"tlbsrx.",    XRC(31,850,1),  XRT_MASK,    PPCA2,     PPCNONE,        {RA, RB}},
+
 {"slbmfev",    X(31,851),      XRA_MASK,    PPC64,     PPCNONE,        {RT, RB}},
 
 {"lbzcix",     X(31,853),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
 
-{"eieio",      X(31,854),      0xffffffff,  PPC,       BOOKE,          {0}},
-{"mbar",       X(31,854),      X_MASK,      BOOKE,     PPCNONE,        {MO}},
+{"eieio",      X(31,854),      0xffffffff,  PPC,   BOOKE|PPCA2|PPC476, {0}},
+{"mbar",       X(31,854),      X_MASK, BOOKE|PPCA2|PPC476, PPCNONE,    {MO}},
+{"eieio",      X(31,854),      0xffffffff, PPCA2|PPC476, PPCNONE,      {0}},
 
-{"lfiwax",     X(31,855),      X_MASK,      POWER6,    PPCNONE,        {FRT, RA0, RB}},
+{"lfiwax",     X(31,855),      X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, RA0, RB}},
 
 {"abso",       XO(31,360,1,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
 {"abso.",      XO(31,360,1,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
@@ -4614,11 +4651,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"divso",      XO(31,363,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
 {"divso.",     XO(31,363,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
 
-{"lxvd2ux",    X(31,876),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA, RB}},
-
 {"ldcix",      X(31,885),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
 
-{"lfiwzx",     X(31,887),      X_MASK,      POWER7,    PPCNONE,        {FRT, RA0, RB}},
+{"lfiwzx",     X(31,887),      X_MASK,   POWER7|PPCA2, PPCNONE,        {FRT, RA0, RB}},
 
 {"stvlxl",     X(31,903),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
 {"stdfcmux",   APU(31,903,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
@@ -4630,8 +4665,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"stxvw4x",    X(31,908),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA, RB}},
 
-{"tlbsx",      XRC(31,914,0),  X_MASK,   PPC403|BOOKE, PPCNONE,        {RTO, RA, RB}},
-{"tlbsx.",     XRC(31,914,1),  X_MASK,   PPC403|BOOKE, PPCNONE,        {RTO, RA, RB}},
+{"tlbsx",      XRC(31,914,0),  X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA, RB}},
+{"tlbsx.",     XRC(31,914,1),  X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA, RB}},
 
 {"slbmfee",    X(31,915),      XRA_MASK,    PPC64,     PPCNONE,        {RT, RB}},
 
@@ -4662,11 +4697,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"divweo",     XO(31,427,1,0), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
 {"divweo.",    XO(31,427,1,1), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
 
-{"stxvw4ux",   X(31,940),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA, RB}},
-
-{"tlbrehi",    XTLB(31,946,0), XTLB_MASK,   PPC403,    PPCNONE,        {RT, RA}},
-{"tlbrelo",    XTLB(31,946,1), XTLB_MASK,   PPC403,    PPCNONE,        {RT, RA}},
-{"tlbre",      X(31,946),      X_MASK,   PPC403|BOOKE, PPCNONE,        {RSO, RAOPT, SHO}},
+{"tlbrehi",    XTLB(31,946,0), XTLB_MASK,   PPC403,    PPCA2,          {RT, RA}},
+{"tlbrelo",    XTLB(31,946,1), XTLB_MASK,   PPC403,    PPCA2,          {RT, RA}},
+{"tlbre",      X(31,946),      X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
 
 {"sthcix",     X(31,949),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
 
@@ -4678,7 +4711,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"extsb",      XRC(31,954,0),  XRB_MASK,    PPC,       PPCNONE,        {RA, RS}},
 {"extsb.",     XRC(31,954,1),  XRB_MASK,    PPC,       PPCNONE,        {RA, RS}},
 
-{"iccci",      X(31,966),     XRT_MASK, PPC403|PPC440, PPCNONE,        {RA, RB}},
+{"iccci",      X(31,966),     XRT_MASK, PPC403|PPC440, PPC476,         {RA, RB}},
+{"ici",                X(31,966),      XRARB_MASK,  PPCA2|PPC476, PPCNONE,     {CT}},
 
 {"divduo",     XO(31,457,1,0), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
 {"divduo.",    XO(31,457,1,1), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
@@ -4688,10 +4722,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"stxvd2x",    X(31,972),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA, RB}},
 
-{"tlbld",      X(31,978),      XRTRA_MASK,  PPC,       PPC403|BOOKE,   {RB}},
+{"tlbld",      X(31,978),      XRTRA_MASK,  PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
 {"tlbwehi",    XTLB(31,978,0), XTLB_MASK,   PPC403,    PPCNONE,        {RT, RA}},
 {"tlbwelo",    XTLB(31,978,1), XTLB_MASK,   PPC403,    PPCNONE,        {RT, RA}},
-{"tlbwe",      X(31,978),      X_MASK,   PPC403|BOOKE, PPCNONE,        {RSO, RAOPT, SHO}},
+{"tlbwe",      X(31,978),      X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
 
 {"stbcix",     X(31,981),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
 
@@ -4702,9 +4736,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"extsw",      XRC(31,986,0),  XRB_MASK,    PPC64,     PPCNONE,        {RA, RS}},
 {"extsw.",     XRC(31,986,1),  XRB_MASK,    PPC64,     PPCNONE,        {RA, RS}},
 
-{"icbiep",     XRT(31,991,0),  XRT_MASK,    E500MC,    PPCNONE,        {RA, RB}},
+{"icbiep",     XRT(31,991,0),  XRT_MASK, E500MC|PPCA2, PPCNONE,        {RA, RB}},
 
-{"icread",     X(31,998),     XRT_MASK, PPC403|PPC440, PPCNONE,        {RA, RB}},
+{"icread",     X(31,998),     XRT_MASK, PPC403|PPC440|PPC476, PPCNONE, {RA, RB}},
 
 {"nabso",      XO(31,488,1,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
 {"nabso.",     XO(31,488,1,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
@@ -4715,8 +4749,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"divwo",      XO(31,491,1,0), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
 {"divwo.",     XO(31,491,1,1), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
 
-{"stxvd2ux",   X(31,1004),     XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA, RB}},
-
 {"tlbli",      X(31,1010),     XRTRA_MASK,  PPC,       PPCNONE,        {RB}},
 
 {"stdcix",     X(31,1013),     X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
@@ -4724,9 +4756,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"dcbz",       X(31,1014),     XRT_MASK,    PPC,       PPCNONE,        {RA, RB}},
 {"dclz",       X(31,1014),     XRT_MASK,    PPC,       PPCNONE,        {RA, RB}},
 
-{"dcbzep",     XRT(31,1023,0), XRT_MASK,    E500MC,    PPCNONE,        {RA, RB}},
+{"dcbzep",     XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, PPCNONE,        {RA, RB}},
 
-{"dcbzl",      XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPCNONE,      {RA, RB}},
+{"dcbzl",      XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476,       {RA, RB}},
 
 {"cctpl",      0x7c210b78,     0xffffffff,  CELL,      PPCNONE,        {0}},
 {"cctpm",      0x7c421378,     0xffffffff,  CELL,      PPCNONE,        {0}},
@@ -4795,7 +4827,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"stfdu",      OP(55),         OP_MASK,     COM,       PPCNONE,        {FRS, D, RAS}},
 
-{"lq",         OP(56),         OP_MASK,     POWER4,    PPCNONE,        {RTQ, DQ, RAQ}},
+{"lq",         OP(56),         OP_MASK,     POWER4,    PPC476,         {RTQ, DQ, RAQ}},
 {"psq_l",      OP(56),         OP_MASK,     PPCPS,     PPCNONE,        {FRT,PSD,RA,PSW,PSQ}},
 {"lfq",                OP(56),         OP_MASK,     POWER2,    PPCNONE,        {FRT, D, RA0}},
 
@@ -4908,14 +4940,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"denbcd",     XRC(59,834,0),  X_MASK,      POWER6,    PPCNONE,        {S, FRT, FRB}},
 {"denbcd.",    XRC(59,834,1),  X_MASK,      POWER6,    PPCNONE,        {S, FRT, FRB}},
 
-{"fcfids",     XRC(59,846,0),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
-{"fcfids.",    XRC(59,846,1),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
+{"fcfids",     XRC(59,846,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
+{"fcfids.",    XRC(59,846,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
 
 {"diex",       XRC(59,866,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
 {"diex.",      XRC(59,866,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
 
-{"fcfidus",    XRC(59,974,0),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
-{"fcfidus.",   XRC(59,974,1),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
+{"fcfidus",    XRC(59,974,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
+{"fcfidus.",   XRC(59,974,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
 
 {"xxsldwi",    XX3(60,2),      XX3SHW_MASK, PPCVSX,    PPCNONE,        {XT6, XA6, XB6, SHW}},
 {"xxsel",      XX4(60,3),      XX4_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6, XC6}},
@@ -5068,7 +5100,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"std",                DSO(62,0),      DS_MASK,     PPC64,     PPCNONE,        {RS, DS, RA0}},
 {"stdu",       DSO(62,1),      DS_MASK,     PPC64,     PPCNONE,        {RS, DS, RAS}},
-{"stq",                DSO(62,2),      DS_MASK,     POWER4,    PPCNONE,        {RSQ, DS, RA0}},
+{"stq",                DSO(62,2),      DS_MASK,     POWER4,    PPC476,         {RSQ, DS, RA0}},
 
 {"fcmpu",      X(63,0),     X_MASK|(3<<21), COM,       PPCNONE,        {BF, FRA, FRB}},
 
@@ -5078,8 +5110,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"dquaq",      ZRC(63,3,0),    Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
 {"dquaq.",     ZRC(63,3,1),    Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
 
-{"fcpsgn",     XRC(63,8,0),    X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
-{"fcpsgn.",    XRC(63,8,1),    X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
+{"fcpsgn",     XRC(63,8,0),    X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, FRA, FRB}},
+{"fcpsgn.",    XRC(63,8,1),    X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, FRA, FRB}},
 
 {"frsp",       XRC(63,12,0),   XRA_MASK,    COM,       PPCNONE,        {FRT, FRB}},
 {"frsp.",      XRC(63,12,1),   XRA_MASK,    COM,       PPCNONE,        {FRT, FRB}},
@@ -5188,10 +5220,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"dcmpoq",     X(63,130),      X_MASK,      POWER6,    PPCNONE,        {BF, FRA, FRB}},
 
-{"mtfsfi",  XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6, PPCNONE, {BFF, U, W}},
-{"mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6,      {BFF, U}},
-{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6, PPCNONE, {BFF, U, W}},
-{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6,      {BFF, U}},
+{"mtfsfi",  XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
+{"mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
+{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
+{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
 
 {"fnabs",      XRC(63,136,0),  XRA_MASK,    COM,       PPCNONE,        {FRT, FRB}},
 {"fnabs.",     XRC(63,136,1),  XRA_MASK,    COM,       PPCNONE,        {FRT, FRB}},
@@ -5247,10 +5279,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"dtstsfq",    X(63,674),      X_MASK,      POWER6,    PPCNONE,        {BF, FRA, FRB}},
 
-{"mtfsf",      XFL(63,711,0),  XFL_MASK,    POWER6,    PPCNONE,        {FLM, FRB, XFL_L, W}},
-{"mtfsf",      XFL(63,711,0),  XFL_MASK,    COM,       POWER6,         {FLM, FRB}},
-{"mtfsf.",     XFL(63,711,1),  XFL_MASK,    POWER6,    PPCNONE,        {FLM, FRB, XFL_L, W}},
-{"mtfsf.",     XFL(63,711,1),  XFL_MASK,    COM,       POWER6,         {FLM, FRB}},
+{"mtfsf",      XFL(63,711,0),  XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
+{"mtfsf",      XFL(63,711,0),  XFL_MASK,    COM, POWER6|PPCA2|PPC476,  {FLM, FRB}},
+{"mtfsf.",     XFL(63,711,1),  XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
+{"mtfsf.",     XFL(63,711,1),  XFL_MASK,    COM, POWER6|PPCA2|PPC476,  {FLM, FRB}},
 
 {"drdpq",      XRC(63,770,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
 {"drdpq.",     XRC(63,770,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
@@ -5259,28 +5291,34 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"dcffixq.",   XRC(63,802,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
 
 {"fctid",      XRC(63,814,0),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
+{"fctid",      XRC(63,814,0),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
 {"fctid.",     XRC(63,814,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
+{"fctid.",     XRC(63,814,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
 
 {"fctidz",     XRC(63,815,0),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
+{"fctidz",     XRC(63,815,0),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
 {"fctidz.",    XRC(63,815,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
+{"fctidz.",    XRC(63,815,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
 
 {"denbcdq",    XRC(63,834,0),  X_MASK,      POWER6,    PPCNONE,        {S, FRT, FRB}},
 {"denbcdq.",   XRC(63,834,1),  X_MASK,      POWER6,    PPCNONE,        {S, FRT, FRB}},
 
 {"fcfid",      XRC(63,846,0),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
+{"fcfid",      XRC(63,846,0),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
 {"fcfid.",     XRC(63,846,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
+{"fcfid.",     XRC(63,846,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
 
 {"diexq",      XRC(63,866,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
 {"diexq.",     XRC(63,866,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
 
-{"fctidu",     XRC(63,942,0),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
-{"fctidu.",    XRC(63,942,1),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
+{"fctidu",     XRC(63,942,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
+{"fctidu.",    XRC(63,942,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
 
-{"fctiduz",    XRC(63,943,0),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
-{"fctiduz.",   XRC(63,943,1),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
+{"fctiduz",    XRC(63,943,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
+{"fctiduz.",   XRC(63,943,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
 
-{"fcfidu",     XRC(63,974,0),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
-{"fcfidu.",    XRC(63,974,1),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
+{"fcfidu",     XRC(63,974,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
+{"fcfidu.",    XRC(63,974,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
 };
 
 const int powerpc_num_opcodes =

diff --git a/opcodes/rx-decode.opc b/opcodes/rx-decode.opc
new file mode 100644 (file)
index 0000000..bddf12b
--- /dev/null
+++ b/opcodes/rx-decode.opc
@@ -0,0 +1,977 @@
+/* -*- c -*- */
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "config.h"
+#include "ansidecl.h"
+#include "opcode/rx.h"
+
+#define RX_OPCODE_BIG_ENDIAN 0
+
+typedef struct
+{
+  RX_Opcode_Decoded * rx;
+  int (* getbyte)(void *);
+  void * ptr;
+  unsigned char * op;
+} LocalData;
+
+static int trace = 0;
+
+#define BSIZE 0
+#define WSIZE 1
+#define LSIZE 2
+
+/* These are for when the upper bits are "don't care" or "undefined".  */
+static int bwl[] =
+{
+  RX_Byte,
+  RX_Word,
+  RX_Long
+};
+
+static int sbwl[] =
+{
+  RX_SByte,
+  RX_SWord,
+  RX_Long
+};
+
+static int ubwl[] =
+{
+  RX_UByte,
+  RX_UWord,
+  RX_Long
+};
+
+static int memex[] =
+{
+  RX_SByte,
+  RX_SWord,
+  RX_Long,
+  RX_UWord
+};
+
+#define ID(x) rx->id = RXO_##x
+#define OP(n,t,r,a) (rx->op[n].type = t, \
+                    rx->op[n].reg = r,      \
+                    rx->op[n].addend = a )
+#define OPs(n,t,r,a,s) (OP (n,t,r,a), \
+                       rx->op[n].size = s )
+
+/* This is for the BWL and BW bitfields.  */
+static int SCALE[] = { 1, 2, 4 };
+/* This is for the prefix size enum.  */
+static int PSCALE[] = { 4, 1, 1, 1, 2, 2, 2, 3, 4 };
+
+static int flagmap[] = {0, 1, 2, 3, 0, 0, 0, 0,
+                      16, 17, 0, 0, 0, 0, 0, 0 };
+
+static int dsp3map[] = { 8, 9, 10, 3, 4, 5, 6, 7 };
+
+/*
+ *C    a constant (immediate) c
+ *R    A register
+ *I    Register indirect, no offset
+ *Is   Register indirect, with offset
+ *D    standard displacement: type (r,[r],dsp8,dsp16 code), register, BWL code
+ *P    standard displacement: type (r,[r]), reg, assumes UByte
+ *Pm   memex displacement: type (r,[r]), reg, memex code
+ *cc   condition code.  */
+
+#define DC(c)       OP (0, RX_Operand_Immediate, 0, c)
+#define DR(r)       OP (0, RX_Operand_Register,  r, 0)
+#define DI(r,a)     OP (0, RX_Operand_Indirect,  r, a)
+#define DIs(r,a,s)  OP (0, RX_Operand_Indirect,  r, (a) * SCALE[s])
+#define DD(t,r,s)   rx_disp (0, t, r, bwl[s], ld);
+#define DF(r)       OP (0, RX_Operand_Flag,  flagmap[r], 0)
+
+#define SC(i)       OP (1, RX_Operand_Immediate, 0, i)
+#define SR(r)       OP (1, RX_Operand_Register,  r, 0)
+#define SI(r,a)     OP (1, RX_Operand_Indirect,  r, a)
+#define SIs(r,a,s)  OP (1, RX_Operand_Indirect,  r, (a) * SCALE[s])
+#define SD(t,r,s)   rx_disp (1, t, r, bwl[s], ld);
+#define SP(t,r)     rx_disp (1, t, r, (t!=3) ? RX_UByte : RX_Long, ld); P(t, 1);
+#define SPm(t,r,m)  rx_disp (1, t, r, memex[m], ld); rx->op[1].size = memex[m];
+#define Scc(cc)     OP (1, RX_Operand_Condition,  cc, 0)
+
+#define S2C(i)      OP (2, RX_Operand_Immediate, 0, i)
+#define S2R(r)      OP (2, RX_Operand_Register,  r, 0)
+#define S2I(r,a)    OP (2, RX_Operand_Indirect,  r, a)
+#define S2Is(r,a,s) OP (2, RX_Operand_Indirect,  r, (a) * SCALE[s])
+#define S2D(t,r,s)  rx_disp (2, t, r, bwl[s], ld);
+#define S2P(t,r)    rx_disp (2, t, r, (t!=3) ? RX_UByte : RX_Long, ld); P(t, 2);
+#define S2Pm(t,r,m) rx_disp (2, t, r, memex[m], ld); rx->op[2].size = memex[m];
+#define S2cc(cc)    OP (2, RX_Operand_Condition,  cc, 0)
+
+#define BWL(sz)     rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = bwl[sz]
+#define sBWL(sz)    rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = sbwl[sz]
+#define uBWL(sz)    rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = ubwl[sz]
+#define P(t, n)            rx->op[n].size = (t!=3) ? RX_UByte : RX_Long;
+
+#define F(f) store_flags(rx, f)
+
+#define AU ATTRIBUTE_UNUSED
+#define GETBYTE() (ld->op [ld->rx->n_bytes++] = ld->getbyte (ld->ptr))
+
+#define SYNTAX(x) rx->syntax = x
+
+#define UNSUPPORTED() \
+  rx->syntax = "*unknown*"
+
+#define IMM(sf)   immediate (sf, 0, ld)
+#define IMMex(sf) immediate (sf, 1, ld)
+
+static int
+immediate (int sfield, int ex, LocalData * ld)
+{
+  unsigned long i = 0, j;
+
+  switch (sfield)
+    {
+#define B ((unsigned long) GETBYTE())
+    case 0:
+#if RX_OPCODE_BIG_ENDIAN
+      i  = B;
+      if (ex && (i & 0x80))
+       i -= 0x100;
+      i <<= 24;
+      i |= B << 16;
+      i |= B << 8;
+      i |= B;
+#else
+      i = B;
+      i |= B << 8;
+      i |= B << 16;
+      j = B;
+      if (ex && (j & 0x80))
+       j -= 0x100;
+      i |= j << 24;
+#endif
+      break;
+    case 3:
+#if RX_OPCODE_BIG_ENDIAN
+      i  = B << 16;
+      i |= B << 8;
+      i |= B;
+#else
+      i  = B;
+      i |= B << 8;
+      i |= B << 16;
+#endif
+      if (ex && (i & 0x800000))
+       i -= 0x1000000;
+      break;
+    case 2:
+#if RX_OPCODE_BIG_ENDIAN
+      i |= B << 8;
+      i |= B;
+#else
+      i |= B;
+      i |= B << 8;
+#endif
+      if (ex && (i & 0x8000))
+       i -= 0x10000;
+      break;
+    case 1:
+      i |= B;
+      if (ex && (i & 0x80))
+       i -= 0x100;
+      break;
+    default:
+      abort();
+    }
+  return i;
+}
+
+static void
+rx_disp (int n, int type, int reg, int size, LocalData * ld)
+{
+  int disp;
+
+  ld->rx->op[n].reg = reg;
+  switch (type)
+    {
+    case 3:
+      ld->rx->op[n].type = RX_Operand_Register;
+      break;
+    case 0:
+      ld->rx->op[n].type = RX_Operand_Indirect;
+      ld->rx->op[n].addend = 0;
+      break;
+    case 1:
+      ld->rx->op[n].type = RX_Operand_Indirect;
+      disp = GETBYTE ();
+      ld->rx->op[n].addend = disp * PSCALE[size];
+      break;
+    case 2:
+      ld->rx->op[n].type = RX_Operand_Indirect;
+      disp = GETBYTE ();
+#if RX_OPCODE_BIG_ENDIAN
+      disp = disp * 256 + GETBYTE ();
+#else
+      disp = disp + GETBYTE () * 256;
+#endif
+      ld->rx->op[n].addend = disp * PSCALE[size];
+      break;
+    default:
+      abort ();
+    }
+}
+
+/* The syntax is "OSZC" where each character is one of the following:
+   - = flag unchanged
+   0 = flag cleared
+   1 = flag set
+   ? = flag undefined
+   x = flag set (any letter will do, use it for hints :).  */
+
+static void
+store_flags (RX_Opcode_Decoded * rx, char * str)
+{
+  int i, mask;
+  rx->flags_0 = 0;
+  rx->flags_1 = 0;
+  rx->flags_s = 0;
+  
+  for (i = 0; i < 4; i++)
+    {
+      mask = 8 >> i;
+      switch (str[i])
+       {
+       case 0:
+         abort ();
+       case '-':
+         break;
+       case '0':
+         rx->flags_0 |= mask;
+         break;
+       case '1':
+         rx->flags_1 |= mask;
+         break;
+       case '?':
+         break;
+       default:
+         rx->flags_0 |= mask;
+         rx->flags_s |= mask;
+         break;
+       }
+    }
+}
+
+int
+rx_decode_opcode (unsigned long pc AU,
+                 RX_Opcode_Decoded * rx,
+                 int (* getbyte)(void *),
+                 void * ptr)
+{
+  LocalData lds, * ld = &lds;
+  unsigned char op[20] = {0};
+
+  lds.rx = rx;
+  lds.getbyte = getbyte;
+  lds.ptr = ptr;
+  lds.op = op;
+
+  memset (rx, 0, sizeof (*rx));
+  BWL(LSIZE);
+
+/** VARY sz 00 01 10 */
+
+/*----------------------------------------------------------------------*/
+/* MOV                                                                 */
+
+/** 0111 0101 0100 rdst                mov%s   #%1, %0 */
+  ID(mov); DR(rdst); SC(IMM (1)); F("----");
+
+/** 1111 10sd rdst im sz       mov%s   #%1, %0 */
+  ID(mov); sBWL (sz); DD(sd, rdst, sz); SC(IMMex(im)); F("----");
+
+/** 0110 0110 immm rdst                mov%s   #%1, %0 */
+  ID(mov); DR(rdst); SC(immm); F("----");
+
+/** 0011 11sz d dst sppp               mov%s   #%1, %0 */
+  ID(mov); sBWL (sz); DIs(dst, d*16+sppp, sz); SC(IMM(1)); F("----");
+
+/** 11sz sd ss rsrc rdst       mov%s   %1, %0 */
+  ID(mov); sBWL(sz); F("----");
+  if ((ss == 3) && (sd != 3))
+    {
+      SD(ss, rdst, sz); DD(sd, rsrc, sz);
+    }
+  else
+    {
+      SD(ss, rsrc, sz); DD(sd, rdst, sz);
+    }
+
+/** 10sz 1dsp a src b dst      mov%s   %1, %0 */
+  ID(mov); sBWL(sz); DR(dst); SIs(src, dsp*4+a*2+b, sz); F("----");
+
+/** 10sz 0dsp a dst b src      mov%s   %1, %0 */
+  ID(mov); sBWL(sz); DIs(dst, dsp*4+a*2+b, sz); SR(src); F("----");
+
+/** 1111 1110 01sz isrc bsrc rdst      mov%s   [%1, %2], %0 */
+  ID(movbi); sBWL(sz); DR(rdst); SR(isrc); S2R(bsrc); F("----");
+
+/** 1111 1110 00sz isrc bsrc rdst      mov%s   %0, [%1, %2] */
+  ID(movbir); sBWL(sz); DR(rdst); SR(isrc); S2R(bsrc); F("----");
+
+/** 1111 1110 11sz isrc bsrc rdst      movu%s  [%1, %2], %0 */
+  ID(movbi); uBWL(sz); DR(rdst); SR(isrc); S2R(bsrc); F("----");
+
+/** 1111 1101 0010 0p sz rdst rsrc     mov%s   %1, %0 */
+  ID(mov); sBWL (sz); SR(rsrc); F("----");
+  OP(0, p ? RX_Operand_Predec : RX_Operand_Postinc, rdst, 0);
+
+/** 1111 1101 0010 1p sz rsrc rdst     mov%s   %1, %0 */
+  ID(mov); sBWL (sz); DR(rdst); F("----");
+  OP(1, p ? RX_Operand_Predec : RX_Operand_Postinc, rsrc, 0);
+
+/** 1011 w dsp a src b dst     movu%s  %1, %0 */
+  ID(mov); uBWL(w); DR(dst); SIs(src, dsp*4+a*2+b, w); F("----");
+
+/** 0101 1 s ss rsrc rdst      movu%s  %1, %0 */
+  ID(mov); uBWL(s); SD(ss, rsrc, s); DR(rdst); F("----");
+
+/** 1111 1101 0011 1p sz rsrc rdst     movu%s  %1, %0 */
+  ID(mov); uBWL (sz); DR(rdst); F("----");
+   OP(1, p ? RX_Operand_Predec : RX_Operand_Postinc, rsrc, 0);
+
+/*----------------------------------------------------------------------*/
+/* PUSH/POP                                                            */
+
+/** 0110 1111 dsta dstb                popm    %1-%2 */
+  ID(popm); SR(dsta); S2R(dstb); F("----");
+
+/** 0110 1110 dsta dstb                pushm   %1-%2 */
+  ID(pushm); SR(dsta); S2R(dstb); F("----");
+  
+/** 0111 1110 1011 rdst                pop     %0 */
+  ID(mov); OP(1, RX_Operand_Postinc, 0, 0); DR(rdst); F("----");
+  
+/** 0111 1110 10sz rsrc                push%s  %1 */
+  ID(mov); BWL(sz); OP(0, RX_Operand_Predec, 0, 0); SR(rsrc); F("----");
+
+/** 1111 01ss rsrc 10sz                push%s  %1 */
+  ID(mov); BWL(sz); OP(0, RX_Operand_Predec, 0, 0); SD(ss, rsrc, sz); F("----");
+
+/*----------------------------------------------------------------------*/
+/* XCHG                                                                        */
+
+/** 1111 1100 0100 00ss rsrc rdst      xchg    %1%S1, %0 */
+  ID(xchg); DR(rdst); SP(ss, rsrc);
+
+/** 0000 0110 mx10 00ss 0001 0000 rsrc rdst    xchg    %1%S1, %0 */
+  ID(xchg); DR(rdst); SPm(ss, rsrc, mx);
+
+/*----------------------------------------------------------------------*/
+/* STZ/STNZ                                                            */
+
+/** 1111 1101 0111 im00 1110rdst       stz     #%1, %0 */
+  ID(stcc); SC(IMMex(im)); DR(rdst); S2cc(RXC_z);
+
+/** 1111 1101 0111 im00 1111rdst       stnz    #%1, %0 */
+  ID(stcc); SC(IMMex(im)); DR(rdst); S2cc(RXC_nz);
+
+/*----------------------------------------------------------------------*/
+/* RTSD                                                                        */
+
+/** 0110 0111                  rtsd    #%1 */
+  ID(rtsd); SC(IMM(1) * 4);
+
+/** 0011 1111 rega regb                rtsd    #%1, %2-%0 */
+  ID(rtsd); SC(IMM(1) * 4); S2R(rega); DR(regb);
+
+/*----------------------------------------------------------------------*/
+/* AND                                                                 */
+
+/** 0110 0100 immm rdst                        and     #%1, %0 */
+  ID(and); SC(immm); DR(rdst); F("-SZ-");
+
+/** 0111 01im 0010 rdst                        and     #%1, %0 */
+  ID(and); SC(IMMex(im)); DR(rdst); F("-SZ-");
+
+/** 0101 00ss rsrc rdst                        and     %1%S1, %0 */
+  ID(and); SP(ss, rsrc); DR(rdst); F("-SZ-");
+
+/** 0000 0110 mx01 00ss rsrc rdst      and     %1%S1, %0 */
+  ID(and); SPm(ss, rsrc, mx); DR(rdst); F("-SZ-");
+
+/** 1111 1111 0100 rdst srca srcb      and     %2, %1, %0 */
+  ID(and); DR(rdst); SR(srcb); S2R(srca); F("-SZ-");
+
+/*----------------------------------------------------------------------*/
+/* OR                                                                  */
+
+/** 0110 0101 immm rdst                        or      #%1, %0 */
+  ID(or); SC(immm); DR(rdst); F("-SZ-");
+
+/** 0111 01im 0011 rdst                        or      #%1, %0 */
+  ID(or); SC(IMMex(im)); DR(rdst); F("-SZ-");
+
+/** 0101 01ss rsrc rdst                        or      %1%S1, %0 */
+  ID(or); SP(ss, rsrc); DR(rdst); F("-SZ-");
+
+/** 0000 0110 mx01 01ss rsrc rdst                      or      %1%S1, %0 */
+  ID(or); SPm(ss, rsrc, mx); DR(rdst); F("-SZ-");
+
+/** 1111 1111 0101 rdst srca srcb      or      %2, %1, %0 */
+  ID(or); DR(rdst); SR(srcb); S2R(srca); F("-SZ-");
+
+/*----------------------------------------------------------------------*/
+/* XOR                                                                 */
+
+/** 1111 1101 0111 im00 1101rdst       xor     #%1, %0 */
+  ID(xor); SC(IMMex(im)); DR(rdst); F("-SZ-");
+
+/** 1111 1100 0011 01ss rsrc rdst      xor     %1%S1, %0 */
+  ID(xor); SP(ss, rsrc); DR(rdst); F("-SZ-");
+
+/** 0000 0110 mx10 00ss 0000 1101 rsrc rdst    xor     %1%S1, %0 */
+  ID(xor); SPm(ss, rsrc, mx); DR(rdst); F("-SZ-");
+
+/*----------------------------------------------------------------------*/
+/* NOT                                                                 */
+
+/** 0111 1110 0000 rdst                        not     %0 */
+  ID(xor); DR(rdst); SR(rdst); S2C(~0); F("-SZ-");
+
+/** 1111 1100 0011 1011 rsrc rdst      not     %1, %0 */
+  ID(xor); DR(rdst); SR(rsrc); S2C(~0); F("-SZ-");
+
+/*----------------------------------------------------------------------*/
+/* TST                                                                 */
+
+/** 1111 1101 0111 im00 1100rdst       tst     #%1, %2 */
+  ID(and); SC(IMMex(im)); S2R(rdst); F("-SZ-");
+
+/** 1111 1100 0011 00ss rsrc rdst      tst     %1%S1, %2 */
+  ID(and); SP(ss, rsrc); S2R(rdst); F("-SZ-");
+
+/** 0000 0110 mx10 00ss 0000 1100 rsrc rdst    tst     %1%S1, %2 */
+  ID(and); SPm(ss, rsrc, mx); S2R(rdst); F("-SZ-");
+
+/*----------------------------------------------------------------------*/
+/* NEG                                                                 */
+
+/** 0111 1110 0001 rdst                        neg     %0 */
+  ID(sub); DR(rdst); SC(0); S2R(rdst); F("OSZC");
+
+/** 1111 1100 0000 0111 rsrc rdst      neg     %2, %0 */
+  ID(sub); DR(rdst); SC(0); S2R(rsrc); F("OSZC");
+
+/*----------------------------------------------------------------------*/
+/* ADC                                                                 */
+
+/** 1111 1101 0111 im00 0010rdst       adc     #%1, %0 */
+  ID(adc); SC(IMMex(im)); DR(rdst); F("OSZC");
+
+/** 1111 1100 0000 1011 rsrc rdst      adc     %1, %0 */
+  ID(adc); SR(rsrc); DR(rdst); F("OSZC");
+
+/** 0000 0110 1010 00ss 0000 0010 rsrc rdst    adc     %1%S1, %0 */
+  ID(adc); SPm(ss, rsrc, 2); DR(rdst); F("OSZC");
+
+/*----------------------------------------------------------------------*/
+/* ADD                                                                 */
+
+/** 0110 0010 immm rdst                        add     #%1, %0 */
+  ID(add); SC(immm); DR(rdst); F("OSZC");
+
+/** 0100 10ss rsrc rdst                        add     %1%S1, %0 */
+  ID(add); SP(ss, rsrc); DR(rdst); F("OSZC");
+
+/** 0000 0110 mx00 10ss rsrc rdst      add     %1%S1, %0 */
+  ID(add); SPm(ss, rsrc, mx); DR(rdst); F("OSZC");
+
+/** 0111 00im rsrc rdst                        add     #%1, %2, %0 */
+  ID(add); SC(IMMex(im)); S2R(rsrc); DR(rdst); F("OSZC");
+
+/** 1111 1111 0010 rdst srca srcb      add     %2, %1, %0 */
+  ID(add); DR(rdst); SR(srcb); S2R(srca); F("OSZC");
+
+/*----------------------------------------------------------------------*/
+/* CMP                                                                 */
+
+/** 0110 0001 immm rdst                        cmp     #%2, %1 */
+  ID(sub); S2C(immm); SR(rdst); F("OSZC");
+
+/** 0111 01im 0000 rsrc                cmp     #%2, %1%S1 */
+  ID(sub); SR(rsrc); S2C(IMMex(im)); F("OSZC");
+
+/** 0111 0101 0101 rsrc                        cmp     #%2, %1 */
+  ID(sub); SR(rsrc); S2C(IMM(1)); F("OSZC");
+
+/** 0100 01ss rsrc rdst                cmp     %2%S2, %1 */
+  ID(sub); S2P(ss, rsrc); SR(rdst); F("OSZC");
+
+/** 0000 0110 mx00 01ss rsrc rdst              cmp     %2%S2, %1 */
+  ID(sub); S2Pm(ss, rsrc, mx); SR(rdst); F("OSZC");
+
+/*----------------------------------------------------------------------*/
+/* SUB                                                                 */
+
+/** 0110 0000 immm rdst                        sub     #%2, %0 */
+  ID(sub); S2C(immm); SR(rdst); DR(rdst); F("OSZC");
+
+/** 0100 00ss rsrc rdst                        sub     %2%S2, %1 */
+  ID(sub); S2P(ss, rsrc); SR(rdst); DR(rdst); F("OSZC");
+
+/** 0000 0110 mx00 00ss rsrc rdst                      sub     %2%S2, %1 */
+  ID(sub); S2Pm(ss, rsrc, mx); SR(rdst); DR(rdst); F("OSZC");
+
+/** 1111 1111 0000 rdst srca srcb      sub     %2, %1, %0 */
+  ID(sub); DR(rdst); SR(srcb); S2R(srca); F("OSZC");
+
+/*----------------------------------------------------------------------*/
+/* SBB                                                                 */
+
+/** 1111 1100 0000 0011 rsrc rdst      sbb     %1, %0 */
+  ID(sbb); SR (rsrc); DR(rdst); F("OSZC");
+
+  /* FIXME: only supports .L */
+/** 0000 0110 mx10 00sp 0000 0000 rsrc rdst    sbb     %1%S1, %0 */
+  ID(sbb); SPm(sp, rsrc, mx); DR(rdst); F("OSZC");
+
+/*----------------------------------------------------------------------*/
+/* ABS                                                                 */
+
+/** 0111 1110 0010 rdst                        abs     %0 */
+  ID(abs); DR(rdst); SR(rdst); F("OSZ-");
+
+/** 1111 1100 0000 1111 rsrc rdst      abs     %1, %0 */
+  ID(abs); DR(rdst); SR(rsrc); F("OSZ-");
+
+/*----------------------------------------------------------------------*/
+/* MAX                                                                 */
+
+/** 1111 1101 0111 im00 0100rdst       max     #%1, %0 */
+  ID(max); DR(rdst); SC(IMMex(im));
+
+/** 1111 1100 0001 00ss rsrc rdst      max     %1%S1, %0 */
+  ID(max); SP(ss, rsrc); DR(rdst);
+
+/** 0000 0110 mx10 00ss 0000 0100 rsrc rdst    max     %1%S1, %0 */
+  ID(max); SPm(ss, rsrc, mx); DR(rdst);
+
+/*----------------------------------------------------------------------*/
+/* MIN                                                                 */
+
+/** 1111 1101 0111 im00 0101rdst       min     #%1, %0 */
+  ID(min); DR(rdst); SC(IMMex(im));
+
+/** 1111 1100 0001 01ss rsrc rdst      min     %1%S1, %0 */
+  ID(min); SP(ss, rsrc); DR(rdst);
+
+/** 0000 0110 mx10 00ss 0000 0101 rsrc rdst    min     %1%S1, %0 */
+  ID(min); SPm(ss, rsrc, mx); DR(rdst);
+
+/*----------------------------------------------------------------------*/
+/* MUL                                                                 */
+
+/** 0110 0011 immm rdst                        mul     #%1, %0 */
+  ID(mul); DR(rdst); SC(immm); F("O---");
+
+/** 0111 01im 0001rdst                 mul     #%1, %0 */
+  ID(mul); DR(rdst); SC(IMMex(im)); F("O---");
+
+/** 0100 11ss rsrc rdst                        mul     %1%S1, %0 */
+  ID(mul); SP(ss, rsrc); DR(rdst); F("O---");
+
+/** 0000 0110 mx00 11ss rsrc rdst      mul     %1%S1, %0 */
+  ID(mul); SPm(ss, rsrc, mx); DR(rdst); F("O---");
+
+/** 1111 1111 0011 rdst srca srcb      mul     %2, %1, %0 */
+  ID(mul); DR(rdst); SR(srcb); S2R(srca); F("O---");
+
+/*----------------------------------------------------------------------*/
+/* EMUL                                                                        */
+
+/** 1111 1101 0111 im00 0110rdst       emul    #%1, %0 */
+  ID(emul); DR(rdst); SC(IMMex(im));
+
+/** 1111 1100 0001 10ss rsrc rdst      emul    %1%S1, %0 */
+  ID(emul); SP(ss, rsrc); DR(rdst);
+
+/** 0000 0110 mx10 00ss 0000 0110 rsrc rdst    emul    %1%S1, %0 */
+  ID(emul); SPm(ss, rsrc, mx); DR(rdst);
+
+/*----------------------------------------------------------------------*/
+/* EMULU                                                                       */
+
+/** 1111 1101 0111 im00 0111rdst       emulu   #%1, %0 */
+  ID(emulu); DR(rdst); SC(IMMex(im));
+
+/** 1111 1100 0001 11ss rsrc rdst      emulu   %1%S1, %0 */
+  ID(emulu); SP(ss, rsrc); DR(rdst);
+
+/** 0000 0110 mx10 00ss 0000 0111 rsrc rdst    emulu   %1%S1, %0 */
+  ID(emulu); SPm(ss, rsrc, mx); DR(rdst);
+
+/*----------------------------------------------------------------------*/
+/* DIV                                                                 */
+
+/** 1111 1101 0111 im00 1000rdst       div     #%1, %0 */
+  ID(div); DR(rdst); SC(IMMex(im)); F("O---");
+
+/** 1111 1100 0010 00ss rsrc rdst      div     %1%S1, %0 */
+  ID(div); SP(ss, rsrc); DR(rdst); F("O---");
+
+/** 0000 0110 mx10 00ss 0000 1000 rsrc rdst    div     %1%S1, %0 */
+  ID(div); SPm(ss, rsrc, mx); DR(rdst); F("O---");
+
+/*----------------------------------------------------------------------*/
+/* DIVU                                                                        */
+
+/** 1111 1101 0111 im00 1001rdst       divu    #%1, %0 */
+  ID(divu); DR(rdst); SC(IMMex(im)); F("O---");
+
+/** 1111 1100 0010 01ss rsrc rdst      divu    %1%S1, %0 */
+  ID(divu); SP(ss, rsrc); DR(rdst); F("O---");
+
+/** 0000 0110 mx10 00ss 0000 1001 rsrc rdst    divu    %1%S1, %0 */
+  ID(divu); SPm(ss, rsrc, mx); DR(rdst); F("O---");
+
+/*----------------------------------------------------------------------*/
+/* SHIFT                                                               */
+
+/** 0110 110i mmmm rdst                        shll    #%2, %0 */
+  ID(shll); S2C(i*16+mmmm); SR(rdst); DR(rdst); F("OSZC");
+
+/** 1111 1101 0110 0010 rsrc rdst      shll    %2, %0 */
+  ID(shll); S2R(rsrc); SR(rdst); DR(rdst); F("OSZC");
+
+/** 1111 1101 110immmm rsrc rdst       shll    #%2, %1, %0 */
+  ID(shll); S2C(immmm); SR(rsrc); DR(rdst); F("OSZC");
+
+
+/** 0110 101i mmmm rdst                        shar    #%2, %0 */
+  ID(shar); S2C(i*16+mmmm); SR(rdst); DR(rdst); F("0SZC");
+
+/** 1111 1101 0110 0001 rsrc rdst      shar    %2, %0 */
+  ID(shar); S2R(rsrc); SR(rdst); DR(rdst); F("0SZC");
+
+/** 1111 1101 101immmm rsrc rdst       shar    #%2, %1, %0 */
+  ID(shar); S2C(immmm); SR(rsrc); DR(rdst); F("0SZC");
+
+
+/** 0110 100i mmmm rdst                        shlr    #%2, %0 */
+  ID(shlr); S2C(i*16+mmmm); SR(rdst); DR(rdst); F("-SZC");
+
+/** 1111 1101 0110 0000 rsrc rdst      shlr    %2, %0 */
+  ID(shlr); S2R(rsrc); SR(rdst); DR(rdst); F("-SZC");
+
+/** 1111 1101 100immmm rsrc rdst       shlr    #%2, %1, %0 */
+  ID(shlr); S2C(immmm); SR(rsrc); DR(rdst); F("-SZC");
+
+/*----------------------------------------------------------------------*/
+/* ROTATE                                                              */
+
+/** 0111 1110 0101 rdst                        rolc    %0 */
+  ID(rolc); DR(rdst); F("-SZC");
+
+/** 0111 1110 0100 rdst                        rorc    %0 */
+  ID(rorc); DR(rdst); F("-SZC");
+
+/** 1111 1101 0110 111i mmmm rdst      rotl    #%1, %0 */
+  ID(rotl); SC(i*16+mmmm); DR(rdst); F("-SZC");
+
+/** 1111 1101 0110 0110 rsrc rdst      rotl    %1, %0 */
+  ID(rotl); SR(rsrc); DR(rdst); F("-SZC");
+
+/** 1111 1101 0110 110i mmmm rdst      rotr    #%1, %0 */
+  ID(rotr); SC(i*16+mmmm); DR(rdst); F("-SZC");
+
+/** 1111 1101 0110 0100 rsrc rdst      rotr    %1, %0 */
+  ID(rotr); SR(rsrc); DR(rdst); F("-SZC");
+
+/** 1111 1101 0110 0101 rsrc rdst      revw    %1, %0 */
+  ID(revw); SR(rsrc); DR(rdst);
+
+/** 1111 1101 0110 0111 rsrc rdst      revl    %1, %0 */
+  ID(revl); SR(rsrc); DR(rdst);
+
+/*----------------------------------------------------------------------*/
+/* BRANCH                                                              */
+
+/** 0001 n dsp                 b%1.s   %a0 */
+  ID(branch); Scc(n); DC(pc + dsp3map[dsp]);
+
+/** 0010 cond                  b%1.b   %a0 */
+  ID(branch); Scc(cond); DC(pc + IMMex (1));
+
+/** 0011 101c                  b%1.w   %a0 */
+  ID(branch); Scc(c); DC(pc + IMMex (2));
+
+
+/** 0000 1dsp                  bra.s   %a0 */
+  ID(branch); Scc(RXC_always); DC(pc + dsp3map[dsp]);
+
+/** 0010 1110                  bra.b   %a0 */
+  ID(branch); Scc(RXC_always); DC(pc + IMMex(1));
+
+/** 0011 1000                  bra.w   %a0 */
+  ID(branch); Scc(RXC_always); DC(pc + IMMex(2));
+
+/** 0000 0100                  bra.a   %a0 */
+  ID(branch); Scc(RXC_always); DC(pc + IMMex(3));
+
+/** 0111 1111 0100 rsrc                bra.l   %0 */
+  ID(branchrel); Scc(RXC_always); DR(rsrc);
+
+
+/** 0111 1111 0000 rsrc                jmp     %0 */
+  ID(branch); Scc(RXC_always); DR(rsrc);
+
+/** 0111 1111 0001 rsrc                jsr     %0 */
+  ID(jsr); DR(rsrc);
+
+/** 0011 1001                  bsr.w   %a0 */
+  ID(jsr); DC(pc + IMMex(2));
+
+/** 0000 0101                  bsr.a   %a0 */
+  ID(jsr); DC(pc + IMMex(3));
+
+/** 0111 1111 0101 rsrc                bsr.l   %0 */
+  ID(jsrrel); DR(rsrc);
+
+/** 0000 0010                  rts */
+  ID(rts);
+
+/*----------------------------------------------------------------------*/
+/* NOP                                                         */
+
+/** 0000 0011                  nop */
+  ID(nop);
+
+/*----------------------------------------------------------------------*/
+/* STRING FUNCTIONS                                                    */
+
+/** 0111 1111 1000 0011                scmpu */
+  ID(scmpu); F("--ZC");
+
+/** 0111 1111 1000 0111                smovu */
+  ID(smovu);
+
+/** 0111 1111 1000 1011                smovb */
+  ID(smovb);
+
+/** 0111 1111 1000 00sz                suntil%s */
+  ID(suntil); BWL(sz); F("OSZC");
+
+/** 0111 1111 1000 01sz                swhile%s */
+  ID(swhile); BWL(sz); F("OSZC");
+
+/** 0111 1111 1000 1111                smovf */
+  ID(smovf);
+
+/** 0111 1111 1000 10sz                sstr%s */
+  ID(sstr); BWL(sz);
+
+/*----------------------------------------------------------------------*/
+/* RMPA                                                                        */
+
+/** 0111 1111 1000 11sz                rmpa%s */
+  ID(rmpa); BWL(sz); F("OS--");
+
+/*----------------------------------------------------------------------*/
+/* HI/LO stuff                                                         */
+
+/** 1111 1101 0000 0000 srca srcb      mulhi   %1, %2 */
+  ID(mulhi); SR(srca); S2R(srcb); F("----");
+
+/** 1111 1101 0000 0001 srca srcb      mullo   %1, %2 */
+  ID(mullo); SR(srca); S2R(srcb); F("----");
+
+/** 1111 1101 0000 0100 srca srcb      machi   %1, %2 */
+  ID(machi); SR(srca); S2R(srcb); F("----");
+
+/** 1111 1101 0000 0101 srca srcb      maclo   %1, %2 */
+  ID(maclo); SR(srca); S2R(srcb); F("----");
+
+/** 1111 1101 0001 0111 0000 rsrc      mvtachi %1 */
+  ID(mvtachi); SR(rsrc); F("----");
+
+/** 1111 1101 0001 0111 0001 rsrc      mvtaclo %1 */
+  ID(mvtaclo); SR(rsrc); F("----");
+
+/** 1111 1101 0001 1111 0000 rdst      mvfachi %0 */
+  ID(mvfachi); DR(rdst); F("----");
+
+/** 1111 1101 0001 1111 0010 rdst      mvfacmi %0 */
+  ID(mvfacmi); DR(rdst); F("----");
+
+/** 1111 1101 0001 1111 0001 rdst      mvfaclo %0 */
+  ID(mvfaclo); DR(rdst); F("----");
+
+/** 1111 1101 0001 1000 000i 0000      racw    #%1 */
+  ID(racw); SC(i+1); F("----");
+
+/*----------------------------------------------------------------------*/
+/* SAT                                                                 */
+
+/** 0111 1110 0011 rdst                sat     %0 */
+  ID(sat); DR (rdst);
+
+/** 0111 1111 1001 0011                satr */
+  ID(satr);
+
+/*----------------------------------------------------------------------*/
+/* FLOAT                                                               */
+
+/** 1111 1101 0111 0010 0010 rdst      fadd    #%1, %0 */
+  ID(fadd); DR(rdst); SC(IMM(0)); F("-SZ-");
+
+/** 1111 1100 1000 10sd rsrc rdst      fadd    %1%S1, %0 */
+  ID(fadd); DR(rdst); SD(sd, rsrc, LSIZE); F("-SZ-");
+
+/** 1111 1101 0111 0010 0001 rdst      fcmp    #%1, %0 */
+  ID(fcmp); DR(rdst); SC(IMM(0)); F("OSZ-");
+
+/** 1111 1100 1000 01sd rsrc rdst      fcmp    %1%S1, %0 */
+  ID(fcmp); DR(rdst); SD(sd, rsrc, LSIZE); F("OSZ-");
+
+/** 1111 1101 0111 0010 0000 rdst      fsub    #%1, %0 */
+  ID(fsub); DR(rdst); SC(IMM(0)); F("-SZ-");
+
+/** 1111 1100 1000 00sd rsrc rdst      fsub    %1%S1, %0 */
+  ID(fsub); DR(rdst); SD(sd, rsrc, LSIZE); F("-SZ-");
+
+/** 1111 1100 1001 01sd rsrc rdst      ftoi    %1%S1, %0 */
+  ID(ftoi); DR(rdst); SD(sd, rsrc, LSIZE); F("-SZ-");
+
+/** 1111 1101 0111 0010 0011 rdst      fmul    #%1, %0 */
+  ID(fmul); DR(rdst); SC(IMM(0)); F("-SZ-");
+
+/** 1111 1100 1000 11sd rsrc rdst      fmul    %1%S1, %0 */
+  ID(fmul); DR(rdst); SD(sd, rsrc, LSIZE); F("-SZ-");
+
+/** 1111 1101 0111 0010 0100 rdst      fdiv    #%1, %0 */
+  ID(fdiv); DR(rdst); SC(IMM(0)); F("-SZ-");
+
+/** 1111 1100 1001 00sd rsrc rdst      fdiv    %1%S1, %0 */
+  ID(fdiv); DR(rdst); SD(sd, rsrc, LSIZE); F("-SZ-");
+
+/** 1111 1100 1001 10sd rsrc rdst      round   %1%S1, %0 */
+  ID(round); DR(rdst); SD(sd, rsrc, LSIZE); F("-SZ-");
+
+/** 1111 1100 0100 01sd rsrc rdst      itof    %1%S1, %0 */
+  ID(itof); DR (rdst); SP(sd, rsrc); F("-SZ-");
+
+/** 0000 0110 mx10 00sd 0001 0001 rsrc rdst    itof    %1%S1, %0 */
+  ID(itof); DR (rdst); SPm(sd, rsrc, mx); F("-SZ-");
+
+/*----------------------------------------------------------------------*/
+/* BIT OPS                                                             */
+
+/** 1111 00sd rdst 0bit                        bset    #%1, %0%S0 */
+  ID(bset); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE); F("----");
+
+/** 1111 1100 0110 00sd rdst rsrc      bset    %1, %0%S0 */
+  ID(bset); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE); F("----");
+
+/** 0111 100b ittt rdst                        bset    #%1, %0 */
+  ID(bset); BWL(LSIZE); SC(b*16+ittt); DR(rdst); F("----");
+
+
+/** 1111 00sd rdst 1bit                        bclr    #%1, %0%S0 */
+  ID(bclr); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE); F("----");
+
+/** 1111 1100 0110 01sd rdst rsrc      bclr    %1, %0%S0 */
+  ID(bclr); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE); F("----");
+
+/** 0111 101b ittt rdst                        bclr    #%1, %0 */
+  ID(bclr); BWL(LSIZE); SC(b*16+ittt); DR(rdst); F("----");
+
+
+/** 1111 01sd rdst 0bit                        btst    #%2, %1%S1 */
+  ID(btst); BWL(BSIZE); S2C(bit); SD(sd, rdst, BSIZE); F("--ZC");
+
+/** 1111 1100 0110 10sd rdst rsrc      btst    %2, %1%S1 */
+  ID(btst); BWL(BSIZE); S2R(rsrc); SD(sd, rdst, BSIZE); F("--ZC");
+
+/** 0111 110b ittt rdst                        btst    #%2, %1 */
+  ID(btst); BWL(LSIZE); S2C(b*16+ittt); SR(rdst); F("--ZC");
+
+
+/** 1111 1100 111bit sd rdst 1111      bnot    #%1, %0%S0 */
+  ID(bnot); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE);
+
+/** 1111 1100 0110 11sd rdst rsrc      bnot    %1, %0%S0 */
+  ID(bnot); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE);
+
+/** 1111 1101 111bittt 1111 rdst       bnot    #%1, %0 */
+  ID(bnot); BWL(LSIZE); SC(bittt); DR(rdst);
+
+
+/** 1111 1100 111bit sd rdst cond      bm%2    #%1, %0%S0 */
+  ID(bmcc); BWL(BSIZE); S2cc(cond); SC(bit); DD(sd, rdst, BSIZE);
+
+/** 1111 1101 111 bittt cond rdst      bm%2    #%1, %0%S0 */
+  ID(bmcc); BWL(LSIZE); S2cc(cond); SC(bittt); DR(rdst);
+
+/*----------------------------------------------------------------------*/
+/* CONTROL REGISTERS                                                   */
+
+/** 0111 1111 1011 rdst                        clrpsw  %0 */
+  ID(clrpsw); DF(rdst);
+
+/** 0111 1111 1010 rdst                        setpsw  %0 */
+  ID(setpsw); DF(rdst);
+
+/** 0111 1110 111 crdst                        popc    %0 */
+  ID(mov); OP(1, RX_Operand_Postinc, 0, 0); DR(crdst + 16);
+
+/** 0111 1110 110 crsrc                        pushc   %1 */
+  ID(mov); OP(0, RX_Operand_Predec, 0, 0); SR(crsrc + 16);
+
+/** 1111 1101 0111 im11 000crdst       mvtc    #%1, %0 */
+  ID(mov); SC(IMMex(im)); DR(crdst + 16);
+
+/** 1111 1101 0110 100c rsrc rdst      mvtc    %1, %0 */
+  ID(mov); SR(rsrc); DR(c*16+rdst + 16);
+
+/** 1111 1101 0110 101s rsrc rdst      mvfc    %1, %0 */
+  ID(mov); SR((s*16+rsrc) + 16); DR(rdst);
+
+/*?* 1111 1101 1111 1010 01cp rsrc     mvtcp   #%2, %1, #%0 */
+  ID(mvtcp); S2C(cp); SR(rsrc); DC (IMM (WSIZE));
+
+/*?* 1111 1101 1111 1011 01cp rdst     mvfcp   #%2, %0, #%1 */
+  ID(mvfcp); S2C(cp); DR(rdst); SC (IMM (WSIZE));
+
+/*?* 1111 1101 1111 1001 01cp 0000     opecp   #%2, #%1 */
+  ID(opecp); S2C(cp); SC (IMM (WSIZE));
+
+/*----------------------------------------------------------------------*/
+/* INTERRUPTS                                                          */
+
+/** 0111 1111 1001 0100                rtfi */
+  ID(rtfi);
+
+/** 0111 1111 1001 0101                rte */
+  ID(rte);
+
+/** 0000 0000                  brk */
+  ID(brk);
+
+/** 0000 0001                  dbt */
+  ID(dbt);
+
+/** 0111 0101 0110 0000                int #%1 */
+  ID(int); SC(IMM(1));
+
+/** 0111 1111 1001 0110                wait */
+  ID(wait);
+
+/*----------------------------------------------------------------------*/
+/* SCcnd                                                               */
+
+/** 1111 1100 1101 sz sd rdst cond     sc%1%s  %0 */
+  ID(sccnd); BWL(sz); DD (sd, rdst, sz); Scc(cond);
+
+/** */
+
+  return rx->n_bytes;
+}

diff --git a/opcodes/rx-dis.c b/opcodes/rx-dis.c
new file mode 100644 (file)
index 0000000..3413b1d
--- /dev/null
+++ b/opcodes/rx-dis.c
@@ -0,0 +1,199 @@
+/* Disassembler code for Renesas RX.
+   Copyright 2008, 2009 Free Software Foundation, Inc.
+   Contributed by Red Hat.
+   Written by DJ Delorie.
+
+   This file is part of the GNU opcodes library.
+
+   This library is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#include <stdio.h>
+
+#include "bfd.h"
+#include "dis-asm.h"
+#include "opcode/rx.h"
+
+typedef struct
+{
+  bfd_vma pc;
+  disassemble_info * dis;
+} RX_Data;
+
+static int
+rx_get_byte (void * vdata)
+{
+  bfd_byte buf[1];
+  RX_Data *rx_data = (RX_Data *) vdata;
+
+  rx_data->dis->read_memory_func (rx_data->pc,
+                                 buf,
+                                 1,
+                                 rx_data->dis);
+
+  rx_data->pc ++;
+  return buf[0];
+}
+
+static char const * size_names[] =
+{
+  "", ".b", ".ub", ".b", ".w", ".uw", ".w", ".a", ".l"
+};
+
+static char const * opsize_names[] =
+{
+  "", ".b", ".b", ".b", ".w", ".w", ".w", ".a", ".l"
+};
+
+static char const * register_names[] =
+{
+  /* general registers */
+  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+  /* control register */
+  "psw", "pc", "usp", "fpsw", "cpen", "", "", "wr",
+  "bpsw", "bpc", "isp", "fintv", "intb", "", "", "",
+  "pbp", "pben", "", "", "", "", "", "",
+  "bbpsw", "bbpc", "", "", "", "", "", ""
+};
+
+static char const * condition_names[] =
+{
+  /* condition codes */
+  "eq", "ne", "c", "nc", "gtu", "leu", "pz", "n",
+  "ge", "lt", "gt", "le", "o", "no", "always", "never"
+};
+
+static const char * flag_names[] =
+{
+  "c", "z", "s", "o", "", "", "", "",
+  "", "", "", "", "", "", "", "",
+  "i", "u", "", "", "", "", "", ""
+  "", "", "", "", "", "", "", "",
+};
+
+int
+print_insn_rx (bfd_vma addr, disassemble_info * dis)
+{
+  int rv;
+  RX_Data rx_data;
+  RX_Opcode_Decoded opcode;
+  const char * s;
+
+  rx_data.pc = addr;
+  rx_data.dis = dis;
+
+  rv = rx_decode_opcode (addr, &opcode, rx_get_byte, &rx_data);
+
+  dis->bytes_per_line = 10;
+
+#define PR (dis->fprintf_func)
+#define PS (dis->stream)
+#define PC(c) PR (PS, "%c", c)
+
+  for (s = opcode.syntax; *s; s++)
+    {
+      if (*s != '%')
+       {
+         PC (*s);
+       }
+      else
+       {
+         RX_Opcode_Operand * oper;
+         int do_size = 0;
+         int do_hex = 0;
+         int do_addr = 0;
+
+         s ++;
+
+         if (*s == 'S')
+           {
+             do_size = 1;
+             s++;
+           }
+         if (*s == 'x')
+           {
+             do_hex = 1;
+             s++;
+           }
+         if (*s == 'a')
+           {
+             do_addr = 1;
+             s++;
+           }
+
+         switch (*s)
+           {
+           case '%':
+             PC ('%');
+             break;
+
+           case 's':
+             PR (PS, "%s", opsize_names[opcode.size]);
+             break;
+
+           case '0':
+           case '1':
+           case '2':
+             oper = opcode.op + *s - '0';
+             if (do_size)
+               {
+                 if (oper->type == RX_Operand_Indirect)
+                   PR (PS, "%s", size_names[oper->size]);
+               }
+             else
+               switch (oper->type)
+                 {
+                 case RX_Operand_Immediate:
+                   if (do_addr)
+                     dis->print_address_func (oper->addend, dis);
+                   else if (do_hex
+                            || oper->addend > 999
+                            || oper->addend < -999)
+                     PR (PS, "%#x", oper->addend);
+                   else
+                     PR (PS, "%d", oper->addend);
+                   break;
+                 case RX_Operand_Register:
+                   PR (PS, "%s", register_names[oper->reg]);
+                   break;
+                 case RX_Operand_Indirect:
+                   if (oper->addend)
+                     PR (PS, "%d[%s]", oper->addend, register_names[oper->reg]);
+                   else
+                     PR (PS, "[%s]", register_names[oper->reg]);
+                   break;
+                 case RX_Operand_Postinc:
+                   PR (PS, "[%s+]", register_names[oper->reg]);
+                   break;
+                 case RX_Operand_Predec:
+                   PR (PS, "[-%s]", register_names[oper->reg]);
+                   break;
+                 case RX_Operand_Condition:
+                   PR (PS, "%s", condition_names[oper->reg]);
+                   break;
+                 case RX_Operand_Flag:
+                   PR (PS, "%s", flag_names[oper->reg]);
+                   break;
+                 default:
+                   PR (PS, "[???]");
+                   break;
+                 }
+           }
+       }
+    }
+
+  return rv;
+}

diff --git a/sim/common/ChangeLog b/sim/common/ChangeLog
index 3facbce..26f00e6 100644 (file)
--- a/sim/common/ChangeLog
+++ b/sim/common/ChangeLog
@@ -1,3 +1,7 @@
+2009-10-02  Ralf Corsepius <ralf.corsepius@rtems.org>
+
+       * Make-common.in: Add datarootdir.
+
 2009-08-29  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 
        * aclocal.m4 (SIM_CHECK_MEMBER, SIM_CHECK_MEMBERS)

diff --git a/sim/common/Make-common.in b/sim/common/Make-common.in
index b6b05a4..cf680de 100644 (file)
--- a/sim/common/Make-common.in
+++ b/sim/common/Make-common.in
@@ -52,6 +52,7 @@ libdir = @libdir@
 tooldir = $(libdir)/$(target_alias)
 
 datadir = @datadir@
+datarootdir = @datarootdir@
 mandir = @mandir@
 man1dir = $(mandir)/man1
 infodir = @infodir@

diff --git a/sim/configure b/sim/configure
index 431bec1..c5b4705 100755 (executable)
--- a/sim/configure
+++ b/sim/configure
@@ -646,6 +646,7 @@ m32c
 m32r
 m68hc11
 mcore
+microblaze
 mips
 mn10300
 moxie
@@ -3678,6 +3679,11 @@ subdirs="$subdirs arm"
 
           testsuite=yes
           ;;
+       microblaze-*-*)
+           subdirs="$subdirs microblaze"
+
+          testsuite=yes
+          ;;
        mips*-*-*)
            subdirs="$subdirs mips"
 

diff --git a/sim/configure.ac b/sim/configure.ac
index 9a55a0c..a113c3a 100644 (file)
--- a/sim/configure.ac
+++ b/sim/configure.ac
@@ -97,6 +97,10 @@ if test "${enable_sim}" != no; then
            AC_CONFIG_SUBDIRS(mcore)
           testsuite=yes
           ;;
+       microblaze-*-*)
+           AC_CONFIG_SUBDIRS(microblaze)
+          testsuite=yes
+          ;;
        mips*-*-*)
            AC_CONFIG_SUBDIRS(mips)
           testsuite=yes

diff --git a/sim/microblaze/Makefile.in b/sim/microblaze/Makefile.in
new file mode 100644 (file)
index 0000000..f8babfe
--- /dev/null
+++ b/sim/microblaze/Makefile.in
@@ -0,0 +1,29 @@
+#    Makefile template for Configure for the MCore sim library.
+#    Copyright (C) 1990, 91, 92, 95, 96, 19, 1999, 2007, 2008, 2009
+#    Free Software Foundation, Inc.
+#    Written by Cygnus Solutions.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+## COMMON_PRE_CONFIG_FRAG
+
+SIM_OBJS = interp.o sim-load.o
+SIM_EXTRA_LIBS = -lm
+SIM_EXTRA_CLEAN = microblaze-clean
+
+## COMMON_POST_CONFIG_FRAG
+
+interp.o: interp.c
+
+microblaze-clean:

diff --git a/sim/microblaze/config.in b/sim/microblaze/config.in
new file mode 100644 (file)
index 0000000..f29d045
--- /dev/null
+++ b/sim/microblaze/config.in
@@ -0,0 +1,104 @@
+/* config.in.  Generated from configure.ac by autoheader.  */
+
+/* Define to 1 if translation of program messages to the user's native
+   language is requested. */
+#undef ENABLE_NLS
+
+/* Define to 1 if you have the <dlfcn.h> header file. */
+#undef HAVE_DLFCN_H
+
+/* Define to 1 if you have the <errno.h> header file. */
+#undef HAVE_ERRNO_H
+
+/* Define to 1 if you have the <fcntl.h> header file. */
+#undef HAVE_FCNTL_H
+
+/* Define to 1 if you have the <fpu_control.h> header file. */
+#undef HAVE_FPU_CONTROL_H
+
+/* Define to 1 if you have the `getrusage' function. */
+#undef HAVE_GETRUSAGE
+
+/* Define to 1 if you have the <inttypes.h> header file. */
+#undef HAVE_INTTYPES_H
+
+/* Define to 1 if you have the `nsl' library (-lnsl). */
+#undef HAVE_LIBNSL
+
+/* Define to 1 if you have the `socket' library (-lsocket). */
+#undef HAVE_LIBSOCKET
+
+/* Define to 1 if you have the <memory.h> header file. */
+#undef HAVE_MEMORY_H
+
+/* Define to 1 if you have the `sigaction' function. */
+#undef HAVE_SIGACTION
+
+/* Define to 1 if you have the <stdint.h> header file. */
+#undef HAVE_STDINT_H
+
+/* Define to 1 if you have the <stdlib.h> header file. */
+#undef HAVE_STDLIB_H
+
+/* Define to 1 if you have the <strings.h> header file. */
+#undef HAVE_STRINGS_H
+
+/* Define to 1 if you have the <string.h> header file. */
+#undef HAVE_STRING_H
+
+/* Define to 1 if you have the <sys/resource.h> header file. */
+#undef HAVE_SYS_RESOURCE_H
+
+/* Define to 1 if you have the <sys/stat.h> header file. */
+#undef HAVE_SYS_STAT_H
+
+/* Define to 1 if you have the <sys/time.h> header file. */
+#undef HAVE_SYS_TIME_H
+
+/* Define to 1 if you have the <sys/types.h> header file. */
+#undef HAVE_SYS_TYPES_H
+
+/* Define to 1 if you have the `time' function. */
+#undef HAVE_TIME
+
+/* Define to 1 if you have the <time.h> header file. */
+#undef HAVE_TIME_H
+
+/* Define to 1 if you have the <unistd.h> header file. */
+#undef HAVE_UNISTD_H
+
+/* Define to 1 if you have the <zlib.h> header file. */
+#undef HAVE_ZLIB_H
+
+/* Define to 1 if you have the `__setfpucw' function. */
+#undef HAVE___SETFPUCW
+
+/* Define to the address where bug reports for this package should be sent. */
+#undef PACKAGE_BUGREPORT
+
+/* Define to the full name of this package. */
+#undef PACKAGE_NAME
+
+/* Define to the full name and version of this package. */
+#undef PACKAGE_STRING
+
+/* Define to the one symbol short name of this package. */
+#undef PACKAGE_TARNAME
+
+/* Define to the home page for this package. */
+#undef PACKAGE_URL
+
+/* Define to the version of this package. */
+#undef PACKAGE_VERSION
+
+/* Additional package description */
+#undef PKGVERSION
+
+/* Bug reporting address */
+#undef REPORT_BUGS_TO
+
+/* Define as the return type of signal handlers (`int' or `void'). */
+#undef RETSIGTYPE
+
+/* Define to 1 if you have the ANSI C header files. */
+#undef STDC_HEADERS

diff --git a/sim/microblaze/configure b/sim/microblaze/configure
new file mode 100644 (file)
index 0000000..23075a8
--- /dev/null
+++ b/sim/microblaze/configure
@@ -0,0 +1,7004 @@
+#! /bin/sh
+# Guess values for system-dependent variables and create Makefiles.
+# Generated by GNU Autoconf 2.63.
+#
+# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001,
+# 2002, 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
+# This configure script is free software; the Free Software Foundation
+# gives unlimited permission to copy, distribute and modify it.
+## --------------------- ##
+## M4sh Initialization.  ##
+## --------------------- ##
+
+# Be more Bourne compatible
+DUALCASE=1; export DUALCASE # for MKS sh
+if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then
+  emulate sh
+  NULLCMD=:
+  # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which
+  # is contrary to our usage.  Disable this feature.
+  alias -g '${1+"$@"}'='"$@"'
+  setopt NO_GLOB_SUBST
+else
+  case `(set -o) 2>/dev/null` in
+  *posix*) set -o posix ;;
+esac
+
+fi
+
+
+
+
+# PATH needs CR
+# Avoid depending upon Character Ranges.
+as_cr_letters='abcdefghijklmnopqrstuvwxyz'
+as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
+as_cr_Letters=$as_cr_letters$as_cr_LETTERS
+as_cr_digits='0123456789'
+as_cr_alnum=$as_cr_Letters$as_cr_digits
+
+as_nl='
+'
+export as_nl
+# Printing a long string crashes Solaris 7 /usr/bin/printf.
+as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\'
+as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo
+as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo
+if (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then
+  as_echo='printf %s\n'
+  as_echo_n='printf %s'
+else
+  if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then
+    as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"'
+    as_echo_n='/usr/ucb/echo -n'
+  else
+    as_echo_body='eval expr "X$1" : "X\\(.*\\)"'
+    as_echo_n_body='eval
+      arg=$1;
+      case $arg in
+      *"$as_nl"*)
+       expr "X$arg" : "X\\(.*\\)$as_nl";
+       arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;;
+      esac;
+      expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl"
+    '
+    export as_echo_n_body
+    as_echo_n='sh -c $as_echo_n_body as_echo'
+  fi
+  export as_echo_body
+  as_echo='sh -c $as_echo_body as_echo'
+fi
+
+# The user is always right.
+if test "${PATH_SEPARATOR+set}" != set; then
+  PATH_SEPARATOR=:
+  (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && {
+    (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 ||
+      PATH_SEPARATOR=';'
+  }
+fi
+
+# Support unset when possible.
+if ( (MAIL=60; unset MAIL) || exit) >/dev/null 2>&1; then
+  as_unset=unset
+else
+  as_unset=false
+fi
+
+
+# IFS
+# We need space, tab and new line, in precisely that order.  Quoting is
+# there to prevent editors from complaining about space-tab.
+# (If _AS_PATH_WALK were called with IFS unset, it would disable word
+# splitting by setting IFS to empty value.)
+IFS=" ""       $as_nl"
+
+# Find who we are.  Look in the path if we contain no directory separator.
+case $0 in
+  *[\\/]* ) as_myself=$0 ;;
+  *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break
+done
+IFS=$as_save_IFS
+
+     ;;
+esac
+# We did not find ourselves, most probably we were run as `sh COMMAND'
+# in which case we are not to be found in the path.
+if test "x$as_myself" = x; then
+  as_myself=$0
+fi
+if test ! -f "$as_myself"; then
+  $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2
+  { (exit 1); exit 1; }
+fi
+
+# Work around bugs in pre-3.0 UWIN ksh.
+for as_var in ENV MAIL MAILPATH
+do ($as_unset $as_var) >/dev/null 2>&1 && $as_unset $as_var
+done
+PS1='$ '
+PS2='> '
+PS4='+ '
+
+# NLS nuisances.
+LC_ALL=C
+export LC_ALL
+LANGUAGE=C
+export LANGUAGE
+
+# Required to use basename.
+if expr a : '\(a\)' >/dev/null 2>&1 &&
+   test "X`expr 00001 : '.*\(...\)'`" = X001; then
+  as_expr=expr
+else
+  as_expr=false
+fi
+
+if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then
+  as_basename=basename
+else
+  as_basename=false
+fi
+
+
+# Name of the executable.
+as_me=`$as_basename -- "$0" ||
+$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \
+        X"$0" : 'X\(//\)$' \| \
+        X"$0" : 'X\(/\)' \| . 2>/dev/null ||
+$as_echo X/"$0" |
+    sed '/^.*\/\([^/][^/]*\)\/*$/{
+           s//\1/
+           q
+         }
+         /^X\/\(\/\/\)$/{
+           s//\1/
+           q
+         }
+         /^X\/\(\/\).*/{
+           s//\1/
+           q
+         }
+         s/.*/./; q'`
+
+# CDPATH.
+$as_unset CDPATH
+
+
+if test "x$CONFIG_SHELL" = x; then
+  if (eval ":") 2>/dev/null; then
+  as_have_required=yes
+else
+  as_have_required=no
+fi
+
+  if test $as_have_required = yes &&    (eval ":
+(as_func_return () {
+  (exit \$1)
+}
+as_func_success () {
+  as_func_return 0
+}
+as_func_failure () {
+  as_func_return 1
+}
+as_func_ret_success () {
+  return 0
+}
+as_func_ret_failure () {
+  return 1
+}
+
+exitcode=0
+if as_func_success; then
+  :
+else
+  exitcode=1
+  echo as_func_success failed.
+fi
+
+if as_func_failure; then
+  exitcode=1
+  echo as_func_failure succeeded.
+fi
+
+if as_func_ret_success; then
+  :
+else
+  exitcode=1
+  echo as_func_ret_success failed.
+fi
+
+if as_func_ret_failure; then
+  exitcode=1
+  echo as_func_ret_failure succeeded.
+fi
+
+if ( set x; as_func_ret_success y && test x = \"\$1\" ); then
+  :
+else
+  exitcode=1
+  echo positional parameters were not saved.
+fi
+
+test \$exitcode = 0) || { (exit 1); exit 1; }
+
+(
+  as_lineno_1=\$LINENO
+  as_lineno_2=\$LINENO
+  test \"x\$as_lineno_1\" != \"x\$as_lineno_2\" &&
+  test \"x\`expr \$as_lineno_1 + 1\`\" = \"x\$as_lineno_2\") || { (exit 1); exit 1; }
+") 2> /dev/null; then
+  :
+else
+  as_candidate_shells=
+    as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  case $as_dir in
+        /*)
+          for as_base in sh bash ksh sh5; do
+            as_candidate_shells="$as_candidate_shells $as_dir/$as_base"
+          done;;
+       esac
+done
+IFS=$as_save_IFS
+
+
+      for as_shell in $as_candidate_shells $SHELL; do
+        # Try only shells that exist, to save several forks.
+        if { test -f "$as_shell" || test -f "$as_shell.exe"; } &&
+               { ("$as_shell") 2> /dev/null <<\_ASEOF
+if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then
+  emulate sh
+  NULLCMD=:
+  # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which
+  # is contrary to our usage.  Disable this feature.
+  alias -g '${1+"$@"}'='"$@"'
+  setopt NO_GLOB_SUBST
+else
+  case `(set -o) 2>/dev/null` in
+  *posix*) set -o posix ;;
+esac
+
+fi
+
+
+:
+_ASEOF
+}; then
+  CONFIG_SHELL=$as_shell
+              as_have_required=yes
+              if { "$as_shell" 2> /dev/null <<\_ASEOF
+if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then
+  emulate sh
+  NULLCMD=:
+  # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which
+  # is contrary to our usage.  Disable this feature.
+  alias -g '${1+"$@"}'='"$@"'
+  setopt NO_GLOB_SUBST
+else
+  case `(set -o) 2>/dev/null` in
+  *posix*) set -o posix ;;
+esac
+
+fi
+
+
+:
+(as_func_return () {
+  (exit $1)
+}
+as_func_success () {
+  as_func_return 0
+}
+as_func_failure () {
+  as_func_return 1
+}
+as_func_ret_success () {
+  return 0
+}
+as_func_ret_failure () {
+  return 1
+}
+
+exitcode=0
+if as_func_success; then
+  :
+else
+  exitcode=1
+  echo as_func_success failed.
+fi
+
+if as_func_failure; then
+  exitcode=1
+  echo as_func_failure succeeded.
+fi
+
+if as_func_ret_success; then
+  :
+else
+  exitcode=1
+  echo as_func_ret_success failed.
+fi
+
+if as_func_ret_failure; then
+  exitcode=1
+  echo as_func_ret_failure succeeded.
+fi
+
+if ( set x; as_func_ret_success y && test x = "$1" ); then
+  :
+else
+  exitcode=1
+  echo positional parameters were not saved.
+fi
+
+test $exitcode = 0) || { (exit 1); exit 1; }
+
+(
+  as_lineno_1=$LINENO
+  as_lineno_2=$LINENO
+  test "x$as_lineno_1" != "x$as_lineno_2" &&
+  test "x`expr $as_lineno_1 + 1`" = "x$as_lineno_2") || { (exit 1); exit 1; }
+
+_ASEOF
+}; then
+  break
+fi
+
+fi
+
+      done
+
+      if test "x$CONFIG_SHELL" != x; then
+  for as_var in BASH_ENV ENV
+       do ($as_unset $as_var) >/dev/null 2>&1 && $as_unset $as_var
+       done
+       export CONFIG_SHELL
+       exec "$CONFIG_SHELL" "$as_myself" ${1+"$@"}
+fi
+
+
+    if test $as_have_required = no; then
+  echo This script requires a shell more modern than all the
+      echo shells that I found on your system.  Please install a
+      echo modern shell, or manually run the script under such a
+      echo shell if you do have one.
+      { (exit 1); exit 1; }
+fi
+
+
+fi
+
+fi
+
+
+
+(eval "as_func_return () {
+  (exit \$1)
+}
+as_func_success () {
+  as_func_return 0
+}
+as_func_failure () {
+  as_func_return 1
+}
+as_func_ret_success () {
+  return 0
+}
+as_func_ret_failure () {
+  return 1
+}
+
+exitcode=0
+if as_func_success; then
+  :
+else
+  exitcode=1
+  echo as_func_success failed.
+fi
+
+if as_func_failure; then
+  exitcode=1
+  echo as_func_failure succeeded.
+fi
+
+if as_func_ret_success; then
+  :
+else
+  exitcode=1
+  echo as_func_ret_success failed.
+fi
+
+if as_func_ret_failure; then
+  exitcode=1
+  echo as_func_ret_failure succeeded.
+fi
+
+if ( set x; as_func_ret_success y && test x = \"\$1\" ); then
+  :
+else
+  exitcode=1
+  echo positional parameters were not saved.
+fi
+
+test \$exitcode = 0") || {
+  echo No shell found that supports shell functions.
+  echo Please tell bug-autoconf@gnu.org about your system,
+  echo including any error possibly output before this message.
+  echo This can help us improve future autoconf versions.
+  echo Configuration will now proceed without shell functions.
+}
+
+
+
+  as_lineno_1=$LINENO
+  as_lineno_2=$LINENO
+  test "x$as_lineno_1" != "x$as_lineno_2" &&
+  test "x`expr $as_lineno_1 + 1`" = "x$as_lineno_2" || {
+
+  # Create $as_me.lineno as a copy of $as_myself, but with $LINENO
+  # uniformly replaced by the line number.  The first 'sed' inserts a
+  # line-number line after each line using $LINENO; the second 'sed'
+  # does the real work.  The second script uses 'N' to pair each
+  # line-number line with the line containing $LINENO, and appends
+  # trailing '-' during substitution so that $LINENO is not a special
+  # case at line end.
+  # (Raja R Harinath suggested sed '=', and Paul Eggert wrote the
+  # scripts with optimization help from Paolo Bonzini.  Blame Lee
+  # E. McMahon (1931-1989) for sed's syntax.  :-)
+  sed -n '
+    p
+    /[$]LINENO/=
+  ' <$as_myself |
+    sed '
+      s/[$]LINENO.*/&-/
+      t lineno
+      b
+      :lineno
+      N
+      :loop
+      s/[$]LINENO\([^'$as_cr_alnum'_].*\n\)\(.*\)/\2\1\2/
+      t loop
+      s/-\n.*//
+    ' >$as_me.lineno &&
+  chmod +x "$as_me.lineno" ||
+    { $as_echo "$as_me: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&2
+   { (exit 1); exit 1; }; }
+
+  # Don't try to exec as it changes $[0], causing all sort of problems
+  # (the dirname of $[0] is not the place where we might find the
+  # original and so on.  Autoconf is especially sensitive to this).
+  . "./$as_me.lineno"
+  # Exit status is that of the last command.
+  exit
+}
+
+
+if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then
+  as_dirname=dirname
+else
+  as_dirname=false
+fi
+
+ECHO_C= ECHO_N= ECHO_T=
+case `echo -n x` in
+-n*)
+  case `echo 'x\c'` in
+  *c*) ECHO_T='        ';;     # ECHO_T is single tab character.
+  *)   ECHO_C='\c';;
+  esac;;
+*)
+  ECHO_N='-n';;
+esac
+if expr a : '\(a\)' >/dev/null 2>&1 &&
+   test "X`expr 00001 : '.*\(...\)'`" = X001; then
+  as_expr=expr
+else
+  as_expr=false
+fi
+
+rm -f conf$$ conf$$.exe conf$$.file
+if test -d conf$$.dir; then
+  rm -f conf$$.dir/conf$$.file
+else
+  rm -f conf$$.dir
+  mkdir conf$$.dir 2>/dev/null
+fi
+if (echo >conf$$.file) 2>/dev/null; then
+  if ln -s conf$$.file conf$$ 2>/dev/null; then
+    as_ln_s='ln -s'
+    # ... but there are two gotchas:
+    # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail.
+    # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable.
+    # In both cases, we have to default to `cp -p'.
+    ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe ||
+      as_ln_s='cp -p'
+  elif ln conf$$.file conf$$ 2>/dev/null; then
+    as_ln_s=ln
+  else
+    as_ln_s='cp -p'
+  fi
+else
+  as_ln_s='cp -p'
+fi
+rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file
+rmdir conf$$.dir 2>/dev/null
+
+if mkdir -p . 2>/dev/null; then
+  as_mkdir_p=:
+else
+  test -d ./-p && rmdir ./-p
+  as_mkdir_p=false
+fi
+
+if test -x / >/dev/null 2>&1; then
+  as_test_x='test -x'
+else
+  if ls -dL / >/dev/null 2>&1; then
+    as_ls_L_option=L
+  else
+    as_ls_L_option=
+  fi
+  as_test_x='
+    eval sh -c '\''
+      if test -d "$1"; then
+       test -d "$1/.";
+      else
+       case $1 in
+       -*)set "./$1";;
+       esac;
+       case `ls -ld'$as_ls_L_option' "$1" 2>/dev/null` in
+       ???[sx]*):;;*)false;;esac;fi
+    '\'' sh
+  '
+fi
+as_executable_p=$as_test_x
+
+# Sed expression to map a string onto a valid CPP name.
+as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'"
+
+# Sed expression to map a string onto a valid variable name.
+as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'"
+
+
+
+exec 7<&0 </dev/null 6>&1
+
+# Name of the host.
+# hostname on some systems (SVR3.2, Linux) returns a bogus exit status,
+# so uname gets run too.
+ac_hostname=`(hostname || uname -n) 2>/dev/null | sed 1q`
+
+#
+# Initializations.
+#
+ac_default_prefix=/usr/local
+ac_clean_files=
+ac_config_libobj_dir=.
+LIBOBJS=
+cross_compiling=no
+subdirs=
+MFLAGS=
+MAKEFLAGS=
+SHELL=${CONFIG_SHELL-/bin/sh}
+
+# Identity of this package.
+PACKAGE_NAME=
+PACKAGE_TARNAME=
+PACKAGE_VERSION=
+PACKAGE_STRING=
+PACKAGE_BUGREPORT=
+
+ac_unique_file="Makefile.in"
+# Factoring default headers for most tests.
+ac_includes_default="\
+#include <stdio.h>
+#ifdef HAVE_SYS_TYPES_H
+# include <sys/types.h>
+#endif
+#ifdef HAVE_SYS_STAT_H
+# include <sys/stat.h>
+#endif
+#ifdef STDC_HEADERS
+# include <stdlib.h>
+# include <stddef.h>
+#else
+# ifdef HAVE_STDLIB_H
+#  include <stdlib.h>
+# endif
+#endif
+#ifdef HAVE_STRING_H
+# if !defined STDC_HEADERS && defined HAVE_MEMORY_H
+#  include <memory.h>
+# endif
+# include <string.h>
+#endif
+#ifdef HAVE_STRINGS_H
+# include <strings.h>
+#endif
+#ifdef HAVE_INTTYPES_H
+# include <inttypes.h>
+#endif
+#ifdef HAVE_STDINT_H
+# include <stdint.h>
+#endif
+#ifdef HAVE_UNISTD_H
+# include <unistd.h>
+#endif"
+
+ac_subst_vars='LTLIBOBJS
+LIBOBJS
+cgen_breaks
+REPORT_BUGS_TEXI
+REPORT_BUGS_TO
+PKGVERSION
+sim_profile
+sim_trace
+sim_stdio
+sim_debug
+sim_cflags
+sim_bswap
+MAINT
+EGREP
+GREP
+CPP
+CATOBJEXT
+GENCAT
+INSTOBJEXT
+DATADIRNAME
+CATALOGS
+POSUB
+GMSGFMT
+XGETTEXT
+INCINTL
+LIBINTL_DEP
+LIBINTL
+USE_NLS
+RANLIB
+AR
+HDEFINES
+CC_FOR_BUILD
+INSTALL_DATA
+INSTALL_SCRIPT
+INSTALL_PROGRAM
+OBJEXT
+EXEEXT
+ac_ct_CC
+CPPFLAGS
+LDFLAGS
+CFLAGS
+CC
+target_os
+target_vendor
+target_cpu
+target
+host_os
+host_vendor
+host_cpu
+host
+build_os
+build_vendor
+build_cpu
+build
+WERROR_CFLAGS
+WARN_CFLAGS
+sim_xor_endian
+sim_stdcall
+sim_smp
+sim_reserved_bits
+sim_regparm
+sim_packages
+sim_inline
+sim_hw
+sim_hw_objs
+sim_hw_cflags
+sim_default_model
+sim_scache
+sim_float
+sim_hostendian
+sim_endian
+sim_bitsize
+sim_assert
+sim_alignment
+sim_environment
+target_alias
+host_alias
+build_alias
+LIBS
+ECHO_T
+ECHO_N
+ECHO_C
+DEFS
+mandir
+localedir
+libdir
+psdir
+pdfdir
+dvidir
+htmldir
+infodir
+docdir
+oldincludedir
+includedir
+localstatedir
+sharedstatedir
+sysconfdir
+datadir
+datarootdir
+libexecdir
+sbindir
+bindir
+program_transform_name
+prefix
+exec_prefix
+PACKAGE_BUGREPORT
+PACKAGE_STRING
+PACKAGE_VERSION
+PACKAGE_TARNAME
+PACKAGE_NAME
+PATH_SEPARATOR
+SHELL'
+ac_subst_files=''
+ac_user_opts='
+enable_option_checking
+enable_maintainer_mode
+enable_sim_bswap
+enable_sim_cflags
+enable_sim_debug
+enable_sim_stdio
+enable_sim_trace
+enable_sim_profile
+with_pkgversion
+with_bugurl
+'
+      ac_precious_vars='build_alias
+host_alias
+target_alias
+CC
+CFLAGS
+LDFLAGS
+LIBS
+CPPFLAGS
+CPP'
+
+
+# Initialize some variables set by options.
+ac_init_help=
+ac_init_version=false
+ac_unrecognized_opts=
+ac_unrecognized_sep=
+# The variables have the same names as the options, with
+# dashes changed to underlines.
+cache_file=/dev/null
+exec_prefix=NONE
+no_create=
+no_recursion=
+prefix=NONE
+program_prefix=NONE
+program_suffix=NONE
+program_transform_name=s,x,x,
+silent=
+site=
+srcdir=
+verbose=
+x_includes=NONE
+x_libraries=NONE
+
+# Installation directory options.
+# These are left unexpanded so users can "make install exec_prefix=/foo"
+# and all the variables that are supposed to be based on exec_prefix
+# by default will actually change.
+# Use braces instead of parens because sh, perl, etc. also accept them.
+# (The list follows the same order as the GNU Coding Standards.)
+bindir='${exec_prefix}/bin'
+sbindir='${exec_prefix}/sbin'
+libexecdir='${exec_prefix}/libexec'
+datarootdir='${prefix}/share'
+datadir='${datarootdir}'
+sysconfdir='${prefix}/etc'
+sharedstatedir='${prefix}/com'
+localstatedir='${prefix}/var'
+includedir='${prefix}/include'
+oldincludedir='/usr/include'
+docdir='${datarootdir}/doc/${PACKAGE}'
+infodir='${datarootdir}/info'
+htmldir='${docdir}'
+dvidir='${docdir}'
+pdfdir='${docdir}'
+psdir='${docdir}'
+libdir='${exec_prefix}/lib'
+localedir='${datarootdir}/locale'
+mandir='${datarootdir}/man'
+
+ac_prev=
+ac_dashdash=
+for ac_option
+do
+  # If the previous option needs an argument, assign it.
+  if test -n "$ac_prev"; then
+    eval $ac_prev=\$ac_option
+    ac_prev=
+    continue
+  fi
+
+  case $ac_option in
+  *=*) ac_optarg=`expr "X$ac_option" : '[^=]*=\(.*\)'` ;;
+  *)   ac_optarg=yes ;;
+  esac
+
+  # Accept the important Cygnus configure options, so we can diagnose typos.
+
+  case $ac_dashdash$ac_option in
+  --)
+    ac_dashdash=yes ;;
+
+  -bindir | --bindir | --bindi | --bind | --bin | --bi)
+    ac_prev=bindir ;;
+  -bindir=* | --bindir=* | --bindi=* | --bind=* | --bin=* | --bi=*)
+    bindir=$ac_optarg ;;
+
+  -build | --build | --buil | --bui | --bu)
+    ac_prev=build_alias ;;
+  -build=* | --build=* | --buil=* | --bui=* | --bu=*)
+    build_alias=$ac_optarg ;;
+
+  -cache-file | --cache-file | --cache-fil | --cache-fi \
+  | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c)
+    ac_prev=cache_file ;;
+  -cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \
+  | --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* | --c=*)
+    cache_file=$ac_optarg ;;
+
+  --config-cache | -C)
+    cache_file=config.cache ;;
+
+  -datadir | --datadir | --datadi | --datad)
+    ac_prev=datadir ;;
+  -datadir=* | --datadir=* | --datadi=* | --datad=*)
+    datadir=$ac_optarg ;;
+
+  -datarootdir | --datarootdir | --datarootdi | --datarootd | --dataroot \
+  | --dataroo | --dataro | --datar)
+    ac_prev=datarootdir ;;
+  -datarootdir=* | --datarootdir=* | --datarootdi=* | --datarootd=* \
+  | --dataroot=* | --dataroo=* | --dataro=* | --datar=*)
+    datarootdir=$ac_optarg ;;
+
+  -disable-* | --disable-*)
+    ac_useropt=`expr "x$ac_option" : 'x-*disable-\(.*\)'`
+    # Reject names that are not valid shell variable names.
+    expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null &&
+      { $as_echo "$as_me: error: invalid feature name: $ac_useropt" >&2
+   { (exit 1); exit 1; }; }
+    ac_useropt_orig=$ac_useropt
+    ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'`
+    case $ac_user_opts in
+      *"
+"enable_$ac_useropt"
+"*) ;;
+      *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--disable-$ac_useropt_orig"
+        ac_unrecognized_sep=', ';;
+    esac
+    eval enable_$ac_useropt=no ;;
+
+  -docdir | --docdir | --docdi | --doc | --do)
+    ac_prev=docdir ;;
+  -docdir=* | --docdir=* | --docdi=* | --doc=* | --do=*)
+    docdir=$ac_optarg ;;
+
+  -dvidir | --dvidir | --dvidi | --dvid | --dvi | --dv)
+    ac_prev=dvidir ;;
+  -dvidir=* | --dvidir=* | --dvidi=* | --dvid=* | --dvi=* | --dv=*)
+    dvidir=$ac_optarg ;;
+
+  -enable-* | --enable-*)
+    ac_useropt=`expr "x$ac_option" : 'x-*enable-\([^=]*\)'`
+    # Reject names that are not valid shell variable names.
+    expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null &&
+      { $as_echo "$as_me: error: invalid feature name: $ac_useropt" >&2
+   { (exit 1); exit 1; }; }
+    ac_useropt_orig=$ac_useropt
+    ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'`
+    case $ac_user_opts in
+      *"
+"enable_$ac_useropt"
+"*) ;;
+      *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--enable-$ac_useropt_orig"
+        ac_unrecognized_sep=', ';;
+    esac
+    eval enable_$ac_useropt=\$ac_optarg ;;
+
+  -exec-prefix | --exec_prefix | --exec-prefix | --exec-prefi \
+  | --exec-pref | --exec-pre | --exec-pr | --exec-p | --exec- \
+  | --exec | --exe | --ex)
+    ac_prev=exec_prefix ;;
+  -exec-prefix=* | --exec_prefix=* | --exec-prefix=* | --exec-prefi=* \
+  | --exec-pref=* | --exec-pre=* | --exec-pr=* | --exec-p=* | --exec-=* \
+  | --exec=* | --exe=* | --ex=*)
+    exec_prefix=$ac_optarg ;;
+
+  -gas | --gas | --ga | --g)
+    # Obsolete; use --with-gas.
+    with_gas=yes ;;
+
+  -help | --help | --hel | --he | -h)
+    ac_init_help=long ;;
+  -help=r* | --help=r* | --hel=r* | --he=r* | -hr*)
+    ac_init_help=recursive ;;
+  -help=s* | --help=s* | --hel=s* | --he=s* | -hs*)
+    ac_init_help=short ;;
+
+  -host | --host | --hos | --ho)
+    ac_prev=host_alias ;;
+  -host=* | --host=* | --hos=* | --ho=*)
+    host_alias=$ac_optarg ;;
+
+  -htmldir | --htmldir | --htmldi | --htmld | --html | --htm | --ht)
+    ac_prev=htmldir ;;
+  -htmldir=* | --htmldir=* | --htmldi=* | --htmld=* | --html=* | --htm=* \
+  | --ht=*)
+    htmldir=$ac_optarg ;;
+
+  -includedir | --includedir | --includedi | --included | --include \
+  | --includ | --inclu | --incl | --inc)
+    ac_prev=includedir ;;
+  -includedir=* | --includedir=* | --includedi=* | --included=* | --include=* \
+  | --includ=* | --inclu=* | --incl=* | --inc=*)
+    includedir=$ac_optarg ;;
+
+  -infodir | --infodir | --infodi | --infod | --info | --inf)
+    ac_prev=infodir ;;
+  -infodir=* | --infodir=* | --infodi=* | --infod=* | --info=* | --inf=*)
+    infodir=$ac_optarg ;;
+
+  -libdir | --libdir | --libdi | --libd)
+    ac_prev=libdir ;;
+  -libdir=* | --libdir=* | --libdi=* | --libd=*)
+    libdir=$ac_optarg ;;
+
+  -libexecdir | --libexecdir | --libexecdi | --libexecd | --libexec \
+  | --libexe | --libex | --libe)
+    ac_prev=libexecdir ;;
+  -libexecdir=* | --libexecdir=* | --libexecdi=* | --libexecd=* | --libexec=* \
+  | --libexe=* | --libex=* | --libe=*)
+    libexecdir=$ac_optarg ;;
+
+  -localedir | --localedir | --localedi | --localed | --locale)
+    ac_prev=localedir ;;
+  -localedir=* | --localedir=* | --localedi=* | --localed=* | --locale=*)
+    localedir=$ac_optarg ;;
+
+  -localstatedir | --localstatedir | --localstatedi | --localstated \
+  | --localstate | --localstat | --localsta | --localst | --locals)
+    ac_prev=localstatedir ;;
+  -localstatedir=* | --localstatedir=* | --localstatedi=* | --localstated=* \
+  | --localstate=* | --localstat=* | --localsta=* | --localst=* | --locals=*)
+    localstatedir=$ac_optarg ;;
+
+  -mandir | --mandir | --mandi | --mand | --man | --ma | --m)
+    ac_prev=mandir ;;
+  -mandir=* | --mandir=* | --mandi=* | --mand=* | --man=* | --ma=* | --m=*)
+    mandir=$ac_optarg ;;
+
+  -nfp | --nfp | --nf)
+    # Obsolete; use --without-fp.
+    with_fp=no ;;
+
+  -no-create | --no-create | --no-creat | --no-crea | --no-cre \
+  | --no-cr | --no-c | -n)
+    no_create=yes ;;
+
+  -no-recursion | --no-recursion | --no-recursio | --no-recursi \
+  | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r)
+    no_recursion=yes ;;
+
+  -oldincludedir | --oldincludedir | --oldincludedi | --oldincluded \
+  | --oldinclude | --oldinclud | --oldinclu | --oldincl | --oldinc \
+  | --oldin | --oldi | --old | --ol | --o)
+    ac_prev=oldincludedir ;;
+  -oldincludedir=* | --oldincludedir=* | --oldincludedi=* | --oldincluded=* \
+  | --oldinclude=* | --oldinclud=* | --oldinclu=* | --oldincl=* | --oldinc=* \
+  | --oldin=* | --oldi=* | --old=* | --ol=* | --o=*)
+    oldincludedir=$ac_optarg ;;
+
+  -prefix | --prefix | --prefi | --pref | --pre | --pr | --p)
+    ac_prev=prefix ;;
+  -prefix=* | --prefix=* | --prefi=* | --pref=* | --pre=* | --pr=* | --p=*)
+    prefix=$ac_optarg ;;
+
+  -program-prefix | --program-prefix | --program-prefi | --program-pref \
+  | --program-pre | --program-pr | --program-p)
+    ac_prev=program_prefix ;;
+  -program-prefix=* | --program-prefix=* | --program-prefi=* \
+  | --program-pref=* | --program-pre=* | --program-pr=* | --program-p=*)
+    program_prefix=$ac_optarg ;;
+
+  -program-suffix | --program-suffix | --program-suffi | --program-suff \
+  | --program-suf | --program-su | --program-s)
+    ac_prev=program_suffix ;;
+  -program-suffix=* | --program-suffix=* | --program-suffi=* \
+  | --program-suff=* | --program-suf=* | --program-su=* | --program-s=*)
+    program_suffix=$ac_optarg ;;
+
+  -program-transform-name | --program-transform-name \
+  | --program-transform-nam | --program-transform-na \
+  | --program-transform-n | --program-transform- \
+  | --program-transform | --program-transfor \
+  | --program-transfo | --program-transf \
+  | --program-trans | --program-tran \
+  | --progr-tra | --program-tr | --program-t)
+    ac_prev=program_transform_name ;;
+  -program-transform-name=* | --program-transform-name=* \
+  | --program-transform-nam=* | --program-transform-na=* \
+  | --program-transform-n=* | --program-transform-=* \
+  | --program-transform=* | --program-transfor=* \
+  | --program-transfo=* | --program-transf=* \
+  | --program-trans=* | --program-tran=* \
+  | --progr-tra=* | --program-tr=* | --program-t=*)
+    program_transform_name=$ac_optarg ;;
+
+  -pdfdir | --pdfdir | --pdfdi | --pdfd | --pdf | --pd)
+    ac_prev=pdfdir ;;
+  -pdfdir=* | --pdfdir=* | --pdfdi=* | --pdfd=* | --pdf=* | --pd=*)
+    pdfdir=$ac_optarg ;;
+
+  -psdir | --psdir | --psdi | --psd | --ps)
+    ac_prev=psdir ;;
+  -psdir=* | --psdir=* | --psdi=* | --psd=* | --ps=*)
+    psdir=$ac_optarg ;;
+
+  -q | -quiet | --quiet | --quie | --qui | --qu | --q \
+  | -silent | --silent | --silen | --sile | --sil)
+    silent=yes ;;
+
+  -sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb)
+    ac_prev=sbindir ;;
+  -sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \
+  | --sbi=* | --sb=*)
+    sbindir=$ac_optarg ;;
+
+  -sharedstatedir | --sharedstatedir | --sharedstatedi \
+  | --sharedstated | --sharedstate | --sharedstat | --sharedsta \
+  | --sharedst | --shareds | --shared | --share | --shar \
+  | --sha | --sh)
+    ac_prev=sharedstatedir ;;
+  -sharedstatedir=* | --sharedstatedir=* | --sharedstatedi=* \
+  | --sharedstated=* | --sharedstate=* | --sharedstat=* | --sharedsta=* \
+  | --sharedst=* | --shareds=* | --shared=* | --share=* | --shar=* \
+  | --sha=* | --sh=*)
+    sharedstatedir=$ac_optarg ;;
+
+  -site | --site | --sit)
+    ac_prev=site ;;
+  -site=* | --site=* | --sit=*)
+    site=$ac_optarg ;;
+
+  -srcdir | --srcdir | --srcdi | --srcd | --src | --sr)
+    ac_prev=srcdir ;;
+  -srcdir=* | --srcdir=* | --srcdi=* | --srcd=* | --src=* | --sr=*)
+    srcdir=$ac_optarg ;;
+
+  -sysconfdir | --sysconfdir | --sysconfdi | --sysconfd | --sysconf \
+  | --syscon | --sysco | --sysc | --sys | --sy)
+    ac_prev=sysconfdir ;;
+  -sysconfdir=* | --sysconfdir=* | --sysconfdi=* | --sysconfd=* | --sysconf=* \
+  | --syscon=* | --sysco=* | --sysc=* | --sys=* | --sy=*)
+    sysconfdir=$ac_optarg ;;
+
+  -target | --target | --targe | --targ | --tar | --ta | --t)
+    ac_prev=target_alias ;;
+  -target=* | --target=* | --targe=* | --targ=* | --tar=* | --ta=* | --t=*)
+    target_alias=$ac_optarg ;;
+
+  -v | -verbose | --verbose | --verbos | --verbo | --verb)
+    verbose=yes ;;
+
+  -version | --version | --versio | --versi | --vers | -V)
+    ac_init_version=: ;;
+
+  -with-* | --with-*)
+    ac_useropt=`expr "x$ac_option" : 'x-*with-\([^=]*\)'`
+    # Reject names that are not valid shell variable names.
+    expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null &&
+      { $as_echo "$as_me: error: invalid package name: $ac_useropt" >&2
+   { (exit 1); exit 1; }; }
+    ac_useropt_orig=$ac_useropt
+    ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'`
+    case $ac_user_opts in
+      *"
+"with_$ac_useropt"
+"*) ;;
+      *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--with-$ac_useropt_orig"
+        ac_unrecognized_sep=', ';;
+    esac
+    eval with_$ac_useropt=\$ac_optarg ;;
+
+  -without-* | --without-*)
+    ac_useropt=`expr "x$ac_option" : 'x-*without-\(.*\)'`
+    # Reject names that are not valid shell variable names.
+    expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null &&
+      { $as_echo "$as_me: error: invalid package name: $ac_useropt" >&2
+   { (exit 1); exit 1; }; }
+    ac_useropt_orig=$ac_useropt
+    ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'`
+    case $ac_user_opts in
+      *"
+"with_$ac_useropt"
+"*) ;;
+      *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--without-$ac_useropt_orig"
+        ac_unrecognized_sep=', ';;
+    esac
+    eval with_$ac_useropt=no ;;
+
+  --x)
+    # Obsolete; use --with-x.
+    with_x=yes ;;
+
+  -x-includes | --x-includes | --x-include | --x-includ | --x-inclu \
+  | --x-incl | --x-inc | --x-in | --x-i)
+    ac_prev=x_includes ;;
+  -x-includes=* | --x-includes=* | --x-include=* | --x-includ=* | --x-inclu=* \
+  | --x-incl=* | --x-inc=* | --x-in=* | --x-i=*)
+    x_includes=$ac_optarg ;;
+
+  -x-libraries | --x-libraries | --x-librarie | --x-librari \
+  | --x-librar | --x-libra | --x-libr | --x-lib | --x-li | --x-l)
+    ac_prev=x_libraries ;;
+  -x-libraries=* | --x-libraries=* | --x-librarie=* | --x-librari=* \
+  | --x-librar=* | --x-libra=* | --x-libr=* | --x-lib=* | --x-li=* | --x-l=*)
+    x_libraries=$ac_optarg ;;
+
+  -*) { $as_echo "$as_me: error: unrecognized option: $ac_option
+Try \`$0 --help' for more information." >&2
+   { (exit 1); exit 1; }; }
+    ;;
+
+  *=*)
+    ac_envvar=`expr "x$ac_option" : 'x\([^=]*\)='`
+    # Reject names that are not valid shell variable names.
+    expr "x$ac_envvar" : ".*[^_$as_cr_alnum]" >/dev/null &&
+      { $as_echo "$as_me: error: invalid variable name: $ac_envvar" >&2
+   { (exit 1); exit 1; }; }
+    eval $ac_envvar=\$ac_optarg
+    export $ac_envvar ;;
+
+  *)
+    # FIXME: should be removed in autoconf 3.0.
+    $as_echo "$as_me: WARNING: you should use --build, --host, --target" >&2
+    expr "x$ac_option" : ".*[^-._$as_cr_alnum]" >/dev/null &&
+      $as_echo "$as_me: WARNING: invalid host type: $ac_option" >&2
+    : ${build_alias=$ac_option} ${host_alias=$ac_option} ${target_alias=$ac_option}
+    ;;
+
+  esac
+done
+
+if test -n "$ac_prev"; then
+  ac_option=--`echo $ac_prev | sed 's/_/-/g'`
+  { $as_echo "$as_me: error: missing argument to $ac_option" >&2
+   { (exit 1); exit 1; }; }
+fi
+
+if test -n "$ac_unrecognized_opts"; then
+  case $enable_option_checking in
+    no) ;;
+    fatal) { $as_echo "$as_me: error: unrecognized options: $ac_unrecognized_opts" >&2
+   { (exit 1); exit 1; }; } ;;
+    *)     $as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2 ;;
+  esac
+fi
+
+# Check all directory arguments for consistency.
+for ac_var in  exec_prefix prefix bindir sbindir libexecdir datarootdir \
+               datadir sysconfdir sharedstatedir localstatedir includedir \
+               oldincludedir docdir infodir htmldir dvidir pdfdir psdir \
+               libdir localedir mandir
+do
+  eval ac_val=\$$ac_var
+  # Remove trailing slashes.
+  case $ac_val in
+    */ )
+      ac_val=`expr "X$ac_val" : 'X\(.*[^/]\)' \| "X$ac_val" : 'X\(.*\)'`
+      eval $ac_var=\$ac_val;;
+  esac
+  # Be sure to have absolute directory names.
+  case $ac_val in
+    [\\/$]* | ?:[\\/]* )  continue;;
+    NONE | '' ) case $ac_var in *prefix ) continue;; esac;;
+  esac
+  { $as_echo "$as_me: error: expected an absolute directory name for --$ac_var: $ac_val" >&2
+   { (exit 1); exit 1; }; }
+done
+
+# There might be people who depend on the old broken behavior: `$host'
+# used to hold the argument of --host etc.
+# FIXME: To remove some day.
+build=$build_alias
+host=$host_alias
+target=$target_alias
+
+# FIXME: To remove some day.
+if test "x$host_alias" != x; then
+  if test "x$build_alias" = x; then
+    cross_compiling=maybe
+    $as_echo "$as_me: WARNING: If you wanted to set the --build type, don't use --host.
+    If a cross compiler is detected then cross compile mode will be used." >&2
+  elif test "x$build_alias" != "x$host_alias"; then
+    cross_compiling=yes
+  fi
+fi
+
+ac_tool_prefix=
+test -n "$host_alias" && ac_tool_prefix=$host_alias-
+
+test "$silent" = yes && exec 6>/dev/null
+
+
+ac_pwd=`pwd` && test -n "$ac_pwd" &&
+ac_ls_di=`ls -di .` &&
+ac_pwd_ls_di=`cd "$ac_pwd" && ls -di .` ||
+  { $as_echo "$as_me: error: working directory cannot be determined" >&2
+   { (exit 1); exit 1; }; }
+test "X$ac_ls_di" = "X$ac_pwd_ls_di" ||
+  { $as_echo "$as_me: error: pwd does not report name of working directory" >&2
+   { (exit 1); exit 1; }; }
+
+
+# Find the source files, if location was not specified.
+if test -z "$srcdir"; then
+  ac_srcdir_defaulted=yes
+  # Try the directory containing this script, then the parent directory.
+  ac_confdir=`$as_dirname -- "$as_myself" ||
+$as_expr X"$as_myself" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+        X"$as_myself" : 'X\(//\)[^/]' \| \
+        X"$as_myself" : 'X\(//\)$' \| \
+        X"$as_myself" : 'X\(/\)' \| . 2>/dev/null ||
+$as_echo X"$as_myself" |
+    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
+           s//\1/
+           q
+         }
+         /^X\(\/\/\)[^/].*/{
+           s//\1/
+           q
+         }
+         /^X\(\/\/\)$/{
+           s//\1/
+           q
+         }
+         /^X\(\/\).*/{
+           s//\1/
+           q
+         }
+         s/.*/./; q'`
+  srcdir=$ac_confdir
+  if test ! -r "$srcdir/$ac_unique_file"; then
+    srcdir=..
+  fi
+else
+  ac_srcdir_defaulted=no
+fi
+if test ! -r "$srcdir/$ac_unique_file"; then
+  test "$ac_srcdir_defaulted" = yes && srcdir="$ac_confdir or .."
+  { $as_echo "$as_me: error: cannot find sources ($ac_unique_file) in $srcdir" >&2
+   { (exit 1); exit 1; }; }
+fi
+ac_msg="sources are in $srcdir, but \`cd $srcdir' does not work"
+ac_abs_confdir=`(
+       cd "$srcdir" && test -r "./$ac_unique_file" || { $as_echo "$as_me: error: $ac_msg" >&2
+   { (exit 1); exit 1; }; }
+       pwd)`
+# When building in place, set srcdir=.
+if test "$ac_abs_confdir" = "$ac_pwd"; then
+  srcdir=.
+fi
+# Remove unnecessary trailing slashes from srcdir.
+# Double slashes in file names in object file debugging info
+# mess up M-x gdb in Emacs.
+case $srcdir in
+*/) srcdir=`expr "X$srcdir" : 'X\(.*[^/]\)' \| "X$srcdir" : 'X\(.*\)'`;;
+esac
+for ac_var in $ac_precious_vars; do
+  eval ac_env_${ac_var}_set=\${${ac_var}+set}
+  eval ac_env_${ac_var}_value=\$${ac_var}
+  eval ac_cv_env_${ac_var}_set=\${${ac_var}+set}
+  eval ac_cv_env_${ac_var}_value=\$${ac_var}
+done
+
+#
+# Report the --help message.
+#
+if test "$ac_init_help" = "long"; then
+  # Omit some internal or obsolete options to make the list less imposing.
+  # This message is too long to be a string in the A/UX 3.1 sh.
+  cat <<_ACEOF
+\`configure' configures this package to adapt to many kinds of systems.
+
+Usage: $0 [OPTION]... [VAR=VALUE]...
+
+To assign environment variables (e.g., CC, CFLAGS...), specify them as
+VAR=VALUE.  See below for descriptions of some of the useful variables.
+
+Defaults for the options are specified in brackets.
+
+Configuration:
+  -h, --help              display this help and exit
+      --help=short        display options specific to this package
+      --help=recursive    display the short help of all the included packages
+  -V, --version           display version information and exit
+  -q, --quiet, --silent   do not print \`checking...' messages
+      --cache-file=FILE   cache test results in FILE [disabled]
+  -C, --config-cache      alias for \`--cache-file=config.cache'
+  -n, --no-create         do not create output files
+      --srcdir=DIR        find the sources in DIR [configure dir or \`..']
+
+Installation directories:
+  --prefix=PREFIX         install architecture-independent files in PREFIX
+                          [$ac_default_prefix]
+  --exec-prefix=EPREFIX   install architecture-dependent files in EPREFIX
+                          [PREFIX]
+
+By default, \`make install' will install all the files in
+\`$ac_default_prefix/bin', \`$ac_default_prefix/lib' etc.  You can specify
+an installation prefix other than \`$ac_default_prefix' using \`--prefix',
+for instance \`--prefix=\$HOME'.
+
+For better control, use the options below.
+
+Fine tuning of the installation directories:
+  --bindir=DIR            user executables [EPREFIX/bin]
+  --sbindir=DIR           system admin executables [EPREFIX/sbin]
+  --libexecdir=DIR        program executables [EPREFIX/libexec]
+  --sysconfdir=DIR        read-only single-machine data [PREFIX/etc]
+  --sharedstatedir=DIR    modifiable architecture-independent data [PREFIX/com]
+  --localstatedir=DIR     modifiable single-machine data [PREFIX/var]
+  --libdir=DIR            object code libraries [EPREFIX/lib]
+  --includedir=DIR        C header files [PREFIX/include]
+  --oldincludedir=DIR     C header files for non-gcc [/usr/include]
+  --datarootdir=DIR       read-only arch.-independent data root [PREFIX/share]
+  --datadir=DIR           read-only architecture-independent data [DATAROOTDIR]
+  --infodir=DIR           info documentation [DATAROOTDIR/info]
+  --localedir=DIR         locale-dependent data [DATAROOTDIR/locale]
+  --mandir=DIR            man documentation [DATAROOTDIR/man]
+  --docdir=DIR            documentation root [DATAROOTDIR/doc/PACKAGE]
+  --htmldir=DIR           html documentation [DOCDIR]
+  --dvidir=DIR            dvi documentation [DOCDIR]
+  --pdfdir=DIR            pdf documentation [DOCDIR]
+  --psdir=DIR             ps documentation [DOCDIR]
+_ACEOF
+
+  cat <<\_ACEOF
+
+Program names:
+  --program-prefix=PREFIX            prepend PREFIX to installed program names
+  --program-suffix=SUFFIX            append SUFFIX to installed program names
+  --program-transform-name=PROGRAM   run sed PROGRAM on installed program names
+
+System types:
+  --build=BUILD     configure for building on BUILD [guessed]
+  --host=HOST       cross-compile to build programs to run on HOST [BUILD]
+  --target=TARGET   configure for building compilers for TARGET [HOST]
+_ACEOF
+fi
+
+if test -n "$ac_init_help"; then
+
+  cat <<\_ACEOF
+
+Optional Features:
+  --disable-option-checking  ignore unrecognized --enable/--with options
+  --disable-FEATURE       do not include FEATURE (same as --enable-FEATURE=no)
+  --enable-FEATURE[=ARG]  include FEATURE [ARG=yes]
+  --enable-maintainer-mode             Enable developer functionality.
+  --enable-sim-bswap                   Use Host specific BSWAP instruction.
+  --enable-sim-cflags=opts             Extra CFLAGS for use in building simulator
+  --enable-sim-debug=opts              Enable debugging flags
+  --enable-sim-stdio                   Specify whether to use stdio for console input/output.
+  --enable-sim-trace=opts              Enable tracing flags
+  --enable-sim-profile=opts            Enable profiling flags
+
+Optional Packages:
+  --with-PACKAGE[=ARG]    use PACKAGE [ARG=yes]
+  --without-PACKAGE       do not use PACKAGE (same as --with-PACKAGE=no)
+  --with-pkgversion=PKG   Use PKG in the version string in place of "GDB"
+  --with-bugurl=URL       Direct users to URL to report a bug
+
+Some influential environment variables:
+  CC          C compiler command
+  CFLAGS      C compiler flags
+  LDFLAGS     linker flags, e.g. -L<lib dir> if you have libraries in a
+              nonstandard directory <lib dir>
+  LIBS        libraries to pass to the linker, e.g. -l<library>
+  CPPFLAGS    C/C++/Objective C preprocessor flags, e.g. -I<include dir> if
+              you have headers in a nonstandard directory <include dir>
+  CPP         C preprocessor
+
+Use these variables to override the choices made by `configure' or to help
+it to find libraries and programs with nonstandard names/locations.
+
+_ACEOF
+ac_status=$?
+fi
+
+if test "$ac_init_help" = "recursive"; then
+  # If there are subdirs, report their specific --help.
+  for ac_dir in : $ac_subdirs_all; do test "x$ac_dir" = x: && continue
+    test -d "$ac_dir" ||
+      { cd "$srcdir" && ac_pwd=`pwd` && srcdir=. && test -d "$ac_dir"; } ||
+      continue
+    ac_builddir=.
+
+case "$ac_dir" in
+.) ac_dir_suffix= ac_top_builddir_sub=. ac_top_build_prefix= ;;
+*)
+  ac_dir_suffix=/`$as_echo "$ac_dir" | sed 's|^\.[\\/]||'`
+  # A ".." for each directory in $ac_dir_suffix.
+  ac_top_builddir_sub=`$as_echo "$ac_dir_suffix" | sed 's|/[^\\/]*|/..|g;s|/||'`
+  case $ac_top_builddir_sub in
+  "") ac_top_builddir_sub=. ac_top_build_prefix= ;;
+  *)  ac_top_build_prefix=$ac_top_builddir_sub/ ;;
+  esac ;;
+esac
+ac_abs_top_builddir=$ac_pwd
+ac_abs_builddir=$ac_pwd$ac_dir_suffix
+# for backward compatibility:
+ac_top_builddir=$ac_top_build_prefix
+
+case $srcdir in
+  .)  # We are building in place.
+    ac_srcdir=.
+    ac_top_srcdir=$ac_top_builddir_sub
+    ac_abs_top_srcdir=$ac_pwd ;;
+  [\\/]* | ?:[\\/]* )  # Absolute name.
+    ac_srcdir=$srcdir$ac_dir_suffix;
+    ac_top_srcdir=$srcdir
+    ac_abs_top_srcdir=$srcdir ;;
+  *) # Relative name.
+    ac_srcdir=$ac_top_build_prefix$srcdir$ac_dir_suffix
+    ac_top_srcdir=$ac_top_build_prefix$srcdir
+    ac_abs_top_srcdir=$ac_pwd/$srcdir ;;
+esac
+ac_abs_srcdir=$ac_abs_top_srcdir$ac_dir_suffix
+
+    cd "$ac_dir" || { ac_status=$?; continue; }
+    # Check for guested configure.
+    if test -f "$ac_srcdir/configure.gnu"; then
+      echo &&
+      $SHELL "$ac_srcdir/configure.gnu" --help=recursive
+    elif test -f "$ac_srcdir/configure"; then
+      echo &&
+      $SHELL "$ac_srcdir/configure" --help=recursive
+    else
+      $as_echo "$as_me: WARNING: no configuration information is in $ac_dir" >&2
+    fi || ac_status=$?
+    cd "$ac_pwd" || { ac_status=$?; break; }
+  done
+fi
+
+test -n "$ac_init_help" && exit $ac_status
+if $ac_init_version; then
+  cat <<\_ACEOF
+configure
+generated by GNU Autoconf 2.63
+
+Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001,
+2002, 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
+This configure script is free software; the Free Software Foundation
+gives unlimited permission to copy, distribute and modify it.
+_ACEOF
+  exit
+fi
+cat >config.log <<_ACEOF
+This file contains any messages produced by compilers while
+running configure, to aid debugging if configure makes a mistake.
+
+It was created by $as_me, which was
+generated by GNU Autoconf 2.63.  Invocation command line was
+
+  $ $0 $@
+
+_ACEOF
+exec 5>>config.log
+{
+cat <<_ASUNAME
+## --------- ##
+## Platform. ##
+## --------- ##
+
+hostname = `(hostname || uname -n) 2>/dev/null | sed 1q`
+uname -m = `(uname -m) 2>/dev/null || echo unknown`
+uname -r = `(uname -r) 2>/dev/null || echo unknown`
+uname -s = `(uname -s) 2>/dev/null || echo unknown`
+uname -v = `(uname -v) 2>/dev/null || echo unknown`
+
+/usr/bin/uname -p = `(/usr/bin/uname -p) 2>/dev/null || echo unknown`
+/bin/uname -X     = `(/bin/uname -X) 2>/dev/null     || echo unknown`
+
+/bin/arch              = `(/bin/arch) 2>/dev/null              || echo unknown`
+/usr/bin/arch -k       = `(/usr/bin/arch -k) 2>/dev/null       || echo unknown`
+/usr/convex/getsysinfo = `(/usr/convex/getsysinfo) 2>/dev/null || echo unknown`
+/usr/bin/hostinfo      = `(/usr/bin/hostinfo) 2>/dev/null      || echo unknown`
+/bin/machine           = `(/bin/machine) 2>/dev/null           || echo unknown`
+/usr/bin/oslevel       = `(/usr/bin/oslevel) 2>/dev/null       || echo unknown`
+/bin/universe          = `(/bin/universe) 2>/dev/null          || echo unknown`
+
+_ASUNAME
+
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  $as_echo "PATH: $as_dir"
+done
+IFS=$as_save_IFS
+
+} >&5
+
+cat >&5 <<_ACEOF
+
+
+## ----------- ##
+## Core tests. ##
+## ----------- ##
+
+_ACEOF
+
+
+# Keep a trace of the command line.
+# Strip out --no-create and --no-recursion so they do not pile up.
+# Strip out --silent because we don't want to record it for future runs.
+# Also quote any args containing shell meta-characters.
+# Make two passes to allow for proper duplicate-argument suppression.
+ac_configure_args=
+ac_configure_args0=
+ac_configure_args1=
+ac_must_keep_next=false
+for ac_pass in 1 2
+do
+  for ac_arg
+  do
+    case $ac_arg in
+    -no-create | --no-c* | -n | -no-recursion | --no-r*) continue ;;
+    -q | -quiet | --quiet | --quie | --qui | --qu | --q \
+    | -silent | --silent | --silen | --sile | --sil)
+      continue ;;
+    *\'*)
+      ac_arg=`$as_echo "$ac_arg" | sed "s/'/'\\\\\\\\''/g"` ;;
+    esac
+    case $ac_pass in
+    1) ac_configure_args0="$ac_configure_args0 '$ac_arg'" ;;
+    2)
+      ac_configure_args1="$ac_configure_args1 '$ac_arg'"
+      if test $ac_must_keep_next = true; then
+       ac_must_keep_next=false # Got value, back to normal.
+      else
+       case $ac_arg in
+         *=* | --config-cache | -C | -disable-* | --disable-* \
+         | -enable-* | --enable-* | -gas | --g* | -nfp | --nf* \
+         | -q | -quiet | --q* | -silent | --sil* | -v | -verb* \
+         | -with-* | --with-* | -without-* | --without-* | --x)
+           case "$ac_configure_args0 " in
+             "$ac_configure_args1"*" '$ac_arg' "* ) continue ;;
+           esac
+           ;;
+         -* ) ac_must_keep_next=true ;;
+       esac
+      fi
+      ac_configure_args="$ac_configure_args '$ac_arg'"
+      ;;
+    esac
+  done
+done
+$as_unset ac_configure_args0 || test "${ac_configure_args0+set}" != set || { ac_configure_args0=; export ac_configure_args0; }
+$as_unset ac_configure_args1 || test "${ac_configure_args1+set}" != set || { ac_configure_args1=; export ac_configure_args1; }
+
+# When interrupted or exit'd, cleanup temporary files, and complete
+# config.log.  We remove comments because anyway the quotes in there
+# would cause problems or look ugly.
+# WARNING: Use '\'' to represent an apostrophe within the trap.
+# WARNING: Do not start the trap code with a newline, due to a FreeBSD 4.0 bug.
+trap 'exit_status=$?
+  # Save into config.log some information that might help in debugging.
+  {
+    echo
+
+    cat <<\_ASBOX
+## ---------------- ##
+## Cache variables. ##
+## ---------------- ##
+_ASBOX
+    echo
+    # The following way of writing the cache mishandles newlines in values,
+(
+  for ac_var in `(set) 2>&1 | sed -n '\''s/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'\''`; do
+    eval ac_val=\$$ac_var
+    case $ac_val in #(
+    *${as_nl}*)
+      case $ac_var in #(
+      *_cv_*) { $as_echo "$as_me:$LINENO: WARNING: cache variable $ac_var contains a newline" >&5
+$as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;;
+      esac
+      case $ac_var in #(
+      _ | IFS | as_nl) ;; #(
+      BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #(
+      *) $as_unset $ac_var ;;
+      esac ;;
+    esac
+  done
+  (set) 2>&1 |
+    case $as_nl`(ac_space='\'' '\''; set) 2>&1` in #(
+    *${as_nl}ac_space=\ *)
+      sed -n \
+       "s/'\''/'\''\\\\'\'''\''/g;
+         s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\''\\2'\''/p"
+      ;; #(
+    *)
+      sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p"
+      ;;
+    esac |
+    sort
+)
+    echo
+
+    cat <<\_ASBOX
+## ----------------- ##
+## Output variables. ##
+## ----------------- ##
+_ASBOX
+    echo
+    for ac_var in $ac_subst_vars
+    do
+      eval ac_val=\$$ac_var
+      case $ac_val in
+      *\'\''*) ac_val=`$as_echo "$ac_val" | sed "s/'\''/'\''\\\\\\\\'\'''\''/g"`;;
+      esac
+      $as_echo "$ac_var='\''$ac_val'\''"
+    done | sort
+    echo
+
+    if test -n "$ac_subst_files"; then
+      cat <<\_ASBOX
+## ------------------- ##
+## File substitutions. ##
+## ------------------- ##
+_ASBOX
+      echo
+      for ac_var in $ac_subst_files
+      do
+       eval ac_val=\$$ac_var
+       case $ac_val in
+       *\'\''*) ac_val=`$as_echo "$ac_val" | sed "s/'\''/'\''\\\\\\\\'\'''\''/g"`;;
+       esac
+       $as_echo "$ac_var='\''$ac_val'\''"
+      done | sort
+      echo
+    fi
+
+    if test -s confdefs.h; then
+      cat <<\_ASBOX
+## ----------- ##
+## confdefs.h. ##
+## ----------- ##
+_ASBOX
+      echo
+      cat confdefs.h
+      echo
+    fi
+    test "$ac_signal" != 0 &&
+      $as_echo "$as_me: caught signal $ac_signal"
+    $as_echo "$as_me: exit $exit_status"
+  } >&5
+  rm -f core *.core core.conftest.* &&
+    rm -f -r conftest* confdefs* conf$$* $ac_clean_files &&
+    exit $exit_status
+' 0
+for ac_signal in 1 2 13 15; do
+  trap 'ac_signal='$ac_signal'; { (exit 1); exit 1; }' $ac_signal
+done
+ac_signal=0
+
+# confdefs.h avoids OS command line length limits that DEFS can exceed.
+rm -f -r conftest* confdefs.h
+
+# Predefined preprocessor variables.
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_NAME "$PACKAGE_NAME"
+_ACEOF
+
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_TARNAME "$PACKAGE_TARNAME"
+_ACEOF
+
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_VERSION "$PACKAGE_VERSION"
+_ACEOF
+
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_STRING "$PACKAGE_STRING"
+_ACEOF
+
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_BUGREPORT "$PACKAGE_BUGREPORT"
+_ACEOF
+
+
+# Let the site file select an alternate cache file if it wants to.
+# Prefer an explicitly selected file to automatically selected ones.
+ac_site_file1=NONE
+ac_site_file2=NONE
+if test -n "$CONFIG_SITE"; then
+  ac_site_file1=$CONFIG_SITE
+elif test "x$prefix" != xNONE; then
+  ac_site_file1=$prefix/share/config.site
+  ac_site_file2=$prefix/etc/config.site
+else
+  ac_site_file1=$ac_default_prefix/share/config.site
+  ac_site_file2=$ac_default_prefix/etc/config.site
+fi
+for ac_site_file in "$ac_site_file1" "$ac_site_file2"
+do
+  test "x$ac_site_file" = xNONE && continue
+  if test -r "$ac_site_file"; then
+    { $as_echo "$as_me:$LINENO: loading site script $ac_site_file" >&5
+$as_echo "$as_me: loading site script $ac_site_file" >&6;}
+    sed 's/^/| /' "$ac_site_file" >&5
+    . "$ac_site_file"
+  fi
+done
+
+if test -r "$cache_file"; then
+  # Some versions of bash will fail to source /dev/null (special
+  # files actually), so we avoid doing that.
+  if test -f "$cache_file"; then
+    { $as_echo "$as_me:$LINENO: loading cache $cache_file" >&5
+$as_echo "$as_me: loading cache $cache_file" >&6;}
+    case $cache_file in
+      [\\/]* | ?:[\\/]* ) . "$cache_file";;
+      *)                      . "./$cache_file";;
+    esac
+  fi
+else
+  { $as_echo "$as_me:$LINENO: creating cache $cache_file" >&5
+$as_echo "$as_me: creating cache $cache_file" >&6;}
+  >$cache_file
+fi
+
+# Check that the precious variables saved in the cache have kept the same
+# value.
+ac_cache_corrupted=false
+for ac_var in $ac_precious_vars; do
+  eval ac_old_set=\$ac_cv_env_${ac_var}_set
+  eval ac_new_set=\$ac_env_${ac_var}_set
+  eval ac_old_val=\$ac_cv_env_${ac_var}_value
+  eval ac_new_val=\$ac_env_${ac_var}_value
+  case $ac_old_set,$ac_new_set in
+    set,)
+      { $as_echo "$as_me:$LINENO: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&5
+$as_echo "$as_me: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&2;}
+      ac_cache_corrupted=: ;;
+    ,set)
+      { $as_echo "$as_me:$LINENO: error: \`$ac_var' was not set in the previous run" >&5
+$as_echo "$as_me: error: \`$ac_var' was not set in the previous run" >&2;}
+      ac_cache_corrupted=: ;;
+    ,);;
+    *)
+      if test "x$ac_old_val" != "x$ac_new_val"; then
+       # differences in whitespace do not lead to failure.
+       ac_old_val_w=`echo x $ac_old_val`
+       ac_new_val_w=`echo x $ac_new_val`
+       if test "$ac_old_val_w" != "$ac_new_val_w"; then
+         { $as_echo "$as_me:$LINENO: error: \`$ac_var' has changed since the previous run:" >&5
+$as_echo "$as_me: error: \`$ac_var' has changed since the previous run:" >&2;}
+         ac_cache_corrupted=:
+       else
+         { $as_echo "$as_me:$LINENO: warning: ignoring whitespace changes in \`$ac_var' since the previous run:" >&5
+$as_echo "$as_me: warning: ignoring whitespace changes in \`$ac_var' since the previous run:" >&2;}
+         eval $ac_var=\$ac_old_val
+       fi
+       { $as_echo "$as_me:$LINENO:   former value:  \`$ac_old_val'" >&5
+$as_echo "$as_me:   former value:  \`$ac_old_val'" >&2;}
+       { $as_echo "$as_me:$LINENO:   current value: \`$ac_new_val'" >&5
+$as_echo "$as_me:   current value: \`$ac_new_val'" >&2;}
+      fi;;
+  esac
+  # Pass precious variables to config.status.
+  if test "$ac_new_set" = set; then
+    case $ac_new_val in
+    *\'*) ac_arg=$ac_var=`$as_echo "$ac_new_val" | sed "s/'/'\\\\\\\\''/g"` ;;
+    *) ac_arg=$ac_var=$ac_new_val ;;
+    esac
+    case " $ac_configure_args " in
+      *" '$ac_arg' "*) ;; # Avoid dups.  Use of quotes ensures accuracy.
+      *) ac_configure_args="$ac_configure_args '$ac_arg'" ;;
+    esac
+  fi
+done
+if $ac_cache_corrupted; then
+  { $as_echo "$as_me:$LINENO: error: in \`$ac_pwd':" >&5
+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
+  { $as_echo "$as_me:$LINENO: error: changes in the environment can compromise the build" >&5
+$as_echo "$as_me: error: changes in the environment can compromise the build" >&2;}
+  { { $as_echo "$as_me:$LINENO: error: run \`make distclean' and/or \`rm $cache_file' and start over" >&5
+$as_echo "$as_me: error: run \`make distclean' and/or \`rm $cache_file' and start over" >&2;}
+   { (exit 1); exit 1; }; }
+fi
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+
+
+ac_config_headers="$ac_config_headers config.h:config.in"
+
+
+# This file contains common code used by all simulators.
+#
+# SIM_AC_COMMON invokes AC macros used by all simulators and by the common
+# directory.  It is intended to be invoked before any target specific stuff.
+# SIM_AC_OUTPUT is a cover function to AC_OUTPUT to generate the Makefile.
+# It is intended to be invoked last.
+#
+# The simulator's configure.in should look like:
+#
+# dnl Process this file with autoconf to produce a configure script.
+# sinclude(../common/aclocal.m4)
+# AC_PREREQ(2.5)dnl
+# AC_INIT(Makefile.in)
+#
+# SIM_AC_COMMON
+#
+# ... target specific stuff ...
+#
+# SIM_AC_OUTPUT
+
+# Include global overrides and fixes for Autoconf.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+sim_inline="-DDEFAULT_INLINE=0"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+# intl sister-directory configuration rules.
+#
+
+# The idea behind this macro is that there's no need to repeat all the
+# autoconf probes done by the intl directory - it's already done them
+# for us.  In fact, there's no need even to look at the cache for the
+# answers.  All we need to do is nab a few pieces of information.
+# The intl directory is set up to make this easy, by generating a
+# small file which can be sourced as a shell script; then we produce
+# the necessary substitutions and definitions for this directory.
+
+
+
+# Autoconf M4 include file defining utility macros for complex Canadian
+# cross builds.
+
+
+
+
+
+
+
+
+
+####
+# _NCN_TOOL_PREFIXES:  Some stuff that oughtta be done in AC_CANONICAL_SYSTEM
+# or AC_INIT.
+# These demand that AC_CANONICAL_SYSTEM be called beforehand.
+
+####
+# NCN_STRICT_CHECK_TOOLS(variable, progs-to-check-for,[value-if-not-found],[path])
+# Like plain AC_CHECK_TOOLS, but require prefix if build!=host.
+
+
+####
+# NCN_STRICT_CHECK_TARGET_TOOLS(variable, progs-to-check-for,[value-if-not-found],[path])
+# Like CVS Autoconf AC_CHECK_TARGET_TOOLS, but require prefix if build!=target.
+
+
+
+# Backported from Autoconf 2.5x; can go away when and if
+# we switch.  Put the OS path separator in $PATH_SEPARATOR.
+
+
+
+
+# ACX_HAVE_GCC_FOR_TARGET
+# Check if the variable GCC_FOR_TARGET really points to a GCC binary.
+
+
+# ACX_CHECK_INSTALLED_TARGET_TOOL(VAR, PROG)
+# Searching for installed target binutils.  We need to take extra care,
+# else we may find the wrong assembler, linker, etc., and lose.
+#
+# First try --with-build-time-tools, if specified.
+#
+# For build != host, we ask the installed GCC for the name of the tool it
+# uses, and accept it if it is an absolute path.  This is because the
+# only good choice for a compiler is the same GCC version that is being
+# installed (or we couldn't make target libraries), and we assume that
+# on the host system we'll have not only the same GCC version, but also
+# the same binutils version.
+#
+# For build == host, search the same directories that the installed
+# compiler will search.  We used to do this for the assembler, linker,
+# and nm only; for simplicity of configuration, however, we extend this
+# criterion to tools (such as ar and ranlib) that are never invoked by
+# the compiler, to avoid mismatches.
+#
+# Also note we have to check MD_EXEC_PREFIX before checking the user's path
+# if build == target.  This makes the most sense only when bootstrapping,
+# but we also do so when build != host.  In this case, we hope that the
+# build and host systems will have similar contents of MD_EXEC_PREFIX.
+#
+# If we do not find a suitable binary, then try the user's path.
+
+
+###
+# AC_PROG_CPP_WERROR
+# Used for autoconf 2.5x to force AC_PREPROC_IFELSE to reject code which
+# triggers warnings from the preprocessor.  Will be in autoconf 2.58.
+# For now, using this also overrides header checks to use only the
+# preprocessor (matches 2.13 behavior; matching 2.58's behavior is a
+# bit harder from here).
+# Eventually autoconf will default to checking headers with the compiler
+# instead, and we'll have to do this differently.
+
+# AC_PROG_CPP_WERROR
+
+# Test for GNAT.
+# We require the gnatbind program, and a compiler driver that
+# understands Ada.  We use the user's CC setting, already found,
+# and possibly add $1 to the command-line parameters.
+#
+# Sets the shell variable have_gnat to yes or no as appropriate, and
+# substitutes GNATBIND and GNATMAKE.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+# Bugs in autoconf 2.59 break the call to SIM_AC_COMMON, hack around
+# it by inlining the macro's contents.
+# This file contains common code used by all simulators.
+#
+# common.m4 invokes AC macros used by all simulators and by the common
+# directory.  It is intended to be included before any target specific
+# stuff.  SIM_AC_OUTPUT is a cover function to AC_OUTPUT to generate
+# the Makefile.  It is intended to be invoked last.
+#
+# The simulator's configure.in should look like:
+#
+# dnl Process this file with autoconf to produce a configure script.
+# AC_PREREQ(2.5)dnl
+# AC_INIT(Makefile.in)
+# AC_CONFIG_HEADER(config.h:config.in)
+#
+# sinclude(../common/aclocal.m4)
+# sinclude(../common/common.m4)
+#
+# ... target specific stuff ...
+
+ac_aux_dir=
+for ac_dir in "$srcdir" "$srcdir/.." "$srcdir/../.."; do
+  if test -f "$ac_dir/install-sh"; then
+    ac_aux_dir=$ac_dir
+    ac_install_sh="$ac_aux_dir/install-sh -c"
+    break
+  elif test -f "$ac_dir/install.sh"; then
+    ac_aux_dir=$ac_dir
+    ac_install_sh="$ac_aux_dir/install.sh -c"
+    break
+  elif test -f "$ac_dir/shtool"; then
+    ac_aux_dir=$ac_dir
+    ac_install_sh="$ac_aux_dir/shtool install -c"
+    break
+  fi
+done
+if test -z "$ac_aux_dir"; then
+  { { $as_echo "$as_me:$LINENO: error: cannot find install-sh or install.sh in \"$srcdir\" \"$srcdir/..\" \"$srcdir/../..\"" >&5
+$as_echo "$as_me: error: cannot find install-sh or install.sh in \"$srcdir\" \"$srcdir/..\" \"$srcdir/../..\"" >&2;}
+   { (exit 1); exit 1; }; }
+fi
+
+# These three variables are undocumented and unsupported,
+# and are intended to be withdrawn in a future Autoconf release.
+# They can cause serious problems if a builder's source tree is in a directory
+# whose full name contains unusual characters.
+ac_config_guess="$SHELL $ac_aux_dir/config.guess"  # Please don't use this var.
+ac_config_sub="$SHELL $ac_aux_dir/config.sub"  # Please don't use this var.
+ac_configure="$SHELL $ac_aux_dir/configure"  # Please don't use this var.
+
+
+# Make sure we can run config.sub.
+$SHELL "$ac_aux_dir/config.sub" sun4 >/dev/null 2>&1 ||
+  { { $as_echo "$as_me:$LINENO: error: cannot run $SHELL $ac_aux_dir/config.sub" >&5
+$as_echo "$as_me: error: cannot run $SHELL $ac_aux_dir/config.sub" >&2;}
+   { (exit 1); exit 1; }; }
+
+{ $as_echo "$as_me:$LINENO: checking build system type" >&5
+$as_echo_n "checking build system type... " >&6; }
+if test "${ac_cv_build+set}" = set; then
+  $as_echo_n "(cached) " >&6
+else
+  ac_build_alias=$build_alias
+test "x$ac_build_alias" = x &&
+  ac_build_alias=`$SHELL "$ac_aux_dir/config.guess"`
+test "x$ac_build_alias" = x &&
+  { { $as_echo "$as_me:$LINENO: error: cannot guess build type; you must specify one" >&5
+$as_echo "$as_me: error: cannot guess build type; you must specify one" >&2;}
+   { (exit 1); exit 1; }; }
+ac_cv_build=`$SHELL "$ac_aux_dir/config.sub" $ac_build_alias` ||
+  { { $as_echo "$as_me:$LINENO: error: $SHELL $ac_aux_dir/config.sub $ac_build_alias failed" >&5
+$as_echo "$as_me: error: $SHELL $ac_aux_dir/config.sub $ac_build_alias failed" >&2;}
+   { (exit 1); exit 1; }; }
+
+fi
+{ $as_echo "$as_me:$LINENO: result: $ac_cv_build" >&5
+$as_echo "$ac_cv_build" >&6; }
+case $ac_cv_build in
+*-*-*) ;;
+*) { { $as_echo "$as_me:$LINENO: error: invalid value of canonical build" >&5
+$as_echo "$as_me: error: invalid value of canonical build" >&2;}
+   { (exit 1); exit 1; }; };;
+esac
+build=$ac_cv_build
+ac_save_IFS=$IFS; IFS='-'
+set x $ac_cv_build
+shift
+build_cpu=$1
+build_vendor=$2
+shift; shift
+# Remember, the first character of IFS is used to create $*,
+# except with old shells:
+build_os=$*
+IFS=$ac_save_IFS
+case $build_os in *\ *) build_os=`echo "$build_os" | sed 's/ /-/g'`;; esac
+
+
+{ $as_echo "$as_me:$LINENO: checking host system type" >&5
+$as_echo_n "checking host system type... " >&6; }
+if test "${ac_cv_host+set}" = set; then
+  $as_echo_n "(cached) " >&6
+else
+  if test "x$host_alias" = x; then
+  ac_cv_host=$ac_cv_build
+else
+  ac_cv_host=`$SHELL "$ac_aux_dir/config.sub" $host_alias` ||
+    { { $as_echo "$as_me:$LINENO: error: $SHELL $ac_aux_dir/config.sub $host_alias failed" >&5
+$as_echo "$as_me: error: $SHELL $ac_aux_dir/config.sub $host_alias failed" >&2;}
+   { (exit 1); exit 1; }; }
+fi
+
+fi
+{ $as_echo "$as_me:$LINENO: result: $ac_cv_host" >&5
+$as_echo "$ac_cv_host" >&6; }
+case $ac_cv_host in
+*-*-*) ;;
+*) { { $as_echo "$as_me:$LINENO: error: invalid value of canonical host" >&5
+$as_echo "$as_me: error: invalid value of canonical host" >&2;}
+   { (exit 1); exit 1; }; };;
+esac
+host=$ac_cv_host
+ac_save_IFS=$IFS; IFS='-'
+set x $ac_cv_host
+shift
+host_cpu=$1
+host_vendor=$2
+shift; shift
+# Remember, the first character of IFS is used to create $*,
+# except with old shells:
+host_os=$*
+IFS=$ac_save_IFS
+case $host_os in *\ *) host_os=`echo "$host_os" | sed 's/ /-/g'`;; esac
+
+
+{ $as_echo "$as_me:$LINENO: checking target system type" >&5
+$as_echo_n "checking target system type... " >&6; }
+if test "${ac_cv_target+set}" = set; then
+  $as_echo_n "(cached) " >&6
+else
+  if test "x$target_alias" = x; then
+  ac_cv_target=$ac_cv_host
+else
+  ac_cv_target=`$SHELL "$ac_aux_dir/config.sub" $target_alias` ||
+    { { $as_echo "$as_me:$LINENO: error: $SHELL $ac_aux_dir/config.sub $target_alias failed" >&5
+$as_echo "$as_me: error: $SHELL $ac_aux_dir/config.sub $target_alias failed" >&2;}
+   { (exit 1); exit 1; }; }
+fi
+
+fi
+{ $as_echo "$as_me:$LINENO: result: $ac_cv_target" >&5
+$as_echo "$ac_cv_target" >&6; }
+case $ac_cv_target in
+*-*-*) ;;
+*) { { $as_echo "$as_me:$LINENO: error: invalid value of canonical target" >&5
+$as_echo "$as_me: error: invalid value of canonical target" >&2;}
+   { (exit 1); exit 1; }; };;
+esac
+target=$ac_cv_target
+ac_save_IFS=$IFS; IFS='-'
+set x $ac_cv_target
+shift
+target_cpu=$1
+target_vendor=$2
+shift; shift
+# Remember, the first character of IFS is used to create $*,
+# except with old shells:
+target_os=$*
+IFS=$ac_save_IFS
+case $target_os in *\ *) target_os=`echo "$target_os" | sed 's/ /-/g'`;; esac
+
+
+# The aliases save the names the user supplied, while $host etc.
+# will get canonicalized.
+test -n "$target_alias" &&
+  test "$program_prefix$program_suffix$program_transform_name" = \
+    NONENONEs,x,x, &&
+  program_prefix=${target_alias}-
+test "$program_prefix" != NONE &&
+  program_transform_name="s&^&$program_prefix&;$program_transform_name"
+# Use a double $ so make ignores it.
+test "$program_suffix" != NONE &&
+  program_transform_name="s&\$&$program_suffix&;$program_transform_name"
+# Double any \ or $.
+# By default was `s,x,x', remove it if useless.
+ac_script='s/[\\$]/&&/g;s/;s,x,x,$//'
+program_transform_name=`$as_echo "$program_transform_name" | sed "$ac_script"`
+
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+if test -n "$ac_tool_prefix"; then
+  # Extract the first word of "${ac_tool_prefix}gcc", so it can be a program name with args.
+set dummy ${ac_tool_prefix}gcc; ac_word=$2
+{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if test "${ac_cv_prog_CC+set}" = set; then
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$CC"; then
+  ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  for ac_exec_ext in '' $ac_executable_extensions; do
+  if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then
+    ac_cv_prog_CC="${ac_tool_prefix}gcc"
+    $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+done
+IFS=$as_save_IFS
+
+fi
+fi
+CC=$ac_cv_prog_CC
+if test -n "$CC"; then
+  { $as_echo "$as_me:$LINENO: result: $CC" >&5
+$as_echo "$CC" >&6; }
+else
+  { $as_echo "$as_me:$LINENO: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+
+fi
+if test -z "$ac_cv_prog_CC"; then
+  ac_ct_CC=$CC
+  # Extract the first word of "gcc", so it can be a program name with args.
+set dummy gcc; ac_word=$2
+{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if test "${ac_cv_prog_ac_ct_CC+set}" = set; then
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$ac_ct_CC"; then
+  ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  for ac_exec_ext in '' $ac_executable_extensions; do
+  if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then
+    ac_cv_prog_ac_ct_CC="gcc"
+    $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+done
+IFS=$as_save_IFS
+
+fi
+fi
+ac_ct_CC=$ac_cv_prog_ac_ct_CC
+if test -n "$ac_ct_CC"; then
+  { $as_echo "$as_me:$LINENO: result: $ac_ct_CC" >&5
+$as_echo "$ac_ct_CC" >&6; }
+else
+  { $as_echo "$as_me:$LINENO: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+  if test "x$ac_ct_CC" = x; then
+    CC=""
+  else
+    case $cross_compiling:$ac_tool_warned in
+yes:)
+{ $as_echo "$as_me:$LINENO: WARNING: using cross tools not prefixed with host triplet" >&5
+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;}
+ac_tool_warned=yes ;;
+esac
+    CC=$ac_ct_CC
+  fi
+else
+  CC="$ac_cv_prog_CC"
+fi
+
+if test -z "$CC"; then
+          if test -n "$ac_tool_prefix"; then
+    # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args.
+set dummy ${ac_tool_prefix}cc; ac_word=$2
+{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if test "${ac_cv_prog_CC+set}" = set; then
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$CC"; then
+  ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  for ac_exec_ext in '' $ac_executable_extensions; do
+  if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then
+    ac_cv_prog_CC="${ac_tool_prefix}cc"
+    $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+done
+IFS=$as_save_IFS
+
+fi
+fi
+CC=$ac_cv_prog_CC
+if test -n "$CC"; then
+  { $as_echo "$as_me:$LINENO: result: $CC" >&5
+$as_echo "$CC" >&6; }
+else
+  { $as_echo "$as_me:$LINENO: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+
+  fi
+fi
+if test -z "$CC"; then
+  # Extract the first word of "cc", so it can be a program name with args.
+set dummy cc; ac_word=$2
+{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if test "${ac_cv_prog_CC+set}" = set; then
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$CC"; then
+  ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+  ac_prog_rejected=no
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  for ac_exec_ext in '' $ac_executable_extensions; do
+  if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then
+    if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then
+       ac_prog_rejected=yes
+       continue
+     fi
+    ac_cv_prog_CC="cc"
+    $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+done
+IFS=$as_save_IFS
+
+if test $ac_prog_rejected = yes; then
+  # We found a bogon in the path, so make sure we never use it.
+  set dummy $ac_cv_prog_CC
+  shift
+  if test $# != 0; then
+    # We chose a different compiler from the bogus one.
+    # However, it has the same basename, so the bogon will be chosen
+    # first if we set CC to just the basename; use the full file name.
+    shift
+    ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@"
+  fi
+fi
+fi
+fi
+CC=$ac_cv_prog_CC
+if test -n "$CC"; then
+  { $as_echo "$as_me:$LINENO: result: $CC" >&5
+$as_echo "$CC" >&6; }
+else
+  { $as_echo "$as_me:$LINENO: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+
+fi
+if test -z "$CC"; then
+  if test -n "$ac_tool_prefix"; then
+  for ac_prog in cl.exe
+  do
+    # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args.
+set dummy $ac_tool_prefix$ac_prog; ac_word=$2
+{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if test "${ac_cv_prog_CC+set}" = set; then
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$CC"; then
+  ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  for ac_exec_ext in '' $ac_executable_extensions; do
+  if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then
+    ac_cv_prog_CC="$ac_tool_prefix$ac_prog"
+    $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+done
+IFS=$as_save_IFS
+
+fi
+fi
+CC=$ac_cv_prog_CC
+if test -n "$CC"; then
+  { $as_echo "$as_me:$LINENO: result: $CC" >&5
+$as_echo "$CC" >&6; }
+else
+  { $as_echo "$as_me:$LINENO: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+
+    test -n "$CC" && break
+  done
+fi
+if test -z "$CC"; then
+  ac_ct_CC=$CC
+  for ac_prog in cl.exe
+do
+  # Extract the first word of "$ac_prog", so it can be a program name with args.
+set dummy $ac_prog; ac_word=$2
+{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if test "${ac_cv_prog_ac_ct_CC+set}" = set; then
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$ac_ct_CC"; then
+  ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  for ac_exec_ext in '' $ac_executable_extensions; do
+  if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then
+    ac_cv_prog_ac_ct_CC="$ac_prog"
+    $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+done
+IFS=$as_save_IFS
+
+fi
+fi
+ac_ct_CC=$ac_cv_prog_ac_ct_CC
+if test -n "$ac_ct_CC"; then
+  { $as_echo "$as_me:$LINENO: result: $ac_ct_CC" >&5
+$as_echo "$ac_ct_CC" >&6; }
+else
+  { $as_echo "$as_me:$LINENO: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+
+  test -n "$ac_ct_CC" && break
+done
+
+  if test "x$ac_ct_CC" = x; then
+    CC=""
+  else
+    case $cross_compiling:$ac_tool_warned in
+yes:)
+{ $as_echo "$as_me:$LINENO: WARNING: using cross tools not prefixed with host triplet" >&5
+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;}
+ac_tool_warned=yes ;;
+esac
+    CC=$ac_ct_CC
+  fi
+fi
+
+fi
+
+
+test -z "$CC" && { { $as_echo "$as_me:$LINENO: error: in \`$ac_pwd':" >&5
+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
+{ { $as_echo "$as_me:$LINENO: error: no acceptable C compiler found in \$PATH
+See \`config.log' for more details." >&5
+$as_echo "$as_me: error: no acceptable C compiler found in \$PATH
+See \`config.log' for more details." >&2;}
+   { (exit 1); exit 1; }; }; }
+
+# Provide some information about the compiler.
+$as_echo "$as_me:$LINENO: checking for C compiler version" >&5
+set X $ac_compile
+ac_compiler=$2
+{ (ac_try="$ac_compiler --version >&5"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_compiler --version >&5") 2>&5
+  ac_status=$?
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }
+{ (ac_try="$ac_compiler -v >&5"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_compiler -v >&5") 2>&5
+  ac_status=$?
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }
+{ (ac_try="$ac_compiler -V >&5"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_compiler -V >&5") 2>&5
+  ac_status=$?
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }
+
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+
+int
+main ()
+{
+
+  ;
+  return 0;
+}
+_ACEOF
+ac_clean_files_save=$ac_clean_files
+ac_clean_files="$ac_clean_files a.out a.out.dSYM a.exe b.out"
+# Try to create an executable without -o first, disregard a.out.
+# It will help us diagnose broken compilers, and finding out an intuition
+# of exeext.
+{ $as_echo "$as_me:$LINENO: checking for C compiler default output file name" >&5
+$as_echo_n "checking for C compiler default output file name... " >&6; }
+ac_link_default=`$as_echo "$ac_link" | sed 's/ -o *conftest[^ ]*//'`
+
+# The possible output files:
+ac_files="a.out conftest.exe conftest a.exe a_out.exe b.out conftest.*"
+
+ac_rmfiles=
+for ac_file in $ac_files
+do
+  case $ac_file in
+    *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;;
+    * ) ac_rmfiles="$ac_rmfiles $ac_file";;
+  esac
+done
+rm -f $ac_rmfiles
+
+if { (ac_try="$ac_link_default"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_link_default") 2>&5
+  ac_status=$?
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; then
+  # Autoconf-2.13 could set the ac_cv_exeext variable to `no'.
+# So ignore a value of `no', otherwise this would lead to `EXEEXT = no'
+# in a Makefile.  We should not override ac_cv_exeext if it was cached,
+# so that the user can short-circuit this test for compilers unknown to
+# Autoconf.
+for ac_file in $ac_files ''
+do
+  test -f "$ac_file" || continue
+  case $ac_file in
+    *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj )
+       ;;
+    [ab].out )
+       # We found the default executable, but exeext='' is most
+       # certainly right.
+       break;;
+    *.* )
+        if test "${ac_cv_exeext+set}" = set && test "$ac_cv_exeext" != no;
+       then :; else
+          ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'`
+       fi
+       # We set ac_cv_exeext here because the later test for it is not
+       # safe: cross compilers may not add the suffix if given an `-o'
+       # argument, so we may need to know it at that point already.
+       # Even if this section looks crufty: it has the advantage of
+       # actually working.
+       break;;
+    * )
+       break;;
+  esac
+done
+test "$ac_cv_exeext" = no && ac_cv_exeext=
+
+else
+  ac_file=''
+fi
+
+{ $as_echo "$as_me:$LINENO: result: $ac_file" >&5
+$as_echo "$ac_file" >&6; }
+if test -z "$ac_file"; then
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+{ { $as_echo "$as_me:$LINENO: error: in \`$ac_pwd':" >&5
+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
+{ { $as_echo "$as_me:$LINENO: error: C compiler cannot create executables
+See \`config.log' for more details." >&5
+$as_echo "$as_me: error: C compiler cannot create executables
+See \`config.log' for more details." >&2;}
+   { (exit 77); exit 77; }; }; }
+fi
+
+ac_exeext=$ac_cv_exeext
+
+# Check that the compiler produces executables we can run.  If not, either
+# the compiler is broken, or we cross compile.
+{ $as_echo "$as_me:$LINENO: checking whether the C compiler works" >&5
+$as_echo_n "checking whether the C compiler works... " >&6; }
+# FIXME: These cross compiler hacks should be removed for Autoconf 3.0
+# If not cross compiling, check that we can run a simple program.
+if test "$cross_compiling" != yes; then
+  if { ac_try='./$ac_file'
+  { (case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_try") 2>&5
+  ac_status=$?
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+    cross_compiling=no
+  else
+    if test "$cross_compiling" = maybe; then
+       cross_compiling=yes
+    else
+       { { $as_echo "$as_me:$LINENO: error: in \`$ac_pwd':" >&5
+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
+{ { $as_echo "$as_me:$LINENO: error: cannot run C compiled programs.
+If you meant to cross compile, use \`--host'.
+See \`config.log' for more details." >&5
+$as_echo "$as_me: error: cannot run C compiled programs.
+If you meant to cross compile, use \`--host'.
+See \`config.log' for more details." >&2;}
+   { (exit 1); exit 1; }; }; }
+    fi
+  fi
+fi
+{ $as_echo "$as_me:$LINENO: result: yes" >&5
+$as_echo "yes" >&6; }
+
+rm -f -r a.out a.out.dSYM a.exe conftest$ac_cv_exeext b.out
+ac_clean_files=$ac_clean_files_save
+# Check that the compiler produces executables we can run.  If not, either
+# the compiler is broken, or we cross compile.
+{ $as_echo "$as_me:$LINENO: checking whether we are cross compiling" >&5
+$as_echo_n "checking whether we are cross compiling... " >&6; }
+{ $as_echo "$as_me:$LINENO: result: $cross_compiling" >&5
+$as_echo "$cross_compiling" >&6; }
+
+{ $as_echo "$as_me:$LINENO: checking for suffix of executables" >&5
+$as_echo_n "checking for suffix of executables... " >&6; }
+if { (ac_try="$ac_link"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_link") 2>&5
+  ac_status=$?
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; then
+  # If both `conftest.exe' and `conftest' are `present' (well, observable)
+# catch `conftest.exe'.  For instance with Cygwin, `ls conftest' will
+# work properly (i.e., refer to `conftest.exe'), while it won't with
+# `rm'.
+for ac_file in conftest.exe conftest conftest.*; do
+  test -f "$ac_file" || continue
+  case $ac_file in
+    *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;;
+    *.* ) ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'`
+         break;;
+    * ) break;;
+  esac
+done
+else
+  { { $as_echo "$as_me:$LINENO: error: in \`$ac_pwd':" >&5
+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
+{ { $as_echo "$as_me:$LINENO: error: cannot compute suffix of executables: cannot compile and link
+See \`config.log' for more details." >&5
+$as_echo "$as_me: error: cannot compute suffix of executables: cannot compile and link
+See \`config.log' for more details." >&2;}
+   { (exit 1); exit 1; }; }; }
+fi
+
+rm -f conftest$ac_cv_exeext
+{ $as_echo "$as_me:$LINENO: result: $ac_cv_exeext" >&5
+$as_echo "$ac_cv_exeext" >&6; }
+
+rm -f conftest.$ac_ext
+EXEEXT=$ac_cv_exeext
+ac_exeext=$EXEEXT
+{ $as_echo "$as_me:$LINENO: checking for suffix of object files" >&5
+$as_echo_n "checking for suffix of object files... " >&6; }
+if test "${ac_cv_objext+set}" = set; then
+  $as_echo_n "(cached) " >&6
+else
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+
+int
+main ()
+{
+
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.o conftest.obj
+if { (ac_try="$ac_compile"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_compile") 2>&5
+  ac_status=$?
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; then
+  for ac_file in conftest.o conftest.obj conftest.*; do
+  test -f "$ac_file" || continue;
+  case $ac_file in
+    *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM ) ;;
+    *) ac_cv_objext=`expr "$ac_file" : '.*\.\(.*\)'`
+       break;;
+  esac
+done
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+{ { $as_echo "$as_me:$LINENO: error: in \`$ac_pwd':" >&5
+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
+{ { $as_echo "$as_me:$LINENO: error: cannot compute suffix of object files: cannot compile
+See \`config.log' for more details." >&5
+$as_echo "$as_me: error: cannot compute suffix of object files: cannot compile
+See \`config.log' for more details." >&2;}
+   { (exit 1); exit 1; }; }; }
+fi
+
+rm -f conftest.$ac_cv_objext conftest.$ac_ext
+fi
+{ $as_echo "$as_me:$LINENO: result: $ac_cv_objext" >&5
+$as_echo "$ac_cv_objext" >&6; }
+OBJEXT=$ac_cv_objext
+ac_objext=$OBJEXT
+{ $as_echo "$as_me:$LINENO: checking whether we are using the GNU C compiler" >&5
+$as_echo_n "checking whether we are using the GNU C compiler... " >&6; }
+if test "${ac_cv_c_compiler_gnu+set}" = set; then
+  $as_echo_n "(cached) " >&6
+else
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+
+int
+main ()
+{
+#ifndef __GNUC__
+       choke me
+#endif
+
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (ac_try="$ac_compile"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_compile") 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } && {
+        test -z "$ac_c_werror_flag" ||
+        test ! -s conftest.err
+       } && test -s conftest.$ac_objext; then
+  ac_compiler_gnu=yes
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+       ac_compiler_gnu=no
+fi
+
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+ac_cv_c_compiler_gnu=$ac_compiler_gnu
+
+fi
+{ $as_echo "$as_me:$LINENO: result: $ac_cv_c_compiler_gnu" >&5
+$as_echo "$ac_cv_c_compiler_gnu" >&6; }
+if test $ac_compiler_gnu = yes; then
+  GCC=yes
+else
+  GCC=
+fi
+ac_test_CFLAGS=${CFLAGS+set}
+ac_save_CFLAGS=$CFLAGS
+{ $as_echo "$as_me:$LINENO: checking whether $CC accepts -g" >&5
+$as_echo_n "checking whether $CC accepts -g... " >&6; }
+if test "${ac_cv_prog_cc_g+set}" = set; then
+  $as_echo_n "(cached) " >&6
+else
+  ac_save_c_werror_flag=$ac_c_werror_flag
+   ac_c_werror_flag=yes
+   ac_cv_prog_cc_g=no
+   CFLAGS="-g"
+   cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+
+int
+main ()
+{
+
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (ac_try="$ac_compile"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_compile") 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } && {
+        test -z "$ac_c_werror_flag" ||
+        test ! -s conftest.err
+       } && test -s conftest.$ac_objext; then
+  ac_cv_prog_cc_g=yes
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+       CFLAGS=""
+      cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+
+int
+main ()
+{
+
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (ac_try="$ac_compile"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_compile") 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } && {
+        test -z "$ac_c_werror_flag" ||
+        test ! -s conftest.err
+       } && test -s conftest.$ac_objext; then
+  :
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+       ac_c_werror_flag=$ac_save_c_werror_flag
+        CFLAGS="-g"
+        cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+
+int
+main ()
+{
+
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (ac_try="$ac_compile"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_compile") 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } && {
+        test -z "$ac_c_werror_flag" ||
+        test ! -s conftest.err
+       } && test -s conftest.$ac_objext; then
+  ac_cv_prog_cc_g=yes
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+
+fi
+
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+   ac_c_werror_flag=$ac_save_c_werror_flag
+fi
+{ $as_echo "$as_me:$LINENO: result: $ac_cv_prog_cc_g" >&5
+$as_echo "$ac_cv_prog_cc_g" >&6; }
+if test "$ac_test_CFLAGS" = set; then
+  CFLAGS=$ac_save_CFLAGS
+elif test $ac_cv_prog_cc_g = yes; then
+  if test "$GCC" = yes; then
+    CFLAGS="-g -O2"
+  else
+    CFLAGS="-g"
+  fi
+else
+  if test "$GCC" = yes; then
+    CFLAGS="-O2"
+  else
+    CFLAGS=
+  fi
+fi
+{ $as_echo "$as_me:$LINENO: checking for $CC option to accept ISO C89" >&5
+$as_echo_n "checking for $CC option to accept ISO C89... " >&6; }
+if test "${ac_cv_prog_cc_c89+set}" = set; then
+  $as_echo_n "(cached) " >&6
+else
+  ac_cv_prog_cc_c89=no
+ac_save_CC=$CC
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#include <stdarg.h>
+#include <stdio.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+/* Most of the following tests are stolen from RCS 5.7's src/conf.sh.  */
+struct buf { int x; };
+FILE * (*rcsopen) (struct buf *, struct stat *, int);
+static char *e (p, i)
+     char **p;
+     int i;
+{
+  return p[i];
+}
+static char *f (char * (*g) (char **, int), char **p, ...)
+{
+  char *s;
+  va_list v;
+  va_start (v,p);
+  s = g (p, va_arg (v,int));
+  va_end (v);
+  return s;
+}
+
+/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default.  It has
+   function prototypes and stuff, but not '\xHH' hex character constants.
+   These don't provoke an error unfortunately, instead are silently treated
+   as 'x'.  The following induces an error, until -std is added to get
+   proper ANSI mode.  Curiously '\x00'!='x' always comes out true, for an
+   array size at least.  It's necessary to write '\x00'==0 to get something
+   that's true only with -std.  */
+int osf4_cc_array ['\x00' == 0 ? 1 : -1];
+
+/* IBM C 6 for AIX is almost-ANSI by default, but it replaces macro parameters
+   inside strings and character constants.  */
+#define FOO(x) 'x'
+int xlc6_cc_array[FOO(a) == 'x' ? 1 : -1];
+
+int test (int i, double x);
+struct s1 {int (*f) (int a);};
+struct s2 {int (*f) (double a);};
+int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int);
+int argc;
+char **argv;
+int
+main ()
+{
+return f (e, argv, 0) != argv[0]  ||  f (e, argv, 1) != argv[1];
+  ;
+  return 0;
+}
+_ACEOF
+for ac_arg in '' -qlanglvl=extc89 -qlanglvl=ansi -std \
+       -Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__"
+do
+  CC="$ac_save_CC $ac_arg"
+  rm -f conftest.$ac_objext
+if { (ac_try="$ac_compile"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_compile") 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } && {
+        test -z "$ac_c_werror_flag" ||
+        test ! -s conftest.err
+       } && test -s conftest.$ac_objext; then
+  ac_cv_prog_cc_c89=$ac_arg
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+
+fi
+
+rm -f core conftest.err conftest.$ac_objext
+  test "x$ac_cv_prog_cc_c89" != "xno" && break
+done
+rm -f conftest.$ac_ext
+CC=$ac_save_CC
+
+fi
+# AC_CACHE_VAL
+case "x$ac_cv_prog_cc_c89" in
+  x)
+    { $as_echo "$as_me:$LINENO: result: none needed" >&5
+$as_echo "none needed" >&6; } ;;
+  xno)
+    { $as_echo "$as_me:$LINENO: result: unsupported" >&5
+$as_echo "unsupported" >&6; } ;;
+  *)
+    CC="$CC $ac_cv_prog_cc_c89"
+    { $as_echo "$as_me:$LINENO: result: $ac_cv_prog_cc_c89" >&5
+$as_echo "$ac_cv_prog_cc_c89" >&6; } ;;
+esac
+
+
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+
+# Find a good install program.  We prefer a C program (faster),
+# so one script is as good as another.  But avoid the broken or
+# incompatible versions:
+# SysV /etc/install, /usr/sbin/install
+# SunOS /usr/etc/install
+# IRIX /sbin/install
+# AIX /bin/install
+# AmigaOS /C/install, which installs bootblocks on floppy discs
+# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag
+# AFS /usr/afsws/bin/install, which mishandles nonexistent args
+# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff"
+# OS/2's system install, which has a completely different semantic
+# ./install, which can be erroneously created by make from ./install.sh.
+# Reject install programs that cannot install multiple files.
+{ $as_echo "$as_me:$LINENO: checking for a BSD-compatible install" >&5
+$as_echo_n "checking for a BSD-compatible install... " >&6; }
+if test -z "$INSTALL"; then
+if test "${ac_cv_path_install+set}" = set; then
+  $as_echo_n "(cached) " >&6
+else
+  as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  # Account for people who put trailing slashes in PATH elements.
+case $as_dir/ in
+  ./ | .// | /cC/* | \
+  /etc/* | /usr/sbin/* | /usr/etc/* | /sbin/* | /usr/afsws/bin/* | \
+  ?:\\/os2\\/install\\/* | ?:\\/OS2\\/INSTALL\\/* | \
+  /usr/ucb/* ) ;;
+  *)
+    # OSF1 and SCO ODT 3.0 have their own names for install.
+    # Don't use installbsd from OSF since it installs stuff as root
+    # by default.
+    for ac_prog in ginstall scoinst install; do
+      for ac_exec_ext in '' $ac_executable_extensions; do
+       if { test -f "$as_dir/$ac_prog$ac_exec_ext" && $as_test_x "$as_dir/$ac_prog$ac_exec_ext"; }; then
+         if test $ac_prog = install &&
+           grep dspmsg "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then
+           # AIX install.  It has an incompatible calling convention.
+           :
+         elif test $ac_prog = install &&
+           grep pwplus "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then
+           # program-specific install script used by HP pwplus--don't use.
+           :
+         else
+           rm -rf conftest.one conftest.two conftest.dir
+           echo one > conftest.one
+           echo two > conftest.two
+           mkdir conftest.dir
+           if "$as_dir/$ac_prog$ac_exec_ext" -c conftest.one conftest.two "`pwd`/conftest.dir" &&
+             test -s conftest.one && test -s conftest.two &&
+             test -s conftest.dir/conftest.one &&
+             test -s conftest.dir/conftest.two
+           then
+             ac_cv_path_install="$as_dir/$ac_prog$ac_exec_ext -c"
+             break 3
+           fi
+         fi
+       fi
+      done
+    done
+    ;;
+esac
+
+done
+IFS=$as_save_IFS
+
+rm -rf conftest.one conftest.two conftest.dir
+
+fi
+  if test "${ac_cv_path_install+set}" = set; then
+    INSTALL=$ac_cv_path_install
+  else
+    # As a last resort, use the slow shell script.  Don't cache a
+    # value for INSTALL within a source directory, because that will
+    # break other packages using the cache if that directory is
+    # removed, or if the value is a relative name.
+    INSTALL=$ac_install_sh
+  fi
+fi
+{ $as_echo "$as_me:$LINENO: result: $INSTALL" >&5
+$as_echo "$INSTALL" >&6; }
+
+# Use test -z because SunOS4 sh mishandles braces in ${var-val}.
+# It thinks the first close brace ends the variable substitution.
+test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}'
+
+test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL}'
+
+test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644'
+
+
+# Put a plausible default for CC_FOR_BUILD in Makefile.
+if test "x$cross_compiling" = "xno"; then
+  CC_FOR_BUILD='$(CC)'
+else
+  CC_FOR_BUILD=gcc
+fi
+
+
+
+
+AR=${AR-ar}
+
+if test -n "$ac_tool_prefix"; then
+  # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args.
+set dummy ${ac_tool_prefix}ranlib; ac_word=$2
+{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if test "${ac_cv_prog_RANLIB+set}" = set; then
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$RANLIB"; then
+  ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  for ac_exec_ext in '' $ac_executable_extensions; do
+  if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then
+    ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib"
+    $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+done
+IFS=$as_save_IFS
+
+fi
+fi
+RANLIB=$ac_cv_prog_RANLIB
+if test -n "$RANLIB"; then
+  { $as_echo "$as_me:$LINENO: result: $RANLIB" >&5
+$as_echo "$RANLIB" >&6; }
+else
+  { $as_echo "$as_me:$LINENO: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+
+fi
+if test -z "$ac_cv_prog_RANLIB"; then
+  ac_ct_RANLIB=$RANLIB
+  # Extract the first word of "ranlib", so it can be a program name with args.
+set dummy ranlib; ac_word=$2
+{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$ac_ct_RANLIB"; then
+  ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  for ac_exec_ext in '' $ac_executable_extensions; do
+  if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then
+    ac_cv_prog_ac_ct_RANLIB="ranlib"
+    $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+done
+IFS=$as_save_IFS
+
+fi
+fi
+ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB
+if test -n "$ac_ct_RANLIB"; then
+  { $as_echo "$as_me:$LINENO: result: $ac_ct_RANLIB" >&5
+$as_echo "$ac_ct_RANLIB" >&6; }
+else
+  { $as_echo "$as_me:$LINENO: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+  if test "x$ac_ct_RANLIB" = x; then
+    RANLIB=":"
+  else
+    case $cross_compiling:$ac_tool_warned in
+yes:)
+{ $as_echo "$as_me:$LINENO: WARNING: using cross tools not prefixed with host triplet" >&5
+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;}
+ac_tool_warned=yes ;;
+esac
+    RANLIB=$ac_ct_RANLIB
+  fi
+else
+  RANLIB="$ac_cv_prog_RANLIB"
+fi
+
+
+ALL_LINGUAS=
+# If we haven't got the data from the intl directory,
+# assume NLS is disabled.
+USE_NLS=no
+LIBINTL=
+LIBINTL_DEP=
+INCINTL=
+XGETTEXT=
+GMSGFMT=
+POSUB=
+
+if test -f  ../../intl/config.intl; then
+  .  ../../intl/config.intl
+fi
+{ $as_echo "$as_me:$LINENO: checking whether NLS is requested" >&5
+$as_echo_n "checking whether NLS is requested... " >&6; }
+if test x"$USE_NLS" != xyes; then
+  { $as_echo "$as_me:$LINENO: result: no" >&5
+$as_echo "no" >&6; }
+else
+  { $as_echo "$as_me:$LINENO: result: yes" >&5
+$as_echo "yes" >&6; }
+
+cat >>confdefs.h <<\_ACEOF
+#define ENABLE_NLS 1
+_ACEOF
+
+
+  { $as_echo "$as_me:$LINENO: checking for catalogs to be installed" >&5
+$as_echo_n "checking for catalogs to be installed... " >&6; }
+  # Look for .po and .gmo files in the source directory.
+  CATALOGS=
+  XLINGUAS=
+  for cat in $srcdir/po/*.gmo $srcdir/po/*.po; do
+    # If there aren't any .gmo files the shell will give us the
+    # literal string "../path/to/srcdir/po/*.gmo" which has to be
+    # weeded out.
+    case "$cat" in *\**)
+      continue;;
+    esac
+    # The quadruple backslash is collapsed to a double backslash
+    # by the backticks, then collapsed again by the double quotes,
+    # leaving us with one backslash in the sed expression (right
+    # before the dot that mustn't act as a wildcard).
+    cat=`echo $cat | sed -e "s!$srcdir/po/!!" -e "s!\\\\.po!.gmo!"`
+    lang=`echo $cat | sed -e "s!\\\\.gmo!!"`
+    # The user is allowed to set LINGUAS to a list of languages to
+    # install catalogs for.  If it's empty that means "all of them."
+    if test "x$LINGUAS" = x; then
+      CATALOGS="$CATALOGS $cat"
+      XLINGUAS="$XLINGUAS $lang"
+    else
+      case "$LINGUAS" in *$lang*)
+        CATALOGS="$CATALOGS $cat"
+        XLINGUAS="$XLINGUAS $lang"
+        ;;
+      esac
+    fi
+  done
+  LINGUAS="$XLINGUAS"
+  { $as_echo "$as_me:$LINENO: result: $LINGUAS" >&5
+$as_echo "$LINGUAS" >&6; }
+
+
+    DATADIRNAME=share
+
+  INSTOBJEXT=.mo
+
+  GENCAT=gencat
+
+  CATOBJEXT=.gmo
+
+fi
+
+# Check for common headers.
+# FIXME: Seems to me this can cause problems for i386-windows hosts.
+# At one point there were hardcoded AC_DEFINE's if ${host} = i386-*-windows*.
+
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+{ $as_echo "$as_me:$LINENO: checking how to run the C preprocessor" >&5
+$as_echo_n "checking how to run the C preprocessor... " >&6; }
+# On Suns, sometimes $CPP names a directory.
+if test -n "$CPP" && test -d "$CPP"; then
+  CPP=
+fi
+if test -z "$CPP"; then
+  if test "${ac_cv_prog_CPP+set}" = set; then
+  $as_echo_n "(cached) " >&6
+else
+      # Double quotes because CPP needs to be expanded
+    for CPP in "$CC -E" "$CC -E -traditional-cpp" "/lib/cpp"
+    do
+      ac_preproc_ok=false
+for ac_c_preproc_warn_flag in '' yes
+do
+  # Use a header file that comes with gcc, so configuring glibc
+  # with a fresh cross-compiler works.
+  # Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
+  # <limits.h> exists even on freestanding compilers.
+  # On the NeXT, cc -E runs the code through the compiler's parser,
+  # not just through cpp. "Syntax error" is here to catch this case.
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#ifdef __STDC__
+# include <limits.h>
+#else
+# include <assert.h>
+#endif
+                    Syntax error
+_ACEOF
+if { (ac_try="$ac_cpp conftest.$ac_ext"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } >/dev/null && {
+        test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" ||
+        test ! -s conftest.err
+       }; then
+  :
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+  # Broken: fails on valid input.
+continue
+fi
+
+rm -f conftest.err conftest.$ac_ext
+
+  # OK, works on sane cases.  Now check whether nonexistent headers
+  # can be detected and how.
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#include <ac_nonexistent.h>
+_ACEOF
+if { (ac_try="$ac_cpp conftest.$ac_ext"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } >/dev/null && {
+        test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" ||
+        test ! -s conftest.err
+       }; then
+  # Broken: success on invalid input.
+continue
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+  # Passes both tests.
+ac_preproc_ok=:
+break
+fi
+
+rm -f conftest.err conftest.$ac_ext
+
+done
+# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped.
+rm -f conftest.err conftest.$ac_ext
+if $ac_preproc_ok; then
+  break
+fi
+
+    done
+    ac_cv_prog_CPP=$CPP
+
+fi
+  CPP=$ac_cv_prog_CPP
+else
+  ac_cv_prog_CPP=$CPP
+fi
+{ $as_echo "$as_me:$LINENO: result: $CPP" >&5
+$as_echo "$CPP" >&6; }
+ac_preproc_ok=false
+for ac_c_preproc_warn_flag in '' yes
+do
+  # Use a header file that comes with gcc, so configuring glibc
+  # with a fresh cross-compiler works.
+  # Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
+  # <limits.h> exists even on freestanding compilers.
+  # On the NeXT, cc -E runs the code through the compiler's parser,
+  # not just through cpp. "Syntax error" is here to catch this case.
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#ifdef __STDC__
+# include <limits.h>
+#else
+# include <assert.h>
+#endif
+                    Syntax error
+_ACEOF
+if { (ac_try="$ac_cpp conftest.$ac_ext"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } >/dev/null && {
+        test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" ||
+        test ! -s conftest.err
+       }; then
+  :
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+  # Broken: fails on valid input.
+continue
+fi
+
+rm -f conftest.err conftest.$ac_ext
+
+  # OK, works on sane cases.  Now check whether nonexistent headers
+  # can be detected and how.
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#include <ac_nonexistent.h>
+_ACEOF
+if { (ac_try="$ac_cpp conftest.$ac_ext"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } >/dev/null && {
+        test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" ||
+        test ! -s conftest.err
+       }; then
+  # Broken: success on invalid input.
+continue
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+  # Passes both tests.
+ac_preproc_ok=:
+break
+fi
+
+rm -f conftest.err conftest.$ac_ext
+
+done
+# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped.
+rm -f conftest.err conftest.$ac_ext
+if $ac_preproc_ok; then
+  :
+else
+  { { $as_echo "$as_me:$LINENO: error: in \`$ac_pwd':" >&5
+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
+{ { $as_echo "$as_me:$LINENO: error: C preprocessor \"$CPP\" fails sanity check
+See \`config.log' for more details." >&5
+$as_echo "$as_me: error: C preprocessor \"$CPP\" fails sanity check
+See \`config.log' for more details." >&2;}
+   { (exit 1); exit 1; }; }; }
+fi
+
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+
+
+{ $as_echo "$as_me:$LINENO: checking for grep that handles long lines and -e" >&5
+$as_echo_n "checking for grep that handles long lines and -e... " >&6; }
+if test "${ac_cv_path_GREP+set}" = set; then
+  $as_echo_n "(cached) " >&6
+else
+  if test -z "$GREP"; then
+  ac_path_GREP_found=false
+  # Loop through the user's path and test for each of PROGNAME-LIST
+  as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  for ac_prog in grep ggrep; do
+    for ac_exec_ext in '' $ac_executable_extensions; do
+      ac_path_GREP="$as_dir/$ac_prog$ac_exec_ext"
+      { test -f "$ac_path_GREP" && $as_test_x "$ac_path_GREP"; } || continue
+# Check for GNU ac_path_GREP and select it if it is found.
+  # Check for GNU $ac_path_GREP
+case `"$ac_path_GREP" --version 2>&1` in
+*GNU*)
+  ac_cv_path_GREP="$ac_path_GREP" ac_path_GREP_found=:;;
+*)
+  ac_count=0
+  $as_echo_n 0123456789 >"conftest.in"
+  while :
+  do
+    cat "conftest.in" "conftest.in" >"conftest.tmp"
+    mv "conftest.tmp" "conftest.in"
+    cp "conftest.in" "conftest.nl"
+    $as_echo 'GREP' >> "conftest.nl"
+    "$ac_path_GREP" -e 'GREP$' -e '-(cannot match)-' < "conftest.nl" >"conftest.out" 2>/dev/null || break
+    diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break
+    ac_count=`expr $ac_count + 1`
+    if test $ac_count -gt ${ac_path_GREP_max-0}; then
+      # Best one so far, save it but keep looking for a better one
+      ac_cv_path_GREP="$ac_path_GREP"
+      ac_path_GREP_max=$ac_count
+    fi
+    # 10*(2^10) chars as input seems more than enough
+    test $ac_count -gt 10 && break
+  done
+  rm -f conftest.in conftest.tmp conftest.nl conftest.out;;
+esac
+
+      $ac_path_GREP_found && break 3
+    done
+  done
+done
+IFS=$as_save_IFS
+  if test -z "$ac_cv_path_GREP"; then
+    { { $as_echo "$as_me:$LINENO: error: no acceptable grep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&5
+$as_echo "$as_me: error: no acceptable grep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&2;}
+   { (exit 1); exit 1; }; }
+  fi
+else
+  ac_cv_path_GREP=$GREP
+fi
+
+fi
+{ $as_echo "$as_me:$LINENO: result: $ac_cv_path_GREP" >&5
+$as_echo "$ac_cv_path_GREP" >&6; }
+ GREP="$ac_cv_path_GREP"
+
+
+{ $as_echo "$as_me:$LINENO: checking for egrep" >&5
+$as_echo_n "checking for egrep... " >&6; }
+if test "${ac_cv_path_EGREP+set}" = set; then
+  $as_echo_n "(cached) " >&6
+else
+  if echo a | $GREP -E '(a|b)' >/dev/null 2>&1
+   then ac_cv_path_EGREP="$GREP -E"
+   else
+     if test -z "$EGREP"; then
+  ac_path_EGREP_found=false
+  # Loop through the user's path and test for each of PROGNAME-LIST
+  as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  for ac_prog in egrep; do
+    for ac_exec_ext in '' $ac_executable_extensions; do
+      ac_path_EGREP="$as_dir/$ac_prog$ac_exec_ext"
+      { test -f "$ac_path_EGREP" && $as_test_x "$ac_path_EGREP"; } || continue
+# Check for GNU ac_path_EGREP and select it if it is found.
+  # Check for GNU $ac_path_EGREP
+case `"$ac_path_EGREP" --version 2>&1` in
+*GNU*)
+  ac_cv_path_EGREP="$ac_path_EGREP" ac_path_EGREP_found=:;;
+*)
+  ac_count=0
+  $as_echo_n 0123456789 >"conftest.in"
+  while :
+  do
+    cat "conftest.in" "conftest.in" >"conftest.tmp"
+    mv "conftest.tmp" "conftest.in"
+    cp "conftest.in" "conftest.nl"
+    $as_echo 'EGREP' >> "conftest.nl"
+    "$ac_path_EGREP" 'EGREP$' < "conftest.nl" >"conftest.out" 2>/dev/null || break
+    diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break
+    ac_count=`expr $ac_count + 1`
+    if test $ac_count -gt ${ac_path_EGREP_max-0}; then
+      # Best one so far, save it but keep looking for a better one
+      ac_cv_path_EGREP="$ac_path_EGREP"
+      ac_path_EGREP_max=$ac_count
+    fi
+    # 10*(2^10) chars as input seems more than enough
+    test $ac_count -gt 10 && break
+  done
+  rm -f conftest.in conftest.tmp conftest.nl conftest.out;;
+esac
+
+      $ac_path_EGREP_found && break 3
+    done
+  done
+done
+IFS=$as_save_IFS
+  if test -z "$ac_cv_path_EGREP"; then
+    { { $as_echo "$as_me:$LINENO: error: no acceptable egrep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&5
+$as_echo "$as_me: error: no acceptable egrep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&2;}
+   { (exit 1); exit 1; }; }
+  fi
+else
+  ac_cv_path_EGREP=$EGREP
+fi
+
+   fi
+fi
+{ $as_echo "$as_me:$LINENO: result: $ac_cv_path_EGREP" >&5
+$as_echo "$ac_cv_path_EGREP" >&6; }
+ EGREP="$ac_cv_path_EGREP"
+
+
+{ $as_echo "$as_me:$LINENO: checking for ANSI C header files" >&5
+$as_echo_n "checking for ANSI C header files... " >&6; }
+if test "${ac_cv_header_stdc+set}" = set; then
+  $as_echo_n "(cached) " >&6
+else
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#include <stdlib.h>
+#include <stdarg.h>
+#include <string.h>
+#include <float.h>
+
+int
+main ()
+{
+
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (ac_try="$ac_compile"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_compile") 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } && {
+        test -z "$ac_c_werror_flag" ||
+        test ! -s conftest.err
+       } && test -s conftest.$ac_objext; then
+  ac_cv_header_stdc=yes
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+       ac_cv_header_stdc=no
+fi
+
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+
+if test $ac_cv_header_stdc = yes; then
+  # SunOS 4.x string.h does not declare mem*, contrary to ANSI.
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#include <string.h>
+
+_ACEOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+  $EGREP "memchr" >/dev/null 2>&1; then
+  :
+else
+  ac_cv_header_stdc=no
+fi
+rm -f conftest*
+
+fi
+
+if test $ac_cv_header_stdc = yes; then
+  # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI.
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#include <stdlib.h>
+
+_ACEOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+  $EGREP "free" >/dev/null 2>&1; then
+  :
+else
+  ac_cv_header_stdc=no
+fi
+rm -f conftest*
+
+fi
+
+if test $ac_cv_header_stdc = yes; then
+  # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi.
+  if test "$cross_compiling" = yes; then
+  :
+else
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#include <ctype.h>
+#include <stdlib.h>
+#if ((' ' & 0x0FF) == 0x020)
+# define ISLOWER(c) ('a' <= (c) && (c) <= 'z')
+# define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c))
+#else
+# define ISLOWER(c) \
+                  (('a' <= (c) && (c) <= 'i') \
+                    || ('j' <= (c) && (c) <= 'r') \
+                    || ('s' <= (c) && (c) <= 'z'))
+# define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c))
+#endif
+
+#define XOR(e, f) (((e) && !(f)) || (!(e) && (f)))
+int
+main ()
+{
+  int i;
+  for (i = 0; i < 256; i++)
+    if (XOR (islower (i), ISLOWER (i))
+       || toupper (i) != TOUPPER (i))
+      return 2;
+  return 0;
+}
+_ACEOF
+rm -f conftest$ac_exeext
+if { (ac_try="$ac_link"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_link") 2>&5
+  ac_status=$?
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } && { ac_try='./conftest$ac_exeext'
+  { (case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_try") 2>&5
+  ac_status=$?
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  :
+else
+  $as_echo "$as_me: program exited with status $ac_status" >&5
+$as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+( exit $ac_status )
+ac_cv_header_stdc=no
+fi
+rm -rf conftest.dSYM
+rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext
+fi
+
+
+fi
+fi
+{ $as_echo "$as_me:$LINENO: result: $ac_cv_header_stdc" >&5
+$as_echo "$ac_cv_header_stdc" >&6; }
+if test $ac_cv_header_stdc = yes; then
+
+cat >>confdefs.h <<\_ACEOF
+#define STDC_HEADERS 1
+_ACEOF
+
+fi
+
+# On IRIX 5.3, sys/types and inttypes.h are conflicting.
+
+
+
+
+
+
+
+
+
+for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \
+                 inttypes.h stdint.h unistd.h
+do
+as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh`
+{ $as_echo "$as_me:$LINENO: checking for $ac_header" >&5
+$as_echo_n "checking for $ac_header... " >&6; }
+if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then
+  $as_echo_n "(cached) " >&6
+else
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+$ac_includes_default
+
+#include <$ac_header>
+_ACEOF
+rm -f conftest.$ac_objext
+if { (ac_try="$ac_compile"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_compile") 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } && {
+        test -z "$ac_c_werror_flag" ||
+        test ! -s conftest.err
+       } && test -s conftest.$ac_objext; then
+  eval "$as_ac_Header=yes"
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+       eval "$as_ac_Header=no"
+fi
+
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+ac_res=`eval 'as_val=${'$as_ac_Header'}
+                $as_echo "$as_val"'`
+              { $as_echo "$as_me:$LINENO: result: $ac_res" >&5
+$as_echo "$ac_res" >&6; }
+as_val=`eval 'as_val=${'$as_ac_Header'}
+                $as_echo "$as_val"'`
+   if test "x$as_val" = x""yes; then
+  cat >>confdefs.h <<_ACEOF
+#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+
+done
+
+
+
+
+
+
+
+for ac_header in stdlib.h string.h strings.h unistd.h time.h
+do
+as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh`
+if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then
+  { $as_echo "$as_me:$LINENO: checking for $ac_header" >&5
+$as_echo_n "checking for $ac_header... " >&6; }
+if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then
+  $as_echo_n "(cached) " >&6
+fi
+ac_res=`eval 'as_val=${'$as_ac_Header'}
+                $as_echo "$as_val"'`
+              { $as_echo "$as_me:$LINENO: result: $ac_res" >&5
+$as_echo "$ac_res" >&6; }
+else
+  # Is the header compilable?
+{ $as_echo "$as_me:$LINENO: checking $ac_header usability" >&5
+$as_echo_n "checking $ac_header usability... " >&6; }
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+$ac_includes_default
+#include <$ac_header>
+_ACEOF
+rm -f conftest.$ac_objext
+if { (ac_try="$ac_compile"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_compile") 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } && {
+        test -z "$ac_c_werror_flag" ||
+        test ! -s conftest.err
+       } && test -s conftest.$ac_objext; then
+  ac_header_compiler=yes
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+       ac_header_compiler=no
+fi
+
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+{ $as_echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
+$as_echo "$ac_header_compiler" >&6; }
+
+# Is the header present?
+{ $as_echo "$as_me:$LINENO: checking $ac_header presence" >&5
+$as_echo_n "checking $ac_header presence... " >&6; }
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#include <$ac_header>
+_ACEOF
+if { (ac_try="$ac_cpp conftest.$ac_ext"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } >/dev/null && {
+        test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" ||
+        test ! -s conftest.err
+       }; then
+  ac_header_preproc=yes
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+  ac_header_preproc=no
+fi
+
+rm -f conftest.err conftest.$ac_ext
+{ $as_echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
+$as_echo "$ac_header_preproc" >&6; }
+
+# So?  What about this header?
+case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
+  yes:no: )
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
+$as_echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
+$as_echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
+    ac_header_preproc=yes
+    ;;
+  no:yes:* )
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
+$as_echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header:     check for missing prerequisite headers?" >&5
+$as_echo "$as_me: WARNING: $ac_header:     check for missing prerequisite headers?" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
+$as_echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&5
+$as_echo "$as_me: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
+$as_echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
+$as_echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
+
+    ;;
+esac
+{ $as_echo "$as_me:$LINENO: checking for $ac_header" >&5
+$as_echo_n "checking for $ac_header... " >&6; }
+if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then
+  $as_echo_n "(cached) " >&6
+else
+  eval "$as_ac_Header=\$ac_header_preproc"
+fi
+ac_res=`eval 'as_val=${'$as_ac_Header'}
+                $as_echo "$as_val"'`
+              { $as_echo "$as_me:$LINENO: result: $ac_res" >&5
+$as_echo "$ac_res" >&6; }
+
+fi
+as_val=`eval 'as_val=${'$as_ac_Header'}
+                $as_echo "$as_val"'`
+   if test "x$as_val" = x""yes; then
+  cat >>confdefs.h <<_ACEOF
+#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+
+done
+
+
+
+for ac_header in sys/time.h sys/resource.h
+do
+as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh`
+if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then
+  { $as_echo "$as_me:$LINENO: checking for $ac_header" >&5
+$as_echo_n "checking for $ac_header... " >&6; }
+if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then
+  $as_echo_n "(cached) " >&6
+fi
+ac_res=`eval 'as_val=${'$as_ac_Header'}
+                $as_echo "$as_val"'`
+              { $as_echo "$as_me:$LINENO: result: $ac_res" >&5
+$as_echo "$ac_res" >&6; }
+else
+  # Is the header compilable?
+{ $as_echo "$as_me:$LINENO: checking $ac_header usability" >&5
+$as_echo_n "checking $ac_header usability... " >&6; }
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+$ac_includes_default
+#include <$ac_header>
+_ACEOF
+rm -f conftest.$ac_objext
+if { (ac_try="$ac_compile"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_compile") 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } && {
+        test -z "$ac_c_werror_flag" ||
+        test ! -s conftest.err
+       } && test -s conftest.$ac_objext; then
+  ac_header_compiler=yes
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+       ac_header_compiler=no
+fi
+
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+{ $as_echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
+$as_echo "$ac_header_compiler" >&6; }
+
+# Is the header present?
+{ $as_echo "$as_me:$LINENO: checking $ac_header presence" >&5
+$as_echo_n "checking $ac_header presence... " >&6; }
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#include <$ac_header>
+_ACEOF
+if { (ac_try="$ac_cpp conftest.$ac_ext"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } >/dev/null && {
+        test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" ||
+        test ! -s conftest.err
+       }; then
+  ac_header_preproc=yes
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+  ac_header_preproc=no
+fi
+
+rm -f conftest.err conftest.$ac_ext
+{ $as_echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
+$as_echo "$ac_header_preproc" >&6; }
+
+# So?  What about this header?
+case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
+  yes:no: )
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
+$as_echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
+$as_echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
+    ac_header_preproc=yes
+    ;;
+  no:yes:* )
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
+$as_echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header:     check for missing prerequisite headers?" >&5
+$as_echo "$as_me: WARNING: $ac_header:     check for missing prerequisite headers?" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
+$as_echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&5
+$as_echo "$as_me: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
+$as_echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
+$as_echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
+
+    ;;
+esac
+{ $as_echo "$as_me:$LINENO: checking for $ac_header" >&5
+$as_echo_n "checking for $ac_header... " >&6; }
+if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then
+  $as_echo_n "(cached) " >&6
+else
+  eval "$as_ac_Header=\$ac_header_preproc"
+fi
+ac_res=`eval 'as_val=${'$as_ac_Header'}
+                $as_echo "$as_val"'`
+              { $as_echo "$as_me:$LINENO: result: $ac_res" >&5
+$as_echo "$ac_res" >&6; }
+
+fi
+as_val=`eval 'as_val=${'$as_ac_Header'}
+                $as_echo "$as_val"'`
+   if test "x$as_val" = x""yes; then
+  cat >>confdefs.h <<_ACEOF
+#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+
+done
+
+
+
+for ac_header in fcntl.h fpu_control.h
+do
+as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh`
+if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then
+  { $as_echo "$as_me:$LINENO: checking for $ac_header" >&5
+$as_echo_n "checking for $ac_header... " >&6; }
+if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then
+  $as_echo_n "(cached) " >&6
+fi
+ac_res=`eval 'as_val=${'$as_ac_Header'}
+                $as_echo "$as_val"'`
+              { $as_echo "$as_me:$LINENO: result: $ac_res" >&5
+$as_echo "$ac_res" >&6; }
+else
+  # Is the header compilable?
+{ $as_echo "$as_me:$LINENO: checking $ac_header usability" >&5
+$as_echo_n "checking $ac_header usability... " >&6; }
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+$ac_includes_default
+#include <$ac_header>
+_ACEOF
+rm -f conftest.$ac_objext
+if { (ac_try="$ac_compile"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_compile") 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } && {
+        test -z "$ac_c_werror_flag" ||
+        test ! -s conftest.err
+       } && test -s conftest.$ac_objext; then
+  ac_header_compiler=yes
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+       ac_header_compiler=no
+fi
+
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+{ $as_echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
+$as_echo "$ac_header_compiler" >&6; }
+
+# Is the header present?
+{ $as_echo "$as_me:$LINENO: checking $ac_header presence" >&5
+$as_echo_n "checking $ac_header presence... " >&6; }
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#include <$ac_header>
+_ACEOF
+if { (ac_try="$ac_cpp conftest.$ac_ext"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } >/dev/null && {
+        test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" ||
+        test ! -s conftest.err
+       }; then
+  ac_header_preproc=yes
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+  ac_header_preproc=no
+fi
+
+rm -f conftest.err conftest.$ac_ext
+{ $as_echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
+$as_echo "$ac_header_preproc" >&6; }
+
+# So?  What about this header?
+case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
+  yes:no: )
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
+$as_echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
+$as_echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
+    ac_header_preproc=yes
+    ;;
+  no:yes:* )
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
+$as_echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header:     check for missing prerequisite headers?" >&5
+$as_echo "$as_me: WARNING: $ac_header:     check for missing prerequisite headers?" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
+$as_echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&5
+$as_echo "$as_me: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
+$as_echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
+$as_echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
+
+    ;;
+esac
+{ $as_echo "$as_me:$LINENO: checking for $ac_header" >&5
+$as_echo_n "checking for $ac_header... " >&6; }
+if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then
+  $as_echo_n "(cached) " >&6
+else
+  eval "$as_ac_Header=\$ac_header_preproc"
+fi
+ac_res=`eval 'as_val=${'$as_ac_Header'}
+                $as_echo "$as_val"'`
+              { $as_echo "$as_me:$LINENO: result: $ac_res" >&5
+$as_echo "$ac_res" >&6; }
+
+fi
+as_val=`eval 'as_val=${'$as_ac_Header'}
+                $as_echo "$as_val"'`
+   if test "x$as_val" = x""yes; then
+  cat >>confdefs.h <<_ACEOF
+#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+
+done
+
+
+
+
+for ac_header in dlfcn.h errno.h sys/stat.h
+do
+as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh`
+if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then
+  { $as_echo "$as_me:$LINENO: checking for $ac_header" >&5
+$as_echo_n "checking for $ac_header... " >&6; }
+if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then
+  $as_echo_n "(cached) " >&6
+fi
+ac_res=`eval 'as_val=${'$as_ac_Header'}
+                $as_echo "$as_val"'`
+              { $as_echo "$as_me:$LINENO: result: $ac_res" >&5
+$as_echo "$ac_res" >&6; }
+else
+  # Is the header compilable?
+{ $as_echo "$as_me:$LINENO: checking $ac_header usability" >&5
+$as_echo_n "checking $ac_header usability... " >&6; }
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+$ac_includes_default
+#include <$ac_header>
+_ACEOF
+rm -f conftest.$ac_objext
+if { (ac_try="$ac_compile"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_compile") 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } && {
+        test -z "$ac_c_werror_flag" ||
+        test ! -s conftest.err
+       } && test -s conftest.$ac_objext; then
+  ac_header_compiler=yes
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+       ac_header_compiler=no
+fi
+
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+{ $as_echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
+$as_echo "$ac_header_compiler" >&6; }
+
+# Is the header present?
+{ $as_echo "$as_me:$LINENO: checking $ac_header presence" >&5
+$as_echo_n "checking $ac_header presence... " >&6; }
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#include <$ac_header>
+_ACEOF
+if { (ac_try="$ac_cpp conftest.$ac_ext"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } >/dev/null && {
+        test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" ||
+        test ! -s conftest.err
+       }; then
+  ac_header_preproc=yes
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+  ac_header_preproc=no
+fi
+
+rm -f conftest.err conftest.$ac_ext
+{ $as_echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
+$as_echo "$ac_header_preproc" >&6; }
+
+# So?  What about this header?
+case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
+  yes:no: )
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
+$as_echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
+$as_echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
+    ac_header_preproc=yes
+    ;;
+  no:yes:* )
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
+$as_echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header:     check for missing prerequisite headers?" >&5
+$as_echo "$as_me: WARNING: $ac_header:     check for missing prerequisite headers?" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
+$as_echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&5
+$as_echo "$as_me: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
+$as_echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
+$as_echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
+
+    ;;
+esac
+{ $as_echo "$as_me:$LINENO: checking for $ac_header" >&5
+$as_echo_n "checking for $ac_header... " >&6; }
+if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then
+  $as_echo_n "(cached) " >&6
+else
+  eval "$as_ac_Header=\$ac_header_preproc"
+fi
+ac_res=`eval 'as_val=${'$as_ac_Header'}
+                $as_echo "$as_val"'`
+              { $as_echo "$as_me:$LINENO: result: $ac_res" >&5
+$as_echo "$ac_res" >&6; }
+
+fi
+as_val=`eval 'as_val=${'$as_ac_Header'}
+                $as_echo "$as_val"'`
+   if test "x$as_val" = x""yes; then
+  cat >>confdefs.h <<_ACEOF
+#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+
+done
+
+
+
+
+
+for ac_func in getrusage time sigaction __setfpucw
+do
+as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh`
+{ $as_echo "$as_me:$LINENO: checking for $ac_func" >&5
+$as_echo_n "checking for $ac_func... " >&6; }
+if { as_var=$as_ac_var; eval "test \"\${$as_var+set}\" = set"; }; then
+  $as_echo_n "(cached) " >&6
+else
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func.
+   For example, HP-UX 11i <limits.h> declares gettimeofday.  */
+#define $ac_func innocuous_$ac_func
+
+/* System header to define __stub macros and hopefully few prototypes,
+    which can conflict with char $ac_func (); below.
+    Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
+    <limits.h> exists even on freestanding compilers.  */
+
+#ifdef __STDC__
+# include <limits.h>
+#else
+# include <assert.h>
+#endif
+
+#undef $ac_func
+
+/* Override any GCC internal prototype to avoid an error.
+   Use char because int might match the return type of a GCC
+   builtin and then its argument prototype would still apply.  */
+#ifdef __cplusplus
+extern "C"
+#endif
+char $ac_func ();
+/* The GNU C library defines this for functions which it implements
+    to always fail with ENOSYS.  Some functions are actually named
+    something starting with __ and the normal name is an alias.  */
+#if defined __stub_$ac_func || defined __stub___$ac_func
+choke me
+#endif
+
+int
+main ()
+{
+return $ac_func ();
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (ac_try="$ac_link"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_link") 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } && {
+        test -z "$ac_c_werror_flag" ||
+        test ! -s conftest.err
+       } && test -s conftest$ac_exeext && {
+        test "$cross_compiling" = yes ||
+        $as_test_x conftest$ac_exeext
+       }; then
+  eval "$as_ac_var=yes"
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+       eval "$as_ac_var=no"
+fi
+
+rm -rf conftest.dSYM
+rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \
+      conftest$ac_exeext conftest.$ac_ext
+fi
+ac_res=`eval 'as_val=${'$as_ac_var'}
+                $as_echo "$as_val"'`
+              { $as_echo "$as_me:$LINENO: result: $ac_res" >&5
+$as_echo "$ac_res" >&6; }
+as_val=`eval 'as_val=${'$as_ac_var'}
+                $as_echo "$as_val"'`
+   if test "x$as_val" = x""yes; then
+  cat >>confdefs.h <<_ACEOF
+#define `$as_echo "HAVE_$ac_func" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+done
+
+
+# Check for socket libraries
+
+{ $as_echo "$as_me:$LINENO: checking for bind in -lsocket" >&5
+$as_echo_n "checking for bind in -lsocket... " >&6; }
+if test "${ac_cv_lib_socket_bind+set}" = set; then
+  $as_echo_n "(cached) " >&6
+else
+  ac_check_lib_save_LIBS=$LIBS
+LIBS="-lsocket  $LIBS"
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+
+/* Override any GCC internal prototype to avoid an error.
+   Use char because int might match the return type of a GCC
+   builtin and then its argument prototype would still apply.  */
+#ifdef __cplusplus
+extern "C"
+#endif
+char bind ();
+int
+main ()
+{
+return bind ();
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (ac_try="$ac_link"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_link") 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } && {
+        test -z "$ac_c_werror_flag" ||
+        test ! -s conftest.err
+       } && test -s conftest$ac_exeext && {
+        test "$cross_compiling" = yes ||
+        $as_test_x conftest$ac_exeext
+       }; then
+  ac_cv_lib_socket_bind=yes
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+       ac_cv_lib_socket_bind=no
+fi
+
+rm -rf conftest.dSYM
+rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \
+      conftest$ac_exeext conftest.$ac_ext
+LIBS=$ac_check_lib_save_LIBS
+fi
+{ $as_echo "$as_me:$LINENO: result: $ac_cv_lib_socket_bind" >&5
+$as_echo "$ac_cv_lib_socket_bind" >&6; }
+if test "x$ac_cv_lib_socket_bind" = x""yes; then
+  cat >>confdefs.h <<_ACEOF
+#define HAVE_LIBSOCKET 1
+_ACEOF
+
+  LIBS="-lsocket $LIBS"
+
+fi
+
+
+{ $as_echo "$as_me:$LINENO: checking for gethostbyname in -lnsl" >&5
+$as_echo_n "checking for gethostbyname in -lnsl... " >&6; }
+if test "${ac_cv_lib_nsl_gethostbyname+set}" = set; then
+  $as_echo_n "(cached) " >&6
+else
+  ac_check_lib_save_LIBS=$LIBS
+LIBS="-lnsl  $LIBS"
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+
+/* Override any GCC internal prototype to avoid an error.
+   Use char because int might match the return type of a GCC
+   builtin and then its argument prototype would still apply.  */
+#ifdef __cplusplus
+extern "C"
+#endif
+char gethostbyname ();
+int
+main ()
+{
+return gethostbyname ();
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (ac_try="$ac_link"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_link") 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } && {
+        test -z "$ac_c_werror_flag" ||
+        test ! -s conftest.err
+       } && test -s conftest$ac_exeext && {
+        test "$cross_compiling" = yes ||
+        $as_test_x conftest$ac_exeext
+       }; then
+  ac_cv_lib_nsl_gethostbyname=yes
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+       ac_cv_lib_nsl_gethostbyname=no
+fi
+
+rm -rf conftest.dSYM
+rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \
+      conftest$ac_exeext conftest.$ac_ext
+LIBS=$ac_check_lib_save_LIBS
+fi
+{ $as_echo "$as_me:$LINENO: result: $ac_cv_lib_nsl_gethostbyname" >&5
+$as_echo "$ac_cv_lib_nsl_gethostbyname" >&6; }
+if test "x$ac_cv_lib_nsl_gethostbyname" = x""yes; then
+  cat >>confdefs.h <<_ACEOF
+#define HAVE_LIBNSL 1
+_ACEOF
+
+  LIBS="-lnsl $LIBS"
+
+fi
+
+
+# BFD conditionally uses zlib, so we must link it in if libbfd does, by
+# using the same condition.
+{ $as_echo "$as_me:$LINENO: checking for library containing zlibVersion" >&5
+$as_echo_n "checking for library containing zlibVersion... " >&6; }
+if test "${ac_cv_search_zlibVersion+set}" = set; then
+  $as_echo_n "(cached) " >&6
+else
+  ac_func_search_save_LIBS=$LIBS
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+
+/* Override any GCC internal prototype to avoid an error.
+   Use char because int might match the return type of a GCC
+   builtin and then its argument prototype would still apply.  */
+#ifdef __cplusplus
+extern "C"
+#endif
+char zlibVersion ();
+int
+main ()
+{
+return zlibVersion ();
+  ;
+  return 0;
+}
+_ACEOF
+for ac_lib in '' z; do
+  if test -z "$ac_lib"; then
+    ac_res="none required"
+  else
+    ac_res=-l$ac_lib
+    LIBS="-l$ac_lib  $ac_func_search_save_LIBS"
+  fi
+  rm -f conftest.$ac_objext conftest$ac_exeext
+if { (ac_try="$ac_link"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_link") 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } && {
+        test -z "$ac_c_werror_flag" ||
+        test ! -s conftest.err
+       } && test -s conftest$ac_exeext && {
+        test "$cross_compiling" = yes ||
+        $as_test_x conftest$ac_exeext
+       }; then
+  ac_cv_search_zlibVersion=$ac_res
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+
+fi
+
+rm -rf conftest.dSYM
+rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \
+      conftest$ac_exeext
+  if test "${ac_cv_search_zlibVersion+set}" = set; then
+  break
+fi
+done
+if test "${ac_cv_search_zlibVersion+set}" = set; then
+  :
+else
+  ac_cv_search_zlibVersion=no
+fi
+rm conftest.$ac_ext
+LIBS=$ac_func_search_save_LIBS
+fi
+{ $as_echo "$as_me:$LINENO: result: $ac_cv_search_zlibVersion" >&5
+$as_echo "$ac_cv_search_zlibVersion" >&6; }
+ac_res=$ac_cv_search_zlibVersion
+if test "$ac_res" != no; then
+  test "$ac_res" = "none required" || LIBS="$ac_res $LIBS"
+
+for ac_header in zlib.h
+do
+as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh`
+if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then
+  { $as_echo "$as_me:$LINENO: checking for $ac_header" >&5
+$as_echo_n "checking for $ac_header... " >&6; }
+if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then
+  $as_echo_n "(cached) " >&6
+fi
+ac_res=`eval 'as_val=${'$as_ac_Header'}
+                $as_echo "$as_val"'`
+              { $as_echo "$as_me:$LINENO: result: $ac_res" >&5
+$as_echo "$ac_res" >&6; }
+else
+  # Is the header compilable?
+{ $as_echo "$as_me:$LINENO: checking $ac_header usability" >&5
+$as_echo_n "checking $ac_header usability... " >&6; }
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+$ac_includes_default
+#include <$ac_header>
+_ACEOF
+rm -f conftest.$ac_objext
+if { (ac_try="$ac_compile"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_compile") 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } && {
+        test -z "$ac_c_werror_flag" ||
+        test ! -s conftest.err
+       } && test -s conftest.$ac_objext; then
+  ac_header_compiler=yes
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+       ac_header_compiler=no
+fi
+
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+{ $as_echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
+$as_echo "$ac_header_compiler" >&6; }
+
+# Is the header present?
+{ $as_echo "$as_me:$LINENO: checking $ac_header presence" >&5
+$as_echo_n "checking $ac_header presence... " >&6; }
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#include <$ac_header>
+_ACEOF
+if { (ac_try="$ac_cpp conftest.$ac_ext"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } >/dev/null && {
+        test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" ||
+        test ! -s conftest.err
+       }; then
+  ac_header_preproc=yes
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+  ac_header_preproc=no
+fi
+
+rm -f conftest.err conftest.$ac_ext
+{ $as_echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
+$as_echo "$ac_header_preproc" >&6; }
+
+# So?  What about this header?
+case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
+  yes:no: )
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
+$as_echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
+$as_echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
+    ac_header_preproc=yes
+    ;;
+  no:yes:* )
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
+$as_echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header:     check for missing prerequisite headers?" >&5
+$as_echo "$as_me: WARNING: $ac_header:     check for missing prerequisite headers?" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
+$as_echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&5
+$as_echo "$as_me: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
+$as_echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
+$as_echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
+
+    ;;
+esac
+{ $as_echo "$as_me:$LINENO: checking for $ac_header" >&5
+$as_echo_n "checking for $ac_header... " >&6; }
+if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then
+  $as_echo_n "(cached) " >&6
+else
+  eval "$as_ac_Header=\$ac_header_preproc"
+fi
+ac_res=`eval 'as_val=${'$as_ac_Header'}
+                $as_echo "$as_val"'`
+              { $as_echo "$as_me:$LINENO: result: $ac_res" >&5
+$as_echo "$ac_res" >&6; }
+
+fi
+as_val=`eval 'as_val=${'$as_ac_Header'}
+                $as_echo "$as_val"'`
+   if test "x$as_val" = x""yes; then
+  cat >>confdefs.h <<_ACEOF
+#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+
+done
+
+fi
+
+
+. ${srcdir}/../../bfd/configure.host
+
+
+
+USE_MAINTAINER_MODE=no
+# Check whether --enable-maintainer-mode was given.
+if test "${enable_maintainer_mode+set}" = set; then
+  enableval=$enable_maintainer_mode; case "${enableval}" in
+  yes) MAINT="" USE_MAINTAINER_MODE=yes ;;
+  no)  MAINT="#" ;;
+  *)   { { $as_echo "$as_me:$LINENO: error: \"--enable-maintainer-mode does not take a value\"" >&5
+$as_echo "$as_me: error: \"--enable-maintainer-mode does not take a value\"" >&2;}
+   { (exit 1); exit 1; }; }; MAINT="#" ;;
+esac
+if test x"$silent" != x"yes" && test x"$MAINT" = x""; then
+  echo "Setting maintainer mode" 6>&1
+fi
+else
+  MAINT="#"
+fi
+
+
+
+# Check whether --enable-sim-bswap was given.
+if test "${enable_sim_bswap+set}" = set; then
+  enableval=$enable_sim_bswap; case "${enableval}" in
+  yes) sim_bswap="-DWITH_BSWAP=1 -DUSE_BSWAP=1";;
+  no)  sim_bswap="-DWITH_BSWAP=0";;
+  *)   { { $as_echo "$as_me:$LINENO: error: \"--enable-sim-bswap does not take a value\"" >&5
+$as_echo "$as_me: error: \"--enable-sim-bswap does not take a value\"" >&2;}
+   { (exit 1); exit 1; }; }; sim_bswap="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_bswap" != x""; then
+  echo "Setting bswap flags = $sim_bswap" 6>&1
+fi
+else
+  sim_bswap=""
+fi
+
+
+
+# Check whether --enable-sim-cflags was given.
+if test "${enable_sim_cflags+set}" = set; then
+  enableval=$enable_sim_cflags; case "${enableval}" in
+  yes)  sim_cflags="-O2 -fomit-frame-pointer";;
+  trace) { { $as_echo "$as_me:$LINENO: error: \"Please use --enable-sim-debug instead.\"" >&5
+$as_echo "$as_me: error: \"Please use --enable-sim-debug instead.\"" >&2;}
+   { (exit 1); exit 1; }; }; sim_cflags="";;
+  no)   sim_cflags="";;
+  *)    sim_cflags=`echo "${enableval}" | sed -e "s/,/ /g"`;;
+esac
+if test x"$silent" != x"yes" && test x"$sim_cflags" != x""; then
+  echo "Setting sim cflags = $sim_cflags" 6>&1
+fi
+else
+  sim_cflags=""
+fi
+
+
+
+# Check whether --enable-sim-debug was given.
+if test "${enable_sim_debug+set}" = set; then
+  enableval=$enable_sim_debug; case "${enableval}" in
+  yes) sim_debug="-DDEBUG=7 -DWITH_DEBUG=7";;
+  no)  sim_debug="-DDEBUG=0 -DWITH_DEBUG=0";;
+  *)   sim_debug="-DDEBUG='(${enableval})' -DWITH_DEBUG='(${enableval})'";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_debug" != x""; then
+  echo "Setting sim debug = $sim_debug" 6>&1
+fi
+else
+  sim_debug=""
+fi
+
+
+
+# Check whether --enable-sim-stdio was given.
+if test "${enable_sim_stdio+set}" = set; then
+  enableval=$enable_sim_stdio; case "${enableval}" in
+  yes) sim_stdio="-DWITH_STDIO=DO_USE_STDIO";;
+  no)  sim_stdio="-DWITH_STDIO=DONT_USE_STDIO";;
+  *)   { { $as_echo "$as_me:$LINENO: error: \"Unknown value $enableval passed to --enable-sim-stdio\"" >&5
+$as_echo "$as_me: error: \"Unknown value $enableval passed to --enable-sim-stdio\"" >&2;}
+   { (exit 1); exit 1; }; }; sim_stdio="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_stdio" != x""; then
+  echo "Setting stdio flags = $sim_stdio" 6>&1
+fi
+else
+  sim_stdio=""
+fi
+
+
+
+# Check whether --enable-sim-trace was given.
+if test "${enable_sim_trace+set}" = set; then
+  enableval=$enable_sim_trace; case "${enableval}" in
+  yes) sim_trace="-DTRACE=1 -DWITH_TRACE=-1";;
+  no)  sim_trace="-DTRACE=0 -DWITH_TRACE=0";;
+  [-0-9]*)
+       sim_trace="-DTRACE='(${enableval})' -DWITH_TRACE='(${enableval})'";;
+  [a-z]*)
+       sim_trace=""
+       for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
+         if test x"$sim_trace" = x; then
+           sim_trace="-DWITH_TRACE='(TRACE_$x"
+         else
+           sim_trace="${sim_trace}|TRACE_$x"
+         fi
+       done
+       sim_trace="$sim_trace)'" ;;
+esac
+if test x"$silent" != x"yes" && test x"$sim_trace" != x""; then
+  echo "Setting sim trace = $sim_trace" 6>&1
+fi
+else
+  sim_trace=""
+fi
+
+
+
+# Check whether --enable-sim-profile was given.
+if test "${enable_sim_profile+set}" = set; then
+  enableval=$enable_sim_profile; case "${enableval}" in
+  yes) sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1";;
+  no)  sim_profile="-DPROFILE=0 -DWITH_PROFILE=0";;
+  [-0-9]*)
+       sim_profile="-DPROFILE='(${enableval})' -DWITH_PROFILE='(${enableval})'";;
+  [a-z]*)
+       sim_profile=""
+       for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
+         if test x"$sim_profile" = x; then
+           sim_profile="-DWITH_PROFILE='(PROFILE_$x"
+         else
+           sim_profile="${sim_profile}|PROFILE_$x"
+         fi
+       done
+       sim_profile="$sim_profile)'" ;;
+esac
+if test x"$silent" != x"yes" && test x"$sim_profile" != x""; then
+  echo "Setting sim profile = $sim_profile" 6>&1
+fi
+else
+  sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1"
+fi
+
+
+
+
+# Check whether --with-pkgversion was given.
+if test "${with_pkgversion+set}" = set; then
+  withval=$with_pkgversion; case "$withval" in
+      yes) { { $as_echo "$as_me:$LINENO: error: package version not specified" >&5
+$as_echo "$as_me: error: package version not specified" >&2;}
+   { (exit 1); exit 1; }; } ;;
+      no)  PKGVERSION= ;;
+      *)   PKGVERSION="($withval) " ;;
+     esac
+else
+  PKGVERSION="(GDB) "
+
+fi
+
+
+
+
+
+# Check whether --with-bugurl was given.
+if test "${with_bugurl+set}" = set; then
+  withval=$with_bugurl; case "$withval" in
+      yes) { { $as_echo "$as_me:$LINENO: error: bug URL not specified" >&5
+$as_echo "$as_me: error: bug URL not specified" >&2;}
+   { (exit 1); exit 1; }; } ;;
+      no)  BUGURL=
+          ;;
+      *)   BUGURL="$withval"
+          ;;
+     esac
+else
+  BUGURL="http://www.gnu.org/software/gdb/bugs/"
+
+fi
+
+  case ${BUGURL} in
+  "")
+    REPORT_BUGS_TO=
+    REPORT_BUGS_TEXI=
+    ;;
+  *)
+    REPORT_BUGS_TO="<$BUGURL>"
+    REPORT_BUGS_TEXI=@uref{`echo "$BUGURL" | sed 's/@/@@/g'`}
+    ;;
+  esac;
+
+
+
+
+cat >>confdefs.h <<_ACEOF
+#define PKGVERSION "$PKGVERSION"
+_ACEOF
+
+
+cat >>confdefs.h <<_ACEOF
+#define REPORT_BUGS_TO "$REPORT_BUGS_TO"
+_ACEOF
+
+
+{ $as_echo "$as_me:$LINENO: checking return type of signal handlers" >&5
+$as_echo_n "checking return type of signal handlers... " >&6; }
+if test "${ac_cv_type_signal+set}" = set; then
+  $as_echo_n "(cached) " >&6
+else
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#include <sys/types.h>
+#include <signal.h>
+
+int
+main ()
+{
+return *(signal (0, 0)) (0) == 1;
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (ac_try="$ac_compile"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_compile") 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } && {
+        test -z "$ac_c_werror_flag" ||
+        test ! -s conftest.err
+       } && test -s conftest.$ac_objext; then
+  ac_cv_type_signal=int
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+       ac_cv_type_signal=void
+fi
+
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+{ $as_echo "$as_me:$LINENO: result: $ac_cv_type_signal" >&5
+$as_echo "$ac_cv_type_signal" >&6; }
+
+cat >>confdefs.h <<_ACEOF
+#define RETSIGTYPE $ac_cv_type_signal
+_ACEOF
+
+
+
+
+
+sim_link_files=
+sim_link_links=
+
+sim_link_links=tconfig.h
+if test -f ${srcdir}/tconfig.in
+then
+  sim_link_files=tconfig.in
+else
+  sim_link_files=../common/tconfig.in
+fi
+
+# targ-vals.def points to the libc macro description file.
+case "${target}" in
+*-*-*) TARG_VALS_DEF=../common/nltvals.def ;;
+esac
+sim_link_files="${sim_link_files} ${TARG_VALS_DEF}"
+sim_link_links="${sim_link_links} targ-vals.def"
+
+
+
+for ac_header in unistd.h
+do
+as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh`
+if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then
+  { $as_echo "$as_me:$LINENO: checking for $ac_header" >&5
+$as_echo_n "checking for $ac_header... " >&6; }
+if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then
+  $as_echo_n "(cached) " >&6
+fi
+ac_res=`eval 'as_val=${'$as_ac_Header'}
+                $as_echo "$as_val"'`
+              { $as_echo "$as_me:$LINENO: result: $ac_res" >&5
+$as_echo "$ac_res" >&6; }
+else
+  # Is the header compilable?
+{ $as_echo "$as_me:$LINENO: checking $ac_header usability" >&5
+$as_echo_n "checking $ac_header usability... " >&6; }
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+$ac_includes_default
+#include <$ac_header>
+_ACEOF
+rm -f conftest.$ac_objext
+if { (ac_try="$ac_compile"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_compile") 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } && {
+        test -z "$ac_c_werror_flag" ||
+        test ! -s conftest.err
+       } && test -s conftest.$ac_objext; then
+  ac_header_compiler=yes
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+       ac_header_compiler=no
+fi
+
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+{ $as_echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
+$as_echo "$ac_header_compiler" >&6; }
+
+# Is the header present?
+{ $as_echo "$as_me:$LINENO: checking $ac_header presence" >&5
+$as_echo_n "checking $ac_header presence... " >&6; }
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#include <$ac_header>
+_ACEOF
+if { (ac_try="$ac_cpp conftest.$ac_ext"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\""
+$as_echo "$ac_try_echo") >&5
+  (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } >/dev/null && {
+        test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" ||
+        test ! -s conftest.err
+       }; then
+  ac_header_preproc=yes
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+  ac_header_preproc=no
+fi
+
+rm -f conftest.err conftest.$ac_ext
+{ $as_echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
+$as_echo "$ac_header_preproc" >&6; }
+
+# So?  What about this header?
+case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
+  yes:no: )
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
+$as_echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
+$as_echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
+    ac_header_preproc=yes
+    ;;
+  no:yes:* )
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
+$as_echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header:     check for missing prerequisite headers?" >&5
+$as_echo "$as_me: WARNING: $ac_header:     check for missing prerequisite headers?" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
+$as_echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&5
+$as_echo "$as_me: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
+$as_echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
+    { $as_echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
+$as_echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
+
+    ;;
+esac
+{ $as_echo "$as_me:$LINENO: checking for $ac_header" >&5
+$as_echo_n "checking for $ac_header... " >&6; }
+if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then
+  $as_echo_n "(cached) " >&6
+else
+  eval "$as_ac_Header=\$ac_header_preproc"
+fi
+ac_res=`eval 'as_val=${'$as_ac_Header'}
+                $as_echo "$as_val"'`
+              { $as_echo "$as_me:$LINENO: result: $ac_res" >&5
+$as_echo "$ac_res" >&6; }
+
+fi
+as_val=`eval 'as_val=${'$as_ac_Header'}
+                $as_echo "$as_val"'`
+   if test "x$as_val" = x""yes; then
+  cat >>confdefs.h <<_ACEOF
+#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+
+done
+
+
+
+ac_sources="$sim_link_files"
+ac_dests="$sim_link_links"
+while test -n "$ac_sources"; do
+  set $ac_dests; ac_dest=$1; shift; ac_dests=$*
+  set $ac_sources; ac_source=$1; shift; ac_sources=$*
+  ac_config_links_1="$ac_config_links_1 $ac_dest:$ac_source"
+done
+ac_config_links="$ac_config_links $ac_config_links_1"
+
+cgen_breaks=""
+if grep CGEN_MAINT $srcdir/Makefile.in >/dev/null; then
+cgen_breaks="break cgen_rtx_error";
+fi
+
+ac_config_files="$ac_config_files Makefile.sim:Makefile.in"
+
+ac_config_files="$ac_config_files Make-common.sim:../common/Make-common.in"
+
+ac_config_files="$ac_config_files .gdbinit:../common/gdbinit.in"
+
+ac_config_commands="$ac_config_commands Makefile"
+
+ac_config_commands="$ac_config_commands stamp-h"
+
+cat >confcache <<\_ACEOF
+# This file is a shell script that caches the results of configure
+# tests run on this system so they can be shared between configure
+# scripts and configure runs, see configure's option --config-cache.
+# It is not useful on other systems.  If it contains results you don't
+# want to keep, you may remove or edit it.
+#
+# config.status only pays attention to the cache file if you give it
+# the --recheck option to rerun configure.
+#
+# `ac_cv_env_foo' variables (set or unset) will be overridden when
+# loading this file, other *unset* `ac_cv_foo' will be assigned the
+# following values.
+
+_ACEOF
+
+# The following way of writing the cache mishandles newlines in values,
+# but we know of no workaround that is simple, portable, and efficient.
+# So, we kill variables containing newlines.
+# Ultrix sh set writes to stderr and can't be redirected directly,
+# and sets the high bit in the cache file unless we assign to the vars.
+(
+  for ac_var in `(set) 2>&1 | sed -n 's/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'`; do
+    eval ac_val=\$$ac_var
+    case $ac_val in #(
+    *${as_nl}*)
+      case $ac_var in #(
+      *_cv_*) { $as_echo "$as_me:$LINENO: WARNING: cache variable $ac_var contains a newline" >&5
+$as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;;
+      esac
+      case $ac_var in #(
+      _ | IFS | as_nl) ;; #(
+      BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #(
+      *) $as_unset $ac_var ;;
+      esac ;;
+    esac
+  done
+
+  (set) 2>&1 |
+    case $as_nl`(ac_space=' '; set) 2>&1` in #(
+    *${as_nl}ac_space=\ *)
+      # `set' does not quote correctly, so add quotes (double-quote
+      # substitution turns \\\\ into \\, and sed turns \\ into \).
+      sed -n \
+       "s/'/'\\\\''/g;
+         s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p"
+      ;; #(
+    *)
+      # `set' quotes correctly as required by POSIX, so do not add quotes.
+      sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p"
+      ;;
+    esac |
+    sort
+) |
+  sed '
+     /^ac_cv_env_/b end
+     t clear
+     :clear
+     s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/
+     t end
+     s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/
+     :end' >>confcache
+if diff "$cache_file" confcache >/dev/null 2>&1; then :; else
+  if test -w "$cache_file"; then
+    test "x$cache_file" != "x/dev/null" &&
+      { $as_echo "$as_me:$LINENO: updating cache $cache_file" >&5
+$as_echo "$as_me: updating cache $cache_file" >&6;}
+    cat confcache >$cache_file
+  else
+    { $as_echo "$as_me:$LINENO: not updating unwritable cache $cache_file" >&5
+$as_echo "$as_me: not updating unwritable cache $cache_file" >&6;}
+  fi
+fi
+rm -f confcache
+
+test "x$prefix" = xNONE && prefix=$ac_default_prefix
+# Let make expand exec_prefix.
+test "x$exec_prefix" = xNONE && exec_prefix='${prefix}'
+
+DEFS=-DHAVE_CONFIG_H
+
+ac_libobjs=
+ac_ltlibobjs=
+for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue
+  # 1. Remove the extension, and $U if already installed.
+  ac_script='s/\$U\././;s/\.o$//;s/\.obj$//'
+  ac_i=`$as_echo "$ac_i" | sed "$ac_script"`
+  # 2. Prepend LIBOBJDIR.  When used with automake>=1.10 LIBOBJDIR
+  #    will be set to the directory where LIBOBJS objects are built.
+  ac_libobjs="$ac_libobjs \${LIBOBJDIR}$ac_i\$U.$ac_objext"
+  ac_ltlibobjs="$ac_ltlibobjs \${LIBOBJDIR}$ac_i"'$U.lo'
+done
+LIBOBJS=$ac_libobjs
+
+LTLIBOBJS=$ac_ltlibobjs
+
+
+
+: ${CONFIG_STATUS=./config.status}
+ac_write_fail=0
+ac_clean_files_save=$ac_clean_files
+ac_clean_files="$ac_clean_files $CONFIG_STATUS"
+{ $as_echo "$as_me:$LINENO: creating $CONFIG_STATUS" >&5
+$as_echo "$as_me: creating $CONFIG_STATUS" >&6;}
+cat >$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+#! $SHELL
+# Generated by $as_me.
+# Run this file to recreate the current configuration.
+# Compiler output produced by configure, useful for debugging
+# configure, is in config.log if it exists.
+
+debug=false
+ac_cs_recheck=false
+ac_cs_silent=false
+SHELL=\${CONFIG_SHELL-$SHELL}
+_ACEOF
+
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+## --------------------- ##
+## M4sh Initialization.  ##
+## --------------------- ##
+
+# Be more Bourne compatible
+DUALCASE=1; export DUALCASE # for MKS sh
+if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then
+  emulate sh
+  NULLCMD=:
+  # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which
+  # is contrary to our usage.  Disable this feature.
+  alias -g '${1+"$@"}'='"$@"'
+  setopt NO_GLOB_SUBST
+else
+  case `(set -o) 2>/dev/null` in
+  *posix*) set -o posix ;;
+esac
+
+fi
+
+
+
+
+# PATH needs CR
+# Avoid depending upon Character Ranges.
+as_cr_letters='abcdefghijklmnopqrstuvwxyz'
+as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
+as_cr_Letters=$as_cr_letters$as_cr_LETTERS
+as_cr_digits='0123456789'
+as_cr_alnum=$as_cr_Letters$as_cr_digits
+
+as_nl='
+'
+export as_nl
+# Printing a long string crashes Solaris 7 /usr/bin/printf.
+as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\'
+as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo
+as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo
+if (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then
+  as_echo='printf %s\n'
+  as_echo_n='printf %s'
+else
+  if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then
+    as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"'
+    as_echo_n='/usr/ucb/echo -n'
+  else
+    as_echo_body='eval expr "X$1" : "X\\(.*\\)"'
+    as_echo_n_body='eval
+      arg=$1;
+      case $arg in
+      *"$as_nl"*)
+       expr "X$arg" : "X\\(.*\\)$as_nl";
+       arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;;
+      esac;
+      expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl"
+    '
+    export as_echo_n_body
+    as_echo_n='sh -c $as_echo_n_body as_echo'
+  fi
+  export as_echo_body
+  as_echo='sh -c $as_echo_body as_echo'
+fi
+
+# The user is always right.
+if test "${PATH_SEPARATOR+set}" != set; then
+  PATH_SEPARATOR=:
+  (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && {
+    (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 ||
+      PATH_SEPARATOR=';'
+  }
+fi
+
+# Support unset when possible.
+if ( (MAIL=60; unset MAIL) || exit) >/dev/null 2>&1; then
+  as_unset=unset
+else
+  as_unset=false
+fi
+
+
+# IFS
+# We need space, tab and new line, in precisely that order.  Quoting is
+# there to prevent editors from complaining about space-tab.
+# (If _AS_PATH_WALK were called with IFS unset, it would disable word
+# splitting by setting IFS to empty value.)
+IFS=" ""       $as_nl"
+
+# Find who we are.  Look in the path if we contain no directory separator.
+case $0 in
+  *[\\/]* ) as_myself=$0 ;;
+  *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break
+done
+IFS=$as_save_IFS
+
+     ;;
+esac
+# We did not find ourselves, most probably we were run as `sh COMMAND'
+# in which case we are not to be found in the path.
+if test "x$as_myself" = x; then
+  as_myself=$0
+fi
+if test ! -f "$as_myself"; then
+  $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2
+  { (exit 1); exit 1; }
+fi
+
+# Work around bugs in pre-3.0 UWIN ksh.
+for as_var in ENV MAIL MAILPATH
+do ($as_unset $as_var) >/dev/null 2>&1 && $as_unset $as_var
+done
+PS1='$ '
+PS2='> '
+PS4='+ '
+
+# NLS nuisances.
+LC_ALL=C
+export LC_ALL
+LANGUAGE=C
+export LANGUAGE
+
+# Required to use basename.
+if expr a : '\(a\)' >/dev/null 2>&1 &&
+   test "X`expr 00001 : '.*\(...\)'`" = X001; then
+  as_expr=expr
+else
+  as_expr=false
+fi
+
+if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then
+  as_basename=basename
+else
+  as_basename=false
+fi
+
+
+# Name of the executable.
+as_me=`$as_basename -- "$0" ||
+$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \
+        X"$0" : 'X\(//\)$' \| \
+        X"$0" : 'X\(/\)' \| . 2>/dev/null ||
+$as_echo X/"$0" |
+    sed '/^.*\/\([^/][^/]*\)\/*$/{
+           s//\1/
+           q
+         }
+         /^X\/\(\/\/\)$/{
+           s//\1/
+           q
+         }
+         /^X\/\(\/\).*/{
+           s//\1/
+           q
+         }
+         s/.*/./; q'`
+
+# CDPATH.
+$as_unset CDPATH
+
+
+
+  as_lineno_1=$LINENO
+  as_lineno_2=$LINENO
+  test "x$as_lineno_1" != "x$as_lineno_2" &&
+  test "x`expr $as_lineno_1 + 1`" = "x$as_lineno_2" || {
+
+  # Create $as_me.lineno as a copy of $as_myself, but with $LINENO
+  # uniformly replaced by the line number.  The first 'sed' inserts a
+  # line-number line after each line using $LINENO; the second 'sed'
+  # does the real work.  The second script uses 'N' to pair each
+  # line-number line with the line containing $LINENO, and appends
+  # trailing '-' during substitution so that $LINENO is not a special
+  # case at line end.
+  # (Raja R Harinath suggested sed '=', and Paul Eggert wrote the
+  # scripts with optimization help from Paolo Bonzini.  Blame Lee
+  # E. McMahon (1931-1989) for sed's syntax.  :-)
+  sed -n '
+    p
+    /[$]LINENO/=
+  ' <$as_myself |
+    sed '
+      s/[$]LINENO.*/&-/
+      t lineno
+      b
+      :lineno
+      N
+      :loop
+      s/[$]LINENO\([^'$as_cr_alnum'_].*\n\)\(.*\)/\2\1\2/
+      t loop
+      s/-\n.*//
+    ' >$as_me.lineno &&
+  chmod +x "$as_me.lineno" ||
+    { $as_echo "$as_me: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&2
+   { (exit 1); exit 1; }; }
+
+  # Don't try to exec as it changes $[0], causing all sort of problems
+  # (the dirname of $[0] is not the place where we might find the
+  # original and so on.  Autoconf is especially sensitive to this).
+  . "./$as_me.lineno"
+  # Exit status is that of the last command.
+  exit
+}
+
+
+if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then
+  as_dirname=dirname
+else
+  as_dirname=false
+fi
+
+ECHO_C= ECHO_N= ECHO_T=
+case `echo -n x` in
+-n*)
+  case `echo 'x\c'` in
+  *c*) ECHO_T='        ';;     # ECHO_T is single tab character.
+  *)   ECHO_C='\c';;
+  esac;;
+*)
+  ECHO_N='-n';;
+esac
+if expr a : '\(a\)' >/dev/null 2>&1 &&
+   test "X`expr 00001 : '.*\(...\)'`" = X001; then
+  as_expr=expr
+else
+  as_expr=false
+fi
+
+rm -f conf$$ conf$$.exe conf$$.file
+if test -d conf$$.dir; then
+  rm -f conf$$.dir/conf$$.file
+else
+  rm -f conf$$.dir
+  mkdir conf$$.dir 2>/dev/null
+fi
+if (echo >conf$$.file) 2>/dev/null; then
+  if ln -s conf$$.file conf$$ 2>/dev/null; then
+    as_ln_s='ln -s'
+    # ... but there are two gotchas:
+    # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail.
+    # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable.
+    # In both cases, we have to default to `cp -p'.
+    ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe ||
+      as_ln_s='cp -p'
+  elif ln conf$$.file conf$$ 2>/dev/null; then
+    as_ln_s=ln
+  else
+    as_ln_s='cp -p'
+  fi
+else
+  as_ln_s='cp -p'
+fi
+rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file
+rmdir conf$$.dir 2>/dev/null
+
+if mkdir -p . 2>/dev/null; then
+  as_mkdir_p=:
+else
+  test -d ./-p && rmdir ./-p
+  as_mkdir_p=false
+fi
+
+if test -x / >/dev/null 2>&1; then
+  as_test_x='test -x'
+else
+  if ls -dL / >/dev/null 2>&1; then
+    as_ls_L_option=L
+  else
+    as_ls_L_option=
+  fi
+  as_test_x='
+    eval sh -c '\''
+      if test -d "$1"; then
+       test -d "$1/.";
+      else
+       case $1 in
+       -*)set "./$1";;
+       esac;
+       case `ls -ld'$as_ls_L_option' "$1" 2>/dev/null` in
+       ???[sx]*):;;*)false;;esac;fi
+    '\'' sh
+  '
+fi
+as_executable_p=$as_test_x
+
+# Sed expression to map a string onto a valid CPP name.
+as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'"
+
+# Sed expression to map a string onto a valid variable name.
+as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'"
+
+
+exec 6>&1
+
+# Save the log message, to keep $[0] and so on meaningful, and to
+# report actual input values of CONFIG_FILES etc. instead of their
+# values after options handling.
+ac_log="
+This file was extended by $as_me, which was
+generated by GNU Autoconf 2.63.  Invocation command line was
+
+  CONFIG_FILES    = $CONFIG_FILES
+  CONFIG_HEADERS  = $CONFIG_HEADERS
+  CONFIG_LINKS    = $CONFIG_LINKS
+  CONFIG_COMMANDS = $CONFIG_COMMANDS
+  $ $0 $@
+
+on `(hostname || uname -n) 2>/dev/null | sed 1q`
+"
+
+_ACEOF
+
+case $ac_config_files in *"
+"*) set x $ac_config_files; shift; ac_config_files=$*;;
+esac
+
+case $ac_config_headers in *"
+"*) set x $ac_config_headers; shift; ac_config_headers=$*;;
+esac
+
+
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+# Files that config.status was made for.
+config_files="$ac_config_files"
+config_headers="$ac_config_headers"
+config_links="$ac_config_links"
+config_commands="$ac_config_commands"
+
+_ACEOF
+
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+ac_cs_usage="\
+\`$as_me' instantiates files from templates according to the
+current configuration.
+
+Usage: $0 [OPTION]... [FILE]...
+
+  -h, --help       print this help, then exit
+  -V, --version    print version number and configuration settings, then exit
+  -q, --quiet, --silent
+                   do not print progress messages
+  -d, --debug      don't remove temporary files
+      --recheck    update $as_me by reconfiguring in the same conditions
+      --file=FILE[:TEMPLATE]
+                   instantiate the configuration file FILE
+      --header=FILE[:TEMPLATE]
+                   instantiate the configuration header FILE
+
+Configuration files:
+$config_files
+
+Configuration headers:
+$config_headers
+
+Configuration links:
+$config_links
+
+Configuration commands:
+$config_commands
+
+Report bugs to <bug-autoconf@gnu.org>."
+
+_ACEOF
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+ac_cs_version="\\
+config.status
+configured by $0, generated by GNU Autoconf 2.63,
+  with options \\"`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\"
+
+Copyright (C) 2008 Free Software Foundation, Inc.
+This config.status script is free software; the Free Software Foundation
+gives unlimited permission to copy, distribute and modify it."
+
+ac_pwd='$ac_pwd'
+srcdir='$srcdir'
+INSTALL='$INSTALL'
+test -n "\$AWK" || AWK=awk
+_ACEOF
+
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+# The default lists apply if the user does not specify any file.
+ac_need_defaults=:
+while test $# != 0
+do
+  case $1 in
+  --*=*)
+    ac_option=`expr "X$1" : 'X\([^=]*\)='`
+    ac_optarg=`expr "X$1" : 'X[^=]*=\(.*\)'`
+    ac_shift=:
+    ;;
+  *)
+    ac_option=$1
+    ac_optarg=$2
+    ac_shift=shift
+    ;;
+  esac
+
+  case $ac_option in
+  # Handling of the options.
+  -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r)
+    ac_cs_recheck=: ;;
+  --version | --versio | --versi | --vers | --ver | --ve | --v | -V )
+    $as_echo "$ac_cs_version"; exit ;;
+  --debug | --debu | --deb | --de | --d | -d )
+    debug=: ;;
+  --file | --fil | --fi | --f )
+    $ac_shift
+    case $ac_optarg in
+    *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;;
+    esac
+    CONFIG_FILES="$CONFIG_FILES '$ac_optarg'"
+    ac_need_defaults=false;;
+  --header | --heade | --head | --hea )
+    $ac_shift
+    case $ac_optarg in
+    *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;;
+    esac
+    CONFIG_HEADERS="$CONFIG_HEADERS '$ac_optarg'"
+    ac_need_defaults=false;;
+  --he | --h)
+    # Conflict between --help and --header
+    { $as_echo "$as_me: error: ambiguous option: $1
+Try \`$0 --help' for more information." >&2
+   { (exit 1); exit 1; }; };;
+  --help | --hel | -h )
+    $as_echo "$ac_cs_usage"; exit ;;
+  -q | -quiet | --quiet | --quie | --qui | --qu | --q \
+  | -silent | --silent | --silen | --sile | --sil | --si | --s)
+    ac_cs_silent=: ;;
+
+  # This is an error.
+  -*) { $as_echo "$as_me: error: unrecognized option: $1
+Try \`$0 --help' for more information." >&2
+   { (exit 1); exit 1; }; } ;;
+
+  *) ac_config_targets="$ac_config_targets $1"
+     ac_need_defaults=false ;;
+
+  esac
+  shift
+done
+
+ac_configure_extra_args=
+
+if $ac_cs_silent; then
+  exec 6>/dev/null
+  ac_configure_extra_args="$ac_configure_extra_args --silent"
+fi
+
+_ACEOF
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+if \$ac_cs_recheck; then
+  set X '$SHELL' '$0' $ac_configure_args \$ac_configure_extra_args --no-create --no-recursion
+  shift
+  \$as_echo "running CONFIG_SHELL=$SHELL \$*" >&6
+  CONFIG_SHELL='$SHELL'
+  export CONFIG_SHELL
+  exec "\$@"
+fi
+
+_ACEOF
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+exec 5>>config.log
+{
+  echo
+  sed 'h;s/./-/g;s/^.../## /;s/...$/ ##/;p;x;p;x' <<_ASBOX
+## Running $as_me. ##
+_ASBOX
+  $as_echo "$ac_log"
+} >&5
+
+_ACEOF
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+_ACEOF
+
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+
+# Handling of arguments.
+for ac_config_target in $ac_config_targets
+do
+  case $ac_config_target in
+    "config.h") CONFIG_HEADERS="$CONFIG_HEADERS config.h:config.in" ;;
+    "$ac_config_links_1") CONFIG_LINKS="$CONFIG_LINKS $ac_config_links_1" ;;
+    "Makefile.sim") CONFIG_FILES="$CONFIG_FILES Makefile.sim:Makefile.in" ;;
+    "Make-common.sim") CONFIG_FILES="$CONFIG_FILES Make-common.sim:../common/Make-common.in" ;;
+    ".gdbinit") CONFIG_FILES="$CONFIG_FILES .gdbinit:../common/gdbinit.in" ;;
+    "Makefile") CONFIG_COMMANDS="$CONFIG_COMMANDS Makefile" ;;
+    "stamp-h") CONFIG_COMMANDS="$CONFIG_COMMANDS stamp-h" ;;
+
+  *) { { $as_echo "$as_me:$LINENO: error: invalid argument: $ac_config_target" >&5
+$as_echo "$as_me: error: invalid argument: $ac_config_target" >&2;}
+   { (exit 1); exit 1; }; };;
+  esac
+done
+
+
+# If the user did not use the arguments to specify the items to instantiate,
+# then the envvar interface is used.  Set only those that are not.
+# We use the long form for the default assignment because of an extremely
+# bizarre bug on SunOS 4.1.3.
+if $ac_need_defaults; then
+  test "${CONFIG_FILES+set}" = set || CONFIG_FILES=$config_files
+  test "${CONFIG_HEADERS+set}" = set || CONFIG_HEADERS=$config_headers
+  test "${CONFIG_LINKS+set}" = set || CONFIG_LINKS=$config_links
+  test "${CONFIG_COMMANDS+set}" = set || CONFIG_COMMANDS=$config_commands
+fi
+
+# Have a temporary directory for convenience.  Make it in the build tree
+# simply because there is no reason against having it here, and in addition,
+# creating and moving files from /tmp can sometimes cause problems.
+# Hook for its removal unless debugging.
+# Note that there is a small window in which the directory will not be cleaned:
+# after its creation but before its name has been assigned to `$tmp'.
+$debug ||
+{
+  tmp=
+  trap 'exit_status=$?
+  { test -z "$tmp" || test ! -d "$tmp" || rm -fr "$tmp"; } && exit $exit_status
+' 0
+  trap '{ (exit 1); exit 1; }' 1 2 13 15
+}
+# Create a (secure) tmp directory for tmp files.
+
+{
+  tmp=`(umask 077 && mktemp -d "./confXXXXXX") 2>/dev/null` &&
+  test -n "$tmp" && test -d "$tmp"
+}  ||
+{
+  tmp=./conf$$-$RANDOM
+  (umask 077 && mkdir "$tmp")
+} ||
+{
+   $as_echo "$as_me: cannot create a temporary directory in ." >&2
+   { (exit 1); exit 1; }
+}
+
+# Set up the scripts for CONFIG_FILES section.
+# No need to generate them if there are no CONFIG_FILES.
+# This happens for instance with `./config.status config.h'.
+if test -n "$CONFIG_FILES"; then
+
+
+ac_cr='\r'
+ac_cs_awk_cr=`$AWK 'BEGIN { print "a\rb" }' </dev/null 2>/dev/null`
+if test "$ac_cs_awk_cr" = "a${ac_cr}b"; then
+  ac_cs_awk_cr='\\r'
+else
+  ac_cs_awk_cr=$ac_cr
+fi
+
+echo 'BEGIN {' >"$tmp/subs1.awk" &&
+_ACEOF
+
+
+{
+  echo "cat >conf$$subs.awk <<_ACEOF" &&
+  echo "$ac_subst_vars" | sed 's/.*/&!$&$ac_delim/' &&
+  echo "_ACEOF"
+} >conf$$subs.sh ||
+  { { $as_echo "$as_me:$LINENO: error: could not make $CONFIG_STATUS" >&5
+$as_echo "$as_me: error: could not make $CONFIG_STATUS" >&2;}
+   { (exit 1); exit 1; }; }
+ac_delim_num=`echo "$ac_subst_vars" | grep -c '$'`
+ac_delim='%!_!# '
+for ac_last_try in false false false false false :; do
+  . ./conf$$subs.sh ||
+    { { $as_echo "$as_me:$LINENO: error: could not make $CONFIG_STATUS" >&5
+$as_echo "$as_me: error: could not make $CONFIG_STATUS" >&2;}
+   { (exit 1); exit 1; }; }
+
+  ac_delim_n=`sed -n "s/.*$ac_delim\$/X/p" conf$$subs.awk | grep -c X`
+  if test $ac_delim_n = $ac_delim_num; then
+    break
+  elif $ac_last_try; then
+    { { $as_echo "$as_me:$LINENO: error: could not make $CONFIG_STATUS" >&5
+$as_echo "$as_me: error: could not make $CONFIG_STATUS" >&2;}
+   { (exit 1); exit 1; }; }
+  else
+    ac_delim="$ac_delim!$ac_delim _$ac_delim!! "
+  fi
+done
+rm -f conf$$subs.sh
+
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+cat >>"\$tmp/subs1.awk" <<\\_ACAWK &&
+_ACEOF
+sed -n '
+h
+s/^/S["/; s/!.*/"]=/
+p
+g
+s/^[^!]*!//
+:repl
+t repl
+s/'"$ac_delim"'$//
+t delim
+:nl
+h
+s/\(.\{148\}\).*/\1/
+t more1
+s/["\\]/\\&/g; s/^/"/; s/$/\\n"\\/
+p
+n
+b repl
+:more1
+s/["\\]/\\&/g; s/^/"/; s/$/"\\/
+p
+g
+s/.\{148\}//
+t nl
+:delim
+h
+s/\(.\{148\}\).*/\1/
+t more2
+s/["\\]/\\&/g; s/^/"/; s/$/"/
+p
+b
+:more2
+s/["\\]/\\&/g; s/^/"/; s/$/"\\/
+p
+g
+s/.\{148\}//
+t delim
+' <conf$$subs.awk | sed '
+/^[^""]/{
+  N
+  s/\n//
+}
+' >>$CONFIG_STATUS || ac_write_fail=1
+rm -f conf$$subs.awk
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+_ACAWK
+cat >>"\$tmp/subs1.awk" <<_ACAWK &&
+  for (key in S) S_is_set[key] = 1
+  FS = "\a"
+
+}
+{
+  line = $ 0
+  nfields = split(line, field, "@")
+  substed = 0
+  len = length(field[1])
+  for (i = 2; i < nfields; i++) {
+    key = field[i]
+    keylen = length(key)
+    if (S_is_set[key]) {
+      value = S[key]
+      line = substr(line, 1, len) "" value "" substr(line, len + keylen + 3)
+      len += length(value) + length(field[++i])
+      substed = 1
+    } else
+      len += 1 + keylen
+  }
+
+  print line
+}
+
+_ACAWK
+_ACEOF
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+if sed "s/$ac_cr//" < /dev/null > /dev/null 2>&1; then
+  sed "s/$ac_cr\$//; s/$ac_cr/$ac_cs_awk_cr/g"
+else
+  cat
+fi < "$tmp/subs1.awk" > "$tmp/subs.awk" \
+  || { { $as_echo "$as_me:$LINENO: error: could not setup config files machinery" >&5
+$as_echo "$as_me: error: could not setup config files machinery" >&2;}
+   { (exit 1); exit 1; }; }
+_ACEOF
+
+# VPATH may cause trouble with some makes, so we remove $(srcdir),
+# ${srcdir} and @srcdir@ from VPATH if srcdir is ".", strip leading and
+# trailing colons and then remove the whole line if VPATH becomes empty
+# (actually we leave an empty line to preserve line numbers).
+if test "x$srcdir" = x.; then
+  ac_vpsub='/^[         ]*VPATH[        ]*=/{
+s/:*\$(srcdir):*/:/
+s/:*\${srcdir}:*/:/
+s/:*@srcdir@:*/:/
+s/^\([^=]*=[    ]*\):*/\1/
+s/:*$//
+s/^[^=]*=[      ]*$//
+}'
+fi
+
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+fi # test -n "$CONFIG_FILES"
+
+# Set up the scripts for CONFIG_HEADERS section.
+# No need to generate them if there are no CONFIG_HEADERS.
+# This happens for instance with `./config.status Makefile'.
+if test -n "$CONFIG_HEADERS"; then
+cat >"$tmp/defines.awk" <<\_ACAWK ||
+BEGIN {
+_ACEOF
+
+# Transform confdefs.h into an awk script `defines.awk', embedded as
+# here-document in config.status, that substitutes the proper values into
+# config.h.in to produce config.h.
+
+# Create a delimiter string that does not exist in confdefs.h, to ease
+# handling of long lines.
+ac_delim='%!_!# '
+for ac_last_try in false false :; do
+  ac_t=`sed -n "/$ac_delim/p" confdefs.h`
+  if test -z "$ac_t"; then
+    break
+  elif $ac_last_try; then
+    { { $as_echo "$as_me:$LINENO: error: could not make $CONFIG_HEADERS" >&5
+$as_echo "$as_me: error: could not make $CONFIG_HEADERS" >&2;}
+   { (exit 1); exit 1; }; }
+  else
+    ac_delim="$ac_delim!$ac_delim _$ac_delim!! "
+  fi
+done
+
+# For the awk script, D is an array of macro values keyed by name,
+# likewise P contains macro parameters if any.  Preserve backslash
+# newline sequences.
+
+ac_word_re=[_$as_cr_Letters][_$as_cr_alnum]*
+sed -n '
+s/.\{148\}/&'"$ac_delim"'/g
+t rset
+:rset
+s/^[    ]*#[    ]*define[       ][      ]*/ /
+t def
+d
+:def
+s/\\$//
+t bsnl
+s/["\\]/\\&/g
+s/^ \('"$ac_word_re"'\)\(([^()]*)\)[    ]*\(.*\)/P["\1"]="\2"\
+D["\1"]=" \3"/p
+s/^ \('"$ac_word_re"'\)[        ]*\(.*\)/D["\1"]=" \2"/p
+d
+:bsnl
+s/["\\]/\\&/g
+s/^ \('"$ac_word_re"'\)\(([^()]*)\)[    ]*\(.*\)/P["\1"]="\2"\
+D["\1"]=" \3\\\\\\n"\\/p
+t cont
+s/^ \('"$ac_word_re"'\)[        ]*\(.*\)/D["\1"]=" \2\\\\\\n"\\/p
+t cont
+d
+:cont
+n
+s/.\{148\}/&'"$ac_delim"'/g
+t clear
+:clear
+s/\\$//
+t bsnlc
+s/["\\]/\\&/g; s/^/"/; s/$/"/p
+d
+:bsnlc
+s/["\\]/\\&/g; s/^/"/; s/$/\\\\\\n"\\/p
+b cont
+' <confdefs.h | sed '
+s/'"$ac_delim"'/"\\\
+"/g' >>$CONFIG_STATUS || ac_write_fail=1
+
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+  for (key in D) D_is_set[key] = 1
+  FS = "\a"
+}
+/^[\t ]*#[\t ]*(define|undef)[\t ]+$ac_word_re([\t (]|\$)/ {
+  line = \$ 0
+  split(line, arg, " ")
+  if (arg[1] == "#") {
+    defundef = arg[2]
+    mac1 = arg[3]
+  } else {
+    defundef = substr(arg[1], 2)
+    mac1 = arg[2]
+  }
+  split(mac1, mac2, "(") #)
+  macro = mac2[1]
+  prefix = substr(line, 1, index(line, defundef) - 1)
+  if (D_is_set[macro]) {
+    # Preserve the white space surrounding the "#".
+    print prefix "define", macro P[macro] D[macro]
+    next
+  } else {
+    # Replace #undef with comments.  This is necessary, for example,
+    # in the case of _POSIX_SOURCE, which is predefined and required
+    # on some systems where configure will not decide to define it.
+    if (defundef == "undef") {
+      print "/*", prefix defundef, macro, "*/"
+      next
+    }
+  }
+}
+{ print }
+_ACAWK
+_ACEOF
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+  { { $as_echo "$as_me:$LINENO: error: could not setup config headers machinery" >&5
+$as_echo "$as_me: error: could not setup config headers machinery" >&2;}
+   { (exit 1); exit 1; }; }
+fi # test -n "$CONFIG_HEADERS"
+
+
+eval set X "  :F $CONFIG_FILES  :H $CONFIG_HEADERS  :L $CONFIG_LINKS  :C $CONFIG_COMMANDS"
+shift
+for ac_tag
+do
+  case $ac_tag in
+  :[FHLC]) ac_mode=$ac_tag; continue;;
+  esac
+  case $ac_mode$ac_tag in
+  :[FHL]*:*);;
+  :L* | :C*:*) { { $as_echo "$as_me:$LINENO: error: invalid tag $ac_tag" >&5
+$as_echo "$as_me: error: invalid tag $ac_tag" >&2;}
+   { (exit 1); exit 1; }; };;
+  :[FH]-) ac_tag=-:-;;
+  :[FH]*) ac_tag=$ac_tag:$ac_tag.in;;
+  esac
+  ac_save_IFS=$IFS
+  IFS=:
+  set x $ac_tag
+  IFS=$ac_save_IFS
+  shift
+  ac_file=$1
+  shift
+
+  case $ac_mode in
+  :L) ac_source=$1;;
+  :[FH])
+    ac_file_inputs=
+    for ac_f
+    do
+      case $ac_f in
+      -) ac_f="$tmp/stdin";;
+      *) # Look for the file first in the build tree, then in the source tree
+        # (if the path is not absolute).  The absolute path cannot be DOS-style,
+        # because $ac_f cannot contain `:'.
+        test -f "$ac_f" ||
+          case $ac_f in
+          [\\/$]*) false;;
+          *) test -f "$srcdir/$ac_f" && ac_f="$srcdir/$ac_f";;
+          esac ||
+          { { $as_echo "$as_me:$LINENO: error: cannot find input file: $ac_f" >&5
+$as_echo "$as_me: error: cannot find input file: $ac_f" >&2;}
+   { (exit 1); exit 1; }; };;
+      esac
+      case $ac_f in *\'*) ac_f=`$as_echo "$ac_f" | sed "s/'/'\\\\\\\\''/g"`;; esac
+      ac_file_inputs="$ac_file_inputs '$ac_f'"
+    done
+
+    # Let's still pretend it is `configure' which instantiates (i.e., don't
+    # use $as_me), people would be surprised to read:
+    #    /* config.h.  Generated by config.status.  */
+    configure_input='Generated from '`
+         $as_echo "$*" | sed 's|^[^:]*/||;s|:[^:]*/|, |g'
+       `' by configure.'
+    if test x"$ac_file" != x-; then
+      configure_input="$ac_file.  $configure_input"
+      { $as_echo "$as_me:$LINENO: creating $ac_file" >&5
+$as_echo "$as_me: creating $ac_file" >&6;}
+    fi
+    # Neutralize special characters interpreted by sed in replacement strings.
+    case $configure_input in #(
+    *\&* | *\|* | *\\* )
+       ac_sed_conf_input=`$as_echo "$configure_input" |
+       sed 's/[\\\\&|]/\\\\&/g'`;; #(
+    *) ac_sed_conf_input=$configure_input;;
+    esac
+
+    case $ac_tag in
+    *:-:* | *:-) cat >"$tmp/stdin" \
+      || { { $as_echo "$as_me:$LINENO: error: could not create $ac_file" >&5
+$as_echo "$as_me: error: could not create $ac_file" >&2;}
+   { (exit 1); exit 1; }; } ;;
+    esac
+    ;;
+  esac
+
+  ac_dir=`$as_dirname -- "$ac_file" ||
+$as_expr X"$ac_file" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+        X"$ac_file" : 'X\(//\)[^/]' \| \
+        X"$ac_file" : 'X\(//\)$' \| \
+        X"$ac_file" : 'X\(/\)' \| . 2>/dev/null ||
+$as_echo X"$ac_file" |
+    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
+           s//\1/
+           q
+         }
+         /^X\(\/\/\)[^/].*/{
+           s//\1/
+           q
+         }
+         /^X\(\/\/\)$/{
+           s//\1/
+           q
+         }
+         /^X\(\/\).*/{
+           s//\1/
+           q
+         }
+         s/.*/./; q'`
+  { as_dir="$ac_dir"
+  case $as_dir in #(
+  -*) as_dir=./$as_dir;;
+  esac
+  test -d "$as_dir" || { $as_mkdir_p && mkdir -p "$as_dir"; } || {
+    as_dirs=
+    while :; do
+      case $as_dir in #(
+      *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'(
+      *) as_qdir=$as_dir;;
+      esac
+      as_dirs="'$as_qdir' $as_dirs"
+      as_dir=`$as_dirname -- "$as_dir" ||
+$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+        X"$as_dir" : 'X\(//\)[^/]' \| \
+        X"$as_dir" : 'X\(//\)$' \| \
+        X"$as_dir" : 'X\(/\)' \| . 2>/dev/null ||
+$as_echo X"$as_dir" |
+    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
+           s//\1/
+           q
+         }
+         /^X\(\/\/\)[^/].*/{
+           s//\1/
+           q
+         }
+         /^X\(\/\/\)$/{
+           s//\1/
+           q
+         }
+         /^X\(\/\).*/{
+           s//\1/
+           q
+         }
+         s/.*/./; q'`
+      test -d "$as_dir" && break
+    done
+    test -z "$as_dirs" || eval "mkdir $as_dirs"
+  } || test -d "$as_dir" || { { $as_echo "$as_me:$LINENO: error: cannot create directory $as_dir" >&5
+$as_echo "$as_me: error: cannot create directory $as_dir" >&2;}
+   { (exit 1); exit 1; }; }; }
+  ac_builddir=.
+
+case "$ac_dir" in
+.) ac_dir_suffix= ac_top_builddir_sub=. ac_top_build_prefix= ;;
+*)
+  ac_dir_suffix=/`$as_echo "$ac_dir" | sed 's|^\.[\\/]||'`
+  # A ".." for each directory in $ac_dir_suffix.
+  ac_top_builddir_sub=`$as_echo "$ac_dir_suffix" | sed 's|/[^\\/]*|/..|g;s|/||'`
+  case $ac_top_builddir_sub in
+  "") ac_top_builddir_sub=. ac_top_build_prefix= ;;
+  *)  ac_top_build_prefix=$ac_top_builddir_sub/ ;;
+  esac ;;
+esac
+ac_abs_top_builddir=$ac_pwd
+ac_abs_builddir=$ac_pwd$ac_dir_suffix
+# for backward compatibility:
+ac_top_builddir=$ac_top_build_prefix
+
+case $srcdir in
+  .)  # We are building in place.
+    ac_srcdir=.
+    ac_top_srcdir=$ac_top_builddir_sub
+    ac_abs_top_srcdir=$ac_pwd ;;
+  [\\/]* | ?:[\\/]* )  # Absolute name.
+    ac_srcdir=$srcdir$ac_dir_suffix;
+    ac_top_srcdir=$srcdir
+    ac_abs_top_srcdir=$srcdir ;;
+  *) # Relative name.
+    ac_srcdir=$ac_top_build_prefix$srcdir$ac_dir_suffix
+    ac_top_srcdir=$ac_top_build_prefix$srcdir
+    ac_abs_top_srcdir=$ac_pwd/$srcdir ;;
+esac
+ac_abs_srcdir=$ac_abs_top_srcdir$ac_dir_suffix
+
+
+  case $ac_mode in
+  :F)
+  #
+  # CONFIG_FILE
+  #
+
+  case $INSTALL in
+  [\\/$]* | ?:[\\/]* ) ac_INSTALL=$INSTALL ;;
+  *) ac_INSTALL=$ac_top_build_prefix$INSTALL ;;
+  esac
+_ACEOF
+
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+# If the template does not know about datarootdir, expand it.
+# FIXME: This hack should be removed a few years after 2.60.
+ac_datarootdir_hack=; ac_datarootdir_seen=
+
+ac_sed_dataroot='
+/datarootdir/ {
+  p
+  q
+}
+/@datadir@/p
+/@docdir@/p
+/@infodir@/p
+/@localedir@/p
+/@mandir@/p
+'
+case `eval "sed -n \"\$ac_sed_dataroot\" $ac_file_inputs"` in
+*datarootdir*) ac_datarootdir_seen=yes;;
+*@datadir@*|*@docdir@*|*@infodir@*|*@localedir@*|*@mandir@*)
+  { $as_echo "$as_me:$LINENO: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&5
+$as_echo "$as_me: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&2;}
+_ACEOF
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+  ac_datarootdir_hack='
+  s&@datadir@&$datadir&g
+  s&@docdir@&$docdir&g
+  s&@infodir@&$infodir&g
+  s&@localedir@&$localedir&g
+  s&@mandir@&$mandir&g
+    s&\\\${datarootdir}&$datarootdir&g' ;;
+esac
+_ACEOF
+
+# Neutralize VPATH when `$srcdir' = `.'.
+# Shell code in configure.ac might set extrasub.
+# FIXME: do we really want to maintain this feature?
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+ac_sed_extra="$ac_vpsub
+$extrasub
+_ACEOF
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+:t
+/@[a-zA-Z_][a-zA-Z_0-9]*@/!b
+s|@configure_input@|$ac_sed_conf_input|;t t
+s&@top_builddir@&$ac_top_builddir_sub&;t t
+s&@top_build_prefix@&$ac_top_build_prefix&;t t
+s&@srcdir@&$ac_srcdir&;t t
+s&@abs_srcdir@&$ac_abs_srcdir&;t t
+s&@top_srcdir@&$ac_top_srcdir&;t t
+s&@abs_top_srcdir@&$ac_abs_top_srcdir&;t t
+s&@builddir@&$ac_builddir&;t t
+s&@abs_builddir@&$ac_abs_builddir&;t t
+s&@abs_top_builddir@&$ac_abs_top_builddir&;t t
+s&@INSTALL@&$ac_INSTALL&;t t
+$ac_datarootdir_hack
+"
+eval sed \"\$ac_sed_extra\" "$ac_file_inputs" | $AWK -f "$tmp/subs.awk" >$tmp/out \
+  || { { $as_echo "$as_me:$LINENO: error: could not create $ac_file" >&5
+$as_echo "$as_me: error: could not create $ac_file" >&2;}
+   { (exit 1); exit 1; }; }
+
+test -z "$ac_datarootdir_hack$ac_datarootdir_seen" &&
+  { ac_out=`sed -n '/\${datarootdir}/p' "$tmp/out"`; test -n "$ac_out"; } &&
+  { ac_out=`sed -n '/^[         ]*datarootdir[  ]*:*=/p' "$tmp/out"`; test -z "$ac_out"; } &&
+  { $as_echo "$as_me:$LINENO: WARNING: $ac_file contains a reference to the variable \`datarootdir'
+which seems to be undefined.  Please make sure it is defined." >&5
+$as_echo "$as_me: WARNING: $ac_file contains a reference to the variable \`datarootdir'
+which seems to be undefined.  Please make sure it is defined." >&2;}
+
+  rm -f "$tmp/stdin"
+  case $ac_file in
+  -) cat "$tmp/out" && rm -f "$tmp/out";;
+  *) rm -f "$ac_file" && mv "$tmp/out" "$ac_file";;
+  esac \
+  || { { $as_echo "$as_me:$LINENO: error: could not create $ac_file" >&5
+$as_echo "$as_me: error: could not create $ac_file" >&2;}
+   { (exit 1); exit 1; }; }
+ ;;
+  :H)
+  #
+  # CONFIG_HEADER
+  #
+  if test x"$ac_file" != x-; then
+    {
+      $as_echo "/* $configure_input  */" \
+      && eval '$AWK -f "$tmp/defines.awk"' "$ac_file_inputs"
+    } >"$tmp/config.h" \
+      || { { $as_echo "$as_me:$LINENO: error: could not create $ac_file" >&5
+$as_echo "$as_me: error: could not create $ac_file" >&2;}
+   { (exit 1); exit 1; }; }
+    if diff "$ac_file" "$tmp/config.h" >/dev/null 2>&1; then
+      { $as_echo "$as_me:$LINENO: $ac_file is unchanged" >&5
+$as_echo "$as_me: $ac_file is unchanged" >&6;}
+    else
+      rm -f "$ac_file"
+      mv "$tmp/config.h" "$ac_file" \
+       || { { $as_echo "$as_me:$LINENO: error: could not create $ac_file" >&5
+$as_echo "$as_me: error: could not create $ac_file" >&2;}
+   { (exit 1); exit 1; }; }
+    fi
+  else
+    $as_echo "/* $configure_input  */" \
+      && eval '$AWK -f "$tmp/defines.awk"' "$ac_file_inputs" \
+      || { { $as_echo "$as_me:$LINENO: error: could not create -" >&5
+$as_echo "$as_me: error: could not create -" >&2;}
+   { (exit 1); exit 1; }; }
+  fi
+ ;;
+  :L)
+  #
+  # CONFIG_LINK
+  #
+
+  if test "$ac_source" = "$ac_file" && test "$srcdir" = '.'; then
+    :
+  else
+    # Prefer the file from the source tree if names are identical.
+    if test "$ac_source" = "$ac_file" || test ! -r "$ac_source"; then
+      ac_source=$srcdir/$ac_source
+    fi
+
+    { $as_echo "$as_me:$LINENO: linking $ac_source to $ac_file" >&5
+$as_echo "$as_me: linking $ac_source to $ac_file" >&6;}
+
+    if test ! -r "$ac_source"; then
+      { { $as_echo "$as_me:$LINENO: error: $ac_source: file not found" >&5
+$as_echo "$as_me: error: $ac_source: file not found" >&2;}
+   { (exit 1); exit 1; }; }
+    fi
+    rm -f "$ac_file"
+
+    # Try a relative symlink, then a hard link, then a copy.
+    case $srcdir in
+    [\\/$]* | ?:[\\/]* ) ac_rel_source=$ac_source ;;
+       *) ac_rel_source=$ac_top_build_prefix$ac_source ;;
+    esac
+    ln -s "$ac_rel_source" "$ac_file" 2>/dev/null ||
+      ln "$ac_source" "$ac_file" 2>/dev/null ||
+      cp -p "$ac_source" "$ac_file" ||
+      { { $as_echo "$as_me:$LINENO: error: cannot link or copy $ac_source to $ac_file" >&5
+$as_echo "$as_me: error: cannot link or copy $ac_source to $ac_file" >&2;}
+   { (exit 1); exit 1; }; }
+  fi
+ ;;
+  :C)  { $as_echo "$as_me:$LINENO: executing $ac_file commands" >&5
+$as_echo "$as_me: executing $ac_file commands" >&6;}
+ ;;
+  esac
+
+
+  case $ac_file$ac_mode in
+    "Makefile":C) echo "Merging Makefile.sim+Make-common.sim into Makefile ..."
+ rm -f Makesim1.tmp Makesim2.tmp Makefile
+ sed -n -e '/^## COMMON_PRE_/,/^## End COMMON_PRE_/ p' <Make-common.sim >Makesim1.tmp
+ sed -n -e '/^## COMMON_POST_/,/^## End COMMON_POST_/ p' <Make-common.sim >Makesim2.tmp
+ sed -e '/^## COMMON_PRE_/ r Makesim1.tmp' \
+       -e '/^## COMMON_POST_/ r Makesim2.tmp' \
+       <Makefile.sim >Makefile
+ rm -f Makefile.sim Make-common.sim Makesim1.tmp Makesim2.tmp
+ ;;
+    "stamp-h":C) echo > stamp-h ;;
+
+  esac
+done # for ac_tag
+
+
+{ (exit 0); exit 0; }
+_ACEOF
+chmod +x $CONFIG_STATUS
+ac_clean_files=$ac_clean_files_save
+
+test $ac_write_fail = 0 ||
+  { { $as_echo "$as_me:$LINENO: error: write failure creating $CONFIG_STATUS" >&5
+$as_echo "$as_me: error: write failure creating $CONFIG_STATUS" >&2;}
+   { (exit 1); exit 1; }; }
+
+
+# configure is writing to config.log, and then calls config.status.
+# config.status does its own redirection, appending to config.log.
+# Unfortunately, on DOS this fails, as config.log is still kept open
+# by configure, so config.status won't be able to write to it; its
+# output is simply discarded.  So we exec the FD to /dev/null,
+# effectively closing config.log, so it can be properly (re)opened and
+# appended to by config.status.  When coming back to configure, we
+# need to make the FD available again.
+if test "$no_create" != yes; then
+  ac_cs_success=:
+  ac_config_status_args=
+  test "$silent" = yes &&
+    ac_config_status_args="$ac_config_status_args --quiet"
+  exec 5>/dev/null
+  $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false
+  exec 5>>config.log
+  # Use ||, not &&, to avoid exiting from the if with $? = 1, which
+  # would make configure fail if this is the last instruction.
+  $ac_cs_success || { (exit 1); exit 1; }
+fi
+if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then
+  { $as_echo "$as_me:$LINENO: WARNING: unrecognized options: $ac_unrecognized_opts" >&5
+$as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2;}
+fi
+
+

diff --git a/sim/microblaze/configure.ac b/sim/microblaze/configure.ac
new file mode 100644 (file)
index 0000000..78ef414
--- /dev/null
+++ b/sim/microblaze/configure.ac
@@ -0,0 +1,14 @@
+dnl Process this file with autoconf to produce a configure script.
+AC_PREREQ(2.59)dnl
+AC_INIT(Makefile.in)
+AC_CONFIG_HEADER(config.h:config.in)
+
+sinclude(../common/aclocal.m4)
+
+# Bugs in autoconf 2.59 break the call to SIM_AC_COMMON, hack around
+# it by inlining the macro's contents.
+sinclude(../common/common.m4)
+
+AC_CHECK_HEADERS(unistd.h)
+
+SIM_AC_OUTPUT

diff --git a/sim/microblaze/microblaze.h b/sim/microblaze/microblaze.h
new file mode 100644 (file)
index 0000000..2b31f2e
--- /dev/null
+++ b/sim/microblaze/microblaze.h
@@ -0,0 +1,106 @@
+#ifndef MICROBLAZE_H
+#define MICROBLAZE_H
+
+/* Copyright 2009 Free Software Foundation, Inc.
+
+   This file is part of the Xilinx MicroBlaze simulator.
+
+   This library is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#include "../../opcodes/microblaze-opcm.h"
+
+#define GET_RD ((inst & RD_MASK) >> RD_LOW)
+#define GET_RA ((inst & RA_MASK) >> RA_LOW)
+#define GET_RB ((inst & RB_MASK) >> RB_LOW)
+
+#define CPU     microblaze_state.cpu[0].microblaze_cpu
+
+#define RD      CPU.regs[rd]
+#define RA      CPU.regs[ra]
+#define RB      CPU.regs[rb]
+/* #define IMM     immword */
+
+#define SA     CPU.spregs[IMM & 0x1]
+
+#define IMM_H  CPU.imm_high
+#define IMM_L  ((inst & IMM_MASK) >> IMM_LOW)
+
+#define IMM_ENABLE CPU.imm_enable
+
+#define IMM             (IMM_ENABLE ?                                  \
+                         (((uhalf)IMM_H << 16) | (uhalf)IMM_L) :       \
+                         (imm_unsigned ?                               \
+                         (0xFFFF & IMM_L) :                            \
+                          (IMM_L & 0x8000 ?                             \
+                          (0xFFFF0000 | IMM_L) :                       \
+                          (0x0000FFFF & IMM_L))))
+
+#define PC     CPU.spregs[0]
+#define        MSR     CPU.spregs[1]
+#define SP      CPU.regs[29]
+#define RETREG  CPU.regs[3]
+
+
+#define MEM(X) memory[X]
+
+#define MEM_RD_BYTE(X) rbat(X)
+#define MEM_RD_HALF(X) rhat(X)
+#define MEM_RD_WORD(X) rlat(X)
+#define MEM_RD_UBYTE(X) (ubyte) MEM_RD_BYTE(X)
+#define MEM_RD_UHALF(X) (uhalf) MEM_RD_HALF(X)
+#define MEM_RD_UWORD(X) (uword) MEM_RD_WORD(X)
+
+#define MEM_WR_BYTE(X, D) wbat(X, D)
+#define MEM_WR_HALF(X, D) what(X, D)
+#define MEM_WR_WORD(X, D) wlat(X, D)
+
+
+#define MICROBLAZE_SEXT8(X)    ((char) X)
+#define MICROBLAZE_SEXT16(X)   ((short) X)
+
+
+#define CARRY          carry
+#define C_rd           ((MSR & 0x4) >> 2)
+#define C_wr(D)                MSR = (D ? MSR | 0x80000004 : MSR & 0x7FFFFFFB)
+
+#define C_calc(X, Y, C)        ((((uword)Y == MAX_WORD) && (C == 1)) ?          \
+                        1 :                                             \
+                        ((MAX_WORD - (uword)X) < ((uword)Y + C)))
+
+#define BIP_MASK       0x00000008
+#define CARRY_MASK     0x00000004
+#define INTR_EN_MASK   0x00000002
+#define BUSLOCK_MASK   0x00000001
+
+#define DELAY_SLOT      delay_slot_enable = 1
+#define BRANCH          branch_taken = 1
+
+#define NUM_REGS       32
+#define NUM_SPECIAL    2
+#define INST_SIZE      4
+
+#define MAX_WORD       0xFFFFFFFF
+#define MICROBLAZE_HALT_INST  0xb8000000
+
+typedef char           byte;
+typedef short          half;
+typedef int            word;
+typedef unsigned char  ubyte;
+typedef unsigned short uhalf;
+typedef unsigned int   uword;
+
+#endif /* MICROBLAZE_H */
+

diff --git a/sim/microblaze/microblaze.isa b/sim/microblaze/microblaze.isa
new file mode 100644 (file)
index 0000000..d1369b2
--- /dev/null
+++ b/sim/microblaze/microblaze.isa
@@ -0,0 +1,823 @@
+/* Copyright 2009 Free Software Foundation, Inc.
+
+   This file is part of the Xilinx MicroBlaze simulator.
+
+   This library is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/*
+ *  MICROBLAZE Instruction Set Architecture
+ *
+ *  INSTRUCTION(NAME,
+ *              OPCODE,
+ *              TYPE,
+ *              SEMANTICS)
+ *
+ */
+
+INSTRUCTION(add,
+           0x00,
+           INST_TYPE_RD_RA_RB,
+           CARRY = C_calc(RA, RB, 0);
+           RD = RA + RB;
+           C_wr(CARRY);
+           PC += INST_SIZE)
+
+INSTRUCTION(rsub,
+           0x01,
+            INST_TYPE_RD_RA_RB, 
+           CARRY = C_calc(RB, ~RA, 1);
+           RD = RB + ~RA + 1;
+            C_wr(CARRY);
+           PC += INST_SIZE)
+
+INSTRUCTION(addc,
+           0x02,
+            INST_TYPE_RD_RA_RB,
+           CARRY = C_calc(RA, RB, C_rd);
+           RD = RA + RB + C_rd;
+           C_wr(CARRY);
+           PC += INST_SIZE)
+
+INSTRUCTION(rsubc,
+           0x03,
+            INST_TYPE_RD_RA_RB,
+           CARRY = C_calc(RB, ~RA, C_rd);
+           RD = RB + ~RA + C_rd;
+            C_wr(CARRY);
+           PC += INST_SIZE)
+
+INSTRUCTION(addk,
+           0x04,
+            INST_TYPE_RD_RA_RB,
+           RD = RA + RB;
+           PC += INST_SIZE)
+
+INSTRUCTION(rsubk,
+           0x05,
+            INST_TYPE_RD_RA_RB,
+           RD = RB + ~RA + 1;
+           PC += INST_SIZE)
+
+INSTRUCTION(cmp,
+            0x05,
+            INST_TYPE_RD_RA_RB,
+            {
+             int tmp_reg = RB + ~RA + 1;
+             if ((RB & 0x80000000) ^ (RA & 0x80000000)) {
+               tmp_reg = ((tmp_reg & 0x7fffffff) | (RB & 0x80000000));
+             }
+             RD = tmp_reg;
+             PC += INST_SIZE;
+           })
+
+INSTRUCTION(cmpu,
+            0x05,
+            INST_TYPE_RD_RA_RB,
+            {
+             int tmp_reg = RB + ~RA + 1;
+             if ((RB & 0x80000000) ^ (RA & 0x80000000)) {
+               tmp_reg = ((tmp_reg & 0x7fffffff) | (RA & 0x80000000));
+             }
+             RD = tmp_reg;
+             PC += INST_SIZE;
+           })
+
+INSTRUCTION(addkc,
+           0x06,
+            INST_TYPE_RD_RA_RB,
+           RD = RA + RB + C_rd;
+           PC += INST_SIZE)
+
+INSTRUCTION(rsubkc,
+           0x07,
+            INST_TYPE_RD_RA_RB,
+           RD = RB + ~RA + C_rd;
+           PC += INST_SIZE)
+
+INSTRUCTION(addi,
+           0x08,
+           INST_TYPE_RD_RA_IMM,
+            CARRY = C_calc(RA, IMM, 0);
+           RD = RA + IMM;
+           C_wr(CARRY);
+           PC += INST_SIZE)
+
+INSTRUCTION(rsubi,
+           0x09,
+           INST_TYPE_RD_RA_IMM,
+            CARRY = C_calc(IMM, ~RA, 1);
+           RD = IMM + ~RA + 1;
+            C_wr(CARRY);
+           PC += INST_SIZE)
+
+INSTRUCTION(addic,
+           0x0A,
+            INST_TYPE_RD_RA_IMM,
+            CARRY = C_calc(RA, IMM, C_rd);
+           RD = RA + IMM + C_rd;
+            C_wr(CARRY);
+           PC += INST_SIZE)
+
+INSTRUCTION(rsubic,
+           0x0B,
+            INST_TYPE_RD_RA_IMM,
+            CARRY = C_calc(IMM, ~RA, C_rd);
+           RD = IMM + ~RA + C_rd;
+            C_wr(CARRY);
+           PC += INST_SIZE)
+
+INSTRUCTION(addik,
+           0x0C,
+            INST_TYPE_RD_RA_IMM,
+           RD = RA + IMM;
+           PC += INST_SIZE)
+
+INSTRUCTION(rsubik,
+           0x0D,
+            INST_TYPE_RD_RA_IMM,
+           RD = IMM + ~RA + 1;
+           PC += INST_SIZE)
+
+INSTRUCTION(addikc,
+           0x0E,
+            INST_TYPE_RD_RA_IMM,
+           RD = RA + IMM + C_rd;
+           PC += INST_SIZE)
+
+INSTRUCTION(rsubikc,
+           0x0F,
+            INST_TYPE_RD_RA_IMM,
+            RD = IMM + ~RA + C_rd;
+           PC += INST_SIZE)
+
+INSTRUCTION(mul,
+           0x10,
+            INST_TYPE_RD_RA_RB, 
+           RD = RA * RB;
+           PC += INST_SIZE)
+
+INSTRUCTION(bsrl,
+           0x11,
+           INST_TYPE_RD_RA_RB,
+           RD = (uword)RA >> RB;
+           PC += INST_SIZE)
+
+INSTRUCTION(bsra,
+           0x11,
+           INST_TYPE_RD_RA_RB,
+           RD = (word)RA >> RB;
+           PC += INST_SIZE)
+
+INSTRUCTION(bsll,
+           0x11,
+           INST_TYPE_RD_RA_RB,
+           RD = (uword)RA << RB;
+           PC += INST_SIZE)
+
+INSTRUCTION(idiv,
+           0x12,
+           INST_TYPE_RD_RA_RB,
+           RD = (word) RB / (word) RA;
+           PC += INST_SIZE)
+
+INSTRUCTION(idivu,
+           0x12,
+           INST_TYPE_RD_RA_RB,
+           RD = (uword) RB / (uword) RA;
+           PC += INST_SIZE)
+
+INSTRUCTION(muli,
+           0x18,
+            INST_TYPE_RD_RA_IMM,
+           RD = RA * IMM;
+           PC += INST_SIZE)
+
+INSTRUCTION(bsrli,
+           0x19,
+           INST_TYPE_RD_RA_IMM5,
+           RD = (uword)RA >> (IMM & 0x1F);
+           PC += INST_SIZE)
+
+INSTRUCTION(bsrai,
+           0x19,
+           INST_TYPE_RD_RA_IMM5,
+           RD = (word)RA >> (IMM & 0x1F);
+           PC += INST_SIZE)
+
+INSTRUCTION(bslli,
+           0x19,
+           INST_TYPE_RD_RA_IMM5,
+           RD = (uword)RA << (IMM & 0x1F);
+           PC += INST_SIZE)
+
+INSTRUCTION(get,
+            0x1b,
+            INST_TYPE_RD_IMM12,
+            PC += INST_SIZE)
+
+INSTRUCTION(put,
+            0x1b,
+            INST_TYPE_R1_IMM12,
+            PC += INST_SIZE)
+
+INSTRUCTION(nget,
+            0x1b,
+            INST_TYPE_RD_IMM12,
+            PC += INST_SIZE)
+
+INSTRUCTION(nput,
+            0x1b,
+            INST_TYPE_R1_IMM12,
+            PC += INST_SIZE)
+
+INSTRUCTION(cget,
+            0x1b,
+            INST_TYPE_RD_IMM12,
+            PC += INST_SIZE)
+
+INSTRUCTION(cput,
+            0x1b,
+            INST_TYPE_R1_IMM12,
+            PC += INST_SIZE)
+
+INSTRUCTION(ncget,
+            0x1b,
+            INST_TYPE_RD_IMM12,
+            PC += INST_SIZE)
+
+INSTRUCTION(ncput,
+            0x1b,
+            INST_TYPE_R1_IMM12,
+            PC += INST_SIZE) 
+
+INSTRUCTION(or,
+           0x20,
+            INST_TYPE_RD_RA_RB,
+           RD = RA | RB;
+           PC += INST_SIZE)
+
+INSTRUCTION(and,
+           0x21,
+            INST_TYPE_RD_RA_RB,
+           RD = RA & RB;
+           PC += INST_SIZE)
+
+INSTRUCTION(xor,
+           0x22,
+            INST_TYPE_RD_RA_RB,
+           RD = RA ^ RB;
+           PC += INST_SIZE)
+
+INSTRUCTION(andn,
+           0x23,
+            INST_TYPE_RD_RA_RB,
+           RD = RA & ~RB;
+           PC += INST_SIZE)
+
+INSTRUCTION(sra,
+           0x24,
+           INST_TYPE_RD_RA,
+           CARRY = (RA & 0x1);
+           RD = (int) (RA >> 1);
+           C_wr(CARRY);
+           PC += INST_SIZE)
+
+INSTRUCTION(src,
+           0x24,
+            INST_TYPE_RD_RA,
+           CARRY = (RA & 0x1);
+            RD = ((((int) (RA >> 1)) & 0x7FFFFFFF) | (uword)(C_rd << 31));
+            C_wr(CARRY);
+           PC += INST_SIZE)
+
+INSTRUCTION(srl,
+           0x24,
+            INST_TYPE_RD_RA,
+            CARRY = (RA & 0x1);
+           RD = (uword) ((RA >> 1) & 0x7FFFFFFF);
+            C_wr(CARRY);
+           PC += INST_SIZE)
+
+INSTRUCTION(sext8,
+           0x24,
+            INST_TYPE_RD_RA,
+           RD = MICROBLAZE_SEXT8(RA);
+           PC += INST_SIZE)
+
+INSTRUCTION(sext16,
+            0x24,
+            INST_TYPE_RD_RA,
+           RD = MICROBLAZE_SEXT16(RA);
+            PC += INST_SIZE)
+
+INSTRUCTION(wdc,
+            0x24,
+            INST_TYPE_RA_RB,
+            PC += INST_SIZE)
+
+INSTRUCTION(wic,
+            0x24,
+            INST_TYPE_RA_RB,
+            PC += INST_SIZE)
+
+INSTRUCTION(mts,
+           0x25,
+           INST_TYPE_SA_RA,
+           SA = RA;
+           PC += INST_SIZE)
+
+INSTRUCTION(mfs,
+           0x25,
+            INST_TYPE_RD_SA,
+           RD = SA;
+           PC += INST_SIZE)
+
+INSTRUCTION(br,
+           0x26,
+           INST_TYPE_RB,
+           PC += RB;
+           BRANCH)
+
+INSTRUCTION(brd,
+            0x26,
+            INST_TYPE_RB,
+            PC += RB;
+           BRANCH;
+            DELAY_SLOT)
+
+INSTRUCTION(brld,
+           0x26,
+           INST_TYPE_RD_RB,
+           RD = PC;
+           PC += RB;
+           BRANCH;
+           DELAY_SLOT)
+
+INSTRUCTION(bra,
+           0x26,
+            INST_TYPE_RB,
+           PC = RB;
+           BRANCH)
+
+INSTRUCTION(brad,
+            0x26,
+            INST_TYPE_RB,
+            PC = RB;
+           BRANCH;
+            DELAY_SLOT)
+
+INSTRUCTION(brald,
+           0x26,
+            INST_TYPE_RD_RB,
+           RD = PC;
+           PC = RB;
+           BRANCH;
+           DELAY_SLOT)
+
+INSTRUCTION(microblaze_brk,
+           0x26,
+            INST_TYPE_RD_RB,
+           RD = PC;
+           PC = RB;
+            MSR = MSR | BIP_MASK;
+           BRANCH)
+
+INSTRUCTION(beq,
+           0x27,
+            INST_TYPE_RA_RB,
+           if (RA == 0) {
+             PC += RB;
+             BRANCH;
+            } else {
+             PC += INST_SIZE;
+           })
+
+INSTRUCTION(beqd,
+            0x27,
+            INST_TYPE_RA_RB,
+            if (RA == 0) {
+             PC += RB;
+             BRANCH;
+           } else {
+             PC += INST_SIZE;
+           }
+           DELAY_SLOT)
+
+INSTRUCTION(bne,
+           0x27,
+            INST_TYPE_RA_RB,
+           if (RA != 0) {
+             PC += RB;
+             BRANCH;
+           } else {
+             PC += INST_SIZE;
+           })
+
+INSTRUCTION(bned,
+            0x27,
+            INST_TYPE_RA_RB,
+            if (RA != 0) {
+             PC += RB;
+             BRANCH;
+           } else {
+             PC += INST_SIZE;
+           }
+           DELAY_SLOT)
+
+INSTRUCTION(blt,
+           0x27,
+            INST_TYPE_RA_RB,
+           if (RA < 0) {
+             PC += RB;
+             BRANCH;
+           } else {
+             PC += INST_SIZE;
+           })
+
+INSTRUCTION(bltd,
+            0x27,
+            INST_TYPE_RA_RB,
+            if (RA < 0) {
+             PC += RB;
+             BRANCH;
+           } else {
+             PC += INST_SIZE;
+           }
+           DELAY_SLOT)
+
+INSTRUCTION(ble,
+           0x27,
+            INST_TYPE_RA_RB,
+           if (RA <= 0) {
+             PC += RB;
+             BRANCH;
+           } else {
+             PC += INST_SIZE;
+           })
+
+INSTRUCTION(bled,
+            0x27,
+            INST_TYPE_RA_RB,
+            if (RA <= 0) {
+             PC += RB;
+             BRANCH;
+           } else {
+             PC += INST_SIZE;
+           }
+           DELAY_SLOT)
+
+INSTRUCTION(bgt,
+           0x27,
+            INST_TYPE_RA_RB,
+           if (RA > 0) {
+             PC += RB;
+             BRANCH;
+           } else {
+             PC += INST_SIZE;
+           })
+
+INSTRUCTION(bgtd,
+            0x27,
+            INST_TYPE_RA_RB,
+            if (RA > 0) {
+             PC += RB;
+             BRANCH;
+           } else {
+             PC += INST_SIZE;
+           }
+           DELAY_SLOT)
+
+INSTRUCTION(bge,
+           0x27,
+            INST_TYPE_RA_RB,
+           if (RA >= 0) {
+             PC += RB;
+             BRANCH;
+           } else {
+             PC += INST_SIZE;
+           })
+
+INSTRUCTION(bged,
+            0x27,
+            INST_TYPE_RA_RB,
+            if (RA >= 0) {
+             PC += RB;
+             BRANCH;
+           } else {
+             PC += INST_SIZE;
+           }
+           DELAY_SLOT)
+
+INSTRUCTION(ori,
+           0x28,
+            INST_TYPE_RD_RA_IMM,
+           RD = RA | IMM;
+           PC += INST_SIZE)
+
+INSTRUCTION(andi,
+           0x29,
+            INST_TYPE_RD_RA_IMM,
+           RD = RA & IMM;
+           PC += INST_SIZE)
+
+INSTRUCTION(xori,
+           0x2A,
+            INST_TYPE_RD_RA_IMM,
+           RD = RA ^ IMM;
+           PC += INST_SIZE)
+
+INSTRUCTION(andni,
+           0x2B,
+            INST_TYPE_RD_RA_IMM,
+           RD = RA & ~IMM;
+           PC += INST_SIZE)
+
+INSTRUCTION(imm,
+           0x2C,
+           INST_TYPE_IMM,
+           IMM_H = IMM_L;
+           PC += INST_SIZE)
+
+INSTRUCTION(rtsd,
+           0x2D,
+            INST_TYPE_RA_IMM,
+           PC = RA + IMM;
+           BRANCH;
+           DELAY_SLOT)
+
+INSTRUCTION(rtid,
+           0x2D,
+            INST_TYPE_RA_IMM,
+           PC = RA + IMM;
+           MSR = MSR | INTR_EN_MASK;
+           BRANCH;
+           DELAY_SLOT)
+
+INSTRUCTION(rtbd,
+           0x2D,
+           INST_TYPE_RA_IMM,
+           PC = RA + IMM;
+           MSR = MSR & ~BIP_MASK;
+           BRANCH;
+            DELAY_SLOT;)
+
+INSTRUCTION(bri,
+           0x2E,
+            INST_TYPE_IMM,
+           PC += IMM;
+           BRANCH)
+
+INSTRUCTION(brid,
+            0x2E,
+            INST_TYPE_IMM,
+            PC += IMM;
+           BRANCH;
+            DELAY_SLOT)
+
+INSTRUCTION(brlid,
+           0x2E,
+            INST_TYPE_RD_IMM,
+           RD = PC;
+           PC += IMM;
+           BRANCH;
+           DELAY_SLOT)
+
+INSTRUCTION(brai,
+           0x2E,
+            INST_TYPE_IMM,
+           PC = IMM;
+           BRANCH)
+
+INSTRUCTION(braid,
+            0x2E,
+            INST_TYPE_IMM,
+            PC = IMM;
+           BRANCH;
+            DELAY_SLOT)
+
+INSTRUCTION(bralid,
+           0x2E,
+           INST_TYPE_RD_IMM,
+           RD = PC;
+           PC = IMM;
+           BRANCH;
+           DELAY_SLOT)
+
+INSTRUCTION(brki,
+           0x2E,
+            INST_TYPE_RD_IMM,
+           RD = PC;
+           PC = IMM;
+            MSR = MSR | BIP_MASK;
+           BRANCH)
+
+INSTRUCTION(beqi,
+           0x2F,
+            INST_TYPE_RA_IMM,
+           if (RA == 0) {
+             PC += IMM;
+             BRANCH;
+           } else {
+             PC += INST_SIZE;
+           })
+
+INSTRUCTION(beqid,
+            0x2F,
+            INST_TYPE_RA_IMM,
+            if (RA == 0) {
+             PC += IMM;
+             BRANCH;
+           } else {
+             PC += INST_SIZE;
+           }
+           DELAY_SLOT)
+
+INSTRUCTION(bnei,
+           0x2F,
+            INST_TYPE_RA_IMM,
+           if (RA != 0) {
+             PC += IMM;
+             BRANCH;
+           } else {
+             PC += INST_SIZE;
+           })
+
+INSTRUCTION(bneid,
+            0x2F,
+            INST_TYPE_RA_IMM,
+            if (RA != 0) {
+             PC += IMM;
+             BRANCH;
+           } else {
+             PC += INST_SIZE;
+           }
+           DELAY_SLOT)
+
+INSTRUCTION(blti,
+           0x2F,
+            INST_TYPE_RA_IMM,
+           if (RA < 0) {
+             PC += IMM;
+             BRANCH;
+           } else {
+             PC += INST_SIZE;
+           })
+
+INSTRUCTION(bltid,
+            0x2F,
+            INST_TYPE_RA_IMM,
+            if (RA < 0) {
+             PC += IMM;
+             BRANCH;
+           } else {
+             PC += INST_SIZE;
+           }
+           DELAY_SLOT)
+
+INSTRUCTION(blei,
+           0x2F,
+            INST_TYPE_RA_IMM,
+           if (RA <= 0) {
+             PC += IMM;
+             BRANCH;
+           } else {
+             PC += INST_SIZE;
+           })
+
+INSTRUCTION(bleid,
+            0x2F,
+            INST_TYPE_RA_IMM,
+            if (RA <= 0) {
+             PC += IMM;
+             BRANCH;
+           } else {
+             PC += INST_SIZE;
+           }
+           DELAY_SLOT)
+
+INSTRUCTION(bgti,
+           0x2F,
+            INST_TYPE_RA_IMM,
+           if (RA > 0) {
+             PC += IMM;
+             BRANCH;
+           } else {
+             PC += INST_SIZE;
+           })
+
+INSTRUCTION(bgtid,
+            0x2F,
+            INST_TYPE_RA_IMM,
+            if (RA > 0) {
+             PC += IMM;
+             BRANCH;
+           } else {
+             PC += INST_SIZE;
+           }
+           DELAY_SLOT)
+
+INSTRUCTION(bgei,
+           0x2F,
+            INST_TYPE_RA_IMM,
+           if (RA >= 0) {
+             PC += IMM;
+             BRANCH;
+           } else {
+             PC += INST_SIZE;
+           })
+
+INSTRUCTION(bgeid,
+            0x2F,
+            INST_TYPE_RA_IMM,
+            if (RA >= 0) {
+             PC += IMM;
+             BRANCH;
+           } else {
+             PC += INST_SIZE;
+           }
+           DELAY_SLOT)
+
+INSTRUCTION(lbu,
+           0x30,
+            INST_TYPE_RD_RA_RB,
+           RD = (MEM_RD_UBYTE(RA + RB));
+           PC += INST_SIZE)
+
+INSTRUCTION(lhu,
+           0x31,
+           INST_TYPE_RD_RA_RB,
+           RD = (MEM_RD_UHALF((RA + RB) & ~0x1));
+           PC += INST_SIZE)
+
+INSTRUCTION(lw,
+           0x32,
+            INST_TYPE_RD_RA_RB, 
+           RD = (MEM_RD_WORD((RA + RB) & ~0x3));
+           PC += INST_SIZE)
+
+INSTRUCTION(sb,
+           0x34,
+            INST_TYPE_RD_RA_RB,
+           MEM_WR_BYTE(RA + RB, RD);
+           PC += INST_SIZE)
+
+INSTRUCTION(sh,
+           0x35,
+            INST_TYPE_RD_RA_RB,
+           MEM_WR_HALF((RA + RB) & ~0x1, RD);
+           PC += INST_SIZE)
+
+INSTRUCTION(sw,
+           0x36,
+            INST_TYPE_RD_RA_RB,
+           MEM_WR_WORD((RA + RB) & ~0x3, RD);
+           PC += INST_SIZE)
+
+INSTRUCTION(lbui,
+           0x38,
+            INST_TYPE_RD_RA_IMM,
+           RD = (MEM_RD_UBYTE(RA + IMM));
+           PC += INST_SIZE)
+
+INSTRUCTION(lhui,
+           0x39,
+            INST_TYPE_RD_RA_IMM,
+           RD = (MEM_RD_UHALF((RA+IMM) & ~0x1));
+           PC += INST_SIZE)
+
+INSTRUCTION(lwi,
+           0x3A,
+            INST_TYPE_RD_RA_IMM, 
+           RD = (MEM_RD_WORD((RA+IMM) & ~0x3));
+           PC += INST_SIZE)
+
+INSTRUCTION(sbi,
+           0x3C,
+            INST_TYPE_RD_RA_IMM,
+           MEM_WR_BYTE(RA + IMM, RD);
+           PC += INST_SIZE)
+
+INSTRUCTION(shi,
+           0x3D,
+            INST_TYPE_RD_RA_IMM,
+           MEM_WR_HALF((RA + IMM) & ~0x1, RD);
+           PC += INST_SIZE)
+
+INSTRUCTION(swi,
+           0x3E,
+            INST_TYPE_RD_RA_IMM,
+           MEM_WR_WORD((RA + IMM) & ~0x3, RD);
+           PC += INST_SIZE)

diff --git a/sim/microblaze/sim-main.h b/sim/microblaze/sim-main.h
new file mode 100644 (file)
index 0000000..67e6fae
--- /dev/null
+++ b/sim/microblaze/sim-main.h
@@ -0,0 +1,64 @@
+#ifndef MICROBLAZE_SIM_MAIN
+#define MICROBLAZE_SIM_MAIN
+
+/* Copyright 2009 Free Software Foundation, Inc.
+
+   This file is part of the Xilinx MicroBlaze simulator.
+
+   This library is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#include "microblaze.h"
+#include "sim-basics.h"
+typedef address_word sim_cia;
+#include "sim-base.h"
+
+/* The machine state.
+   This state is maintained in host byte order.  The
+   fetch/store register functions must translate between host
+   byte order and the target processor byte order.
+   Keeping this data in target byte order simplifies the register
+   read/write functions.  Keeping this data in native order improves
+   the performance of the simulator.  Simulation speed is deemed more
+   important.  */
+
+/* The ordering of the microblaze_regset structure is matched in the
+   gdb/config/microblaze/tm-microblaze.h file in the REGISTER_NAMES macro.  */
+ struct microblaze_regset
+{
+  word           regs[32];             /* primary registers */
+  word           spregs[2];            /* pc + msr */
+  int            cycles;
+  int            insts;
+  int            exception;
+  unsigned long   msize;
+  unsigned char  *memory;
+  ubyte           imm_enable;
+  half            imm_high;
+};
+
+struct _sim_cpu {
+  struct microblaze_regset microblaze_cpu;
+  sim_cpu_base base;
+};
+
+#define MAX_NR_PROCESSORS 1
+struct sim_state {
+  sim_cpu cpu[MAX_NR_PROCESSORS];
+#define STATE_CPU(sd, n) (&(sd)->cpu[0])
+  sim_state_base base;
+};
+#endif /* MICROBLAZE_SIM_MAIN */
+

diff --git a/sim/microblaze/sysdep.h b/sim/microblaze/sysdep.h
new file mode 100644 (file)
index 0000000..335f52a
--- /dev/null
+++ b/sim/microblaze/sysdep.h
@@ -0,0 +1,95 @@
+/* System includes and definitions used by the Xilinx MicroBlaze simulator.
+   Copyright (C) 1999 Free Software Foundation, Inc.
+   Contributed by Cygnus Solutions.
+
+This file is part of GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef __SYSDEP_H
+#define __SYSDEP_H
+
+#ifndef        hosts_std_host_H
+#include <fcntl.h>
+#include <errno.h>
+#include <stdio.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <ctype.h>
+#include <string.h>
+#include <sys/file.h>
+#include "ansidecl.h"
+
+#ifndef        O_ACCMODE
+#define O_ACCMODE (O_RDONLY | O_WRONLY | O_RDWR)
+#endif
+#ifndef        SEEK_SET
+#define SEEK_SET 0
+#endif
+#ifndef        SEEK_CUR
+#define SEEK_CUR 1
+#endif
+#ifdef STDC_HEADERS
+#include <stdlib.h>
+/*#include <string.h>*/
+#else
+extern char *mktemp ();
+#ifndef memset
+extern PTR    memset ();
+#endif
+
+#ifndef        DONTDECLARE_MALLOC
+extern PTR   malloc ();
+extern PTR   realloc ();
+#endif
+
+#ifndef        __GNUC__
+extern PTR   memcpy ();
+#else
+/* char *memcpy (); */
+#endif
+
+#ifdef __STDC__
+extern void free ();
+#else
+extern int free();
+#endif
+
+#ifndef strchr
+extern char *strchr();
+#endif
+extern char *getenv();
+extern PTR    memchr();
+extern char *strrchr();
+
+extern char *strrchr();
+extern char *ctime();
+extern long   atol();
+extern char *getenv();
+#endif /* STDC_HEADERS */
+
+#ifndef        BYTES_IN_PRINTF_INT
+#define BYTES_IN_PRINTF_INT 4
+#endif
+
+#include "fopen-same.h"
+#define hosts_std_host_H
+#endif
+
+#ifdef STDC_HEADERS
+#include <stddef.h>
+#endif /* STDC_HEADERS */
+
+#endif /* __SYSDEP_H */