Add ms2.
* archures.c (bfd_mach_ms2): Define.
* cpu-ms1.c (arch_info_struct): Add ms2 stanza.
* elf32-ms1.c (elf32_ms1_machine): Add ms2 case.
(ms1_elf_merge_private_bfd_data): Remove unused variables. Add
correct merging logic, with workaround.
(ms1_elf_print_private_bfd_data): Add ms2 case.
* reloc.c (BFD_RELOC_MS1_PCINSN8): Add ms2 specific reloc.
* libbfd.h: Regenerated.
* bfd-in2.h: Regenerated.
cpu:
Add ms2
* ms1.cpu (ms2, ms2bf): New architecture variant, cpu, machine and
model.
(f-uu8, f-uu1, f-imm16l, f-loopo, f-cb1sel, f-cb2sel, f-cb1incr,
f-cb2incr, f-rc3): New fields.
(LOOP): New instruction.
(JAL-HAZARD): New hazard.
(imm16o, loopsize, imm16l, rc3, cb1sel, cb2sel, cb1incr, cb2incr):
New operands.
(mul, muli, dbnz, iflush): Enable for ms2
(jal, reti): Has JAL-HAZARD.
(ldctxt, ldfb, stfb): Only ms1.
(fbcb): Only ms1,ms1-003.
(wfbinc, mefbinc, wfbincr, mwfbincr, fbcbincs, mfbcbincs,
fbcbincrs, mfbcbincrs): Enable for ms2.
(loop, loopu, dfbc, dwfb, fbwfb, dfbr): New ms2 insns.
* ms1.opc (parse_loopsize): New.
(parse_imm16): hi16/lo16 relocs are applicable to IMM16L.
(print_pcrel): New.
gas:
Add ms2.
* config/tc-ms1.c (ms1_mach_bitmask): Initialize to MS1.
(ms1_architectures): Add ms2.
(md_parse_option): Add ms2.
(md_show_usage): Add ms2.
(md_assemble): Add JAL_HAZARD detection logic.
(md_cgen_lookup_reloc): Add MS1_OPERAND_LOOPSIZE case.
* doc/c-ms1.texi: New.
* doc/all.texi: Add MS1.
* doc/Makefile.am (CPU_DOCS): Add c-ms1.texi.
* doc/Makefile.in: Rebuilt.
* doc/Makefile: Rebuilt.
gas/testsuite:
Add ms2.
* gas/ms1/allinsn.d: Adjust pcrel disassembly.
* gas/ms1/errors.exp: Fix target triplet.
* gas/ms1/ms1-16-003.d: Adjust pcrel disassembly.
* gas/ms1/ms1-16-003.s: Tweak label.
* gas/ms1/ms1.exp: Adjust target triplet. Add ms2 test.
* gas/ms1/ms2.d, gas/ms1/ms2.s: New.
* gas/ms1/relocs.d: Adjust expected machine name and pcrel
disassembly.
* gas/ms1/relocs.exp: Adjust target triplet.
include:
Add ms2.
* elf/ms1.h (EF_MS1_CPU_MS2): New.
opcodes:
Add ms2.
* ms1-asm.c, ms1-desc.c, ms1-desc.h, ms1-dis.c, ms1-ibld.c,
ms1-opc.c, ms1-opc.h: Regenerated.
+2005-11-08 Nathan Sidwell <nathan@codesourcery.com>
+
+ Add ms2 support
+ * archures.c (bfd_mach_ms2): Define.
+ * cpu-ms1.c (arch_info_struct): Add ms2 stanza.
+ * elf32-ms1.c (elf32_ms1_machine): Add ms2 case.
+ (ms1_elf_merge_private_bfd_data): Remove unused variables. Add
+ correct merging logic, with workaround.
+ (ms1_elf_print_private_bfd_data): Add ms2 case.
+ * reloc.c (BFD_RELOC_MS1_PCINSN8): Add ms2 specific reloc.
+ * libbfd.h: Regenerated.
+ * bfd-in2.h: Regenerated.
+
2005-11-07 Steve Ellcey <sje@cup.hp.com>
* warning.m4 (AM_BINUTILS_WARNINGS): Default to empty string
. bfd_arch_ms1,
.#define bfd_mach_ms1 1
.#define bfd_mach_mrisc2 2
+.#define bfd_mach_ms2 3
. bfd_arch_pj,
. bfd_arch_avr, {* Atmel AVR microcontrollers. *}
.#define bfd_mach_avr1 1
bfd_arch_ms1,
#define bfd_mach_ms1 1
#define bfd_mach_mrisc2 2
+#define bfd_mach_ms2 3
bfd_arch_pj,
bfd_arch_avr, /* Atmel AVR microcontrollers. */
#define bfd_mach_avr1 1
/* Morpho MS1 - Used to tell the linker which vtable entries are used. */
BFD_RELOC_MS1_GNU_VTENTRY,
+/* Morpho MS1 - 8 bit immediate relocation. */
+ BFD_RELOC_MS1_PCINSN8,
+
/* msp430 specific relocation codes */
BFD_RELOC_MSP430_10_PCREL,
BFD_RELOC_MSP430_16_PCREL,
FALSE, /* The default ? */
bfd_default_compatible, /* Architecture comparison fn. */
bfd_default_scan, /* String to architecture convert fn. */
+ &arch_info_struct[1] /* Next in list. */
+},
+{
+ 32, /* Bits per word - not really true. */
+ 32, /* Bits per address. */
+ 8, /* Bits per byte. */
+ bfd_arch_ms1, /* Architecture. */
+ bfd_mach_ms2, /* Machine. */
+ "ms1", /* Architecture name. */
+ "ms2", /* Printable name. */
+ 1, /* Section align power. */
+ FALSE, /* The default ? */
+ bfd_default_compatible, /* Architecture comparison fn. */
+ bfd_default_scan, /* String to architecture convert fn. */
NULL /* Next in list. */
-}
+},
};
const bfd_arch_info_type bfd_ms1_arch =
{
case EF_MS1_CPU_MRISC: return bfd_mach_ms1;
case EF_MS1_CPU_MRISC2: return bfd_mach_mrisc2;
+ case EF_MS1_CPU_MS2: return bfd_mach_ms2;
}
return bfd_mach_ms1;
{
flagword old_flags, new_flags;
bfd_boolean error = FALSE;
- static bfd * last_ibfd = 0;
/* Check if we have the same endianess. */
if (_bfd_generic_verify_endian_match (ibfd, obfd) == FALSE)
ibfd, old_flags, new_flags, elf_flags_init (obfd) ? "yes" : "no");
#endif
- elf_flags_init (obfd) = TRUE;
-
- if ((new_flags & EF_MS1_CPU_MASK) == EF_MS1_CPU_MRISC2)
+ if (!elf_flags_init (obfd))
+ {
+ old_flags = new_flags;
+ elf_flags_init (obfd) = TRUE;
+ }
+ else if ((new_flags & EF_MS1_CPU_MASK) != (old_flags & EF_MS1_CPU_MASK))
+ {
+ /* CPU has changed. This is invalid, because MRISC, MRISC2 and
+ MS2 are not subsets of each other. */
+ error = 1;
+
+ /* FIXME:However, until the compiler is multilibbed, preventing
+ mixing breaks the build. So we allow merging and use the
+ greater CPU value. This is of course unsafe. */
+ error = 0;
+ if ((new_flags & EF_MS1_CPU_MASK) > (old_flags & EF_MS1_CPU_MASK))
+ old_flags = ((old_flags & ~EF_MS1_CPU_MASK)
+ | (new_flags & EF_MS1_CPU_MASK));
+ }
+ if (!error)
{
- elf_elfheader (obfd)->e_flags = new_flags;
- last_ibfd = ibfd;
obfd->arch_info = ibfd->arch_info;
+ elf_elfheader (obfd)->e_flags = old_flags;
}
return !error;
switch (flags & EF_MS1_CPU_MASK)
{
default:
- case EF_MS1_CPU_MRISC: fprintf (file, " ms1-16-002"); break;
+ case EF_MS1_CPU_MRISC: fprintf (file, " ms1-16-002"); break;
case EF_MS1_CPU_MRISC2: fprintf (file, " ms1-16-003"); break;
+ case EF_MS1_CPU_MS2: fprintf (file, " ms2"); break;
}
fputc ('\n', file);
"BFD_RELOC_MS1_LO16",
"BFD_RELOC_MS1_GNU_VTINHERIT",
"BFD_RELOC_MS1_GNU_VTENTRY",
+ "BFD_RELOC_MS1_PCINSN8",
"BFD_RELOC_MSP430_10_PCREL",
"BFD_RELOC_MSP430_16_PCREL",
"BFD_RELOC_MSP430_16",
BFD_RELOC_MS1_GNU_VTENTRY
ENUMDOC
Morpho MS1 - Used to tell the linker which vtable entries are used.
+ENUM
+ BFD_RELOC_MS1_PCINSN8
+ENUMDOC
+ Morpho MS1 - 8 bit immediate relocation.
ENUM
BFD_RELOC_MSP430_10_PCREL
+2005-11-08 Nathan Sidwell <nathan@codesourcery.com>
+
+ Add ms2
+ * ms1.cpu (ms2, ms2bf): New architecture variant, cpu, machine and
+ model.
+ (f-uu8, f-uu1, f-imm16l, f-loopo, f-cb1sel, f-cb2sel, f-cb1incr,
+ f-cb2incr, f-rc3): New fields.
+ (LOOP): New instruction.
+ (JAL-HAZARD): New hazard.
+ (imm16o, loopsize, imm16l, rc3, cb1sel, cb2sel, cb1incr, cb2incr):
+ New operands.
+ (mul, muli, dbnz, iflush): Enable for ms2
+ (jal, reti): Has JAL-HAZARD.
+ (ldctxt, ldfb, stfb): Only ms1.
+ (fbcb): Only ms1,ms1-003.
+ (wfbinc, mefbinc, wfbincr, mwfbincr, fbcbincs, mfbcbincs,
+ fbcbincrs, mfbcbincrs): Enable for ms2.
+ (loop, loopu, dfbc, dwfb, fbwfb, dfbr): New ms2 insns.
+ * ms1.opc (parse_loopsize): New.
+ (parse_imm16): hi16/lo16 relocs are applicable to IMM16L.
+ (print_pcrel): New.
+
2005-10-28 Dave Brolley <brolley@redhat.com>
Contribute the following change:
(comment "Morpho Technologies mRISC family")
(default-alignment aligned)
(insn-lsb0? #t)
- (machs ms1 ms1-003)
+ (machs ms1 ms1-003 ms2)
(isas ms1)
)
(word-bitsize 32)
)
+(define-cpu
+ ; cpu names must be distinct from the architecture name and machine names.
+ (name ms2bf)
+ (comment "Morpho Technologies mRISC family")
+ (endian big)
+ (word-bitsize 32)
+)
+
(define-mach
(name ms1)
(comment "Morpho Technologies mrisc")
(isas ms1)
)
+(define-mach
+ (name ms2)
+ (comment "Morpho Technologies ms2")
+ (cpu ms2bf)
+ (isas ms1)
+)
+
\f
; Model descriptions.
; Can probably take the u-exec out. We'll see.
)
)
-; Macros to simplify MACH attribute specification.
-
-(define-pmacro MACHMS1 (MACH ms1))
-(define-pmacro MACHMS1-003 (MACH ms1-003))
+(define-model
+ (name ms2)
+ (comment "Morpho Technologies ms2")
+ (mach ms2)
+ (unit u-exec "Execution Unit" ()
+ 1 1 ; issue done
+ () ; state
+ () ; inputs
+ () ; outputs
+ () ; profile action (default)
+ )
+)
; FIXME: It might simplify things to separate the execute process from the
; one that updates the PC.
; f-imm16a: 16 bit immediate value when it's a pc-rel offset.
; f-uu4a: unused 4 bit field.
; f-uu4b: second unsed 4 bit field.
+; f-uu1: unused 1 bit field
; f-uu12: unused 12 bit field.
; f-uu16: unused 16 bit field.
; f-uu24: unused 24 bit field.
(dnf f-uu4a "unused 4 bit field" () 19 4)
(dnf f-uu4b "unused 4 bit field" () 23 4)
(dnf f-uu12 "unused 12 bit field" () 11 12)
+(dnf f-uu8 "unused 8 bit field" () 15 8)
(dnf f-uu16 "unused 16 bit field" () 15 16)
+(dnf f-uu1 "unused 1 bit field" () 7 1)
; The following ifields are used exclusively for the MorphoSys instructions.
; In a few cases, a bit field is used for something in addition to what its
(dnf f-rc2 "rc2" () 6 1)
(dnf f-ctxdisp "context displacement" () 5 6)
+; additional fields in ms2
+(dnf f-imm16l "loop count" () 23 16)
+(df f-loopo "loop offset" () 7 8 UINT
+ ((value pc) (srl SI value 2))
+ ((value pc) (add SI (sll value 2) 8))
+ )
+(dnf f-cb1sel "cb1 select" () 25 3)
+(dnf f-cb2sel "cb2 select" () 22 3)
+(dnf f-cb1incr "cb1 increment" (SIGNED) 19 6)
+(dnf f-cb2incr "cb2 increment" (SIGNED) 13 6)
+(dnf f-rc3 "row/colum context" () 7 1)
; The following is just for a test
(dnf f-msysfrsr2 "sr2 for msys" () 19 4)
(ADD ADDU SUB SUBU MUL - - -
AND OR XOR NAND NOR XNOR LDUI -
LSL LSR ASR - - - - -
- BRLT BRLE BREQ JMP JAL BRNEQ DBNZ -
+ BRLT BRLE BREQ JMP JAL BRNEQ DBNZ LOOP
LDW STW - - - - - -
- - - - - - - -
EI DI SI RETI BREAK IFLUSH - -
; insn-imm: bit 24. Immediate operand indicator.
(define-normal-insn-enum insn-imm "imm enums" () IMM_ f-imm
; This bit specifies whether and immediate operand will be present.
- ; It's 1 if ther is, 0 if there is not.
+ ; It's 1 if there is, 0 if there is not.
(NO YES)
)
;;;;;;;;;;;;;;;;
(comment "insn performs an I/O operation")
)
+(define-attr
+ (for insn)
+ (type boolean)
+ (name JAL-HAZARD)
+ (comment "insn has jal-like hazard")
+)
+
(define-pmacro (define-reg-use-attr regfield)
(define-attr
(for insn)
(type h-sint) (index f-imm16s) (handlers (parse "imm16") (print "dollarhex")))
(define-operand (name imm16z) (comment "immediate value - zero extd") (attrs)
(type h-uint) (index f-imm16u) (handlers (parse "imm16") (print "dollarhex")))
-(define-operand (name imm16o) (comment "immediate value") (attrs)
- (type h-uint) (index f-imm16s) (handlers (parse "imm16") (print "dollarhex")))
+(define-operand (name imm16o) (comment "immediate value") (attrs PCREL-ADDR)
+ (type h-uint) (index f-imm16s) (handlers (parse "imm16") (print "pcrel")))
; Operands for MorphoSys Instructions
(define-operand (name fbincr) (comment "fb incr") (attrs)
(type h-uint) (index f-fbincr) (handlers (print "dollarhex")))
+; For the ms2 insns
+(define-operand (name loopsize) (comment "immediate value")
+ (attrs (MACH ms2) PCREL-ADDR)
+ (type h-uint) (index f-loopo) (handlers (parse "loopsize") (print "pcrel")))
+(define-operand (name imm16l) (comment "immediate value")
+ (attrs (MACH ms2))
+ (type h-uint) (index f-imm16l) (handlers (print "dollarhex")))
+(define-operand (name rc3) (comment "rc3") (attrs (MACH ms2))
+ (type h-uint) (index f-rc3) (handlers (parse "rc") (print "dollarhex")))
+(define-operand (name cb1sel) (comment "cb1sel") (attrs (MACH ms2))
+ (type h-uint) (index f-cb1sel) (handlers (print "dollarhex")))
+(define-operand (name cb2sel) (comment "cb2sel") (attrs (MACH ms2))
+ (type h-uint) (index f-cb2sel) (handlers (print "dollarhex")))
+(define-operand (name cb1incr) (comment "cb1incr") (attrs (MACH ms2))
+ (type h-sint) (index f-cb1incr) (handlers (print "dollarhex")))
+(define-operand (name cb2incr) (comment "cb2incr") (attrs (MACH ms2))
+ (type h-sint) (index f-cb2incr) (handlers (print "dollarhex")))
+
; Probaby won't need most of these.
(define-pmacro r0 (reg h-spr #x0))
(define-pmacro r1 (reg h-spr #x01))
)
(dni mul "MUL DstReg, SrcReg1, SrcReg2"
- (MACHMS1-003 AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
+ ((MACH ms1-003,ms2) AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
"mul $frdrrr,$frsr1,$frsr2"
(+ MSYS_NO OPC_MUL IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
(sequence((HI op1) (HI op2))
)
(dni muli "MULI DstReg, SrcReg1, UnsImm"
- (MACHMS1-003 AL-INSN USES-FRDR USES-FRSR1)
+ ((MACH ms1-003,ms2) AL-INSN USES-FRDR USES-FRSR1)
"muli $frdr,$frsr1,#$imm16"
(+ MSYS_NO OPC_MUL IMM_YES frsr1 frdr imm16)
(sequence((HI op1) (HI op2))
)
(dni jal "JAL DstReg, SrcReg1"
- (BR-INSN DELAY-SLOT BR-INSN USES-FRDR USES-FRSR1)
+ (BR-INSN DELAY-SLOT BR-INSN USES-FRDR USES-FRSR1 JAL-HAZARD)
"jal $frdrrr,$frsr1"
(+ MSYS_NO OPC_JAL IMM_NO frsr1 (f-uu4a 0) frdrrr (f-uu12 0))
(sequence()
)
(dni dbnz "DBNZ SrcReg1, label"
- (MACHMS1-003 BR-INSN DELAY-SLOT USES-FRSR1)
+ ((MACH ms1-003,ms2) BR-INSN DELAY-SLOT USES-FRSR1)
"dbnz $frsr1,$imm16o"
(+ MSYS_NO OPC_DBNZ IMM_YES frsr1 (f-uu4a 0) imm16o)
(sequence()
)
(dni reti "RETI SrcReg1"
- (DELAY-SLOT BR-INSN USES-FRSR1)
+ (DELAY-SLOT BR-INSN USES-FRSR1 JAL-HAZARD)
"reti $frsr1"
(+ MSYS_NO OPC_RETI IMM_NO frsr1 (f-uu4a 0) (f-uu16 0))
(sequence()
; Cache Flush Instruction
(dni iflush "IFLUSH"
- (MACHMS1-003)
+ ((MACH ms1-003,ms2))
"iflush"
(+ MSYS_NO OPC_IFLUSH (f-imm 0) (f-uu24 0))
(nop)
; MorphoSys Instructions
(dni ldctxt "LDCTXT SRC1, SRC2, r/c, r/c#, context#"
- ()
+ ((MACH ms1))
"ldctxt $frsr1,$frsr2,#$rc,#$rcnum,#$contnum"
(+ MSYS_YES MSOPC_LDCTXT (f-uu-2-25 0) frsr1 frsr2 rc rcnum (f-uu-3-11 0)
contnum )
)
(dni ldfb "LDFB SRC1, byte#"
- ()
+ ((MACH ms1))
"ldfb $frsr1,$frsr2,#$imm16z"
(+ MSYS_YES MSOPC_LDFB (f-uu-2-25 0) frsr1 frsr2 imm16z)
(nop)
)
(dni stfb "STFB SRC1, SRC2, byte "
- ()
+ ((MACH ms1))
"stfb $frsr1,$frsr2,#$imm16z"
(+ MSYS_YES MSOPC_STFB (f-uu-2-25 0) frsr1 frsr2 imm16z)
(nop)
)
(dni fbcb "FBCB SRC1, RT/BR1/BR2/CS, B_all, B_r_c, r/c, CB/RB, cell, dup, ctx_disp"
- ()
+ ((MACH ms1,ms1-003))
"fbcb $frsr1,#$rbbc,#$ball,#$brc,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_FBCB rbbc frsr1 ball brc (f-uu-4-15 0) rc cbrb cell dup ctxdisp)
(nop)
;; Issue 66262: The documenatation gives the wrong order for
;; the arguments to the WFBINC instruction.
(dni wfbinc "WFBINC type, ccb/rcb, incr, all, c/r, length, rca_row, word, dup, ctxt_disp"
- (MACHMS1-003)
+ ((MACH ms1-003,ms2))
"wfbinc #$rda,#$wr,#$fbincr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_WFBINC rda wr fbincr ball colnum length rownum1 rownum2 dup ctxdisp)
(nop)
)
(dni mwfbinc "MWFBINC mreg, type, ccb/rcb, incr, length, rca_row, word, dup, ctxt_disp"
- (MACHMS1-003)
+ ((MACH ms1-003,ms2))
"mwfbinc $frsr2,#$rda,#$wr,#$fbincr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_MWFBINC rda wr fbincr frsr2 length rownum1 rownum2 dup ctxdisp)
(nop)
)
(dni wfbincr "WFBINCR ireg, type, ccb/rcb, all, c/r, length, rca_row, word, dup, ctxt_disp"
- (MACHMS1-003)
+ ((MACH ms1-003,ms2))
"wfbincr $frsr1,#$rda,#$wr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_WFBINCR rda wr frsr1 ball colnum length rownum1 rownum2 dup ctxdisp)
(nop)
)
(dni mwfbincr "MWFBINCR ireg, mreg, type, ccb/rcb, length, rca_row, word, dup, ctxt_disp"
- (MACHMS1-003)
+ ((MACH ms1-003,ms2))
"mwfbincr $frsr1,$frsr2,#$rda,#$wr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_MWFBINCR rda wr frsr1 frsr2 length rownum1 rownum2 dup ctxdisp)
(nop)
)
(dni fbcbincs "FBCBINCS perm, all, c/r, cbs, incr, ccb/rcb, cdb/rdb, word, dup, ctxt_disp"
- (MACHMS1-003)
+ ((MACH ms1-003,ms2))
"fbcbincs #$perm,#$a23,#$cr,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_FBCBINCS perm a23 cr cbs incr ccb cdb rownum2 dup ctxdisp)
(nop)
)
(dni mfbcbincs "MFBCBINCS ireg, perm, cbs, incr, ccb/rcb, cdb/rdb, word, dup, ctxt_disp"
- (MACHMS1-003)
+ ((MACH ms1-003,ms2))
"mfbcbincs $frsr1,#$perm,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_MFBCBINCS perm frsr1 cbs incr ccb cdb rownum2 dup ctxdisp)
(nop)
)
(dni fbcbincrs "FBCBINCRS ireg, perm, all, c/r, cbs, ccb/rcb, cdb/rdb, word, dup, ctxt_disp"
- (MACHMS1-003)
+ ((MACH ms1-003,ms2))
"fbcbincrs $frsr1,#$perm,#$ball,#$colnum,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_FBCBINCRS perm frsr1 ball colnum (f-uu-1-15 0) cbx ccb cdb rownum2 dup ctxdisp)
(nop)
)
(dni mfbcbincrs "MFBCBINCRS ireg, mreg, perm, cbs, ccb/rcb, cdb/rdb, word, dup, ctxt_disp"
- (MACHMS1-003)
+ ((MACH ms1-003,ms2))
"mfbcbincrs $frsr1,$frsr2,#$perm,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_MFBCBINCRS perm frsr1 frsr2 (f-uu-1-15 0) cbx ccb cdb rownum2 dup ctxdisp)
(nop)
()
)
+
+; MS2 instructions
+(dni loop "LOOP SrcReg1, label"
+ ((MACH ms2) DELAY-SLOT USES-FRSR1)
+ "loop $frsr1,$loopsize"
+ (+ MSYS_NO OPC_LOOP IMM_NO frsr1 (f-uu4a 0) (f-uu8 0) loopsize)
+ (nop) ;; to be filled in
+ ()
+)
+
+(dni loopi "LOOPI niter, label"
+ ((MACH ms2) DELAY-SLOT)
+ "loopi #$imm16l,$loopsize"
+ (+ MSYS_NO OPC_LOOP IMM_YES imm16l loopsize)
+ (nop) ;; to be filled in
+ ()
+)
+
+(dni dfbc "dfbc cb1sel,cb2sel,cb1inc,cb2inc,dr/c,cr/c,ctxdisp"
+ ((MACH ms2))
+ "dfbc #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp"
+ (+ MSYS_YES MSOPC_LDCTXT cb1sel cb2sel cb1incr cb2incr rc3 rc2 ctxdisp)
+ (nop)
+ ()
+)
+
+(dni dwfb "dwfb cb1sel,cb2sel,cb1inc,cb2inc,cr/c,ctxdisp"
+ ((MACH ms2))
+ "dwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc2,#$ctxdisp"
+ (+ MSYS_YES MSOPC_LDFB cb1sel cb2sel cb1incr cb2incr (f-uu1 0) rc2 ctxdisp)
+ (nop)
+ ()
+)
+
+(dni fbwfb "fbwfb cb1sel,cb2sel,cb1inc,cb2inc,r0/1,cr/c,ctxdisp"
+ ((MACH ms2))
+ "fbwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp"
+ (+ MSYS_YES MSOPC_STFB cb1sel cb2sel cb1incr cb2incr rc3 rc2 ctxdisp)
+ (nop)
+ ()
+)
+
+(dni dfbr "dfbr cb1sel,cb2sel,reg,W/O1,W/O2,mode,cr/c,ctxdisp"
+ ((MACH ms2) USES-FRSR2)
+ "dfbr #$cb1sel,#$cb2sel,$frsr2,#$length,#$rownum1,#$rownum2,#$rc2,#$ctxdisp"
+ (+ MSYS_YES MSOPC_FBCB cb1sel cb2sel frsr2 length rownum1 rownum2 rc2 ctxdisp)
+ (nop)
+ ()
+)
}
static const char *
+parse_loopsize (CGEN_CPU_DESC cd,
+ const char **strp,
+ int opindex,
+ void *arg)
+{
+ signed long * valuep = (signed long *) arg;
+ const char *errmsg;
+ bfd_reloc_code_real_type code = BFD_RELOC_NONE;
+ enum cgen_parse_operand_result result_type;
+ bfd_vma value;
+
+ /* Is it a control transfer instructions? */
+ if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_LOOPSIZE)
+ {
+ code = BFD_RELOC_MS1_PCINSN8;
+ errmsg = cgen_parse_address (cd, strp, opindex, code,
+ & result_type, & value);
+ *valuep = value;
+ return errmsg;
+ }
+
+ abort ();
+}
+
+static const char *
parse_imm16 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
/* If it's not a control transfer instruction, then
we have to check for %OP relocating operators. */
- if (strncmp (*strp, "%hi16", 5) == 0)
+ if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_IMM16L)
+ ;
+ else if (strncmp (*strp, "%hi16", 5) == 0)
{
*strp += 5;
code = BFD_RELOC_HI16;
/* -- dis.c */
static void print_dollarhex (CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int);
+static void print_pcrel (CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int);
static void
print_dollarhex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
print_normal (cd, dis_info, value, attrs, pc, length);
}
+static void
+print_pcrel (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ void * dis_info,
+ long value,
+ unsigned int attrs ATTRIBUTE_UNUSED,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED)
+{
+ print_address (cd, dis_info, value + pc, attrs, pc, length);
+}
/* -- */
+2005-11-08 Nathan Sidwell <nathan@codesourcery.com>
+
+ Add ms2 support.
+ * config/tc-ms1.c (ms1_mach_bitmask): Initialize to MS1.
+ (ms1_architectures): Add ms2.
+ (md_parse_option): Add ms2.
+ (md_show_usage): Add ms2.
+ (md_assemble): Add JAL_HAZARD detection logic.
+ (md_cgen_lookup_reloc): Add MS1_OPERAND_LOOPSIZE case.
+ * doc/c-ms1.texi: New.
+ * doc/all.texi: Add MS1.
+ * doc/Makefile.am (CPU_DOCS): Add c-ms1.texi.
+ * doc/Makefile.in: Rebuilt.
+ * doc/Makefile: Rebuilt.
+
2005-11-07 Steve Ellcey <sje@cup.hp.com>
* configure: Regenerate after modifying bfd/warning.m4.
/* Mach selected from command line. */
static int ms1_mach = bfd_mach_ms1;
-static unsigned ms1_mach_bitmask = 0;
+static unsigned ms1_mach_bitmask = 1 << MACH_MS1;
/* Flags to set in the elf header */
static flagword ms1_flags = EF_MS1_CPU_MRISC;
{
ms1_64_001,
ms1_16_002,
- ms1_16_003
+ ms1_16_003,
+ ms2
};
/* MS1 architecture we are using for this output file. */
ms1_mach_bitmask = 1 << MACH_MS1_003;
ms1_arch = ms1_16_003;
}
+ else if (strcasecmp (arg, "MS2") == 0)
+ {
+ ms1_flags = (ms1_flags & ~EF_MS1_CPU_MASK) | EF_MS1_CPU_MS2;
+ ms1_mach = bfd_mach_mrisc2;
+ ms1_mach_bitmask = 1 << MACH_MS2;
+ ms1_arch = ms2;
+ }
case OPTION_NO_SCHED_REST:
no_scheduling_restrictions = 1;
break;
fprintf (stream, _(" -march=ms1-64-001 allow ms1-64-001 instructions (default) \n"));
fprintf (stream, _(" -march=ms1-16-002 allow ms1-16-002 instructions \n"));
fprintf (stream, _(" -march=ms1-16-003 allow ms1-16-003 instructions \n"));
+ fprintf (stream, _(" -march=ms2 allow ms2 instructions \n"));
fprintf (stream, _(" -nosched disable scheduling restrictions \n"));
}
md_assemble (char * str)
{
static long delayed_load_register = 0;
+ static long prev_delayed_load_register = 0;
static int last_insn_had_delay_slot = 0;
static int last_insn_in_noncond_delay_slot = 0;
static int last_insn_has_load_delay = 0;
insn.fields.f_sr2);
}
+ /* Detect JAL/RETI hazard */
+ if (ms1_mach == ms2
+ && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_JAL_HAZARD))
+ {
+ if ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR1)
+ && insn.fields.f_sr1 == delayed_load_register)
+ || (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2)
+ && insn.fields.f_sr2 == delayed_load_register))
+ as_warn (_("operand references R%ld of previous instrutcion."),
+ delayed_load_register);
+ else if ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR1)
+ && insn.fields.f_sr1 == prev_delayed_load_register)
+ || (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2)
+ && insn.fields.f_sr2 == prev_delayed_load_register))
+ as_warn (_("operand references R%ld of instructcion before previous."),
+ prev_delayed_load_register);
+ }
+
/* Detect data dependency between conditional branch instruction
and an immediately preceding arithmetic or logical instruction. */
if (last_insn_was_arithmetic_or_logic
CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_BR_INSN)
&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2);
+ prev_delayed_load_register = delayed_load_register;
+
if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRDR))
delayed_load_register = insn.fields.f_dr;
else if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRDRRR))
result = fixP->fx_cgen.opinfo;
fixP->fx_no_overflow = 1;
break;
+ case MS1_OPERAND_LOOPSIZE:
+ result = BFD_RELOC_MS1_PCINSN8;
+ fixP->fx_pcrel = 1;
+ /* Adjust for the delay slot, which is not part of the loop */
+ fixP->fx_offset -= 8;
+ break;
default:
result = BFD_RELOC_NONE;
break;
c-m68k.texi \
c-mips.texi \
c-mmix.texi \
+ c-ms1.texi \
c-msp430.texi \
c-ns32k.texi \
c-pdp11.texi \
c-m68k.texi \
c-mips.texi \
c-mmix.texi \
+ c-ms1.texi \
c-msp430.texi \
c-ns32k.texi \
c-pdp11.texi \
@set MCORE
@set MIPS
@set MMIX
+@set MS1
@set MSP430
@set PDP11
@set PJ
--- /dev/null
+@c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
+@c Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+
+@ifset GENERIC
+@page
+@node MS1-Dependent
+@chapter MS1 Dependent Features
+@end ifset
+
+@ifclear GENERIC
+@node Machine Dependencies
+@chapter MS1 Dependent Features
+@end ifclear
+
+@cindex MS1 support
+@menu
+* MS1 Options:: Options
+@end menu
+
+@node MS1 Options
+@section Options
+@cindex MS1 options (none)
+@cindex options for MS1 (none)
+
+@table @code
+
+@cindex @code{-march=} command line option, MS1
+@item -march=@var{processor}
+This option specifies the target processor. The assembler will issue an
+error message if an attempt is made to assemble an instruction which
+will not execute on the target processor. The following processor names are
+recognized:
+@code{ms1-64-001},
+@code{ms1-16-002},
+@code{ms1-16-003},
+and @code{ms2}.
+
+@cindex @code{-nosched} command line option, MS1
+@item -nosched
+This option disables scheduling restriction checking.
+
+@end table
+2005-11-08 Nathan Sidwell <nathan@codesourcery.com>
+
+ Add ms2.
+ * gas/ms1/allinsn.d: Adjust pcrel disassembly.
+ * gas/ms1/errors.exp: Fix target triplet.
+ * gas/ms1/ms1-16-003.d: Adjust pcrel disassembly.
+ * gas/ms1/ms1-16-003.s: Tweak label.
+ * gas/ms1/ms1.exp: Adjust target triplet. Add ms2 test.
+ * gas/ms1/ms2.d, gas/ms1/ms2.s: New.
+ * gas/ms1/relocs.d: Adjust expected machine name and pcrel
+ disassembly.
+ * gas/ms1/relocs.exp: Adjust target triplet.
+
2005-11-07 Jan Beulich <jbeulich@novell.com>
* gas/all/redef2.[sd]: New.
68: 25 00 00 00 asri R0,R0,#\$0
0000006c <brlt>:
- 6c: 31 00 00 00 brlt R0,R0,\$0
+ 6c: 31 00 00 00 brlt R0,R0,6c <brlt>
00000070 <brle>:
- 70: 33 00 00 00 brle R0,R0,\$0
+ 70: 33 00 00 00 brle R0,R0,70 <brle>
00000074 <breq>:
- 74: 35 00 00 00 breq R0,R0,\$0
+ 74: 35 00 00 00 breq R0,R0,74 <breq>
00000078 <jmp>:
- 78: 37 00 00 00 jmp \$0
+ 78: 37 00 00 00 jmp 78 <jmp>
0000007c <jal>:
7c: 38 00 00 00 jal R0,R0
94: 64 00 00 00 si R0
00000098 <brne>:
- 98: 3b 00 00 00 brne R0,R0,\$0
+ 98: 3b 00 00 00 brne R0,R0,98 <brne>
0000009c <break>:
9c: 68 00 00 00 break
}
}
-if [istarget mrisc1*-*-*] {
+if [istarget ms1-*-*] {
foreach file [glob -nocomplain -- $srcdir/$subdir/bad*.s] {
set file [file tail $file]
switch -- $file {
4: 08 00 00 00 mul R0,R0,R0
00000008 <muli>:
8: 09 00 00 00 muli R0,R0,#\$0
-0000000c <dbnz>:
- c: 3d 00 00 00 dbnz R0,\$0
+0000000c <dbnz_>:
+ c: 3d 00 00 00 dbnz R0,c <dbnz_>
[ ]*c: R_MS1_PC16 dbnz
00000010 <fbcbincs>:
10: f0 00 00 00 fbcbincs #\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
muli R0, R0, #0
.global dbnz
-dbnz:
+dbnz_:
dbnz r0, dbnz
.global fbcbincs
# MRISC1 assembler testsuite.
-if { [istarget mrisc1*-*-*] || [istarget ms1-*-*]} then {
+if [istarget ms1*-*-*] {
#
run_dump_test "allinsn"
run_dump_test "misc"
run_dump_test "msys"
run_dump_test "ms1-16-003"
+ run_dump_test "ms2"
#
}
--- /dev/null
+#as: -march=ms2
+#objdump: -dr
+#name: ms2
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <code>:
+ 0: 3e 10 00 05 loop R1,1c <label>
+ 4: 3f 00 10 04 loopi #\$10,1c <label>
+ 8: 83 ff ff ff dfbc #\$7,#\$7,#\$ffffffff,#\$ffffffff,#\$1,#\$1,#\$3f
+ c: 87 ff ff 7f dwfb #\$7,#\$7,#\$ffffffff,#\$ffffffff,#\$1,#\$3f
+ 10: 8b ff ff ff fbwfb #\$7,#\$7,#\$ffffffff,#\$ffffffff,#\$1,#\$1,#\$3f
+ 14: 8f f0 ff ff dfbr #\$7,#\$7,R0,#\$7,#\$7,#\$7,#\$1,#\$3f
+ 18: 12 00 00 00 nop
+0000001c <label>:
+ 1c: f0 00 00 00 fbcbincs #\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
--- /dev/null
+
+code:
+ loop R1, label
+ loopi #16,label
+ dfbc #7,#7,#-1,#-1,#1,#1,#63
+ dwfb #7,#7,#-1,#-1,#1,#63
+ fbwfb #7,#7,#-1,#-1,#1,#1,#63
+ dfbr #7,#7,R0,#7,#7,#7,#1,#63
+ nop
+label:
+ fbcbincs #0,#0,#0,#0,#0,#0,#0,#0,#0,#0
-relocs.x: file format elf32-mrisc1
+relocs.x: file format elf32-(mrisc1|ms1)
Contents of section .text:
- 2000 00131000 37000004 12000000 3700fff8 ....7.......7...
+ 2000 00131000 3700dffc 12000000 3700fff8 ....7.......7...
2010 03210000 03212215 03210001 03210000 .!...!"..!...!..
2020 0321ffff 0321eeee 03210005 03210006 .!...!...!...!..
2030 00675000 .gP.
22f4 00000000 00000000 00000000 00000000 ................
2304 00000000 00000000 00000000 00000000 ................
2314 000003 ...
-Contents of section .sbss:
+Contents of section .stack:
+ 7ffff0 deaddead ....
Disassembly of section .text:
00002000 <_start>:
2000: 00 13 10 00 add R1,R1,R3
00002004 <local>:
- 2004: 37 00 00 04 jmp \$4
+ 2004: 37 00 df fc jmp 0 <_start-0x2000>
00002008 <none>:
- 2008: 12 00 00 00 or R0,R0,R0
- 200c: 37 00 ff f8 jmp \$fffffff8
+ 2008: 12 00 00 00 nop
+ 200c: 37 00 ff f8 jmp 2004 <local>
2010: 03 21 00 00 addui R1,R2,#\$0
2014: 03 21 22 15 addui R1,R2,#\$2215
2018: 03 21 00 01 addui R1,R2,#\$1
global srcdir subdir
-if [istarget mrisc1*-*-* || istarget ms1-*] {
+if [istarget ms1-*] {
gas_test "relocs1.s" {-o relocs1.o} {} {assembling relocs1}
# gas_test "relocs2.s" {-o relocs2.o} {} {assembling relocs2}
+2005-11-07 Nathan Sidwell <nathan@codesourcery.com>
+
+ Add ms2.
+ * elf/ms1.h (EF_MS1_CPU_MS2): New.
+
2005-11-06 John David Anglin <dave.anglin@nrc-crnc.gc.ca>
* elf/hppa.h (R_PARISC_DIR64WR, R_PARISC_DIR64DR): Remove relocs.
#define EF_MS1_CPU_MRISC 0x00000001 /* default */
#define EF_MS1_CPU_MRISC2 0x00000002 /* MRISC2 */
+#define EF_MS1_CPU_MS2 0x00000003 /* MS2 */
#define EF_MS1_CPU_MASK 0x00000003 /* specific cpu bits */
#define EF_MS1_ALL_FLAGS (EF_MS1_CPU_MASK)
+2005-11-08 Nathan Sidwell <nathan@codesourcery.com>
+
+ Add ms2.
+ * ms1-asm.c, ms1-desc.c, ms1-desc.h, ms1-dis.c, ms1-ibld.c,
+ ms1-opc.c, ms1-opc.h: Regenerated.
+
2005-11-07 Steve Ellcey <sje@cup.hp.com>
* configure: Regenerate after modifying bfd/warning.m4.
}
static const char *
+parse_loopsize (CGEN_CPU_DESC cd,
+ const char **strp,
+ int opindex,
+ void *arg)
+{
+ signed long * valuep = (signed long *) arg;
+ const char *errmsg;
+ bfd_reloc_code_real_type code = BFD_RELOC_NONE;
+ enum cgen_parse_operand_result result_type;
+ bfd_vma value;
+
+ /* Is it a control transfer instructions? */
+ if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_LOOPSIZE)
+ {
+ code = BFD_RELOC_MS1_PCINSN8;
+ errmsg = cgen_parse_address (cd, strp, opindex, code,
+ & result_type, & value);
+ *valuep = value;
+ return errmsg;
+ }
+
+ abort ();
+}
+
+static const char *
parse_imm16 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
/* If it's not a control transfer instruction, then
we have to check for %OP relocating operators. */
- if (strncmp (*strp, "%hi16", 5) == 0)
+ if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_IMM16L)
+ ;
+ else if (strncmp (*strp, "%hi16", 5) == 0)
{
*strp += 5;
code = BFD_RELOC_HI16;
case MS1_OPERAND_BRC2 :
errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_BRC2, (unsigned long *) (& fields->f_brc2));
break;
+ case MS1_OPERAND_CB1INCR :
+ errmsg = cgen_parse_signed_integer (cd, strp, MS1_OPERAND_CB1INCR, (long *) (& fields->f_cb1incr));
+ break;
+ case MS1_OPERAND_CB1SEL :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CB1SEL, (unsigned long *) (& fields->f_cb1sel));
+ break;
+ case MS1_OPERAND_CB2INCR :
+ errmsg = cgen_parse_signed_integer (cd, strp, MS1_OPERAND_CB2INCR, (long *) (& fields->f_cb2incr));
+ break;
+ case MS1_OPERAND_CB2SEL :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CB2SEL, (unsigned long *) (& fields->f_cb2sel));
+ break;
case MS1_OPERAND_CBRB :
errmsg = parse_cbrb (cd, strp, MS1_OPERAND_CBRB, (unsigned long *) (& fields->f_cbrb));
break;
case MS1_OPERAND_IMM16 :
errmsg = parse_imm16 (cd, strp, MS1_OPERAND_IMM16, (long *) (& fields->f_imm16s));
break;
+ case MS1_OPERAND_IMM16L :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_IMM16L, (unsigned long *) (& fields->f_imm16l));
+ break;
case MS1_OPERAND_IMM16O :
errmsg = parse_imm16 (cd, strp, MS1_OPERAND_IMM16O, (unsigned long *) (& fields->f_imm16s));
break;
case MS1_OPERAND_LENGTH :
errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_LENGTH, (unsigned long *) (& fields->f_length));
break;
+ case MS1_OPERAND_LOOPSIZE :
+ errmsg = parse_loopsize (cd, strp, MS1_OPERAND_LOOPSIZE, (unsigned long *) (& fields->f_loopo));
+ break;
case MS1_OPERAND_MASK :
errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_MASK, (unsigned long *) (& fields->f_mask));
break;
case MS1_OPERAND_RC2 :
errmsg = parse_rc (cd, strp, MS1_OPERAND_RC2, (unsigned long *) (& fields->f_rc2));
break;
+ case MS1_OPERAND_RC3 :
+ errmsg = parse_rc (cd, strp, MS1_OPERAND_RC3, (unsigned long *) (& fields->f_rc3));
+ break;
case MS1_OPERAND_RCNUM :
errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_RCNUM, (unsigned long *) (& fields->f_rcnum));
break;
{ "base", MACH_BASE },
{ "ms1", MACH_MS1 },
{ "ms1_003", MACH_MS1_003 },
+ { "ms2", MACH_MS2 },
{ "max", MACH_MAX },
{ 0, 0 }
};
{ "AL-INSN", &bool_attr[0], &bool_attr[0] },
{ "IO-INSN", &bool_attr[0], &bool_attr[0] },
{ "BR-INSN", &bool_attr[0], &bool_attr[0] },
+ { "JAL-HAZARD", &bool_attr[0], &bool_attr[0] },
{ "USES-FRDR", &bool_attr[0], &bool_attr[0] },
{ "USES-FRDRRR", &bool_attr[0], &bool_attr[0] },
{ "USES-FRSR1", &bool_attr[0], &bool_attr[0] },
static const CGEN_MACH ms1_cgen_mach_table[] = {
{ "ms1", "ms1", MACH_MS1, 0 },
{ "ms1-003", "ms1-003", MACH_MS1_003, 0 },
+ { "ms2", "ms2", MACH_MS2, 0 },
{ 0, 0, 0, 0 }
};
{ MS1_F_UU4A, "f-uu4a", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ MS1_F_UU4B, "f-uu4b", 0, 32, 23, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ MS1_F_UU12, "f-uu12", 0, 32, 11, 12, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MS1_F_UU8, "f-uu8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ MS1_F_UU16, "f-uu16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MS1_F_UU1, "f-uu1", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ MS1_F_MSOPC, "f-msopc", 0, 32, 30, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ MS1_F_UU_26_25, "f-uu-26-25", 0, 32, 25, 26, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ MS1_F_MASK, "f-mask", 0, 32, 25, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ MS1_F_DUP, "f-dup", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ MS1_F_RC2, "f-rc2", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ MS1_F_CTXDISP, "f-ctxdisp", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MS1_F_IMM16L, "f-imm16l", 0, 32, 23, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MS1_F_LOOPO, "f-loopo", 0, 32, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MS1_F_CB1SEL, "f-cb1sel", 0, 32, 25, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MS1_F_CB2SEL, "f-cb2sel", 0, 32, 22, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MS1_F_CB1INCR, "f-cb1incr", 0, 32, 19, 6, { 0|A(SIGNED), { { { (1<<MACH_BASE), 0 } } } } },
+ { MS1_F_CB2INCR, "f-cb2incr", 0, 32, 13, 6, { 0|A(SIGNED), { { { (1<<MACH_BASE), 0 } } } } },
+ { MS1_F_RC3, "f-rc3", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ MS1_F_MSYSFRSR2, "f-msysfrsr2", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ MS1_F_BRC2, "f-brc2", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ MS1_F_BALL2, "f-ball2", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* imm16o: immediate value */
{ "imm16o", MS1_OPERAND_IMM16O, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_IMM16S] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* rc: rc */
{ "rc", MS1_OPERAND_RC, HW_H_UINT, 15, 1,
{ 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_RC] } },
{ "fbincr", MS1_OPERAND_FBINCR, HW_H_UINT, 23, 4,
{ 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_FBINCR] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
+/* loopsize: immediate value */
+ { "loopsize", MS1_OPERAND_LOOPSIZE, HW_H_UINT, 7, 8,
+ { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_LOOPO] } },
+ { 0|A(PCREL_ADDR), { { { (1<<MACH_MS2), 0 } } } } },
+/* imm16l: immediate value */
+ { "imm16l", MS1_OPERAND_IMM16L, HW_H_UINT, 23, 16,
+ { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_IMM16L] } },
+ { 0, { { { (1<<MACH_MS2), 0 } } } } },
+/* rc3: rc3 */
+ { "rc3", MS1_OPERAND_RC3, HW_H_UINT, 7, 1,
+ { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_RC3] } },
+ { 0, { { { (1<<MACH_MS2), 0 } } } } },
+/* cb1sel: cb1sel */
+ { "cb1sel", MS1_OPERAND_CB1SEL, HW_H_UINT, 25, 3,
+ { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CB1SEL] } },
+ { 0, { { { (1<<MACH_MS2), 0 } } } } },
+/* cb2sel: cb2sel */
+ { "cb2sel", MS1_OPERAND_CB2SEL, HW_H_UINT, 22, 3,
+ { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CB2SEL] } },
+ { 0, { { { (1<<MACH_MS2), 0 } } } } },
+/* cb1incr: cb1incr */
+ { "cb1incr", MS1_OPERAND_CB1INCR, HW_H_SINT, 19, 6,
+ { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CB1INCR] } },
+ { 0|A(SIGNED), { { { (1<<MACH_MS2), 0 } } } } },
+/* cb2incr: cb2incr */
+ { "cb2incr", MS1_OPERAND_CB2INCR, HW_H_SINT, 13, 6,
+ { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CB2INCR] } },
+ { 0|A(SIGNED), { { { (1<<MACH_MS2), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
{ 0, { (const PTR) 0 } },
/* mul $frdrrr,$frsr1,$frsr2 */
{
MS1_INSN_MUL, "mul", "mul", 32,
- { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_MS1_003), 0 } } } }
+ { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
},
/* muli $frdr,$frsr1,#$imm16 */
{
MS1_INSN_MULI, "muli", "muli", 32,
- { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_MS1_003), 0 } } } }
+ { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
},
/* and $frdrrr,$frsr1,$frsr2 */
{
/* jal $frdrrr,$frsr1 */
{
MS1_INSN_JAL, "jal", "jal", 32,
- { 0|A(USES_FRSR1)|A(USES_FRDR)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
+ { 0|A(JAL_HAZARD)|A(USES_FRSR1)|A(USES_FRDR)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
},
/* dbnz $frsr1,$imm16o */
{
MS1_INSN_DBNZ, "dbnz", "dbnz", 32,
- { 0|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_MS1_003), 0 } } } }
+ { 0|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
},
/* ei */
{
/* reti $frsr1 */
{
MS1_INSN_RETI, "reti", "reti", 32,
- { 0|A(USES_FRSR1)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
+ { 0|A(JAL_HAZARD)|A(USES_FRSR1)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
},
/* ldw $frdr,$frsr1,#$imm16 */
{
/* iflush */
{
MS1_INSN_IFLUSH, "iflush", "iflush", 32,
- { 0, { { { (1<<MACH_MS1_003), 0 } } } }
+ { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
},
/* ldctxt $frsr1,$frsr2,#$rc,#$rcnum,#$contnum */
{
MS1_INSN_LDCTXT, "ldctxt", "ldctxt", 32,
- { 0, { { { (1<<MACH_BASE), 0 } } } }
+ { 0, { { { (1<<MACH_MS1), 0 } } } }
},
/* ldfb $frsr1,$frsr2,#$imm16z */
{
MS1_INSN_LDFB, "ldfb", "ldfb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } } } }
+ { 0, { { { (1<<MACH_MS1), 0 } } } }
},
/* stfb $frsr1,$frsr2,#$imm16z */
{
MS1_INSN_STFB, "stfb", "stfb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } } } }
+ { 0, { { { (1<<MACH_MS1), 0 } } } }
},
/* fbcb $frsr1,#$rbbc,#$ball,#$brc,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
{
MS1_INSN_FBCB, "fbcb", "fbcb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } } } }
+ { 0, { { { (1<<MACH_MS1)|(1<<MACH_MS1_003), 0 } } } }
},
/* mfbcb $frsr1,#$rbbc,$frsr2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
{
/* wfbinc #$rda,#$wr,#$fbincr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
{
MS1_INSN_WFBINC, "wfbinc", "wfbinc", 32,
- { 0, { { { (1<<MACH_MS1_003), 0 } } } }
+ { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
},
/* mwfbinc $frsr2,#$rda,#$wr,#$fbincr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
{
MS1_INSN_MWFBINC, "mwfbinc", "mwfbinc", 32,
- { 0, { { { (1<<MACH_MS1_003), 0 } } } }
+ { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
},
/* wfbincr $frsr1,#$rda,#$wr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
{
MS1_INSN_WFBINCR, "wfbincr", "wfbincr", 32,
- { 0, { { { (1<<MACH_MS1_003), 0 } } } }
+ { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
},
/* mwfbincr $frsr1,$frsr2,#$rda,#$wr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
{
MS1_INSN_MWFBINCR, "mwfbincr", "mwfbincr", 32,
- { 0, { { { (1<<MACH_MS1_003), 0 } } } }
+ { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
},
/* fbcbincs #$perm,#$a23,#$cr,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
{
MS1_INSN_FBCBINCS, "fbcbincs", "fbcbincs", 32,
- { 0, { { { (1<<MACH_MS1_003), 0 } } } }
+ { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
},
/* mfbcbincs $frsr1,#$perm,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
{
MS1_INSN_MFBCBINCS, "mfbcbincs", "mfbcbincs", 32,
- { 0, { { { (1<<MACH_MS1_003), 0 } } } }
+ { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
},
/* fbcbincrs $frsr1,#$perm,#$ball,#$colnum,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
{
MS1_INSN_FBCBINCRS, "fbcbincrs", "fbcbincrs", 32,
- { 0, { { { (1<<MACH_MS1_003), 0 } } } }
+ { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
},
/* mfbcbincrs $frsr1,$frsr2,#$perm,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
{
MS1_INSN_MFBCBINCRS, "mfbcbincrs", "mfbcbincrs", 32,
- { 0, { { { (1<<MACH_MS1_003), 0 } } } }
+ { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
+ },
+/* loop $frsr1,$loopsize */
+ {
+ MS1_INSN_LOOP, "loop", "loop", 32,
+ { 0|A(USES_FRSR1)|A(DELAY_SLOT), { { { (1<<MACH_MS2), 0 } } } }
+ },
+/* loopi #$imm16l,$loopsize */
+ {
+ MS1_INSN_LOOPI, "loopi", "loopi", 32,
+ { 0|A(DELAY_SLOT), { { { (1<<MACH_MS2), 0 } } } }
+ },
+/* dfbc #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp */
+ {
+ MS1_INSN_DFBC, "dfbc", "dfbc", 32,
+ { 0, { { { (1<<MACH_MS2), 0 } } } }
+ },
+/* dwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc2,#$ctxdisp */
+ {
+ MS1_INSN_DWFB, "dwfb", "dwfb", 32,
+ { 0, { { { (1<<MACH_MS2), 0 } } } }
+ },
+/* fbwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp */
+ {
+ MS1_INSN_FBWFB, "fbwfb", "fbwfb", 32,
+ { 0, { { { (1<<MACH_MS2), 0 } } } }
+ },
+/* dfbr #$cb1sel,#$cb2sel,$frsr2,#$length,#$rownum1,#$rownum2,#$rc2,#$ctxdisp */
+ {
+ MS1_INSN_DFBR, "dfbr", "dfbr", 32,
+ { 0|A(USES_FRSR2), { { { (1<<MACH_MS2), 0 } } } }
},
};
/* Selected cpu families. */
#define HAVE_CPU_MS1BF
#define HAVE_CPU_MS1_003BF
+#define HAVE_CPU_MS2BF
#define CGEN_INSN_LSB0_P 1
, OPC_NAND = 11, OPC_NOR = 12, OPC_XNOR = 13, OPC_LDUI = 14
, OPC_LSL = 16, OPC_LSR = 17, OPC_ASR = 18, OPC_BRLT = 24
, OPC_BRLE = 25, OPC_BREQ = 26, OPC_JMP = 27, OPC_JAL = 28
- , OPC_BRNEQ = 29, OPC_DBNZ = 30, OPC_LDW = 32, OPC_STW = 33
- , OPC_EI = 48, OPC_DI = 49, OPC_SI = 50, OPC_RETI = 51
- , OPC_BREAK = 52, OPC_IFLUSH = 53
+ , OPC_BRNEQ = 29, OPC_DBNZ = 30, OPC_LOOP = 31, OPC_LDW = 32
+ , OPC_STW = 33, OPC_EI = 48, OPC_DI = 49, OPC_SI = 50
+ , OPC_RETI = 51, OPC_BREAK = 52, OPC_IFLUSH = 53
} INSN_OPC;
/* Enum declaration for msopc enums. */
/* Enum declaration for machine type selection. */
typedef enum mach_attr {
- MACH_BASE, MACH_MS1, MACH_MS1_003, MACH_MAX
+ MACH_BASE, MACH_MS1, MACH_MS1_003, MACH_MS2
+ , MACH_MAX
} MACH_ATTR;
/* Enum declaration for instruction set selection. */
, MS1_F_IMM, MS1_F_UU24, MS1_F_SR1, MS1_F_SR2
, MS1_F_DR, MS1_F_DRRR, MS1_F_IMM16U, MS1_F_IMM16S
, MS1_F_IMM16A, MS1_F_UU4A, MS1_F_UU4B, MS1_F_UU12
- , MS1_F_UU16, MS1_F_MSOPC, MS1_F_UU_26_25, MS1_F_MASK
- , MS1_F_BANKADDR, MS1_F_RDA, MS1_F_UU_2_25, MS1_F_RBBC
- , MS1_F_PERM, MS1_F_MODE, MS1_F_UU_1_24, MS1_F_WR
- , MS1_F_FBINCR, MS1_F_UU_2_23, MS1_F_XMODE, MS1_F_A23
- , MS1_F_MASK1, MS1_F_CR, MS1_F_TYPE, MS1_F_INCAMT
- , MS1_F_CBS, MS1_F_UU_1_19, MS1_F_BALL, MS1_F_COLNUM
- , MS1_F_BRC, MS1_F_INCR, MS1_F_FBDISP, MS1_F_UU_4_15
- , MS1_F_LENGTH, MS1_F_UU_1_15, MS1_F_RC, MS1_F_RCNUM
- , MS1_F_ROWNUM, MS1_F_CBX, MS1_F_ID, MS1_F_SIZE
- , MS1_F_ROWNUM1, MS1_F_UU_3_11, MS1_F_RC1, MS1_F_CCB
- , MS1_F_CBRB, MS1_F_CDB, MS1_F_ROWNUM2, MS1_F_CELL
- , MS1_F_UU_3_9, MS1_F_CONTNUM, MS1_F_UU_1_6, MS1_F_DUP
- , MS1_F_RC2, MS1_F_CTXDISP, MS1_F_MSYSFRSR2, MS1_F_BRC2
- , MS1_F_BALL2, MS1_F_MAX
+ , MS1_F_UU8, MS1_F_UU16, MS1_F_UU1, MS1_F_MSOPC
+ , MS1_F_UU_26_25, MS1_F_MASK, MS1_F_BANKADDR, MS1_F_RDA
+ , MS1_F_UU_2_25, MS1_F_RBBC, MS1_F_PERM, MS1_F_MODE
+ , MS1_F_UU_1_24, MS1_F_WR, MS1_F_FBINCR, MS1_F_UU_2_23
+ , MS1_F_XMODE, MS1_F_A23, MS1_F_MASK1, MS1_F_CR
+ , MS1_F_TYPE, MS1_F_INCAMT, MS1_F_CBS, MS1_F_UU_1_19
+ , MS1_F_BALL, MS1_F_COLNUM, MS1_F_BRC, MS1_F_INCR
+ , MS1_F_FBDISP, MS1_F_UU_4_15, MS1_F_LENGTH, MS1_F_UU_1_15
+ , MS1_F_RC, MS1_F_RCNUM, MS1_F_ROWNUM, MS1_F_CBX
+ , MS1_F_ID, MS1_F_SIZE, MS1_F_ROWNUM1, MS1_F_UU_3_11
+ , MS1_F_RC1, MS1_F_CCB, MS1_F_CBRB, MS1_F_CDB
+ , MS1_F_ROWNUM2, MS1_F_CELL, MS1_F_UU_3_9, MS1_F_CONTNUM
+ , MS1_F_UU_1_6, MS1_F_DUP, MS1_F_RC2, MS1_F_CTXDISP
+ , MS1_F_IMM16L, MS1_F_LOOPO, MS1_F_CB1SEL, MS1_F_CB2SEL
+ , MS1_F_CB1INCR, MS1_F_CB2INCR, MS1_F_RC3, MS1_F_MSYSFRSR2
+ , MS1_F_BRC2, MS1_F_BALL2, MS1_F_MAX
} IFIELD_TYPE;
#define MAX_IFLD ((int) MS1_F_MAX)
, MS1_OPERAND_A23, MS1_OPERAND_CR, MS1_OPERAND_CBS, MS1_OPERAND_INCR
, MS1_OPERAND_LENGTH, MS1_OPERAND_CBX, MS1_OPERAND_CCB, MS1_OPERAND_CDB
, MS1_OPERAND_MODE, MS1_OPERAND_ID, MS1_OPERAND_SIZE, MS1_OPERAND_FBINCR
- , MS1_OPERAND_MAX
+ , MS1_OPERAND_LOOPSIZE, MS1_OPERAND_IMM16L, MS1_OPERAND_RC3, MS1_OPERAND_CB1SEL
+ , MS1_OPERAND_CB2SEL, MS1_OPERAND_CB1INCR, MS1_OPERAND_CB2INCR, MS1_OPERAND_MAX
} CGEN_OPERAND_TYPE;
/* Number of operands types. */
-#define MAX_OPERANDS 48
+#define MAX_OPERANDS 55
/* Maximum number of operands referenced by any insn. */
#define MAX_OPERAND_INSTANCES 8
CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_LOAD_DELAY, CGEN_INSN_MEMORY_ACCESS
- , CGEN_INSN_AL_INSN, CGEN_INSN_IO_INSN, CGEN_INSN_BR_INSN, CGEN_INSN_USES_FRDR
- , CGEN_INSN_USES_FRDRRR, CGEN_INSN_USES_FRSR1, CGEN_INSN_USES_FRSR2, CGEN_INSN_SKIPA
- , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
+ , CGEN_INSN_AL_INSN, CGEN_INSN_IO_INSN, CGEN_INSN_BR_INSN, CGEN_INSN_JAL_HAZARD
+ , CGEN_INSN_USES_FRDR, CGEN_INSN_USES_FRDRRR, CGEN_INSN_USES_FRSR1, CGEN_INSN_USES_FRSR2
+ , CGEN_INSN_SKIPA, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH
+ , CGEN_INSN_END_NBOOLS
} CGEN_INSN_ATTR;
/* Number of non-boolean elements in cgen_insn_attr. */
#define CGEN_ATTR_CGEN_INSN_AL_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_AL_INSN)) != 0)
#define CGEN_ATTR_CGEN_INSN_IO_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_IO_INSN)) != 0)
#define CGEN_ATTR_CGEN_INSN_BR_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_BR_INSN)) != 0)
+#define CGEN_ATTR_CGEN_INSN_JAL_HAZARD_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_JAL_HAZARD)) != 0)
#define CGEN_ATTR_CGEN_INSN_USES_FRDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRDR)) != 0)
#define CGEN_ATTR_CGEN_INSN_USES_FRDRRR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRDRRR)) != 0)
#define CGEN_ATTR_CGEN_INSN_USES_FRSR1_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRSR1)) != 0)
/* -- dis.c */
static void print_dollarhex (CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int);
+static void print_pcrel (CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int);
static void
print_dollarhex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
print_normal (cd, dis_info, value, attrs, pc, length);
}
+static void
+print_pcrel (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ void * dis_info,
+ long value,
+ unsigned int attrs ATTRIBUTE_UNUSED,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED)
+{
+ print_address (cd, dis_info, value + pc, attrs, pc, length);
+}
/* -- */
case MS1_OPERAND_BRC2 :
print_dollarhex (cd, info, fields->f_brc2, 0, pc, length);
break;
+ case MS1_OPERAND_CB1INCR :
+ print_dollarhex (cd, info, fields->f_cb1incr, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ break;
+ case MS1_OPERAND_CB1SEL :
+ print_dollarhex (cd, info, fields->f_cb1sel, 0, pc, length);
+ break;
+ case MS1_OPERAND_CB2INCR :
+ print_dollarhex (cd, info, fields->f_cb2incr, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ break;
+ case MS1_OPERAND_CB2SEL :
+ print_dollarhex (cd, info, fields->f_cb2sel, 0, pc, length);
+ break;
case MS1_OPERAND_CBRB :
print_dollarhex (cd, info, fields->f_cbrb, 0, pc, length);
break;
case MS1_OPERAND_IMM16 :
print_dollarhex (cd, info, fields->f_imm16s, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
+ case MS1_OPERAND_IMM16L :
+ print_dollarhex (cd, info, fields->f_imm16l, 0, pc, length);
+ break;
case MS1_OPERAND_IMM16O :
- print_dollarhex (cd, info, fields->f_imm16s, 0, pc, length);
+ print_pcrel (cd, info, fields->f_imm16s, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
break;
case MS1_OPERAND_IMM16Z :
print_dollarhex (cd, info, fields->f_imm16u, 0, pc, length);
case MS1_OPERAND_LENGTH :
print_dollarhex (cd, info, fields->f_length, 0, pc, length);
break;
+ case MS1_OPERAND_LOOPSIZE :
+ print_pcrel (cd, info, fields->f_loopo, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ break;
case MS1_OPERAND_MASK :
print_dollarhex (cd, info, fields->f_mask, 0, pc, length);
break;
case MS1_OPERAND_RC2 :
print_dollarhex (cd, info, fields->f_rc2, 0, pc, length);
break;
+ case MS1_OPERAND_RC3 :
+ print_dollarhex (cd, info, fields->f_rc3, 0, pc, length);
+ break;
case MS1_OPERAND_RCNUM :
print_dollarhex (cd, info, fields->f_rcnum, 0, pc, length);
break;
case MS1_OPERAND_BRC2 :
errmsg = insert_normal (cd, fields->f_brc2, 0, 0, 14, 3, 32, total_length, buffer);
break;
+ case MS1_OPERAND_CB1INCR :
+ errmsg = insert_normal (cd, fields->f_cb1incr, 0|(1<<CGEN_IFLD_SIGNED), 0, 19, 6, 32, total_length, buffer);
+ break;
+ case MS1_OPERAND_CB1SEL :
+ errmsg = insert_normal (cd, fields->f_cb1sel, 0, 0, 25, 3, 32, total_length, buffer);
+ break;
+ case MS1_OPERAND_CB2INCR :
+ errmsg = insert_normal (cd, fields->f_cb2incr, 0|(1<<CGEN_IFLD_SIGNED), 0, 13, 6, 32, total_length, buffer);
+ break;
+ case MS1_OPERAND_CB2SEL :
+ errmsg = insert_normal (cd, fields->f_cb2sel, 0, 0, 22, 3, 32, total_length, buffer);
+ break;
case MS1_OPERAND_CBRB :
errmsg = insert_normal (cd, fields->f_cbrb, 0, 0, 10, 1, 32, total_length, buffer);
break;
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, buffer);
}
break;
+ case MS1_OPERAND_IMM16L :
+ errmsg = insert_normal (cd, fields->f_imm16l, 0, 0, 23, 16, 32, total_length, buffer);
+ break;
case MS1_OPERAND_IMM16O :
{
long value = fields->f_imm16s;
case MS1_OPERAND_LENGTH :
errmsg = insert_normal (cd, fields->f_length, 0, 0, 15, 3, 32, total_length, buffer);
break;
+ case MS1_OPERAND_LOOPSIZE :
+ {
+ long value = fields->f_loopo;
+ value = ((unsigned int) (value) >> (2));
+ errmsg = insert_normal (cd, value, 0, 0, 7, 8, 32, total_length, buffer);
+ }
+ break;
case MS1_OPERAND_MASK :
errmsg = insert_normal (cd, fields->f_mask, 0, 0, 25, 16, 32, total_length, buffer);
break;
case MS1_OPERAND_RC2 :
errmsg = insert_normal (cd, fields->f_rc2, 0, 0, 6, 1, 32, total_length, buffer);
break;
+ case MS1_OPERAND_RC3 :
+ errmsg = insert_normal (cd, fields->f_rc3, 0, 0, 7, 1, 32, total_length, buffer);
+ break;
case MS1_OPERAND_RCNUM :
errmsg = insert_normal (cd, fields->f_rcnum, 0, 0, 14, 3, 32, total_length, buffer);
break;
case MS1_OPERAND_BRC2 :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 3, 32, total_length, pc, & fields->f_brc2);
break;
+ case MS1_OPERAND_CB1INCR :
+ length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 19, 6, 32, total_length, pc, & fields->f_cb1incr);
+ break;
+ case MS1_OPERAND_CB1SEL :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 3, 32, total_length, pc, & fields->f_cb1sel);
+ break;
+ case MS1_OPERAND_CB2INCR :
+ length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 13, 6, 32, total_length, pc, & fields->f_cb2incr);
+ break;
+ case MS1_OPERAND_CB2SEL :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 22, 3, 32, total_length, pc, & fields->f_cb2sel);
+ break;
case MS1_OPERAND_CBRB :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 1, 32, total_length, pc, & fields->f_cbrb);
break;
fields->f_imm16s = value;
}
break;
+ case MS1_OPERAND_IMM16L :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 16, 32, total_length, pc, & fields->f_imm16l);
+ break;
case MS1_OPERAND_IMM16O :
{
long value;
case MS1_OPERAND_LENGTH :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_length);
break;
+ case MS1_OPERAND_LOOPSIZE :
+ {
+ long value;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 8, 32, total_length, pc, & value);
+ value = ((((value) << (2))) + (8));
+ fields->f_loopo = value;
+ }
+ break;
case MS1_OPERAND_MASK :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 16, 32, total_length, pc, & fields->f_mask);
break;
case MS1_OPERAND_RC2 :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 6, 1, 32, total_length, pc, & fields->f_rc2);
break;
+ case MS1_OPERAND_RC3 :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 1, 32, total_length, pc, & fields->f_rc3);
+ break;
case MS1_OPERAND_RCNUM :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 3, 32, total_length, pc, & fields->f_rcnum);
break;
case MS1_OPERAND_BRC2 :
value = fields->f_brc2;
break;
+ case MS1_OPERAND_CB1INCR :
+ value = fields->f_cb1incr;
+ break;
+ case MS1_OPERAND_CB1SEL :
+ value = fields->f_cb1sel;
+ break;
+ case MS1_OPERAND_CB2INCR :
+ value = fields->f_cb2incr;
+ break;
+ case MS1_OPERAND_CB2SEL :
+ value = fields->f_cb2sel;
+ break;
case MS1_OPERAND_CBRB :
value = fields->f_cbrb;
break;
case MS1_OPERAND_IMM16 :
value = fields->f_imm16s;
break;
+ case MS1_OPERAND_IMM16L :
+ value = fields->f_imm16l;
+ break;
case MS1_OPERAND_IMM16O :
value = fields->f_imm16s;
break;
case MS1_OPERAND_LENGTH :
value = fields->f_length;
break;
+ case MS1_OPERAND_LOOPSIZE :
+ value = fields->f_loopo;
+ break;
case MS1_OPERAND_MASK :
value = fields->f_mask;
break;
case MS1_OPERAND_RC2 :
value = fields->f_rc2;
break;
+ case MS1_OPERAND_RC3 :
+ value = fields->f_rc3;
+ break;
case MS1_OPERAND_RCNUM :
value = fields->f_rcnum;
break;
case MS1_OPERAND_BRC2 :
value = fields->f_brc2;
break;
+ case MS1_OPERAND_CB1INCR :
+ value = fields->f_cb1incr;
+ break;
+ case MS1_OPERAND_CB1SEL :
+ value = fields->f_cb1sel;
+ break;
+ case MS1_OPERAND_CB2INCR :
+ value = fields->f_cb2incr;
+ break;
+ case MS1_OPERAND_CB2SEL :
+ value = fields->f_cb2sel;
+ break;
case MS1_OPERAND_CBRB :
value = fields->f_cbrb;
break;
case MS1_OPERAND_IMM16 :
value = fields->f_imm16s;
break;
+ case MS1_OPERAND_IMM16L :
+ value = fields->f_imm16l;
+ break;
case MS1_OPERAND_IMM16O :
value = fields->f_imm16s;
break;
case MS1_OPERAND_LENGTH :
value = fields->f_length;
break;
+ case MS1_OPERAND_LOOPSIZE :
+ value = fields->f_loopo;
+ break;
case MS1_OPERAND_MASK :
value = fields->f_mask;
break;
case MS1_OPERAND_RC2 :
value = fields->f_rc2;
break;
+ case MS1_OPERAND_RC3 :
+ value = fields->f_rc3;
+ break;
case MS1_OPERAND_RCNUM :
value = fields->f_rcnum;
break;
case MS1_OPERAND_BRC2 :
fields->f_brc2 = value;
break;
+ case MS1_OPERAND_CB1INCR :
+ fields->f_cb1incr = value;
+ break;
+ case MS1_OPERAND_CB1SEL :
+ fields->f_cb1sel = value;
+ break;
+ case MS1_OPERAND_CB2INCR :
+ fields->f_cb2incr = value;
+ break;
+ case MS1_OPERAND_CB2SEL :
+ fields->f_cb2sel = value;
+ break;
case MS1_OPERAND_CBRB :
fields->f_cbrb = value;
break;
case MS1_OPERAND_IMM16 :
fields->f_imm16s = value;
break;
+ case MS1_OPERAND_IMM16L :
+ fields->f_imm16l = value;
+ break;
case MS1_OPERAND_IMM16O :
fields->f_imm16s = value;
break;
case MS1_OPERAND_LENGTH :
fields->f_length = value;
break;
+ case MS1_OPERAND_LOOPSIZE :
+ fields->f_loopo = value;
+ break;
case MS1_OPERAND_MASK :
fields->f_mask = value;
break;
case MS1_OPERAND_RC2 :
fields->f_rc2 = value;
break;
+ case MS1_OPERAND_RC3 :
+ fields->f_rc3 = value;
+ break;
case MS1_OPERAND_RCNUM :
fields->f_rcnum = value;
break;
case MS1_OPERAND_BRC2 :
fields->f_brc2 = value;
break;
+ case MS1_OPERAND_CB1INCR :
+ fields->f_cb1incr = value;
+ break;
+ case MS1_OPERAND_CB1SEL :
+ fields->f_cb1sel = value;
+ break;
+ case MS1_OPERAND_CB2INCR :
+ fields->f_cb2incr = value;
+ break;
+ case MS1_OPERAND_CB2SEL :
+ fields->f_cb2sel = value;
+ break;
case MS1_OPERAND_CBRB :
fields->f_cbrb = value;
break;
case MS1_OPERAND_IMM16 :
fields->f_imm16s = value;
break;
+ case MS1_OPERAND_IMM16L :
+ fields->f_imm16l = value;
+ break;
case MS1_OPERAND_IMM16O :
fields->f_imm16s = value;
break;
case MS1_OPERAND_LENGTH :
fields->f_length = value;
break;
+ case MS1_OPERAND_LOOPSIZE :
+ fields->f_loopo = value;
+ break;
case MS1_OPERAND_MASK :
fields->f_mask = value;
break;
case MS1_OPERAND_RC2 :
fields->f_rc2 = value;
break;
+ case MS1_OPERAND_RC3 :
+ fields->f_rc3 = value;
+ break;
case MS1_OPERAND_RCNUM :
fields->f_rcnum = value;
break;
32, 32, 0xfc008000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_PERM) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_UU_1_15) }, { F (F_CBX) }, { F (F_CCB) }, { F (F_CDB) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
};
+static const CGEN_IFMT ifmt_loop ATTRIBUTE_UNUSED = {
+ 32, 32, 0xff0fff00, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_UU4A) }, { F (F_UU8) }, { F (F_LOOPO) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_loopi ATTRIBUTE_UNUSED = {
+ 32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_IMM16L) }, { F (F_LOOPO) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_dfbc ATTRIBUTE_UNUSED = {
+ 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_CB1SEL) }, { F (F_CB2SEL) }, { F (F_CB1INCR) }, { F (F_CB2INCR) }, { F (F_RC3) }, { F (F_RC2) }, { F (F_CTXDISP) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_dwfb ATTRIBUTE_UNUSED = {
+ 32, 32, 0xfc000080, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_CB1SEL) }, { F (F_CB2SEL) }, { F (F_CB1INCR) }, { F (F_CB2INCR) }, { F (F_UU1) }, { F (F_RC2) }, { F (F_CTXDISP) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_dfbr ATTRIBUTE_UNUSED = {
+ 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_CB1SEL) }, { F (F_CB2SEL) }, { F (F_SR2) }, { F (F_LENGTH) }, { F (F_ROWNUM1) }, { F (F_ROWNUM2) }, { F (F_RC2) }, { F (F_CTXDISP) }, { 0 } }
+};
+
#undef F
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
{ { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (PERM), ',', '#', OP (CBX), ',', '#', OP (CCB), ',', '#', OP (CDB), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
& ifmt_mfbcbincrs, { 0xfc000000 }
},
+/* loop $frsr1,$loopsize */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FRSR1), ',', OP (LOOPSIZE), 0 } },
+ & ifmt_loop, { 0x3e000000 }
+ },
+/* loopi #$imm16l,$loopsize */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '#', OP (IMM16L), ',', OP (LOOPSIZE), 0 } },
+ & ifmt_loopi, { 0x3f000000 }
+ },
+/* dfbc #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '#', OP (CB1SEL), ',', '#', OP (CB2SEL), ',', '#', OP (CB1INCR), ',', '#', OP (CB2INCR), ',', '#', OP (RC3), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } },
+ & ifmt_dfbc, { 0x80000000 }
+ },
+/* dwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc2,#$ctxdisp */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '#', OP (CB1SEL), ',', '#', OP (CB2SEL), ',', '#', OP (CB1INCR), ',', '#', OP (CB2INCR), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } },
+ & ifmt_dwfb, { 0x84000000 }
+ },
+/* fbwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '#', OP (CB1SEL), ',', '#', OP (CB2SEL), ',', '#', OP (CB1INCR), ',', '#', OP (CB2INCR), ',', '#', OP (RC3), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } },
+ & ifmt_dfbc, { 0x88000000 }
+ },
+/* dfbr #$cb1sel,#$cb2sel,$frsr2,#$length,#$rownum1,#$rownum2,#$rc2,#$ctxdisp */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '#', OP (CB1SEL), ',', '#', OP (CB2SEL), ',', OP (FRSR2), ',', '#', OP (LENGTH), ',', '#', OP (ROWNUM1), ',', '#', OP (ROWNUM2), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } },
+ & ifmt_dfbr, { 0x8c000000 }
+ },
};
#undef A
, MS1_INSN_WFBI, MS1_INSN_WFB, MS1_INSN_RCRISC, MS1_INSN_FBCBINC
, MS1_INSN_RCXMODE, MS1_INSN_INTERLEAVER, MS1_INSN_WFBINC, MS1_INSN_MWFBINC
, MS1_INSN_WFBINCR, MS1_INSN_MWFBINCR, MS1_INSN_FBCBINCS, MS1_INSN_MFBCBINCS
- , MS1_INSN_FBCBINCRS, MS1_INSN_MFBCBINCRS
+ , MS1_INSN_FBCBINCRS, MS1_INSN_MFBCBINCRS, MS1_INSN_LOOP, MS1_INSN_LOOPI
+ , MS1_INSN_DFBC, MS1_INSN_DWFB, MS1_INSN_FBWFB, MS1_INSN_DFBR
} CGEN_INSN_TYPE;
/* Index of `invalid' insn place holder. */
#define CGEN_INSN_INVALID MS1_INSN_INVALID
/* Total number of insns in table. */
-#define MAX_INSNS ((int) MS1_INSN_MFBCBINCRS + 1)
+#define MAX_INSNS ((int) MS1_INSN_DFBR + 1)
/* This struct records data prior to insertion or after extraction. */
struct cgen_fields
long f_uu4a;
long f_uu4b;
long f_uu12;
+ long f_uu8;
long f_uu16;
+ long f_uu1;
long f_msopc;
long f_uu_26_25;
long f_mask;
long f_dup;
long f_rc2;
long f_ctxdisp;
+ long f_imm16l;
+ long f_loopo;
+ long f_cb1sel;
+ long f_cb2sel;
+ long f_cb1incr;
+ long f_cb2incr;
+ long f_rc3;
long f_msysfrsr2;
long f_brc2;
long f_ball2;
OSDN Git Service
