* cgen-fpu.h (cgen_fp_ops): Update signatures of floating point

	conversion functions.
	* cgen-fpu.cxx (cgen_fp_ops): Ditto.
	* cgen-types (fpconv_kind): New enum.
	* fp.h (enum round_mode_t): Define values in terms of cgen's
	builtin values.

	sh/
	* sh.cxx (sh64_fldi0): Update call to floating point convertion func.
	(sh64_fldi1, sh64_fcnvds, sh64_fcnvsd, sh64_floatld, sh64_floatls,
	sh64_floatqd, sh64_floatqs, sh64_ftrcdl, sh64_ftrcsl, sh64_ftrcdq,
	sh64_ftrcsq, sh64_ftrvs): Ditto.
	* sh2a-fpu-cpu.h, * sh2e-cpu.h, * sh3e-cpu.h, * sh4-cpu.h,
	* sh4a-cpu.h, * sh5-cpu.h: Regenerate.

diff --git a/sid/component/cgen-cpu/ChangeLog b/sid/component/cgen-cpu/ChangeLog
index 0a81313..becbe10 100644 (file)
--- a/sid/component/cgen-cpu/ChangeLog
+++ b/sid/component/cgen-cpu/ChangeLog
@@ -1,3 +1,12 @@
+2010-01-24  Doug Evans  <dje@sebabeach.org>
+
+       * cgen-fpu.h (cgen_fp_ops): Update signatures of floating point
+       conversion functions.
+       * cgen-fpu.cxx (cgen_fp_ops): Ditto.
+       * cgen-types (fpconv_kind): New enum.
+       * fp.h (enum round_mode_t): Define values in terms of cgen's
+       builtin values.
+
 2009-11-23  Doug Evans  <dje@sebabeach.org>
 
        * cgen-engine.h (EXTRACT_MSB0_SINT): Renamed from EXTRACT_MSB0_INT.

diff --git a/sid/component/cgen-cpu/cgen-fpu.cxx b/sid/component/cgen-cpu/cgen-fpu.cxx
index fed3cd8..f0a9cd1 100644 (file)
--- a/sid/component/cgen-cpu/cgen-fpu.cxx
+++ b/sid/component/cgen-cpu/cgen-fpu.cxx
@@ -1,7 +1,7 @@
 // cgen-fpu.cxx - CPU components.  -*- C++ -*-
 // CGEN fpu support for SID
 //
-// Copyright (C) 2005 Red Hat.
+// Copyright (C) 2005, 2010 Red Hat.
 // This file is part of SID and is licensed under the GPL.
 // See the file COPYING.SID for conditions for redistribution.
 
@@ -230,7 +230,8 @@ int cgen_fp_ops::unordereddf (const cgen_fpu *fpu, DF x, DF y)
 }
 
 /* SF/DF conversion ops */
-DF cgen_fp_ops::fextsfdf (const cgen_fpu *fpu, SF x)
+
+DF cgen_fp_ops::fextsfdf (const cgen_fpu *fpu, int how, SF x)
 {
   fp r (x);
   DF tmp;
@@ -238,7 +239,7 @@ DF cgen_fp_ops::fextsfdf (const cgen_fpu *fpu, SF x)
   return tmp;
 }
 
-SF cgen_fp_ops::ftruncdfsf (const cgen_fpu *fpu, DF x)
+SF cgen_fp_ops::ftruncdfsf (const cgen_fpu *fpu, int how, DF x)
 {
   fp r (x);
   SF tmp;
@@ -246,7 +247,7 @@ SF cgen_fp_ops::ftruncdfsf (const cgen_fpu *fpu, DF x)
   return tmp;
 }
 
-SF cgen_fp_ops::floatsisf (const cgen_fpu* fpu, SI x)
+SF cgen_fp_ops::floatsisf (const cgen_fpu* fpu, int how, SI x)
 {
   fp r = fp::from_int (x);
   check_result (fpu, r);
@@ -255,7 +256,7 @@ SF cgen_fp_ops::floatsisf (const cgen_fpu* fpu, SI x)
   return tmp;
 }
 
-SF cgen_fp_ops::floatdisf (const cgen_fpu *fpu, DI x)
+SF cgen_fp_ops::floatdisf (const cgen_fpu *fpu, int how, DI x)
 {
   fp r = fp::from_int (x);
   check_result (fpu, r);
@@ -265,11 +266,11 @@ SF cgen_fp_ops::floatdisf (const cgen_fpu *fpu, DI x)
 }
 
 #if 0 // not implemented yet
-SF cgen_fp_ops::ufloatsisf (const cgen_fpu*, USI);
-SF cgen_fp_ops::ufloatdisf (const cgen_fpu*, UDI);
+SF cgen_fp_ops::ufloatsisf (const cgen_fpu*, int how, USI);
+SF cgen_fp_ops::ufloatdisf (const cgen_fpu*, int how, UDI);
 #endif // not implemented yet
 
-SI cgen_fp_ops::fixsfsi (const cgen_fpu *fpu, SF x)
+SI cgen_fp_ops::fixsfsi (const cgen_fpu *fpu, int how, SF x)
 {
   fp r (x);
   SI tmp;
@@ -277,7 +278,7 @@ SI cgen_fp_ops::fixsfsi (const cgen_fpu *fpu, SF x)
   return tmp;
 }
 
-DI cgen_fp_ops::fixsfdi (const cgen_fpu *fpu, SF x)
+DI cgen_fp_ops::fixsfdi (const cgen_fpu *fpu, int how, SF x)
 {
   fp r (x);
   DI tmp;
@@ -286,10 +287,11 @@ DI cgen_fp_ops::fixsfdi (const cgen_fpu *fpu, SF x)
 }
 
 #if 0 // not implemented yet
-USI cgen_fp_ops::ufixsfsi (const cgen_fpu*, SF)
-UDI cgen_fp_ops::ufixsfdi (const cgen_fpu*, SF);
+USI cgen_fp_ops::ufixsfsi (const cgen_fpu*, int how, SF);
+UDI cgen_fp_ops::ufixsfdi (const cgen_fpu*, int how, SF);
 #endif
-DF cgen_fp_ops::floatsidf (const cgen_fpu *fpu, SI x)
+
+DF cgen_fp_ops::floatsidf (const cgen_fpu *fpu, int how, SI x)
 {
   fp r = fp::from_int (x);
   check_result (fpu, r);
@@ -298,7 +300,7 @@ DF cgen_fp_ops::floatsidf (const cgen_fpu *fpu, SI x)
   return tmp;
 }
 
-DF cgen_fp_ops::floatdidf (const cgen_fpu *fpu, DI x)
+DF cgen_fp_ops::floatdidf (const cgen_fpu *fpu, int how, DI x)
 {
   fp r = fp::from_int (x);
   check_result (fpu, r);
@@ -308,10 +310,11 @@ DF cgen_fp_ops::floatdidf (const cgen_fpu *fpu, DI x)
 }
 
 #if 0
-DF cgen_fp_ops::ufloatsidf (const cgen_fpu*, USI);
-DF cgen_fp_ops::ufloatdidf (const cgen_fpu*, UDI);
+DF cgen_fp_ops::ufloatsidf (const cgen_fpu*, int how, USI);
+DF cgen_fp_ops::ufloatdidf (const cgen_fpu*, int how, UDI);
 #endif
-SI cgen_fp_ops::fixdfsi (const cgen_fpu *fpu, DF x)
+
+SI cgen_fp_ops::fixdfsi (const cgen_fpu *fpu, int how, DF x)
 {
   fp r (x);
   SI tmp;
@@ -319,7 +322,7 @@ SI cgen_fp_ops::fixdfsi (const cgen_fpu *fpu, DF x)
   return tmp;
 }
 
-DI cgen_fp_ops::fixdfdi (const cgen_fpu *fpu, DF x)
+DI cgen_fp_ops::fixdfdi (const cgen_fpu *fpu, int how, DF x)
 {
   fp r (x);
   DI tmp;
@@ -328,8 +331,8 @@ DI cgen_fp_ops::fixdfdi (const cgen_fpu *fpu, DF x)
 }
 
 #if 0
-USI cgen_fp_ops::ufixdfsi (const cgen_fpu*, DF);
-UDI cgen_fp_ops::ufixdfdi (const cgen_fpu*, DF);
+USI cgen_fp_ops::ufixdfsi (const cgen_fpu*, int how, DF);
+UDI cgen_fp_ops::ufixdfdi (const cgen_fpu*, int how, DF);
 
 /* XF mode support (kept separate 'cus not always present) */
 XF cgen_fp_ops::addxf (const cgen_fpu*, XF, XF);
@@ -352,20 +355,20 @@ int cgen_fp_ops::lexf (const cgen_fpu*, XF, XF);
 int cgen_fp_ops::gtxf (const cgen_fpu*, XF, XF);
 int cgen_fp_ops::gexf (const cgen_fpu*, XF, XF);
 
-XF cgen_fp_ops::extsfxf (const cgen_fpu*, SF);
-XF cgen_fp_ops::extdfxf (const cgen_fpu*, DF);
-SF cgen_fp_ops::truncxfsf (const cgen_fpu*, XF);
-DF cgen_fp_ops::truncxfdf (const cgen_fpu*, XF);
+XF cgen_fp_ops::extsfxf (const cgen_fpu*, int how, SF);
+XF cgen_fp_ops::extdfxf (const cgen_fpu*, int how, DF);
+SF cgen_fp_ops::truncxfsf (const cgen_fpu*, int how, XF);
+DF cgen_fp_ops::truncxfdf (const cgen_fpu*, int how, XF);
 
-XF cgen_fp_ops::floatsixf (const cgen_fpu*, SI);
-XF cgen_fp_ops::floatdixf (const cgen_fpu*, DI);
-XF cgen_fp_ops::ufloatsixf (const cgen_fpu*, USI);
-XF cgen_fp_ops::ufloatdixf (const cgen_fpu*, UDI);
+XF cgen_fp_ops::floatsixf (const cgen_fpu*, int how, SI);
+XF cgen_fp_ops::floatdixf (const cgen_fpu*, int how, DI);
+XF cgen_fp_ops::ufloatsixf (const cgen_fpu*, int how, USI);
+XF cgen_fp_ops::ufloatdixf (const cgen_fpu*, int how, UDI);
 
-SI cgen_fp_ops::fixxfsi (const cgen_fpu*, XF);
-DI cgen_fp_ops::fixxfdi (const cgen_fpu*, XF);
-USI cgen_fp_ops::ufixxfsi (const cgen_fpu*, XF);
-UDI cgen_fp_ops::ufixxfdi (const cgen_fpu*, XF);
+SI cgen_fp_ops::fixxfsi (const cgen_fpu*, int how, XF);
+DI cgen_fp_ops::fixxfdi (const cgen_fpu*, int how, XF);
+USI cgen_fp_ops::ufixxfsi (const cgen_fpu*, int how, XF);
+UDI cgen_fp_ops::ufixxfdi (const cgen_fpu*, int how, XF);
 
 /* TF mode support (kept separate 'cus not always present) */
 TF cgen_fp_ops::addtf (const cgen_fpu*, TF, TF);
@@ -388,20 +391,20 @@ int cgen_fp_ops::letf (const cgen_fpu*, TF, TF);
 int cgen_fp_ops::gttf (const cgen_fpu*, TF, TF);
 int cgen_fp_ops::getf (const cgen_fpu*, TF, TF);
 
-TF cgen_fp_ops::extsftf (const cgen_fpu*, SF);
-TF cgen_fp_ops::extdftf (const cgen_fpu*, DF);
-SF cgen_fp_ops::trunctfsf (const cgen_fpu*, TF);
-DF cgen_fp_ops::trunctfdf (const cgen_fpu*, TF);
+TF cgen_fp_ops::extsftf (const cgen_fpu*, int how, SF);
+TF cgen_fp_ops::extdftf (const cgen_fpu*, int how, DF);
+SF cgen_fp_ops::trunctfsf (const cgen_fpu*, int how, TF);
+DF cgen_fp_ops::trunctfdf (const cgen_fpu*, int how, TF);
 
-TF cgen_fp_ops::floatsitf (const cgen_fpu*, SI);
-TF cgen_fp_ops::floatditf (const cgen_fpu*, DI);
-TF cgen_fp_ops::ufloatsitf (const cgen_fpu*, USI);
-TF cgen_fp_ops::ufloatditf (const cgen_fpu*, UDI);
+TF cgen_fp_ops::floatsitf (const cgen_fpu*, int how, SI);
+TF cgen_fp_ops::floatditf (const cgen_fpu*, int how, DI);
+TF cgen_fp_ops::ufloatsitf (const cgen_fpu*, int how, USI);
+TF cgen_fp_ops::ufloatditf (const cgen_fpu*, int how, UDI);
 
-SI cgen_fp_ops::fixtfsi (const cgen_fpu*, TF);
-DI cgen_fp_ops::fixtfdi (const cgen_fpu*, TF);
-USI cgen_fp_ops::ufixtfsi (const cgen_fpu*, TF);
-UDI cgen_fp_ops::ufixtfdi (const cgen_fpu*, TF);
+SI cgen_fp_ops::fixtfsi (const cgen_fpu*, int how, TF);
+DI cgen_fp_ops::fixtfdi (const cgen_fpu*, int how, TF);
+USI cgen_fp_ops::ufixtfsi (const cgen_fpu*, int how, TF);
+UDI cgen_fp_ops::ufixtfdi (const cgen_fpu*, int how, TF);
 #endif // not implemented yet
 
 }; // namespace cgen 

diff --git a/sid/component/cgen-cpu/cgen-fpu.h b/sid/component/cgen-cpu/cgen-fpu.h
index b80cedc..2c3e83b 100644 (file)
--- a/sid/component/cgen-cpu/cgen-fpu.h
+++ b/sid/component/cgen-cpu/cgen-fpu.h
@@ -1,7 +1,7 @@
 // cgen-fpu.h - CPU components.  -*- C++ -*-
 // CGEN fpu support for SID
 //
-// Copyright (C) 2005 Red Hat.
+// Copyright (C) 2005, 2010 Red Hat.
 // This file is part of SID and is licensed under the GPL.
 // See the file COPYING.SID for conditions for redistribution.
 
@@ -72,33 +72,33 @@ public:
   virtual int unordereddf (const cgen_fpu*, DF, DF);
 
   /* SF/DF conversion ops */
-  virtual DF fextsfdf (const cgen_fpu*, SF);
-  virtual SF ftruncdfsf (const cgen_fpu*, DF);
+  virtual DF fextsfdf (const cgen_fpu*, int, SF);
+  virtual SF ftruncdfsf (const cgen_fpu*, int, DF);
 
-  virtual SF floatsisf (const cgen_fpu*, SI);
-  virtual SF floatdisf (const cgen_fpu*, DI);
+  virtual SF floatsisf (const cgen_fpu*, int, SI);
+  virtual SF floatdisf (const cgen_fpu*, int, DI);
 #if 0 // not implemented yet
-  virtual SF ufloatsisf (const cgen_fpu*, USI);
-  virtual SF ufloatdisf (const cgen_fpu*, UDI);
+  virtual SF ufloatsisf (const cgen_fpu*, int, USI);
+  virtual SF ufloatdisf (const cgen_fpu*, int, UDI);
 #endif // not implemented yet
 
-  virtual SI fixsfsi (const cgen_fpu*, SF);
-  virtual DI fixsfdi (const cgen_fpu*, SF);
+  virtual SI fixsfsi (const cgen_fpu*, int, SF);
+  virtual DI fixsfdi (const cgen_fpu*, int, SF);
 #if 0 // not implemented yet
-  virtual USI ufixsfsi (const cgen_fpu*, SF);
-  virtual UDI ufixsfdi (const cgen_fpu*, SF);
+  virtual USI ufixsfsi (const cgen_fpu*, int, SF);
+  virtual UDI ufixsfdi (const cgen_fpu*, int, SF);
 #endif
-  virtual DF floatsidf (const cgen_fpu*, SI);
-  virtual DF floatdidf (const cgen_fpu*, DI);
+  virtual DF floatsidf (const cgen_fpu*, int, SI);
+  virtual DF floatdidf (const cgen_fpu*, int, DI);
 #if 0
-  virtual DF ufloatsidf (const cgen_fpu*, USI);
-  virtual DF ufloatdidf (const cgen_fpu*, UDI);
+  virtual DF ufloatsidf (const cgen_fpu*, int, USI);
+  virtual DF ufloatdidf (const cgen_fpu*, int, UDI);
 #endif
-  virtual SI fixdfsi (const cgen_fpu*, DF);
-  virtual DI fixdfdi (const cgen_fpu*, DF);
+  virtual SI fixdfsi (const cgen_fpu*, int, DF);
+  virtual DI fixdfdi (const cgen_fpu*, int, DF);
 #if 0
-  virtual USI ufixdfsi (const cgen_fpu*, DF);
-  virtual UDI ufixdfdi (const cgen_fpu*, DF);
+  virtual USI ufixdfsi (const cgen_fpu*, int, DF);
+  virtual UDI ufixdfdi (const cgen_fpu*, int, DF);
 
   /* XF mode support (kept separate 'cus not always present) */
   virtual XF addxf (const cgen_fpu*, XF, XF);
@@ -121,20 +121,20 @@ public:
   virtual int gtxf (const cgen_fpu*, XF, XF);
   virtual int gexf (const cgen_fpu*, XF, XF);
 
-  virtual XF extsfxf (const cgen_fpu*, SF);
-  virtual XF extdfxf (const cgen_fpu*, DF);
-  virtual SF truncxfsf (const cgen_fpu*, XF);
-  virtual DF truncxfdf (const cgen_fpu*, XF);
+  virtual XF extsfxf (const cgen_fpu*, int, SF);
+  virtual XF extdfxf (const cgen_fpu*, int, DF);
+  virtual SF truncxfsf (const cgen_fpu*, int, XF);
+  virtual DF truncxfdf (const cgen_fpu*, int, XF);
 
-  virtual XF floatsixf (const cgen_fpu*, SI);
-  virtual XF floatdixf (const cgen_fpu*, DI);
-  virtual XF ufloatsixf (const cgen_fpu*, USI);
-  virtual XF ufloatdixf (const cgen_fpu*, UDI);
+  virtual XF floatsixf (const cgen_fpu*, int, SI);
+  virtual XF floatdixf (const cgen_fpu*, int, DI);
+  virtual XF ufloatsixf (const cgen_fpu*, int, USI);
+  virtual XF ufloatdixf (const cgen_fpu*, int, UDI);
 
-  virtual SI fixxfsi (const cgen_fpu*, XF);
-  virtual DI fixxfdi (const cgen_fpu*, XF);
-  virtual USI ufixxfsi (const cgen_fpu*, XF);
-  virtual UDI ufixxfdi (const cgen_fpu*, XF);
+  virtual SI fixxfsi (const cgen_fpu*, int, XF);
+  virtual DI fixxfdi (const cgen_fpu*, int, XF);
+  virtual USI ufixxfsi (const cgen_fpu*, int, XF);
+  virtual UDI ufixxfdi (const cgen_fpu*, int, XF);
 
   /* TF mode support (kept separate 'cus not always present) */
   virtual TF addtf (const cgen_fpu*, TF, TF);
@@ -157,20 +157,20 @@ public:
   virtual int gttf (const cgen_fpu*, TF, TF);
   virtual int getf (const cgen_fpu*, TF, TF);
 
-  virtual TF extsftf (const cgen_fpu*, SF);
-  virtual TF extdftf (const cgen_fpu*, DF);
-  virtual SF trunctfsf (const cgen_fpu*, TF);
-  virtual DF trunctfdf (const cgen_fpu*, TF);
+  virtual TF extsftf (const cgen_fpu*, int, SF);
+  virtual TF extdftf (const cgen_fpu*, int, DF);
+  virtual SF trunctfsf (const cgen_fpu*, int, TF);
+  virtual DF trunctfdf (const cgen_fpu*, int, TF);
 
-  virtual TF floatsitf (const cgen_fpu*, SI);
-  virtual TF floatditf (const cgen_fpu*, DI);
-  virtual TF ufloatsitf (const cgen_fpu*, USI);
-  virtual TF ufloatditf (const cgen_fpu*, UDI);
+  virtual TF floatsitf (const cgen_fpu*, int, SI);
+  virtual TF floatditf (const cgen_fpu*, int, DI);
+  virtual TF ufloatsitf (const cgen_fpu*, int, USI);
+  virtual TF ufloatditf (const cgen_fpu*, int, UDI);
 
-  virtual SI fixtfsi (const cgen_fpu*, TF);
-  virtual DI fixtfdi (const cgen_fpu*, TF);
-  virtual USI ufixtfsi (const cgen_fpu*, TF);
-  virtual UDI ufixtfdi (const cgen_fpu*, TF);
+  virtual SI fixtfsi (const cgen_fpu*, int, TF);
+  virtual DI fixtfdi (const cgen_fpu*, int, TF);
+  virtual USI ufixtfsi (const cgen_fpu*, int, TF);
+  virtual UDI ufixtfdi (const cgen_fpu*, int, TF);
 #endif // not implemented yet
 };
 

diff --git a/sid/component/cgen-cpu/cgen-types.h b/sid/component/cgen-cpu/cgen-types.h
index 90d0940..a823e72 100644 (file)
--- a/sid/component/cgen-cpu/cgen-types.h
+++ b/sid/component/cgen-cpu/cgen-types.h
@@ -1,6 +1,6 @@
 // cgen-types.h - Types for CGEN-based SID simulators.  -*- C++ -*-
 
-// Copyright (C) 1999, 2000 Red Hat.
+// Copyright (C) 1999, 2000, 2010 Red Hat.
 // This file is part of SID and is licensed under the GPL.
 // See the file COPYING.SID for conditions for redistribution.
 
@@ -46,6 +46,18 @@ typedef unsigned long ADDR;
 // Deprecated.
 typedef IADDR PCADDR;  
 
+// Builtin floating point conversion kinds.
+// The values here are defined by cgen.
+
+enum fpconv_kind {
+  FPCONV_DEFAULT = 0,
+  FPCONV_TIES_TO_EVEN = 1,
+  FPCONV_TIES_TO_AWAY = 2,
+  FPCONV_TOWARD_ZERO = 3,
+  FPCONV_TOWARD_POSITIVE = 4,
+  FPCONV_TOWARD_NEGATIVE = 5
+};
+
 } // namespace cgen
 
 #endif // CGEN_TYPES_H

diff --git a/sid/component/cgen-cpu/fp.h b/sid/component/cgen-cpu/fp.h
index 0ef2acb..b9b6df1 100644 (file)
--- a/sid/component/cgen-cpu/fp.h
+++ b/sid/component/cgen-cpu/fp.h
@@ -1,6 +1,6 @@
 // fp.h - Floating point number class using host integer ops.  -*- C++ -*-
 
-// Copyright 1997, 1998, 2002, 2005, 2006 Free Software Foundation, Inc.
+// Copyright 1997, 1998, 2002, 2005, 2006, 2010 Free Software Foundation, Inc.
 // Copyright 2002 Red Hat, Inc.
 // This file is part of SID.
 
@@ -191,11 +191,11 @@ namespace sidutil
       
       enum round_mode_t
        {
-         round_default,
-         round_near,
-         round_zero,
-         round_up,
-         round_down
+         round_default = cgen::FPCONV_DEFAULT,
+         round_near = cgen::FPCONV_TIES_TO_EVEN,
+         round_zero = cgen::FPCONV_TOWARD_ZERO,
+         round_up = cgen::FPCONV_TOWARD_POSITIVE,
+         round_down = cgen::FPCONV_TOWARD_NEGATIVE
        };
       
       enum denorm_t

diff --git a/sid/component/cgen-cpu/sh/ChangeLog b/sid/component/cgen-cpu/sh/ChangeLog
index 912235f..c579fa0 100644 (file)
--- a/sid/component/cgen-cpu/sh/ChangeLog
+++ b/sid/component/cgen-cpu/sh/ChangeLog
@@ -1,3 +1,12 @@
+2010-01-24  Doug Evans  <dje@sebabeach.org>
+
+       * sh.cxx (sh64_fldi0): Update call to floating point convertion func.
+       (sh64_fldi1, sh64_fcnvds, sh64_fcnvsd, sh64_floatld, sh64_floatls,
+       sh64_floatqd, sh64_floatqs, sh64_ftrcdl, sh64_ftrcsl, sh64_ftrcdq,
+       sh64_ftrcsq, sh64_ftrvs): Ditto.
+       * sh2a-fpu-cpu.h, * sh2e-cpu.h, * sh3e-cpu.h, * sh4-cpu.h,
+       * sh4a-cpu.h, * sh5-cpu.h: Regenerate.
+
 2010-01-02  Doug Evans  <dje@sebabeach.org>
 
        * sh-desc.h, * sh2-cpu.h, * sh2-decode.cxx, * sh2-decode.h,

diff --git a/sid/component/cgen-cpu/sh/sh.cxx b/sid/component/cgen-cpu/sh/sh.cxx
index dd01fb3..3981951 100644 (file)
--- a/sid/component/cgen-cpu/sh/sh.cxx
+++ b/sid/component/cgen-cpu/sh/sh.cxx
@@ -1,7 +1,7 @@
 // sh.cxx - Implementations of hand-written functions for the sh
 // simulator. -*- C++ -*-
 
-// Copyright (C) 2006 Red Hat.
+// Copyright (C) 2006, 2010 Red Hat.
 // This file is part of SID and is licensed under the GPL.
 // See the file COPYING.SID for conditions for redistribution.
 
@@ -203,14 +203,14 @@ template<class CGEN_CPU>
 SF
 sh_cpu<CGEN_CPU>::sh64_fldi0 ()
 {
-  return this->fpu.ops->floatsisf (& this->fpu, 0);
+  return this->fpu.ops->floatsisf (& this->fpu, fp::round_default, 0);
 }
 
 template<class CGEN_CPU>
 SF
 sh_cpu<CGEN_CPU>::sh64_fldi1 ()
 {
-  return this->fpu.ops->floatsisf (& this->fpu, 1);
+  return this->fpu.ops->floatsisf (& this->fpu, fp::round_default, 1);
 }
 
 template<class CGEN_CPU>
@@ -301,14 +301,14 @@ template<class CGEN_CPU>
 SF
 sh_cpu<CGEN_CPU>::sh64_fcnvds(DF drgh)
 {
-  return this->fpu.ops->ftruncdfsf (& this->fpu, drgh);
+  return this->fpu.ops->ftruncdfsf (& this->fpu, fp::round_default, drgh);
 }
 
 template<class CGEN_CPU>
 DF
 sh_cpu<CGEN_CPU>::sh64_fcnvsd(SF frgh)
 {
-  return this->fpu.ops->fextsfdf (& this->fpu, frgh);
+  return this->fpu.ops->fextsfdf (& this->fpu, fp::round_default, frgh);
 }
 
 template<class CGEN_CPU>
@@ -329,28 +329,28 @@ template<class CGEN_CPU>
 DF
 sh_cpu<CGEN_CPU>::sh64_floatld(SF frgh)
 {
-  return this->fpu.ops->floatsidf (& this->fpu, frgh);
+  return this->fpu.ops->floatsidf (& this->fpu, fp::round_default, frgh);
 }
 
 template<class CGEN_CPU>
 SF
 sh_cpu<CGEN_CPU>::sh64_floatls(SF frgh)
 {
-  return this->fpu.ops->floatsisf (& this->fpu, frgh);
+  return this->fpu.ops->floatsisf (& this->fpu, fp::round_default, frgh);
 }
 
 template<class CGEN_CPU>
 DF
 sh_cpu<CGEN_CPU>::sh64_floatqd(DF drgh)
 {
-  return this->fpu.ops->floatdidf (& this->fpu, drgh);
+  return this->fpu.ops->floatdidf (& this->fpu, fp::round_default, drgh);
 }
 
 template<class CGEN_CPU>
 SF
 sh_cpu<CGEN_CPU>::sh64_floatqs(DF drgh)
 {
-  return this->fpu.ops->floatdisf (& this->fpu, drgh);
+  return this->fpu.ops->floatdisf (& this->fpu, fp::round_default, drgh);
 }
 
 template<class CGEN_CPU>
@@ -422,28 +422,28 @@ template<class CGEN_CPU>
 SF
 sh_cpu<CGEN_CPU>::sh64_ftrcdl(DF drgh)
 {
-  return this->fpu.ops->fixdfsi (& this->fpu, drgh);
+  return this->fpu.ops->fixdfsi (& this->fpu, fp::round_default, drgh);
 }
 
 template<class CGEN_CPU>
 SF
 sh_cpu<CGEN_CPU>::sh64_ftrcsl(SF frgh)
 {
-  return this->fpu.ops->fixsfsi (& this->fpu, frgh);
+  return this->fpu.ops->fixsfsi (& this->fpu, fp::round_default, frgh);
 }
 
 template<class CGEN_CPU>
 DF
 sh_cpu<CGEN_CPU>::sh64_ftrcdq(DF drgh)
 {
-  return this->fpu.ops->fixdfdi (& this->fpu, drgh);
+  return this->fpu.ops->fixdfdi (& this->fpu, fp::round_default, drgh);
 }
 
 template<class CGEN_CPU>
 DF
 sh_cpu<CGEN_CPU>::sh64_ftrcsq(SF frgh)
 {
-  return this->fpu.ops->fixsfdi (& this->fpu, frgh);
+  return this->fpu.ops->fixsfdi (& this->fpu, fp::round_default, frgh);
 }
 
 template<class CGEN_CPU>
@@ -451,7 +451,7 @@ void
 sh_cpu<CGEN_CPU>::sh64_ftrvs(unsigned g, unsigned h, unsigned f)
 {
   int i, j;
-  SF zero = this->fpu.ops->floatsisf (& this->fpu, 0);
+  SF zero = this->fpu.ops->floatsisf (& this->fpu, fp::round_default, 0);
   for (i = 0; i < 4; i++)
     {
       SF result = zero;

diff --git a/sid/component/cgen-cpu/sh/sh2a-fpu-cpu.h b/sid/component/cgen-cpu/sh/sh2a-fpu-cpu.h
index 7876aa9..3954ec6 100644 (file)
--- a/sid/component/cgen-cpu/sh/sh2a-fpu-cpu.h
+++ b/sid/component/cgen-cpu/sh/sh2a-fpu-cpu.h
@@ -175,17 +175,17 @@ current_cpu->hardware.h_fr[((regno) + (1))] = SUBWORDSISF (SUBWORDDFSI (newval,
 }
  }
 
-  inline DF h_fsd_get (UINT regno) const { return ((current_cpu->h_prbit_get ()) ? (current_cpu->h_drc_get (regno)) : (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), current_cpu->hardware.h_fr[regno]))); }
+  inline DF h_fsd_get (UINT regno) const { return ((current_cpu->h_prbit_get ()) ? (current_cpu->h_drc_get (regno)) : (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, current_cpu->hardware.h_fr[regno]))); }
   inline void h_fsd_set (UINT regno, DF newval) { if (current_cpu->h_prbit_get ()) {
 current_cpu->h_drc_set (regno, newval);
 } else {
-current_cpu->h_frc_set (regno, CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), newval));
+current_cpu->h_frc_set (regno, CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, newval));
 }
  }
 
-  inline DF h_fmov_get (UINT regno) const { return ((NOTBI (current_cpu->h_szbit_get ())) ? (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), current_cpu->h_frc_get (regno))) : (((((((regno) & (1))) == (1))) ? (current_cpu->h_xd_get (((regno) & ((~ (1)))))) : (current_cpu->h_dr_get (regno))))); }
+  inline DF h_fmov_get (UINT regno) const { return ((NOTBI (current_cpu->h_szbit_get ())) ? (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, current_cpu->h_frc_get (regno))) : (((((((regno) & (1))) == (1))) ? (current_cpu->h_xd_get (((regno) & ((~ (1)))))) : (current_cpu->h_dr_get (regno))))); }
   inline void h_fmov_set (UINT regno, DF newval) { if (NOTBI (current_cpu->h_szbit_get ())) {
-current_cpu->h_frc_set (regno, CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), newval));
+current_cpu->h_frc_set (regno, CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, newval));
 } else {
 if (((((regno) & (1))) == (1))) {
 current_cpu->h_xd_set (((regno) & ((~ (1)))), newval);

diff --git a/sid/component/cgen-cpu/sh/sh2e-cpu.h b/sid/component/cgen-cpu/sh/sh2e-cpu.h
index 93117c3..9a6aff3 100644 (file)
--- a/sid/component/cgen-cpu/sh/sh2e-cpu.h
+++ b/sid/component/cgen-cpu/sh/sh2e-cpu.h
@@ -175,17 +175,17 @@ current_cpu->hardware.h_fr[((regno) + (1))] = SUBWORDSISF (SUBWORDDFSI (newval,
 }
  }
 
-  inline DF h_fsd_get (UINT regno) const { return ((current_cpu->h_prbit_get ()) ? (current_cpu->h_drc_get (regno)) : (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), current_cpu->hardware.h_fr[regno]))); }
+  inline DF h_fsd_get (UINT regno) const { return ((current_cpu->h_prbit_get ()) ? (current_cpu->h_drc_get (regno)) : (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, current_cpu->hardware.h_fr[regno]))); }
   inline void h_fsd_set (UINT regno, DF newval) { if (current_cpu->h_prbit_get ()) {
 current_cpu->h_drc_set (regno, newval);
 } else {
-current_cpu->h_frc_set (regno, CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), newval));
+current_cpu->h_frc_set (regno, CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, newval));
 }
  }
 
-  inline DF h_fmov_get (UINT regno) const { return ((NOTBI (current_cpu->h_szbit_get ())) ? (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), current_cpu->h_frc_get (regno))) : (((((((regno) & (1))) == (1))) ? (current_cpu->h_xd_get (((regno) & ((~ (1)))))) : (current_cpu->h_dr_get (regno))))); }
+  inline DF h_fmov_get (UINT regno) const { return ((NOTBI (current_cpu->h_szbit_get ())) ? (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, current_cpu->h_frc_get (regno))) : (((((((regno) & (1))) == (1))) ? (current_cpu->h_xd_get (((regno) & ((~ (1)))))) : (current_cpu->h_dr_get (regno))))); }
   inline void h_fmov_set (UINT regno, DF newval) { if (NOTBI (current_cpu->h_szbit_get ())) {
-current_cpu->h_frc_set (regno, CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), newval));
+current_cpu->h_frc_set (regno, CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, newval));
 } else {
 if (((((regno) & (1))) == (1))) {
 current_cpu->h_xd_set (((regno) & ((~ (1)))), newval);

diff --git a/sid/component/cgen-cpu/sh/sh3e-cpu.h b/sid/component/cgen-cpu/sh/sh3e-cpu.h
index b03aeab..6c910d1 100644 (file)
--- a/sid/component/cgen-cpu/sh/sh3e-cpu.h
+++ b/sid/component/cgen-cpu/sh/sh3e-cpu.h
@@ -175,17 +175,17 @@ current_cpu->hardware.h_fr[((regno) + (1))] = SUBWORDSISF (SUBWORDDFSI (newval,
 }
  }
 
-  inline DF h_fsd_get (UINT regno) const { return ((current_cpu->h_prbit_get ()) ? (current_cpu->h_drc_get (regno)) : (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), current_cpu->hardware.h_fr[regno]))); }
+  inline DF h_fsd_get (UINT regno) const { return ((current_cpu->h_prbit_get ()) ? (current_cpu->h_drc_get (regno)) : (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, current_cpu->hardware.h_fr[regno]))); }
   inline void h_fsd_set (UINT regno, DF newval) { if (current_cpu->h_prbit_get ()) {
 current_cpu->h_drc_set (regno, newval);
 } else {
-current_cpu->h_frc_set (regno, CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), newval));
+current_cpu->h_frc_set (regno, CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, newval));
 }
  }
 
-  inline DF h_fmov_get (UINT regno) const { return ((NOTBI (current_cpu->h_szbit_get ())) ? (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), current_cpu->h_frc_get (regno))) : (((((((regno) & (1))) == (1))) ? (current_cpu->h_xd_get (((regno) & ((~ (1)))))) : (current_cpu->h_dr_get (regno))))); }
+  inline DF h_fmov_get (UINT regno) const { return ((NOTBI (current_cpu->h_szbit_get ())) ? (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, current_cpu->h_frc_get (regno))) : (((((((regno) & (1))) == (1))) ? (current_cpu->h_xd_get (((regno) & ((~ (1)))))) : (current_cpu->h_dr_get (regno))))); }
   inline void h_fmov_set (UINT regno, DF newval) { if (NOTBI (current_cpu->h_szbit_get ())) {
-current_cpu->h_frc_set (regno, CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), newval));
+current_cpu->h_frc_set (regno, CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, newval));
 } else {
 if (((((regno) & (1))) == (1))) {
 current_cpu->h_xd_set (((regno) & ((~ (1)))), newval);

diff --git a/sid/component/cgen-cpu/sh/sh4-cpu.h b/sid/component/cgen-cpu/sh/sh4-cpu.h
index acd4a65..882e571 100644 (file)
--- a/sid/component/cgen-cpu/sh/sh4-cpu.h
+++ b/sid/component/cgen-cpu/sh/sh4-cpu.h
@@ -175,17 +175,17 @@ current_cpu->hardware.h_fr[((regno) + (1))] = SUBWORDSISF (SUBWORDDFSI (newval,
 }
  }
 
-  inline DF h_fsd_get (UINT regno) const { return ((current_cpu->h_prbit_get ()) ? (current_cpu->h_drc_get (regno)) : (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), current_cpu->hardware.h_fr[regno]))); }
+  inline DF h_fsd_get (UINT regno) const { return ((current_cpu->h_prbit_get ()) ? (current_cpu->h_drc_get (regno)) : (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, current_cpu->hardware.h_fr[regno]))); }
   inline void h_fsd_set (UINT regno, DF newval) { if (current_cpu->h_prbit_get ()) {
 current_cpu->h_drc_set (regno, newval);
 } else {
-current_cpu->h_frc_set (regno, CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), newval));
+current_cpu->h_frc_set (regno, CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, newval));
 }
  }
 
-  inline DF h_fmov_get (UINT regno) const { return ((NOTBI (current_cpu->h_szbit_get ())) ? (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), current_cpu->h_frc_get (regno))) : (((((((regno) & (1))) == (1))) ? (current_cpu->h_xd_get (((regno) & ((~ (1)))))) : (current_cpu->h_dr_get (regno))))); }
+  inline DF h_fmov_get (UINT regno) const { return ((NOTBI (current_cpu->h_szbit_get ())) ? (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, current_cpu->h_frc_get (regno))) : (((((((regno) & (1))) == (1))) ? (current_cpu->h_xd_get (((regno) & ((~ (1)))))) : (current_cpu->h_dr_get (regno))))); }
   inline void h_fmov_set (UINT regno, DF newval) { if (NOTBI (current_cpu->h_szbit_get ())) {
-current_cpu->h_frc_set (regno, CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), newval));
+current_cpu->h_frc_set (regno, CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, newval));
 } else {
 if (((((regno) & (1))) == (1))) {
 current_cpu->h_xd_set (((regno) & ((~ (1)))), newval);

diff --git a/sid/component/cgen-cpu/sh/sh4a-cpu.h b/sid/component/cgen-cpu/sh/sh4a-cpu.h
index 581082e..4fbcb3a 100644 (file)
--- a/sid/component/cgen-cpu/sh/sh4a-cpu.h
+++ b/sid/component/cgen-cpu/sh/sh4a-cpu.h
@@ -175,17 +175,17 @@ current_cpu->hardware.h_fr[((regno) + (1))] = SUBWORDSISF (SUBWORDDFSI (newval,
 }
  }
 
-  inline DF h_fsd_get (UINT regno) const { return ((current_cpu->h_prbit_get ()) ? (current_cpu->h_drc_get (regno)) : (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), current_cpu->hardware.h_fr[regno]))); }
+  inline DF h_fsd_get (UINT regno) const { return ((current_cpu->h_prbit_get ()) ? (current_cpu->h_drc_get (regno)) : (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, current_cpu->hardware.h_fr[regno]))); }
   inline void h_fsd_set (UINT regno, DF newval) { if (current_cpu->h_prbit_get ()) {
 current_cpu->h_drc_set (regno, newval);
 } else {
-current_cpu->h_frc_set (regno, CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), newval));
+current_cpu->h_frc_set (regno, CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, newval));
 }
  }
 
-  inline DF h_fmov_get (UINT regno) const { return ((NOTBI (current_cpu->h_szbit_get ())) ? (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), current_cpu->h_frc_get (regno))) : (((((((regno) & (1))) == (1))) ? (current_cpu->h_xd_get (((regno) & ((~ (1)))))) : (current_cpu->h_dr_get (regno))))); }
+  inline DF h_fmov_get (UINT regno) const { return ((NOTBI (current_cpu->h_szbit_get ())) ? (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, current_cpu->h_frc_get (regno))) : (((((((regno) & (1))) == (1))) ? (current_cpu->h_xd_get (((regno) & ((~ (1)))))) : (current_cpu->h_dr_get (regno))))); }
   inline void h_fmov_set (UINT regno, DF newval) { if (NOTBI (current_cpu->h_szbit_get ())) {
-current_cpu->h_frc_set (regno, CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), newval));
+current_cpu->h_frc_set (regno, CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, newval));
 } else {
 if (((((regno) & (1))) == (1))) {
 current_cpu->h_xd_set (((regno) & ((~ (1)))), newval);

diff --git a/sid/component/cgen-cpu/sh/sh5-cpu.h b/sid/component/cgen-cpu/sh/sh5-cpu.h
index 57653ac..65e89e7 100644 (file)
--- a/sid/component/cgen-cpu/sh/sh5-cpu.h
+++ b/sid/component/cgen-cpu/sh/sh5-cpu.h
@@ -195,17 +195,17 @@ current_cpu->hardware.h_fr[((regno) + (1))] = SUBWORDSISF (SUBWORDDFSI (newval,
 }
  }
 
-  inline DF h_fsd_get (UINT regno) const { return ((current_cpu->h_prbit_get ()) ? (current_cpu->h_drc_get (regno)) : (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), current_cpu->hardware.h_fr[regno]))); }
+  inline DF h_fsd_get (UINT regno) const { return ((current_cpu->h_prbit_get ()) ? (current_cpu->h_drc_get (regno)) : (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, current_cpu->hardware.h_fr[regno]))); }
   inline void h_fsd_set (UINT regno, DF newval) { if (current_cpu->h_prbit_get ()) {
 current_cpu->h_drc_set (regno, newval);
 } else {
-current_cpu->h_frc_set (regno, CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), newval));
+current_cpu->h_frc_set (regno, CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, newval));
 }
  }
 
-  inline DF h_fmov_get (UINT regno) const { return ((NOTBI (current_cpu->h_szbit_get ())) ? (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), current_cpu->h_frc_get (regno))) : (((((((regno) & (1))) == (1))) ? (current_cpu->h_xd_get (((regno) & ((~ (1)))))) : (current_cpu->h_dr_get (regno))))); }
+  inline DF h_fmov_get (UINT regno) const { return ((NOTBI (current_cpu->h_szbit_get ())) ? (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, current_cpu->h_frc_get (regno))) : (((((((regno) & (1))) == (1))) ? (current_cpu->h_xd_get (((regno) & ((~ (1)))))) : (current_cpu->h_dr_get (regno))))); }
   inline void h_fmov_set (UINT regno, DF newval) { if (NOTBI (current_cpu->h_szbit_get ())) {
-current_cpu->h_frc_set (regno, CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), newval));
+current_cpu->h_frc_set (regno, CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, newval));
 } else {
 if (((((regno) & (1))) == (1))) {
 current_cpu->h_xd_set (((regno) & ((~ (1)))), newval);