2009-09-16 Mike Frysinger <michael.frysinger@analog.com>
+ * bfin/include/cdefBF512.h, bfin/include/cdefBF514.h,
+ bfin/include/cdefBF516.h, bfin/include/cdefBF518.h,
+ bfin/include/cdefBF51x_base.h, bfin/include/cdefBF523.h,
+ bfin/include/cdefBF524.h, bfin/include/cdefBF526.h,
+ bfin/include/cdefBF542M.h, bfin/include/cdefBF544M.h,
+ bfin/include/cdefBF547M.h, bfin/include/cdefBF548M.h,
+ bfin/include/cdefBF549M.h, bfin/include/defBF512.h,
+ bfin/include/defBF514.h, bfin/include/defBF516.h,
+ bfin/include/defBF518.h, bfin/include/defBF51x_base.h,
+ bfin/include/defBF523.h, bfin/include/defBF524.h,
+ bfin/include/defBF526.h, bfin/include/defBF542M.h,
+ bfin/include/defBF544M.h, bfin/include/defBF547M.h,
+ bfin/include/defBF548M.h, bfin/include/defBF549M.h:
+ New file.
+ * bfin/include/ccblkfn.h, bfin/include/cdefBF525.h,
+ bfin/include/cdefBF527.h, bfin/include/cdefBF52x_base.h,
+ bfin/include/cdefBF532.h, bfin/include/cdefBF534.h,
+ bfin/include/cdefBF535.h, bfin/include/cdefBF538.h,
+ bfin/include/cdefBF539.h, bfin/include/cdefBF542.h,
+ bfin/include/cdefBF544.h, bfin/include/cdefBF547.h,
+ bfin/include/cdefBF548.h, bfin/include/cdefBF549.h,
+ bfin/include/cdefBF54x_base.h, bfin/include/cdefBF561.h,
+ bfin/include/cdefblackfin.h, bfin/include/cdef_LPBlackfin.h,
+ bfin/include/cplb.h, bfin/include/defBF527.h,
+ bfin/include/defBF52x_base.h, bfin/include/defBF532.h,
+ bfin/include/defBF534.h, bfin/include/defBF535.h,
+ bfin/include/defBF537.h, bfin/include/defBF538.h,
+ bfin/include/defBF539.h, bfin/include/defBF542.h,
+ bfin/include/defBF544.h, bfin/include/defBF547.h,
+ bfin/include/defBF548.h, bfin/include/defBF549.h,
+ bfin/include/defBF54x_base.h, bfin/include/defBF561.h,
+ bfin/include/defblackfin.h, bfin/include/def_LPBlackfin.h,
+ bfin/include/sys/_adi_platform.h,
+ bfin/include/sys/anomaly_macros_rtl.h,
+ bfin/include/sys/exception.h, bfin/include/sysreg.h:
+ Update to Visual DSP 5.0 Update 6.
+
+2009-09-16 Mike Frysinger <michael.frysinger@analog.com>
+
* bfin/Makefile.in (BOARD_SCRIPTS): Add bf512.ld, bf514.ld,
and bf516.ld, bf518.ld.
* bfin/bf512.ld: New file.
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
/* For now, a dummy header file, fill in with gcc-specific items later.
Header files from VisualDSP require that this exists. */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** Copyright (C) 2009 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for the ADSP-BF512 peripherals.
+**
+************************************************************************************
+** System MMR Register Map
+************************************************************************************/
+
+#ifndef _CDEF_BF512_H
+#define _CDEF_BF512_H
+
+/* include all Core registers and bit definitions */
+#include <defBF512.h>
+
+/* include core specific register pointer definitions */
+#include <cdef_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF512 */
+
+/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
+#include <cdefBF51x_base.h>
+
+#endif /* _CDEF_BF512_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** Copyright (C) 2009 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for the ADSP-BF514 peripherals.
+**
+************************************************************************************
+** System MMR Register Map
+************************************************************************************/
+
+#ifndef _CDEF_BF514_H
+#define _CDEF_BF514_H
+
+/* include all Core registers and bit definitions */
+#include <defBF514.h>
+
+/* include core specific register pointer definitions */
+#include <cdef_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */
+
+/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
+#include <cdefBF51x_base.h>
+
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
+#endif /* _MISRA_RULES */
+
+/* The following are the #defines needed by ADSP-BF514 that are not in the common header */
+
+/* SDH Registers (0xFFC03800 - 0xFFC03CFF)*/
+#define pSDH_PWR_CTL ((volatile unsigned short *)SDH_PWR_CTL)
+#define pSDH_CLK_CTL ((volatile unsigned short *)SDH_CLK_CTL)
+#define pSDH_ARGUMENT ((volatile unsigned long *)SDH_ARGUMENT)
+#define pSDH_COMMAND ((volatile unsigned short *)SDH_COMMAND)
+#define pSDH_RESP_CMD ((volatile unsigned short *)SDH_RESP_CMD)
+#define pSDH_RESPONSE0 ((volatile unsigned long *)SDH_RESPONSE0)
+#define pSDH_RESPONSE1 ((volatile unsigned long *)SDH_RESPONSE1)
+#define pSDH_RESPONSE2 ((volatile unsigned long *)SDH_RESPONSE2)
+#define pSDH_RESPONSE3 ((volatile unsigned long *)SDH_RESPONSE3)
+#define pSDH_DATA_TIMER ((volatile unsigned long *)SDH_DATA_TIMER)
+#define pSDH_DATA_LGTH ((volatile unsigned short *)SDH_DATA_LGTH)
+#define pSDH_DATA_CTL ((volatile unsigned short *)SDH_DATA_CTL)
+#define pSDH_DATA_CNT ((volatile unsigned short *)SDH_DATA_CNT)
+#define pSDH_STATUS ((volatile unsigned long *)SDH_STATUS)
+#define pSDH_STATUS_CLR ((volatile unsigned short *)SDH_STATUS_CLR)
+#define pSDH_MASK0 ((volatile unsigned long *)SDH_MASK0)
+#define pSDH_MASK1 ((volatile unsigned long *)SDH_MASK1)
+#define pSDH_FIFO_CNT ((volatile unsigned short *)SDH_FIFO_CNT)
+#define pSDH_FIFO ((volatile unsigned long *)SDH_FIFO)
+#define pSDH_E_STATUS ((volatile unsigned short *)SDH_E_STATUS)
+#define pSDH_E_MASK ((volatile unsigned short *)SDH_E_MASK)
+#define pSDH_CFG ((volatile unsigned short *)SDH_CFG)
+#define pSDH_RD_WAIT_EN ((volatile unsigned short *)SDH_RD_WAIT_EN)
+#define pSDH_PID0 ((volatile unsigned short *)SDH_PID0)
+#define pSDH_PID1 ((volatile unsigned short *)SDH_PID1)
+#define pSDH_PID2 ((volatile unsigned short *)SDH_PID2)
+#define pSDH_PID3 ((volatile unsigned short *)SDH_PID3)
+#define pSDH_PID4 ((volatile unsigned short *)SDH_PID4)
+#define pSDH_PID5 ((volatile unsigned short *)SDH_PID5)
+#define pSDH_PID6 ((volatile unsigned short *)SDH_PID6)
+#define pSDH_PID7 ((volatile unsigned short *)SDH_PID7)
+
+
+/* RSI Registers (0xFFC03800 - 0xFFC03CFF)*/
+#define pRSI_PWR_CONTROL ((volatile unsigned short *)RSI_PWR_CONTROL)
+#define pRSI_CLK_CONTROL ((volatile unsigned short *)RSI_CLK_CONTROL)
+#define pRSI_ARGUMENT ((volatile unsigned long *)RSI_ARGUMENT)
+#define pRSI_COMMAND ((volatile unsigned short *)RSI_COMMAND)
+#define pRSI_RESP_CMD ((volatile unsigned short *)RSI_RESP_CMD)
+#define pRSI_RESPONSE0 ((volatile unsigned long *)RSI_RESPONSE0)
+#define pRSI_RESPONSE1 ((volatile unsigned long *)RSI_RESPONSE1)
+#define pRSI_RESPONSE2 ((volatile unsigned long *)RSI_RESPONSE2)
+#define pRSI_RESPONSE3 ((volatile unsigned long *)RSI_RESPONSE3)
+#define pRSI_DATA_TIMER ((volatile unsigned long *)RSI_DATA_TIMER)
+#define pRSI_DATA_LGTH ((volatile unsigned short *)RSI_DATA_LGTH)
+#define pRSI_DATA_CONTROL ((volatile unsigned short *)RSI_DATA_CONTROL)
+#define pRSI_DATA_CNT ((volatile unsigned short *)RSI_DATA_CNT)
+#define pRSI_STATUS ((volatile unsigned long *)RSI_STATUS)
+#define pRSI_STATUSCL ((volatile unsigned short *)RSI_STATUSCL)
+#define pRSI_MASK0 ((volatile unsigned long *)RSI_MASK0)
+#define pRSI_MASK1 ((volatile unsigned long *)RSI_MASK1)
+#define pRSI_FIFO_CNT ((volatile unsigned short *)RSI_FIFO_CNT)
+#define pRSI_CEATA_CONTROL ((volatile unsigned short *)RSI_CEATA_CONTROL)
+#define pRSI_FIFO ((volatile unsigned long *)RSI_FIFO)
+#define pRSI_ESTAT ((volatile unsigned short *)RSI_ESTAT)
+#define pRSI_EMASK ((volatile unsigned short *)RSI_EMASK)
+#define pRSI_CONFIG ((volatile unsigned short *)RSI_CONFIG)
+#define pRSI_RD_WAIT_EN ((volatile unsigned short *)RSI_RD_WAIT_EN)
+#define pRSI_PID0 ((volatile unsigned short *)RSI_PID0)
+#define pRSI_PID1 ((volatile unsigned short *)RSI_PID1)
+#define pRSI_PID2 ((volatile unsigned short *)RSI_PID2)
+#define pRSI_PID3 ((volatile unsigned short *)RSI_PID3)
+
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif /* _CDEF_BF514_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** Copyright (C) 2009 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for the ADSP-BF516 peripherals.
+**
+************************************************************************************
+** System MMR Register Map
+************************************************************************************/
+
+#ifndef _CDEF_BF516_H
+#define _CDEF_BF516_H
+
+/* include all Core registers and bit definitions */
+#include <defBF516.h>
+
+/* include core specific register pointer definitions */
+#include <cdef_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF516 */
+
+/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
+#include <cdefBF51x_base.h>
+
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
+#endif /* _MISRA_RULES */
+
+/* The following are the #defines needed by ADSP-BF516 that are not in the common header */
+
+/* 10/100 Ethernet Controller */
+#define pEMAC_OPMODE ((volatile unsigned long *)EMAC_OPMODE)
+#define pEMAC_ADDRLO ((volatile unsigned long *)EMAC_ADDRLO)
+#define pEMAC_ADDRHI ((volatile unsigned long *)EMAC_ADDRHI)
+#define pEMAC_HASHLO ((volatile unsigned long *)EMAC_HASHLO)
+#define pEMAC_HASHHI ((volatile unsigned long *)EMAC_HASHHI)
+#define pEMAC_STAADD ((volatile unsigned long *)EMAC_STAADD)
+#define pEMAC_STADAT ((volatile unsigned long *)EMAC_STADAT)
+#define pEMAC_FLC ((volatile unsigned long *)EMAC_FLC)
+#define pEMAC_VLAN1 ((volatile unsigned long *)EMAC_VLAN1)
+#define pEMAC_VLAN2 ((volatile unsigned long *)EMAC_VLAN2)
+#define pEMAC_WKUP_CTL ((volatile unsigned long *)EMAC_WKUP_CTL)
+#define pEMAC_WKUP_FFMSK0 ((volatile unsigned long *)EMAC_WKUP_FFMSK0)
+#define pEMAC_WKUP_FFMSK1 ((volatile unsigned long *)EMAC_WKUP_FFMSK1)
+#define pEMAC_WKUP_FFMSK2 ((volatile unsigned long *)EMAC_WKUP_FFMSK2)
+#define pEMAC_WKUP_FFMSK3 ((volatile unsigned long *)EMAC_WKUP_FFMSK3)
+#define pEMAC_WKUP_FFCMD ((volatile unsigned long *)EMAC_WKUP_FFCMD)
+#define pEMAC_WKUP_FFOFF ((volatile unsigned long *)EMAC_WKUP_FFOFF)
+#define pEMAC_WKUP_FFCRC0 ((volatile unsigned long *)EMAC_WKUP_FFCRC0)
+#define pEMAC_WKUP_FFCRC1 ((volatile unsigned long *)EMAC_WKUP_FFCRC1)
+
+#define pEMAC_SYSCTL ((volatile unsigned long *)EMAC_SYSCTL)
+#define pEMAC_SYSTAT ((volatile unsigned long *)EMAC_SYSTAT)
+#define pEMAC_RX_STAT ((volatile unsigned long *)EMAC_RX_STAT)
+#define pEMAC_RX_STKY ((volatile unsigned long *)EMAC_RX_STKY)
+#define pEMAC_RX_IRQE ((volatile unsigned long *)EMAC_RX_IRQE)
+#define pEMAC_TX_STAT ((volatile unsigned long *)EMAC_TX_STAT)
+#define pEMAC_TX_STKY ((volatile unsigned long *)EMAC_TX_STKY)
+#define pEMAC_TX_IRQE ((volatile unsigned long *)EMAC_TX_IRQE)
+
+#define pEMAC_MMC_CTL ((volatile unsigned long *)EMAC_MMC_CTL)
+#define pEMAC_MMC_RIRQS ((volatile unsigned long *)EMAC_MMC_RIRQS)
+#define pEMAC_MMC_RIRQE ((volatile unsigned long *)EMAC_MMC_RIRQE)
+#define pEMAC_MMC_TIRQS ((volatile unsigned long *)EMAC_MMC_TIRQS)
+#define pEMAC_MMC_TIRQE ((volatile unsigned long *)EMAC_MMC_TIRQE)
+
+#define pEMAC_RXC_OK ((volatile unsigned long *)EMAC_RXC_OK)
+#define pEMAC_RXC_FCS ((volatile unsigned long *)EMAC_RXC_FCS)
+#define pEMAC_RXC_ALIGN ((volatile unsigned long *)EMAC_RXC_ALIGN)
+#define pEMAC_RXC_OCTET ((volatile unsigned long *)EMAC_RXC_OCTET)
+#define pEMAC_RXC_DMAOVF ((volatile unsigned long *)EMAC_RXC_DMAOVF)
+#define pEMAC_RXC_UNICST ((volatile unsigned long *)EMAC_RXC_UNICST)
+#define pEMAC_RXC_MULTI ((volatile unsigned long *)EMAC_RXC_MULTI)
+#define pEMAC_RXC_BROAD ((volatile unsigned long *)EMAC_RXC_BROAD)
+#define pEMAC_RXC_LNERRI ((volatile unsigned long *)EMAC_RXC_LNERRI)
+#define pEMAC_RXC_LNERRO ((volatile unsigned long *)EMAC_RXC_LNERRO)
+#define pEMAC_RXC_LONG ((volatile unsigned long *)EMAC_RXC_LONG)
+#define pEMAC_RXC_MACCTL ((volatile unsigned long *)EMAC_RXC_MACCTL)
+#define pEMAC_RXC_OPCODE ((volatile unsigned long *)EMAC_RXC_OPCODE)
+#define pEMAC_RXC_PAUSE ((volatile unsigned long *)EMAC_RXC_PAUSE)
+#define pEMAC_RXC_ALLFRM ((volatile unsigned long *)EMAC_RXC_ALLFRM)
+#define pEMAC_RXC_ALLOCT ((volatile unsigned long *)EMAC_RXC_ALLOCT)
+#define pEMAC_RXC_TYPED ((volatile unsigned long *)EMAC_RXC_TYPED)
+#define pEMAC_RXC_SHORT ((volatile unsigned long *)EMAC_RXC_SHORT)
+#define pEMAC_RXC_EQ64 ((volatile unsigned long *)EMAC_RXC_EQ64)
+#define pEMAC_RXC_LT128 ((volatile unsigned long *)EMAC_RXC_LT128)
+#define pEMAC_RXC_LT256 ((volatile unsigned long *)EMAC_RXC_LT256)
+#define pEMAC_RXC_LT512 ((volatile unsigned long *)EMAC_RXC_LT512)
+#define pEMAC_RXC_LT1024 ((volatile unsigned long *)EMAC_RXC_LT1024)
+#define pEMAC_RXC_GE1024 ((volatile unsigned long *)EMAC_RXC_GE1024)
+
+#define pEMAC_TXC_OK ((volatile unsigned long *)EMAC_TXC_OK)
+#define pEMAC_TXC_1COL ((volatile unsigned long *)EMAC_TXC_1COL)
+#define pEMAC_TXC_GT1COL ((volatile unsigned long *)EMAC_TXC_GT1COL)
+#define pEMAC_TXC_OCTET ((volatile unsigned long *)EMAC_TXC_OCTET)
+#define pEMAC_TXC_DEFER ((volatile unsigned long *)EMAC_TXC_DEFER)
+#define pEMAC_TXC_LATECL ((volatile unsigned long *)EMAC_TXC_LATECL)
+#define pEMAC_TXC_XS_COL ((volatile unsigned long *)EMAC_TXC_XS_COL)
+#define pEMAC_TXC_DMAUND ((volatile unsigned long *)EMAC_TXC_DMAUND)
+#define pEMAC_TXC_CRSERR ((volatile unsigned long *)EMAC_TXC_CRSERR)
+#define pEMAC_TXC_UNICST ((volatile unsigned long *)EMAC_TXC_UNICST)
+#define pEMAC_TXC_MULTI ((volatile unsigned long *)EMAC_TXC_MULTI)
+#define pEMAC_TXC_BROAD ((volatile unsigned long *)EMAC_TXC_BROAD)
+#define pEMAC_TXC_XS_DFR ((volatile unsigned long *)EMAC_TXC_XS_DFR)
+#define pEMAC_TXC_MACCTL ((volatile unsigned long *)EMAC_TXC_MACCTL)
+#define pEMAC_TXC_ALLFRM ((volatile unsigned long *)EMAC_TXC_ALLFRM)
+#define pEMAC_TXC_ALLOCT ((volatile unsigned long *)EMAC_TXC_ALLOCT)
+#define pEMAC_TXC_EQ64 ((volatile unsigned long *)EMAC_TXC_EQ64)
+#define pEMAC_TXC_LT128 ((volatile unsigned long *)EMAC_TXC_LT128)
+#define pEMAC_TXC_LT256 ((volatile unsigned long *)EMAC_TXC_LT256)
+#define pEMAC_TXC_LT512 ((volatile unsigned long *)EMAC_TXC_LT512)
+#define pEMAC_TXC_LT1024 ((volatile unsigned long *)EMAC_TXC_LT1024)
+#define pEMAC_TXC_GE1024 ((volatile unsigned long *)EMAC_TXC_GE1024)
+#define pEMAC_TXC_ABORT ((volatile unsigned long *)EMAC_TXC_ABORT)
+
+
+/* SDH Registers (0xFFC03800 - 0xFFC03CFF)*/
+#define pSDH_PWR_CTL ((volatile unsigned short *)SDH_PWR_CTL)
+#define pSDH_CLK_CTL ((volatile unsigned short *)SDH_CLK_CTL)
+#define pSDH_ARGUMENT ((volatile unsigned long *)SDH_ARGUMENT)
+#define pSDH_COMMAND ((volatile unsigned short *)SDH_COMMAND)
+#define pSDH_RESP_CMD ((volatile unsigned short *)SDH_RESP_CMD)
+#define pSDH_RESPONSE0 ((volatile unsigned long *)SDH_RESPONSE0)
+#define pSDH_RESPONSE1 ((volatile unsigned long *)SDH_RESPONSE1)
+#define pSDH_RESPONSE2 ((volatile unsigned long *)SDH_RESPONSE2)
+#define pSDH_RESPONSE3 ((volatile unsigned long *)SDH_RESPONSE3)
+#define pSDH_DATA_TIMER ((volatile unsigned long *)SDH_DATA_TIMER)
+#define pSDH_DATA_LGTH ((volatile unsigned short *)SDH_DATA_LGTH)
+#define pSDH_DATA_CTL ((volatile unsigned short *)SDH_DATA_CTL)
+#define pSDH_DATA_CNT ((volatile unsigned short *)SDH_DATA_CNT)
+#define pSDH_STATUS ((volatile unsigned long *)SDH_STATUS)
+#define pSDH_STATUS_CLR ((volatile unsigned short *)SDH_STATUS_CLR)
+#define pSDH_MASK0 ((volatile unsigned long *)SDH_MASK0)
+#define pSDH_MASK1 ((volatile unsigned long *)SDH_MASK1)
+#define pSDH_FIFO_CNT ((volatile unsigned short *)SDH_FIFO_CNT)
+#define pSDH_FIFO ((volatile unsigned long *)SDH_FIFO)
+#define pSDH_E_STATUS ((volatile unsigned short *)SDH_E_STATUS)
+#define pSDH_E_MASK ((volatile unsigned short *)SDH_E_MASK)
+#define pSDH_CFG ((volatile unsigned short *)SDH_CFG)
+#define pSDH_RD_WAIT_EN ((volatile unsigned short *)SDH_RD_WAIT_EN)
+#define pSDH_PID0 ((volatile unsigned short *)SDH_PID0)
+#define pSDH_PID1 ((volatile unsigned short *)SDH_PID1)
+#define pSDH_PID2 ((volatile unsigned short *)SDH_PID2)
+#define pSDH_PID3 ((volatile unsigned short *)SDH_PID3)
+#define pSDH_PID4 ((volatile unsigned short *)SDH_PID4)
+#define pSDH_PID5 ((volatile unsigned short *)SDH_PID5)
+#define pSDH_PID6 ((volatile unsigned short *)SDH_PID6)
+#define pSDH_PID7 ((volatile unsigned short *)SDH_PID7)
+
+
+/* RSI Registers (0xFFC03800 - 0xFFC03CFF)*/
+#define pRSI_PWR_CONTROL ((volatile unsigned short *)RSI_PWR_CONTROL)
+#define pRSI_CLK_CONTROL ((volatile unsigned short *)RSI_CLK_CONTROL)
+#define pRSI_ARGUMENT ((volatile unsigned long *)RSI_ARGUMENT)
+#define pRSI_COMMAND ((volatile unsigned short *)RSI_COMMAND)
+#define pRSI_RESP_CMD ((volatile unsigned short *)RSI_RESP_CMD)
+#define pRSI_RESPONSE0 ((volatile unsigned long *)RSI_RESPONSE0)
+#define pRSI_RESPONSE1 ((volatile unsigned long *)RSI_RESPONSE1)
+#define pRSI_RESPONSE2 ((volatile unsigned long *)RSI_RESPONSE2)
+#define pRSI_RESPONSE3 ((volatile unsigned long *)RSI_RESPONSE3)
+#define pRSI_DATA_TIMER ((volatile unsigned long *)RSI_DATA_TIMER)
+#define pRSI_DATA_LGTH ((volatile unsigned short *)RSI_DATA_LGTH)
+#define pRSI_DATA_CONTROL ((volatile unsigned short *)RSI_DATA_CONTROL)
+#define pRSI_DATA_CNT ((volatile unsigned short *)RSI_DATA_CNT)
+#define pRSI_STATUS ((volatile unsigned long *)RSI_STATUS)
+#define pRSI_STATUSCL ((volatile unsigned short *)RSI_STATUSCL)
+#define pRSI_MASK0 ((volatile unsigned long *)RSI_MASK0)
+#define pRSI_MASK1 ((volatile unsigned long *)RSI_MASK1)
+#define pRSI_FIFO_CNT ((volatile unsigned short *)RSI_FIFO_CNT)
+#define pRSI_CEATA_CONTROL ((volatile unsigned short *)RSI_CEATA_CONTROL)
+#define pRSI_FIFO ((volatile unsigned long *)RSI_FIFO)
+#define pRSI_ESTAT ((volatile unsigned short *)RSI_ESTAT)
+#define pRSI_EMASK ((volatile unsigned short *)RSI_EMASK)
+#define pRSI_CONFIG ((volatile unsigned short *)RSI_CONFIG)
+#define pRSI_RD_WAIT_EN ((volatile unsigned short *)RSI_RD_WAIT_EN)
+#define pRSI_PID0 ((volatile unsigned short *)RSI_PID0)
+#define pRSI_PID1 ((volatile unsigned short *)RSI_PID1)
+#define pRSI_PID2 ((volatile unsigned short *)RSI_PID2)
+#define pRSI_PID3 ((volatile unsigned short *)RSI_PID3)
+
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif /* _CDEF_BF516_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** Copyright (C) 2009 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for the ADSP-BF518 peripherals.
+**
+************************************************************************************
+** System MMR Register Map
+************************************************************************************/
+
+#ifndef _CDEF_BF518_H
+#define _CDEF_BF518_H
+
+/* include all Core registers and bit definitions */
+#include <defBF518.h>
+
+/* include core specific register pointer definitions */
+#include <cdef_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF518 */
+
+/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
+#include <cdefBF51x_base.h>
+
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
+#endif /* _MISRA_RULES */
+
+/* The following are the #defines needed by ADSP-BF518 that are not in the common header */
+
+/* 10/100 Ethernet Controller */
+#define pEMAC_OPMODE ((volatile unsigned long *)EMAC_OPMODE)
+#define pEMAC_ADDRLO ((volatile unsigned long *)EMAC_ADDRLO)
+#define pEMAC_ADDRHI ((volatile unsigned long *)EMAC_ADDRHI)
+#define pEMAC_HASHLO ((volatile unsigned long *)EMAC_HASHLO)
+#define pEMAC_HASHHI ((volatile unsigned long *)EMAC_HASHHI)
+#define pEMAC_STAADD ((volatile unsigned long *)EMAC_STAADD)
+#define pEMAC_STADAT ((volatile unsigned long *)EMAC_STADAT)
+#define pEMAC_FLC ((volatile unsigned long *)EMAC_FLC)
+#define pEMAC_VLAN1 ((volatile unsigned long *)EMAC_VLAN1)
+#define pEMAC_VLAN2 ((volatile unsigned long *)EMAC_VLAN2)
+#define pEMAC_WKUP_CTL ((volatile unsigned long *)EMAC_WKUP_CTL)
+#define pEMAC_WKUP_FFMSK0 ((volatile unsigned long *)EMAC_WKUP_FFMSK0)
+#define pEMAC_WKUP_FFMSK1 ((volatile unsigned long *)EMAC_WKUP_FFMSK1)
+#define pEMAC_WKUP_FFMSK2 ((volatile unsigned long *)EMAC_WKUP_FFMSK2)
+#define pEMAC_WKUP_FFMSK3 ((volatile unsigned long *)EMAC_WKUP_FFMSK3)
+#define pEMAC_WKUP_FFCMD ((volatile unsigned long *)EMAC_WKUP_FFCMD)
+#define pEMAC_WKUP_FFOFF ((volatile unsigned long *)EMAC_WKUP_FFOFF)
+#define pEMAC_WKUP_FFCRC0 ((volatile unsigned long *)EMAC_WKUP_FFCRC0)
+#define pEMAC_WKUP_FFCRC1 ((volatile unsigned long *)EMAC_WKUP_FFCRC1)
+
+#define pEMAC_SYSCTL ((volatile unsigned long *)EMAC_SYSCTL)
+#define pEMAC_SYSTAT ((volatile unsigned long *)EMAC_SYSTAT)
+#define pEMAC_RX_STAT ((volatile unsigned long *)EMAC_RX_STAT)
+#define pEMAC_RX_STKY ((volatile unsigned long *)EMAC_RX_STKY)
+#define pEMAC_RX_IRQE ((volatile unsigned long *)EMAC_RX_IRQE)
+#define pEMAC_TX_STAT ((volatile unsigned long *)EMAC_TX_STAT)
+#define pEMAC_TX_STKY ((volatile unsigned long *)EMAC_TX_STKY)
+#define pEMAC_TX_IRQE ((volatile unsigned long *)EMAC_TX_IRQE)
+
+#define pEMAC_MMC_CTL ((volatile unsigned long *)EMAC_MMC_CTL)
+#define pEMAC_MMC_RIRQS ((volatile unsigned long *)EMAC_MMC_RIRQS)
+#define pEMAC_MMC_RIRQE ((volatile unsigned long *)EMAC_MMC_RIRQE)
+#define pEMAC_MMC_TIRQS ((volatile unsigned long *)EMAC_MMC_TIRQS)
+#define pEMAC_MMC_TIRQE ((volatile unsigned long *)EMAC_MMC_TIRQE)
+
+#define pEMAC_RXC_OK ((volatile unsigned long *)EMAC_RXC_OK)
+#define pEMAC_RXC_FCS ((volatile unsigned long *)EMAC_RXC_FCS)
+#define pEMAC_RXC_ALIGN ((volatile unsigned long *)EMAC_RXC_ALIGN)
+#define pEMAC_RXC_OCTET ((volatile unsigned long *)EMAC_RXC_OCTET)
+#define pEMAC_RXC_DMAOVF ((volatile unsigned long *)EMAC_RXC_DMAOVF)
+#define pEMAC_RXC_UNICST ((volatile unsigned long *)EMAC_RXC_UNICST)
+#define pEMAC_RXC_MULTI ((volatile unsigned long *)EMAC_RXC_MULTI)
+#define pEMAC_RXC_BROAD ((volatile unsigned long *)EMAC_RXC_BROAD)
+#define pEMAC_RXC_LNERRI ((volatile unsigned long *)EMAC_RXC_LNERRI)
+#define pEMAC_RXC_LNERRO ((volatile unsigned long *)EMAC_RXC_LNERRO)
+#define pEMAC_RXC_LONG ((volatile unsigned long *)EMAC_RXC_LONG)
+#define pEMAC_RXC_MACCTL ((volatile unsigned long *)EMAC_RXC_MACCTL)
+#define pEMAC_RXC_OPCODE ((volatile unsigned long *)EMAC_RXC_OPCODE)
+#define pEMAC_RXC_PAUSE ((volatile unsigned long *)EMAC_RXC_PAUSE)
+#define pEMAC_RXC_ALLFRM ((volatile unsigned long *)EMAC_RXC_ALLFRM)
+#define pEMAC_RXC_ALLOCT ((volatile unsigned long *)EMAC_RXC_ALLOCT)
+#define pEMAC_RXC_TYPED ((volatile unsigned long *)EMAC_RXC_TYPED)
+#define pEMAC_RXC_SHORT ((volatile unsigned long *)EMAC_RXC_SHORT)
+#define pEMAC_RXC_EQ64 ((volatile unsigned long *)EMAC_RXC_EQ64)
+#define pEMAC_RXC_LT128 ((volatile unsigned long *)EMAC_RXC_LT128)
+#define pEMAC_RXC_LT256 ((volatile unsigned long *)EMAC_RXC_LT256)
+#define pEMAC_RXC_LT512 ((volatile unsigned long *)EMAC_RXC_LT512)
+#define pEMAC_RXC_LT1024 ((volatile unsigned long *)EMAC_RXC_LT1024)
+#define pEMAC_RXC_GE1024 ((volatile unsigned long *)EMAC_RXC_GE1024)
+
+#define pEMAC_TXC_OK ((volatile unsigned long *)EMAC_TXC_OK)
+#define pEMAC_TXC_1COL ((volatile unsigned long *)EMAC_TXC_1COL)
+#define pEMAC_TXC_GT1COL ((volatile unsigned long *)EMAC_TXC_GT1COL)
+#define pEMAC_TXC_OCTET ((volatile unsigned long *)EMAC_TXC_OCTET)
+#define pEMAC_TXC_DEFER ((volatile unsigned long *)EMAC_TXC_DEFER)
+#define pEMAC_TXC_LATECL ((volatile unsigned long *)EMAC_TXC_LATECL)
+#define pEMAC_TXC_XS_COL ((volatile unsigned long *)EMAC_TXC_XS_COL)
+#define pEMAC_TXC_DMAUND ((volatile unsigned long *)EMAC_TXC_DMAUND)
+#define pEMAC_TXC_CRSERR ((volatile unsigned long *)EMAC_TXC_CRSERR)
+#define pEMAC_TXC_UNICST ((volatile unsigned long *)EMAC_TXC_UNICST)
+#define pEMAC_TXC_MULTI ((volatile unsigned long *)EMAC_TXC_MULTI)
+#define pEMAC_TXC_BROAD ((volatile unsigned long *)EMAC_TXC_BROAD)
+#define pEMAC_TXC_XS_DFR ((volatile unsigned long *)EMAC_TXC_XS_DFR)
+#define pEMAC_TXC_MACCTL ((volatile unsigned long *)EMAC_TXC_MACCTL)
+#define pEMAC_TXC_ALLFRM ((volatile unsigned long *)EMAC_TXC_ALLFRM)
+#define pEMAC_TXC_ALLOCT ((volatile unsigned long *)EMAC_TXC_ALLOCT)
+#define pEMAC_TXC_EQ64 ((volatile unsigned long *)EMAC_TXC_EQ64)
+#define pEMAC_TXC_LT128 ((volatile unsigned long *)EMAC_TXC_LT128)
+#define pEMAC_TXC_LT256 ((volatile unsigned long *)EMAC_TXC_LT256)
+#define pEMAC_TXC_LT512 ((volatile unsigned long *)EMAC_TXC_LT512)
+#define pEMAC_TXC_LT1024 ((volatile unsigned long *)EMAC_TXC_LT1024)
+#define pEMAC_TXC_GE1024 ((volatile unsigned long *)EMAC_TXC_GE1024)
+#define pEMAC_TXC_ABORT ((volatile unsigned long *)EMAC_TXC_ABORT)
+
+
+/* EMAC PTP (IEEE 1588) (0xFFC030A0 - 0xFFC030EC)*/
+#define pEMAC_PTP_CTL ((volatile unsigned short *)EMAC_PTP_CTL)
+#define pEMAC_PTP_IE ((volatile unsigned short *)EMAC_PTP_IE)
+#define pEMAC_PTP_ISTAT ((volatile unsigned short *)EMAC_PTP_ISTAT)
+#define pEMAC_PTP_FOFF ((volatile unsigned long *)EMAC_PTP_FOFF)
+#define pEMAC_PTP_FV1 ((volatile unsigned long *)EMAC_PTP_FV1)
+#define pEMAC_PTP_FV2 ((volatile unsigned long *)EMAC_PTP_FV2)
+#define pEMAC_PTP_FV3 ((volatile unsigned long *)EMAC_PTP_FV3)
+#define pEMAC_PTP_ADDEND ((volatile unsigned long *)EMAC_PTP_ADDEND)
+#define pEMAC_PTP_ACCR ((volatile unsigned long *)EMAC_PTP_ACCR)
+#define pEMAC_PTP_OFFSET ((volatile unsigned long *)EMAC_PTP_OFFSET)
+#define pEMAC_PTP_TIMELO ((volatile unsigned long *)EMAC_PTP_TIMELO)
+#define pEMAC_PTP_TIMEHI ((volatile unsigned long *)EMAC_PTP_TIMEHI)
+#define pEMAC_PTP_RXSNAPLO ((volatile unsigned long *)EMAC_PTP_RXSNAPLO)
+#define pEMAC_PTP_RXSNAPHI ((volatile unsigned long *)EMAC_PTP_RXSNAPHI)
+#define pEMAC_PTP_TXSNAPLO ((volatile unsigned long *)EMAC_PTP_TXSNAPLO)
+#define pEMAC_PTP_TXSNAPHI ((volatile unsigned long *)EMAC_PTP_TXSNAPHI)
+#define pEMAC_PTP_ALARMLO ((volatile unsigned long *)EMAC_PTP_ALARMLO)
+#define pEMAC_PTP_ALARMHI ((volatile unsigned long *)EMAC_PTP_ALARMHI)
+#define pEMAC_PTP_ID_OFF ((volatile unsigned short *)EMAC_PTP_ID_OFF)
+#define pEMAC_PTP_ID_SNAP ((volatile unsigned long *)EMAC_PTP_ID_SNAP)
+#define pEMAC_PTP_PPS_STARTLO ((volatile unsigned long *)EMAC_PTP_PPS_STARTLO)
+#define pEMAC_PTP_PPS_STARTHI ((volatile unsigned long *)EMAC_PTP_PPS_STARTHI)
+#define pEMAC_PTP_PPS_PERIOD ((volatile unsigned long *)EMAC_PTP_PPS_PERIOD)
+
+
+/* SDH Registers (0xFFC03800 - 0xFFC03CFF)*/
+#define pSDH_PWR_CTL ((volatile unsigned short *)SDH_PWR_CTL)
+#define pSDH_CLK_CTL ((volatile unsigned short *)SDH_CLK_CTL)
+#define pSDH_ARGUMENT ((volatile unsigned long *)SDH_ARGUMENT)
+#define pSDH_COMMAND ((volatile unsigned short *)SDH_COMMAND)
+#define pSDH_RESP_CMD ((volatile unsigned short *)SDH_RESP_CMD)
+#define pSDH_RESPONSE0 ((volatile unsigned long *)SDH_RESPONSE0)
+#define pSDH_RESPONSE1 ((volatile unsigned long *)SDH_RESPONSE1)
+#define pSDH_RESPONSE2 ((volatile unsigned long *)SDH_RESPONSE2)
+#define pSDH_RESPONSE3 ((volatile unsigned long *)SDH_RESPONSE3)
+#define pSDH_DATA_TIMER ((volatile unsigned long *)SDH_DATA_TIMER)
+#define pSDH_DATA_LGTH ((volatile unsigned short *)SDH_DATA_LGTH)
+#define pSDH_DATA_CTL ((volatile unsigned short *)SDH_DATA_CTL)
+#define pSDH_DATA_CNT ((volatile unsigned short *)SDH_DATA_CNT)
+#define pSDH_STATUS ((volatile unsigned long *)SDH_STATUS)
+#define pSDH_STATUS_CLR ((volatile unsigned short *)SDH_STATUS_CLR)
+#define pSDH_MASK0 ((volatile unsigned long *)SDH_MASK0)
+#define pSDH_MASK1 ((volatile unsigned long *)SDH_MASK1)
+#define pSDH_FIFO_CNT ((volatile unsigned short *)SDH_FIFO_CNT)
+#define pSDH_FIFO ((volatile unsigned long *)SDH_FIFO)
+#define pSDH_E_STATUS ((volatile unsigned short *)SDH_E_STATUS)
+#define pSDH_E_MASK ((volatile unsigned short *)SDH_E_MASK)
+#define pSDH_CFG ((volatile unsigned short *)SDH_CFG)
+#define pSDH_RD_WAIT_EN ((volatile unsigned short *)SDH_RD_WAIT_EN)
+#define pSDH_PID0 ((volatile unsigned short *)SDH_PID0)
+#define pSDH_PID1 ((volatile unsigned short *)SDH_PID1)
+#define pSDH_PID2 ((volatile unsigned short *)SDH_PID2)
+#define pSDH_PID3 ((volatile unsigned short *)SDH_PID3)
+#define pSDH_PID4 ((volatile unsigned short *)SDH_PID4)
+#define pSDH_PID5 ((volatile unsigned short *)SDH_PID5)
+#define pSDH_PID6 ((volatile unsigned short *)SDH_PID6)
+#define pSDH_PID7 ((volatile unsigned short *)SDH_PID7)
+
+
+/* RSI Registers (0xFFC03800 - 0xFFC03CFF)*/
+#define pRSI_PWR_CONTROL ((volatile unsigned short *)RSI_PWR_CONTROL)
+#define pRSI_CLK_CONTROL ((volatile unsigned short *)RSI_CLK_CONTROL)
+#define pRSI_ARGUMENT ((volatile unsigned long *)RSI_ARGUMENT)
+#define pRSI_COMMAND ((volatile unsigned short *)RSI_COMMAND)
+#define pRSI_RESP_CMD ((volatile unsigned short *)RSI_RESP_CMD)
+#define pRSI_RESPONSE0 ((volatile unsigned long *)RSI_RESPONSE0)
+#define pRSI_RESPONSE1 ((volatile unsigned long *)RSI_RESPONSE1)
+#define pRSI_RESPONSE2 ((volatile unsigned long *)RSI_RESPONSE2)
+#define pRSI_RESPONSE3 ((volatile unsigned long *)RSI_RESPONSE3)
+#define pRSI_DATA_TIMER ((volatile unsigned long *)RSI_DATA_TIMER)
+#define pRSI_DATA_LGTH ((volatile unsigned short *)RSI_DATA_LGTH)
+#define pRSI_DATA_CONTROL ((volatile unsigned short *)RSI_DATA_CONTROL)
+#define pRSI_DATA_CNT ((volatile unsigned short *)RSI_DATA_CNT)
+#define pRSI_STATUS ((volatile unsigned long *)RSI_STATUS)
+#define pRSI_STATUSCL ((volatile unsigned short *)RSI_STATUSCL)
+#define pRSI_MASK0 ((volatile unsigned long *)RSI_MASK0)
+#define pRSI_MASK1 ((volatile unsigned long *)RSI_MASK1)
+#define pRSI_FIFO_CNT ((volatile unsigned short *)RSI_FIFO_CNT)
+#define pRSI_CEATA_CONTROL ((volatile unsigned short *)RSI_CEATA_CONTROL)
+#define pRSI_FIFO ((volatile unsigned long *)RSI_FIFO)
+#define pRSI_ESTAT ((volatile unsigned short *)RSI_ESTAT)
+#define pRSI_EMASK ((volatile unsigned short *)RSI_EMASK)
+#define pRSI_CONFIG ((volatile unsigned short *)RSI_CONFIG)
+#define pRSI_RD_WAIT_EN ((volatile unsigned short *)RSI_RD_WAIT_EN)
+#define pRSI_PID0 ((volatile unsigned short *)RSI_PID0)
+#define pRSI_PID1 ((volatile unsigned short *)RSI_PID1)
+#define pRSI_PID2 ((volatile unsigned short *)RSI_PID2)
+#define pRSI_PID3 ((volatile unsigned short *)RSI_PID3)
+
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif /* _CDEF_BF518_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** cdefBF51x_base.h
+**
+** Copyright (C) 2009 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for the registers common to the ADSP-BF51x peripherals.
+**
+***************************************************************/
+
+#ifndef _CDEF_BF51X_H
+#define _CDEF_BF51X_H
+
+#include <defBF51x_base.h>
+
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
+#endif /* _MISRA_RULES */
+
+#ifndef _PTR_TO_VOL_VOID_PTR
+#ifndef _USE_LEGACY_CDEF_BEHAVIOUR
+#define _PTR_TO_VOL_VOID_PTR (void * volatile *)
+#else
+#define _PTR_TO_VOL_VOID_PTR (volatile void **)
+#endif
+#endif
+
+
+/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
+#define pPLL_CTL ((volatile unsigned short *)PLL_CTL)
+#define pPLL_DIV ((volatile unsigned short *)PLL_DIV)
+#define pVR_CTL ((volatile unsigned short *)VR_CTL)
+#define pPLL_STAT ((volatile unsigned short *)PLL_STAT)
+#define pPLL_LOCKCNT ((volatile unsigned short *)PLL_LOCKCNT)
+#define pCHIPID ((volatile unsigned long *)CHIPID)
+
+
+/* System Interrupt Controller(0xFFC00100 - 0xFFC001FF) */
+#define pSWRST ((volatile unsigned short *)SWRST)
+#define pSYSCR ((volatile unsigned short *)SYSCR)
+
+#define pSIC_IMASK0 ((volatile unsigned long *)SIC_IMASK0) /* legacy register name (below) provided for backwards code compatibility */
+#define pSIC_IMASK ((volatile unsigned long *)SIC_IMASK0)
+#define pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0)
+#define pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1)
+#define pSIC_IAR2 ((volatile unsigned long *)SIC_IAR2)
+#define pSIC_IAR3 ((volatile unsigned long *)SIC_IAR3)
+#define pSIC_ISR0 ((volatile unsigned long *)SIC_ISR0) /* legacy register name (below) provided for backwards code compatibility */
+#define pSIC_ISR ((volatile unsigned long *)SIC_ISR0)
+#define pSIC_IWR0 ((volatile unsigned long *)SIC_IWR0) /* legacy register name (below) provided for backwards code compatibility */
+#define pSIC_IWR ((volatile unsigned long *)SIC_IWR0)
+
+/* SIC Additions to ADSP-BF51x(0xFFC0014C - 0xFFC00162) */
+#define pSIC_IMASK1 ((volatile unsigned long *)SIC_IMASK1)
+#define pSIC_IAR4 ((volatile unsigned long *)SIC_IAR4)
+#define pSIC_IAR5 ((volatile unsigned long *)SIC_IAR5)
+#define pSIC_IAR6 ((volatile unsigned long *)SIC_IAR6)
+#define pSIC_IAR7 ((volatile unsigned long *)SIC_IAR7)
+#define pSIC_ISR1 ((volatile unsigned long *)SIC_ISR1)
+#define pSIC_IWR1 ((volatile unsigned long *)SIC_IWR1)
+
+/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
+#define pWDOG_CTL ((volatile unsigned short *)WDOG_CTL)
+#define pWDOG_CNT ((volatile unsigned long *)WDOG_CNT)
+#define pWDOG_STAT ((volatile unsigned long *)WDOG_STAT)
+
+
+/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
+#define pRTC_STAT ((volatile unsigned long *)RTC_STAT)
+#define pRTC_ICTL ((volatile unsigned short *)RTC_ICTL)
+#define pRTC_ISTAT ((volatile unsigned short *)RTC_ISTAT)
+#define pRTC_SWCNT ((volatile unsigned short *)RTC_SWCNT)
+#define pRTC_ALARM ((volatile unsigned long *)RTC_ALARM)
+#define pRTC_FAST ((volatile unsigned short *)RTC_FAST)
+#define pRTC_PREN ((volatile unsigned short *)RTC_PREN)
+
+
+/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
+#define pUART0_THR ((volatile unsigned short *)UART0_THR)
+#define pUART0_RBR ((volatile unsigned short *)UART0_RBR)
+#define pUART0_DLL ((volatile unsigned short *)UART0_DLL)
+#define pUART0_IER ((volatile unsigned short *)UART0_IER)
+#define pUART0_DLH ((volatile unsigned short *)UART0_DLH)
+#define pUART0_IIR ((volatile unsigned short *)UART0_IIR)
+#define pUART0_LCR ((volatile unsigned short *)UART0_LCR)
+#define pUART0_MCR ((volatile unsigned short *)UART0_MCR)
+#define pUART0_LSR ((volatile unsigned short *)UART0_LSR)
+#define pUART0_MSR ((volatile unsigned short *)UART0_LSR)
+#define pUART0_SCR ((volatile unsigned short *)UART0_SCR)
+#define pUART0_GCTL ((volatile unsigned short *)UART0_GCTL)
+
+
+/* SPI0 Controller (0xFFC00500 - 0xFFC005FF)*/
+#define pSPI0_CTL ((volatile unsigned short *)SPI0_CTL)
+/* legacy register name (below) provided for backwards code compatibility */
+#define pSPI_CTL pSPI0_CTL
+#define pSPI0_FLG ((volatile unsigned short *)SPI0_FLG)
+/* legacy register name (below) provided for backwards code compatibility */
+#define pSPI_FLG pSPI0_FLG
+#define pSPI0_STAT ((volatile unsigned short *)SPI0_STAT)
+/* legacy register name (below) provided for backwards code compatibility */
+#define pSPI_STAT pSPI0_STAT
+#define pSPI0_TDBR ((volatile unsigned short *)SPI0_TDBR)
+/* legacy register name (below) provided for backwards code compatibility */
+#define pSPI_TDBR pSPI0_TDBR
+#define pSPI0_RDBR ((volatile unsigned short *)SPI0_RDBR)
+/* legacy register name (below) provided for backwards code compatibility */
+#define pSPI_RDBR pSPI0_RDBR
+#define pSPI0_BAUD ((volatile unsigned short *)SPI0_BAUD)
+/* legacy register name (below) provided for backwards code compatibility */
+#define pSPI_BAUD pSPI0_BAUD
+#define pSPI0_SHADOW ((volatile unsigned short *)SPI0_SHADOW)
+/* legacy register name (below) provided for backwards code compatibility */
+#define pSPI_SHADOW pSPI0_SHADOW
+
+
+/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
+#define pTIMER0_CONFIG ((volatile unsigned short *)TIMER0_CONFIG)
+#define pTIMER0_COUNTER ((volatile unsigned long *)TIMER0_COUNTER)
+#define pTIMER0_PERIOD ((volatile unsigned long *)TIMER0_PERIOD)
+#define pTIMER0_WIDTH ((volatile unsigned long *)TIMER0_WIDTH)
+
+#define pTIMER1_CONFIG ((volatile unsigned short *)TIMER1_CONFIG)
+#define pTIMER1_COUNTER ((volatile unsigned long *)TIMER1_COUNTER)
+#define pTIMER1_PERIOD ((volatile unsigned long *)TIMER1_PERIOD)
+#define pTIMER1_WIDTH ((volatile unsigned long *)TIMER1_WIDTH)
+
+#define pTIMER2_CONFIG ((volatile unsigned short *)TIMER2_CONFIG)
+#define pTIMER2_COUNTER ((volatile unsigned long *)TIMER2_COUNTER)
+#define pTIMER2_PERIOD ((volatile unsigned long *)TIMER2_PERIOD)
+#define pTIMER2_WIDTH ((volatile unsigned long *)TIMER2_WIDTH)
+
+#define pTIMER3_CONFIG ((volatile unsigned short *)TIMER3_CONFIG)
+#define pTIMER3_COUNTER ((volatile unsigned long *)TIMER3_COUNTER)
+#define pTIMER3_PERIOD ((volatile unsigned long *)TIMER3_PERIOD)
+#define pTIMER3_WIDTH ((volatile unsigned long *)TIMER3_WIDTH)
+
+#define pTIMER4_CONFIG ((volatile unsigned short *)TIMER4_CONFIG)
+#define pTIMER4_COUNTER ((volatile unsigned long *)TIMER4_COUNTER)
+#define pTIMER4_PERIOD ((volatile unsigned long *)TIMER4_PERIOD)
+#define pTIMER4_WIDTH ((volatile unsigned long *)TIMER4_WIDTH)
+
+#define pTIMER5_CONFIG ((volatile unsigned short *)TIMER5_CONFIG)
+#define pTIMER5_COUNTER ((volatile unsigned long *)TIMER5_COUNTER)
+#define pTIMER5_PERIOD ((volatile unsigned long *)TIMER5_PERIOD)
+#define pTIMER5_WIDTH ((volatile unsigned long *)TIMER5_WIDTH)
+
+#define pTIMER6_CONFIG ((volatile unsigned short *)TIMER6_CONFIG)
+#define pTIMER6_COUNTER ((volatile unsigned long *)TIMER6_COUNTER)
+#define pTIMER6_PERIOD ((volatile unsigned long *)TIMER6_PERIOD)
+#define pTIMER6_WIDTH ((volatile unsigned long *)TIMER6_WIDTH)
+
+#define pTIMER7_CONFIG ((volatile unsigned short *)TIMER7_CONFIG)
+#define pTIMER7_COUNTER ((volatile unsigned long *)TIMER7_COUNTER)
+#define pTIMER7_PERIOD ((volatile unsigned long *)TIMER7_PERIOD)
+#define pTIMER7_WIDTH ((volatile unsigned long *)TIMER7_WIDTH)
+
+#define pTIMER_ENABLE ((volatile unsigned short *)TIMER_ENABLE)
+#define pTIMER_DISABLE ((volatile unsigned short *)TIMER_DISABLE)
+#define pTIMER_STATUS ((volatile unsigned long *)TIMER_STATUS)
+
+
+/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
+#define pPORTFIO ((volatile unsigned short *)PORTFIO)
+#define pPORTFIO_CLEAR ((volatile unsigned short *)PORTFIO_CLEAR)
+#define pPORTFIO_SET ((volatile unsigned short *)PORTFIO_SET)
+#define pPORTFIO_TOGGLE ((volatile unsigned short *)PORTFIO_TOGGLE)
+#define pPORTFIO_MASKA ((volatile unsigned short *)PORTFIO_MASKA)
+#define pPORTFIO_MASKA_CLEAR ((volatile unsigned short *)PORTFIO_MASKA_CLEAR)
+#define pPORTFIO_MASKA_SET ((volatile unsigned short *)PORTFIO_MASKA_SET)
+#define pPORTFIO_MASKA_TOGGLE ((volatile unsigned short *)PORTFIO_MASKA_TOGGLE)
+#define pPORTFIO_MASKB ((volatile unsigned short *)PORTFIO_MASKB)
+#define pPORTFIO_MASKB_CLEAR ((volatile unsigned short *)PORTFIO_MASKB_CLEAR)
+#define pPORTFIO_MASKB_SET ((volatile unsigned short *)PORTFIO_MASKB_SET)
+#define pPORTFIO_MASKB_TOGGLE ((volatile unsigned short *)PORTFIO_MASKB_TOGGLE)
+#define pPORTFIO_DIR ((volatile unsigned short *)PORTFIO_DIR)
+#define pPORTFIO_POLAR ((volatile unsigned short *)PORTFIO_POLAR)
+#define pPORTFIO_EDGE ((volatile unsigned short *)PORTFIO_EDGE)
+#define pPORTFIO_BOTH ((volatile unsigned short *)PORTFIO_BOTH)
+#define pPORTFIO_INEN ((volatile unsigned short *)PORTFIO_INEN)
+
+
+/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
+#define pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1)
+#define pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2)
+#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV)
+#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV)
+#define pSPORT0_TX ((volatile unsigned long *)SPORT0_TX)
+#define pSPORT0_RX ((volatile unsigned long *)SPORT0_RX)
+#define pSPORT0_TX32 ((volatile unsigned long *)SPORT0_TX)
+#define pSPORT0_RX32 ((volatile unsigned long *)SPORT0_RX)
+#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX)
+#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX)
+#define pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1)
+#define pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2)
+#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV)
+#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV)
+#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT)
+#define pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL)
+#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1)
+#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2)
+#define pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0)
+#define pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1)
+#define pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2)
+#define pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3)
+#define pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0)
+#define pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1)
+#define pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2)
+#define pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3)
+
+
+/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
+#define pSPORT1_TCR1 ((volatile unsigned short *)SPORT1_TCR1)
+#define pSPORT1_TCR2 ((volatile unsigned short *)SPORT1_TCR2)
+#define pSPORT1_TCLKDIV ((volatile unsigned short *)SPORT1_TCLKDIV)
+#define pSPORT1_TFSDIV ((volatile unsigned short *)SPORT1_TFSDIV)
+#define pSPORT1_TX ((volatile unsigned long *)SPORT1_TX)
+#define pSPORT1_RX ((volatile unsigned long *)SPORT1_RX)
+#define pSPORT1_TX32 ((volatile unsigned long *)SPORT1_TX)
+#define pSPORT1_RX32 ((volatile unsigned long *)SPORT1_RX)
+#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX)
+#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX)
+#define pSPORT1_RCR1 ((volatile unsigned short *)SPORT1_RCR1)
+#define pSPORT1_RCR2 ((volatile unsigned short *)SPORT1_RCR2)
+#define pSPORT1_RCLKDIV ((volatile unsigned short *)SPORT1_RCLKDIV)
+#define pSPORT1_RFSDIV ((volatile unsigned short *)SPORT1_RFSDIV)
+#define pSPORT1_STAT ((volatile unsigned short *)SPORT1_STAT)
+#define pSPORT1_CHNL ((volatile unsigned short *)SPORT1_CHNL)
+#define pSPORT1_MCMC1 ((volatile unsigned short *)SPORT1_MCMC1)
+#define pSPORT1_MCMC2 ((volatile unsigned short *)SPORT1_MCMC2)
+#define pSPORT1_MTCS0 ((volatile unsigned long *)SPORT1_MTCS0)
+#define pSPORT1_MTCS1 ((volatile unsigned long *)SPORT1_MTCS1)
+#define pSPORT1_MTCS2 ((volatile unsigned long *)SPORT1_MTCS2)
+#define pSPORT1_MTCS3 ((volatile unsigned long *)SPORT1_MTCS3)
+#define pSPORT1_MRCS0 ((volatile unsigned long *)SPORT1_MRCS0)
+#define pSPORT1_MRCS1 ((volatile unsigned long *)SPORT1_MRCS1)
+#define pSPORT1_MRCS2 ((volatile unsigned long *)SPORT1_MRCS2)
+#define pSPORT1_MRCS3 ((volatile unsigned long *)SPORT1_MRCS3)
+
+
+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
+#define pEBIU_AMGCTL ((volatile unsigned short *)EBIU_AMGCTL)
+#define pEBIU_AMBCTL0 ((volatile unsigned long *)EBIU_AMBCTL0)
+#define pEBIU_AMBCTL1 ((volatile unsigned long *)EBIU_AMBCTL1)
+#define pEBIU_SDGCTL ((volatile unsigned long *)EBIU_SDGCTL)
+#define pEBIU_SDBCTL ((volatile unsigned short *)EBIU_SDBCTL)
+#define pEBIU_SDRRC ((volatile unsigned short *)EBIU_SDRRC)
+#define pEBIU_SDSTAT ((volatile unsigned short *)EBIU_SDSTAT)
+
+
+/* DMA Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */
+#define pDMA_TC_PER ((volatile unsigned short *)DMA_TC_PER)
+#define pDMA_TC_CNT ((volatile unsigned short *)DMA_TC_CNT)
+
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
+#define pDMA_TCPER ((volatile unsigned short *)DMA_TCPER)
+#define pDMA_TCCNT ((volatile unsigned short *)DMA_TCCNT)
+
+/* DMA Controller (0xFFC00C00 - FFC00FFF)*/
+#define pDMA0_CONFIG ((volatile unsigned short *)DMA0_CONFIG)
+#define pDMA0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA0_NEXT_DESC_PTR)
+#define pDMA0_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA0_START_ADDR)
+#define pDMA0_X_COUNT ((volatile unsigned short *)DMA0_X_COUNT)
+#define pDMA0_Y_COUNT ((volatile unsigned short *)DMA0_Y_COUNT)
+#define pDMA0_X_MODIFY ((volatile signed short *)DMA0_X_MODIFY)
+#define pDMA0_Y_MODIFY ((volatile signed short *)DMA0_Y_MODIFY)
+#define pDMA0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA0_CURR_DESC_PTR)
+#define pDMA0_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA0_CURR_ADDR)
+#define pDMA0_CURR_X_COUNT ((volatile unsigned short *)DMA0_CURR_X_COUNT)
+#define pDMA0_CURR_Y_COUNT ((volatile unsigned short *)DMA0_CURR_Y_COUNT)
+#define pDMA0_IRQ_STATUS ((volatile unsigned short *)DMA0_IRQ_STATUS)
+#define pDMA0_PERIPHERAL_MAP ((volatile unsigned short *)DMA0_PERIPHERAL_MAP)
+
+#define pDMA1_CONFIG ((volatile unsigned short *)DMA1_CONFIG)
+#define pDMA1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_NEXT_DESC_PTR)
+#define pDMA1_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_START_ADDR)
+#define pDMA1_X_COUNT ((volatile unsigned short *)DMA1_X_COUNT)
+#define pDMA1_Y_COUNT ((volatile unsigned short *)DMA1_Y_COUNT)
+#define pDMA1_X_MODIFY ((volatile signed short *)DMA1_X_MODIFY)
+#define pDMA1_Y_MODIFY ((volatile signed short *)DMA1_Y_MODIFY)
+#define pDMA1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_CURR_DESC_PTR)
+#define pDMA1_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_CURR_ADDR)
+#define pDMA1_CURR_X_COUNT ((volatile unsigned short *)DMA1_CURR_X_COUNT)
+#define pDMA1_CURR_Y_COUNT ((volatile unsigned short *)DMA1_CURR_Y_COUNT)
+#define pDMA1_IRQ_STATUS ((volatile unsigned short *)DMA1_IRQ_STATUS)
+#define pDMA1_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_PERIPHERAL_MAP)
+
+#define pDMA2_CONFIG ((volatile unsigned short *)DMA2_CONFIG)
+#define pDMA2_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_NEXT_DESC_PTR)
+#define pDMA2_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_START_ADDR)
+#define pDMA2_X_COUNT ((volatile unsigned short *)DMA2_X_COUNT)
+#define pDMA2_Y_COUNT ((volatile unsigned short *)DMA2_Y_COUNT)
+#define pDMA2_X_MODIFY ((volatile signed short *)DMA2_X_MODIFY)
+#define pDMA2_Y_MODIFY ((volatile signed short *)DMA2_Y_MODIFY)
+#define pDMA2_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_CURR_DESC_PTR)
+#define pDMA2_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_CURR_ADDR)
+#define pDMA2_CURR_X_COUNT ((volatile unsigned short *)DMA2_CURR_X_COUNT)
+#define pDMA2_CURR_Y_COUNT ((volatile unsigned short *)DMA2_CURR_Y_COUNT)
+#define pDMA2_IRQ_STATUS ((volatile unsigned short *)DMA2_IRQ_STATUS)
+#define pDMA2_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_PERIPHERAL_MAP)
+
+#define pDMA3_CONFIG ((volatile unsigned short *)DMA3_CONFIG)
+#define pDMA3_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA3_NEXT_DESC_PTR)
+#define pDMA3_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA3_START_ADDR)
+#define pDMA3_X_COUNT ((volatile unsigned short *)DMA3_X_COUNT)
+#define pDMA3_Y_COUNT ((volatile unsigned short *)DMA3_Y_COUNT)
+#define pDMA3_X_MODIFY ((volatile signed short *)DMA3_X_MODIFY)
+#define pDMA3_Y_MODIFY ((volatile signed short *)DMA3_Y_MODIFY)
+#define pDMA3_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA3_CURR_DESC_PTR)
+#define pDMA3_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA3_CURR_ADDR)
+#define pDMA3_CURR_X_COUNT ((volatile unsigned short *)DMA3_CURR_X_COUNT)
+#define pDMA3_CURR_Y_COUNT ((volatile unsigned short *)DMA3_CURR_Y_COUNT)
+#define pDMA3_IRQ_STATUS ((volatile unsigned short *)DMA3_IRQ_STATUS)
+#define pDMA3_PERIPHERAL_MAP ((volatile unsigned short *)DMA3_PERIPHERAL_MAP)
+
+#define pDMA4_CONFIG ((volatile unsigned short *)DMA4_CONFIG)
+#define pDMA4_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA4_NEXT_DESC_PTR)
+#define pDMA4_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA4_START_ADDR)
+#define pDMA4_X_COUNT ((volatile unsigned short *)DMA4_X_COUNT)
+#define pDMA4_Y_COUNT ((volatile unsigned short *)DMA4_Y_COUNT)
+#define pDMA4_X_MODIFY ((volatile signed short *)DMA4_X_MODIFY)
+#define pDMA4_Y_MODIFY ((volatile signed short *)DMA4_Y_MODIFY)
+#define pDMA4_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA4_CURR_DESC_PTR)
+#define pDMA4_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA4_CURR_ADDR)
+#define pDMA4_CURR_X_COUNT ((volatile unsigned short *)DMA4_CURR_X_COUNT)
+#define pDMA4_CURR_Y_COUNT ((volatile unsigned short *)DMA4_CURR_Y_COUNT)
+#define pDMA4_IRQ_STATUS ((volatile unsigned short *)DMA4_IRQ_STATUS)
+#define pDMA4_PERIPHERAL_MAP ((volatile unsigned short *)DMA4_PERIPHERAL_MAP)
+
+#define pDMA5_CONFIG ((volatile unsigned short *)DMA5_CONFIG)
+#define pDMA5_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA5_NEXT_DESC_PTR)
+#define pDMA5_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA5_START_ADDR)
+#define pDMA5_X_COUNT ((volatile unsigned short *)DMA5_X_COUNT)
+#define pDMA5_Y_COUNT ((volatile unsigned short *)DMA5_Y_COUNT)
+#define pDMA5_X_MODIFY ((volatile signed short *)DMA5_X_MODIFY)
+#define pDMA5_Y_MODIFY ((volatile signed short *)DMA5_Y_MODIFY)
+#define pDMA5_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA5_CURR_DESC_PTR)
+#define pDMA5_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA5_CURR_ADDR)
+#define pDMA5_CURR_X_COUNT ((volatile unsigned short *)DMA5_CURR_X_COUNT)
+#define pDMA5_CURR_Y_COUNT ((volatile unsigned short *)DMA5_CURR_Y_COUNT)
+#define pDMA5_IRQ_STATUS ((volatile unsigned short *)DMA5_IRQ_STATUS)
+#define pDMA5_PERIPHERAL_MAP ((volatile unsigned short *)DMA5_PERIPHERAL_MAP)
+
+#define pDMA6_CONFIG ((volatile unsigned short *)DMA6_CONFIG)
+#define pDMA6_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA6_NEXT_DESC_PTR)
+#define pDMA6_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA6_START_ADDR)
+#define pDMA6_X_COUNT ((volatile unsigned short *)DMA6_X_COUNT)
+#define pDMA6_Y_COUNT ((volatile unsigned short *)DMA6_Y_COUNT)
+#define pDMA6_X_MODIFY ((volatile signed short *)DMA6_X_MODIFY)
+#define pDMA6_Y_MODIFY ((volatile signed short *)DMA6_Y_MODIFY)
+#define pDMA6_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA6_CURR_DESC_PTR)
+#define pDMA6_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA6_CURR_ADDR)
+#define pDMA6_CURR_X_COUNT ((volatile unsigned short *)DMA6_CURR_X_COUNT)
+#define pDMA6_CURR_Y_COUNT ((volatile unsigned short *)DMA6_CURR_Y_COUNT)
+#define pDMA6_IRQ_STATUS ((volatile unsigned short *)DMA6_IRQ_STATUS)
+#define pDMA6_PERIPHERAL_MAP ((volatile unsigned short *)DMA6_PERIPHERAL_MAP)
+
+#define pDMA7_CONFIG ((volatile unsigned short *)DMA7_CONFIG)
+#define pDMA7_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA7_NEXT_DESC_PTR)
+#define pDMA7_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA7_START_ADDR)
+#define pDMA7_X_COUNT ((volatile unsigned short *)DMA7_X_COUNT)
+#define pDMA7_Y_COUNT ((volatile unsigned short *)DMA7_Y_COUNT)
+#define pDMA7_X_MODIFY ((volatile signed short *)DMA7_X_MODIFY)
+#define pDMA7_Y_MODIFY ((volatile signed short *)DMA7_Y_MODIFY)
+#define pDMA7_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA7_CURR_DESC_PTR)
+#define pDMA7_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA7_CURR_ADDR)
+#define pDMA7_CURR_X_COUNT ((volatile unsigned short *)DMA7_CURR_X_COUNT)
+#define pDMA7_CURR_Y_COUNT ((volatile unsigned short *)DMA7_CURR_Y_COUNT)
+#define pDMA7_IRQ_STATUS ((volatile unsigned short *)DMA7_IRQ_STATUS)
+#define pDMA7_PERIPHERAL_MAP ((volatile unsigned short *)DMA7_PERIPHERAL_MAP)
+
+#define pDMA8_CONFIG ((volatile unsigned short *)DMA8_CONFIG)
+#define pDMA8_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA8_NEXT_DESC_PTR)
+#define pDMA8_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA8_START_ADDR)
+#define pDMA8_X_COUNT ((volatile unsigned short *)DMA8_X_COUNT)
+#define pDMA8_Y_COUNT ((volatile unsigned short *)DMA8_Y_COUNT)
+#define pDMA8_X_MODIFY ((volatile signed short *)DMA8_X_MODIFY)
+#define pDMA8_Y_MODIFY ((volatile signed short *)DMA8_Y_MODIFY)
+#define pDMA8_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA8_CURR_DESC_PTR)
+#define pDMA8_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA8_CURR_ADDR)
+#define pDMA8_CURR_X_COUNT ((volatile unsigned short *)DMA8_CURR_X_COUNT)
+#define pDMA8_CURR_Y_COUNT ((volatile unsigned short *)DMA8_CURR_Y_COUNT)
+#define pDMA8_IRQ_STATUS ((volatile unsigned short *)DMA8_IRQ_STATUS)
+#define pDMA8_PERIPHERAL_MAP ((volatile unsigned short *)DMA8_PERIPHERAL_MAP)
+
+#define pDMA9_CONFIG ((volatile unsigned short *)DMA9_CONFIG)
+#define pDMA9_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA9_NEXT_DESC_PTR)
+#define pDMA9_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA9_START_ADDR)
+#define pDMA9_X_COUNT ((volatile unsigned short *)DMA9_X_COUNT)
+#define pDMA9_Y_COUNT ((volatile unsigned short *)DMA9_Y_COUNT)
+#define pDMA9_X_MODIFY ((volatile signed short *)DMA9_X_MODIFY)
+#define pDMA9_Y_MODIFY ((volatile signed short *)DMA9_Y_MODIFY)
+#define pDMA9_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA9_CURR_DESC_PTR)
+#define pDMA9_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA9_CURR_ADDR)
+#define pDMA9_CURR_X_COUNT ((volatile unsigned short *)DMA9_CURR_X_COUNT)
+#define pDMA9_CURR_Y_COUNT ((volatile unsigned short *)DMA9_CURR_Y_COUNT)
+#define pDMA9_IRQ_STATUS ((volatile unsigned short *)DMA9_IRQ_STATUS)
+#define pDMA9_PERIPHERAL_MAP ((volatile unsigned short *)DMA9_PERIPHERAL_MAP)
+
+#define pDMA10_CONFIG ((volatile unsigned short *)DMA10_CONFIG)
+#define pDMA10_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA10_NEXT_DESC_PTR)
+#define pDMA10_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA10_START_ADDR)
+#define pDMA10_X_COUNT ((volatile unsigned short *)DMA10_X_COUNT)
+#define pDMA10_Y_COUNT ((volatile unsigned short *)DMA10_Y_COUNT)
+#define pDMA10_X_MODIFY ((volatile signed short *)DMA10_X_MODIFY)
+#define pDMA10_Y_MODIFY ((volatile signed short *)DMA10_Y_MODIFY)
+#define pDMA10_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA10_CURR_DESC_PTR)
+#define pDMA10_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA10_CURR_ADDR)
+#define pDMA10_CURR_X_COUNT ((volatile unsigned short *)DMA10_CURR_X_COUNT)
+#define pDMA10_CURR_Y_COUNT ((volatile unsigned short *)DMA10_CURR_Y_COUNT)
+#define pDMA10_IRQ_STATUS ((volatile unsigned short *)DMA10_IRQ_STATUS)
+#define pDMA10_PERIPHERAL_MAP ((volatile unsigned short *)DMA10_PERIPHERAL_MAP)
+
+#define pDMA11_CONFIG ((volatile unsigned short *)DMA11_CONFIG)
+#define pDMA11_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA11_NEXT_DESC_PTR)
+#define pDMA11_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA11_START_ADDR)
+#define pDMA11_X_COUNT ((volatile unsigned short *)DMA11_X_COUNT)
+#define pDMA11_Y_COUNT ((volatile unsigned short *)DMA11_Y_COUNT)
+#define pDMA11_X_MODIFY ((volatile signed short *)DMA11_X_MODIFY)
+#define pDMA11_Y_MODIFY ((volatile signed short *)DMA11_Y_MODIFY)
+#define pDMA11_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA11_CURR_DESC_PTR)
+#define pDMA11_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA11_CURR_ADDR)
+#define pDMA11_CURR_X_COUNT ((volatile unsigned short *)DMA11_CURR_X_COUNT)
+#define pDMA11_CURR_Y_COUNT ((volatile unsigned short *)DMA11_CURR_Y_COUNT)
+#define pDMA11_IRQ_STATUS ((volatile unsigned short *)DMA11_IRQ_STATUS)
+#define pDMA11_PERIPHERAL_MAP ((volatile unsigned short *)DMA11_PERIPHERAL_MAP)
+
+#define pMDMA_D0_CONFIG ((volatile unsigned short *)MDMA_D0_CONFIG)
+#define pMDMA_D0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_D0_NEXT_DESC_PTR)
+#define pMDMA_D0_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_D0_START_ADDR)
+#define pMDMA_D0_X_COUNT ((volatile unsigned short *)MDMA_D0_X_COUNT)
+#define pMDMA_D0_Y_COUNT ((volatile unsigned short *)MDMA_D0_Y_COUNT)
+#define pMDMA_D0_X_MODIFY ((volatile signed short *)MDMA_D0_X_MODIFY)
+#define pMDMA_D0_Y_MODIFY ((volatile signed short *)MDMA_D0_Y_MODIFY)
+#define pMDMA_D0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_D0_CURR_DESC_PTR)
+#define pMDMA_D0_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_D0_CURR_ADDR)
+#define pMDMA_D0_CURR_X_COUNT ((volatile unsigned short *)MDMA_D0_CURR_X_COUNT)
+#define pMDMA_D0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D0_CURR_Y_COUNT)
+#define pMDMA_D0_IRQ_STATUS ((volatile unsigned short *)MDMA_D0_IRQ_STATUS)
+#define pMDMA_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D0_PERIPHERAL_MAP)
+
+#define pMDMA_S0_CONFIG ((volatile unsigned short *)MDMA_S0_CONFIG)
+#define pMDMA_S0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_S0_NEXT_DESC_PTR)
+#define pMDMA_S0_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_S0_START_ADDR)
+#define pMDMA_S0_X_COUNT ((volatile unsigned short *)MDMA_S0_X_COUNT)
+#define pMDMA_S0_Y_COUNT ((volatile unsigned short *)MDMA_S0_Y_COUNT)
+#define pMDMA_S0_X_MODIFY ((volatile signed short *)MDMA_S0_X_MODIFY)
+#define pMDMA_S0_Y_MODIFY ((volatile signed short *)MDMA_S0_Y_MODIFY)
+#define pMDMA_S0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_S0_CURR_DESC_PTR)
+#define pMDMA_S0_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_S0_CURR_ADDR)
+#define pMDMA_S0_CURR_X_COUNT ((volatile unsigned short *)MDMA_S0_CURR_X_COUNT)
+#define pMDMA_S0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S0_CURR_Y_COUNT)
+#define pMDMA_S0_IRQ_STATUS ((volatile unsigned short *)MDMA_S0_IRQ_STATUS)
+#define pMDMA_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S0_PERIPHERAL_MAP)
+
+#define pMDMA_D1_CONFIG ((volatile unsigned short *)MDMA_D1_CONFIG)
+#define pMDMA_D1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_D1_NEXT_DESC_PTR)
+#define pMDMA_D1_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_D1_START_ADDR)
+#define pMDMA_D1_X_COUNT ((volatile unsigned short *)MDMA_D1_X_COUNT)
+#define pMDMA_D1_Y_COUNT ((volatile unsigned short *)MDMA_D1_Y_COUNT)
+#define pMDMA_D1_X_MODIFY ((volatile signed short *)MDMA_D1_X_MODIFY)
+#define pMDMA_D1_Y_MODIFY ((volatile signed short *)MDMA_D1_Y_MODIFY)
+#define pMDMA_D1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_D1_CURR_DESC_PTR)
+#define pMDMA_D1_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_D1_CURR_ADDR)
+#define pMDMA_D1_CURR_X_COUNT ((volatile unsigned short *)MDMA_D1_CURR_X_COUNT)
+#define pMDMA_D1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D1_CURR_Y_COUNT)
+#define pMDMA_D1_IRQ_STATUS ((volatile unsigned short *)MDMA_D1_IRQ_STATUS)
+#define pMDMA_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D1_PERIPHERAL_MAP)
+
+#define pMDMA_S1_CONFIG ((volatile unsigned short *)MDMA_S1_CONFIG)
+#define pMDMA_S1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_S1_NEXT_DESC_PTR)
+#define pMDMA_S1_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_S1_START_ADDR)
+#define pMDMA_S1_X_COUNT ((volatile unsigned short *)MDMA_S1_X_COUNT)
+#define pMDMA_S1_Y_COUNT ((volatile unsigned short *)MDMA_S1_Y_COUNT)
+#define pMDMA_S1_X_MODIFY ((volatile signed short *)MDMA_S1_X_MODIFY)
+#define pMDMA_S1_Y_MODIFY ((volatile signed short *)MDMA_S1_Y_MODIFY)
+#define pMDMA_S1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_S1_CURR_DESC_PTR)
+#define pMDMA_S1_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_S1_CURR_ADDR)
+#define pMDMA_S1_CURR_X_COUNT ((volatile unsigned short *)MDMA_S1_CURR_X_COUNT)
+#define pMDMA_S1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S1_CURR_Y_COUNT)
+#define pMDMA_S1_IRQ_STATUS ((volatile unsigned short *)MDMA_S1_IRQ_STATUS)
+#define pMDMA_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S1_PERIPHERAL_MAP)
+
+
+/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
+#define pPPI_CONTROL ((volatile unsigned short *)PPI_CONTROL)
+#define pPPI_STATUS ((volatile unsigned short *)PPI_STATUS)
+#define pPPI_DELAY ((volatile unsigned short *)PPI_DELAY)
+#define pPPI_COUNT ((volatile unsigned short *)PPI_COUNT)
+#define pPPI_FRAME ((volatile unsigned short *)PPI_FRAME)
+
+
+/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
+#define pTWI_CLKDIV ((volatile unsigned short *)TWI_CLKDIV)
+#define pTWI_CONTROL ((volatile unsigned short *)TWI_CONTROL)
+#define pTWI_SLAVE_CTL ((volatile unsigned short *)TWI_SLAVE_CTL)
+#define pTWI_SLAVE_STAT ((volatile unsigned short *)TWI_SLAVE_STAT)
+#define pTWI_SLAVE_ADDR ((volatile unsigned short *)TWI_SLAVE_ADDR)
+#define pTWI_MASTER_CTL ((volatile unsigned short *)TWI_MASTER_CTL)
+#define pTWI_MASTER_STAT ((volatile unsigned short *)TWI_MASTER_STAT)
+#define pTWI_MASTER_ADDR ((volatile unsigned short *)TWI_MASTER_ADDR)
+#define pTWI_INT_STAT ((volatile unsigned short *)TWI_INT_STAT)
+#define pTWI_INT_MASK ((volatile unsigned short *)TWI_INT_MASK)
+#define pTWI_FIFO_CTL ((volatile unsigned short *)TWI_FIFO_CTL)
+#define pTWI_FIFO_STAT ((volatile unsigned short *)TWI_FIFO_STAT)
+#define pTWI_XMT_DATA8 ((volatile unsigned short *)TWI_XMT_DATA8)
+#define pTWI_XMT_DATA16 ((volatile unsigned short *)TWI_XMT_DATA16)
+#define pTWI_RCV_DATA8 ((volatile unsigned short *)TWI_RCV_DATA8)
+#define pTWI_RCV_DATA16 ((volatile unsigned short *)TWI_RCV_DATA16)
+
+
+/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
+#define pPORTGIO ((volatile unsigned short *)PORTGIO)
+#define pPORTGIO_CLEAR ((volatile unsigned short *)PORTGIO_CLEAR)
+#define pPORTGIO_SET ((volatile unsigned short *)PORTGIO_SET)
+#define pPORTGIO_TOGGLE ((volatile unsigned short *)PORTGIO_TOGGLE)
+#define pPORTGIO_MASKA ((volatile unsigned short *)PORTGIO_MASKA)
+#define pPORTGIO_MASKA_CLEAR ((volatile unsigned short *)PORTGIO_MASKA_CLEAR)
+#define pPORTGIO_MASKA_SET ((volatile unsigned short *)PORTGIO_MASKA_SET)
+#define pPORTGIO_MASKA_TOGGLE ((volatile unsigned short *)PORTGIO_MASKA_TOGGLE)
+#define pPORTGIO_MASKB ((volatile unsigned short *)PORTGIO_MASKB)
+#define pPORTGIO_MASKB_CLEAR ((volatile unsigned short *)PORTGIO_MASKB_CLEAR)
+#define pPORTGIO_MASKB_SET ((volatile unsigned short *)PORTGIO_MASKB_SET)
+#define pPORTGIO_MASKB_TOGGLE ((volatile unsigned short *)PORTGIO_MASKB_TOGGLE)
+#define pPORTGIO_DIR ((volatile unsigned short *)PORTGIO_DIR)
+#define pPORTGIO_POLAR ((volatile unsigned short *)PORTGIO_POLAR)
+#define pPORTGIO_EDGE ((volatile unsigned short *)PORTGIO_EDGE)
+#define pPORTGIO_BOTH ((volatile unsigned short *)PORTGIO_BOTH)
+#define pPORTGIO_INEN ((volatile unsigned short *)PORTGIO_INEN)
+
+
+/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
+#define pPORTHIO ((volatile unsigned short *)PORTHIO)
+#define pPORTHIO_CLEAR ((volatile unsigned short *)PORTHIO_CLEAR)
+#define pPORTHIO_SET ((volatile unsigned short *)PORTHIO_SET)
+#define pPORTHIO_TOGGLE ((volatile unsigned short *)PORTHIO_TOGGLE)
+#define pPORTHIO_MASKA ((volatile unsigned short *)PORTHIO_MASKA)
+#define pPORTHIO_MASKA_CLEAR ((volatile unsigned short *)PORTHIO_MASKA_CLEAR)
+#define pPORTHIO_MASKA_SET ((volatile unsigned short *)PORTHIO_MASKA_SET)
+#define pPORTHIO_MASKA_TOGGLE ((volatile unsigned short *)PORTHIO_MASKA_TOGGLE)
+#define pPORTHIO_MASKB ((volatile unsigned short *)PORTHIO_MASKB)
+#define pPORTHIO_MASKB_CLEAR ((volatile unsigned short *)PORTHIO_MASKB_CLEAR)
+#define pPORTHIO_MASKB_SET ((volatile unsigned short *)PORTHIO_MASKB_SET)
+#define pPORTHIO_MASKB_TOGGLE ((volatile unsigned short *)PORTHIO_MASKB_TOGGLE)
+#define pPORTHIO_DIR ((volatile unsigned short *)PORTHIO_DIR)
+#define pPORTHIO_POLAR ((volatile unsigned short *)PORTHIO_POLAR)
+#define pPORTHIO_EDGE ((volatile unsigned short *)PORTHIO_EDGE)
+#define pPORTHIO_BOTH ((volatile unsigned short *)PORTHIO_BOTH)
+#define pPORTHIO_INEN ((volatile unsigned short *)PORTHIO_INEN)
+
+
+/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
+#define pUART1_THR ((volatile unsigned short *)UART1_THR)
+#define pUART1_RBR ((volatile unsigned short *)UART1_RBR)
+#define pUART1_DLL ((volatile unsigned short *)UART1_DLL)
+#define pUART1_IER ((volatile unsigned short *)UART1_IER)
+#define pUART1_DLH ((volatile unsigned short *)UART1_DLH)
+#define pUART1_IIR ((volatile unsigned short *)UART1_IIR)
+#define pUART1_LCR ((volatile unsigned short *)UART1_LCR)
+#define pUART1_MCR ((volatile unsigned short *)UART1_MCR)
+#define pUART1_LSR ((volatile unsigned short *)UART1_LSR)
+#define pUART1_MSR ((volatile unsigned short *)UART1_LSR)
+#define pUART1_SCR ((volatile unsigned short *)UART1_SCR)
+#define pUART1_GCTL ((volatile unsigned short *)UART1_GCTL)
+
+
+/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
+#define pPORTF_FER ((volatile unsigned short *)PORTF_FER)
+#define pPORTG_FER ((volatile unsigned short *)PORTG_FER)
+#define pPORTH_FER ((volatile unsigned short *)PORTH_FER)
+
+
+/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
+#define pHMDMA0_CONTROL ((volatile unsigned short *)HMDMA0_CONTROL)
+#define pHMDMA0_ECINIT ((volatile unsigned short *)HMDMA0_ECINIT)
+#define pHMDMA0_BCINIT ((volatile unsigned short *)HMDMA0_BCINIT)
+#define pHMDMA0_ECURGENT ((volatile unsigned short *)HMDMA0_ECURGENT)
+#define pHMDMA0_ECOVERFLOW ((volatile unsigned short *)HMDMA0_ECOVERFLOW)
+#define pHMDMA0_ECOUNT ((volatile unsigned short *)HMDMA0_ECOUNT)
+#define pHMDMA0_BCOUNT ((volatile unsigned short *)HMDMA0_BCOUNT)
+
+#define pHMDMA1_CONTROL ((volatile unsigned short *)HMDMA1_CONTROL)
+#define pHMDMA1_ECINIT ((volatile unsigned short *)HMDMA1_ECINIT)
+#define pHMDMA1_BCINIT ((volatile unsigned short *)HMDMA1_BCINIT)
+#define pHMDMA1_ECURGENT ((volatile unsigned short *)HMDMA1_ECURGENT)
+#define pHMDMA1_ECOVERFLOW ((volatile unsigned short *)HMDMA1_ECOVERFLOW)
+#define pHMDMA1_ECOUNT ((volatile unsigned short *)HMDMA1_ECOUNT)
+#define pHMDMA1_BCOUNT ((volatile unsigned short *)HMDMA1_BCOUNT)
+
+
+/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
+#define pPORTF_MUX ((volatile unsigned short *)PORTF_MUX)
+#define pPORTG_MUX ((volatile unsigned short *)PORTG_MUX)
+#define pPORTH_MUX ((volatile unsigned short *)PORTH_MUX)
+#define pPORTF_DRIVE ((volatile unsigned short *)PORTF_DRIVE)
+#define pPORTG_DRIVE ((volatile unsigned short *)PORTG_DRIVE)
+#define pPORTH_DRIVE ((volatile unsigned short *)PORTH_DRIVE)
+#define pPORTF_HYSTERESIS ((volatile unsigned short *)PORTF_HYSTERESIS)
+#define pPORTG_HYSTERESIS ((volatile unsigned short *)PORTG_HYSTERESIS)
+#define pPORTH_HYSTERESIS ((volatile unsigned short *)PORTH_HYSTERESIS)
+#define pNONGPIO_DRIVE ((volatile unsigned short *)NONGPIO_DRIVE)
+#define pNONGPIO_HYSTERESIS ((volatile unsigned short *)NONGPIO_HYSTERESIS)
+
+
+/* SPI1 Controller (0xFFC03400 - 0xFFC034FF)*/
+#define pSPI1_CTL ((volatile unsigned short *)SPI1_CTL)
+#define pSPI1_FLG ((volatile unsigned short *)SPI1_FLG)
+#define pSPI1_STAT ((volatile unsigned short *)SPI1_STAT)
+#define pSPI1_TDBR ((volatile unsigned short *)SPI1_TDBR)
+#define pSPI1_RDBR ((volatile unsigned short *)SPI1_RDBR)
+#define pSPI1_BAUD ((volatile unsigned short *)SPI1_BAUD)
+#define pSPI1_SHADOW ((volatile unsigned short *)SPI1_SHADOW)
+
+
+/* Counter Registers (0xFFC03500 - 0xFFC035FF)*/
+#define pCNT_CONFIG ((volatile unsigned short *)CNT_CONFIG)
+#define pCNT_IMASK ((volatile unsigned short *)CNT_IMASK)
+#define pCNT_STATUS ((volatile unsigned short *)CNT_STATUS)
+#define pCNT_COMMAND ((volatile unsigned short *)CNT_COMMAND)
+#define pCNT_DEBOUNCE ((volatile unsigned short *)CNT_DEBOUNCE)
+#define pCNT_COUNTER ((volatile unsigned long *)CNT_COUNTER)
+#define pCNT_MAX ((volatile unsigned long *)CNT_MAX)
+#define pCNT_MIN ((volatile unsigned long *)CNT_MIN)
+
+
+/* OTP Registers (0xFFC03600 - 0xFFC036FF) */
+/* Security Registers */
+#define pSECURE_SYSSWT ((volatile unsigned long *)SECURE_SYSSWT)
+#define pSECURE_CONTROL ((volatile unsigned short *)SECURE_CONTROL)
+#define pSECURE_STATUS ((volatile unsigned short *)SECURE_STATUS)
+
+/* OTP Read/Write Data Buffer Registers */
+#define pOTP_DATA0 ((volatile unsigned long *)OTP_DATA0)
+#define pOTP_DATA1 ((volatile unsigned long *)OTP_DATA1)
+#define pOTP_DATA2 ((volatile unsigned long *)OTP_DATA2)
+#define pOTP_DATA3 ((volatile unsigned long *)OTP_DATA3)
+
+
+/* PWM 3PHASE (0xFFC03700 - 0xFFC037FF)*/
+#define pPWM_CTRL ((volatile unsigned short *)PWM_CTRL)
+#define pPWM_STAT ((volatile unsigned short *)PWM_STAT)
+#define pPWM_TM ((volatile unsigned short *)PWM_TM)
+#define pPWM_DT ((volatile unsigned short *)PWM_DT)
+#define pPWM_GATE ((volatile unsigned short *)PWM_GATE)
+#define pPWM_CHA ((volatile unsigned short *)PWM_CHA)
+#define pPWM_CHB ((volatile unsigned short *)PWM_CHB)
+#define pPWM_CHC ((volatile unsigned short *)PWM_CHC)
+#define pPWM_SEG ((volatile unsigned short *)PWM_SEG)
+#define pPWM_SYNCWT ((volatile unsigned short *)PWM_SYNCWT)
+#define pPWM_CHAL ((volatile unsigned short *)PWM_CHAL)
+#define pPWM_CHBL ((volatile unsigned short *)PWM_CHBL)
+#define pPWM_CHCL ((volatile unsigned short *)PWM_CHCL)
+#define pPWM_LSI ((volatile unsigned short *)PWM_LSI)
+#define pPWM_STAT2 ((volatile unsigned short *)PWM_STAT2)
+
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+
+#endif /*_CDEF_BF51X_H*/
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** Copyright (C) 2009 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for the ADSP-BF523 peripherals.
+**
+************************************************************************************
+** System MMR Register Map
+************************************************************************************/
+
+#ifndef _CDEF_BF523_H
+#define _CDEF_BF523_H
+
+/* include all Core registers and bit definitions */
+#include <defBF523.h>
+
+/* include core specific register pointer definitions */
+#include <cdef_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF523 */
+
+/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
+#include <cdefBF52x_base.h>
+
+#endif /* _CDEF_BF523_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** Copyright (C) 2009 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for the ADSP-BF524 peripherals.
+**
+************************************************************************************
+** System MMR Register Map
+************************************************************************************/
+
+#ifndef _CDEF_BF524_H
+#define _CDEF_BF524_H
+
+/* include all Core registers and bit definitions */
+#include <defBF524.h>
+
+/* include core specific register pointer definitions */
+#include <cdef_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF524 */
+
+/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
+#include <cdefBF52x_base.h>
+
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
+#endif /* _MISRA_RULES */
+
+/* The following are the #defines needed by ADSP-BF524 that are not in the common header */
+
+/* USB Control Registers */
+
+#define pUSB_FADDR ((volatile unsigned short *)USB_FADDR)
+#define pUSB_POWER ((volatile unsigned short *)USB_POWER)
+#define pUSB_INTRTX ((volatile unsigned short *)USB_INTRTX)
+#define pUSB_INTRRX ((volatile unsigned short *)USB_INTRRX)
+#define pUSB_INTRTXE ((volatile unsigned short *)USB_INTRTXE)
+#define pUSB_INTRRXE ((volatile unsigned short *)USB_INTRRXE)
+#define pUSB_INTRUSB ((volatile unsigned short *)USB_INTRUSB)
+#define pUSB_INTRUSBE ((volatile unsigned short *)USB_INTRUSBE)
+#define pUSB_FRAME ((volatile unsigned short *)USB_FRAME)
+#define pUSB_INDEX ((volatile unsigned short *)USB_INDEX)
+#define pUSB_TESTMODE ((volatile unsigned short *)USB_TESTMODE)
+#define pUSB_GLOBINTR ((volatile unsigned short *)USB_GLOBINTR)
+#define pUSB_GLOBAL_CTL ((volatile unsigned short *)USB_GLOBAL_CTL)
+
+/* USB Packet Control Registers */
+
+#define pUSB_TX_MAX_PACKET ((volatile unsigned short *)USB_TX_MAX_PACKET)
+#define pUSB_CSR0 ((volatile unsigned short *)USB_CSR0)
+#define pUSB_TXCSR ((volatile unsigned short *)USB_TXCSR)
+#define pUSB_RX_MAX_PACKET ((volatile unsigned short *)USB_RX_MAX_PACKET)
+#define pUSB_RXCSR ((volatile unsigned short *)USB_RXCSR)
+#define pUSB_COUNT0 ((volatile unsigned short *)USB_COUNT0)
+#define pUSB_RXCOUNT ((volatile unsigned short *)USB_RXCOUNT)
+#define pUSB_TXTYPE ((volatile unsigned short *)USB_TXTYPE)
+#define pUSB_NAKLIMIT0 ((volatile unsigned short *)USB_NAKLIMIT0)
+#define pUSB_TXINTERVAL ((volatile unsigned short *)USB_TXINTERVAL)
+#define pUSB_RXTYPE ((volatile unsigned short *)USB_RXTYPE)
+#define pUSB_RXINTERVAL ((volatile unsigned short *)USB_RXINTERVAL)
+#define pUSB_TXCOUNT ((volatile unsigned short *)USB_TXCOUNT)
+
+/* USB Endpoint FIFO Registers */
+
+#define pUSB_EP0_FIFO ((volatile unsigned short *)USB_EP0_FIFO)
+#define pUSB_EP1_FIFO ((volatile unsigned short *)USB_EP1_FIFO)
+#define pUSB_EP2_FIFO ((volatile unsigned short *)USB_EP2_FIFO)
+#define pUSB_EP3_FIFO ((volatile unsigned short *)USB_EP3_FIFO)
+#define pUSB_EP4_FIFO ((volatile unsigned short *)USB_EP4_FIFO)
+#define pUSB_EP5_FIFO ((volatile unsigned short *)USB_EP5_FIFO)
+#define pUSB_EP6_FIFO ((volatile unsigned short *)USB_EP6_FIFO)
+#define pUSB_EP7_FIFO ((volatile unsigned short *)USB_EP7_FIFO)
+
+/* USB OTG Control Registers */
+
+#define pUSB_OTG_DEV_CTL ((volatile unsigned short *)USB_OTG_DEV_CTL)
+#define pUSB_OTG_VBUS_IRQ ((volatile unsigned short *)USB_OTG_VBUS_IRQ)
+#define pUSB_OTG_VBUS_MASK ((volatile unsigned short *)USB_OTG_VBUS_MASK)
+
+/* USB Phy Control Registers */
+
+#define pUSB_LINKINFO ((volatile unsigned short *)USB_LINKINFO)
+#define pUSB_VPLEN ((volatile unsigned short *)USB_VPLEN)
+#define pUSB_HS_EOF1 ((volatile unsigned short *)USB_HS_EOF1)
+#define pUSB_FS_EOF1 ((volatile unsigned short *)USB_FS_EOF1)
+#define pUSB_LS_EOF1 ((volatile unsigned short *)USB_LS_EOF1)
+
+/* (APHY_CNTRL is for ADI usage only) */
+
+#define pUSB_APHY_CNTRL ((volatile unsigned short *)USB_APHY_CNTRL)
+
+/* (APHY_CALIB is for ADI usage only) */
+
+#define pUSB_APHY_CALIB ((volatile unsigned short *)USB_APHY_CALIB)
+
+#define pUSB_APHY_CNTRL2 ((volatile unsigned short *)USB_APHY_CNTRL2)
+
+/* (PHY_TEST is for ADI usage only) */
+
+#define pUSB_PHY_TEST ((volatile unsigned short *)USB_PHY_TEST)
+
+#define pUSB_PLLOSC_CTRL ((volatile unsigned short *)USB_PLLOSC_CTRL)
+#define pUSB_SRP_CLKDIV ((volatile unsigned short *)USB_SRP_CLKDIV)
+
+/* USB Endpoint 0 Control Registers */
+
+#define pUSB_EP_NI0_TXMAXP ((volatile unsigned short *)USB_EP_NI0_TXMAXP)
+#define pUSB_EP_NI0_TXCSR ((volatile unsigned short *)USB_EP_NI0_TXCSR)
+#define pUSB_EP_NI0_RXMAXP ((volatile unsigned short *)USB_EP_NI0_RXMAXP)
+#define pUSB_EP_NI0_RXCSR ((volatile unsigned short *)USB_EP_NI0_RXCSR)
+#define pUSB_EP_NI0_RXCOUNT ((volatile unsigned short *)USB_EP_NI0_RXCOUNT)
+#define pUSB_EP_NI0_TXTYPE ((volatile unsigned short *)USB_EP_NI0_TXTYPE)
+#define pUSB_EP_NI0_TXINTERVAL ((volatile unsigned short *)USB_EP_NI0_TXINTERVAL)
+#define pUSB_EP_NI0_RXTYPE ((volatile unsigned short *)USB_EP_NI0_RXTYPE)
+#define pUSB_EP_NI0_RXINTERVAL ((volatile unsigned short *)USB_EP_NI0_RXINTERVAL)
+#define pUSB_EP_NI0_TXCOUNT ((volatile unsigned short *)USB_EP_NI0_TXCOUNT)
+
+/* USB Endpoint 1 Control Registers */
+
+#define pUSB_EP_NI1_TXMAXP ((volatile unsigned short *)USB_EP_NI1_TXMAXP)
+#define pUSB_EP_NI1_TXCSR ((volatile unsigned short *)USB_EP_NI1_TXCSR)
+#define pUSB_EP_NI1_RXMAXP ((volatile unsigned short *)USB_EP_NI1_RXMAXP)
+#define pUSB_EP_NI1_RXCSR ((volatile unsigned short *)USB_EP_NI1_RXCSR)
+#define pUSB_EP_NI1_RXCOUNT ((volatile unsigned short *)USB_EP_NI1_RXCOUNT)
+#define pUSB_EP_NI1_TXTYPE ((volatile unsigned short *)USB_EP_NI1_TXTYPE)
+#define pUSB_EP_NI1_TXINTERVAL ((volatile unsigned short *)USB_EP_NI1_TXINTERVAL)
+#define pUSB_EP_NI1_RXTYPE ((volatile unsigned short *)USB_EP_NI1_RXTYPE)
+#define pUSB_EP_NI1_RXINTERVAL ((volatile unsigned short *)USB_EP_NI1_RXINTERVAL)
+#define pUSB_EP_NI1_TXCOUNT ((volatile unsigned short *)USB_EP_NI1_TXCOUNT)
+
+/* USB Endpoint 2 Control Registers */
+
+#define pUSB_EP_NI2_TXMAXP ((volatile unsigned short *)USB_EP_NI2_TXMAXP)
+#define pUSB_EP_NI2_TXCSR ((volatile unsigned short *)USB_EP_NI2_TXCSR)
+#define pUSB_EP_NI2_RXMAXP ((volatile unsigned short *)USB_EP_NI2_RXMAXP)
+#define pUSB_EP_NI2_RXCSR ((volatile unsigned short *)USB_EP_NI2_RXCSR)
+#define pUSB_EP_NI2_RXCOUNT ((volatile unsigned short *)USB_EP_NI2_RXCOUNT)
+#define pUSB_EP_NI2_TXTYPE ((volatile unsigned short *)USB_EP_NI2_TXTYPE)
+#define pUSB_EP_NI2_TXINTERVAL ((volatile unsigned short *)USB_EP_NI2_TXINTERVAL)
+#define pUSB_EP_NI2_RXTYPE ((volatile unsigned short *)USB_EP_NI2_RXTYPE)
+#define pUSB_EP_NI2_RXINTERVAL ((volatile unsigned short *)USB_EP_NI2_RXINTERVAL)
+#define pUSB_EP_NI2_TXCOUNT ((volatile unsigned short *)USB_EP_NI2_TXCOUNT)
+
+/* USB Endpoint 3 Control Registers */
+
+#define pUSB_EP_NI3_TXMAXP ((volatile unsigned short *)USB_EP_NI3_TXMAXP)
+#define pUSB_EP_NI3_TXCSR ((volatile unsigned short *)USB_EP_NI3_TXCSR)
+#define pUSB_EP_NI3_RXMAXP ((volatile unsigned short *)USB_EP_NI3_RXMAXP)
+#define pUSB_EP_NI3_RXCSR ((volatile unsigned short *)USB_EP_NI3_RXCSR)
+#define pUSB_EP_NI3_RXCOUNT ((volatile unsigned short *)USB_EP_NI3_RXCOUNT)
+#define pUSB_EP_NI3_TXTYPE ((volatile unsigned short *)USB_EP_NI3_TXTYPE)
+#define pUSB_EP_NI3_TXINTERVAL ((volatile unsigned short *)USB_EP_NI3_TXINTERVAL)
+#define pUSB_EP_NI3_RXTYPE ((volatile unsigned short *)USB_EP_NI3_RXTYPE)
+#define pUSB_EP_NI3_RXINTERVAL ((volatile unsigned short *)USB_EP_NI3_RXINTERVAL)
+#define pUSB_EP_NI3_TXCOUNT ((volatile unsigned short *)USB_EP_NI3_TXCOUNT)
+
+/* USB Endpoint 4 Control Registers */
+
+#define pUSB_EP_NI4_TXMAXP ((volatile unsigned short *)USB_EP_NI4_TXMAXP)
+#define pUSB_EP_NI4_TXCSR ((volatile unsigned short *)USB_EP_NI4_TXCSR)
+#define pUSB_EP_NI4_RXMAXP ((volatile unsigned short *)USB_EP_NI4_RXMAXP)
+#define pUSB_EP_NI4_RXCSR ((volatile unsigned short *)USB_EP_NI4_RXCSR)
+#define pUSB_EP_NI4_RXCOUNT ((volatile unsigned short *)USB_EP_NI4_RXCOUNT)
+#define pUSB_EP_NI4_TXTYPE ((volatile unsigned short *)USB_EP_NI4_TXTYPE)
+#define pUSB_EP_NI4_TXINTERVAL ((volatile unsigned short *)USB_EP_NI4_TXINTERVAL)
+#define pUSB_EP_NI4_RXTYPE ((volatile unsigned short *)USB_EP_NI4_RXTYPE)
+#define pUSB_EP_NI4_RXINTERVAL ((volatile unsigned short *)USB_EP_NI4_RXINTERVAL)
+#define pUSB_EP_NI4_TXCOUNT ((volatile unsigned short *)USB_EP_NI4_TXCOUNT)
+
+/* USB Endpoint 5 Control Registers */
+
+#define pUSB_EP_NI5_TXMAXP ((volatile unsigned short *)USB_EP_NI5_TXMAXP)
+#define pUSB_EP_NI5_TXCSR ((volatile unsigned short *)USB_EP_NI5_TXCSR)
+#define pUSB_EP_NI5_RXMAXP ((volatile unsigned short *)USB_EP_NI5_RXMAXP)
+#define pUSB_EP_NI5_RXCSR ((volatile unsigned short *)USB_EP_NI5_RXCSR)
+#define pUSB_EP_NI5_RXCOUNT ((volatile unsigned short *)USB_EP_NI5_RXCOUNT)
+#define pUSB_EP_NI5_TXTYPE ((volatile unsigned short *)USB_EP_NI5_TXTYPE)
+#define pUSB_EP_NI5_TXINTERVAL ((volatile unsigned short *)USB_EP_NI5_TXINTERVAL)
+#define pUSB_EP_NI5_RXTYPE ((volatile unsigned short *)USB_EP_NI5_RXTYPE)
+#define pUSB_EP_NI5_RXINTERVAL ((volatile unsigned short *)USB_EP_NI5_RXINTERVAL)
+#define pUSB_EP_NI5_TXCOUNT ((volatile unsigned short *)USB_EP_NI5_TXCOUNT)
+
+/* USB Endpoint 6 Control Registers */
+
+#define pUSB_EP_NI6_TXMAXP ((volatile unsigned short *)USB_EP_NI6_TXMAXP)
+#define pUSB_EP_NI6_TXCSR ((volatile unsigned short *)USB_EP_NI6_TXCSR)
+#define pUSB_EP_NI6_RXMAXP ((volatile unsigned short *)USB_EP_NI6_RXMAXP)
+#define pUSB_EP_NI6_RXCSR ((volatile unsigned short *)USB_EP_NI6_RXCSR)
+#define pUSB_EP_NI6_RXCOUNT ((volatile unsigned short *)USB_EP_NI6_RXCOUNT)
+#define pUSB_EP_NI6_TXTYPE ((volatile unsigned short *)USB_EP_NI6_TXTYPE)
+#define pUSB_EP_NI6_TXINTERVAL ((volatile unsigned short *)USB_EP_NI6_TXINTERVAL)
+#define pUSB_EP_NI6_RXTYPE ((volatile unsigned short *)USB_EP_NI6_RXTYPE)
+#define pUSB_EP_NI6_RXINTERVAL ((volatile unsigned short *)USB_EP_NI6_RXINTERVAL)
+#define pUSB_EP_NI6_TXCOUNT ((volatile unsigned short *)USB_EP_NI6_TXCOUNT)
+
+/* USB Endpoint 7 Control Registers */
+
+#define pUSB_EP_NI7_TXMAXP ((volatile unsigned short *)USB_EP_NI7_TXMAXP)
+#define pUSB_EP_NI7_TXCSR ((volatile unsigned short *)USB_EP_NI7_TXCSR)
+#define pUSB_EP_NI7_RXMAXP ((volatile unsigned short *)USB_EP_NI7_RXMAXP)
+#define pUSB_EP_NI7_RXCSR ((volatile unsigned short *)USB_EP_NI7_RXCSR)
+#define pUSB_EP_NI7_RXCOUNT ((volatile unsigned short *)USB_EP_NI7_RXCOUNT)
+#define pUSB_EP_NI7_TXTYPE ((volatile unsigned short *)USB_EP_NI7_TXTYPE)
+#define pUSB_EP_NI7_TXINTERVAL ((volatile unsigned short *)USB_EP_NI7_TXINTERVAL)
+#define pUSB_EP_NI7_RXTYPE ((volatile unsigned short *)USB_EP_NI7_RXTYPE)
+#define pUSB_EP_NI7_RXINTERVAL ((volatile unsigned short *)USB_EP_NI7_RXINTERVAL)
+#define pUSB_EP_NI7_TXCOUNT ((volatile unsigned short *)USB_EP_NI7_TXCOUNT)
+
+#define pUSB_DMA_INTERRUPT ((volatile unsigned short *)USB_DMA_INTERRUPT)
+
+/* USB Channel 0 Config Registers */
+
+#define pUSB_DMA0CONTROL ((volatile unsigned short *)USB_DMA0CONTROL)
+#define pUSB_DMA0ADDRLOW ((volatile unsigned short *)USB_DMA0ADDRLOW)
+#define pUSB_DMA0ADDRHIGH ((volatile unsigned short *)USB_DMA0ADDRHIGH)
+#define pUSB_DMA0COUNTLOW ((volatile unsigned short *)USB_DMA0COUNTLOW)
+#define pUSB_DMA0COUNTHIGH ((volatile unsigned short *)USB_DMA0COUNTHIGH)
+
+/* USB Channel 1 Config Registers */
+
+#define pUSB_DMA1CONTROL ((volatile unsigned short *)USB_DMA1CONTROL)
+#define pUSB_DMA1ADDRLOW ((volatile unsigned short *)USB_DMA1ADDRLOW)
+#define pUSB_DMA1ADDRHIGH ((volatile unsigned short *)USB_DMA1ADDRHIGH)
+#define pUSB_DMA1COUNTLOW ((volatile unsigned short *)USB_DMA1COUNTLOW)
+#define pUSB_DMA1COUNTHIGH ((volatile unsigned short *)USB_DMA1COUNTHIGH)
+
+/* USB Channel 2 Config Registers */
+
+#define pUSB_DMA2CONTROL ((volatile unsigned short *)USB_DMA2CONTROL)
+#define pUSB_DMA2ADDRLOW ((volatile unsigned short *)USB_DMA2ADDRLOW)
+#define pUSB_DMA2ADDRHIGH ((volatile unsigned short *)USB_DMA2ADDRHIGH)
+#define pUSB_DMA2COUNTLOW ((volatile unsigned short *)USB_DMA2COUNTLOW)
+#define pUSB_DMA2COUNTHIGH ((volatile unsigned short *)USB_DMA2COUNTHIGH)
+
+/* USB Channel 3 Config Registers */
+
+#define pUSB_DMA3CONTROL ((volatile unsigned short *)USB_DMA3CONTROL)
+#define pUSB_DMA3ADDRLOW ((volatile unsigned short *)USB_DMA3ADDRLOW)
+#define pUSB_DMA3ADDRHIGH ((volatile unsigned short *)USB_DMA3ADDRHIGH)
+#define pUSB_DMA3COUNTLOW ((volatile unsigned short *)USB_DMA3COUNTLOW)
+#define pUSB_DMA3COUNTHIGH ((volatile unsigned short *)USB_DMA3COUNTHIGH)
+
+/* USB Channel 4 Config Registers */
+
+#define pUSB_DMA4CONTROL ((volatile unsigned short *)USB_DMA4CONTROL)
+#define pUSB_DMA4ADDRLOW ((volatile unsigned short *)USB_DMA4ADDRLOW)
+#define pUSB_DMA4ADDRHIGH ((volatile unsigned short *)USB_DMA4ADDRHIGH)
+#define pUSB_DMA4COUNTLOW ((volatile unsigned short *)USB_DMA4COUNTLOW)
+#define pUSB_DMA4COUNTHIGH ((volatile unsigned short *)USB_DMA4COUNTHIGH)
+
+/* USB Channel 5 Config Registers */
+
+#define pUSB_DMA5CONTROL ((volatile unsigned short *)USB_DMA5CONTROL)
+#define pUSB_DMA5ADDRLOW ((volatile unsigned short *)USB_DMA5ADDRLOW)
+#define pUSB_DMA5ADDRHIGH ((volatile unsigned short *)USB_DMA5ADDRHIGH)
+#define pUSB_DMA5COUNTLOW ((volatile unsigned short *)USB_DMA5COUNTLOW)
+#define pUSB_DMA5COUNTHIGH ((volatile unsigned short *)USB_DMA5COUNTHIGH)
+
+/* USB Channel 6 Config Registers */
+
+#define pUSB_DMA6CONTROL ((volatile unsigned short *)USB_DMA6CONTROL)
+#define pUSB_DMA6ADDRLOW ((volatile unsigned short *)USB_DMA6ADDRLOW)
+#define pUSB_DMA6ADDRHIGH ((volatile unsigned short *)USB_DMA6ADDRHIGH)
+#define pUSB_DMA6COUNTLOW ((volatile unsigned short *)USB_DMA6COUNTLOW)
+#define pUSB_DMA6COUNTHIGH ((volatile unsigned short *)USB_DMA6COUNTHIGH)
+
+/* USB Channel 7 Config Registers */
+
+#define pUSB_DMA7CONTROL ((volatile unsigned short *)USB_DMA7CONTROL)
+#define pUSB_DMA7ADDRLOW ((volatile unsigned short *)USB_DMA7ADDRLOW)
+#define pUSB_DMA7ADDRHIGH ((volatile unsigned short *)USB_DMA7ADDRHIGH)
+#define pUSB_DMA7COUNTLOW ((volatile unsigned short *)USB_DMA7COUNTLOW)
+#define pUSB_DMA7COUNTHIGH ((volatile unsigned short *)USB_DMA7COUNTHIGH)
+
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif /* _CDEF_BF524_H */
*/
/*
-** Copyright (C) 2008 Analog Devices, Inc.
+** Copyright (C) 2008, 2009 Analog Devices, Inc.
**
************************************************************************************
**
/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
#include <cdefBF52x_base.h>
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
+#endif /* _MISRA_RULES */
+
/* The following are the #defines needed by ADSP-BF525 that are not in the common header */
/* USB Control Registers */
#define pUSB_DMA7COUNTLOW ((volatile unsigned short *)USB_DMA7COUNTLOW)
#define pUSB_DMA7COUNTHIGH ((volatile unsigned short *)USB_DMA7COUNTHIGH)
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
#endif /* _CDEF_BF525_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** Copyright (C) 2009 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for the ADSP-BF526 peripherals.
+**
+************************************************************************************
+** System MMR Register Map
+************************************************************************************/
+
+#ifndef _CDEF_BF526_H
+#define _CDEF_BF526_H
+
+/* include all Core registers and bit definitions */
+#include <defBF526.h>
+
+/* include core specific register pointer definitions */
+#include <cdef_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF526 */
+
+/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
+#include <cdefBF52x_base.h>
+
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
+#endif /* _MISRA_RULES */
+
+/* The following are the #defines needed by ADSP-BF526 that are not in the common header */
+
+/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
+
+#define pEMAC_OPMODE ((volatile unsigned long *)EMAC_OPMODE)
+#define pEMAC_ADDRLO ((volatile unsigned long *)EMAC_ADDRLO)
+#define pEMAC_ADDRHI ((volatile unsigned long *)EMAC_ADDRHI)
+#define pEMAC_HASHLO ((volatile unsigned long *)EMAC_HASHLO)
+#define pEMAC_HASHHI ((volatile unsigned long *)EMAC_HASHHI)
+#define pEMAC_STAADD ((volatile unsigned long *)EMAC_STAADD)
+#define pEMAC_STADAT ((volatile unsigned long *)EMAC_STADAT)
+#define pEMAC_FLC ((volatile unsigned long *)EMAC_FLC)
+#define pEMAC_VLAN1 ((volatile unsigned long *)EMAC_VLAN1)
+#define pEMAC_VLAN2 ((volatile unsigned long *)EMAC_VLAN2)
+#define pEMAC_WKUP_CTL ((volatile unsigned long *)EMAC_WKUP_CTL)
+#define pEMAC_WKUP_FFMSK0 ((volatile unsigned long *)EMAC_WKUP_FFMSK0)
+#define pEMAC_WKUP_FFMSK1 ((volatile unsigned long *)EMAC_WKUP_FFMSK1)
+#define pEMAC_WKUP_FFMSK2 ((volatile unsigned long *)EMAC_WKUP_FFMSK2)
+#define pEMAC_WKUP_FFMSK3 ((volatile unsigned long *)EMAC_WKUP_FFMSK3)
+#define pEMAC_WKUP_FFCMD ((volatile unsigned long *)EMAC_WKUP_FFCMD)
+#define pEMAC_WKUP_FFOFF ((volatile unsigned long *)EMAC_WKUP_FFOFF)
+#define pEMAC_WKUP_FFCRC0 ((volatile unsigned long *)EMAC_WKUP_FFCRC0)
+#define pEMAC_WKUP_FFCRC1 ((volatile unsigned long *)EMAC_WKUP_FFCRC1)
+
+#define pEMAC_SYSCTL ((volatile unsigned long *)EMAC_SYSCTL)
+#define pEMAC_SYSTAT ((volatile unsigned long *)EMAC_SYSTAT)
+#define pEMAC_RX_STAT ((volatile unsigned long *)EMAC_RX_STAT)
+#define pEMAC_RX_STKY ((volatile unsigned long *)EMAC_RX_STKY)
+#define pEMAC_RX_IRQE ((volatile unsigned long *)EMAC_RX_IRQE)
+#define pEMAC_TX_STAT ((volatile unsigned long *)EMAC_TX_STAT)
+#define pEMAC_TX_STKY ((volatile unsigned long *)EMAC_TX_STKY)
+#define pEMAC_TX_IRQE ((volatile unsigned long *)EMAC_TX_IRQE)
+
+#define pEMAC_MMC_CTL ((volatile unsigned long *)EMAC_MMC_CTL)
+#define pEMAC_MMC_RIRQS ((volatile unsigned long *)EMAC_MMC_RIRQS)
+#define pEMAC_MMC_RIRQE ((volatile unsigned long *)EMAC_MMC_RIRQE)
+#define pEMAC_MMC_TIRQS ((volatile unsigned long *)EMAC_MMC_TIRQS)
+#define pEMAC_MMC_TIRQE ((volatile unsigned long *)EMAC_MMC_TIRQE)
+
+#define pEMAC_RXC_OK ((volatile unsigned long *)EMAC_RXC_OK)
+#define pEMAC_RXC_FCS ((volatile unsigned long *)EMAC_RXC_FCS)
+#define pEMAC_RXC_ALIGN ((volatile unsigned long *)EMAC_RXC_ALIGN)
+#define pEMAC_RXC_OCTET ((volatile unsigned long *)EMAC_RXC_OCTET)
+#define pEMAC_RXC_DMAOVF ((volatile unsigned long *)EMAC_RXC_DMAOVF)
+#define pEMAC_RXC_UNICST ((volatile unsigned long *)EMAC_RXC_UNICST)
+#define pEMAC_RXC_MULTI ((volatile unsigned long *)EMAC_RXC_MULTI)
+#define pEMAC_RXC_BROAD ((volatile unsigned long *)EMAC_RXC_BROAD)
+#define pEMAC_RXC_LNERRI ((volatile unsigned long *)EMAC_RXC_LNERRI)
+#define pEMAC_RXC_LNERRO ((volatile unsigned long *)EMAC_RXC_LNERRO)
+#define pEMAC_RXC_LONG ((volatile unsigned long *)EMAC_RXC_LONG)
+#define pEMAC_RXC_MACCTL ((volatile unsigned long *)EMAC_RXC_MACCTL)
+#define pEMAC_RXC_OPCODE ((volatile unsigned long *)EMAC_RXC_OPCODE)
+#define pEMAC_RXC_PAUSE ((volatile unsigned long *)EMAC_RXC_PAUSE)
+#define pEMAC_RXC_ALLFRM ((volatile unsigned long *)EMAC_RXC_ALLFRM)
+#define pEMAC_RXC_ALLOCT ((volatile unsigned long *)EMAC_RXC_ALLOCT)
+#define pEMAC_RXC_TYPED ((volatile unsigned long *)EMAC_RXC_TYPED)
+#define pEMAC_RXC_SHORT ((volatile unsigned long *)EMAC_RXC_SHORT)
+#define pEMAC_RXC_EQ64 ((volatile unsigned long *)EMAC_RXC_EQ64)
+#define pEMAC_RXC_LT128 ((volatile unsigned long *)EMAC_RXC_LT128)
+#define pEMAC_RXC_LT256 ((volatile unsigned long *)EMAC_RXC_LT256)
+#define pEMAC_RXC_LT512 ((volatile unsigned long *)EMAC_RXC_LT512)
+#define pEMAC_RXC_LT1024 ((volatile unsigned long *)EMAC_RXC_LT1024)
+#define pEMAC_RXC_GE1024 ((volatile unsigned long *)EMAC_RXC_GE1024)
+
+#define pEMAC_TXC_OK ((volatile unsigned long *)EMAC_TXC_OK)
+#define pEMAC_TXC_1COL ((volatile unsigned long *)EMAC_TXC_1COL)
+#define pEMAC_TXC_GT1COL ((volatile unsigned long *)EMAC_TXC_GT1COL)
+#define pEMAC_TXC_OCTET ((volatile unsigned long *)EMAC_TXC_OCTET)
+#define pEMAC_TXC_DEFER ((volatile unsigned long *)EMAC_TXC_DEFER)
+#define pEMAC_TXC_LATECL ((volatile unsigned long *)EMAC_TXC_LATECL)
+#define pEMAC_TXC_XS_COL ((volatile unsigned long *)EMAC_TXC_XS_COL)
+#define pEMAC_TXC_DMAUND ((volatile unsigned long *)EMAC_TXC_DMAUND)
+#define pEMAC_TXC_CRSERR ((volatile unsigned long *)EMAC_TXC_CRSERR)
+#define pEMAC_TXC_UNICST ((volatile unsigned long *)EMAC_TXC_UNICST)
+#define pEMAC_TXC_MULTI ((volatile unsigned long *)EMAC_TXC_MULTI)
+#define pEMAC_TXC_BROAD ((volatile unsigned long *)EMAC_TXC_BROAD)
+#define pEMAC_TXC_XS_DFR ((volatile unsigned long *)EMAC_TXC_XS_DFR)
+#define pEMAC_TXC_MACCTL ((volatile unsigned long *)EMAC_TXC_MACCTL)
+#define pEMAC_TXC_ALLFRM ((volatile unsigned long *)EMAC_TXC_ALLFRM)
+#define pEMAC_TXC_ALLOCT ((volatile unsigned long *)EMAC_TXC_ALLOCT)
+#define pEMAC_TXC_EQ64 ((volatile unsigned long *)EMAC_TXC_EQ64)
+#define pEMAC_TXC_LT128 ((volatile unsigned long *)EMAC_TXC_LT128)
+#define pEMAC_TXC_LT256 ((volatile unsigned long *)EMAC_TXC_LT256)
+#define pEMAC_TXC_LT512 ((volatile unsigned long *)EMAC_TXC_LT512)
+#define pEMAC_TXC_LT1024 ((volatile unsigned long *)EMAC_TXC_LT1024)
+#define pEMAC_TXC_GE1024 ((volatile unsigned long *)EMAC_TXC_GE1024)
+#define pEMAC_TXC_ABORT ((volatile unsigned long *)EMAC_TXC_ABORT)
+
+/* USB Control Registers */
+
+#define pUSB_FADDR ((volatile unsigned short *)USB_FADDR)
+#define pUSB_POWER ((volatile unsigned short *)USB_POWER)
+#define pUSB_INTRTX ((volatile unsigned short *)USB_INTRTX)
+#define pUSB_INTRRX ((volatile unsigned short *)USB_INTRRX)
+#define pUSB_INTRTXE ((volatile unsigned short *)USB_INTRTXE)
+#define pUSB_INTRRXE ((volatile unsigned short *)USB_INTRRXE)
+#define pUSB_INTRUSB ((volatile unsigned short *)USB_INTRUSB)
+#define pUSB_INTRUSBE ((volatile unsigned short *)USB_INTRUSBE)
+#define pUSB_FRAME ((volatile unsigned short *)USB_FRAME)
+#define pUSB_INDEX ((volatile unsigned short *)USB_INDEX)
+#define pUSB_TESTMODE ((volatile unsigned short *)USB_TESTMODE)
+#define pUSB_GLOBINTR ((volatile unsigned short *)USB_GLOBINTR)
+#define pUSB_GLOBAL_CTL ((volatile unsigned short *)USB_GLOBAL_CTL)
+
+/* USB Packet Control Registers */
+
+#define pUSB_TX_MAX_PACKET ((volatile unsigned short *)USB_TX_MAX_PACKET)
+#define pUSB_CSR0 ((volatile unsigned short *)USB_CSR0)
+#define pUSB_TXCSR ((volatile unsigned short *)USB_TXCSR)
+#define pUSB_RX_MAX_PACKET ((volatile unsigned short *)USB_RX_MAX_PACKET)
+#define pUSB_RXCSR ((volatile unsigned short *)USB_RXCSR)
+#define pUSB_COUNT0 ((volatile unsigned short *)USB_COUNT0)
+#define pUSB_RXCOUNT ((volatile unsigned short *)USB_RXCOUNT)
+#define pUSB_TXTYPE ((volatile unsigned short *)USB_TXTYPE)
+#define pUSB_NAKLIMIT0 ((volatile unsigned short *)USB_NAKLIMIT0)
+#define pUSB_TXINTERVAL ((volatile unsigned short *)USB_TXINTERVAL)
+#define pUSB_RXTYPE ((volatile unsigned short *)USB_RXTYPE)
+#define pUSB_RXINTERVAL ((volatile unsigned short *)USB_RXINTERVAL)
+#define pUSB_TXCOUNT ((volatile unsigned short *)USB_TXCOUNT)
+
+/* USB Endpoint FIFO Registers */
+
+#define pUSB_EP0_FIFO ((volatile unsigned short *)USB_EP0_FIFO)
+#define pUSB_EP1_FIFO ((volatile unsigned short *)USB_EP1_FIFO)
+#define pUSB_EP2_FIFO ((volatile unsigned short *)USB_EP2_FIFO)
+#define pUSB_EP3_FIFO ((volatile unsigned short *)USB_EP3_FIFO)
+#define pUSB_EP4_FIFO ((volatile unsigned short *)USB_EP4_FIFO)
+#define pUSB_EP5_FIFO ((volatile unsigned short *)USB_EP5_FIFO)
+#define pUSB_EP6_FIFO ((volatile unsigned short *)USB_EP6_FIFO)
+#define pUSB_EP7_FIFO ((volatile unsigned short *)USB_EP7_FIFO)
+
+/* USB OTG Control Registers */
+
+#define pUSB_OTG_DEV_CTL ((volatile unsigned short *)USB_OTG_DEV_CTL)
+#define pUSB_OTG_VBUS_IRQ ((volatile unsigned short *)USB_OTG_VBUS_IRQ)
+#define pUSB_OTG_VBUS_MASK ((volatile unsigned short *)USB_OTG_VBUS_MASK)
+
+/* USB Phy Control Registers */
+
+#define pUSB_LINKINFO ((volatile unsigned short *)USB_LINKINFO)
+#define pUSB_VPLEN ((volatile unsigned short *)USB_VPLEN)
+#define pUSB_HS_EOF1 ((volatile unsigned short *)USB_HS_EOF1)
+#define pUSB_FS_EOF1 ((volatile unsigned short *)USB_FS_EOF1)
+#define pUSB_LS_EOF1 ((volatile unsigned short *)USB_LS_EOF1)
+
+/* (APHY_CNTRL is for ADI usage only) */
+
+#define pUSB_APHY_CNTRL ((volatile unsigned short *)USB_APHY_CNTRL)
+
+/* (APHY_CALIB is for ADI usage only) */
+
+#define pUSB_APHY_CALIB ((volatile unsigned short *)USB_APHY_CALIB)
+
+#define pUSB_APHY_CNTRL2 ((volatile unsigned short *)USB_APHY_CNTRL2)
+
+/* (PHY_TEST is for ADI usage only) */
+
+#define pUSB_PHY_TEST ((volatile unsigned short *)USB_PHY_TEST)
+
+#define pUSB_PLLOSC_CTRL ((volatile unsigned short *)USB_PLLOSC_CTRL)
+#define pUSB_SRP_CLKDIV ((volatile unsigned short *)USB_SRP_CLKDIV)
+
+/* USB Endpoint 0 Control Registers */
+
+#define pUSB_EP_NI0_TXMAXP ((volatile unsigned short *)USB_EP_NI0_TXMAXP)
+#define pUSB_EP_NI0_TXCSR ((volatile unsigned short *)USB_EP_NI0_TXCSR)
+#define pUSB_EP_NI0_RXMAXP ((volatile unsigned short *)USB_EP_NI0_RXMAXP)
+#define pUSB_EP_NI0_RXCSR ((volatile unsigned short *)USB_EP_NI0_RXCSR)
+#define pUSB_EP_NI0_RXCOUNT ((volatile unsigned short *)USB_EP_NI0_RXCOUNT)
+#define pUSB_EP_NI0_TXTYPE ((volatile unsigned short *)USB_EP_NI0_TXTYPE)
+#define pUSB_EP_NI0_TXINTERVAL ((volatile unsigned short *)USB_EP_NI0_TXINTERVAL)
+#define pUSB_EP_NI0_RXTYPE ((volatile unsigned short *)USB_EP_NI0_RXTYPE)
+#define pUSB_EP_NI0_RXINTERVAL ((volatile unsigned short *)USB_EP_NI0_RXINTERVAL)
+#define pUSB_EP_NI0_TXCOUNT ((volatile unsigned short *)USB_EP_NI0_TXCOUNT)
+
+/* USB Endpoint 1 Control Registers */
+
+#define pUSB_EP_NI1_TXMAXP ((volatile unsigned short *)USB_EP_NI1_TXMAXP)
+#define pUSB_EP_NI1_TXCSR ((volatile unsigned short *)USB_EP_NI1_TXCSR)
+#define pUSB_EP_NI1_RXMAXP ((volatile unsigned short *)USB_EP_NI1_RXMAXP)
+#define pUSB_EP_NI1_RXCSR ((volatile unsigned short *)USB_EP_NI1_RXCSR)
+#define pUSB_EP_NI1_RXCOUNT ((volatile unsigned short *)USB_EP_NI1_RXCOUNT)
+#define pUSB_EP_NI1_TXTYPE ((volatile unsigned short *)USB_EP_NI1_TXTYPE)
+#define pUSB_EP_NI1_TXINTERVAL ((volatile unsigned short *)USB_EP_NI1_TXINTERVAL)
+#define pUSB_EP_NI1_RXTYPE ((volatile unsigned short *)USB_EP_NI1_RXTYPE)
+#define pUSB_EP_NI1_RXINTERVAL ((volatile unsigned short *)USB_EP_NI1_RXINTERVAL)
+#define pUSB_EP_NI1_TXCOUNT ((volatile unsigned short *)USB_EP_NI1_TXCOUNT)
+
+/* USB Endpoint 2 Control Registers */
+
+#define pUSB_EP_NI2_TXMAXP ((volatile unsigned short *)USB_EP_NI2_TXMAXP)
+#define pUSB_EP_NI2_TXCSR ((volatile unsigned short *)USB_EP_NI2_TXCSR)
+#define pUSB_EP_NI2_RXMAXP ((volatile unsigned short *)USB_EP_NI2_RXMAXP)
+#define pUSB_EP_NI2_RXCSR ((volatile unsigned short *)USB_EP_NI2_RXCSR)
+#define pUSB_EP_NI2_RXCOUNT ((volatile unsigned short *)USB_EP_NI2_RXCOUNT)
+#define pUSB_EP_NI2_TXTYPE ((volatile unsigned short *)USB_EP_NI2_TXTYPE)
+#define pUSB_EP_NI2_TXINTERVAL ((volatile unsigned short *)USB_EP_NI2_TXINTERVAL)
+#define pUSB_EP_NI2_RXTYPE ((volatile unsigned short *)USB_EP_NI2_RXTYPE)
+#define pUSB_EP_NI2_RXINTERVAL ((volatile unsigned short *)USB_EP_NI2_RXINTERVAL)
+#define pUSB_EP_NI2_TXCOUNT ((volatile unsigned short *)USB_EP_NI2_TXCOUNT)
+
+/* USB Endpoint 3 Control Registers */
+
+#define pUSB_EP_NI3_TXMAXP ((volatile unsigned short *)USB_EP_NI3_TXMAXP)
+#define pUSB_EP_NI3_TXCSR ((volatile unsigned short *)USB_EP_NI3_TXCSR)
+#define pUSB_EP_NI3_RXMAXP ((volatile unsigned short *)USB_EP_NI3_RXMAXP)
+#define pUSB_EP_NI3_RXCSR ((volatile unsigned short *)USB_EP_NI3_RXCSR)
+#define pUSB_EP_NI3_RXCOUNT ((volatile unsigned short *)USB_EP_NI3_RXCOUNT)
+#define pUSB_EP_NI3_TXTYPE ((volatile unsigned short *)USB_EP_NI3_TXTYPE)
+#define pUSB_EP_NI3_TXINTERVAL ((volatile unsigned short *)USB_EP_NI3_TXINTERVAL)
+#define pUSB_EP_NI3_RXTYPE ((volatile unsigned short *)USB_EP_NI3_RXTYPE)
+#define pUSB_EP_NI3_RXINTERVAL ((volatile unsigned short *)USB_EP_NI3_RXINTERVAL)
+#define pUSB_EP_NI3_TXCOUNT ((volatile unsigned short *)USB_EP_NI3_TXCOUNT)
+
+/* USB Endpoint 4 Control Registers */
+
+#define pUSB_EP_NI4_TXMAXP ((volatile unsigned short *)USB_EP_NI4_TXMAXP)
+#define pUSB_EP_NI4_TXCSR ((volatile unsigned short *)USB_EP_NI4_TXCSR)
+#define pUSB_EP_NI4_RXMAXP ((volatile unsigned short *)USB_EP_NI4_RXMAXP)
+#define pUSB_EP_NI4_RXCSR ((volatile unsigned short *)USB_EP_NI4_RXCSR)
+#define pUSB_EP_NI4_RXCOUNT ((volatile unsigned short *)USB_EP_NI4_RXCOUNT)
+#define pUSB_EP_NI4_TXTYPE ((volatile unsigned short *)USB_EP_NI4_TXTYPE)
+#define pUSB_EP_NI4_TXINTERVAL ((volatile unsigned short *)USB_EP_NI4_TXINTERVAL)
+#define pUSB_EP_NI4_RXTYPE ((volatile unsigned short *)USB_EP_NI4_RXTYPE)
+#define pUSB_EP_NI4_RXINTERVAL ((volatile unsigned short *)USB_EP_NI4_RXINTERVAL)
+#define pUSB_EP_NI4_TXCOUNT ((volatile unsigned short *)USB_EP_NI4_TXCOUNT)
+
+/* USB Endpoint 5 Control Registers */
+
+#define pUSB_EP_NI5_TXMAXP ((volatile unsigned short *)USB_EP_NI5_TXMAXP)
+#define pUSB_EP_NI5_TXCSR ((volatile unsigned short *)USB_EP_NI5_TXCSR)
+#define pUSB_EP_NI5_RXMAXP ((volatile unsigned short *)USB_EP_NI5_RXMAXP)
+#define pUSB_EP_NI5_RXCSR ((volatile unsigned short *)USB_EP_NI5_RXCSR)
+#define pUSB_EP_NI5_RXCOUNT ((volatile unsigned short *)USB_EP_NI5_RXCOUNT)
+#define pUSB_EP_NI5_TXTYPE ((volatile unsigned short *)USB_EP_NI5_TXTYPE)
+#define pUSB_EP_NI5_TXINTERVAL ((volatile unsigned short *)USB_EP_NI5_TXINTERVAL)
+#define pUSB_EP_NI5_RXTYPE ((volatile unsigned short *)USB_EP_NI5_RXTYPE)
+#define pUSB_EP_NI5_RXINTERVAL ((volatile unsigned short *)USB_EP_NI5_RXINTERVAL)
+#define pUSB_EP_NI5_TXCOUNT ((volatile unsigned short *)USB_EP_NI5_TXCOUNT)
+
+/* USB Endpoint 6 Control Registers */
+
+#define pUSB_EP_NI6_TXMAXP ((volatile unsigned short *)USB_EP_NI6_TXMAXP)
+#define pUSB_EP_NI6_TXCSR ((volatile unsigned short *)USB_EP_NI6_TXCSR)
+#define pUSB_EP_NI6_RXMAXP ((volatile unsigned short *)USB_EP_NI6_RXMAXP)
+#define pUSB_EP_NI6_RXCSR ((volatile unsigned short *)USB_EP_NI6_RXCSR)
+#define pUSB_EP_NI6_RXCOUNT ((volatile unsigned short *)USB_EP_NI6_RXCOUNT)
+#define pUSB_EP_NI6_TXTYPE ((volatile unsigned short *)USB_EP_NI6_TXTYPE)
+#define pUSB_EP_NI6_TXINTERVAL ((volatile unsigned short *)USB_EP_NI6_TXINTERVAL)
+#define pUSB_EP_NI6_RXTYPE ((volatile unsigned short *)USB_EP_NI6_RXTYPE)
+#define pUSB_EP_NI6_RXINTERVAL ((volatile unsigned short *)USB_EP_NI6_RXINTERVAL)
+#define pUSB_EP_NI6_TXCOUNT ((volatile unsigned short *)USB_EP_NI6_TXCOUNT)
+
+/* USB Endpoint 7 Control Registers */
+
+#define pUSB_EP_NI7_TXMAXP ((volatile unsigned short *)USB_EP_NI7_TXMAXP)
+#define pUSB_EP_NI7_TXCSR ((volatile unsigned short *)USB_EP_NI7_TXCSR)
+#define pUSB_EP_NI7_RXMAXP ((volatile unsigned short *)USB_EP_NI7_RXMAXP)
+#define pUSB_EP_NI7_RXCSR ((volatile unsigned short *)USB_EP_NI7_RXCSR)
+#define pUSB_EP_NI7_RXCOUNT ((volatile unsigned short *)USB_EP_NI7_RXCOUNT)
+#define pUSB_EP_NI7_TXTYPE ((volatile unsigned short *)USB_EP_NI7_TXTYPE)
+#define pUSB_EP_NI7_TXINTERVAL ((volatile unsigned short *)USB_EP_NI7_TXINTERVAL)
+#define pUSB_EP_NI7_RXTYPE ((volatile unsigned short *)USB_EP_NI7_RXTYPE)
+#define pUSB_EP_NI7_RXINTERVAL ((volatile unsigned short *)USB_EP_NI7_RXINTERVAL)
+#define pUSB_EP_NI7_TXCOUNT ((volatile unsigned short *)USB_EP_NI7_TXCOUNT)
+
+#define pUSB_DMA_INTERRUPT ((volatile unsigned short *)USB_DMA_INTERRUPT)
+
+/* USB Channel 0 Config Registers */
+
+#define pUSB_DMA0CONTROL ((volatile unsigned short *)USB_DMA0CONTROL)
+#define pUSB_DMA0ADDRLOW ((volatile unsigned short *)USB_DMA0ADDRLOW)
+#define pUSB_DMA0ADDRHIGH ((volatile unsigned short *)USB_DMA0ADDRHIGH)
+#define pUSB_DMA0COUNTLOW ((volatile unsigned short *)USB_DMA0COUNTLOW)
+#define pUSB_DMA0COUNTHIGH ((volatile unsigned short *)USB_DMA0COUNTHIGH)
+
+/* USB Channel 1 Config Registers */
+
+#define pUSB_DMA1CONTROL ((volatile unsigned short *)USB_DMA1CONTROL)
+#define pUSB_DMA1ADDRLOW ((volatile unsigned short *)USB_DMA1ADDRLOW)
+#define pUSB_DMA1ADDRHIGH ((volatile unsigned short *)USB_DMA1ADDRHIGH)
+#define pUSB_DMA1COUNTLOW ((volatile unsigned short *)USB_DMA1COUNTLOW)
+#define pUSB_DMA1COUNTHIGH ((volatile unsigned short *)USB_DMA1COUNTHIGH)
+
+/* USB Channel 2 Config Registers */
+
+#define pUSB_DMA2CONTROL ((volatile unsigned short *)USB_DMA2CONTROL)
+#define pUSB_DMA2ADDRLOW ((volatile unsigned short *)USB_DMA2ADDRLOW)
+#define pUSB_DMA2ADDRHIGH ((volatile unsigned short *)USB_DMA2ADDRHIGH)
+#define pUSB_DMA2COUNTLOW ((volatile unsigned short *)USB_DMA2COUNTLOW)
+#define pUSB_DMA2COUNTHIGH ((volatile unsigned short *)USB_DMA2COUNTHIGH)
+
+/* USB Channel 3 Config Registers */
+
+#define pUSB_DMA3CONTROL ((volatile unsigned short *)USB_DMA3CONTROL)
+#define pUSB_DMA3ADDRLOW ((volatile unsigned short *)USB_DMA3ADDRLOW)
+#define pUSB_DMA3ADDRHIGH ((volatile unsigned short *)USB_DMA3ADDRHIGH)
+#define pUSB_DMA3COUNTLOW ((volatile unsigned short *)USB_DMA3COUNTLOW)
+#define pUSB_DMA3COUNTHIGH ((volatile unsigned short *)USB_DMA3COUNTHIGH)
+
+/* USB Channel 4 Config Registers */
+
+#define pUSB_DMA4CONTROL ((volatile unsigned short *)USB_DMA4CONTROL)
+#define pUSB_DMA4ADDRLOW ((volatile unsigned short *)USB_DMA4ADDRLOW)
+#define pUSB_DMA4ADDRHIGH ((volatile unsigned short *)USB_DMA4ADDRHIGH)
+#define pUSB_DMA4COUNTLOW ((volatile unsigned short *)USB_DMA4COUNTLOW)
+#define pUSB_DMA4COUNTHIGH ((volatile unsigned short *)USB_DMA4COUNTHIGH)
+
+/* USB Channel 5 Config Registers */
+
+#define pUSB_DMA5CONTROL ((volatile unsigned short *)USB_DMA5CONTROL)
+#define pUSB_DMA5ADDRLOW ((volatile unsigned short *)USB_DMA5ADDRLOW)
+#define pUSB_DMA5ADDRHIGH ((volatile unsigned short *)USB_DMA5ADDRHIGH)
+#define pUSB_DMA5COUNTLOW ((volatile unsigned short *)USB_DMA5COUNTLOW)
+#define pUSB_DMA5COUNTHIGH ((volatile unsigned short *)USB_DMA5COUNTHIGH)
+
+/* USB Channel 6 Config Registers */
+
+#define pUSB_DMA6CONTROL ((volatile unsigned short *)USB_DMA6CONTROL)
+#define pUSB_DMA6ADDRLOW ((volatile unsigned short *)USB_DMA6ADDRLOW)
+#define pUSB_DMA6ADDRHIGH ((volatile unsigned short *)USB_DMA6ADDRHIGH)
+#define pUSB_DMA6COUNTLOW ((volatile unsigned short *)USB_DMA6COUNTLOW)
+#define pUSB_DMA6COUNTHIGH ((volatile unsigned short *)USB_DMA6COUNTHIGH)
+
+/* USB Channel 7 Config Registers */
+
+#define pUSB_DMA7CONTROL ((volatile unsigned short *)USB_DMA7CONTROL)
+#define pUSB_DMA7ADDRLOW ((volatile unsigned short *)USB_DMA7ADDRLOW)
+#define pUSB_DMA7ADDRHIGH ((volatile unsigned short *)USB_DMA7ADDRHIGH)
+#define pUSB_DMA7COUNTLOW ((volatile unsigned short *)USB_DMA7COUNTLOW)
+#define pUSB_DMA7COUNTHIGH ((volatile unsigned short *)USB_DMA7COUNTHIGH)
+
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif /* _CDEF_BF526_H */
*/
/*
-** Copyright (C) 2008 Analog Devices, Inc.
+** Copyright (C) 2008, 2009 Analog Devices, Inc.
**
************************************************************************************
**
/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
#include <cdefBF52x_base.h>
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
+#endif /* _MISRA_RULES */
+
/* The following are the #defines needed by ADSP-BF527 that are not in the common header */
/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
#define pUSB_DMA7COUNTLOW ((volatile unsigned short *)USB_DMA7COUNTLOW)
#define pUSB_DMA7COUNTHIGH ((volatile unsigned short *)USB_DMA7COUNTHIGH)
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
#endif /* _CDEF_BF527_H */
/*
** cdefBF52x_base.h
**
-** Copyright (C) 2008 Analog Devices, Inc.
+** Copyright (C) 2008, 2009 Analog Devices, Inc.
**
************************************************************************************
**
#include <defBF52x_base.h>
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
+#endif /* _MISRA_RULES */
+
/* ==== begin from cdefBF534.h ==== */
#ifndef _PTR_TO_VOL_VOID_PTR
#define pSWRST ((volatile unsigned short *)SWRST)
#define pSYSCR ((volatile unsigned short *)SYSCR)
-#define pSIC_RVECT (_PTR_TO_VOL_VOID_PTR SIC_RVECT)
#define pSIC_IMASK0 ((volatile unsigned long *)SIC_IMASK0)
/* legacy register name (below) provided for backwards code compatibility */
#define pSIC_IMASK ((volatile unsigned long *)SIC_IMASK0)
#define pPORTF_DRIVE ((volatile unsigned short *)PORTF_DRIVE)
#define pPORTG_DRIVE ((volatile unsigned short *)PORTG_DRIVE)
#define pPORTH_DRIVE ((volatile unsigned short *)PORTH_DRIVE)
-#define pPORTF_SLEW ((volatile unsigned short *)PORTF_SLEW)
-#define pPORTG_SLEW ((volatile unsigned short *)PORTG_SLEW)
-#define pPORTH_SLEW ((volatile unsigned short *)PORTH_SLEW)
#define pPORTF_HYSTERESIS ((volatile unsigned short *)PORTF_HYSTERESIS)
#define pPORTG_HYSTERESIS ((volatile unsigned short *)PORTG_HYSTERESIS)
#define pPORTH_HYSTERESIS ((volatile unsigned short *)PORTH_HYSTERESIS)
#define pNONGPIO_DRIVE ((volatile unsigned short *)NONGPIO_DRIVE)
-#define pNONGPIO_SLEW ((volatile unsigned short *)NONGPIO_SLEW)
#define pNONGPIO_HYSTERESIS ((volatile unsigned short *)NONGPIO_HYSTERESIS)
/* HOST Port Registers */
#define pCNT_MAX ((volatile unsigned long *)CNT_MAX)
#define pCNT_MIN ((volatile unsigned long *)CNT_MIN)
-/* OTP/FUSE Registers */
-
-#define pOTP_CONTROL ((volatile unsigned short *)OTP_CONTROL)
-#define pOTP_BEN ((volatile unsigned short *)OTP_BEN)
-#define pOTP_STATUS ((volatile unsigned short *)OTP_STATUS)
-#define pOTP_TIMING ((volatile unsigned long *)OTP_TIMING)
-
/* Security Registers */
#define pSECURE_SYSSWT ((volatile unsigned long *)SECURE_SYSSWT)
#define pNFC_DATA_WR ((volatile unsigned short *)NFC_DATA_WR)
#define pNFC_DATA_RD ((volatile unsigned short *)NFC_DATA_RD)
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
#endif /* _CDEF_BF52X_H */
*
* cdefBF532.h
*
- * Copyright (C) 2008 Analog Devices, Inc.
+ * Copyright (C) 2008, 2009 Analog Devices, Inc.
*
************************************************************************/
/* System Interrupt Controller */
#define pSWRST ((volatile unsigned short *)SWRST)
#define pSYSCR ((volatile unsigned short *)SYSCR)
-#define pSIC_RVECT ((void * volatile *)SIC_RVECT)
#define pSIC_IMASK ((volatile unsigned long *)SIC_IMASK)
#define pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0)
#define pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1)
*/
/*
-** Copyright (C) 2008 Analog Devices, Inc.
+** Copyright (C) 2008, 2009 Analog Devices, Inc.
**
************************************************************************************
**
#ifndef _CDEF_BF534_H
#define _CDEF_BF534_H
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_7:"ADI header allows function macros")
+#endif /* _MISRA_RULES */
+
/* Include all Core registers and bit definitions */
#include <defBF534.h>
/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
#define pSWRST ((volatile unsigned short *)SWRST)
#define pSYSCR ((volatile unsigned short *)SYSCR)
-#define pSIC_RVECT (_PTR_TO_VOL_VOID_PTR SIC_RVECT)
#define pSIC_IMASK ((volatile unsigned long *)SIC_IMASK)
#define pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0)
#define pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1)
#define pCAN_MBTD ((volatile unsigned short *)CAN_MBTD)
#define pCAN_EWR ((volatile unsigned short *)CAN_EWR)
#define pCAN_ESR ((volatile unsigned short *)CAN_ESR)
-#define pCAN_UCREG ((volatile unsigned short *)CAN_UCREG)
#define pCAN_UCCNT ((volatile unsigned short *)CAN_UCCNT)
#define pCAN_UCRC ((volatile unsigned short *)CAN_UCRC)
#define pCAN_UCCNF ((volatile unsigned short *)CAN_UCCNF)
#define pHMDMA1_ECOUNT ((volatile unsigned short *)HMDMA1_ECOUNT)
#define pHMDMA1_BCOUNT ((volatile unsigned short *)HMDMA1_BCOUNT)
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
#endif /* _CDEF_BF534_H */
*
* cdefBF535.h
*
- * Copyright (C) 2008 Analog Devices, Inc.
+ * Copyright (C) 2008, 2009 Analog Devices, Inc.
*
************************************************************************/
/* include core specific register pointer definitions */
#include <cdefblackfin.h>
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
+#endif /* _MISRA_RULES */
+
#ifndef _PTR_TO_VOL_VOID_PTR
#ifndef _USE_LEGACY_CDEF_BEHAVIOUR
#define _PTR_TO_VOL_VOID_PTR (void * volatile *)
#define pDB_ACOMP (_PTR_TO_VOL_VOID_PTR DB_ACOMP)
#define pDB_CCOMP ((volatile unsigned long *)DB_CCOMP)
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
#endif /* _CDEF_BF535_H */
*
* cdefBF538.h
*
- * Copyright (C) 2008 Analog Devices, Inc.
+ * Copyright (C) 2008, 2009 Analog Devices, Inc.
*
************************************************************************/
/* include common system register pointer definitions from ADSP-BF532 */
#include <cdefBF532.h>
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
+#pragma diag(suppress:misra_rule_19_7:"ADI header allows function macros")
+#endif /* _MISRA_RULES */
/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
/* ADSP-BF538 SIC0 is same as SIC on ADSP-BF532 */
#define pCAN_MBTD ((volatile unsigned short *)CAN_MBTD)
#define pCAN_EWR ((volatile unsigned short *)CAN_EWR)
#define pCAN_ESR ((volatile unsigned short *)CAN_ESR)
-#define pCAN_UCREG ((volatile unsigned short *)CAN_UCREG)
#define pCAN_UCCNT ((volatile unsigned short *)CAN_UCCNT)
#define pCAN_UCRC ((volatile unsigned short *)CAN_UCRC)
#define pCAN_UCCNF ((volatile unsigned short *)CAN_UCCNF)
#define pTWI1_INT_SRC pTWI1_INT_STAT
#define pTWI1_INT_ENABLE pTWI1_INT_MASK
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
#endif /* _CDEF_BF538_H */
*/
/*
-** Copyright (C) 2008 Analog Devices, Inc.
+** Copyright (C) 2008, 2009 Analog Devices, Inc.
**
************************************************************************************
**
/* include built-in mneumonic macros */
#include <ccblkfn.h>
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
+#pragma diag(suppress:misra_rule_19_7:"ADI header allows function macros")
+#endif /* _MISRA_RULES */
+
#ifndef _PTR_TO_VOL_VOID_PTR
#ifndef _USE_LEGACY_CDEF_BEHAVIOUR
#define _PTR_TO_VOL_VOID_PTR (void * volatile *)
/* System Interrupt Controllers */
#define pSWRST ((volatile unsigned short *)SWRST)
#define pSYSCR ((volatile unsigned short *)SYSCR)
-#define pSIC_RVECT ((void * volatile *)SIC_RVECT)
#define pSIC_IMASK0 ((volatile unsigned long *)SIC_IMASK0)
#define pSIC_IMASK1 ((volatile unsigned long *)SIC_IMASK1)
#define pCAN_MBTD ((volatile unsigned short *)CAN_MBTD)
#define pCAN_EWR ((volatile unsigned short *)CAN_EWR)
#define pCAN_ESR ((volatile unsigned short *)CAN_ESR)
-#define pCAN_UCREG ((volatile unsigned short *)CAN_UCREG)
#define pCAN_UCCNT ((volatile unsigned short *)CAN_UCCNT)
#define pCAN_UCRC ((volatile unsigned short *)CAN_UCRC)
#define pCAN_UCCNF ((volatile unsigned short *)CAN_UCCNF)
#define pTWI1_INT_SRC pTWI1_INT_STAT
#define pTWI1_INT_ENABLE pTWI1_INT_MASK
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
#endif /* _CDEF_BF539_H */
/*
** cdefBF542.h
**
-** Copyright (C) 2008 Analog Devices, Inc.
+** Copyright (C) 2008, 2009 Analog Devices, Inc.
**
************************************************************************************
**
/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
#include <cdefBF54x_base.h>
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
+#endif /* _MISRA_RULES */
+
/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
/* ATAPI Registers */
#define pKPAD_STAT ((volatile unsigned short *)KPAD_STAT)
#define pKPAD_SOFTEVAL ((volatile unsigned short *)KPAD_SOFTEVAL)
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
#endif /* _CDEF_BF542_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** cdefBF542M.h
+**
+** Copyright (C) 2009 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This file just maps to the cdef for BF542 unless anything
+** is required to change.
+**
+************************************************************************************/
+
+#include <cdefBF542.h>
/*
** cdefBF544.h
**
-** Copyright (C) 2008 Analog Devices, Inc.
+** Copyright (C) 2008, 2009 Analog Devices, Inc.
**
************************************************************************************
**
/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
#include <cdefBF54x_base.h>
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
+#endif /* _MISRA_RULES */
+
/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
/* Timer Registers */
#define pPIXC_CCBIAS ((volatile unsigned long *)PIXC_CCBIAS)
#define pPIXC_TC ((volatile unsigned long *)PIXC_TC)
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
#endif /* _CDEF_BF544_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** cdefBF544M.h
+**
+** Copyright (C) 2009 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This file just maps to the cdef for BF544 unless anything
+** is required to change.
+**
+************************************************************************************/
+
+#include <cdefBF544.h>
/*
** cdefBF547.h
**
-** Copyright (C) 2008 Analog Devices, Inc.
+** Copyright (C) 2008, 2009 Analog Devices, Inc.
**
************************************************************************************
**
/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
#include <cdefBF54x_base.h>
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
+#endif /* _MISRA_RULES */
+
/* The following are the #defines needed by ADSP-BF547 that are not in the common header */
/* Timer Registers */
#define pPIXC_CCBIAS ((volatile unsigned long *)PIXC_CCBIAS)
#define pPIXC_TC ((volatile unsigned long *)PIXC_TC)
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
#endif /* _CDEF_BF547_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** cdefBF547M.h
+**
+** Copyright (C) 2009 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This file just maps to the cdef for BF547 unless anything
+** is required to change.
+**
+************************************************************************************/
+
+#include <cdefBF547.h>
/*
** cdefBF548.h
**
-** Copyright (C) 2008 Analog Devices, Inc.
+** Copyright (C) 2008, 2009 Analog Devices, Inc.
**
************************************************************************************
**
/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
#include <cdefBF54x_base.h>
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
+#endif /* _MISRA_RULES */
+
/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
/* Timer Registers */
#define pPIXC_CCBIAS ((volatile unsigned long *)PIXC_CCBIAS)
#define pPIXC_TC ((volatile unsigned long *)PIXC_TC)
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
#endif /* _CDEF_BF548_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** cdefBF548M.h
+**
+** Copyright (C) 2009 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This file just maps to the cdef for BF548 unless anything
+** is required to change.
+**
+************************************************************************************/
+
+#include <cdefBF548.h>
/*
** cdefBF549.h
**
-** Copyright (C) 2008 Analog Devices, Inc.
+** Copyright (C) 2008, 2009 Analog Devices, Inc.
**
************************************************************************************
**
/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
#include <cdefBF54x_base.h>
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
+#endif /* _MISRA_RULES */
+
/* The following are the #defines needed by ADSP-BF549 that are not in the common header */
/* Timer Registers */
#define pPIXC_CCBIAS ((volatile unsigned long *)PIXC_CCBIAS)
#define pPIXC_TC ((volatile unsigned long *)PIXC_TC)
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
#endif /* _CDEF_BF549_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** cdefBF549M.h
+**
+** Copyright (C) 2009 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This file just maps to the cdef for BF549 unless anything
+** is required to change.
+**
+************************************************************************************/
+
+#include <cdefBF549.h>
/*
** cdefBF54x_base.h
**
-** Copyright (C) 2008 Analog Devices, Inc.
+** Copyright (C) 2008, 2009 Analog Devices, Inc.
**
************************************************************************************
**
#include <defBF54x_base.h>
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
+#endif /* _MISRA_RULES */
+
/* ************************************************************** */
/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
/* ************************************************************** */
#define pCNT_MAX ((volatile unsigned long *)CNT_MAX)
#define pCNT_MIN ((volatile unsigned long *)CNT_MIN)
-/* OTP/FUSE Registers */
-
-#define pOTP_CONTROL ((volatile unsigned short *)OTP_CONTROL)
-#define pOTP_BEN ((volatile unsigned short *)OTP_BEN)
-#define pOTP_STATUS ((volatile unsigned short *)OTP_STATUS)
-#define pOTP_TIMING ((volatile unsigned long *)OTP_TIMING)
-
/* Security Registers */
#define pSECURE_SYSSWT ((volatile unsigned long *)SECURE_SYSSWT)
#define pPINT2_IRQ pPINT2_REQUEST
#define pPINT3_IRQ pPINT3_REQUEST
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
#endif /* _CDEF_BF54X_H */
*
* cdefBF561.h
*
- * Copyright (C) 2008 Analog Devices, Inc.
+ * Copyright (C) 2008, 2009 Analog Devices, Inc.
*
************************************************************************/
#include <defBF561.h>
#include <cdef_LPBlackfin.h>
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
+#endif /* _MISRA_RULES */
+
/*********************************************************************************** */
/* System MMR Register Map */
/*********************************************************************************** */
/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define pPLL_CTL (volatile unsigned short *)PLL_CTL
-#define pPLL_DIV (volatile unsigned short *)PLL_DIV
-#define pVR_CTL (volatile unsigned short *)VR_CTL
-#define pPLL_STAT (volatile unsigned short *)PLL_STAT
-#define pPLL_LOCKCNT (volatile unsigned short *)PLL_LOCKCNT
+#define pPLL_CTL ((volatile unsigned short *)PLL_CTL)
+#define pPLL_DIV ((volatile unsigned short *)PLL_DIV)
+#define pVR_CTL ((volatile unsigned short *)VR_CTL)
+#define pPLL_STAT ((volatile unsigned short *)PLL_STAT)
+#define pPLL_LOCKCNT ((volatile unsigned short *)PLL_LOCKCNT)
#define pCHIPID ((volatile unsigned long*)CHIPID)
/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
-#define pSICA_SWRST (volatile unsigned short *)SICA_SWRST
-#define pSICA_SYSCR (volatile unsigned short *)SICA_SYSCR
-#define pSICA_RVECT (volatile unsigned short *)SICA_RVECT
-#define pSICA_IMASK (volatile unsigned long *)SICA_IMASK
-#define pSICA_IMASK0 (volatile unsigned long *)SICA_IMASK0
-#define pSICA_IMASK1 (volatile unsigned long *)SICA_IMASK1
-#define pSICA_IAR0 (volatile unsigned long *)SICA_IAR0
-#define pSICA_IAR1 (volatile unsigned long *)SICA_IAR1
-#define pSICA_IAR2 (volatile unsigned long *)SICA_IAR2
-#define pSICA_IAR3 (volatile unsigned long *)SICA_IAR3
-#define pSICA_IAR4 (volatile unsigned long *)SICA_IAR4
-#define pSICA_IAR5 (volatile unsigned long *)SICA_IAR5
-#define pSICA_IAR6 (volatile unsigned long *)SICA_IAR6
-#define pSICA_IAR7 (volatile unsigned long *)SICA_IAR7
-#define pSICA_ISR0 (volatile unsigned long *)SICA_ISR0
-#define pSICA_ISR1 (volatile unsigned long *)SICA_ISR1
-#define pSICA_IWR0 (volatile unsigned long *)SICA_IWR0
-#define pSICA_IWR1 (volatile unsigned long *)SICA_IWR1
+#define pSICA_SWRST ((volatile unsigned short *)SICA_SWRST)
+#define pSICA_SYSCR ((volatile unsigned short *)SICA_SYSCR)
+#define pSICA_RVECT ((volatile unsigned short *)SICA_RVECT)
+#define pSICA_IMASK ((volatile unsigned long *)SICA_IMASK)
+#define pSICA_IMASK0 ((volatile unsigned long *)SICA_IMASK0)
+#define pSICA_IMASK1 ((volatile unsigned long *)SICA_IMASK1)
+#define pSICA_IAR0 ((volatile unsigned long *)SICA_IAR0)
+#define pSICA_IAR1 ((volatile unsigned long *)SICA_IAR1)
+#define pSICA_IAR2 ((volatile unsigned long *)SICA_IAR2)
+#define pSICA_IAR3 ((volatile unsigned long *)SICA_IAR3)
+#define pSICA_IAR4 ((volatile unsigned long *)SICA_IAR4)
+#define pSICA_IAR5 ((volatile unsigned long *)SICA_IAR5)
+#define pSICA_IAR6 ((volatile unsigned long *)SICA_IAR6)
+#define pSICA_IAR7 ((volatile unsigned long *)SICA_IAR7)
+#define pSICA_ISR0 ((volatile unsigned long *)SICA_ISR0)
+#define pSICA_ISR1 ((volatile unsigned long *)SICA_ISR1)
+#define pSICA_IWR0 ((volatile unsigned long *)SICA_IWR0)
+#define pSICA_IWR1 ((volatile unsigned long *)SICA_IWR1)
/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
-#define pSICB_SWRST (volatile unsigned short *)SICB_SWRST
-#define pSICB_SYSCR (volatile unsigned short *)SICB_SYSCR
-#define pSICB_RVECT (volatile unsigned short *)SICB_RVECT
-#define pSICB_IMASK0 (volatile unsigned long *)SICB_IMASK0
-#define pSICB_IMASK1 (volatile unsigned long *)SICB_IMASK1
-#define pSICB_IAR0 (volatile unsigned long *)SICB_IAR0
-#define pSICB_IAR1 (volatile unsigned long *)SICB_IAR1
-#define pSICB_IAR2 (volatile unsigned long *)SICB_IAR2
-#define pSICB_IAR3 (volatile unsigned long *)SICB_IAR3
-#define pSICB_IAR4 (volatile unsigned long *)SICB_IAR4
-#define pSICB_IAR5 (volatile unsigned long *)SICB_IAR5
-#define pSICB_IAR6 (volatile unsigned long *)SICB_IAR6
-#define pSICB_IAR7 (volatile unsigned long *)SICB_IAR7
-#define pSICB_ISR0 (volatile unsigned long *)SICB_ISR0
-#define pSICB_ISR1 (volatile unsigned long *)SICB_ISR1
-#define pSICB_IWR0 (volatile unsigned long *)SICB_IWR0
-#define pSICB_IWR1 (volatile unsigned long *)SICB_IWR1
+#define pSICB_SWRST ((volatile unsigned short *)SICB_SWRST)
+#define pSICB_SYSCR ((volatile unsigned short *)SICB_SYSCR)
+#define pSICB_RVECT ((volatile unsigned short *)SICB_RVECT)
+#define pSICB_IMASK0 ((volatile unsigned long *)SICB_IMASK0)
+#define pSICB_IMASK1 ((volatile unsigned long *)SICB_IMASK1)
+#define pSICB_IAR0 ((volatile unsigned long *)SICB_IAR0)
+#define pSICB_IAR1 ((volatile unsigned long *)SICB_IAR1)
+#define pSICB_IAR2 ((volatile unsigned long *)SICB_IAR2)
+#define pSICB_IAR3 ((volatile unsigned long *)SICB_IAR3)
+#define pSICB_IAR4 ((volatile unsigned long *)SICB_IAR4)
+#define pSICB_IAR5 ((volatile unsigned long *)SICB_IAR5)
+#define pSICB_IAR6 ((volatile unsigned long *)SICB_IAR6)
+#define pSICB_IAR7 ((volatile unsigned long *)SICB_IAR7)
+#define pSICB_ISR0 ((volatile unsigned long *)SICB_ISR0)
+#define pSICB_ISR1 ((volatile unsigned long *)SICB_ISR1)
+#define pSICB_IWR0 ((volatile unsigned long *)SICB_IWR0)
+#define pSICB_IWR1 ((volatile unsigned long *)SICB_IWR1)
/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
-#define pWDOGA_CTL (volatile unsigned short *)WDOGA_CTL
-#define pWDOGA_CNT (volatile unsigned long *)WDOGA_CNT
-#define pWDOGA_STAT (volatile unsigned long *)WDOGA_STAT
+#define pWDOGA_CTL ((volatile unsigned short *)WDOGA_CTL)
+#define pWDOGA_CNT ((volatile unsigned long *)WDOGA_CNT)
+#define pWDOGA_STAT ((volatile unsigned long *)WDOGA_STAT)
/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
-#define pWDOGB_CTL (volatile unsigned short *)WDOGB_CTL
-#define pWDOGB_CNT (volatile unsigned long *)WDOGB_CNT
-#define pWDOGB_STAT (volatile unsigned long *)WDOGB_STAT
+#define pWDOGB_CTL ((volatile unsigned short *)WDOGB_CTL)
+#define pWDOGB_CNT ((volatile unsigned long *)WDOGB_CNT)
+#define pWDOGB_STAT ((volatile unsigned long *)WDOGB_STAT)
/* UART Controller (0xFFC00400 - 0xFFC004FF) */
-#define pUART_THR (volatile unsigned short *)UART_THR
-#define pUART_RBR (volatile unsigned short *)UART_RBR
-#define pUART_DLL (volatile unsigned short *)UART_DLL
-#define pUART_IER (volatile unsigned short *)UART_IER
-#define pUART_DLH (volatile unsigned short *)UART_DLH
-#define pUART_IIR (volatile unsigned short *)UART_IIR
-#define pUART_LCR (volatile unsigned short *)UART_LCR
-#define pUART_MCR (volatile unsigned short *)UART_MCR
-#define pUART_LSR (volatile unsigned short *)UART_LSR
-#define pUART_MSR (volatile unsigned short *)UART_MSR
-#define pUART_SCR (volatile unsigned short *)UART_SCR
-#define pUART_GCTL (volatile unsigned short *)UART_GCTL
+#define pUART_THR ((volatile unsigned short *)UART_THR)
+#define pUART_RBR ((volatile unsigned short *)UART_RBR)
+#define pUART_DLL ((volatile unsigned short *)UART_DLL)
+#define pUART_IER ((volatile unsigned short *)UART_IER)
+#define pUART_DLH ((volatile unsigned short *)UART_DLH)
+#define pUART_IIR ((volatile unsigned short *)UART_IIR)
+#define pUART_LCR ((volatile unsigned short *)UART_LCR)
+#define pUART_MCR ((volatile unsigned short *)UART_MCR)
+#define pUART_LSR ((volatile unsigned short *)UART_LSR)
+#define pUART_MSR ((volatile unsigned short *)UART_MSR)
+#define pUART_SCR ((volatile unsigned short *)UART_SCR)
+#define pUART_GCTL ((volatile unsigned short *)UART_GCTL)
/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define pSPI_CTL (volatile unsigned short *)SPI_CTL
-#define pSPI_FLG (volatile unsigned short *)SPI_FLG
-#define pSPI_STAT (volatile unsigned short *)SPI_STAT
-#define pSPI_TDBR (volatile unsigned short *)SPI_TDBR
-#define pSPI_RDBR (volatile unsigned short *)SPI_RDBR
-#define pSPI_BAUD (volatile unsigned short *)SPI_BAUD
-#define pSPI_SHADOW (volatile unsigned short *)SPI_SHADOW
+#define pSPI_CTL ((volatile unsigned short *)SPI_CTL)
+#define pSPI_FLG ((volatile unsigned short *)SPI_FLG)
+#define pSPI_STAT ((volatile unsigned short *)SPI_STAT)
+#define pSPI_TDBR ((volatile unsigned short *)SPI_TDBR)
+#define pSPI_RDBR ((volatile unsigned short *)SPI_RDBR)
+#define pSPI_BAUD ((volatile unsigned short *)SPI_BAUD)
+#define pSPI_SHADOW ((volatile unsigned short *)SPI_SHADOW)
/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
-#define pTIMER0_CONFIG (volatile unsigned short *)TIMER0_CONFIG
-#define pTIMER0_COUNTER (volatile unsigned long *)TIMER0_COUNTER
-#define pTIMER0_PERIOD (volatile unsigned long *)TIMER0_PERIOD
-#define pTIMER0_WIDTH (volatile unsigned long *)TIMER0_WIDTH
-#define pTIMER1_CONFIG (volatile unsigned short *)TIMER1_CONFIG
-#define pTIMER1_COUNTER (volatile unsigned long *)TIMER1_COUNTER
-#define pTIMER1_PERIOD (volatile unsigned long *)TIMER1_PERIOD
-#define pTIMER1_WIDTH (volatile unsigned long *)TIMER1_WIDTH
-#define pTIMER2_CONFIG (volatile unsigned short *)TIMER2_CONFIG
-#define pTIMER2_COUNTER (volatile unsigned long *)TIMER2_COUNTER
-#define pTIMER2_PERIOD (volatile unsigned long *)TIMER2_PERIOD
-#define pTIMER2_WIDTH (volatile unsigned long *)TIMER2_WIDTH
-#define pTIMER3_CONFIG (volatile unsigned short *)TIMER3_CONFIG
-#define pTIMER3_COUNTER (volatile unsigned long *)TIMER3_COUNTER
-#define pTIMER3_PERIOD (volatile unsigned long *)TIMER3_PERIOD
-#define pTIMER3_WIDTH (volatile unsigned long *)TIMER3_WIDTH
-#define pTIMER4_CONFIG (volatile unsigned short *)TIMER4_CONFIG
-#define pTIMER4_COUNTER (volatile unsigned long *)TIMER4_COUNTER
-#define pTIMER4_PERIOD (volatile unsigned long *)TIMER4_PERIOD
-#define pTIMER4_WIDTH (volatile unsigned long *)TIMER4_WIDTH
-#define pTIMER5_CONFIG (volatile unsigned short *)TIMER5_CONFIG
-#define pTIMER5_COUNTER (volatile unsigned long *)TIMER5_COUNTER
-#define pTIMER5_PERIOD (volatile unsigned long *)TIMER5_PERIOD
-#define pTIMER5_WIDTH (volatile unsigned long *)TIMER5_WIDTH
-#define pTIMER6_CONFIG (volatile unsigned short *)TIMER6_CONFIG
-#define pTIMER6_COUNTER (volatile unsigned long *)TIMER6_COUNTER
-#define pTIMER6_PERIOD (volatile unsigned long *)TIMER6_PERIOD
-#define pTIMER6_WIDTH (volatile unsigned long *)TIMER6_WIDTH
-#define pTIMER7_CONFIG (volatile unsigned short *)TIMER7_CONFIG
-#define pTIMER7_COUNTER (volatile unsigned long *)TIMER7_COUNTER
-#define pTIMER7_PERIOD (volatile unsigned long *)TIMER7_PERIOD
-#define pTIMER7_WIDTH (volatile unsigned long *)TIMER7_WIDTH
+#define pTIMER0_CONFIG ((volatile unsigned short *)TIMER0_CONFIG)
+#define pTIMER0_COUNTER ((volatile unsigned long *)TIMER0_COUNTER)
+#define pTIMER0_PERIOD ((volatile unsigned long *)TIMER0_PERIOD)
+#define pTIMER0_WIDTH ((volatile unsigned long *)TIMER0_WIDTH)
+#define pTIMER1_CONFIG ((volatile unsigned short *)TIMER1_CONFIG)
+#define pTIMER1_COUNTER ((volatile unsigned long *)TIMER1_COUNTER)
+#define pTIMER1_PERIOD ((volatile unsigned long *)TIMER1_PERIOD)
+#define pTIMER1_WIDTH ((volatile unsigned long *)TIMER1_WIDTH)
+#define pTIMER2_CONFIG ((volatile unsigned short *)TIMER2_CONFIG)
+#define pTIMER2_COUNTER ((volatile unsigned long *)TIMER2_COUNTER)
+#define pTIMER2_PERIOD ((volatile unsigned long *)TIMER2_PERIOD)
+#define pTIMER2_WIDTH ((volatile unsigned long *)TIMER2_WIDTH)
+#define pTIMER3_CONFIG ((volatile unsigned short *)TIMER3_CONFIG)
+#define pTIMER3_COUNTER ((volatile unsigned long *)TIMER3_COUNTER)
+#define pTIMER3_PERIOD ((volatile unsigned long *)TIMER3_PERIOD)
+#define pTIMER3_WIDTH ((volatile unsigned long *)TIMER3_WIDTH)
+#define pTIMER4_CONFIG ((volatile unsigned short *)TIMER4_CONFIG)
+#define pTIMER4_COUNTER ((volatile unsigned long *)TIMER4_COUNTER)
+#define pTIMER4_PERIOD ((volatile unsigned long *)TIMER4_PERIOD)
+#define pTIMER4_WIDTH ((volatile unsigned long *)TIMER4_WIDTH)
+#define pTIMER5_CONFIG ((volatile unsigned short *)TIMER5_CONFIG)
+#define pTIMER5_COUNTER ((volatile unsigned long *)TIMER5_COUNTER)
+#define pTIMER5_PERIOD ((volatile unsigned long *)TIMER5_PERIOD)
+#define pTIMER5_WIDTH ((volatile unsigned long *)TIMER5_WIDTH)
+#define pTIMER6_CONFIG ((volatile unsigned short *)TIMER6_CONFIG)
+#define pTIMER6_COUNTER ((volatile unsigned long *)TIMER6_COUNTER)
+#define pTIMER6_PERIOD ((volatile unsigned long *)TIMER6_PERIOD)
+#define pTIMER6_WIDTH ((volatile unsigned long *)TIMER6_WIDTH)
+#define pTIMER7_CONFIG ((volatile unsigned short *)TIMER7_CONFIG)
+#define pTIMER7_COUNTER ((volatile unsigned long *)TIMER7_COUNTER)
+#define pTIMER7_PERIOD ((volatile unsigned long *)TIMER7_PERIOD)
+#define pTIMER7_WIDTH ((volatile unsigned long *)TIMER7_WIDTH)
/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
-#define pTMRS8_ENABLE (volatile unsigned short *)TMRS8_ENABLE
-#define pTMRS8_DISABLE (volatile unsigned short *)TMRS8_DISABLE
-#define pTMRS8_STATUS (volatile unsigned long *)TMRS8_STATUS
-#define pTIMER8_CONFIG (volatile unsigned short *)TIMER8_CONFIG
-#define pTIMER8_COUNTER (volatile unsigned long *)TIMER8_COUNTER
-#define pTIMER8_PERIOD (volatile unsigned long *)TIMER8_PERIOD
-#define pTIMER8_WIDTH (volatile unsigned long *)TIMER8_WIDTH
-#define pTIMER9_CONFIG (volatile unsigned short *)TIMER9_CONFIG
-#define pTIMER9_COUNTER (volatile unsigned long *)TIMER9_COUNTER
-#define pTIMER9_PERIOD (volatile unsigned long *)TIMER9_PERIOD
-#define pTIMER9_WIDTH (volatile unsigned long *)TIMER9_WIDTH
-#define pTIMER10_CONFIG (volatile unsigned short *)TIMER10_CONFIG
-#define pTIMER10_COUNTER (volatile unsigned long *)TIMER10_COUNTER
-#define pTIMER10_PERIOD (volatile unsigned long *)TIMER10_PERIOD
-#define pTIMER10_WIDTH (volatile unsigned long *)TIMER10_WIDTH
-#define pTIMER11_CONFIG (volatile unsigned short *)TIMER11_CONFIG
-#define pTIMER11_COUNTER (volatile unsigned long *)TIMER11_COUNTER
-#define pTIMER11_PERIOD (volatile unsigned long *)TIMER11_PERIOD
-#define pTIMER11_WIDTH (volatile unsigned long *)TIMER11_WIDTH
-#define pTMRS4_ENABLE (volatile unsigned short *)TMRS4_ENABLE
-#define pTMRS4_DISABLE (volatile unsigned short *)TMRS4_DISABLE
-#define pTMRS4_STATUS (volatile unsigned long *)TMRS4_STATUS
+#define pTMRS8_ENABLE ((volatile unsigned short *)TMRS8_ENABLE)
+#define pTMRS8_DISABLE ((volatile unsigned short *)TMRS8_DISABLE)
+#define pTMRS8_STATUS ((volatile unsigned long *)TMRS8_STATUS)
+#define pTIMER8_CONFIG ((volatile unsigned short *)TIMER8_CONFIG)
+#define pTIMER8_COUNTER ((volatile unsigned long *)TIMER8_COUNTER)
+#define pTIMER8_PERIOD ((volatile unsigned long *)TIMER8_PERIOD)
+#define pTIMER8_WIDTH ((volatile unsigned long *)TIMER8_WIDTH)
+#define pTIMER9_CONFIG ((volatile unsigned short *)TIMER9_CONFIG)
+#define pTIMER9_COUNTER ((volatile unsigned long *)TIMER9_COUNTER)
+#define pTIMER9_PERIOD ((volatile unsigned long *)TIMER9_PERIOD)
+#define pTIMER9_WIDTH ((volatile unsigned long *)TIMER9_WIDTH)
+#define pTIMER10_CONFIG ((volatile unsigned short *)TIMER10_CONFIG)
+#define pTIMER10_COUNTER ((volatile unsigned long *)TIMER10_COUNTER)
+#define pTIMER10_PERIOD ((volatile unsigned long *)TIMER10_PERIOD)
+#define pTIMER10_WIDTH ((volatile unsigned long *)TIMER10_WIDTH)
+#define pTIMER11_CONFIG ((volatile unsigned short *)TIMER11_CONFIG)
+#define pTIMER11_COUNTER ((volatile unsigned long *)TIMER11_COUNTER)
+#define pTIMER11_PERIOD ((volatile unsigned long *)TIMER11_PERIOD)
+#define pTIMER11_WIDTH ((volatile unsigned long *)TIMER11_WIDTH)
+#define pTMRS4_ENABLE ((volatile unsigned short *)TMRS4_ENABLE)
+#define pTMRS4_DISABLE ((volatile unsigned short *)TMRS4_DISABLE)
+#define pTMRS4_STATUS ((volatile unsigned long *)TMRS4_STATUS)
/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
-#define pFIO0_FLAG_D (volatile unsigned short *)FIO0_FLAG_D
-#define pFIO0_FLAG_C (volatile unsigned short *)FIO0_FLAG_C
-#define pFIO0_FLAG_S (volatile unsigned short *)FIO0_FLAG_S
-#define pFIO0_FLAG_T (volatile unsigned short *)FIO0_FLAG_T
-#define pFIO0_MASKA_D (volatile unsigned short *)FIO0_MASKA_D
-#define pFIO0_MASKA_C (volatile unsigned short *)FIO0_MASKA_C
-#define pFIO0_MASKA_S (volatile unsigned short *)FIO0_MASKA_S
-#define pFIO0_MASKA_T (volatile unsigned short *)FIO0_MASKA_T
-#define pFIO0_MASKB_D (volatile unsigned short *)FIO0_MASKB_D
-#define pFIO0_MASKB_C (volatile unsigned short *)FIO0_MASKB_C
-#define pFIO0_MASKB_S (volatile unsigned short *)FIO0_MASKB_S
-#define pFIO0_MASKB_T (volatile unsigned short *)FIO0_MASKB_T
-#define pFIO0_DIR (volatile unsigned short *)FIO0_DIR
-#define pFIO0_POLAR (volatile unsigned short *)FIO0_POLAR
-#define pFIO0_EDGE (volatile unsigned short *)FIO0_EDGE
-#define pFIO0_BOTH (volatile unsigned short *)FIO0_BOTH
-#define pFIO0_INEN (volatile unsigned short *)FIO0_INEN
+#define pFIO0_FLAG_D ((volatile unsigned short *)FIO0_FLAG_D)
+#define pFIO0_FLAG_C ((volatile unsigned short *)FIO0_FLAG_C)
+#define pFIO0_FLAG_S ((volatile unsigned short *)FIO0_FLAG_S)
+#define pFIO0_FLAG_T ((volatile unsigned short *)FIO0_FLAG_T)
+#define pFIO0_MASKA_D ((volatile unsigned short *)FIO0_MASKA_D)
+#define pFIO0_MASKA_C ((volatile unsigned short *)FIO0_MASKA_C)
+#define pFIO0_MASKA_S ((volatile unsigned short *)FIO0_MASKA_S)
+#define pFIO0_MASKA_T ((volatile unsigned short *)FIO0_MASKA_T)
+#define pFIO0_MASKB_D ((volatile unsigned short *)FIO0_MASKB_D)
+#define pFIO0_MASKB_C ((volatile unsigned short *)FIO0_MASKB_C)
+#define pFIO0_MASKB_S ((volatile unsigned short *)FIO0_MASKB_S)
+#define pFIO0_MASKB_T ((volatile unsigned short *)FIO0_MASKB_T)
+#define pFIO0_DIR ((volatile unsigned short *)FIO0_DIR)
+#define pFIO0_POLAR ((volatile unsigned short *)FIO0_POLAR)
+#define pFIO0_EDGE ((volatile unsigned short *)FIO0_EDGE)
+#define pFIO0_BOTH ((volatile unsigned short *)FIO0_BOTH)
+#define pFIO0_INEN ((volatile unsigned short *)FIO0_INEN)
/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
-#define pFIO1_FLAG_D (volatile unsigned short *)FIO1_FLAG_D
-#define pFIO1_FLAG_C (volatile unsigned short *)FIO1_FLAG_C
-#define pFIO1_FLAG_S (volatile unsigned short *)FIO1_FLAG_S
-#define pFIO1_FLAG_T (volatile unsigned short *)FIO1_FLAG_T
-#define pFIO1_MASKA_D (volatile unsigned short *)FIO1_MASKA_D
-#define pFIO1_MASKA_C (volatile unsigned short *)FIO1_MASKA_C
-#define pFIO1_MASKA_S (volatile unsigned short *)FIO1_MASKA_S
-#define pFIO1_MASKA_T (volatile unsigned short *)FIO1_MASKA_T
-#define pFIO1_MASKB_D (volatile unsigned short *)FIO1_MASKB_D
-#define pFIO1_MASKB_C (volatile unsigned short *)FIO1_MASKB_C
-#define pFIO1_MASKB_S (volatile unsigned short *)FIO1_MASKB_S
-#define pFIO1_MASKB_T (volatile unsigned short *)FIO1_MASKB_T
-#define pFIO1_DIR (volatile unsigned short *)FIO1_DIR
-#define pFIO1_POLAR (volatile unsigned short *)FIO1_POLAR
-#define pFIO1_EDGE (volatile unsigned short *)FIO1_EDGE
-#define pFIO1_BOTH (volatile unsigned short *)FIO1_BOTH
-#define pFIO1_INEN (volatile unsigned short *)FIO1_INEN
+#define pFIO1_FLAG_D ((volatile unsigned short *)FIO1_FLAG_D)
+#define pFIO1_FLAG_C ((volatile unsigned short *)FIO1_FLAG_C)
+#define pFIO1_FLAG_S ((volatile unsigned short *)FIO1_FLAG_S)
+#define pFIO1_FLAG_T ((volatile unsigned short *)FIO1_FLAG_T)
+#define pFIO1_MASKA_D ((volatile unsigned short *)FIO1_MASKA_D)
+#define pFIO1_MASKA_C ((volatile unsigned short *)FIO1_MASKA_C)
+#define pFIO1_MASKA_S ((volatile unsigned short *)FIO1_MASKA_S)
+#define pFIO1_MASKA_T ((volatile unsigned short *)FIO1_MASKA_T)
+#define pFIO1_MASKB_D ((volatile unsigned short *)FIO1_MASKB_D)
+#define pFIO1_MASKB_C ((volatile unsigned short *)FIO1_MASKB_C)
+#define pFIO1_MASKB_S ((volatile unsigned short *)FIO1_MASKB_S)
+#define pFIO1_MASKB_T ((volatile unsigned short *)FIO1_MASKB_T)
+#define pFIO1_DIR ((volatile unsigned short *)FIO1_DIR)
+#define pFIO1_POLAR ((volatile unsigned short *)FIO1_POLAR)
+#define pFIO1_EDGE ((volatile unsigned short *)FIO1_EDGE)
+#define pFIO1_BOTH ((volatile unsigned short *)FIO1_BOTH)
+#define pFIO1_INEN ((volatile unsigned short *)FIO1_INEN)
/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
-#define pFIO2_FLAG_D (volatile unsigned short *)FIO2_FLAG_D
-#define pFIO2_FLAG_C (volatile unsigned short *)FIO2_FLAG_C
-#define pFIO2_FLAG_S (volatile unsigned short *)FIO2_FLAG_S
-#define pFIO2_FLAG_T (volatile unsigned short *)FIO2_FLAG_T
-#define pFIO2_MASKA_D (volatile unsigned short *)FIO2_MASKA_D
-#define pFIO2_MASKA_C (volatile unsigned short *)FIO2_MASKA_C
-#define pFIO2_MASKA_S (volatile unsigned short *)FIO2_MASKA_S
-#define pFIO2_MASKA_T (volatile unsigned short *)FIO2_MASKA_T
-#define pFIO2_MASKB_D (volatile unsigned short *)FIO2_MASKB_D
-#define pFIO2_MASKB_C (volatile unsigned short *)FIO2_MASKB_C
-#define pFIO2_MASKB_S (volatile unsigned short *)FIO2_MASKB_S
-#define pFIO2_MASKB_T (volatile unsigned short *)FIO2_MASKB_T
-#define pFIO2_DIR (volatile unsigned short *)FIO2_DIR
-#define pFIO2_POLAR (volatile unsigned short *)FIO2_POLAR
-#define pFIO2_EDGE (volatile unsigned short *)FIO2_EDGE
-#define pFIO2_BOTH (volatile unsigned short *)FIO2_BOTH
-#define pFIO2_INEN (volatile unsigned short *)FIO2_INEN
+#define pFIO2_FLAG_D ((volatile unsigned short *)FIO2_FLAG_D)
+#define pFIO2_FLAG_C ((volatile unsigned short *)FIO2_FLAG_C)
+#define pFIO2_FLAG_S ((volatile unsigned short *)FIO2_FLAG_S)
+#define pFIO2_FLAG_T ((volatile unsigned short *)FIO2_FLAG_T)
+#define pFIO2_MASKA_D ((volatile unsigned short *)FIO2_MASKA_D)
+#define pFIO2_MASKA_C ((volatile unsigned short *)FIO2_MASKA_C)
+#define pFIO2_MASKA_S ((volatile unsigned short *)FIO2_MASKA_S)
+#define pFIO2_MASKA_T ((volatile unsigned short *)FIO2_MASKA_T)
+#define pFIO2_MASKB_D ((volatile unsigned short *)FIO2_MASKB_D)
+#define pFIO2_MASKB_C ((volatile unsigned short *)FIO2_MASKB_C)
+#define pFIO2_MASKB_S ((volatile unsigned short *)FIO2_MASKB_S)
+#define pFIO2_MASKB_T ((volatile unsigned short *)FIO2_MASKB_T)
+#define pFIO2_DIR ((volatile unsigned short *)FIO2_DIR)
+#define pFIO2_POLAR ((volatile unsigned short *)FIO2_POLAR)
+#define pFIO2_EDGE ((volatile unsigned short *)FIO2_EDGE)
+#define pFIO2_BOTH ((volatile unsigned short *)FIO2_BOTH)
+#define pFIO2_INEN ((volatile unsigned short *)FIO2_INEN)
/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define pSPORT0_TCR1 (volatile unsigned short *)SPORT0_TCR1
-#define pSPORT0_TCR2 (volatile unsigned short *)SPORT0_TCR2
-#define pSPORT0_TCLKDIV (volatile unsigned short *)SPORT0_TCLKDIV
-#define pSPORT0_TFSDIV (volatile unsigned short *)SPORT0_TFSDIV
-#define pSPORT0_TX (volatile unsigned long *)SPORT0_TX
-#define pSPORT0_RX (volatile unsigned long *)SPORT0_RX
+#define pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1)
+#define pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2)
+#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV)
+#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV)
+#define pSPORT0_TX ((volatile unsigned long *)SPORT0_TX)
+#define pSPORT0_RX ((volatile unsigned long *)SPORT0_RX)
#define pSPORT0_TX32 ((volatile long *)SPORT0_TX)
#define pSPORT0_RX32 ((volatile long *)SPORT0_RX)
#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX)
#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX)
-#define pSPORT0_RCR1 (volatile unsigned short *)SPORT0_RCR1
-#define pSPORT0_RCR2 (volatile unsigned short *)SPORT0_RCR2
-#define pSPORT0_RCLKDIV (volatile unsigned short *)SPORT0_RCLKDIV
-#define pSPORT0_RFSDIV (volatile unsigned short *)SPORT0_RFSDIV
-#define pSPORT0_STAT (volatile unsigned short *)SPORT0_STAT
-#define pSPORT0_CHNL (volatile unsigned short *)SPORT0_CHNL
-#define pSPORT0_MCMC1 (volatile unsigned short *)SPORT0_MCMC1
-#define pSPORT0_MCMC2 (volatile unsigned short *)SPORT0_MCMC2
-#define pSPORT0_MTCS0 (volatile unsigned long *)SPORT0_MTCS0
-#define pSPORT0_MTCS1 (volatile unsigned long *)SPORT0_MTCS1
-#define pSPORT0_MTCS2 (volatile unsigned long *)SPORT0_MTCS2
-#define pSPORT0_MTCS3 (volatile unsigned long *)SPORT0_MTCS3
-#define pSPORT0_MRCS0 (volatile unsigned long *)SPORT0_MRCS0
-#define pSPORT0_MRCS1 (volatile unsigned long *)SPORT0_MRCS1
-#define pSPORT0_MRCS2 (volatile unsigned long *)SPORT0_MRCS2
-#define pSPORT0_MRCS3 (volatile unsigned long *)SPORT0_MRCS3
+#define pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1)
+#define pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2)
+#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV)
+#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV)
+#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT)
+#define pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL)
+#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1)
+#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2)
+#define pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0)
+#define pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1)
+#define pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2)
+#define pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3)
+#define pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0)
+#define pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1)
+#define pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2)
+#define pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3)
/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define pSPORT1_TCR1 (volatile unsigned short *)SPORT1_TCR1
-#define pSPORT1_TCR2 (volatile unsigned short *)SPORT1_TCR2
-#define pSPORT1_TCLKDIV (volatile unsigned short *)SPORT1_TCLKDIV
-#define pSPORT1_TFSDIV (volatile unsigned short *)SPORT1_TFSDIV
-#define pSPORT1_TX (volatile unsigned long *)SPORT1_TX
-#define pSPORT1_RX (volatile unsigned long *)SPORT1_RX
+#define pSPORT1_TCR1 ((volatile unsigned short *)SPORT1_TCR1)
+#define pSPORT1_TCR2 ((volatile unsigned short *)SPORT1_TCR2)
+#define pSPORT1_TCLKDIV ((volatile unsigned short *)SPORT1_TCLKDIV)
+#define pSPORT1_TFSDIV ((volatile unsigned short *)SPORT1_TFSDIV)
+#define pSPORT1_TX ((volatile unsigned long *)SPORT1_TX)
+#define pSPORT1_RX ((volatile unsigned long *)SPORT1_RX)
#define pSPORT1_TX32 ((volatile long *)SPORT1_TX)
#define pSPORT1_RX32 ((volatile long *)SPORT1_RX)
#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX)
#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX)
-#define pSPORT1_RCR1 (volatile unsigned short *)SPORT1_RCR1
-#define pSPORT1_RCR2 (volatile unsigned short *)SPORT1_RCR2
-#define pSPORT1_RCLKDIV (volatile unsigned short *)SPORT1_RCLKDIV
-#define pSPORT1_RFSDIV (volatile unsigned short *)SPORT1_RFSDIV
-#define pSPORT1_STAT (volatile unsigned short *)SPORT1_STAT
-#define pSPORT1_CHNL (volatile unsigned short *)SPORT1_CHNL
-#define pSPORT1_MCMC1 (volatile unsigned short *)SPORT1_MCMC1
-#define pSPORT1_MCMC2 (volatile unsigned short *)SPORT1_MCMC2
-#define pSPORT1_MTCS0 (volatile unsigned long *)SPORT1_MTCS0
-#define pSPORT1_MTCS1 (volatile unsigned long *)SPORT1_MTCS1
-#define pSPORT1_MTCS2 (volatile unsigned long *)SPORT1_MTCS2
-#define pSPORT1_MTCS3 (volatile unsigned long *)SPORT1_MTCS3
-#define pSPORT1_MRCS0 (volatile unsigned long *)SPORT1_MRCS0
-#define pSPORT1_MRCS1 (volatile unsigned long *)SPORT1_MRCS1
-#define pSPORT1_MRCS2 (volatile unsigned long *)SPORT1_MRCS2
-#define pSPORT1_MRCS3 (volatile unsigned long *)SPORT1_MRCS3
+#define pSPORT1_RCR1 ((volatile unsigned short *)SPORT1_RCR1)
+#define pSPORT1_RCR2 ((volatile unsigned short *)SPORT1_RCR2)
+#define pSPORT1_RCLKDIV ((volatile unsigned short *)SPORT1_RCLKDIV)
+#define pSPORT1_RFSDIV ((volatile unsigned short *)SPORT1_RFSDIV)
+#define pSPORT1_STAT ((volatile unsigned short *)SPORT1_STAT)
+#define pSPORT1_CHNL ((volatile unsigned short *)SPORT1_CHNL)
+#define pSPORT1_MCMC1 ((volatile unsigned short *)SPORT1_MCMC1)
+#define pSPORT1_MCMC2 ((volatile unsigned short *)SPORT1_MCMC2)
+#define pSPORT1_MTCS0 ((volatile unsigned long *)SPORT1_MTCS0)
+#define pSPORT1_MTCS1 ((volatile unsigned long *)SPORT1_MTCS1)
+#define pSPORT1_MTCS2 ((volatile unsigned long *)SPORT1_MTCS2)
+#define pSPORT1_MTCS3 ((volatile unsigned long *)SPORT1_MTCS3)
+#define pSPORT1_MRCS0 ((volatile unsigned long *)SPORT1_MRCS0)
+#define pSPORT1_MRCS1 ((volatile unsigned long *)SPORT1_MRCS1)
+#define pSPORT1_MRCS2 ((volatile unsigned long *)SPORT1_MRCS2)
+#define pSPORT1_MRCS3 ((volatile unsigned long *)SPORT1_MRCS3)
/* Asynchronous Memory Controller - External Bus Interface Unit */
-#define pEBIU_AMGCTL (volatile unsigned short *)EBIU_AMGCTL
-#define pEBIU_AMBCTL0 (volatile unsigned long *)EBIU_AMBCTL0
-#define pEBIU_AMBCTL1 (volatile unsigned long *)EBIU_AMBCTL1
+#define pEBIU_AMGCTL ((volatile unsigned short *)EBIU_AMGCTL)
+#define pEBIU_AMBCTL0 ((volatile unsigned long *)EBIU_AMBCTL0)
+#define pEBIU_AMBCTL1 ((volatile unsigned long *)EBIU_AMBCTL1)
/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define pEBIU_SDGCTL (volatile unsigned long *)EBIU_SDGCTL
-#define pEBIU_SDBCTL (volatile unsigned long *)EBIU_SDBCTL
-#define pEBIU_SDRRC (volatile unsigned short *)EBIU_SDRRC
-#define pEBIU_SDSTAT (volatile unsigned short *)EBIU_SDSTAT
+#define pEBIU_SDGCTL ((volatile unsigned long *)EBIU_SDGCTL)
+#define pEBIU_SDBCTL ((volatile unsigned long *)EBIU_SDBCTL)
+#define pEBIU_SDRRC ((volatile unsigned short *)EBIU_SDRRC)
+#define pEBIU_SDSTAT ((volatile unsigned short *)EBIU_SDSTAT)
/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
-#define pPPI0_CONTROL (volatile unsigned short *)PPI0_CONTROL
-#define pPPI0_STATUS (volatile unsigned short *)PPI0_STATUS
-#define pPPI0_COUNT (volatile unsigned short *)PPI0_COUNT
-#define pPPI0_DELAY (volatile unsigned short *)PPI0_DELAY
-#define pPPI0_FRAME (volatile unsigned short *)PPI0_FRAME
+#define pPPI0_CONTROL ((volatile unsigned short *)PPI0_CONTROL)
+#define pPPI0_STATUS ((volatile unsigned short *)PPI0_STATUS)
+#define pPPI0_COUNT ((volatile unsigned short *)PPI0_COUNT)
+#define pPPI0_DELAY ((volatile unsigned short *)PPI0_DELAY)
+#define pPPI0_FRAME ((volatile unsigned short *)PPI0_FRAME)
/* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
-#define pPPI1_CONTROL (volatile unsigned short *)PPI1_CONTROL
-#define pPPI1_STATUS (volatile unsigned short *)PPI1_STATUS
-#define pPPI1_COUNT (volatile unsigned short *)PPI1_COUNT
-#define pPPI1_DELAY (volatile unsigned short *)PPI1_DELAY
-#define pPPI1_FRAME (volatile unsigned short *)PPI1_FRAME
+#define pPPI1_CONTROL ((volatile unsigned short *)PPI1_CONTROL)
+#define pPPI1_STATUS ((volatile unsigned short *)PPI1_STATUS)
+#define pPPI1_COUNT ((volatile unsigned short *)PPI1_COUNT)
+#define pPPI1_DELAY ((volatile unsigned short *)PPI1_DELAY)
+#define pPPI1_FRAME ((volatile unsigned short *)PPI1_FRAME)
/*DMA traffic control registers */
-#define pDMA1_TC_PER (volatile unsigned short *)DMA1_TC_PER
-#define pDMA1_TC_CNT (volatile unsigned short *)DMA1_TC_CNT
-#define pDMA2_TC_PER (volatile unsigned short *)DMA2_TC_PER
-#define pDMA2_TC_CNT (volatile unsigned short *)DMA2_TC_CNT
+#define pDMA1_TC_PER ((volatile unsigned short *)DMA1_TC_PER)
+#define pDMA1_TC_CNT ((volatile unsigned short *)DMA1_TC_CNT)
+#define pDMA2_TC_PER ((volatile unsigned short *)DMA2_TC_PER)
+#define pDMA2_TC_CNT ((volatile unsigned short *)DMA2_TC_CNT)
/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
-#define pDMA1_0_CONFIG (volatile unsigned short *)DMA1_0_CONFIG
-#define pDMA1_0_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_0_NEXT_DESC_PTR
-#define pDMA1_0_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_0_START_ADDR
-#define pDMA1_0_X_COUNT (volatile unsigned short *)DMA1_0_X_COUNT
-#define pDMA1_0_Y_COUNT (volatile unsigned short *)DMA1_0_Y_COUNT
+#define pDMA1_0_CONFIG ((volatile unsigned short *)DMA1_0_CONFIG)
+#define pDMA1_0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_0_NEXT_DESC_PTR)
+#define pDMA1_0_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_0_START_ADDR)
+#define pDMA1_0_X_COUNT ((volatile unsigned short *)DMA1_0_X_COUNT)
+#define pDMA1_0_Y_COUNT ((volatile unsigned short *)DMA1_0_Y_COUNT)
#define pDMA1_0_X_MODIFY (volatile signed short *)DMA1_0_X_MODIFY
#define pDMA1_0_Y_MODIFY (volatile signed short *)DMA1_0_Y_MODIFY
-#define pDMA1_0_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_0_CURR_DESC_PTR
-#define pDMA1_0_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_0_CURR_ADDR
-#define pDMA1_0_CURR_X_COUNT (volatile unsigned short *)DMA1_0_CURR_X_COUNT
-#define pDMA1_0_CURR_Y_COUNT (volatile unsigned short *)DMA1_0_CURR_Y_COUNT
-#define pDMA1_0_IRQ_STATUS (volatile unsigned short *)DMA1_0_IRQ_STATUS
-#define pDMA1_0_PERIPHERAL_MAP (volatile unsigned short *)DMA1_0_PERIPHERAL_MAP
-#define pDMA1_1_CONFIG (volatile unsigned short *)DMA1_1_CONFIG
-#define pDMA1_1_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_1_NEXT_DESC_PTR
-#define pDMA1_1_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_1_START_ADDR
-#define pDMA1_1_X_COUNT (volatile unsigned short *)DMA1_1_X_COUNT
-#define pDMA1_1_Y_COUNT (volatile unsigned short *)DMA1_1_Y_COUNT
+#define pDMA1_0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_0_CURR_DESC_PTR)
+#define pDMA1_0_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_0_CURR_ADDR)
+#define pDMA1_0_CURR_X_COUNT ((volatile unsigned short *)DMA1_0_CURR_X_COUNT)
+#define pDMA1_0_CURR_Y_COUNT ((volatile unsigned short *)DMA1_0_CURR_Y_COUNT)
+#define pDMA1_0_IRQ_STATUS ((volatile unsigned short *)DMA1_0_IRQ_STATUS)
+#define pDMA1_0_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_0_PERIPHERAL_MAP)
+#define pDMA1_1_CONFIG ((volatile unsigned short *)DMA1_1_CONFIG)
+#define pDMA1_1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_1_NEXT_DESC_PTR)
+#define pDMA1_1_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_1_START_ADDR)
+#define pDMA1_1_X_COUNT ((volatile unsigned short *)DMA1_1_X_COUNT)
+#define pDMA1_1_Y_COUNT ((volatile unsigned short *)DMA1_1_Y_COUNT)
#define pDMA1_1_X_MODIFY (volatile signed short *)DMA1_1_X_MODIFY
#define pDMA1_1_Y_MODIFY (volatile signed short *)DMA1_1_Y_MODIFY
-#define pDMA1_1_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_1_CURR_DESC_PTR
-#define pDMA1_1_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_1_CURR_ADDR
-#define pDMA1_1_CURR_X_COUNT (volatile unsigned short *)DMA1_1_CURR_X_COUNT
-#define pDMA1_1_CURR_Y_COUNT (volatile unsigned short *)DMA1_1_CURR_Y_COUNT
-#define pDMA1_1_IRQ_STATUS (volatile unsigned short *)DMA1_1_IRQ_STATUS
-#define pDMA1_1_PERIPHERAL_MAP (volatile unsigned short *)DMA1_1_PERIPHERAL_MAP
-#define pDMA1_2_CONFIG (volatile unsigned short *)DMA1_2_CONFIG
-#define pDMA1_2_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_2_NEXT_DESC_PTR
-#define pDMA1_2_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_2_START_ADDR
-#define pDMA1_2_X_COUNT (volatile unsigned short *)DMA1_2_X_COUNT
-#define pDMA1_2_Y_COUNT (volatile unsigned short *)DMA1_2_Y_COUNT
+#define pDMA1_1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_1_CURR_DESC_PTR)
+#define pDMA1_1_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_1_CURR_ADDR)
+#define pDMA1_1_CURR_X_COUNT ((volatile unsigned short *)DMA1_1_CURR_X_COUNT)
+#define pDMA1_1_CURR_Y_COUNT ((volatile unsigned short *)DMA1_1_CURR_Y_COUNT)
+#define pDMA1_1_IRQ_STATUS ((volatile unsigned short *)DMA1_1_IRQ_STATUS)
+#define pDMA1_1_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_1_PERIPHERAL_MAP)
+#define pDMA1_2_CONFIG ((volatile unsigned short *)DMA1_2_CONFIG)
+#define pDMA1_2_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_2_NEXT_DESC_PTR)
+#define pDMA1_2_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_2_START_ADDR)
+#define pDMA1_2_X_COUNT ((volatile unsigned short *)DMA1_2_X_COUNT)
+#define pDMA1_2_Y_COUNT ((volatile unsigned short *)DMA1_2_Y_COUNT)
#define pDMA1_2_X_MODIFY (volatile signed short *)DMA1_2_X_MODIFY
#define pDMA1_2_Y_MODIFY (volatile signed short *)DMA1_2_Y_MODIFY
-#define pDMA1_2_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_2_CURR_DESC_PTR
-#define pDMA1_2_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_2_CURR_ADDR
-#define pDMA1_2_CURR_X_COUNT (volatile unsigned short *)DMA1_2_CURR_X_COUNT
-#define pDMA1_2_CURR_Y_COUNT (volatile unsigned short *)DMA1_2_CURR_Y_COUNT
-#define pDMA1_2_IRQ_STATUS (volatile unsigned short *)DMA1_2_IRQ_STATUS
-#define pDMA1_2_PERIPHERAL_MAP (volatile unsigned short *)DMA1_2_PERIPHERAL_MAP
-#define pDMA1_3_CONFIG (volatile unsigned short *)DMA1_3_CONFIG
-#define pDMA1_3_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_3_NEXT_DESC_PTR
-#define pDMA1_3_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_3_START_ADDR
-#define pDMA1_3_X_COUNT (volatile unsigned short *)DMA1_3_X_COUNT
-#define pDMA1_3_Y_COUNT (volatile unsigned short *)DMA1_3_Y_COUNT
+#define pDMA1_2_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_2_CURR_DESC_PTR)
+#define pDMA1_2_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_2_CURR_ADDR)
+#define pDMA1_2_CURR_X_COUNT ((volatile unsigned short *)DMA1_2_CURR_X_COUNT)
+#define pDMA1_2_CURR_Y_COUNT ((volatile unsigned short *)DMA1_2_CURR_Y_COUNT)
+#define pDMA1_2_IRQ_STATUS ((volatile unsigned short *)DMA1_2_IRQ_STATUS)
+#define pDMA1_2_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_2_PERIPHERAL_MAP)
+#define pDMA1_3_CONFIG ((volatile unsigned short *)DMA1_3_CONFIG)
+#define pDMA1_3_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_3_NEXT_DESC_PTR)
+#define pDMA1_3_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_3_START_ADDR)
+#define pDMA1_3_X_COUNT ((volatile unsigned short *)DMA1_3_X_COUNT)
+#define pDMA1_3_Y_COUNT ((volatile unsigned short *)DMA1_3_Y_COUNT)
#define pDMA1_3_X_MODIFY (volatile signed short *)DMA1_3_X_MODIFY
#define pDMA1_3_Y_MODIFY (volatile signed short *)DMA1_3_Y_MODIFY
-#define pDMA1_3_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_3_CURR_DESC_PTR
-#define pDMA1_3_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_3_CURR_ADDR
-#define pDMA1_3_CURR_X_COUNT (volatile unsigned short *)DMA1_3_CURR_X_COUNT
-#define pDMA1_3_CURR_Y_COUNT (volatile unsigned short *)DMA1_3_CURR_Y_COUNT
-#define pDMA1_3_IRQ_STATUS (volatile unsigned short *)DMA1_3_IRQ_STATUS
-#define pDMA1_3_PERIPHERAL_MAP (volatile unsigned short *)DMA1_3_PERIPHERAL_MAP
-#define pDMA1_4_CONFIG (volatile unsigned short *)DMA1_4_CONFIG
-#define pDMA1_4_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_4_NEXT_DESC_PTR
-#define pDMA1_4_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_4_START_ADDR
-#define pDMA1_4_X_COUNT (volatile unsigned short *)DMA1_4_X_COUNT
-#define pDMA1_4_Y_COUNT (volatile unsigned short *)DMA1_4_Y_COUNT
+#define pDMA1_3_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_3_CURR_DESC_PTR)
+#define pDMA1_3_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_3_CURR_ADDR)
+#define pDMA1_3_CURR_X_COUNT ((volatile unsigned short *)DMA1_3_CURR_X_COUNT)
+#define pDMA1_3_CURR_Y_COUNT ((volatile unsigned short *)DMA1_3_CURR_Y_COUNT)
+#define pDMA1_3_IRQ_STATUS ((volatile unsigned short *)DMA1_3_IRQ_STATUS)
+#define pDMA1_3_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_3_PERIPHERAL_MAP)
+#define pDMA1_4_CONFIG ((volatile unsigned short *)DMA1_4_CONFIG)
+#define pDMA1_4_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_4_NEXT_DESC_PTR)
+#define pDMA1_4_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_4_START_ADDR)
+#define pDMA1_4_X_COUNT ((volatile unsigned short *)DMA1_4_X_COUNT)
+#define pDMA1_4_Y_COUNT ((volatile unsigned short *)DMA1_4_Y_COUNT)
#define pDMA1_4_X_MODIFY (volatile signed short *)DMA1_4_X_MODIFY
#define pDMA1_4_Y_MODIFY (volatile signed short *)DMA1_4_Y_MODIFY
-#define pDMA1_4_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_4_CURR_DESC_PTR
-#define pDMA1_4_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_4_CURR_ADDR
-#define pDMA1_4_CURR_X_COUNT (volatile unsigned short *)DMA1_4_CURR_X_COUNT
-#define pDMA1_4_CURR_Y_COUNT (volatile unsigned short *)DMA1_4_CURR_Y_COUNT
-#define pDMA1_4_IRQ_STATUS (volatile unsigned short *)DMA1_4_IRQ_STATUS
-#define pDMA1_4_PERIPHERAL_MAP (volatile unsigned short *)DMA1_4_PERIPHERAL_MAP
-#define pDMA1_5_CONFIG (volatile unsigned short *)DMA1_5_CONFIG
-#define pDMA1_5_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_5_NEXT_DESC_PTR
-#define pDMA1_5_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_5_START_ADDR
-#define pDMA1_5_X_COUNT (volatile unsigned short *)DMA1_5_X_COUNT
-#define pDMA1_5_Y_COUNT (volatile unsigned short *)DMA1_5_Y_COUNT
+#define pDMA1_4_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_4_CURR_DESC_PTR)
+#define pDMA1_4_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_4_CURR_ADDR)
+#define pDMA1_4_CURR_X_COUNT ((volatile unsigned short *)DMA1_4_CURR_X_COUNT)
+#define pDMA1_4_CURR_Y_COUNT ((volatile unsigned short *)DMA1_4_CURR_Y_COUNT)
+#define pDMA1_4_IRQ_STATUS ((volatile unsigned short *)DMA1_4_IRQ_STATUS)
+#define pDMA1_4_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_4_PERIPHERAL_MAP)
+#define pDMA1_5_CONFIG ((volatile unsigned short *)DMA1_5_CONFIG)
+#define pDMA1_5_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_5_NEXT_DESC_PTR)
+#define pDMA1_5_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_5_START_ADDR)
+#define pDMA1_5_X_COUNT ((volatile unsigned short *)DMA1_5_X_COUNT)
+#define pDMA1_5_Y_COUNT ((volatile unsigned short *)DMA1_5_Y_COUNT)
#define pDMA1_5_X_MODIFY (volatile signed short *)DMA1_5_X_MODIFY
#define pDMA1_5_Y_MODIFY (volatile signed short *)DMA1_5_Y_MODIFY
-#define pDMA1_5_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_5_CURR_DESC_PTR
-#define pDMA1_5_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_5_CURR_ADDR
-#define pDMA1_5_CURR_X_COUNT (volatile unsigned short *)DMA1_5_CURR_X_COUNT
-#define pDMA1_5_CURR_Y_COUNT (volatile unsigned short *)DMA1_5_CURR_Y_COUNT
-#define pDMA1_5_IRQ_STATUS (volatile unsigned short *)DMA1_5_IRQ_STATUS
-#define pDMA1_5_PERIPHERAL_MAP (volatile unsigned short *)DMA1_5_PERIPHERAL_MAP
-#define pDMA1_6_CONFIG (volatile unsigned short *)DMA1_6_CONFIG
-#define pDMA1_6_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_6_NEXT_DESC_PTR
-#define pDMA1_6_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_6_START_ADDR
-#define pDMA1_6_X_COUNT (volatile unsigned short *)DMA1_6_X_COUNT
-#define pDMA1_6_Y_COUNT (volatile unsigned short *)DMA1_6_Y_COUNT
+#define pDMA1_5_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_5_CURR_DESC_PTR)
+#define pDMA1_5_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_5_CURR_ADDR)
+#define pDMA1_5_CURR_X_COUNT ((volatile unsigned short *)DMA1_5_CURR_X_COUNT)
+#define pDMA1_5_CURR_Y_COUNT ((volatile unsigned short *)DMA1_5_CURR_Y_COUNT)
+#define pDMA1_5_IRQ_STATUS ((volatile unsigned short *)DMA1_5_IRQ_STATUS)
+#define pDMA1_5_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_5_PERIPHERAL_MAP)
+#define pDMA1_6_CONFIG ((volatile unsigned short *)DMA1_6_CONFIG)
+#define pDMA1_6_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_6_NEXT_DESC_PTR)
+#define pDMA1_6_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_6_START_ADDR)
+#define pDMA1_6_X_COUNT ((volatile unsigned short *)DMA1_6_X_COUNT)
+#define pDMA1_6_Y_COUNT ((volatile unsigned short *)DMA1_6_Y_COUNT)
#define pDMA1_6_X_MODIFY (volatile signed short *)DMA1_6_X_MODIFY
#define pDMA1_6_Y_MODIFY (volatile signed short *)DMA1_6_Y_MODIFY
-#define pDMA1_6_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_6_CURR_DESC_PTR
-#define pDMA1_6_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_6_CURR_ADDR
-#define pDMA1_6_CURR_X_COUNT (volatile unsigned short *)DMA1_6_CURR_X_COUNT
-#define pDMA1_6_CURR_Y_COUNT (volatile unsigned short *)DMA1_6_CURR_Y_COUNT
-#define pDMA1_6_IRQ_STATUS (volatile unsigned short *)DMA1_6_IRQ_STATUS
-#define pDMA1_6_PERIPHERAL_MAP (volatile unsigned short *)DMA1_6_PERIPHERAL_MAP
-#define pDMA1_7_CONFIG (volatile unsigned short *)DMA1_7_CONFIG
-#define pDMA1_7_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_7_NEXT_DESC_PTR
-#define pDMA1_7_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_7_START_ADDR
-#define pDMA1_7_X_COUNT (volatile unsigned short *)DMA1_7_X_COUNT
-#define pDMA1_7_Y_COUNT (volatile unsigned short *)DMA1_7_Y_COUNT
+#define pDMA1_6_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_6_CURR_DESC_PTR)
+#define pDMA1_6_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_6_CURR_ADDR)
+#define pDMA1_6_CURR_X_COUNT ((volatile unsigned short *)DMA1_6_CURR_X_COUNT)
+#define pDMA1_6_CURR_Y_COUNT ((volatile unsigned short *)DMA1_6_CURR_Y_COUNT)
+#define pDMA1_6_IRQ_STATUS ((volatile unsigned short *)DMA1_6_IRQ_STATUS)
+#define pDMA1_6_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_6_PERIPHERAL_MAP)
+#define pDMA1_7_CONFIG ((volatile unsigned short *)DMA1_7_CONFIG)
+#define pDMA1_7_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_7_NEXT_DESC_PTR)
+#define pDMA1_7_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_7_START_ADDR)
+#define pDMA1_7_X_COUNT ((volatile unsigned short *)DMA1_7_X_COUNT)
+#define pDMA1_7_Y_COUNT ((volatile unsigned short *)DMA1_7_Y_COUNT)
#define pDMA1_7_X_MODIFY (volatile signed short *)DMA1_7_X_MODIFY
#define pDMA1_7_Y_MODIFY (volatile signed short *)DMA1_7_Y_MODIFY
-#define pDMA1_7_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_7_CURR_DESC_PTR
-#define pDMA1_7_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_7_CURR_ADDR
-#define pDMA1_7_CURR_X_COUNT (volatile unsigned short *)DMA1_7_CURR_X_COUNT
-#define pDMA1_7_CURR_Y_COUNT (volatile unsigned short *)DMA1_7_CURR_Y_COUNT
-#define pDMA1_7_IRQ_STATUS (volatile unsigned short *)DMA1_7_IRQ_STATUS
-#define pDMA1_7_PERIPHERAL_MAP (volatile unsigned short *)DMA1_7_PERIPHERAL_MAP
-#define pDMA1_8_CONFIG (volatile unsigned short *)DMA1_8_CONFIG
-#define pDMA1_8_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_8_NEXT_DESC_PTR
-#define pDMA1_8_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_8_START_ADDR
-#define pDMA1_8_X_COUNT (volatile unsigned short *)DMA1_8_X_COUNT
-#define pDMA1_8_Y_COUNT (volatile unsigned short *)DMA1_8_Y_COUNT
+#define pDMA1_7_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_7_CURR_DESC_PTR)
+#define pDMA1_7_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_7_CURR_ADDR)
+#define pDMA1_7_CURR_X_COUNT ((volatile unsigned short *)DMA1_7_CURR_X_COUNT)
+#define pDMA1_7_CURR_Y_COUNT ((volatile unsigned short *)DMA1_7_CURR_Y_COUNT)
+#define pDMA1_7_IRQ_STATUS ((volatile unsigned short *)DMA1_7_IRQ_STATUS)
+#define pDMA1_7_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_7_PERIPHERAL_MAP)
+#define pDMA1_8_CONFIG ((volatile unsigned short *)DMA1_8_CONFIG)
+#define pDMA1_8_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_8_NEXT_DESC_PTR)
+#define pDMA1_8_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_8_START_ADDR)
+#define pDMA1_8_X_COUNT ((volatile unsigned short *)DMA1_8_X_COUNT)
+#define pDMA1_8_Y_COUNT ((volatile unsigned short *)DMA1_8_Y_COUNT)
#define pDMA1_8_X_MODIFY (volatile signed short *)DMA1_8_X_MODIFY
#define pDMA1_8_Y_MODIFY (volatile signed short *)DMA1_8_Y_MODIFY
-#define pDMA1_8_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_8_CURR_DESC_PTR
-#define pDMA1_8_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_8_CURR_ADDR
-#define pDMA1_8_CURR_X_COUNT (volatile unsigned short *)DMA1_8_CURR_X_COUNT
-#define pDMA1_8_CURR_Y_COUNT (volatile unsigned short *)DMA1_8_CURR_Y_COUNT
-#define pDMA1_8_IRQ_STATUS (volatile unsigned short *)DMA1_8_IRQ_STATUS
-#define pDMA1_8_PERIPHERAL_MAP (volatile unsigned short *)DMA1_8_PERIPHERAL_MAP
-#define pDMA1_9_CONFIG (volatile unsigned short *)DMA1_9_CONFIG
-#define pDMA1_9_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_9_NEXT_DESC_PTR
-#define pDMA1_9_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_9_START_ADDR
-#define pDMA1_9_X_COUNT (volatile unsigned short *)DMA1_9_X_COUNT
-#define pDMA1_9_Y_COUNT (volatile unsigned short *)DMA1_9_Y_COUNT
+#define pDMA1_8_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_8_CURR_DESC_PTR)
+#define pDMA1_8_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_8_CURR_ADDR)
+#define pDMA1_8_CURR_X_COUNT ((volatile unsigned short *)DMA1_8_CURR_X_COUNT)
+#define pDMA1_8_CURR_Y_COUNT ((volatile unsigned short *)DMA1_8_CURR_Y_COUNT)
+#define pDMA1_8_IRQ_STATUS ((volatile unsigned short *)DMA1_8_IRQ_STATUS)
+#define pDMA1_8_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_8_PERIPHERAL_MAP)
+#define pDMA1_9_CONFIG ((volatile unsigned short *)DMA1_9_CONFIG)
+#define pDMA1_9_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_9_NEXT_DESC_PTR)
+#define pDMA1_9_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_9_START_ADDR)
+#define pDMA1_9_X_COUNT ((volatile unsigned short *)DMA1_9_X_COUNT)
+#define pDMA1_9_Y_COUNT ((volatile unsigned short *)DMA1_9_Y_COUNT)
#define pDMA1_9_X_MODIFY (volatile signed short *)DMA1_9_X_MODIFY
#define pDMA1_9_Y_MODIFY (volatile signed short *)DMA1_9_Y_MODIFY
-#define pDMA1_9_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_9_CURR_DESC_PTR
-#define pDMA1_9_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_9_CURR_ADDR
-#define pDMA1_9_CURR_X_COUNT (volatile unsigned short *)DMA1_9_CURR_X_COUNT
-#define pDMA1_9_CURR_Y_COUNT (volatile unsigned short *)DMA1_9_CURR_Y_COUNT
-#define pDMA1_9_IRQ_STATUS (volatile unsigned short *)DMA1_9_IRQ_STATUS
-#define pDMA1_9_PERIPHERAL_MAP (volatile unsigned short *)DMA1_9_PERIPHERAL_MAP
-#define pDMA1_10_CONFIG (volatile unsigned short *)DMA1_10_CONFIG
-#define pDMA1_10_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_10_NEXT_DESC_PTR
-#define pDMA1_10_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_10_START_ADDR
-#define pDMA1_10_X_COUNT (volatile unsigned short *)DMA1_10_X_COUNT
-#define pDMA1_10_Y_COUNT (volatile unsigned short *)DMA1_10_Y_COUNT
+#define pDMA1_9_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_9_CURR_DESC_PTR)
+#define pDMA1_9_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_9_CURR_ADDR)
+#define pDMA1_9_CURR_X_COUNT ((volatile unsigned short *)DMA1_9_CURR_X_COUNT)
+#define pDMA1_9_CURR_Y_COUNT ((volatile unsigned short *)DMA1_9_CURR_Y_COUNT)
+#define pDMA1_9_IRQ_STATUS ((volatile unsigned short *)DMA1_9_IRQ_STATUS)
+#define pDMA1_9_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_9_PERIPHERAL_MAP)
+#define pDMA1_10_CONFIG ((volatile unsigned short *)DMA1_10_CONFIG)
+#define pDMA1_10_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_10_NEXT_DESC_PTR)
+#define pDMA1_10_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_10_START_ADDR)
+#define pDMA1_10_X_COUNT ((volatile unsigned short *)DMA1_10_X_COUNT)
+#define pDMA1_10_Y_COUNT ((volatile unsigned short *)DMA1_10_Y_COUNT)
#define pDMA1_10_X_MODIFY (volatile signed short *)DMA1_10_X_MODIFY
#define pDMA1_10_Y_MODIFY (volatile signed short *)DMA1_10_Y_MODIFY
-#define pDMA1_10_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_10_CURR_DESC_PTR
-#define pDMA1_10_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_10_CURR_ADDR
-#define pDMA1_10_CURR_X_COUNT (volatile unsigned short *)DMA1_10_CURR_X_COUNT
-#define pDMA1_10_CURR_Y_COUNT (volatile unsigned short *)DMA1_10_CURR_Y_COUNT
-#define pDMA1_10_IRQ_STATUS (volatile unsigned short *)DMA1_10_IRQ_STATUS
-#define pDMA1_10_PERIPHERAL_MAP (volatile unsigned short *)DMA1_10_PERIPHERAL_MAP
-#define pDMA1_11_CONFIG (volatile unsigned short *)DMA1_11_CONFIG
-#define pDMA1_11_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_11_NEXT_DESC_PTR
-#define pDMA1_11_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_11_START_ADDR
-#define pDMA1_11_X_COUNT (volatile unsigned short *)DMA1_11_X_COUNT
-#define pDMA1_11_Y_COUNT (volatile unsigned short *)DMA1_11_Y_COUNT
+#define pDMA1_10_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_10_CURR_DESC_PTR)
+#define pDMA1_10_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_10_CURR_ADDR)
+#define pDMA1_10_CURR_X_COUNT ((volatile unsigned short *)DMA1_10_CURR_X_COUNT)
+#define pDMA1_10_CURR_Y_COUNT ((volatile unsigned short *)DMA1_10_CURR_Y_COUNT)
+#define pDMA1_10_IRQ_STATUS ((volatile unsigned short *)DMA1_10_IRQ_STATUS)
+#define pDMA1_10_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_10_PERIPHERAL_MAP)
+#define pDMA1_11_CONFIG ((volatile unsigned short *)DMA1_11_CONFIG)
+#define pDMA1_11_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_11_NEXT_DESC_PTR)
+#define pDMA1_11_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_11_START_ADDR)
+#define pDMA1_11_X_COUNT ((volatile unsigned short *)DMA1_11_X_COUNT)
+#define pDMA1_11_Y_COUNT ((volatile unsigned short *)DMA1_11_Y_COUNT)
#define pDMA1_11_X_MODIFY (volatile signed short *)DMA1_11_X_MODIFY
#define pDMA1_11_Y_MODIFY (volatile signed short *)DMA1_11_Y_MODIFY
-#define pDMA1_11_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_11_CURR_DESC_PTR
-#define pDMA1_11_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_11_CURR_ADDR
-#define pDMA1_11_CURR_X_COUNT (volatile unsigned short *)DMA1_11_CURR_X_COUNT
-#define pDMA1_11_CURR_Y_COUNT (volatile unsigned short *)DMA1_11_CURR_Y_COUNT
-#define pDMA1_11_IRQ_STATUS (volatile unsigned short *)DMA1_11_IRQ_STATUS
-#define pDMA1_11_PERIPHERAL_MAP (volatile unsigned short *)DMA1_11_PERIPHERAL_MAP
+#define pDMA1_11_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_11_CURR_DESC_PTR)
+#define pDMA1_11_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_11_CURR_ADDR)
+#define pDMA1_11_CURR_X_COUNT ((volatile unsigned short *)DMA1_11_CURR_X_COUNT)
+#define pDMA1_11_CURR_Y_COUNT ((volatile unsigned short *)DMA1_11_CURR_Y_COUNT)
+#define pDMA1_11_IRQ_STATUS ((volatile unsigned short *)DMA1_11_IRQ_STATUS)
+#define pDMA1_11_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_11_PERIPHERAL_MAP)
/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
-#define pMDMA1_D0_CONFIG (volatile unsigned short *)MDMA1_D0_CONFIG
-#define pMDMA1_D0_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA1_D0_NEXT_DESC_PTR
-#define pMDMA1_D0_START_ADDR _PTR_TO_VOL_VOID_PTR MDMA1_D0_START_ADDR
-#define pMDMA1_D0_X_COUNT (volatile unsigned short *)MDMA1_D0_X_COUNT
-#define pMDMA1_D0_Y_COUNT (volatile unsigned short *)MDMA1_D0_Y_COUNT
+#define pMDMA1_D0_CONFIG ((volatile unsigned short *)MDMA1_D0_CONFIG)
+#define pMDMA1_D0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA1_D0_NEXT_DESC_PTR)
+#define pMDMA1_D0_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA1_D0_START_ADDR)
+#define pMDMA1_D0_X_COUNT ((volatile unsigned short *)MDMA1_D0_X_COUNT)
+#define pMDMA1_D0_Y_COUNT ((volatile unsigned short *)MDMA1_D0_Y_COUNT)
#define pMDMA1_D0_X_MODIFY (volatile signed short *)MDMA1_D0_X_MODIFY
#define pMDMA1_D0_Y_MODIFY (volatile signed short *)MDMA1_D0_Y_MODIFY
-#define pMDMA1_D0_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA1_D0_CURR_DESC_PTR
-#define pMDMA1_D0_CURR_ADDR _PTR_TO_VOL_VOID_PTR MDMA1_D0_CURR_ADDR
-#define pMDMA1_D0_CURR_X_COUNT (volatile unsigned short *)MDMA1_D0_CURR_X_COUNT
-#define pMDMA1_D0_CURR_Y_COUNT (volatile unsigned short *)MDMA1_D0_CURR_Y_COUNT
-#define pMDMA1_D0_IRQ_STATUS (volatile unsigned short *)MDMA1_D0_IRQ_STATUS
-#define pMDMA1_D0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D0_PERIPHERAL_MAP
-#define pMDMA1_S0_CONFIG (volatile unsigned short *)MDMA1_S0_CONFIG
-#define pMDMA1_S0_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA1_S0_NEXT_DESC_PTR
-#define pMDMA1_S0_START_ADDR _PTR_TO_VOL_VOID_PTR MDMA1_S0_START_ADDR
-#define pMDMA1_S0_X_COUNT (volatile unsigned short *)MDMA1_S0_X_COUNT
-#define pMDMA1_S0_Y_COUNT (volatile unsigned short *)MDMA1_S0_Y_COUNT
+#define pMDMA1_D0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA1_D0_CURR_DESC_PTR)
+#define pMDMA1_D0_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA1_D0_CURR_ADDR)
+#define pMDMA1_D0_CURR_X_COUNT ((volatile unsigned short *)MDMA1_D0_CURR_X_COUNT )
+#define pMDMA1_D0_CURR_Y_COUNT ((volatile unsigned short *)MDMA1_D0_CURR_Y_COUNT)
+#define pMDMA1_D0_IRQ_STATUS ((volatile unsigned short *)MDMA1_D0_IRQ_STATUS)
+#define pMDMA1_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA1_D0_PERIPHERAL_MAP)
+#define pMDMA1_S0_CONFIG ((volatile unsigned short *)MDMA1_S0_CONFIG)
+#define pMDMA1_S0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA1_S0_NEXT_DESC_PTR)
+#define pMDMA1_S0_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA1_S0_START_ADDR)
+#define pMDMA1_S0_X_COUNT ((volatile unsigned short *)MDMA1_S0_X_COUNT)
+#define pMDMA1_S0_Y_COUNT ((volatile unsigned short *)MDMA1_S0_Y_COUNT)
#define pMDMA1_S0_X_MODIFY (volatile signed short *)MDMA1_S0_X_MODIFY
#define pMDMA1_S0_Y_MODIFY (volatile signed short *)MDMA1_S0_Y_MODIFY
-#define pMDMA1_S0_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA1_S0_CURR_DESC_PTR
-#define pMDMA1_S0_CURR_ADDR _PTR_TO_VOL_VOID_PTR MDMA1_S0_CURR_ADDR
-#define pMDMA1_S0_CURR_X_COUNT (volatile unsigned short *)MDMA1_S0_CURR_X_COUNT
-#define pMDMA1_S0_CURR_Y_COUNT (volatile unsigned short *)MDMA1_S0_CURR_Y_COUNT
-#define pMDMA1_S0_IRQ_STATUS (volatile unsigned short *)MDMA1_S0_IRQ_STATUS
-#define pMDMA1_S0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S0_PERIPHERAL_MAP
-#define pMDMA1_D1_CONFIG (volatile unsigned short *)MDMA1_D1_CONFIG
-#define pMDMA1_D1_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA1_D1_NEXT_DESC_PTR
-#define pMDMA1_D1_START_ADDR _PTR_TO_VOL_VOID_PTR MDMA1_D1_START_ADDR
-#define pMDMA1_D1_X_COUNT (volatile unsigned short *)MDMA1_D1_X_COUNT
-#define pMDMA1_D1_Y_COUNT (volatile unsigned short *)MDMA1_D1_Y_COUNT
+#define pMDMA1_S0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA1_S0_CURR_DESC_PTR)
+#define pMDMA1_S0_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA1_S0_CURR_ADDR)
+#define pMDMA1_S0_CURR_X_COUNT ((volatile unsigned short *)MDMA1_S0_CURR_X_COUNT)
+#define pMDMA1_S0_CURR_Y_COUNT ((volatile unsigned short *)MDMA1_S0_CURR_Y_COUNT)
+#define pMDMA1_S0_IRQ_STATUS ((volatile unsigned short *)MDMA1_S0_IRQ_STATUS)
+#define pMDMA1_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA1_S0_PERIPHERAL_MAP)
+#define pMDMA1_D1_CONFIG ((volatile unsigned short *)MDMA1_D1_CONFIG)
+#define pMDMA1_D1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA1_D1_NEXT_DESC_PTR)
+#define pMDMA1_D1_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA1_D1_START_ADDR)
+#define pMDMA1_D1_X_COUNT ((volatile unsigned short *)MDMA1_D1_X_COUNT)
+#define pMDMA1_D1_Y_COUNT ((volatile unsigned short *)MDMA1_D1_Y_COUNT)
#define pMDMA1_D1_X_MODIFY (volatile signed short *)MDMA1_D1_X_MODIFY
#define pMDMA1_D1_Y_MODIFY (volatile signed short *)MDMA1_D1_Y_MODIFY
-#define pMDMA1_D1_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA1_D1_CURR_DESC_PTR
-#define pMDMA1_D1_CURR_ADDR _PTR_TO_VOL_VOID_PTR MDMA1_D1_CURR_ADDR
-#define pMDMA1_D1_CURR_X_COUNT (volatile unsigned short *)MDMA1_D1_CURR_X_COUNT
-#define pMDMA1_D1_CURR_Y_COUNT (volatile unsigned short *)MDMA1_D1_CURR_Y_COUNT
-#define pMDMA1_D1_IRQ_STATUS (volatile unsigned short *)MDMA1_D1_IRQ_STATUS
-#define pMDMA1_D1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D1_PERIPHERAL_MAP
-#define pMDMA1_S1_CONFIG (volatile unsigned short *)MDMA1_S1_CONFIG
-#define pMDMA1_S1_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA1_S1_NEXT_DESC_PTR
-#define pMDMA1_S1_START_ADDR _PTR_TO_VOL_VOID_PTR MDMA1_S1_START_ADDR
-#define pMDMA1_S1_X_COUNT (volatile unsigned short *)MDMA1_S1_X_COUNT
-#define pMDMA1_S1_Y_COUNT (volatile unsigned short *)MDMA1_S1_Y_COUNT
+#define pMDMA1_D1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA1_D1_CURR_DESC_PTR)
+#define pMDMA1_D1_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA1_D1_CURR_ADDR)
+#define pMDMA1_D1_CURR_X_COUNT ((volatile unsigned short *)MDMA1_D1_CURR_X_COUNT)
+#define pMDMA1_D1_CURR_Y_COUNT ((volatile unsigned short *)MDMA1_D1_CURR_Y_COUNT)
+#define pMDMA1_D1_IRQ_STATUS ((volatile unsigned short *)MDMA1_D1_IRQ_STATUS)
+#define pMDMA1_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA1_D1_PERIPHERAL_MAP)
+#define pMDMA1_S1_CONFIG ((volatile unsigned short *)MDMA1_S1_CONFIG)
+#define pMDMA1_S1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA1_S1_NEXT_DESC_PTR)
+#define pMDMA1_S1_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA1_S1_START_ADDR)
+#define pMDMA1_S1_X_COUNT ((volatile unsigned short *)MDMA1_S1_X_COUNT)
+#define pMDMA1_S1_Y_COUNT ((volatile unsigned short *)MDMA1_S1_Y_COUNT)
#define pMDMA1_S1_X_MODIFY (volatile signed short *)MDMA1_S1_X_MODIFY
#define pMDMA1_S1_Y_MODIFY (volatile signed short *)MDMA1_S1_Y_MODIFY
-#define pMDMA1_S1_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA1_S1_CURR_DESC_PTR
-#define pMDMA1_S1_CURR_ADDR _PTR_TO_VOL_VOID_PTR MDMA1_S1_CURR_ADDR
-#define pMDMA1_S1_CURR_X_COUNT (volatile unsigned short *)MDMA1_S1_CURR_X_COUNT
-#define pMDMA1_S1_CURR_Y_COUNT (volatile unsigned short *)MDMA1_S1_CURR_Y_COUNT
-#define pMDMA1_S1_IRQ_STATUS (volatile unsigned short *)MDMA1_S1_IRQ_STATUS
-#define pMDMA1_S1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S1_PERIPHERAL_MAP
+#define pMDMA1_S1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA1_S1_CURR_DESC_PTR)
+#define pMDMA1_S1_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA1_S1_CURR_ADDR)
+#define pMDMA1_S1_CURR_X_COUNT ((volatile unsigned short *)MDMA1_S1_CURR_X_COUNT)
+#define pMDMA1_S1_CURR_Y_COUNT ((volatile unsigned short *)MDMA1_S1_CURR_Y_COUNT)
+#define pMDMA1_S1_IRQ_STATUS ((volatile unsigned short *)MDMA1_S1_IRQ_STATUS)
+#define pMDMA1_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA1_S1_PERIPHERAL_MAP)
/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
-#define pDMA2_0_CONFIG (volatile unsigned short *)DMA2_0_CONFIG
-#define pDMA2_0_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_0_NEXT_DESC_PTR
-#define pDMA2_0_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_0_START_ADDR
-#define pDMA2_0_X_COUNT (volatile unsigned short *)DMA2_0_X_COUNT
-#define pDMA2_0_Y_COUNT (volatile unsigned short *)DMA2_0_Y_COUNT
+#define pDMA2_0_CONFIG ((volatile unsigned short *)DMA2_0_CONFIG)
+#define pDMA2_0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_0_NEXT_DESC_PTR)
+#define pDMA2_0_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_0_START_ADDR)
+#define pDMA2_0_X_COUNT ((volatile unsigned short *)DMA2_0_X_COUNT)
+#define pDMA2_0_Y_COUNT ((volatile unsigned short *)DMA2_0_Y_COUNT)
#define pDMA2_0_X_MODIFY (volatile signed short *)DMA2_0_X_MODIFY
#define pDMA2_0_Y_MODIFY (volatile signed short *)DMA2_0_Y_MODIFY
-#define pDMA2_0_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_0_CURR_DESC_PTR
-#define pDMA2_0_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_0_CURR_ADDR
-#define pDMA2_0_CURR_X_COUNT (volatile unsigned short *)DMA2_0_CURR_X_COUNT
-#define pDMA2_0_CURR_Y_COUNT (volatile unsigned short *)DMA2_0_CURR_Y_COUNT
-#define pDMA2_0_IRQ_STATUS (volatile unsigned short *)DMA2_0_IRQ_STATUS
-#define pDMA2_0_PERIPHERAL_MAP (volatile unsigned short *)DMA2_0_PERIPHERAL_MAP
-#define pDMA2_1_CONFIG (volatile unsigned short *)DMA2_1_CONFIG
-#define pDMA2_1_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_1_NEXT_DESC_PTR
-#define pDMA2_1_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_1_START_ADDR
-#define pDMA2_1_X_COUNT (volatile unsigned short *)DMA2_1_X_COUNT
-#define pDMA2_1_Y_COUNT (volatile unsigned short *)DMA2_1_Y_COUNT
+#define pDMA2_0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_0_CURR_DESC_PTR)
+#define pDMA2_0_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_0_CURR_ADDR)
+#define pDMA2_0_CURR_X_COUNT ((volatile unsigned short *)DMA2_0_CURR_X_COUNT)
+#define pDMA2_0_CURR_Y_COUNT ((volatile unsigned short *)DMA2_0_CURR_Y_COUNT)
+#define pDMA2_0_IRQ_STATUS ((volatile unsigned short *)DMA2_0_IRQ_STATUS)
+#define pDMA2_0_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_0_PERIPHERAL_MAP)
+#define pDMA2_1_CONFIG ((volatile unsigned short *)DMA2_1_CONFIG)
+#define pDMA2_1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_1_NEXT_DESC_PTR)
+#define pDMA2_1_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_1_START_ADDR)
+#define pDMA2_1_X_COUNT ((volatile unsigned short *)DMA2_1_X_COUNT)
+#define pDMA2_1_Y_COUNT ((volatile unsigned short *)DMA2_1_Y_COUNT)
#define pDMA2_1_X_MODIFY (volatile signed short *)DMA2_1_X_MODIFY
#define pDMA2_1_Y_MODIFY (volatile signed short *)DMA2_1_Y_MODIFY
-#define pDMA2_1_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_1_CURR_DESC_PTR
-#define pDMA2_1_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_1_CURR_ADDR
-#define pDMA2_1_CURR_X_COUNT (volatile unsigned short *)DMA2_1_CURR_X_COUNT
-#define pDMA2_1_CURR_Y_COUNT (volatile unsigned short *)DMA2_1_CURR_Y_COUNT
-#define pDMA2_1_IRQ_STATUS (volatile unsigned short *)DMA2_1_IRQ_STATUS
-#define pDMA2_1_PERIPHERAL_MAP (volatile unsigned short *)DMA2_1_PERIPHERAL_MAP
-#define pDMA2_2_CONFIG (volatile unsigned short *)DMA2_2_CONFIG
-#define pDMA2_2_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_2_NEXT_DESC_PTR
-#define pDMA2_2_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_2_START_ADDR
-#define pDMA2_2_X_COUNT (volatile unsigned short *)DMA2_2_X_COUNT
-#define pDMA2_2_Y_COUNT (volatile unsigned short *)DMA2_2_Y_COUNT
+#define pDMA2_1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_1_CURR_DESC_PTR)
+#define pDMA2_1_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_1_CURR_ADDR)
+#define pDMA2_1_CURR_X_COUNT ((volatile unsigned short *)DMA2_1_CURR_X_COUNT)
+#define pDMA2_1_CURR_Y_COUNT ((volatile unsigned short *)DMA2_1_CURR_Y_COUNT)
+#define pDMA2_1_IRQ_STATUS ((volatile unsigned short *)DMA2_1_IRQ_STATUS)
+#define pDMA2_1_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_1_PERIPHERAL_MAP)
+#define pDMA2_2_CONFIG ((volatile unsigned short *)DMA2_2_CONFIG)
+#define pDMA2_2_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_2_NEXT_DESC_PTR)
+#define pDMA2_2_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_2_START_ADDR)
+#define pDMA2_2_X_COUNT ((volatile unsigned short *)DMA2_2_X_COUNT)
+#define pDMA2_2_Y_COUNT ((volatile unsigned short *)DMA2_2_Y_COUNT)
#define pDMA2_2_X_MODIFY (volatile signed short *)DMA2_2_X_MODIFY
#define pDMA2_2_Y_MODIFY (volatile signed short *)DMA2_2_Y_MODIFY
-#define pDMA2_2_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_2_CURR_DESC_PTR
-#define pDMA2_2_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_2_CURR_ADDR
-#define pDMA2_2_CURR_X_COUNT (volatile unsigned short *)DMA2_2_CURR_X_COUNT
-#define pDMA2_2_CURR_Y_COUNT (volatile unsigned short *)DMA2_2_CURR_Y_COUNT
-#define pDMA2_2_IRQ_STATUS (volatile unsigned short *)DMA2_2_IRQ_STATUS
-#define pDMA2_2_PERIPHERAL_MAP (volatile unsigned short *)DMA2_2_PERIPHERAL_MAP
-#define pDMA2_3_CONFIG (volatile unsigned short *)DMA2_3_CONFIG
-#define pDMA2_3_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_3_NEXT_DESC_PTR
-#define pDMA2_3_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_3_START_ADDR
-#define pDMA2_3_X_COUNT (volatile unsigned short *)DMA2_3_X_COUNT
-#define pDMA2_3_Y_COUNT (volatile unsigned short *)DMA2_3_Y_COUNT
+#define pDMA2_2_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_2_CURR_DESC_PTR)
+#define pDMA2_2_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_2_CURR_ADDR)
+#define pDMA2_2_CURR_X_COUNT ((volatile unsigned short *)DMA2_2_CURR_X_COUNT)
+#define pDMA2_2_CURR_Y_COUNT ((volatile unsigned short *)DMA2_2_CURR_Y_COUNT)
+#define pDMA2_2_IRQ_STATUS ((volatile unsigned short *)DMA2_2_IRQ_STATUS)
+#define pDMA2_2_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_2_PERIPHERAL_MAP)
+#define pDMA2_3_CONFIG ((volatile unsigned short *)DMA2_3_CONFIG)
+#define pDMA2_3_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_3_NEXT_DESC_PTR)
+#define pDMA2_3_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_3_START_ADDR)
+#define pDMA2_3_X_COUNT ((volatile unsigned short *)DMA2_3_X_COUNT)
+#define pDMA2_3_Y_COUNT ((volatile unsigned short *)DMA2_3_Y_COUNT)
#define pDMA2_3_X_MODIFY (volatile signed short *)DMA2_3_X_MODIFY
#define pDMA2_3_Y_MODIFY (volatile signed short *)DMA2_3_Y_MODIFY
-#define pDMA2_3_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_3_CURR_DESC_PTR
-#define pDMA2_3_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_3_CURR_ADDR
-#define pDMA2_3_CURR_X_COUNT (volatile unsigned short *)DMA2_3_CURR_X_COUNT
-#define pDMA2_3_CURR_Y_COUNT (volatile unsigned short *)DMA2_3_CURR_Y_COUNT
-#define pDMA2_3_IRQ_STATUS (volatile unsigned short *)DMA2_3_IRQ_STATUS
-#define pDMA2_3_PERIPHERAL_MAP (volatile unsigned short *)DMA2_3_PERIPHERAL_MAP
-#define pDMA2_4_CONFIG (volatile unsigned short *)DMA2_4_CONFIG
-#define pDMA2_4_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_4_NEXT_DESC_PTR
-#define pDMA2_4_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_4_START_ADDR
-#define pDMA2_4_X_COUNT (volatile unsigned short *)DMA2_4_X_COUNT
-#define pDMA2_4_Y_COUNT (volatile unsigned short *)DMA2_4_Y_COUNT
+#define pDMA2_3_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_3_CURR_DESC_PTR)
+#define pDMA2_3_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_3_CURR_ADDR)
+#define pDMA2_3_CURR_X_COUNT ((volatile unsigned short *)DMA2_3_CURR_X_COUNT)
+#define pDMA2_3_CURR_Y_COUNT ((volatile unsigned short *)DMA2_3_CURR_Y_COUNT)
+#define pDMA2_3_IRQ_STATUS ((volatile unsigned short *)DMA2_3_IRQ_STATUS)
+#define pDMA2_3_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_3_PERIPHERAL_MAP)
+#define pDMA2_4_CONFIG ((volatile unsigned short *)DMA2_4_CONFIG)
+#define pDMA2_4_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_4_NEXT_DESC_PTR)
+#define pDMA2_4_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_4_START_ADDR)
+#define pDMA2_4_X_COUNT ((volatile unsigned short *)DMA2_4_X_COUNT)
+#define pDMA2_4_Y_COUNT ((volatile unsigned short *)DMA2_4_Y_COUNT)
#define pDMA2_4_X_MODIFY (volatile signed short *)DMA2_4_X_MODIFY
#define pDMA2_4_Y_MODIFY (volatile signed short *)DMA2_4_Y_MODIFY
-#define pDMA2_4_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_4_CURR_DESC_PTR
-#define pDMA2_4_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_4_CURR_ADDR
-#define pDMA2_4_CURR_X_COUNT (volatile unsigned short *)DMA2_4_CURR_X_COUNT
-#define pDMA2_4_CURR_Y_COUNT (volatile unsigned short *)DMA2_4_CURR_Y_COUNT
-#define pDMA2_4_IRQ_STATUS (volatile unsigned short *)DMA2_4_IRQ_STATUS
-#define pDMA2_4_PERIPHERAL_MAP (volatile unsigned short *)DMA2_4_PERIPHERAL_MAP
-#define pDMA2_5_CONFIG (volatile unsigned short *)DMA2_5_CONFIG
-#define pDMA2_5_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_5_NEXT_DESC_PTR
-#define pDMA2_5_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_5_START_ADDR
-#define pDMA2_5_X_COUNT (volatile unsigned short *)DMA2_5_X_COUNT
-#define pDMA2_5_Y_COUNT (volatile unsigned short *)DMA2_5_Y_COUNT
+#define pDMA2_4_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_4_CURR_DESC_PTR)
+#define pDMA2_4_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_4_CURR_ADDR)
+#define pDMA2_4_CURR_X_COUNT ((volatile unsigned short *)DMA2_4_CURR_X_COUNT)
+#define pDMA2_4_CURR_Y_COUNT ((volatile unsigned short *)DMA2_4_CURR_Y_COUNT)
+#define pDMA2_4_IRQ_STATUS ((volatile unsigned short *)DMA2_4_IRQ_STATUS)
+#define pDMA2_4_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_4_PERIPHERAL_MAP)
+#define pDMA2_5_CONFIG ((volatile unsigned short *)DMA2_5_CONFIG)
+#define pDMA2_5_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_5_NEXT_DESC_PTR)
+#define pDMA2_5_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_5_START_ADDR)
+#define pDMA2_5_X_COUNT ((volatile unsigned short *)DMA2_5_X_COUNT)
+#define pDMA2_5_Y_COUNT ((volatile unsigned short *)DMA2_5_Y_COUNT)
#define pDMA2_5_X_MODIFY (volatile signed short *)DMA2_5_X_MODIFY
#define pDMA2_5_Y_MODIFY (volatile signed short *)DMA2_5_Y_MODIFY
-#define pDMA2_5_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_5_CURR_DESC_PTR
-#define pDMA2_5_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_5_CURR_ADDR
-#define pDMA2_5_CURR_X_COUNT (volatile unsigned short *)DMA2_5_CURR_X_COUNT
-#define pDMA2_5_CURR_Y_COUNT (volatile unsigned short *)DMA2_5_CURR_Y_COUNT
-#define pDMA2_5_IRQ_STATUS (volatile unsigned short *)DMA2_5_IRQ_STATUS
-#define pDMA2_5_PERIPHERAL_MAP (volatile unsigned short *)DMA2_5_PERIPHERAL_MAP
-#define pDMA2_6_CONFIG (volatile unsigned short *)DMA2_6_CONFIG
-#define pDMA2_6_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_6_NEXT_DESC_PTR
-#define pDMA2_6_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_6_START_ADDR
-#define pDMA2_6_X_COUNT (volatile unsigned short *)DMA2_6_X_COUNT
-#define pDMA2_6_Y_COUNT (volatile unsigned short *)DMA2_6_Y_COUNT
+#define pDMA2_5_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_5_CURR_DESC_PTR)
+#define pDMA2_5_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_5_CURR_ADDR)
+#define pDMA2_5_CURR_X_COUNT ((volatile unsigned short *)DMA2_5_CURR_X_COUNT)
+#define pDMA2_5_CURR_Y_COUNT ((volatile unsigned short *)DMA2_5_CURR_Y_COUNT)
+#define pDMA2_5_IRQ_STATUS ((volatile unsigned short *)DMA2_5_IRQ_STATUS)
+#define pDMA2_5_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_5_PERIPHERAL_MAP)
+#define pDMA2_6_CONFIG ((volatile unsigned short *)DMA2_6_CONFIG)
+#define pDMA2_6_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_6_NEXT_DESC_PTR)
+#define pDMA2_6_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_6_START_ADDR)
+#define pDMA2_6_X_COUNT ((volatile unsigned short *)DMA2_6_X_COUNT)
+#define pDMA2_6_Y_COUNT ((volatile unsigned short *)DMA2_6_Y_COUNT)
#define pDMA2_6_X_MODIFY (volatile signed short *)DMA2_6_X_MODIFY
#define pDMA2_6_Y_MODIFY (volatile signed short *)DMA2_6_Y_MODIFY
-#define pDMA2_6_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_6_CURR_DESC_PTR
-#define pDMA2_6_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_6_CURR_ADDR
-#define pDMA2_6_CURR_X_COUNT (volatile unsigned short *)DMA2_6_CURR_X_COUNT
-#define pDMA2_6_CURR_Y_COUNT (volatile unsigned short *)DMA2_6_CURR_Y_COUNT
-#define pDMA2_6_IRQ_STATUS (volatile unsigned short *)DMA2_6_IRQ_STATUS
-#define pDMA2_6_PERIPHERAL_MAP (volatile unsigned short *)DMA2_6_PERIPHERAL_MAP
-#define pDMA2_7_CONFIG (volatile unsigned short *)DMA2_7_CONFIG
-#define pDMA2_7_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_7_NEXT_DESC_PTR
-#define pDMA2_7_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_7_START_ADDR
-#define pDMA2_7_X_COUNT (volatile unsigned short *)DMA2_7_X_COUNT
-#define pDMA2_7_Y_COUNT (volatile unsigned short *)DMA2_7_Y_COUNT
+#define pDMA2_6_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_6_CURR_DESC_PTR)
+#define pDMA2_6_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_6_CURR_ADDR)
+#define pDMA2_6_CURR_X_COUNT ((volatile unsigned short *)DMA2_6_CURR_X_COUNT)
+#define pDMA2_6_CURR_Y_COUNT ((volatile unsigned short *)DMA2_6_CURR_Y_COUNT)
+#define pDMA2_6_IRQ_STATUS ((volatile unsigned short *)DMA2_6_IRQ_STATUS)
+#define pDMA2_6_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_6_PERIPHERAL_MAP)
+#define pDMA2_7_CONFIG ((volatile unsigned short *)DMA2_7_CONFIG)
+#define pDMA2_7_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_7_NEXT_DESC_PTR)
+#define pDMA2_7_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_7_START_ADDR)
+#define pDMA2_7_X_COUNT ((volatile unsigned short *)DMA2_7_X_COUNT)
+#define pDMA2_7_Y_COUNT ((volatile unsigned short *)DMA2_7_Y_COUNT)
#define pDMA2_7_X_MODIFY (volatile signed short *)DMA2_7_X_MODIFY
#define pDMA2_7_Y_MODIFY (volatile signed short *)DMA2_7_Y_MODIFY
-#define pDMA2_7_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_7_CURR_DESC_PTR
-#define pDMA2_7_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_7_CURR_ADDR
-#define pDMA2_7_CURR_X_COUNT (volatile unsigned short *)DMA2_7_CURR_X_COUNT
-#define pDMA2_7_CURR_Y_COUNT (volatile unsigned short *)DMA2_7_CURR_Y_COUNT
-#define pDMA2_7_IRQ_STATUS (volatile unsigned short *)DMA2_7_IRQ_STATUS
-#define pDMA2_7_PERIPHERAL_MAP (volatile unsigned short *)DMA2_7_PERIPHERAL_MAP
-#define pDMA2_8_CONFIG (volatile unsigned short *)DMA2_8_CONFIG
-#define pDMA2_8_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_8_NEXT_DESC_PTR
-#define pDMA2_8_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_8_START_ADDR
-#define pDMA2_8_X_COUNT (volatile unsigned short *)DMA2_8_X_COUNT
-#define pDMA2_8_Y_COUNT (volatile unsigned short *)DMA2_8_Y_COUNT
+#define pDMA2_7_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_7_CURR_DESC_PTR)
+#define pDMA2_7_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_7_CURR_ADDR)
+#define pDMA2_7_CURR_X_COUNT ((volatile unsigned short *)DMA2_7_CURR_X_COUNT)
+#define pDMA2_7_CURR_Y_COUNT ((volatile unsigned short *)DMA2_7_CURR_Y_COUNT)
+#define pDMA2_7_IRQ_STATUS ((volatile unsigned short *)DMA2_7_IRQ_STATUS)
+#define pDMA2_7_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_7_PERIPHERAL_MAP)
+#define pDMA2_8_CONFIG ((volatile unsigned short *)DMA2_8_CONFIG)
+#define pDMA2_8_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_8_NEXT_DESC_PTR)
+#define pDMA2_8_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_8_START_ADDR)
+#define pDMA2_8_X_COUNT ((volatile unsigned short *)DMA2_8_X_COUNT)
+#define pDMA2_8_Y_COUNT ((volatile unsigned short *)DMA2_8_Y_COUNT)
#define pDMA2_8_X_MODIFY (volatile signed short *)DMA2_8_X_MODIFY
#define pDMA2_8_Y_MODIFY (volatile signed short *)DMA2_8_Y_MODIFY
-#define pDMA2_8_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_8_CURR_DESC_PTR
-#define pDMA2_8_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_8_CURR_ADDR
-#define pDMA2_8_CURR_X_COUNT (volatile unsigned short *)DMA2_8_CURR_X_COUNT
-#define pDMA2_8_CURR_Y_COUNT (volatile unsigned short *)DMA2_8_CURR_Y_COUNT
-#define pDMA2_8_IRQ_STATUS (volatile unsigned short *)DMA2_8_IRQ_STATUS
-#define pDMA2_8_PERIPHERAL_MAP (volatile unsigned short *)DMA2_8_PERIPHERAL_MAP
-#define pDMA2_9_CONFIG (volatile unsigned short *)DMA2_9_CONFIG
-#define pDMA2_9_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_9_NEXT_DESC_PTR
-#define pDMA2_9_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_9_START_ADDR
-#define pDMA2_9_X_COUNT (volatile unsigned short *)DMA2_9_X_COUNT
-#define pDMA2_9_Y_COUNT (volatile unsigned short *)DMA2_9_Y_COUNT
+#define pDMA2_8_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_8_CURR_DESC_PTR)
+#define pDMA2_8_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_8_CURR_ADDR)
+#define pDMA2_8_CURR_X_COUNT ((volatile unsigned short *)DMA2_8_CURR_X_COUNT)
+#define pDMA2_8_CURR_Y_COUNT ((volatile unsigned short *)DMA2_8_CURR_Y_COUNT)
+#define pDMA2_8_IRQ_STATUS ((volatile unsigned short *)DMA2_8_IRQ_STATUS)
+#define pDMA2_8_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_8_PERIPHERAL_MAP)
+#define pDMA2_9_CONFIG ((volatile unsigned short *)DMA2_9_CONFIG)
+#define pDMA2_9_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_9_NEXT_DESC_PTR)
+#define pDMA2_9_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_9_START_ADDR)
+#define pDMA2_9_X_COUNT ((volatile unsigned short *)DMA2_9_X_COUNT)
+#define pDMA2_9_Y_COUNT ((volatile unsigned short *)DMA2_9_Y_COUNT)
#define pDMA2_9_X_MODIFY (volatile signed short *)DMA2_9_X_MODIFY
#define pDMA2_9_Y_MODIFY (volatile signed short *)DMA2_9_Y_MODIFY
-#define pDMA2_9_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_9_CURR_DESC_PTR
-#define pDMA2_9_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_9_CURR_ADDR
-#define pDMA2_9_CURR_X_COUNT (volatile unsigned short *)DMA2_9_CURR_X_COUNT
-#define pDMA2_9_CURR_Y_COUNT (volatile unsigned short *)DMA2_9_CURR_Y_COUNT
-#define pDMA2_9_IRQ_STATUS (volatile unsigned short *)DMA2_9_IRQ_STATUS
-#define pDMA2_9_PERIPHERAL_MAP (volatile unsigned short *)DMA2_9_PERIPHERAL_MAP
-#define pDMA2_10_CONFIG (volatile unsigned short *)DMA2_10_CONFIG
-#define pDMA2_10_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_10_NEXT_DESC_PTR
-#define pDMA2_10_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_10_START_ADDR
-#define pDMA2_10_X_COUNT (volatile unsigned short *)DMA2_10_X_COUNT
-#define pDMA2_10_Y_COUNT (volatile unsigned short *)DMA2_10_Y_COUNT
+#define pDMA2_9_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_9_CURR_DESC_PTR)
+#define pDMA2_9_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_9_CURR_ADDR)
+#define pDMA2_9_CURR_X_COUNT ((volatile unsigned short *)DMA2_9_CURR_X_COUNT)
+#define pDMA2_9_CURR_Y_COUNT ((volatile unsigned short *)DMA2_9_CURR_Y_COUNT)
+#define pDMA2_9_IRQ_STATUS ((volatile unsigned short *)DMA2_9_IRQ_STATUS)
+#define pDMA2_9_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_9_PERIPHERAL_MAP)
+#define pDMA2_10_CONFIG ((volatile unsigned short *)DMA2_10_CONFIG)
+#define pDMA2_10_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_10_NEXT_DESC_PTR)
+#define pDMA2_10_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_10_START_ADDR)
+#define pDMA2_10_X_COUNT ((volatile unsigned short *)DMA2_10_X_COUNT)
+#define pDMA2_10_Y_COUNT ((volatile unsigned short *)DMA2_10_Y_COUNT)
#define pDMA2_10_X_MODIFY (volatile signed short *)DMA2_10_X_MODIFY
#define pDMA2_10_Y_MODIFY (volatile signed short *)DMA2_10_Y_MODIFY
-#define pDMA2_10_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_10_CURR_DESC_PTR
-#define pDMA2_10_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_10_CURR_ADDR
-#define pDMA2_10_CURR_X_COUNT (volatile unsigned short *)DMA2_10_CURR_X_COUNT
-#define pDMA2_10_CURR_Y_COUNT (volatile unsigned short *)DMA2_10_CURR_Y_COUNT
-#define pDMA2_10_IRQ_STATUS (volatile unsigned short *)DMA2_10_IRQ_STATUS
-#define pDMA2_10_PERIPHERAL_MAP (volatile unsigned short *)DMA2_10_PERIPHERAL_MAP
-#define pDMA2_11_CONFIG (volatile unsigned short *)DMA2_11_CONFIG
-#define pDMA2_11_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_11_NEXT_DESC_PTR
-#define pDMA2_11_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_11_START_ADDR
-#define pDMA2_11_X_COUNT (volatile unsigned short *)DMA2_11_X_COUNT
-#define pDMA2_11_Y_COUNT (volatile unsigned short *)DMA2_11_Y_COUNT
+#define pDMA2_10_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_10_CURR_DESC_PTR)
+#define pDMA2_10_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_10_CURR_ADDR)
+#define pDMA2_10_CURR_X_COUNT ((volatile unsigned short *)DMA2_10_CURR_X_COUNT)
+#define pDMA2_10_CURR_Y_COUNT ((volatile unsigned short *)DMA2_10_CURR_Y_COUNT)
+#define pDMA2_10_IRQ_STATUS ((volatile unsigned short *)DMA2_10_IRQ_STATUS)
+#define pDMA2_10_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_10_PERIPHERAL_MAP)
+#define pDMA2_11_CONFIG ((volatile unsigned short *)DMA2_11_CONFIG)
+#define pDMA2_11_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_11_NEXT_DESC_PTR)
+#define pDMA2_11_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_11_START_ADDR)
+#define pDMA2_11_X_COUNT ((volatile unsigned short *)DMA2_11_X_COUNT)
+#define pDMA2_11_Y_COUNT ((volatile unsigned short *)DMA2_11_Y_COUNT)
#define pDMA2_11_X_MODIFY (volatile signed short *)DMA2_11_X_MODIFY
#define pDMA2_11_Y_MODIFY (volatile signed short *)DMA2_11_Y_MODIFY
-#define pDMA2_11_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_11_CURR_DESC_PTR
-#define pDMA2_11_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_11_CURR_ADDR
-#define pDMA2_11_CURR_X_COUNT (volatile unsigned short *)DMA2_11_CURR_X_COUNT
-#define pDMA2_11_CURR_Y_COUNT (volatile unsigned short *)DMA2_11_CURR_Y_COUNT
-#define pDMA2_11_IRQ_STATUS (volatile unsigned short *)DMA2_11_IRQ_STATUS
-#define pDMA2_11_PERIPHERAL_MAP (volatile unsigned short *)DMA2_11_PERIPHERAL_MAP
+#define pDMA2_11_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_11_CURR_DESC_PTR)
+#define pDMA2_11_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_11_CURR_ADDR)
+#define pDMA2_11_CURR_X_COUNT ((volatile unsigned short *)DMA2_11_CURR_X_COUNT)
+#define pDMA2_11_CURR_Y_COUNT ((volatile unsigned short *)DMA2_11_CURR_Y_COUNT)
+#define pDMA2_11_IRQ_STATUS ((volatile unsigned short *)DMA2_11_IRQ_STATUS)
+#define pDMA2_11_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_11_PERIPHERAL_MAP)
/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
-#define pMDMA2_D0_CONFIG (volatile unsigned short *)MDMA2_D0_CONFIG
-#define pMDMA2_D0_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA2_D0_NEXT_DESC_PTR
-#define pMDMA2_D0_START_ADDR _PTR_TO_VOL_VOID_PTR MDMA2_D0_START_ADDR
-#define pMDMA2_D0_X_COUNT (volatile unsigned short *)MDMA2_D0_X_COUNT
-#define pMDMA2_D0_Y_COUNT (volatile unsigned short *)MDMA2_D0_Y_COUNT
+#define pMDMA2_D0_CONFIG ((volatile unsigned short *)MDMA2_D0_CONFIG)
+#define pMDMA2_D0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA2_D0_NEXT_DESC_PTR)
+#define pMDMA2_D0_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA2_D0_START_ADDR)
+#define pMDMA2_D0_X_COUNT ((volatile unsigned short *)MDMA2_D0_X_COUNT)
+#define pMDMA2_D0_Y_COUNT ((volatile unsigned short *)MDMA2_D0_Y_COUNT)
#define pMDMA2_D0_X_MODIFY (volatile signed short *)MDMA2_D0_X_MODIFY
#define pMDMA2_D0_Y_MODIFY (volatile signed short *)MDMA2_D0_Y_MODIFY
-#define pMDMA2_D0_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA2_D0_CURR_DESC_PTR
-#define pMDMA2_D0_CURR_ADDR _PTR_TO_VOL_VOID_PTR MDMA2_D0_CURR_ADDR
-#define pMDMA2_D0_CURR_X_COUNT (volatile unsigned short *)MDMA2_D0_CURR_X_COUNT
-#define pMDMA2_D0_CURR_Y_COUNT (volatile unsigned short *)MDMA2_D0_CURR_Y_COUNT
-#define pMDMA2_D0_IRQ_STATUS (volatile unsigned short *)MDMA2_D0_IRQ_STATUS
-#define pMDMA2_D0_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_D0_PERIPHERAL_MAP
-#define pMDMA2_S0_CONFIG (volatile unsigned short *)MDMA2_S0_CONFIG
-#define pMDMA2_S0_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA2_S0_NEXT_DESC_PTR
-#define pMDMA2_S0_START_ADDR _PTR_TO_VOL_VOID_PTR MDMA2_S0_START_ADDR
-#define pMDMA2_S0_X_COUNT (volatile unsigned short *)MDMA2_S0_X_COUNT
-#define pMDMA2_S0_Y_COUNT (volatile unsigned short *)MDMA2_S0_Y_COUNT
+#define pMDMA2_D0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA2_D0_CURR_DESC_PTR)
+#define pMDMA2_D0_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA2_D0_CURR_ADDR)
+#define pMDMA2_D0_CURR_X_COUNT ((volatile unsigned short *)MDMA2_D0_CURR_X_COUNT)
+#define pMDMA2_D0_CURR_Y_COUNT ((volatile unsigned short *)MDMA2_D0_CURR_Y_COUNT)
+#define pMDMA2_D0_IRQ_STATUS ((volatile unsigned short *)MDMA2_D0_IRQ_STATUS)
+#define pMDMA2_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA2_D0_PERIPHERAL_MAP)
+#define pMDMA2_S0_CONFIG ((volatile unsigned short *)MDMA2_S0_CONFIG)
+#define pMDMA2_S0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA2_S0_NEXT_DESC_PTR)
+#define pMDMA2_S0_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA2_S0_START_ADDR)
+#define pMDMA2_S0_X_COUNT ((volatile unsigned short *)MDMA2_S0_X_COUNT)
+#define pMDMA2_S0_Y_COUNT ((volatile unsigned short *)MDMA2_S0_Y_COUNT)
#define pMDMA2_S0_X_MODIFY (volatile signed short *)MDMA2_S0_X_MODIFY
#define pMDMA2_S0_Y_MODIFY (volatile signed short *)MDMA2_S0_Y_MODIFY
-#define pMDMA2_S0_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA2_S0_CURR_DESC_PTR
-#define pMDMA2_S0_CURR_ADDR _PTR_TO_VOL_VOID_PTR MDMA2_S0_CURR_ADDR
-#define pMDMA2_S0_CURR_X_COUNT (volatile unsigned short *)MDMA2_S0_CURR_X_COUNT
-#define pMDMA2_S0_CURR_Y_COUNT (volatile unsigned short *)MDMA2_S0_CURR_Y_COUNT
-#define pMDMA2_S0_IRQ_STATUS (volatile unsigned short *)MDMA2_S0_IRQ_STATUS
-#define pMDMA2_S0_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_S0_PERIPHERAL_MAP
-#define pMDMA2_D1_CONFIG (volatile unsigned short *)MDMA2_D1_CONFIG
-#define pMDMA2_D1_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA2_D1_NEXT_DESC_PTR
-#define pMDMA2_D1_START_ADDR _PTR_TO_VOL_VOID_PTR MDMA2_D1_START_ADDR
-#define pMDMA2_D1_X_COUNT (volatile unsigned short *)MDMA2_D1_X_COUNT
-#define pMDMA2_D1_Y_COUNT (volatile unsigned short *)MDMA2_D1_Y_COUNT
+#define pMDMA2_S0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA2_S0_CURR_DESC_PTR)
+#define pMDMA2_S0_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA2_S0_CURR_ADDR)
+#define pMDMA2_S0_CURR_X_COUNT ((volatile unsigned short *)MDMA2_S0_CURR_X_COUNT)
+#define pMDMA2_S0_CURR_Y_COUNT ((volatile unsigned short *)MDMA2_S0_CURR_Y_COUNT)
+#define pMDMA2_S0_IRQ_STATUS ((volatile unsigned short *)MDMA2_S0_IRQ_STATUS)
+#define pMDMA2_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA2_S0_PERIPHERAL_MAP)
+#define pMDMA2_D1_CONFIG ((volatile unsigned short *)MDMA2_D1_CONFIG)
+#define pMDMA2_D1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA2_D1_NEXT_DESC_PTR)
+#define pMDMA2_D1_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA2_D1_START_ADDR)
+#define pMDMA2_D1_X_COUNT ((volatile unsigned short *)MDMA2_D1_X_COUNT)
+#define pMDMA2_D1_Y_COUNT ((volatile unsigned short *)MDMA2_D1_Y_COUNT)
#define pMDMA2_D1_X_MODIFY (volatile signed short *)MDMA2_D1_X_MODIFY
#define pMDMA2_D1_Y_MODIFY (volatile signed short *)MDMA2_D1_Y_MODIFY
-#define pMDMA2_D1_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA2_D1_CURR_DESC_PTR
-#define pMDMA2_D1_CURR_ADDR _PTR_TO_VOL_VOID_PTR MDMA2_D1_CURR_ADDR
-#define pMDMA2_D1_CURR_X_COUNT (volatile unsigned short *)MDMA2_D1_CURR_X_COUNT
-#define pMDMA2_D1_CURR_Y_COUNT (volatile unsigned short *)MDMA2_D1_CURR_Y_COUNT
-#define pMDMA2_D1_IRQ_STATUS (volatile unsigned short *)MDMA2_D1_IRQ_STATUS
-#define pMDMA2_D1_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_D1_PERIPHERAL_MAP
-#define pMDMA2_S1_CONFIG (volatile unsigned short *)MDMA2_S1_CONFIG
-#define pMDMA2_S1_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA2_S1_NEXT_DESC_PTR
-#define pMDMA2_S1_START_ADDR _PTR_TO_VOL_VOID_PTR MDMA2_S1_START_ADDR
-#define pMDMA2_S1_X_COUNT (volatile unsigned short *)MDMA2_S1_X_COUNT
-#define pMDMA2_S1_Y_COUNT (volatile unsigned short *)MDMA2_S1_Y_COUNT
+#define pMDMA2_D1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA2_D1_CURR_DESC_PTR)
+#define pMDMA2_D1_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA2_D1_CURR_ADDR)
+#define pMDMA2_D1_CURR_X_COUNT ((volatile unsigned short *)MDMA2_D1_CURR_X_COUNT)
+#define pMDMA2_D1_CURR_Y_COUNT ((volatile unsigned short *)MDMA2_D1_CURR_Y_COUNT)
+#define pMDMA2_D1_IRQ_STATUS ((volatile unsigned short *)MDMA2_D1_IRQ_STATUS)
+#define pMDMA2_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA2_D1_PERIPHERAL_MAP)
+#define pMDMA2_S1_CONFIG ((volatile unsigned short *)MDMA2_S1_CONFIG)
+#define pMDMA2_S1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA2_S1_NEXT_DESC_PTR)
+#define pMDMA2_S1_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA2_S1_START_ADDR)
+#define pMDMA2_S1_X_COUNT ((volatile unsigned short *)MDMA2_S1_X_COUNT)
+#define pMDMA2_S1_Y_COUNT ((volatile unsigned short *)MDMA2_S1_Y_COUNT)
#define pMDMA2_S1_X_MODIFY (volatile signed short *)MDMA2_S1_X_MODIFY
#define pMDMA2_S1_Y_MODIFY (volatile signed short *)MDMA2_S1_Y_MODIFY
-#define pMDMA2_S1_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA2_S1_CURR_DESC_PTR
-#define pMDMA2_S1_CURR_ADDR _PTR_TO_VOL_VOID_PTR MDMA2_S1_CURR_ADDR
-#define pMDMA2_S1_CURR_X_COUNT (volatile unsigned short *)MDMA2_S1_CURR_X_COUNT
-#define pMDMA2_S1_CURR_Y_COUNT (volatile unsigned short *)MDMA2_S1_CURR_Y_COUNT
-#define pMDMA2_S1_IRQ_STATUS (volatile unsigned short *)MDMA2_S1_IRQ_STATUS
-#define pMDMA2_S1_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_S1_PERIPHERAL_MAP
+#define pMDMA2_S1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA2_S1_CURR_DESC_PTR)
+#define pMDMA2_S1_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA2_S1_CURR_ADDR)
+#define pMDMA2_S1_CURR_X_COUNT ((volatile unsigned short *)MDMA2_S1_CURR_X_COUNT)
+#define pMDMA2_S1_CURR_Y_COUNT ((volatile unsigned short *)MDMA2_S1_CURR_Y_COUNT)
+#define pMDMA2_S1_IRQ_STATUS ((volatile unsigned short *)MDMA2_S1_IRQ_STATUS)
+#define pMDMA2_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA2_S1_PERIPHERAL_MAP)
/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
-#define pIMDMA_D0_CONFIG (volatile unsigned short *)IMDMA_D0_CONFIG
-#define pIMDMA_D0_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR IMDMA_D0_NEXT_DESC_PTR
-#define pIMDMA_D0_START_ADDR _PTR_TO_VOL_VOID_PTR IMDMA_D0_START_ADDR
-#define pIMDMA_D0_X_COUNT (volatile unsigned short *)IMDMA_D0_X_COUNT
-#define pIMDMA_D0_Y_COUNT (volatile unsigned short *)IMDMA_D0_Y_COUNT
+#define pIMDMA_D0_CONFIG ((volatile unsigned short *)IMDMA_D0_CONFIG)
+#define pIMDMA_D0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR IMDMA_D0_NEXT_DESC_PTR)
+#define pIMDMA_D0_START_ADDR (_PTR_TO_VOL_VOID_PTR IMDMA_D0_START_ADDR)
+#define pIMDMA_D0_X_COUNT ((volatile unsigned short *)IMDMA_D0_X_COUNT)
+#define pIMDMA_D0_Y_COUNT ((volatile unsigned short *)IMDMA_D0_Y_COUNT)
#define pIMDMA_D0_X_MODIFY (volatile signed short *)IMDMA_D0_X_MODIFY
#define pIMDMA_D0_Y_MODIFY (volatile signed short *)IMDMA_D0_Y_MODIFY
-#define pIMDMA_D0_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR IMDMA_D0_CURR_DESC_PTR
-#define pIMDMA_D0_CURR_ADDR _PTR_TO_VOL_VOID_PTR IMDMA_D0_CURR_ADDR
-#define pIMDMA_D0_CURR_X_COUNT (volatile unsigned short *)IMDMA_D0_CURR_X_COUNT
-#define pIMDMA_D0_CURR_Y_COUNT (volatile unsigned short *)IMDMA_D0_CURR_Y_COUNT
-#define pIMDMA_D0_IRQ_STATUS (volatile unsigned short *)IMDMA_D0_IRQ_STATUS
-#define pIMDMA_S0_CONFIG (volatile unsigned short *)IMDMA_S0_CONFIG
-#define pIMDMA_S0_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR IMDMA_S0_NEXT_DESC_PTR
-#define pIMDMA_S0_START_ADDR _PTR_TO_VOL_VOID_PTR IMDMA_S0_START_ADDR
-#define pIMDMA_S0_X_COUNT (volatile unsigned short *)IMDMA_S0_X_COUNT
-#define pIMDMA_S0_Y_COUNT (volatile unsigned short *)IMDMA_S0_Y_COUNT
+#define pIMDMA_D0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR IMDMA_D0_CURR_DESC_PTR)
+#define pIMDMA_D0_CURR_ADDR (_PTR_TO_VOL_VOID_PTR IMDMA_D0_CURR_ADDR)
+#define pIMDMA_D0_CURR_X_COUNT ((volatile unsigned short *)IMDMA_D0_CURR_X_COUNT)
+#define pIMDMA_D0_CURR_Y_COUNT ((volatile unsigned short *)IMDMA_D0_CURR_Y_COUNT)
+#define pIMDMA_D0_IRQ_STATUS ((volatile unsigned short *)IMDMA_D0_IRQ_STATUS)
+#define pIMDMA_S0_CONFIG ((volatile unsigned short *)IMDMA_S0_CONFIG)
+#define pIMDMA_S0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR IMDMA_S0_NEXT_DESC_PTR)
+#define pIMDMA_S0_START_ADDR (_PTR_TO_VOL_VOID_PTR IMDMA_S0_START_ADDR)
+#define pIMDMA_S0_X_COUNT ((volatile unsigned short *)IMDMA_S0_X_COUNT)
+#define pIMDMA_S0_Y_COUNT ((volatile unsigned short *)IMDMA_S0_Y_COUNT)
#define pIMDMA_S0_X_MODIFY (volatile signed short *)IMDMA_S0_X_MODIFY
#define pIMDMA_S0_Y_MODIFY (volatile signed short *)IMDMA_S0_Y_MODIFY
-#define pIMDMA_S0_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR IMDMA_S0_CURR_DESC_PTR
-#define pIMDMA_S0_CURR_ADDR _PTR_TO_VOL_VOID_PTR IMDMA_S0_CURR_ADDR
-#define pIMDMA_S0_CURR_X_COUNT (volatile unsigned short *)IMDMA_S0_CURR_X_COUNT
-#define pIMDMA_S0_CURR_Y_COUNT (volatile unsigned short *)IMDMA_S0_CURR_Y_COUNT
-#define pIMDMA_S0_IRQ_STATUS (volatile unsigned short *)IMDMA_S0_IRQ_STATUS
-#define pIMDMA_D1_CONFIG (volatile unsigned short *)IMDMA_D1_CONFIG
-#define pIMDMA_D1_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR IMDMA_D1_NEXT_DESC_PTR
-#define pIMDMA_D1_START_ADDR _PTR_TO_VOL_VOID_PTR IMDMA_D1_START_ADDR
-#define pIMDMA_D1_X_COUNT (volatile unsigned short *)IMDMA_D1_X_COUNT
-#define pIMDMA_D1_Y_COUNT (volatile unsigned short *)IMDMA_D1_Y_COUNT
+#define pIMDMA_S0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR IMDMA_S0_CURR_DESC_PTR)
+#define pIMDMA_S0_CURR_ADDR (_PTR_TO_VOL_VOID_PTR IMDMA_S0_CURR_ADDR)
+#define pIMDMA_S0_CURR_X_COUNT ((volatile unsigned short *)IMDMA_S0_CURR_X_COUNT)
+#define pIMDMA_S0_CURR_Y_COUNT ((volatile unsigned short *)IMDMA_S0_CURR_Y_COUNT)
+#define pIMDMA_S0_IRQ_STATUS ((volatile unsigned short *)IMDMA_S0_IRQ_STATUS)
+#define pIMDMA_D1_CONFIG ((volatile unsigned short *)IMDMA_D1_CONFIG)
+#define pIMDMA_D1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR IMDMA_D1_NEXT_DESC_PTR)
+#define pIMDMA_D1_START_ADDR (_PTR_TO_VOL_VOID_PTR IMDMA_D1_START_ADDR)
+#define pIMDMA_D1_X_COUNT ((volatile unsigned short *)IMDMA_D1_X_COUNT)
+#define pIMDMA_D1_Y_COUNT ((volatile unsigned short *)IMDMA_D1_Y_COUNT)
#define pIMDMA_D1_X_MODIFY (volatile signed short *)IMDMA_D1_X_MODIFY
#define pIMDMA_D1_Y_MODIFY (volatile signed short *)IMDMA_D1_Y_MODIFY
-#define pIMDMA_D1_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR IMDMA_D1_CURR_DESC_PTR
-#define pIMDMA_D1_CURR_ADDR _PTR_TO_VOL_VOID_PTR IMDMA_D1_CURR_ADDR
-#define pIMDMA_D1_CURR_X_COUNT (volatile unsigned short *)IMDMA_D1_CURR_X_COUNT
-#define pIMDMA_D1_CURR_Y_COUNT (volatile unsigned short *)IMDMA_D1_CURR_Y_COUNT
-#define pIMDMA_D1_IRQ_STATUS (volatile unsigned short *)IMDMA_D1_IRQ_STATUS
-#define pIMDMA_S1_CONFIG (volatile unsigned short *)IMDMA_S1_CONFIG
-#define pIMDMA_S1_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR IMDMA_S1_NEXT_DESC_PTR
-#define pIMDMA_S1_START_ADDR _PTR_TO_VOL_VOID_PTR IMDMA_S1_START_ADDR
-#define pIMDMA_S1_X_COUNT (volatile unsigned short *)IMDMA_S1_X_COUNT
-#define pIMDMA_S1_Y_COUNT (volatile unsigned short *)IMDMA_S1_Y_COUNT
+#define pIMDMA_D1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR IMDMA_D1_CURR_DESC_PTR)
+#define pIMDMA_D1_CURR_ADDR (_PTR_TO_VOL_VOID_PTR IMDMA_D1_CURR_ADDR)
+#define pIMDMA_D1_CURR_X_COUNT ((volatile unsigned short *)IMDMA_D1_CURR_X_COUNT)
+#define pIMDMA_D1_CURR_Y_COUNT ((volatile unsigned short *)IMDMA_D1_CURR_Y_COUNT)
+#define pIMDMA_D1_IRQ_STATUS ((volatile unsigned short *)IMDMA_D1_IRQ_STATUS)
+#define pIMDMA_S1_CONFIG ((volatile unsigned short *)IMDMA_S1_CONFIG)
+#define pIMDMA_S1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR IMDMA_S1_NEXT_DESC_PTR)
+#define pIMDMA_S1_START_ADDR (_PTR_TO_VOL_VOID_PTR IMDMA_S1_START_ADDR)
+#define pIMDMA_S1_X_COUNT ((volatile unsigned short *)IMDMA_S1_X_COUNT)
+#define pIMDMA_S1_Y_COUNT ((volatile unsigned short *)IMDMA_S1_Y_COUNT)
#define pIMDMA_S1_X_MODIFY (volatile signed short *)IMDMA_S1_X_MODIFY
#define pIMDMA_S1_Y_MODIFY (volatile signed short *)IMDMA_S1_Y_MODIFY
-#define pIMDMA_S1_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR IMDMA_S1_CURR_DESC_PTR
-#define pIMDMA_S1_CURR_ADDR _PTR_TO_VOL_VOID_PTR IMDMA_S1_CURR_ADDR
-#define pIMDMA_S1_CURR_X_COUNT (volatile unsigned short *)IMDMA_S1_CURR_X_COUNT
-#define pIMDMA_S1_CURR_Y_COUNT (volatile unsigned short *)IMDMA_S1_CURR_Y_COUNT
-#define pIMDMA_S1_IRQ_STATUS (volatile unsigned short *)IMDMA_S1_IRQ_STATUS
+#define pIMDMA_S1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR IMDMA_S1_CURR_DESC_PTR)
+#define pIMDMA_S1_CURR_ADDR (_PTR_TO_VOL_VOID_PTR IMDMA_S1_CURR_ADDR)
+#define pIMDMA_S1_CURR_X_COUNT ((volatile unsigned short *)IMDMA_S1_CURR_X_COUNT)
+#define pIMDMA_S1_CURR_Y_COUNT ((volatile unsigned short *)IMDMA_S1_CURR_Y_COUNT)
+#define pIMDMA_S1_IRQ_STATUS ((volatile unsigned short *)IMDMA_S1_IRQ_STATUS)
+
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
#endif /* _CDEF_BF561_H */
*
* cdef_LPBlackfin.h
*
- * Copyright (C) 2008 Analog Devices, Inc.
+ * Copyright (C) 2008, 2009 Analog Devices, Inc.
*
************************************************************************/
#endif
#include <def_LPBlackfin.h>
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
+#endif /* _MISRA_RULES */
+
#ifndef _PTR_TO_VOL_VOID_PTR
#ifndef _USE_LEGACY_CDEF_BEHAVIOUR
#define _PTR_TO_VOL_VOID_PTR (void * volatile *)
#define pPFCNTR0 ((volatile unsigned long *)PFCNTR0)
#define pPFCNTR1 ((volatile unsigned long *)PFCNTR1)
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
#endif /* _CDEF_LPBLACKFIN_H */
*
* cdefblackfin.h
*
- * Copyright (C) 2008 Analog Devices, Inc.
+ * Copyright (C) 2008, 2009 Analog Devices, Inc.
*
************************************************************************/
#endif
#include <defblackfin.h>
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
+#endif /* _MISRA_RULES */
+
#ifndef _PTR_TO_VOL_VOID_PTR
#ifndef _USE_LEGACY_CDEF_BEHAVIOUR
#define _PTR_TO_VOL_VOID_PTR (void * volatile *)
#define pPFCNTR0 ((volatile unsigned long *)PFCNTR0)
#define pPFCNTR1 ((volatile unsigned long *)PFCNTR1)
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
#endif /* _CDEF_BLACKFIN_H */
*
* cplb.h
*
- * Copyright (C) 2008 Analog Devices, Inc.
+ * Copyright (C) 2008, 2009 Analog Devices, Inc.
*
************************************************************************/
#define CPLB_EVT_DCPLB_MISS 1
#define CPLB_EVT_DCPLB_WRITE 2
+/* size of cplb tables */
+#define __CPLB_TABLE_SIZE 16
+
#ifdef _MISRA_RULES
#pragma diag(pop)
#endif /* _MISRA_RULES */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** Copyright (C) 2009 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for register-access and bit-manipulation.
+**
+**/
+#ifndef _DEF_BF512_H
+#define _DEF_BF512_H
+
+/* Include all Core registers and bit definitions */
+#include <def_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF512 */
+
+/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
+#include <defBF51x_base.h>
+
+#endif /* _DEF_BF512_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** Copyright (C) 2009 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for register-access and bit-manipulation.
+**
+**/
+#ifndef _DEF_BF514_H
+#define _DEF_BF514_H
+
+/* Include all Core registers and bit definitions */
+#include <def_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */
+
+/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
+#include <defBF51x_base.h>
+
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"macros violate rule 19.4")
+#endif /* _MISRA_RULES */
+
+/* The following are the #defines needed by ADSP-BF514 that are not in the common header */
+
+/* RSI Registers */
+
+#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_PWR_CTL RSI_PWR_CONTROL /* SDH Power Control */
+#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_CLK_CTL RSI_CLK_CONTROL /* SDH Clock Control */
+#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_ARGUMENT RSI_ARGUMENT /* SDH Argument */
+#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_COMMAND RSI_COMMAND /* SDH Command */
+#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_RESP_CMD RSI_RESP_CMD /* SDH Response Command */
+#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_RESPONSE0 RSI_RESPONSE0 /* SDH Response0 */
+#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_RESPONSE1 RSI_RESPONSE1 /* SDH Response1 */
+#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_RESPONSE2 RSI_RESPONSE2 /* SDH Response2 */
+#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_RESPONSE3 RSI_RESPONSE3 /* SDH Response3 */
+#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_DATA_TIMER RSI_DATA_TIMER /* SDH Data Timer */
+#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_DATA_LGTH RSI_DATA_LGTH /* SDH Data Length */
+#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_DATA_CTL RSI_DATA_CONTROL /* SDH Data Control */
+#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_DATA_CNT RSI_DATA_CNT /* SDH Data Counter */
+#define RSI_STATUS 0xFFC03834 /* RSI Status Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_STATUS RSI_STATUS /* SDH Status */
+#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_STATUS_CLR RSI_STATUSCL /* SDH Status Clear */
+#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_MASK0 RSI_MASK0 /* SDH Interrupt0 Mask */
+#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_MASK1 RSI_MASK1 /* SDH Interrupt1 Mask */
+#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_FIFO_CNT RSI_FIFO_CNT /* SDH FIFO Counter */
+#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */
+#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_FIFO RSI_FIFO /* SDH Data FIFO */
+#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_E_STATUS RSI_ESTAT /* SDH Exception Status */
+#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_E_MASK RSI_EMASK /* SDH Exception Mask */
+#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_CFG RSI_CONFIG /* SDH Configuration */
+#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_RD_WAIT_EN RSI_RD_WAIT_EN /* SDH Read Wait Enable */
+#define RSI_PID0 0xFFC038D0 /* RSI Peripheral ID Register 0 */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_PID0 RSI_PID0 /* SDH Peripheral Identification0 */
+#define RSI_PID1 0xFFC038D4 /* RSI Peripheral ID Register 1 */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_PID1 RSI_PID1 /* SDH Peripheral Identification1 */
+#define RSI_PID2 0xFFC038D8 /* RSI Peripheral ID Register 2 */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_PID2 RSI_PID2 /* SDH Peripheral Identification2 */
+#define RSI_PID3 0xFFC038DC /* RSI Peripheral ID Register 3 */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_PID3 RSI_PID3 /* SDH Peripheral Identification3 */
+/* RSI Registers */
+
+
+
+/* ********************************************************** */
+/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
+/* and MULTI BIT READ MACROS */
+/* ********************************************************** */
+
+/* Bit masks for RSI_PWR_CONTROL */
+#define PWR_ON 0x3 /* Power On */
+#define RSI_CMD_OD 0x40 /* Open Drain Output */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define SD_CMD_OD RSI_CMD_OD /* Open Drain Output */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nSD_CMD_OD 0x0
+/* legacy bit mask (below) provided for backwards code compatibility */
+#if 0
+#define TBD 0x3c /* TBD */
+#endif
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define ROD_CTL 0x80
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nROD_CTL 0x80
+
+
+/* Bit masks for RSI_CLK_CONTROL */
+#define CLKDIV 0xff /* MC_CLK Divisor */
+#define CLK_EN 0x100 /* MC_CLK Bus Clock Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define CLK_E CLK_EN /* MC_CLK Bus Clock Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCLK_E 0x0
+#define PWR_SV_EN 0x200 /* Power Save Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define PWR_SV_E PWR_SV_EN /* Power Save Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nPWR_SV_E 0x0
+#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCLKDIV_BYPASS 0x0
+#define BUS_MODE 0x1800 /* Bus width selection */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define WIDE_BUS 0x0800 /* Wide Bus Mode Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nWIDE_BUS 0x0
+
+
+/* Bit masks for RSI_COMMAND */
+#define CMD_IDX 0x3f /* Command Index */
+#define CMD_RSP_EN 0x40 /* Response */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define CMD_RSP CMD_RSP_EN /* Response */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_RSP 0x0
+#define CMD_LRSP_EN 0x80 /* Long Response */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define CMD_L_RSP CMD_LRSP_EN /* Long Response */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_L_RSP 0x0
+#define CMD_INT_EN 0x100 /* Command Interrupt */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define CMD_INT_E CMD_INT_EN /* Command Interrupt */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_INT_E 0x0
+#define CMD_PEND_EN 0x200 /* Command Pending */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define CMD_PEND_E CMD_PEND_EN /* Command Pending */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_PEND_E 0x0
+#define CMD_EN 0x400 /* Command Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define CMD_E CMD_EN /* Command Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_E 0x0
+
+
+/* Bit masks for RSI_RESP_CMD */
+#define RESP_CMD 0x3f /* Response Command */
+
+/* Bit masks for RSI_DATA_LGTH */
+#define DATA_LENGTH 0xffff /* Data Length */
+
+
+/* Bit masks for RSI_DATA_CONTROL */
+#define DATA_EN 0x1 /* Data Transfer Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define DTX_E DATA_EN /* Data Transfer Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDTX_E 0x0
+#define DATA_DIR 0x2 /* Data Transfer Direction */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define DTX_DIR DATA_DIR /* Data Transfer Direction */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDTX_DIR 0x0
+#define DATA_MODE 0x4 /* Data Transfer Mode */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define DTX_MODE DATA_MODE /* Data Transfer Mode */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDTX_MODE 0x0
+#define DATA_DMA_EN 0x8 /* Data Transfer DMA Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDTX_DMA_E 0x0
+#define DATA_BLK_LGTH 0xf0 /* Data Transfer Block Length */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
+#define CEATA_EN 0x100 /* CE-ATA operation mode enable */
+#define CEATA_CCS_EN 0x200 /* CE-ATA CCS mode enable */
+
+/* Bit masks for RSI_DATA_CNT */
+#define DATA_COUNT 0xffff /* Data Count */
+
+/* Bit masks for RSI_STATUS */
+#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_CRC_FAIL 0x0
+#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_CRC_FAIL 0x0
+#define CMD_TIMEOUT 0x4 /* CMD Time Out */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_TIMEOUT 0x0
+#define DAT_TIMEOUT 0x8 /* Data Time Out */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_TIMEOUT 0x0
+#define TX_UNDERRUN 0x10 /* Transmit Underrun */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_UNDERRUN 0x0
+#define RX_OVERRUN 0x20 /* Receive Overrun */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_OVERRUN 0x0
+#define CMD_RESP_END 0x40 /* CMD Response End */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_RESP_END 0x0
+#define CMD_SENT 0x80 /* CMD Sent */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_SENT 0x0
+#define DAT_END 0x100 /* Data End */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_END 0x0
+#define START_BIT_ERR 0x200 /* Start Bit Error */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nSTART_BIT_ERR 0x0
+#define DAT_BLK_END 0x400 /* Data Block End */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_BLK_END 0x0
+#define CMD_ACT 0x800 /* CMD Active */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_ACT 0x0
+#define TX_ACT 0x1000 /* Transmit Active */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_ACT 0x0
+#define RX_ACT 0x2000 /* Receive Active */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_ACT 0x0
+#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_FIFO_STAT 0x0
+#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_FIFO_STAT 0x0
+#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_FIFO_FULL 0x0
+#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_FIFO_FULL 0x0
+#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_FIFO_ZERO 0x0
+#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_DAT_ZERO 0x0
+#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_DAT_RDY 0x0
+#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_FIFO_RDY 0x0
+
+/* Bit masks for RSI_STATCL */
+#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_CRC_FAIL_STAT 0x0
+#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_CRC_FAIL_STAT 0x0
+#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_TIMEOUT_STAT 0x0
+#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_TIMEOUT_STAT 0x0
+#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_UNDERRUN_STAT 0x0
+#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_OVERRUN_STAT 0x0
+#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_RESP_END_STAT 0x0
+#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_SENT_STAT 0x0
+#define DAT_END_STAT 0x100 /* Data End Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_END_STAT 0x0
+#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nSTART_BIT_ERR_STAT 0x0
+#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_BLK_END_STAT 0x0
+
+/* Bit masks for RSI_MASKx */
+#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_CRC_FAIL_MASK 0x0
+#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_CRC_FAIL_MASK 0x0
+#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_TIMEOUT_MASK 0x0
+#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_TIMEOUT_MASK 0x0
+#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_UNDERRUN_MASK 0x0
+#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_OVERRUN_MASK 0x0
+#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_RESP_END_MASK 0x0
+#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_SENT_MASK 0x0
+#define DAT_END_MASK 0x100 /* Data End Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_END_MASK 0x0
+#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nSTART_BIT_ERR_MASK 0x0
+#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_BLK_END_MASK 0x0
+#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_ACT_MASK 0x0
+#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_ACT_MASK 0x0
+#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_ACT_MASK 0x0
+#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_FIFO_STAT_MASK 0x0
+#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_FIFO_STAT_MASK 0x0
+#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_FIFO_FULL_MASK 0x0
+#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_FIFO_FULL_MASK 0x0
+#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_FIFO_ZERO_MASK 0x0
+#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_DAT_ZERO_MASK 0x0
+#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_DAT_RDY_MASK 0x0
+#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_FIFO_RDY_MASK 0x0
+
+/* Bit masks for RSI_FIFO_CNT */
+#define FIFO_COUNT 0x7fff /* FIFO Count */
+
+/* Bit masks for RSI_CEATA_CONTROL */
+#define CEATA_TX_CCSD 0x1 /* Send CE-ATA CCSD sequence */
+
+/* Bit masks for RSI_ESTAT */
+#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nSDIO_INT_DET 0x0
+#define SD_CARD_DET 0x10 /* SD Card Detect */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nSD_CARD_DET 0x0
+#define CEATA_INT_DET 0x20
+
+/* Bit masks for RSI_EMASK */
+#define SDIO_INT_DET_MASK 0x2 /* Mask SDIO Int Detected */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define SDIO_MSK SDIO_INT_DET_MASK /* Mask SDIO Int Detected */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nSDIO_MSK 0x0
+#define SD_CARD_DET_MASK 0x10 /* Mask Card Detect */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define SCD_MASK SD_CARD_DET_MASK /* Mask Card Detect */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nSCD_MSK 0x0
+#define CEATA_INT_DET_MASK 0x20
+
+
+/* Bit masks for RSI_CFG */
+/* Left in for backwards compatibility */
+#define RSI_CLK_EN 0x1
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define CLKS_EN RSI_CLK_EN /* Clocks Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCLKS_EN 0x0
+#define SDIO4_EN 0x4 /* SDIO 4-Bit Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define SD4E SDIO4_EN /* SDIO 4-Bit Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nSD4E 0x0
+#define MW_EN 0x8 /* Moving Window Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define MWE MW_EN /* Moving Window Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nMWE 0x0
+#define RSI_RST 0x10 /* SDMMC Reset */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define SD_RST RSI_RST /* SDMMC Reset */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nSD_RST 0x0
+#define PU_DAT 0x20 /* Pull-up SD_DAT */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define PUP_SDDAT PU_DAT /* Pull-up SD_DAT */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nPUP_SDDAT 0x0
+#define PU_DAT3 0x40 /* Pull-up SD_DAT3 */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define PUP_SDDAT3 PU_DAT3 /* Pull-up SD_DAT3 */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nPUP_SDDAT3 0x0
+#define PD_DAT3 0x80 /* Pull-down SD_DAT3 */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define PD_SDDAT3 PD_DAT3 /* Pull-down SD_DAT3 */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nPD_SDDAT3 0x0
+
+
+/* Bit masks for RSI_RD_WAIT_EN */
+#define SDIO_RWR 0x1 /* Read Wait Request */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define RWR SDIO_RWR /* Read Wait Request */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRWR 0x0
+
+/* Bit masks for RSI_PIDx */
+#define RSI_PID 0xff /* RSI Peripheral ID */
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif /* _DEF_BF514_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** Copyright (C) 2009 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for register-access and bit-manipulation.
+**
+**/
+#ifndef _DEF_BF516_H
+#define _DEF_BF516_H
+
+/* Include all Core registers and bit definitions */
+#include <def_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF516 */
+
+/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
+#include <defBF51x_base.h>
+
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"macros not strictly following 19.4")
+#pragma diag(suppress:misra_rule_19_7:"Allow function-like macros")
+#endif /* _MISRA_RULES */
+
+/* The following are the #defines needed by ADSP-BF516 that are not in the common header */
+/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
+
+#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
+#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
+#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
+#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
+#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
+#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
+#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
+#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
+#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
+#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
+#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
+#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
+#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
+#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
+#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
+#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
+#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
+#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
+#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
+
+#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
+#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
+#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
+#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
+#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
+#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
+#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
+#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
+
+#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
+#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
+#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
+#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
+#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
+
+#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
+#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
+#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
+#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
+#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
+#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
+#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
+#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
+#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
+#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
+#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
+#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
+#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
+#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
+#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
+#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
+#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
+#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
+#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
+#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */
+#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
+#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
+#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
+#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
+
+#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
+#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
+#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
+#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
+#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
+#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
+#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
+#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
+#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
+#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
+#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
+#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
+#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
+#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
+#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
+#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
+#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
+#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */
+#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
+#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
+#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
+#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
+#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
+
+/* Listing for IEEE-Supported Count Registers */
+
+#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
+#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
+#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
+#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
+#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
+#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
+#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
+#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
+#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
+#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
+#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
+#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
+#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
+#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
+#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
+#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
+#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
+#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
+#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
+#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */
+#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
+#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
+#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
+#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
+
+#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
+#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
+#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
+#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
+#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
+#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
+#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
+#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
+#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
+#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
+#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
+#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
+#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
+#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
+#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
+#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
+#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
+#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */
+#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
+#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
+#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
+#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
+#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
+
+
+/* RSI Registers */
+
+#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_PWR_CTL RSI_PWR_CONTROL /* SDH Power Control */
+#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_CLK_CTL RSI_CLK_CONTROL /* SDH Clock Control */
+#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_ARGUMENT RSI_ARGUMENT /* SDH Argument */
+#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_COMMAND RSI_COMMAND /* SDH Command */
+#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_RESP_CMD RSI_RESP_CMD /* SDH Response Command */
+#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_RESPONSE0 RSI_RESPONSE0 /* SDH Response0 */
+#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_RESPONSE1 RSI_RESPONSE1 /* SDH Response1 */
+#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_RESPONSE2 RSI_RESPONSE2 /* SDH Response2 */
+#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_RESPONSE3 RSI_RESPONSE3 /* SDH Response3 */
+#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_DATA_TIMER RSI_DATA_TIMER /* SDH Data Timer */
+#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_DATA_LGTH RSI_DATA_LGTH /* SDH Data Length */
+#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_DATA_CTL RSI_DATA_CONTROL /* SDH Data Control */
+#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_DATA_CNT RSI_DATA_CNT /* SDH Data Counter */
+#define RSI_STATUS 0xFFC03834 /* RSI Status Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_STATUS RSI_STATUS /* SDH Status */
+#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_STATUS_CLR RSI_STATUSCL /* SDH Status Clear */
+#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_MASK0 RSI_MASK0 /* SDH Interrupt0 Mask */
+#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_MASK1 RSI_MASK1 /* SDH Interrupt1 Mask */
+#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_FIFO_CNT RSI_FIFO_CNT /* SDH FIFO Counter */
+#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */
+#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_FIFO RSI_FIFO /* SDH Data FIFO */
+#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_E_STATUS RSI_ESTAT /* SDH Exception Status */
+#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_E_MASK RSI_EMASK /* SDH Exception Mask */
+#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_CFG RSI_CONFIG /* SDH Configuration */
+#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_RD_WAIT_EN RSI_RD_WAIT_EN /* SDH Read Wait Enable */
+#define RSI_PID0 0xFFC038D0 /* RSI Peripheral ID Register 0 */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_PID0 RSI_PID0 /* SDH Peripheral Identification0 */
+#define RSI_PID1 0xFFC038D4 /* RSI Peripheral ID Register 1 */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_PID1 RSI_PID1 /* SDH Peripheral Identification1 */
+#define RSI_PID2 0xFFC038D8 /* RSI Peripheral ID Register 2 */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_PID2 RSI_PID2 /* SDH Peripheral Identification2 */
+#define RSI_PID3 0xFFC038DC /* RSI Peripheral ID Register 3 */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_PID3 RSI_PID3 /* SDH Peripheral Identification3 */
+/* RSI Registers */
+
+
+
+/***********************************************************************************
+** System MMR Register Bits And Macros
+**
+** Disclaimer: All macros are intended to make C and Assembly code more readable.
+** Use these macros carefully, as any that do left shifts for field
+** depositing will result in the lower order bits being destroyed. Any
+** macro that shifts left to properly position the bit-field should be
+** used as part of an OR to initialize a register and NOT as a dynamic
+** modifier UNLESS the lower order bits are saved and ORed back in when
+** the macro is used.
+*************************************************************************************/
+
+/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
+
+/* EMAC_OPMODE Masks */
+
+#define RE 0x00000001 /* Receiver Enable */
+#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
+#define HU 0x00000010 /* Hash Filter Unicast Address */
+#define HM 0x00000020 /* Hash Filter Multicast Address */
+#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
+#define PR 0x00000080 /* Promiscuous Mode Enable */
+#define IFE 0x00000100 /* Inverse Filtering Enable */
+#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
+#define PBF 0x00000400 /* Pass Bad Frames Enable */
+#define PSF 0x00000800 /* Pass Short Frames Enable */
+#define RAF 0x00001000 /* Receive-All Mode */
+#define TE 0x00010000 /* Transmitter Enable */
+#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
+#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
+#define DC 0x00080000 /* Deferral Check */
+#define BOLMT 0x00300000 /* Back-Off Limit */
+#define BOLMT_10 0x00000000 /* 10-bit range */
+#define BOLMT_8 0x00100000 /* 8-bit range */
+#define BOLMT_4 0x00200000 /* 4-bit range */
+#define BOLMT_1 0x00300000 /* 1-bit range */
+#define DRTY 0x00400000 /* Disable TX Retry On Collision */
+#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
+#define RMII 0x01000000 /* RMII/MII* Mode */
+#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
+#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
+#define LB 0x08000000 /* Internal Loopback Enable */
+#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
+
+/* EMAC_STAADD Masks */
+
+#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
+#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
+#define STADISPRE 0x00000004 /* Disable Preamble Generation */
+#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
+#define REGAD 0x000007C0 /* STA Register Address */
+#define PHYAD 0x0000F800 /* PHY Device Address */
+
+#ifdef _MISRA_RULES
+#define SET_REGAD(x) (((x)&0x1Fu)<< 6 ) /* Set STA Register Address */
+#define SET_PHYAD(x) (((x)&0x1Fu)<< 11 ) /* Set PHY Device Address */
+#else
+#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
+#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
+#endif /* _MISRA_RULES */
+
+/* EMAC_STADAT Mask */
+
+#define STADATA 0x0000FFFF /* Station Management Data */
+
+/* EMAC_FLC Masks */
+
+#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
+#define FLCE 0x00000002 /* Flow Control Enable */
+#define PCF 0x00000004 /* Pass Control Frames */
+#define BKPRSEN 0x00000008 /* Enable Backpressure */
+#define FLCPAUSE 0xFFFF0000 /* Pause Time */
+
+#ifdef _MISRA_RULES
+#define SET_FLCPAUSE(x) (((x)&0xFFFFu)<< 16) /* Set Pause Time */
+#else
+#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
+#endif /* _MISRA_RULES */
+
+/* EMAC_WKUP_CTL Masks */
+
+#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
+#define MPKE 0x00000002 /* Magic Packet Enable */
+#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
+#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
+#define MPKS 0x00000020 /* Magic Packet Received Status */
+#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
+
+/* EMAC_WKUP_FFCMD Masks */
+
+#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
+#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
+#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
+#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
+#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
+#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
+#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
+#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
+
+/* EMAC_WKUP_FFOFF Masks */
+
+#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
+#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
+#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
+#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
+
+#ifdef _MISRA_RULES
+#define SET_WF0_OFF(x) (((x)&0xFFu)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
+#define SET_WF1_OFF(x) (((x)&0xFFu)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
+#define SET_WF2_OFF(x) (((x)&0xFFu)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
+#define SET_WF3_OFF(x) (((x)&0xFFu)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
+#else
+#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
+#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
+#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
+#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
+#endif /* _MISRA_RULES */
+
+/* Set ALL Offsets */
+#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
+
+/* EMAC_WKUP_FFCRC0 Masks */
+
+#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
+#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
+
+#ifdef _MISRA_RULES
+#define SET_WF0_CRC(x) (((x)&0xFFFFu)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
+#define SET_WF1_CRC(x) (((x)&0xFFFFu)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
+#else
+#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
+#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
+#endif /* _MISRA_RULES */
+
+/* EMAC_WKUP_FFCRC1 Masks */
+
+#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
+#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
+
+#ifdef _MISRA_RULES
+#define SET_WF2_CRC(x) (((x)&0xFFFFu)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
+#define SET_WF3_CRC(x) (((x)&0xFFFFu)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
+#else
+#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
+#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
+#endif /* _MISRA_RULES */
+
+/* EMAC_SYSCTL Masks */
+
+#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
+#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
+#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
+#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
+
+#ifdef _MISRA_RULES
+#define SET_MDCDIV(x) (((x)&0x3Fu)<< 8) /* Set MDC Clock Divisor */
+#else
+#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
+#endif /* _MISRA_RULES */
+
+/* EMAC_SYSTAT Masks */
+
+#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
+#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
+#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
+#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
+#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
+#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
+#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
+#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
+
+/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
+
+#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
+#define RX_COMP 0x00001000 /* RX Frame Complete */
+#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
+#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
+#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
+#define RX_CRC 0x00010000 /* RX Frame CRC Error */
+#define RX_LEN 0x00020000 /* RX Frame Length Error */
+#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
+#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
+#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
+#define RX_PHY 0x00200000 /* RX Frame PHY Error */
+#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
+#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
+#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
+#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
+#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
+#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
+#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
+#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
+#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
+#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
+
+/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
+
+#define TX_COMP 0x00000001 /* TX Frame Complete */
+#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
+#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
+#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
+#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
+#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
+#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
+#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
+#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
+#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
+#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
+#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
+#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
+#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
+#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
+
+/* EMAC_MMC_CTL Masks */
+#define RSTC 0x00000001 /* Reset All Counters */
+#define CROLL 0x00000002 /* Counter Roll-Over Enable */
+#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
+#define MMCE 0x00000008 /* Enable MMC Counter Operation */
+
+/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
+#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
+#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
+#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
+#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
+#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
+#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
+#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
+#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
+#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
+#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
+#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
+#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
+#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
+#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
+#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
+#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
+#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
+#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
+#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
+#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
+#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
+#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
+#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
+#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
+
+/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
+
+#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
+#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
+#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
+#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
+#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
+#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
+#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
+#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
+#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
+#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
+#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
+#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
+#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
+#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
+#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
+#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
+#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
+#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
+#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
+#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
+#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
+#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
+#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
+
+
+/* Bit masks for EMAC_PTP_CTL */
+
+#define EMAC_PTP_CTL_EN 0x1 /* Block Enable */
+#define EMAC_PTP_CTL_TL 0x2 /* Time Stamp Lock */
+#define EMAC_PTP_CTL_CKS 0xC /* Clock source for the PTP_TSYNC block */
+#define EMAC_PTP_CTL_ASEN 0x10 /* Auxiliary Snapshot Enable */
+#define EMAC_PTP_CTL_CKDIV 0x60 /* Divider for the selected PTP_CLK output */
+#define EMAC_PTP_CTL_PPSEN 0x80 /* Pulse Per Second (PPS) Enable */
+#define EMAC_PTP_CTL_EFTM 0x100 /* Ethernet Frame type field compare mask */
+#define EMAC_PTP_CTL_IPVM 0x200 /* IP Version field compare mask */
+#define EMAC_PTP_CTL_IPTM 0x400 /* IP Type Frame field (Layer 4 protocol) compare mask */
+#define EMAC_PTP_CTL_UDPEM 0x800 /* UDP Event port field compare mask */
+#define EMAC_PTP_CTL_PTPCM 0x1000 /* PTP Control field compare mask */
+#define EMAC_PTP_CTL_CKOEN 0x2000 /* Clock output Enable */
+
+/* Bit masks for EMAC_PTP_IE */
+
+#define EMAC_PTP_IE_ALIE 0x1 /* Alarm Feature and Interrupt Enable */
+#define EMAC_PTP_IE_RXEIE 0x2 /* Receive Event Interrupt Enable */
+#define EMAC_PTP_IE_RXGIE 0x4 /* Receive General Interrupt Enable */
+#define EMAC_PTP_IE_TXIE 0x8 /* Transmit Interrupt Enable */
+#define EMAC_PTP_IE_TXOVE 0x10 /* Transmit Overrun Error Interrupt Enable */
+#define EMAC_PTP_IE_RXOVE 0x20 /* Receive Overrun Error Interrupt Enable */
+#define EMAC_PTP_IE_ASIE 0x40 /* Auxiliary Snapshot Interrupt Enable */
+
+/* Bit masks for EMAC_PTP_ISTAT */
+
+#define EMAC_PTP_ISTAT_ALS 0x1 /* Alarm Status */
+#define EMAC_PTP_ISTAT_RXEL 0x2 /* Receive Event Interrupt Locked */
+#define EMAC_PTP_ISTAT_RXGL 0x4 /* Receive General Interrupt Locked */
+#define EMAC_PTP_ISTAT_TXTL 0x8 /* Transmit Snapshot Locked */
+#define EMAC_PTP_ISTAT_RXOV 0x10 /* Receive Snapshot Overrun Status */
+#define EMAC_PTP_ISTAT_TXOV 0x20 /* Transmit snapshot Overrun Status */
+#define EMAC_PTP_ISTAT_ASL 0x40 /* Auxiliary Snapshot Interrupt Status */
+
+
+/* Bit masks for RSI_PWR_CONTROL */
+#define PWR_ON 0x3 /* Power On */
+#define RSI_CMD_OD 0x40 /* Open Drain Output */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define SD_CMD_OD RSI_CMD_OD /* Open Drain Output */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nSD_CMD_OD 0x0
+/* legacy bit mask (below) provided for backwards code compatibility */
+#if 0
+#define TBD 0x3c /* TBD */
+#endif
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define ROD_CTL 0x80
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nROD_CTL 0x80
+
+
+/* Bit masks for RSI_CLK_CONTROL */
+#define CLKDIV 0xff /* MC_CLK Divisor */
+#define CLK_EN 0x100 /* MC_CLK Bus Clock Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define CLK_E CLK_EN /* MC_CLK Bus Clock Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCLK_E 0x0
+#define PWR_SV_EN 0x200 /* Power Save Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define PWR_SV_E PWR_SV_EN /* Power Save Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nPWR_SV_E 0x0
+#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCLKDIV_BYPASS 0x0
+#define BUS_MODE 0x1800 /* Bus width selection */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define WIDE_BUS 0x0800 /* Wide Bus Mode Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nWIDE_BUS 0x0
+
+
+/* Bit masks for RSI_COMMAND */
+#define CMD_IDX 0x3f /* Command Index */
+#define CMD_RSP_EN 0x40 /* Response */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define CMD_RSP CMD_RSP_EN /* Response */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_RSP 0x0
+#define CMD_LRSP_EN 0x80 /* Long Response */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define CMD_L_RSP CMD_LRSP_EN /* Long Response */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_L_RSP 0x0
+#define CMD_INT_EN 0x100 /* Command Interrupt */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define CMD_INT_E CMD_INT_EN /* Command Interrupt */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_INT_E 0x0
+#define CMD_PEND_EN 0x200 /* Command Pending */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define CMD_PEND_E CMD_PEND_EN /* Command Pending */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_PEND_E 0x0
+#define CMD_EN 0x400 /* Command Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define CMD_E CMD_EN /* Command Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_E 0x0
+
+
+/* Bit masks for RSI_RESP_CMD */
+#define RESP_CMD 0x3f /* Response Command */
+
+/* Bit masks for RSI_DATA_LGTH */
+#define DATA_LENGTH 0xffff /* Data Length */
+
+
+/* Bit masks for RSI_DATA_CONTROL */
+#define DATA_EN 0x1 /* Data Transfer Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define DTX_E DATA_EN /* Data Transfer Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDTX_E 0x0
+#define DATA_DIR 0x2 /* Data Transfer Direction */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define DTX_DIR DATA_DIR /* Data Transfer Direction */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDTX_DIR 0x0
+#define DATA_MODE 0x4 /* Data Transfer Mode */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define DTX_MODE DATA_MODE /* Data Transfer Mode */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDTX_MODE 0x0
+#define DATA_DMA_EN 0x8 /* Data Transfer DMA Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDTX_DMA_E 0x0
+#define DATA_BLK_LGTH 0xf0 /* Data Transfer Block Length */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
+#define CEATA_EN 0x100 /* CE-ATA operation mode enable */
+#define CEATA_CCS_EN 0x200 /* CE-ATA CCS mode enable */
+
+/* Bit masks for RSI_DATA_CNT */
+#define DATA_COUNT 0xffff /* Data Count */
+
+/* Bit masks for RSI_STATUS */
+#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_CRC_FAIL 0x0
+#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_CRC_FAIL 0x0
+#define CMD_TIMEOUT 0x4 /* CMD Time Out */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_TIMEOUT 0x0
+#define DAT_TIMEOUT 0x8 /* Data Time Out */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_TIMEOUT 0x0
+#define TX_UNDERRUN 0x10 /* Transmit Underrun */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_UNDERRUN 0x0
+#define RX_OVERRUN 0x20 /* Receive Overrun */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_OVERRUN 0x0
+#define CMD_RESP_END 0x40 /* CMD Response End */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_RESP_END 0x0
+#define CMD_SENT 0x80 /* CMD Sent */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_SENT 0x0
+#define DAT_END 0x100 /* Data End */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_END 0x0
+#define START_BIT_ERR 0x200 /* Start Bit Error */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nSTART_BIT_ERR 0x0
+#define DAT_BLK_END 0x400 /* Data Block End */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_BLK_END 0x0
+#define CMD_ACT 0x800 /* CMD Active */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_ACT 0x0
+#define TX_ACT 0x1000 /* Transmit Active */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_ACT 0x0
+#define RX_ACT 0x2000 /* Receive Active */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_ACT 0x0
+#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_FIFO_STAT 0x0
+#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_FIFO_STAT 0x0
+#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_FIFO_FULL 0x0
+#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_FIFO_FULL 0x0
+#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_FIFO_ZERO 0x0
+#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_DAT_ZERO 0x0
+#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_DAT_RDY 0x0
+#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_FIFO_RDY 0x0
+
+/* Bit masks for RSI_STATCL */
+
+#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_CRC_FAIL_STAT 0x0
+#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_CRC_FAIL_STAT 0x0
+#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_TIMEOUT_STAT 0x0
+#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_TIMEOUT_STAT 0x0
+#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_UNDERRUN_STAT 0x0
+#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_OVERRUN_STAT 0x0
+#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_RESP_END_STAT 0x0
+#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_SENT_STAT 0x0
+#define DAT_END_STAT 0x100 /* Data End Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_END_STAT 0x0
+#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nSTART_BIT_ERR_STAT 0x0
+#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_BLK_END_STAT 0x0
+
+/* Bit masks for RSI_MASKx */
+
+#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_CRC_FAIL_MASK 0x0
+#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_CRC_FAIL_MASK 0x0
+#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_TIMEOUT_MASK 0x0
+#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_TIMEOUT_MASK 0x0
+#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_UNDERRUN_MASK 0x0
+#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_OVERRUN_MASK 0x0
+#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_RESP_END_MASK 0x0
+#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_SENT_MASK 0x0
+#define DAT_END_MASK 0x100 /* Data End Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_END_MASK 0x0
+#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nSTART_BIT_ERR_MASK 0x0
+#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_BLK_END_MASK 0x0
+#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_ACT_MASK 0x0
+#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_ACT_MASK 0x0
+#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_ACT_MASK 0x0
+#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_FIFO_STAT_MASK 0x0
+#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_FIFO_STAT_MASK 0x0
+#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_FIFO_FULL_MASK 0x0
+#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_FIFO_FULL_MASK 0x0
+#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_FIFO_ZERO_MASK 0x0
+#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_DAT_ZERO_MASK 0x0
+#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_DAT_RDY_MASK 0x0
+#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_FIFO_RDY_MASK 0x0
+
+/* Bit masks for RSI_FIFO_CNT */
+#define FIFO_COUNT 0x7fff /* FIFO Count */
+
+/* Bit masks for RSI_CEATA_CONTROL */
+#define CEATA_TX_CCSD 0x1 /* Send CE-ATA CCSD sequence */
+
+/* Bit masks for RSI_ESTAT */
+#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nSDIO_INT_DET 0x0
+#define SD_CARD_DET 0x10 /* SD Card Detect */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nSD_CARD_DET 0x0
+#define CEATA_INT_DET 0x20
+
+/* Bit masks for RSI_EMASK */
+#define SDIO_INT_DET_MASK 0x2 /* Mask SDIO Int Detected */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define SDIO_MSK SDIO_INT_DET_MASK /* Mask SDIO Int Detected */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nSDIO_MSK 0x0
+#define SD_CARD_DET_MASK 0x10 /* Mask Card Detect */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define SCD_MASK SD_CARD_DET_MASK /* Mask Card Detect */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nSCD_MSK 0x0
+#define CEATA_INT_DET_MASK 0x20
+
+
+/* Bit masks for SDH_CFG */
+
+/* Left in for backwards compatibility */
+#define RSI_CLK_EN 0x1
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define CLKS_EN RSI_CLK_EN /* Clocks Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCLKS_EN 0x0
+#define SDIO4_EN 0x4 /* SDIO 4-Bit Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define SD4E SDIO4_EN /* SDIO 4-Bit Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nSD4E 0x0
+#define MW_EN 0x8 /* Moving Window Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define MWE MW_EN /* Moving Window Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nMWE 0x0
+#define RSI_RST 0x10 /* SDMMC Reset */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define SD_RST RSI_RST /* SDMMC Reset */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nSD_RST 0x0
+#define PU_DAT 0x20 /* Pull-up SD_DAT */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define PUP_SDDAT PU_DAT /* Pull-up SD_DAT */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nPUP_SDDAT 0x0
+#define PU_DAT3 0x40 /* Pull-up SD_DAT3 */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define PUP_SDDAT3 PU_DAT3 /* Pull-up SD_DAT3 */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nPUP_SDDAT3 0x0
+#define PD_DAT3 0x80 /* Pull-down SD_DAT3 */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define PD_SDDAT3 PD_DAT3 /* Pull-down SD_DAT3 */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nPD_SDDAT3 0x0
+
+
+/* Bit masks for RSI_RD_WAIT_EN */
+#define SDIO_RWR 0x1 /* Read Wait Request */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define RWR SDIO_RWR /* Read Wait Request */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRWR 0x0
+
+/* Bit masks for RSI_PIDx */
+#define RSI_PID 0xff /* RSI Peripheral ID */
+
+
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif /* _DEF_BF516_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** Copyright (C) 2009 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for register-access and bit-manipulation.
+**
+**/
+#ifndef _DEF_BF518_H
+#define _DEF_BF518_H
+
+/* Include all Core registers and bit definitions */
+#include <def_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF518 */
+
+/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
+#include <defBF51x_base.h>
+
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"macros not strictly following 19.4")
+#pragma diag(suppress:misra_rule_19_7:"Allow function-like macros")
+#endif /* _MISRA_RULES */
+
+/* The following are the #defines needed by ADSP-BF518 that are not in the common header */
+/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
+
+#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
+#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
+#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
+#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
+#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
+#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
+#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
+#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
+#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
+#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
+#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
+#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
+#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
+#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
+#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
+#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
+#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
+#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
+#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
+
+#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
+#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
+#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
+#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
+#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
+#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
+#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
+#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
+
+#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
+#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
+#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
+#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
+#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
+
+/* EMAC PTP (IEEE 1588) */
+
+#define EMAC_PTP_CTL 0xffc030a0 /* PTP Block Control */
+#define EMAC_PTP_IE 0xffc030a4 /* PTP Block Interrupt Enable */
+#define EMAC_PTP_ISTAT 0xffc030a8 /* PTP Block Interrupt Status */
+#define EMAC_PTP_FOFF 0xffc030ac /* PTP Filter offset Register */
+#define EMAC_PTP_FV1 0xffc030b0 /* PTP Filter Value Register 1 */
+#define EMAC_PTP_FV2 0xffc030b4 /* PTP Filter Value Register 2 */
+#define EMAC_PTP_FV3 0xffc030b8 /* PTP Filter Value Register 3 */
+#define EMAC_PTP_ADDEND 0xffc030bc /* PTP Addend for Frequency Compensation */
+#define EMAC_PTP_ACCR 0xffc030c0 /* PTP Accumulator for Frequency Compensation */
+#define EMAC_PTP_OFFSET 0xffc030c4 /* PTP Time Offset Register */
+#define EMAC_PTP_TIMELO 0xffc030c8 /* PTP Precision Clock Time Low */
+#define EMAC_PTP_TIMEHI 0xffc030cc /* PTP Precision Clock Time High */
+#define EMAC_PTP_RXSNAPLO 0xffc030d0 /* PTP Receive Snapshot Register Low */
+#define EMAC_PTP_RXSNAPHI 0xffc030d4 /* PTP Receive Snapshot Register High */
+#define EMAC_PTP_TXSNAPLO 0xffc030d8 /* PTP Transmit Snapshot Register Low */
+#define EMAC_PTP_TXSNAPHI 0xffc030dc /* PTP Transmit Snapshot Register High */
+#define EMAC_PTP_ALARMLO 0xffc030e0 /* PTP Alarm time Low */
+#define EMAC_PTP_ALARMHI 0xffc030e4 /* PTP Alarm time High */
+#define EMAC_PTP_ID_OFF 0xffc030e8 /* PTP Capture ID offset register */
+#define EMAC_PTP_ID_SNAP 0xffc030ec /* PTP Capture ID register */
+#define EMAC_PTP_PPS_STARTLOP 0xffc030f0 /* PPS Start Time Low */
+#define EMAC_PTP_PPS_STARTHIP 0xffc030f4 /* PPS Start Time High */
+#define EMAC_PTP_PPS_PERIOD 0xffc030f8 /* PPS Count Register */
+
+#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
+#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
+#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
+#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
+#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
+#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
+#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
+#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
+#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
+#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
+#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
+#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
+#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
+#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
+#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
+#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
+#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
+#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
+#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
+#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */
+#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
+#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
+#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
+#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
+
+#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
+#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
+#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
+#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
+#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
+#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
+#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
+#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
+#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
+#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
+#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
+#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
+#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
+#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
+#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
+#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
+#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
+#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */
+#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
+#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
+#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
+#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
+#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
+
+/* Listing for IEEE-Supported Count Registers */
+
+#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
+#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
+#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
+#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
+#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
+#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
+#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
+#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
+#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
+#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
+#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
+#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
+#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
+#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
+#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
+#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
+#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
+#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
+#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
+#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */
+#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
+#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
+#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
+#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
+
+#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
+#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
+#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
+#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
+#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
+#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
+#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
+#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
+#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
+#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
+#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
+#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
+#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
+#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
+#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
+#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
+#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
+#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */
+#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
+#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
+#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
+#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
+#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
+
+
+/* RSI Registers */
+
+#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_PWR_CTL RSI_PWR_CONTROL /* SDH Power Control */
+#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_CLK_CTL RSI_CLK_CONTROL /* SDH Clock Control */
+#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_ARGUMENT RSI_ARGUMENT /* SDH Argument */
+#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_COMMAND RSI_COMMAND /* SDH Command */
+#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_RESP_CMD RSI_RESP_CMD /* SDH Response Command */
+#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_RESPONSE0 RSI_RESPONSE0 /* SDH Response0 */
+#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_RESPONSE1 RSI_RESPONSE1 /* SDH Response1 */
+#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_RESPONSE2 RSI_RESPONSE2 /* SDH Response2 */
+#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_RESPONSE3 RSI_RESPONSE3 /* SDH Response3 */
+#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_DATA_TIMER RSI_DATA_TIMER /* SDH Data Timer */
+#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_DATA_LGTH RSI_DATA_LGTH /* SDH Data Length */
+#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_DATA_CTL RSI_DATA_CONTROL /* SDH Data Control */
+#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_DATA_CNT RSI_DATA_CNT /* SDH Data Counter */
+#define RSI_STATUS 0xFFC03834 /* RSI Status Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_STATUS RSI_STATUS /* SDH Status */
+#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_STATUS_CLR RSI_STATUSCL /* SDH Status Clear */
+#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_MASK0 RSI_MASK0 /* SDH Interrupt0 Mask */
+#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_MASK1 RSI_MASK1 /* SDH Interrupt1 Mask */
+#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_FIFO_CNT RSI_FIFO_CNT /* SDH FIFO Counter */
+#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */
+#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_FIFO RSI_FIFO /* SDH Data FIFO */
+#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_E_STATUS RSI_ESTAT /* SDH Exception Status */
+#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_E_MASK RSI_EMASK /* SDH Exception Mask */
+#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_CFG RSI_CONFIG /* SDH Configuration */
+#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_RD_WAIT_EN RSI_RD_WAIT_EN /* SDH Read Wait Enable */
+#define RSI_PID0 0xFFC038D0 /* RSI Peripheral ID Register 0 */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_PID0 RSI_PID0 /* SDH Peripheral Identification0 */
+#define RSI_PID1 0xFFC038D4 /* RSI Peripheral ID Register 1 */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_PID1 RSI_PID1 /* SDH Peripheral Identification1 */
+#define RSI_PID2 0xFFC038D8 /* RSI Peripheral ID Register 2 */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_PID2 RSI_PID2 /* SDH Peripheral Identification2 */
+#define RSI_PID3 0xFFC038DC /* RSI Peripheral ID Register 3 */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SDH_PID3 RSI_PID3 /* SDH Peripheral Identification3 */
+/* RSI Registers */
+
+
+
+/***********************************************************************************
+** System MMR Register Bits And Macros
+**
+** Disclaimer: All macros are intended to make C and Assembly code more readable.
+** Use these macros carefully, as any that do left shifts for field
+** depositing will result in the lower order bits being destroyed. Any
+** macro that shifts left to properly position the bit-field should be
+** used as part of an OR to initialize a register and NOT as a dynamic
+** modifier UNLESS the lower order bits are saved and ORed back in when
+** the macro is used.
+*************************************************************************************/
+
+/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
+
+/* EMAC_OPMODE Masks */
+
+#define RE 0x00000001 /* Receiver Enable */
+#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
+#define HU 0x00000010 /* Hash Filter Unicast Address */
+#define HM 0x00000020 /* Hash Filter Multicast Address */
+#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
+#define PR 0x00000080 /* Promiscuous Mode Enable */
+#define IFE 0x00000100 /* Inverse Filtering Enable */
+#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
+#define PBF 0x00000400 /* Pass Bad Frames Enable */
+#define PSF 0x00000800 /* Pass Short Frames Enable */
+#define RAF 0x00001000 /* Receive-All Mode */
+#define TE 0x00010000 /* Transmitter Enable */
+#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
+#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
+#define DC 0x00080000 /* Deferral Check */
+#define BOLMT 0x00300000 /* Back-Off Limit */
+#define BOLMT_10 0x00000000 /* 10-bit range */
+#define BOLMT_8 0x00100000 /* 8-bit range */
+#define BOLMT_4 0x00200000 /* 4-bit range */
+#define BOLMT_1 0x00300000 /* 1-bit range */
+#define DRTY 0x00400000 /* Disable TX Retry On Collision */
+#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
+#define RMII 0x01000000 /* RMII/MII* Mode */
+#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
+#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
+#define LB 0x08000000 /* Internal Loopback Enable */
+#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
+
+/* EMAC_STAADD Masks */
+
+#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
+#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
+#define STADISPRE 0x00000004 /* Disable Preamble Generation */
+#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
+#define REGAD 0x000007C0 /* STA Register Address */
+#define PHYAD 0x0000F800 /* PHY Device Address */
+
+#ifdef _MISRA_RULES
+#define SET_REGAD(x) (((x)&0x1Fu)<< 6 ) /* Set STA Register Address */
+#define SET_PHYAD(x) (((x)&0x1Fu)<< 11 ) /* Set PHY Device Address */
+#else
+#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
+#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
+#endif /* _MISRA_RULES */
+
+/* EMAC_STADAT Mask */
+
+#define STADATA 0x0000FFFF /* Station Management Data */
+
+/* EMAC_FLC Masks */
+
+#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
+#define FLCE 0x00000002 /* Flow Control Enable */
+#define PCF 0x00000004 /* Pass Control Frames */
+#define BKPRSEN 0x00000008 /* Enable Backpressure */
+#define FLCPAUSE 0xFFFF0000 /* Pause Time */
+
+#ifdef _MISRA_RULES
+#define SET_FLCPAUSE(x) (((x)&0xFFFFu)<< 16) /* Set Pause Time */
+#else
+#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
+#endif /* _MISRA_RULES */
+
+/* EMAC_WKUP_CTL Masks */
+
+#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
+#define MPKE 0x00000002 /* Magic Packet Enable */
+#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
+#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
+#define MPKS 0x00000020 /* Magic Packet Received Status */
+#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
+
+/* EMAC_WKUP_FFCMD Masks */
+
+#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
+#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
+#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
+#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
+#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
+#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
+#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
+#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
+
+/* EMAC_WKUP_FFOFF Masks */
+
+#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
+#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
+#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
+#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
+
+#ifdef _MISRA_RULES
+#define SET_WF0_OFF(x) (((x)&0xFFu)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
+#define SET_WF1_OFF(x) (((x)&0xFFu)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
+#define SET_WF2_OFF(x) (((x)&0xFFu)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
+#define SET_WF3_OFF(x) (((x)&0xFFu)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
+#else
+#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
+#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
+#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
+#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
+#endif /* _MISRA_RULES */
+
+/* Set ALL Offsets */
+#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
+
+/* EMAC_WKUP_FFCRC0 Masks */
+
+#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
+#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
+
+#ifdef _MISRA_RULES
+#define SET_WF0_CRC(x) (((x)&0xFFFFu)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
+#define SET_WF1_CRC(x) (((x)&0xFFFFu)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
+#else
+#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
+#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
+#endif /* _MISRA_RULES */
+
+/* EMAC_WKUP_FFCRC1 Masks */
+
+#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
+#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
+
+#ifdef _MISRA_RULES
+#define SET_WF2_CRC(x) (((x)&0xFFFFu)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
+#define SET_WF3_CRC(x) (((x)&0xFFFFu)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
+#else
+#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
+#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
+#endif /* _MISRA_RULES */
+
+/* EMAC_SYSCTL Masks */
+
+#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
+#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
+#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
+#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
+
+#ifdef _MISRA_RULES
+#define SET_MDCDIV(x) (((x)&0x3Fu)<< 8) /* Set MDC Clock Divisor */
+#else
+#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
+#endif /* _MISRA_RULES */
+
+/* EMAC_SYSTAT Masks */
+
+#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
+#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
+#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
+#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
+#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
+#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
+#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
+#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
+
+/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
+
+#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
+#define RX_COMP 0x00001000 /* RX Frame Complete */
+#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
+#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
+#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
+#define RX_CRC 0x00010000 /* RX Frame CRC Error */
+#define RX_LEN 0x00020000 /* RX Frame Length Error */
+#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
+#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
+#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
+#define RX_PHY 0x00200000 /* RX Frame PHY Error */
+#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
+#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
+#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
+#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
+#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
+#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
+#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
+#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
+#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
+#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
+
+/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
+
+#define TX_COMP 0x00000001 /* TX Frame Complete */
+#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
+#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
+#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
+#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
+#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
+#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
+#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
+#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
+#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
+#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
+#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
+#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
+#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
+#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
+
+/* EMAC_MMC_CTL Masks */
+#define RSTC 0x00000001 /* Reset All Counters */
+#define CROLL 0x00000002 /* Counter Roll-Over Enable */
+#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
+#define MMCE 0x00000008 /* Enable MMC Counter Operation */
+
+/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
+#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
+#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
+#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
+#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
+#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
+#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
+#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
+#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
+#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
+#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
+#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
+#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
+#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
+#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
+#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
+#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
+#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
+#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
+#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
+#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
+#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
+#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
+#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
+#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
+
+/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
+
+#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
+#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
+#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
+#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
+#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
+#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
+#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
+#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
+#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
+#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
+#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
+#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
+#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
+#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
+#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
+#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
+#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
+#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
+#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
+#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
+#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
+#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
+#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
+
+
+/* Bit masks for EMAC_PTP_CTL */
+
+#define EMAC_PTP_CTL_EN 0x1 /* Block Enable */
+#define EMAC_PTP_CTL_TL 0x2 /* Time Stamp Lock */
+#define EMAC_PTP_CTL_CKS 0xC /* Clock source for the PTP_TSYNC block */
+#define EMAC_PTP_CTL_ASEN 0x10 /* Auxiliary Snapshot Enable */
+#define EMAC_PTP_CTL_CKDIV 0x60 /* Divider for the selected PTP_CLK output */
+#define EMAC_PTP_CTL_PPSEN 0x80 /* Pulse Per Second (PPS) Enable */
+#define EMAC_PTP_CTL_EFTM 0x100 /* Ethernet Frame type field compare mask */
+#define EMAC_PTP_CTL_IPVM 0x200 /* IP Version field compare mask */
+#define EMAC_PTP_CTL_IPTM 0x400 /* IP Type Frame field (Layer 4 protocol) compare mask */
+#define EMAC_PTP_CTL_UDPEM 0x800 /* UDP Event port field compare mask */
+#define EMAC_PTP_CTL_PTPCM 0x1000 /* PTP Control field compare mask */
+#define EMAC_PTP_CTL_CKOEN 0x2000 /* Clock output Enable */
+
+/* Bit masks for EMAC_PTP_IE */
+
+#define EMAC_PTP_IE_ALIE 0x1 /* Alarm Feature and Interrupt Enable */
+#define EMAC_PTP_IE_RXEIE 0x2 /* Receive Event Interrupt Enable */
+#define EMAC_PTP_IE_RXGIE 0x4 /* Receive General Interrupt Enable */
+#define EMAC_PTP_IE_TXIE 0x8 /* Transmit Interrupt Enable */
+#define EMAC_PTP_IE_TXOVE 0x10 /* Transmit Overrun Error Interrupt Enable */
+#define EMAC_PTP_IE_RXOVE 0x20 /* Receive Overrun Error Interrupt Enable */
+#define EMAC_PTP_IE_ASIE 0x40 /* Auxiliary Snapshot Interrupt Enable */
+
+/* Bit masks for EMAC_PTP_ISTAT */
+
+#define EMAC_PTP_ISTAT_ALS 0x1 /* Alarm Status */
+#define EMAC_PTP_ISTAT_RXEL 0x2 /* Receive Event Interrupt Locked */
+#define EMAC_PTP_ISTAT_RXGL 0x4 /* Receive General Interrupt Locked */
+#define EMAC_PTP_ISTAT_TXTL 0x8 /* Transmit Snapshot Locked */
+#define EMAC_PTP_ISTAT_RXOV 0x10 /* Receive Snapshot Overrun Status */
+#define EMAC_PTP_ISTAT_TXOV 0x20 /* Transmit snapshot Overrun Status */
+#define EMAC_PTP_ISTAT_ASL 0x40 /* Auxiliary Snapshot Interrupt Status */
+
+
+/* Bit masks for RSI_PWR_CONTROL */
+#define PWR_ON 0x3 /* Power On */
+#define RSI_CMD_OD 0x40 /* Open Drain Output */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define SD_CMD_OD RSI_CMD_OD /* Open Drain Output */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nSD_CMD_OD 0x0
+/* legacy bit mask (below) provided for backwards code compatibility */
+#if 0
+#define TBD 0x3c /* TBD */
+#endif
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define ROD_CTL 0x80
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nROD_CTL 0x80
+
+
+/* Bit masks for RSI_CLK_CONTROL */
+#define CLKDIV 0xff /* MC_CLK Divisor */
+#define CLK_EN 0x100 /* MC_CLK Bus Clock Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define CLK_E CLK_EN /* MC_CLK Bus Clock Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCLK_E 0x0
+#define PWR_SV_EN 0x200 /* Power Save Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define PWR_SV_E PWR_SV_EN /* Power Save Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nPWR_SV_E 0x0
+#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCLKDIV_BYPASS 0x0
+#define BUS_MODE 0x1800 /* Bus width selection */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define WIDE_BUS 0x0800 /* Wide Bus Mode Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nWIDE_BUS 0x0
+
+
+/* Bit masks for RSI_COMMAND */
+#define CMD_IDX 0x3f /* Command Index */
+#define CMD_RSP_EN 0x40 /* Response */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define CMD_RSP CMD_RSP_EN /* Response */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_RSP 0x0
+#define CMD_LRSP_EN 0x80 /* Long Response */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define CMD_L_RSP CMD_LRSP_EN /* Long Response */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_L_RSP 0x0
+#define CMD_INT_EN 0x100 /* Command Interrupt */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define CMD_INT_E CMD_INT_EN /* Command Interrupt */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_INT_E 0x0
+#define CMD_PEND_EN 0x200 /* Command Pending */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define CMD_PEND_E CMD_PEND_EN /* Command Pending */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_PEND_E 0x0
+#define CMD_EN 0x400 /* Command Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define CMD_E CMD_EN /* Command Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_E 0x0
+
+
+/* Bit masks for RSI_RESP_CMD */
+#define RESP_CMD 0x3f /* Response Command */
+
+/* Bit masks for RSI_DATA_LGTH */
+#define DATA_LENGTH 0xffff /* Data Length */
+
+
+/* Bit masks for RSI_DATA_CONTROL */
+#define DATA_EN 0x1 /* Data Transfer Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define DTX_E DATA_EN /* Data Transfer Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDTX_E 0x0
+#define DATA_DIR 0x2 /* Data Transfer Direction */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define DTX_DIR DATA_DIR /* Data Transfer Direction */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDTX_DIR 0x0
+#define DATA_MODE 0x4 /* Data Transfer Mode */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define DTX_MODE DATA_MODE /* Data Transfer Mode */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDTX_MODE 0x0
+#define DATA_DMA_EN 0x8 /* Data Transfer DMA Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDTX_DMA_E 0x0
+#define DATA_BLK_LGTH 0xf0 /* Data Transfer Block Length */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
+#define CEATA_EN 0x100 /* CE-ATA operation mode enable */
+#define CEATA_CCS_EN 0x200 /* CE-ATA CCS mode enable */
+
+/* Bit masks for RSI_DATA_CNT */
+#define DATA_COUNT 0xffff /* Data Count */
+
+/* Bit masks for RSI_STATUS */
+#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_CRC_FAIL 0x0
+#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_CRC_FAIL 0x0
+#define CMD_TIMEOUT 0x4 /* CMD Time Out */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_TIMEOUT 0x0
+#define DAT_TIMEOUT 0x8 /* Data Time Out */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_TIMEOUT 0x0
+#define TX_UNDERRUN 0x10 /* Transmit Underrun */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_UNDERRUN 0x0
+#define RX_OVERRUN 0x20 /* Receive Overrun */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_OVERRUN 0x0
+#define CMD_RESP_END 0x40 /* CMD Response End */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_RESP_END 0x0
+#define CMD_SENT 0x80 /* CMD Sent */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_SENT 0x0
+#define DAT_END 0x100 /* Data End */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_END 0x0
+#define START_BIT_ERR 0x200 /* Start Bit Error */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nSTART_BIT_ERR 0x0
+#define DAT_BLK_END 0x400 /* Data Block End */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_BLK_END 0x0
+#define CMD_ACT 0x800 /* CMD Active */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_ACT 0x0
+#define TX_ACT 0x1000 /* Transmit Active */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_ACT 0x0
+#define RX_ACT 0x2000 /* Receive Active */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_ACT 0x0
+#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_FIFO_STAT 0x0
+#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_FIFO_STAT 0x0
+#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_FIFO_FULL 0x0
+#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_FIFO_FULL 0x0
+#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_FIFO_ZERO 0x0
+#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_DAT_ZERO 0x0
+#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_DAT_RDY 0x0
+#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_FIFO_RDY 0x0
+
+/* Bit masks for RSI_STATCL */
+
+#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_CRC_FAIL_STAT 0x0
+#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_CRC_FAIL_STAT 0x0
+#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_TIMEOUT_STAT 0x0
+#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_TIMEOUT_STAT 0x0
+#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_UNDERRUN_STAT 0x0
+#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_OVERRUN_STAT 0x0
+#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_RESP_END_STAT 0x0
+#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_SENT_STAT 0x0
+#define DAT_END_STAT 0x100 /* Data End Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_END_STAT 0x0
+#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nSTART_BIT_ERR_STAT 0x0
+#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_BLK_END_STAT 0x0
+
+/* Bit masks for RSI_MASKx */
+
+#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_CRC_FAIL_MASK 0x0
+#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_CRC_FAIL_MASK 0x0
+#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_TIMEOUT_MASK 0x0
+#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_TIMEOUT_MASK 0x0
+#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_UNDERRUN_MASK 0x0
+#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_OVERRUN_MASK 0x0
+#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_RESP_END_MASK 0x0
+#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_SENT_MASK 0x0
+#define DAT_END_MASK 0x100 /* Data End Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_END_MASK 0x0
+#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nSTART_BIT_ERR_MASK 0x0
+#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nDAT_BLK_END_MASK 0x0
+#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCMD_ACT_MASK 0x0
+#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_ACT_MASK 0x0
+#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_ACT_MASK 0x0
+#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_FIFO_STAT_MASK 0x0
+#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_FIFO_STAT_MASK 0x0
+#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_FIFO_FULL_MASK 0x0
+#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_FIFO_FULL_MASK 0x0
+#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_FIFO_ZERO_MASK 0x0
+#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_DAT_ZERO_MASK 0x0
+#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nTX_DAT_RDY_MASK 0x0
+#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRX_FIFO_RDY_MASK 0x0
+
+/* Bit masks for RSI_FIFO_CNT */
+#define FIFO_COUNT 0x7fff /* FIFO Count */
+
+/* Bit masks for RSI_CEATA_CONTROL */
+#define CEATA_TX_CCSD 0x1 /* Send CE-ATA CCSD sequence */
+
+/* Bit masks for RSI_ESTAT */
+#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nSDIO_INT_DET 0x0
+#define SD_CARD_DET 0x10 /* SD Card Detect */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nSD_CARD_DET 0x0
+#define CEATA_INT_DET 0x20
+
+/* Bit masks for RSI_EMASK */
+#define SDIO_INT_DET_MASK 0x2 /* Mask SDIO Int Detected */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define SDIO_MSK SDIO_INT_DET_MASK /* Mask SDIO Int Detected */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nSDIO_MSK 0x0
+#define SD_CARD_DET_MASK 0x10 /* Mask Card Detect */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define SCD_MASK SD_CARD_DET_MASK /* Mask Card Detect */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nSCD_MSK 0x0
+#define CEATA_INT_DET_MASK 0x20
+
+
+/* Bit masks for SDH_CFG */
+
+/* Left in for backwards compatibility */
+#define RSI_CLK_EN 0x1
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define CLKS_EN RSI_CLK_EN /* Clocks Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nCLKS_EN 0x0
+#define SDIO4_EN 0x4 /* SDIO 4-Bit Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define SD4E SDIO4_EN /* SDIO 4-Bit Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nSD4E 0x0
+#define MW_EN 0x8 /* Moving Window Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define MWE MW_EN /* Moving Window Enable */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nMWE 0x0
+#define RSI_RST 0x10 /* SDMMC Reset */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define SD_RST RSI_RST /* SDMMC Reset */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nSD_RST 0x0
+#define PU_DAT 0x20 /* Pull-up SD_DAT */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define PUP_SDDAT PU_DAT /* Pull-up SD_DAT */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nPUP_SDDAT 0x0
+#define PU_DAT3 0x40 /* Pull-up SD_DAT3 */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define PUP_SDDAT3 PU_DAT3 /* Pull-up SD_DAT3 */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nPUP_SDDAT3 0x0
+#define PD_DAT3 0x80 /* Pull-down SD_DAT3 */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define PD_SDDAT3 PD_DAT3 /* Pull-down SD_DAT3 */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nPD_SDDAT3 0x0
+
+
+/* Bit masks for RSI_RD_WAIT_EN */
+#define SDIO_RWR 0x1 /* Read Wait Request */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define RWR SDIO_RWR /* Read Wait Request */
+/* legacy bit mask (below) provided for backwards code compatibility */
+#define nRWR 0x0
+
+/* Bit masks for RSI_PIDx */
+#define RSI_PID 0xff /* RSI Peripheral ID */
+
+
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif /* _DEF_BF518_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** defBF51x_base.h
+**
+** Copyright (C) 2009 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for the registers common to the ADSP-BF51x peripherals.
+**
+************************************************************************************
+** System MMR Register Map
+************************************************************************************/
+
+#ifndef _DEF_BF51X_H
+#define _DEF_BF51X_H
+
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4)
+#pragma diag(suppress:misra_rule_19_7)
+#endif /* _MISRA_RULES */
+
+
+/* ************************************************************************************************************** */
+/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF51x */
+/* ************************************************************************************************************** */
+
+/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
+#define PLL_CTL 0xFFC00000 /* PLL Control Register */
+#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
+#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
+#define PLL_STAT 0xFFC0000C /* PLL Status Register */
+#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
+#define CHIPID 0xFFC00014 /* Device ID Register */
+
+
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
+#define SWRST 0xFFC00100 /* Software Reset Register */
+#define SYSCR 0xFFC00104 /* System Configuration Register */
+
+#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SIC_IMASK SIC_IMASK0
+#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
+#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
+#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
+#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
+#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SIC_ISR SIC_ISR0
+#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SIC_IWR SIC_IWR0
+
+/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
+#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
+#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */
+#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */
+#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */
+#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */
+#define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */
+#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */
+
+
+/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
+#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
+#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
+#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
+
+
+/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
+#define RTC_STAT 0xFFC00300 /* RTC Status Register */
+#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
+#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
+#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
+#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
+#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
+#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
+
+
+/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
+#define UART0_THR 0xFFC00400 /* Transmit Holding register */
+#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
+#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
+#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
+#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
+#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
+#define UART0_LCR 0xFFC0040C /* Line Control Register */
+#define UART0_MCR 0xFFC00410 /* Modem Control Register */
+#define UART0_LSR 0xFFC00414 /* Line Status Register */
+#define UART0_MSR 0xFFC00418 /* Modem Status Register */
+#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
+#define UART0_GCTL 0xFFC00424 /* Global Control Register */
+
+
+/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
+#define SPI0_CTL 0xFFC00500 /* SPI Control Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SPI_CTL SPI0_CTL
+#define SPI0_FLG 0xFFC00504 /* SPI Flag register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SPI_FLG SPI0_FLG
+#define SPI0_STAT 0xFFC00508 /* SPI Status register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SPI_STAT SPI0_STAT
+#define SPI0_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SPI_TDBR SPI0_TDBR
+#define SPI0_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SPI_RDBR SPI0_RDBR
+#define SPI0_BAUD 0xFFC00514 /* SPI Baud rate Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SPI_BAUD SPI0_BAUD
+#define SPI0_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SPI_SHADOW SPI0_SHADOW
+
+
+/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
+#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
+#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
+#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
+#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
+
+#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
+#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
+#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
+#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
+
+#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
+#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
+#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
+#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
+
+#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
+#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
+#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
+#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
+
+#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
+#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
+#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
+#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
+
+#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
+#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
+#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
+#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
+
+#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
+#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
+#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
+#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
+
+#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
+#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
+#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
+#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
+
+#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
+#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
+#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
+
+
+/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
+#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
+#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
+#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
+#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
+#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
+#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
+#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
+#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
+#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
+#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
+#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
+#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
+#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
+#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
+#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
+#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
+#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
+
+
+/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
+#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
+#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
+#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
+#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
+#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
+#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
+#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
+#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
+#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
+#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
+#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
+#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
+#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
+#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
+#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
+#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
+#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
+#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
+
+
+/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
+#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
+#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
+#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
+#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
+#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
+#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
+#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
+#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
+#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
+#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
+#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
+#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
+#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
+#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
+#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
+#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
+#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
+#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
+
+
+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
+#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
+#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
+#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
+#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
+#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
+#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
+
+
+/* DMA Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */
+#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
+#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
+
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
+#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
+#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
+
+/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
+#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
+#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
+#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
+#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
+#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
+#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
+#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
+#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
+#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
+#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
+#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
+#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
+#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
+
+#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
+#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
+#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
+#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
+#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
+#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
+#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
+#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
+#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
+#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
+#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
+#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
+#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
+
+#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
+#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
+#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
+#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
+#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
+#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
+#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
+#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
+#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
+#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
+#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
+#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
+#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
+
+#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
+#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
+#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
+#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
+#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
+#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
+#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
+#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
+#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
+#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
+#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
+#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
+#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
+
+#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
+#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
+#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
+#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
+#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
+#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
+#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
+#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
+#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
+#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
+#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
+#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
+#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
+
+#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
+#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
+#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
+#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
+#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
+#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
+#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
+#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
+#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
+#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
+#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
+#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
+#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
+
+#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
+#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
+#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
+#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
+#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
+#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
+#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
+#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
+#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
+#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
+#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
+#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
+#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
+
+#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
+#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
+#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
+#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
+#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
+#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
+#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
+#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
+#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
+#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
+#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
+#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
+#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
+
+#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
+#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
+#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
+#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
+#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
+#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
+#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
+#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
+#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
+#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
+#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
+#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
+#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
+
+#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
+#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
+#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
+#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
+#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
+#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
+#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
+#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
+#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
+#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
+#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
+#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
+#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
+
+#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
+#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
+#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
+#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
+#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
+#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
+#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
+#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
+#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
+#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
+#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
+#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
+#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
+
+#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
+#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
+#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
+#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
+#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
+#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
+#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
+#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
+#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
+#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
+#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
+#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
+#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
+
+#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
+#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
+#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
+#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
+#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
+#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
+#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register*/
+#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
+#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
+#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
+#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
+#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
+
+#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
+#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
+#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
+#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
+#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
+#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
+#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
+#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
+#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
+#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
+#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
+
+#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
+#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
+#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
+#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
+#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
+#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
+#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register*/
+#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
+#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
+#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
+#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
+#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
+
+#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
+#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
+#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
+#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
+#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
+#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
+#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
+#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
+#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
+#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
+#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
+
+
+/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
+#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
+#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
+#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
+#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
+#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
+
+
+/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
+#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
+#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
+#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
+#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
+#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
+#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
+#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
+#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
+#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
+#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
+#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
+#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
+#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
+#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
+#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
+#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
+
+
+/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
+#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
+#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
+#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
+#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
+#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
+#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
+#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
+#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
+#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
+#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
+#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
+#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
+#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
+#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
+#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
+#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
+#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
+
+
+/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
+#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
+#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
+#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
+#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
+#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
+#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
+#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
+#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
+#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
+#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
+#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
+#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
+#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
+#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
+#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
+#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
+#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
+
+
+/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
+#define UART1_THR 0xFFC02000 /* Transmit Holding register */
+#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
+#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
+#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
+#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
+#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
+#define UART1_LCR 0xFFC0200C /* Line Control Register */
+#define UART1_MCR 0xFFC02010 /* Modem Control Register */
+#define UART1_LSR 0xFFC02014 /* Line Status Register */
+#define UART1_MSR 0xFFC02018 /* Modem Status Register */
+#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
+#define UART1_GCTL 0xFFC02024 /* Global Control Register */
+
+
+/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
+#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
+#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
+#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
+
+
+/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
+#define PORTF_MUX 0xFFC03210 /* Port F mux control */
+#define PORTG_MUX 0xFFC03214 /* Port G mux control */
+#define PORTH_MUX 0xFFC03218 /* Port H mux control */
+#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */
+#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */
+#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */
+#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */
+#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */
+#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */
+#define NONGPIO_DRIVE 0xFFC03280 /* Misc Port drive strength control */
+#define NONGPIO_HYSTERESIS 0xFFC03288 /* Misc Port Schmitt Trigger control */
+
+
+/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
+#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
+#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
+#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
+#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
+#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
+#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
+#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
+
+#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
+#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
+#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
+#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
+#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
+#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
+#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
+
+
+/* SPI1 Controller (0xFFC03400 - 0xFFC034FF) */
+#define SPI1_CTL 0xFFC03400 /* SPI0 Control Register */
+#define SPI1_FLG 0xFFC03404 /* SPI0 Flag register */
+#define SPI1_STAT 0xFFC03408 /* SPI0 Status register */
+#define SPI1_TDBR 0xFFC0340C /* SPI0 Transmit Data Buffer Register */
+#define SPI1_RDBR 0xFFC03410 /* SPI0 Receive Data Buffer Register */
+#define SPI1_BAUD 0xFFC03414 /* SPI0 Baud rate Register */
+#define SPI1_SHADOW 0xFFC03418 /* SPI0_RDBR Shadow Register */
+
+
+/* Counter Registers (0xFFC03500 - 0xFFC035FF) */
+#define CNT_CONFIG 0xFFC03500 /* Configuration Register */
+#define CNT_IMASK 0xFFC03504 /* Interrupt Mask Register */
+#define CNT_STATUS 0xFFC03508 /* Status Register */
+#define CNT_COMMAND 0xFFC0350C /* Command Register */
+#define CNT_DEBOUNCE 0xFFC03510 /* Debounce Register */
+#define CNT_COUNTER 0xFFC03514 /* Counter Register */
+#define CNT_MAX 0xFFC03518 /* Boundry Value Register - max count */
+#define CNT_MIN 0xFFC0351C /* Boundry Value Register - min count */
+
+
+/* OTP/FUSE Registers (0xFFC03600 - 0xFFC036FF) */
+#define OTP_CONTROL 0xFFC03600 /* OTPSEC Fuse Control */
+#define OTP_BEN 0xFFC03604 /* OTPSEC Fuse Byte Enable */
+#define OTP_STATUS 0xFFC03608 /* OTPSEC Fuse Status */
+#define OTP_TIMING 0xFFC0360C /* OTPSEC Fuse SCLK Divider */
+
+/* Security Registers */
+#define SECURE_SYSSWT 0xFFC03620 /* OTPSEC Secure System Switches */
+#define SECURE_CONTROL 0xFFC03624 /* OTPSEC Secure Control */
+#define SECURE_STATUS 0xFFC03628 /* OTPSEC Secure Status */
+
+/* OTP Read/Write Data Buffer Registers */
+#define OTP_DATA0 0xFFC03680 /* OTP Read Write buffer */
+#define OTP_DATA1 0xFFC03684 /* OTP Read Write buffer */
+#define OTP_DATA2 0xFFC03688 /* OTP Read Write buffer */
+#define OTP_DATA3 0xFFC0368C /* OTP Read Write buffer */
+
+
+/* Motor Control PWM Registers (0xFFC03700 - 0xFFC037FF) */
+#define PWM_CTRL 0xFFC03700 /* PWM Control Register */
+#define PWM_STAT 0xFFC03704 /* PWM Status Register */
+#define PWM_TM 0xFFC03708 /* PWM Period Register */
+#define PWM_DT 0xFFC0370C /* PWM Dead Time Register */
+#define PWM_GATE 0xFFC03710 /* PWM Chopping Control */
+#define PWM_CHA 0xFFC03714 /* PWM Channel A Duty Control */
+#define PWM_CHB 0xFFC03718 /* PWM Channel B Duty Control */
+#define PWM_CHC 0xFFC0371C /* PWM Channel C Duty Control */
+#define PWM_SEG 0xFFC03720 /* PWM Crossover and Output Enable */
+#define PWM_SYNCWT 0xFFC03724 /* PWM Sync pulse width control */
+#define PWM_CHAL 0xFFC03728 /* PWM Channel AL Duty Control (SR mode only) */
+#define PWM_CHBL 0xFFC0372C /* PWM Channel BL Duty Control (SR mode only) */
+#define PWM_CHCL 0xFFC03730 /* PWM Channel CL Duty Control (SR mode only) */
+#define PWM_LSI 0xFFC03734 /* Low Side Invert (SR mode only) */
+#define PWM_STAT2 0xFFC03738 /* PWM Status Register */
+
+
+
+/******************************************************************************************************************
+** System MMR Register Bits And Macros
+**
+** Disclaimer: All macros are intended to make C and Assembly code more readable.
+** Use these macros carefully, as any that do left shifts for field
+** depositing will result in the lower order bits being destroyed. Any
+** macro that shifts left to properly position the bit-field should be
+** used as part of an OR to initialize a register and NOT as a dynamic
+** modifier UNLESS the lower order bits are saved and ORed back in when
+** the macro is used.
+*******************************************************************************************************************/
+
+/************************************** PLL AND RESET MASKS *******************************************************/
+
+/* PLL_CTL Masks */
+#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
+#define PLL_OFF 0x0002 /* PLL Not Powered */
+#define STOPCK 0x0008 /* Core Clock Off */
+#define PDWN 0x0020 /* Enter Deep Sleep Mode */
+#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
+#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
+#define BYPASS 0x0100 /* Bypass the PLL */
+#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
+
+/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
+#ifdef _MISRA_RULES
+#define SET_MSEL(x) (((x)&0x3Fu) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
+#else
+#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
+#endif /* _MISRA_RULES */
+
+/* PLL_DIV Masks */
+#define SSEL 0x000F /* System Select */
+#define CSEL 0x0030 /* Core Select */
+#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
+#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
+#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
+#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
+
+/* PLL_DIV Macros */
+#ifdef _MISRA_RULES
+#define SET_SSEL(x) ((x)&0xFu) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
+#else
+#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
+#endif /* _MISRA_RULES */
+
+/* VR_CTL Masks */
+#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */
+#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
+
+#define VLEV 0x00F0 /* Internal Voltage Level - Only Program Values Within Specifications */
+#define VLEV_085 0x0040 /* VLEV = 0.85 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_090 0x0050 /* VLEV = 0.90 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_095 0x0060 /* VLEV = 0.95 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_100 0x0070 /* VLEV = 1.00 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_105 0x0080 /* VLEV = 1.05 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_110 0x0090 /* VLEV = 1.10 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_115 0x00A0 /* VLEV = 1.15 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_120 0x00B0 /* VLEV = 1.20 V (See Datasheet for Regulator Tolerance) */
+
+#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
+/* no USB WAKE UP */
+#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
+#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
+#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */
+#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */
+
+/* PLL_STAT Masks */
+#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
+#define FULL_ON 0x0002 /* Processor In Full On Mode */
+#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
+#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
+#define VSTAT 0x0080 /* Voltage Regulator Status: Regulator at programmed voltage */
+
+/* SWRST Masks */
+#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
+#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
+#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
+#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
+#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
+
+/* SYSCR Masks */
+#define BMODE_BYPASS 0x0000 /* Bypass boot ROM, execute from 16-bit external memory */
+#define BMODE_FLASH 0x0001 /* Use Boot ROM to load from 8-bit or 16-bit flash */
+#define BMODE_SPIMEM 0x0003 /* Boot from serial SPI memory */
+#define BMODE_SPIHOST 0x0004 /* Boot from SPI0 host (slave mode) */
+#define BMODE_TWIMEM 0x0005 /* Boot from serial TWI memory */
+#define BMODE_TWIHOST 0x0006 /* Boot from TWI0 host (slave mode) */
+#define BMODE_UART0HOST 0x0007 /* Boot from UART0 host */
+#define BMODE_UART1HOST 0x0008 /* Boot from UART1 host */
+#define BMODE_SDRAMMEM 0x000A /* Boot from SDRAM memory (warm boot) */
+#define BMODE_OTPMEM 0x000B /* Boot from OTP memory */
+#define BMODE_HOSTDMA_ACK 0x000E /* Boot from 16-bit host DMA (ACK mode) */
+#define BMODE_HOSTDMA_INT 0x000F /* Boot from 8-bit host DMA (INT mode) */
+#define BMODE 0x000F /* Boot Mode. Mirror of BMODE Mode Pins */
+
+#define BCODE 0x00F0
+#define BCODE_NORMAL 0x0000 /* normal boot, update PLL/VR, quickboot as by WURESET */
+#define BCODE_NOBOOT 0x0010 /* bypass boot, don't update PLL/VR */
+#define BCODE_QUICKBOOT 0x0020 /* quick boot, overrule WURESET, don't update PLL/VR */
+#define BCODE_ALLBOOT 0x0040 /* no quick boot, overrule WURESET, don't update PLL/VR */
+#define BCODE_FULLBOOT 0x0060 /* no quick boot, overrule WURESET, update PLL/VR */
+
+#define DCB1_PRIO 0x0100 /* DCB1 requests are urgent */
+#define DCB_ROT_PRIO 0x0200 /* enable rotating DCB priority */
+#define DEB1_PRIO 0x0400 /* DEB1 requests are urgent */
+#define DEB_ROT_PRIO 0x0800 /* enable rotating DEB priority */
+
+#define WURESET 0x1000 /* wakeup event since last hardware reset */
+#define DFRESET 0x2000 /* recent reset was due to a double fault event */
+#define WDRESET 0x4000 /* recent reset was due to a watchdog event */
+#define SWRESET 0x8000 /* recent reset was issued by software */
+
+/********************************* SYSTEM INTERRUPT CONTROLLER MASKS *********************************************/
+
+/* Peripheral Masks For SIC_ISR0, SIC_IWR0, SIC_IMASK0 */
+#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
+#define IRQ_DMA_ERR0 0x00000002 /* Error Interrupt (DMA error 0 interrupt (generic)) */
+#define IRQ_DMAR0 0x00000004 /* DMAR0 Block (DMAR0 block interrupt) */
+#define IRQ_DMAR1 0x00000008 /* DMAR1 Block (DMAR1 block interrupt) */
+#define IRQ_DMAR0_ERR 0x00000010 /* Error Interrupt (DMAR0 overflow error interrupt) */
+#define IRQ_DMAR1_ERR 0x00000020 /* Error Interrupt (DMAR1 overflow error interrupt) */
+#define IRQ_PPI_ERR 0x00000040 /* Error Interrupt (PPI error interrupt) */
+#define IRQ_MAC_ERR 0x00000080 /* Error Interrupt (MAC status interrupt) */
+#define IRQ_SPORT0_ERR 0x00000100 /* Error Interrupt (SPORT0 status interrupt) */
+#define IRQ_SPORT1_ERR 0x00000200 /* Error Interrupt (SPORT1 status interrupt) */
+#define IRQ_PTP_ERR 0x00000400 /* Error Interrupt (PTP error interrupt) */
+
+#define IRQ_UART0_ERR 0x00001000 /* Error Interrupt (UART0 status interrupt) */
+#define IRQ_UART1_ERR 0x00002000 /* Error Interrupt (UART1 status interrupt) */
+#define IRQ_RTC 0x00004000 /* Real Time Clock Interrupt */
+#define IRQ_DMA0 0x00008000 /* DMA channel 0 (PPI/NFC) Interrupt */
+#define IRQ_DMA3 0x00010000 /* DMA Channel 3 (SPORT0 RX) Interrupt */
+#define IRQ_DMA4 0x00020000 /* DMA Channel 4 (SPORT0 TX) Interrupt */
+#define IRQ_DMA5 0x00040000 /* DMA Channel 5 (SPORT1 RX) Interrupt */
+#define IRQ_DMA6 0x00080000 /* DMA Channel 6 (SPORT1 TX) Interrupt */
+#define IRQ_TWI 0x00100000 /* TWI Interrupt */
+#define IRQ_DMA7 0x00200000 /* DMA Channel 7 (SPI) Interrupt */
+#define IRQ_DMA8 0x00400000 /* DMA Channel 8 (UART0 RX) Interrupt */
+#define IRQ_DMA9 0x00800000 /* DMA Channel 9 (UART0 TX) Interrupt */
+#define IRQ_DMA10 0x01000000 /* DMA Channel 10 (UART1 RX) Interrupt */
+#define IRQ_DMA11 0x02000000 /* DMA Channel 11 (UART1 TX) Interrupt */
+#define IRQ_OTP 0x04000000 /* OTP Interrupt */
+#define IRQ_CNT 0x08000000 /* GP Counter Interrupt */
+#define IRQ_DMA1 0x10000000 /* DMA Channel 1 (EthernetRX/HOSTDP) Interrupt */
+#define IRQ_PFA_PORTH 0x20000000 /* PF Port H Interrupt A */
+#define IRQ_DMA2 0x40000000 /* DMA Channel 2 (Ethernet TX/NFC) Interrupt */
+#define IRQ_PFB_PORTH 0x80000000 /* PF Port H Interrupt B */
+
+/* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1 */
+#define IRQ_TIMER0 0x00000001 /* Timer 0 Interrupt */
+#define IRQ_TIMER1 0x00000002 /* Timer 1 Interrupt */
+#define IRQ_TIMER2 0x00000004 /* Timer 2 Interrupt */
+#define IRQ_TIMER3 0x00000008 /* Timer 3 Interrupt */
+#define IRQ_TIMER4 0x00000010 /* Timer 4 Interrupt */
+#define IRQ_TIMER5 0x00000020 /* Timer 5 Interrupt */
+#define IRQ_TIMER6 0x00000040 /* Timer 6 Interrupt */
+#define IRQ_TIMER7 0x00000080 /* Timer 7 Interrupt */
+#define IRQ_PFA_PORTG 0x00000100 /* PF Port G Interrupt A */
+#define IRQ_PFB_PORTG 0x00000200 /* PF Port G Interrupt B */
+#define IRQ_DMA12 0x00000400 /* DMA Channels 12 (MDMA0 Destination) TX Interrupt */
+#define IRQ_DMA13 0x00000400 /* DMA Channels 13 (MDMA0 Source) RX Interrupt */
+#define IRQ_DMA14 0x00000800 /* DMA Channels 14 (MDMA1 Destination) TX Interrupt */
+#define IRQ_DMA15 0x00000800 /* DMA Channels 15 (MDMA1 Source) RX Interrupt */
+#define IRQ_WDOG 0x00001000 /* Software Watchdog Timer Interrupt */
+#define IRQ_PFA_PORTF 0x00002000 /* PF Port F Interrupt A */
+#define IRQ_PFB_PORTF 0x00004000 /* PF Port F Interrupt B */
+#define IRQ_SPI0_ERR 0x00008000 /* Error Interrupt (SPI0 status interrupt) */
+#define IRQ_SPI1_ERR 0x00010000 /* Error Interrupt (SPI1 status interrupt) */
+
+#define IRQ_RSI_INT0 0x00080000 /* USB EINT interrupt */
+#define IRQ_RSI_INT1 0x00100000 /* USB INT0 interrupt */
+#define IRQ_PWM_TRIPINT 0x00200000 /* USB INT1 interrupt */
+#define IRQ_PWM_SYNCINT 0x00400000 /* USB INT1 interrupt */
+#define IRQ_PTP_STATINT 0x00800000 /* USB DMAINT interrupt */
+
+
+/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
+#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
+#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
+/* x = pos 0 to 31, for 32-63 use value-32 */
+#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
+#define IWR_DISABLE(x) (0xFFFFFFFF^(1<<(x))) /* Wakeup Disable Peripheral #x */
+
+
+#ifdef _MISRA_RULES
+#define _MF15 0xFu
+#define _MF7 7u
+#else
+#define _MF15 0xF
+#define _MF7 7
+#endif /* _MISRA_RULES */
+
+
+/* SIC_IAR0 Macros*/
+#define P0_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #0 assigned IVG #x */
+#define P1_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #1 assigned IVG #x */
+#define P2_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #2 assigned IVG #x */
+#define P3_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #3 assigned IVG #x */
+#define P4_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #4 assigned IVG #x */
+#define P5_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #5 assigned IVG #x */
+#define P6_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #6 assigned IVG #x */
+#define P7_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #7 assigned IVG #x */
+
+/* SIC_IAR1 Macros*/
+#define P8_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #8 assigned IVG #x */
+#define P9_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #9 assigned IVG #x */
+#define P10_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #10 assigned IVG #x */
+#define P11_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #11 assigned IVG #x */
+#define P12_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #12 assigned IVG #x */
+#define P13_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #13 assigned IVG #x */
+
+/* SIC_IAR2 Macros*/
+#define P14_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #14 assigned IVG #x */
+#define P15_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #15 assigned IVG #x */
+#define P16_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #16 assigned IVG #x */
+#define P17_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #17 assigned IVG #x */
+#define P18_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #18 assigned IVG #x */
+#define P19_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #19 assigned IVG #x */
+#define P20_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #20 assigned IVG #x */
+#define P21_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #21 assigned IVG #x */
+
+/* SIC_IAR3 Macros*/
+#define P22_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #22 assigned IVG #x */
+#define P23_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #23 assigned IVG #x */
+#define P24_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #24 assigned IVG #x */
+#define P25_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #25 assigned IVG #x */
+#define P26_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #26 assigned IVG #x */
+#define P27_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #27 assigned IVG #x */
+#define P28_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #28 assigned IVG #x */
+#define P29_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #29 assigned IVG #x */
+
+/* SIC_IAR4 Macros*/
+#define P30_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #30 assigned IVG #x */
+#define P31_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #31 assigned IVG #x */
+#define P32_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #32 assigned IVG #x */
+#define P33_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #33 assigned IVG #x */
+#define P34_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #34 assigned IVG #x */
+#define P35_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #35 assigned IVG #x */
+#define P36_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #36 assigned IVG #x */
+#define P37_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #37 assigned IVG #x */
+
+/* SIC_IAR5 Macros*/
+#define P38_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #38 assigned IVG #x */
+#define P39_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #39 assigned IVG #x */
+#define P40_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #40 assigned IVG #x */
+#define P41_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #41 assigned IVG #x */
+#define P42_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #42 assigned IVG #x */
+#define P43_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #43 assigned IVG #x */
+#define P44_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #44 assigned IVG #x */
+#define P45_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #45 assigned IVG #x */
+
+/* SIC_IAR6 Macros*/
+#define P46_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #46 assigned IVG #x */
+#define P47_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #47 assigned IVG #x */
+#define P48_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #48 assigned IVG #x */
+#define P49_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #49 assigned IVG #x */
+#define P50_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #50 assigned IVG #x */
+#define P51_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #51 assigned IVG #x */
+#define P52_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #52 assigned IVG #x */
+#define P53_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #53 assigned IVG #x */
+
+/* SIC_IAR7 Macros*/
+#define P54_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #54 assigned IVG #x */
+#define P55_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #55 assigned IVG #x */
+#define P56_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #56 assigned IVG #x */
+#define P57_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #57 assigned IVG #x */
+#define P58_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #58 assigned IVG #x */
+#define P59_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #59 assigned IVG #x */
+#define P60_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #60 assigned IVG #x */
+#define P61_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #61 assigned IVG #x */
+
+
+/* SIC_IMASK0 Masks*/
+#define SIC_UNMASK0_ALL 0x00000000 /* Unmask all peripheral interrupts */
+#define SIC_MASK0_ALL 0xFFFFF3FF /* Mask all peripheral interrupts */
+#ifdef _MISRA_RULES
+#define SIC_MASK0(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
+#define SIC_UNMASK0(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))/*Unmask Peripheral #x interrupt*/
+#else
+#define SIC_MASK0(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
+#define SIC_UNMASK0(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F)))/* Unmask Peripheral #x interrupt */
+#endif /* _MISRA_RULES */
+
+/* SIC_IMASK1 Masks*/
+#define SIC_UNMASK1_ALL 0x00000000 /* Unmask all peripheral interrupts */
+#define SIC_MASK1_ALL 0xFFFFFF /* Mask all peripheral interrupts */
+#ifdef _MISRA_RULES
+#define SIC_MASK1(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
+#define SIC_UNMASK1(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))/*Unmask Peripheral #x interrupt*/
+#else
+#define SIC_MASK1(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
+#define SIC_UNMASK1(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F)))/* Unmask Peripheral #x interrupt */
+#endif /* _MISRA_RULES */
+
+
+/* SIC_IWR0 Masks*/
+#define IWR0_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
+#define IWR0_ENABLE_ALL 0xFFFFF3FF /* Wakeup Enable all peripherals */
+#ifdef _MISRA_RULES
+#define IWR0_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
+#define IWR0_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))/*Wakeup Disable Peripheral #x */
+#else
+#define IWR0_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
+#define IWR0_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F)))/* Wakeup Disable Peripheral #x */
+#endif /* _MISRA_RULES */
+
+/* SIC_IWR1 Masks*/
+#define IWR1_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
+#define IWR1_ENABLE_ALL 0xFFFFFF /* Wakeup Enable all peripherals */
+#ifdef _MISRA_RULES
+#define IWR1_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
+#define IWR1_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))/* Wakeup Disable Peripheral #x*/
+#else
+#define IWR1_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
+#define IWR1_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F)))/* Wakeup Disable Peripheral #x */
+#endif /* _MISRA_RULES */
+
+
+/* ************************************** WATCHDOG TIMER MASKS ****************************************************/
+
+/* Watchdog Timer WDOG_CTL Register Masks */
+#ifdef _MISRA_RULES
+#define WDEV(x) (((x)<<1) & 0x0006u) /* event generated on roll over */
+#else
+#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
+#endif /* _MISRA_RULES */
+
+#define WDEV_RESET 0x0000 /* generate reset event on roll over */
+#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
+#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
+#define WDEV_NONE 0x0006 /* no event on roll over */
+#define WDEN 0x0FF0 /* enable watchdog */
+#define WDDIS 0x0AD0 /* disable watchdog */
+#define WDRO 0x8000 /* watchdog rolled over latch */
+
+/* depreciated WDOG_CTL Register Masks for legacy code */
+#define ICTL WDEV
+#define ENABLE_RESET WDEV_RESET
+#define WDOG_RESET WDEV_RESET
+#define ENABLE_NMI WDEV_NMI
+#define WDOG_NMI WDEV_NMI
+#define ENABLE_GPI WDEV_GPI
+#define WDOG_GPI WDEV_GPI
+#define DISABLE_EVT WDEV_NONE
+#define WDOG_NONE WDEV_NONE
+
+#define TMR_EN WDEN
+#define TMR_DIS WDDIS
+#define TRO WDRO
+#define ICTL_P0 0x01
+#define ICTL_P1 0x02
+#define TRO_P 0x0F
+
+
+/* ************************************** REAL TIME CLOCK MASKS *************************************************/
+
+/* RTC_STAT and RTC_ALARM Masks*/
+#define RTC_SEC 0x0000003F /* Real-Time Clock Seconds */
+#define RTC_MIN 0x00000FC0 /* Real-Time Clock Minutes */
+#define RTC_HR 0x0001F000 /* Real-Time Clock Hours */
+#define RTC_DAY 0xFFFE0000 /* Real-Time Clock Days */
+
+/* RTC_ALARM Macro z=day y=hr x=min w=sec */
+#ifdef _MISRA_RULES
+#define SET_ALARM(z,y,x,w) ((((z)&0x7FFFu)<<0x11)|(((y)&0x1Fu)<<0xC)|(((x)&0x3Fu)<<0x6)|((w)&0x3Fu))
+#else
+#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
+#endif /* _MISRA_RULES */
+
+/* RTC_ICTL and RTC_ISTAT Masks*/
+#define STOPWATCH 0x0001 /* Stopwatch Interrupt Enable */
+#define ALARM 0x0002 /* Alarm Interrupt Enable */
+#define SECOND 0x0004 /* Seconds (1 Hz) Interrupt Enable */
+#define MINUTE 0x0008 /* Minutes Interrupt Enable */
+#define HOUR 0x0010 /* Hours Interrupt Enable */
+#define DAY 0x0020 /* 24 Hours (Days) Interrupt Enable */
+#define DAY_ALARM 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
+#define WRITE_PENDING 0x4000 /* Write Pending Status */
+#define WRITE_COMPLETE 0x8000 /* Write Complete Interrupt Enable */
+
+/* RTC_FAST / RTC_PREN Mask */
+#define PREN 0x0001 /* Enable Prescaler, RTC Runs @1 Hz */
+
+
+/* ************************************ UART CONTROLLER MASKS *****************************************************/
+
+/* UARTx_LCR Masks*/
+#ifdef _MISRA_RULES
+#define WLS(x) (((x)-5u) & 0x03u) /* Word Length Select */
+#else
+#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
+#endif /* _MISRA_RULES */
+
+#define STB 0x04 /* Stop Bits */
+#define PEN 0x08 /* Parity Enable */
+#define EPS 0x10 /* Even Parity Select */
+#define STP 0x20 /* Stick Parity */
+#define SB 0x40 /* Set Break */
+#define DLAB 0x80 /* Divisor Latch Access */
+
+/* UARTx_MCR Mask */
+#define LOOP_ENA 0x10 /* Loopback Mode Enable */
+#define LOOP_ENA_P 0x04
+
+/* UARTx_LSR Masks */
+#define DR 0x01 /* Data Ready */
+#define OE 0x02 /* Overrun Error */
+#define PE 0x04 /* Parity Error */
+#define FE 0x08 /* Framing Error */
+#define BI 0x10 /* Break Interrupt */
+#define THRE 0x20 /* THR Empty */
+#define TEMT 0x40 /* TSR and UART_THR Empty */
+
+/* UARTx_IER Masks*/
+#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
+#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
+#define ELSI 0x04 /* Enable RX Status Interrupt */
+
+/* UARTx_IIR Masks*/
+#define NINT 0x01 /* Pending Interrupt */
+#define STATUS 0x06 /* Highest Priority Pending Interrupt */
+
+/* UARTx_GCTL Masks*/
+#define UCEN 0x01 /* Enable UARTx Clocks */
+#define IREN 0x02 /* Enable IrDA Mode */
+#define TPOLC 0x04 /* IrDA TX Polarity Change */
+#define RPOLC 0x08 /* IrDA RX Polarity Change */
+#define FPE 0x10 /* Force Parity Error On Transmit */
+#define FFE 0x20 /* Force Framing Error On Transmit */
+
+/* Bit masks for UART Divisor Latch Registers: UARTx_DLL & UARTx_DLH */
+#define UARTDLL 0x00FF /* Divisor Latch Low Byte */
+#define UARTDLH 0xFF00 /* Divisor Latch High Byte */
+
+
+/******************************** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ***************************************/
+
+/* SPI_CTL Masks*/
+#define TIMOD 0x0003 /* Transfer Initiate Mode */
+#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
+#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
+#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
+#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
+#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
+#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
+#define PSSE 0x0010 /* Slave-Select Input Enable */
+#define EMISO 0x0020 /* Enable MISO As Output */
+#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
+#define LSBF 0x0200 /* LSB First */
+#define CPHA 0x0400 /* Clock Phase */
+#define CPOL 0x0800 /* Clock Polarity */
+#define MSTR 0x1000 /* Master/Slave* */
+#define WOM 0x2000 /* Write Open Drain Master */
+#define SPE 0x4000 /* SPI Enable */
+
+/* SPI_FLG Masks*/
+#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */
+#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */
+#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */
+#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */
+#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */
+#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */
+#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */
+#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */
+#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */
+#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */
+#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */
+#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */
+#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */
+#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */
+
+/* SPI_STAT Masks*/
+#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */
+#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */
+#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */
+#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */
+#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */
+#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */
+#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */
+
+
+/*********************************** GENERAL PURPOSE TIMER MASKS ************************************************/
+/* TIMER_ENABLE Masks*/
+#define TIMEN0 0x0001 /* Enable Timer 0 */
+#define TIMEN1 0x0002 /* Enable Timer 1 */
+#define TIMEN2 0x0004 /* Enable Timer 2 */
+#define TIMEN3 0x0008 /* Enable Timer 3 */
+#define TIMEN4 0x0010 /* Enable Timer 4 */
+#define TIMEN5 0x0020 /* Enable Timer 5 */
+#define TIMEN6 0x0040 /* Enable Timer 6 */
+#define TIMEN7 0x0080 /* Enable Timer 7 */
+
+/* TIMER_DISABLE Masks*/
+#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
+#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
+#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
+#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
+#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
+#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
+#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
+#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
+
+/* TIMER_STATUS Masks*/
+#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
+#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
+#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
+#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
+#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
+#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
+#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
+#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
+#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
+#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
+#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
+#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
+#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
+#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
+#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
+#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
+#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
+#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
+#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
+#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
+#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
+#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
+#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
+#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define TOVL_ERR0 TOVF_ERR0
+#define TOVL_ERR1 TOVF_ERR1
+#define TOVL_ERR2 TOVF_ERR2
+#define TOVL_ERR3 TOVF_ERR3
+#define TOVL_ERR4 TOVF_ERR4
+#define TOVL_ERR5 TOVF_ERR5
+#define TOVL_ERR6 TOVF_ERR6
+#define TOVL_ERR7 TOVF_ERR7
+
+/* TIMERx_CONFIG Masks */
+#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
+#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
+#define EXT_CLK 0x0003 /* External Clock Mode */
+#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
+#define PERIOD_CNT 0x0008 /* Period Count */
+#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
+#define TIN_SEL 0x0020 /* Timer Input Select */
+#define OUT_DIS 0x0040 /* Output Pad Disable */
+#define CLK_SEL 0x0080 /* Timer Clock Select */
+#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
+#define EMU_RUN 0x0200 /* Emulation Behavior Select */
+#define ERR_TYP 0xC000 /* Error Type */
+
+
+/* ************************************* GPIO PORTS F, G, H MASKS **********************************************/
+
+/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
+/* Port F Masks */
+#define PF0 0x0001
+#define PF1 0x0002
+#define PF2 0x0004
+#define PF3 0x0008
+#define PF4 0x0010
+#define PF5 0x0020
+#define PF6 0x0040
+#define PF7 0x0080
+#define PF8 0x0100
+#define PF9 0x0200
+#define PF10 0x0400
+#define PF11 0x0800
+#define PF12 0x1000
+#define PF13 0x2000
+#define PF14 0x4000
+#define PF15 0x8000
+
+/* Port G Masks */
+#define PG0 0x0001
+#define PG1 0x0002
+#define PG2 0x0004
+#define PG3 0x0008
+#define PG4 0x0010
+#define PG5 0x0020
+#define PG6 0x0040
+#define PG7 0x0080
+#define PG8 0x0100
+#define PG9 0x0200
+#define PG10 0x0400
+#define PG11 0x0800
+#define PG12 0x1000
+#define PG13 0x2000
+#define PG14 0x4000
+#define PG15 0x8000
+
+/* Port H Masks */
+#define PH0 0x0001
+#define PH1 0x0002
+#define PH2 0x0004
+#define PH3 0x0008
+#define PH4 0x0010
+#define PH5 0x0020
+#define PH6 0x0040
+#define PH7 0x0080
+#define PH8 0x0100
+
+/* ************************************** SERIAL PORT MASKS *****************************************************/
+/* SPORTx_TCR1 Masks */
+#define TSPEN 0x0001 /* Transmit Enable */
+#define ITCLK 0x0002 /* Internal Transmit Clock Select */
+#define DTYPE_NORM 0x0004 /* Data Format Normal */
+#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
+#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
+#define TLSBIT 0x0010 /* Transmit Bit Order */
+#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
+#define TFSR 0x0400 /* Transmit Frame Sync Required Select */
+#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
+#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
+#define LATFS 0x2000 /* Late Transmit Frame Sync Select */
+#define TCKFE 0x4000 /* Clock Falling Edge Select */
+
+/* SPORTx_TCR2 Masks and Macro */
+#ifdef _MISRA_RULES
+#define SLEN(x) ((x)&0x1Fu) /* SPORT TX Word Length (2 - 31) */
+#else
+#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
+#endif /* _MISRA_RULES */
+
+#define TXSE 0x0100 /* TX Secondary Enable */
+#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
+#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
+
+/* SPORTx_RCR1 Masks */
+#define RSPEN 0x0001 /* Receive Enable */
+#define IRCLK 0x0002 /* Internal Receive Clock Select */
+#define DTYPE_NORM 0x0004 /* Data Format Normal */
+#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
+#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
+#define RLSBIT 0x0010 /* Receive Bit Order */
+#define IRFS 0x0200 /* Internal Receive Frame Sync Select */
+#define RFSR 0x0400 /* Receive Frame Sync Required Select */
+#define LRFS 0x1000 /* Low Receive Frame Sync Select */
+#define LARFS 0x2000 /* Late Receive Frame Sync Select */
+#define RCKFE 0x4000 /* Clock Falling Edge Select */
+
+/* SPORTx_RCR2 Masks */
+#ifdef _MISRA_RULES
+#define SLEN(x) ((x)&0x1Fu) /* SPORT RX Word Length (2 - 31) */
+#else
+#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
+#endif /* _MISRA_RULES */
+
+#define RXSE 0x0100 /* RX Secondary Enable */
+#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
+#define RRFST 0x0400 /* Right-First Data Order */
+
+/* SPORTx_STAT Masks */
+#define RXNE 0x0001 /* Receive FIFO Not Empty Status */
+#define RUVF 0x0002 /* Sticky Receive Underflow Status */
+#define ROVF 0x0004 /* Sticky Receive Overflow Status */
+#define TXF 0x0008 /* Transmit FIFO Full Status */
+#define TUVF 0x0010 /* Sticky Transmit Underflow Status */
+#define TOVF 0x0020 /* Sticky Transmit Overflow Status */
+#define TXHRE 0x0040 /* Transmit Hold Register Empty */
+
+/* SPORTx_MCMC1 Macros */
+#ifdef _MISRA_RULES
+#define WOFF(x) ((x) & 0x3FFu) /* Multichannel Window Offset Field */
+/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits*/
+#define WSIZE(x) (((((x)>>0x3)-1u)&0xFu) << 0xC) /* Multichannel Window Size = (x/8)-1 */
+#else
+#define WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
+/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
+#define WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
+#endif /* _MISRA_RULES */
+
+/* SPORTx_MCMC2 Masks */
+#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
+#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
+#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
+#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
+#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
+#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
+#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
+#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
+#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
+#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
+#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
+#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
+#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
+#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
+#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
+#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
+#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
+#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
+#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
+#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
+#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
+#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
+#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
+
+
+/*********************************** ASYNCHRONOUS MEMORY CONTROLLER MASKS ***************************************/
+
+/* EBIU_AMGCTL Masks */
+#define AMCKEN 0x0001 /* Enable CLKOUT */
+#define AMBEN 0x000e /* Async bank enable */
+#define AMBEN_NONE 0x0000 /* All Banks Disabled */
+#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
+#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
+#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
+#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
+#define CDPRIO 0x0100 /* DMA has priority over core for for external accesses */
+
+/* EBIU_AMBCTL0 Masks */
+#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
+#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
+#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
+#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
+#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
+#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
+#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
+#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
+#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
+#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
+#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
+#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
+#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
+#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
+#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
+#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
+#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
+#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
+#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
+#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
+#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
+#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
+#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
+#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
+#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
+#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
+#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
+#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
+#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
+#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
+#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
+#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
+#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
+#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
+#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
+#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
+#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
+#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
+#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
+#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
+#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
+#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
+#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
+#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
+
+#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
+#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
+#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
+#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
+#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
+#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
+#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
+#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
+#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
+#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
+#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
+#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
+#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
+#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
+#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
+#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
+#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
+#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
+#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
+#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
+#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
+#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
+#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
+#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
+#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
+#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
+#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
+#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
+#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
+#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
+#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
+#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
+#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
+#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
+#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
+#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
+#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
+#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
+#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
+#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
+#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
+#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
+#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
+#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
+
+/* EBIU_AMBCTL1 Masks */
+#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
+#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
+#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
+#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
+#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
+#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
+#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
+#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
+#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
+#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
+#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
+#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
+#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
+#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
+#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
+#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
+#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
+#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
+#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
+#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
+#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
+#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
+#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
+#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
+#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
+#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
+#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
+#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
+#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
+#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
+#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
+#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
+#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
+#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
+#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
+#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
+#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
+#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
+#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
+#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
+#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
+#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
+#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
+#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
+
+#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
+#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
+#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
+#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
+#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
+#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
+#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
+#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
+#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
+#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
+#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
+#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
+#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
+#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
+#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
+#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
+#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
+#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
+#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
+#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
+#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
+#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
+#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
+#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
+#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
+#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
+#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
+#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
+#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
+#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
+#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
+#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
+#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
+#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
+#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
+#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
+#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
+#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
+#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
+#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
+#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
+#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
+#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
+#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
+
+
+/***************************************** SDRAM CONTROLLER MASKS ***********************************************/
+
+/* EBIU_SDGCTL Masks */
+#define CL 0x0000000C /* SDRAM CAS latency */
+#define PASR 0x00000030 /* SDRAM partial array self-refresh */
+#define TRAS 0x000003C0 /* SDRAM tRAS in SCLK cycles */
+#define TRP 0x00003800 /* SDRAM tRP in SCLK cycles */
+#define TRCD 0x00030000 /* SDRAM tRCD in SCLK cycles */
+#define TWR 0x00180000 /* SDRAM tWR in SCLK cycles */
+
+#define SCTLE 0x00000001 /* Enable SDRAM Signals */
+#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
+#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
+#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
+#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
+#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
+#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
+#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
+#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
+#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
+#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
+#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
+#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
+#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
+#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
+#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
+#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
+#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
+#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
+#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
+#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
+#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
+#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
+#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
+#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
+#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
+#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
+#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
+#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
+#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
+#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
+#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
+#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
+#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
+#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
+#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
+#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
+#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
+#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
+#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
+#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
+#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
+#define EBUFE 0x02000000 /* Enable External Buffering Timing */
+#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
+#define EMREN 0x10000000 /* Extended Mode Register Enable */
+#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
+#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
+
+/* EBIU_SDBCTL Masks */
+#define EBE 0x0001 /* Enable SDRAM External Bank */
+#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
+#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
+#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
+#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
+#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
+#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
+#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
+#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
+
+#define EBSZ 0x0006 /* SDRAM external bank size */
+#define EBCAW 0x0030 /* SDRAM external bank column address width */
+
+/* EBIU_SDSTAT Masks */
+#define SDCI 0x0001 /* SDRAM Controller Idle */
+#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
+#define SDPUA 0x0004 /* SDRAM Power-Up Active */
+#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
+#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
+#define BGSTAT 0x0020 /* Bus Grant Status */
+
+
+/**************************************** DMA CONTROLLER MASKS **************************************************/
+
+/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
+#define DMAEN 0x0001 /* DMA Channel Enable */
+#define WNR 0x0002 /* Channel Direction (W/R*) */
+#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
+#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
+#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
+#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
+#define SYNC 0x0020 /* DMA Buffer Clear */
+#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
+#define DI_EN 0x0080 /* Data Interrupt Enable */
+#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
+#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
+#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
+#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
+#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
+#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
+#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
+#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
+#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
+#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
+#define FLOW_STOP 0x0000 /* Stop Mode */
+#define FLOW_AUTO 0x1000 /* Autobuffer Mode */
+#define FLOW_ARRAY 0x4000 /* Descriptor Array Mode */
+#define FLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
+#define FLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
+
+/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
+#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
+#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
+#define PMAP_PPI 0x0000 /* PPI Port DMA */
+#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
+#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
+#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
+#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
+#define PMAP_RSI 0x4000 /* RSI DMA */
+#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
+#define PMAP_SPI1 0x5000 /* SPI1 Transmit/Receive DMA */
+#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
+#define PMAP_SPI 0x7000 /* SPI DMA */
+#define PMAP_SPI0 0x7000 /* SPI0 DMA */
+#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
+#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
+#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
+#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
+
+/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
+#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
+#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
+#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
+#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
+
+
+/********************************* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************************************/
+
+/* PPI_CONTROL Masks */
+#define PORT_EN 0x0001 /* PPI Port Enable */
+#define PORT_DIR 0x0002 /* PPI Port Direction */
+#define XFR_TYPE 0x000C /* PPI Transfer Type */
+#define PORT_CFG 0x0030 /* PPI Port Configuration */
+#define FLD_SEL 0x0040 /* PPI Active Field Select */
+#define PACK_EN 0x0080 /* PPI Packing Mode */ /* previous versions of defBF532.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
+#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
+#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
+#define DLEN_8 0x0000 /* Data Length = 8 Bits */
+#define DLEN_10 0x0800 /* Data Length = 10 Bits */
+#define DLEN_11 0x1000 /* Data Length = 11 Bits */
+#define DLEN_12 0x1800 /* Data Length = 12 Bits */
+#define DLEN_13 0x2000 /* Data Length = 13 Bits */
+#define DLEN_14 0x2800 /* Data Length = 14 Bits */
+#define DLEN_15 0x3000 /* Data Length = 15 Bits */
+#define DLEN_16 0x3800 /* Data Length = 16 Bits */
+#define POLC 0x4000 /* PPI Clock Polarity */
+#define POLS 0x8000 /* PPI Frame Sync Polarity */
+
+/* PPI_STATUS Masks */
+#define LT_ERR_OVR 0x0100 /* Line Track Overflow Error */
+#define LT_ERR_UNDR 0x0200 /* Line Track Underflow Error */
+#define FLD 0x0400 /* Field Indicator */
+#define FT_ERR 0x0800 /* Frame Track Error */
+#define OVR 0x1000 /* FIFO Overflow Error */
+#define UNDR 0x2000 /* FIFO Underrun Error */
+#define ERR_DET 0x4000 /* Error Detected Indicator */
+#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
+
+
+/*************************************** TWO-WIRE INTERFACE (TWI) MASKS *****************************************/
+
+/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
+#ifdef _MISRA_RULES
+#define CLKLOW(x) ((x) & 0xFFu)/* Periods Clock Is Held Low */
+#define CLKHI(y) (((y)&0xFFu)<<0x8)/* Periods Before New Clock Low */
+#else
+#define CLKLOW(x) ((x) & 0xFF)/* Periods Clock Is Held Low */
+#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
+#endif /* _MISRA_RULES */
+
+/* TWI_PRESCALE Masks */
+#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
+#define TWI_ENA 0x0080 /* TWI Enable */
+#define SCCB 0x0200 /* SCCB Compatibility Enable */
+
+/* TWI_SLAVE_CTRL Masks */
+#define SEN 0x0001 /* Slave Enable */
+#define SADD_LEN 0x0002 /* Slave Address Length */
+#define STDVAL 0x0004 /* Slave Transmit Data Valid */
+#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
+#define GEN 0x0010 /* General Call Adrress Matching Enabled */
+
+/* TWI_SLAVE_STAT Masks */
+#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
+#define GCALL 0x0002 /* General Call Indicator */
+
+/* TWI_MASTER_CTRL Masks */
+#define MEN 0x0001 /* Master Mode Enable */
+#define MADD_LEN 0x0002 /* Master Address Length */
+#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
+#define FAST 0x0008 /* Use Fast Mode Timing Specs */
+#define STOP 0x0010 /* Issue Stop Condition */
+#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
+#define DCNT 0x3FC0 /* Data Bytes To Transfer */
+#define SDAOVR 0x4000 /* Serial Data Override */
+#define SCLOVR 0x8000 /* Serial Clock Override */
+
+/* TWI_MASTER_STAT Masks */
+#define MPROG 0x0001 /* Master Transfer In Progress */
+#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
+#define ANAK 0x0004 /* Address Not Acknowledged */
+#define DNAK 0x0008 /* Data Not Acknowledged */
+#define BUFRDERR 0x0010 /* Buffer Read Error */
+#define BUFWRERR 0x0020 /* Buffer Write Error */
+#define SDASEN 0x0040 /* Serial Data Sense */
+#define SCLSEN 0x0080 /* Serial Clock Sense */
+#define BUSBUSY 0x0100 /* Bus Busy Indicator */
+
+/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
+#define SINIT 0x0001 /* Slave Transfer Initiated */
+#define SCOMP 0x0002 /* Slave Transfer Complete */
+#define SERR 0x0004 /* Slave Transfer Error */
+#define SOVF 0x0008 /* Slave Overflow */
+#define MCOMP 0x0010 /* Master Transfer Complete */
+#define MERR 0x0020 /* Master Transfer Error */
+#define XMTSERV 0x0040 /* Transmit FIFO Service */
+#define RCVSERV 0x0080 /* Receive FIFO Service */
+
+/* TWI_FIFO_CTRL Masks */
+#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
+#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
+#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
+#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
+
+/* TWI_FIFO_STAT Masks */
+#define XMTSTAT 0x0003 /* Transmit FIFO Status */
+#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
+#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
+#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
+
+#define RCVSTAT 0x000C /* Receive FIFO Status */
+#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
+#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
+#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
+
+
+/************************************* PIN CONTROL REGISTER MASKS ***********************************************/
+
+/* PORT_MUX deleted in VisualDSP++ 5.0 Update 3 */
+
+
+/*********************************** HANDSHAKE DMA (HMDMA) MASKS ************************************************/
+
+/* HMDMAx_CTL Masks */
+#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */
+#define REP 0x0002 /* HMDMA Request Polarity */
+#define UTE 0x0004 /* Urgency Threshold Enable */
+#define OIE 0x0010 /* Overflow Interrupt Enable */
+#define BDIE 0x0020 /* Block Done Interrupt Enable */
+#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */
+#define DRQ 0x0300 /* HMDMA Request Type */
+#define DRQ_NONE 0x0000 /* No Request */
+#define DRQ_SINGLE 0x0100 /* Channels Request Single */
+#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */
+#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */
+#define RBC 0x1000 /* Reload BCNT With IBCNT */
+#define PS 0x2000 /* HMDMA Pin Status */
+#define OI 0x4000 /* Overflow Interrupt Generated */
+#define BDI 0x8000 /* Block Done Interrupt Generated */
+
+/* entry addresses of the user-callable Boot ROM functions */
+#define _BOOTROM_RESET 0xEF000000
+#define _BOOTROM_FINAL_INIT 0xEF000002
+#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
+#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
+#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
+#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
+#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
+#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
+#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define PGDE_UART PFDE_UART
+#define PGDE_DMA PFDE_DMA
+#define CKELOW SCKELOW
+
+
+/**************************************** COUNTER MASKS ******************************************************/
+
+/* Bit masks for CNT_CONFIG */
+#define CNTE 0x1 /* Counter Enable */
+#define nCNTE 0x0
+#define DEBE 0x2 /* Debounce Enable */
+#define nDEBE 0x0
+#define CDGINV 0x10 /* CDG Pin Polarity Invert */
+#define nCDGINV 0x0
+#define CUDINV 0x20 /* CUD Pin Polarity Invert */
+#define nCUDINV 0x0
+#define CZMINV 0x40 /* CZM Pin Polarity Invert */
+#define nCZMINV 0x0
+#define CNTMODE 0x700 /* Counter Operating Mode */
+#define ZMZC 0x800 /* CZM Zeroes Counter Enable */
+#define nZMZC 0x0
+#define BNDMODE 0x3000 /* Boundary register Mode */
+#define INPDIS 0x8000 /* CUG and CDG Input Disable */
+#define nINPDIS 0x0
+
+/* Bit masks for CNT_IMASK */
+#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */
+#define nICIE 0x0
+#define UCIE 0x2 /* Up count Interrupt Enable */
+#define nUCIE 0x0
+#define DCIE 0x4 /* Down count Interrupt Enable */
+#define nDCIE 0x0
+#define MINCIE 0x8 /* Min Count Interrupt Enable */
+#define nMINCIE 0x0
+#define MAXCIE 0x10 /* Max Count Interrupt Enable */
+#define nMAXCIE 0x0
+#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */
+#define nCOV31IE 0x0
+#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */
+#define nCOV15IE 0x0
+#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */
+#define nCZEROIE 0x0
+#define CZMIE 0x100 /* CZM Pin Interrupt Enable */
+#define nCZMIE 0x0
+#define CZMEIE 0x200 /* CZM Error Interrupt Enable */
+#define nCZMEIE 0x0
+#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */
+#define nCZMZIE 0x0
+
+/* Bit masks for CNT_STATUS */
+#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */
+#define nICII 0x0
+#define UCII 0x2 /* Up count Interrupt Identifier */
+#define nUCII 0x0
+#define DCII 0x4 /* Down count Interrupt Identifier */
+#define nDCII 0x0
+#define MINCII 0x8 /* Min Count Interrupt Identifier */
+#define nMINCII 0x0
+#define MAXCII 0x10 /* Max Count Interrupt Identifier */
+#define nMAXCII 0x0
+#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */
+#define nCOV31II 0x0
+#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */
+#define nCOV15II 0x0
+#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */
+#define nCZEROII 0x0
+#define CZMII 0x100 /* CZM Pin Interrupt Identifier */
+#define nCZMII 0x0
+#define CZMEII 0x200 /* CZM Error Interrupt Identifier */
+#define nCZMEII 0x0
+#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */
+#define nCZMZII 0x0
+
+/* Bit masks for CNT_COMMAND */
+#define W1LCNT 0xf /* Load Counter Register */
+#define W1LMIN 0xf0 /* Load Min Register */
+#define W1LMAX 0xf00 /* Load Max Register */
+#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */
+#define nW1ZMONCE 0x0
+
+/* Bit masks for CNT_DEBOUNCE */
+#define DPRESCALE 0xf /* Load Counter Register */
+
+
+/************************************* SECURITY REGISTER MASKs **************************************************/
+
+/* Bit masks for SECURE_SYSSWT */
+#define EMUDABL 0x1 /* Emulation Disable. */
+#define nEMUDABL 0x0
+#define RSTDABL 0x2 /* Reset Disable */
+#define nRSTDABL 0x0
+#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
+#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
+#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
+#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
+#define nDMA0OVR 0x0
+#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
+#define nDMA1OVR 0x0
+#define EMUOVR 0x4000 /* Emulation Override */
+#define nEMUOVR 0x0
+#define OTPSEN 0x8000 /* OTP Secrets Enable. */
+#define nOTPSEN 0x0
+
+/* Bit masks for SECURE_CONTROL */
+#define SECURE0 0x1 /* SECURE 0 */
+#define nSECURE0 0x0
+#define SECURE1 0x2 /* SECURE 1 */
+#define nSECURE1 0x0
+#define SECURE2 0x4 /* SECURE 2 */
+#define nSECURE2 0x0
+#define SECURE3 0x8 /* SECURE 3 */
+#define nSECURE3 0x0
+
+/* Bit masks for SECURE_STATUS */
+#define SECMODE 0x3 /* Secured Mode Control State */
+#define NMI 0x4 /* Non Maskable Interrupt */
+#define nNMI 0x0
+#define AFVALID 0x8 /* Authentication Firmware Valid */
+#define nAFVALID 0x0
+#define AFEXIT 0x10 /* Authentication Firmware Exit */
+#define nAFEXIT 0x0
+#define SECSTAT 0xe0 /* Secure Status */
+
+
+/********************************************** PWM Masks *******************************************************/
+
+/* Bit masks for PWM_CTRL */
+#define PWM_EN 0x1 /* PWM Enable */
+#define PWM_SYNC_EN 0X2 /* Enable Sync Enable */
+#define PWM_DBL 0x4 /* Double Update Mode */
+#define PWM_EXTSYNC 0x8 /* External Sync */
+#define PWM_SYNCSEL 0x10 /* External Sync Select */
+#define PWM_POLARITY 0x20 /* PWM Output Polarity */
+#define PWM_SRMODE 0x40 /* PWM SR MODE */
+#define PWMTRIPINT_EN 0x80 /* Trip Interrupt Enable */
+#define PWMSYNCINT_EN 0x100 /* Sync Interrupt Enable */
+#define PWMTRIP_DSBL 0x200 /* Trip Input Disable */
+
+/* Bit masks for PWM_STAT */
+#define PWM_PHASE 0x1 /* PWM phase */
+#define PWM_POL 0x2 /* PWM polarity */
+#define PWM_SR 0x4 /* PWM SR mode */
+#define PWM_TRIP 0x8 /* PWM Trip mode */
+#define PWM_TRIPINT 0x100 /* PWM Trip Interrupt */
+#define PWM_SYNCINT 0x200 /* PWM Sync Interrupt */
+
+/* Bit masks for PWMGATE Register */
+
+#define CHOPHI 0x100 /* Gate Chopping Enable High Side */
+#define CHOPLO 0x200 /* Gate Chopping Enable Low Side */
+
+/* Bit masks for PWMSEG Register */
+
+#define CH_EN 0x1 /* CH output Enable */
+#define CL_EN 0x2 /* CL output Enable */
+#define BH_EN 0x4 /* BH output Enable */
+#define BL_EN 0x8 /* BL output Enable */
+#define AH_EN 0x10 /* AH output Enable */
+#define AL_EN 0x20 /* AL output Enable */
+#define CHCL_XOVR 0x40 /* Channel C output Crossover */
+#define BHBL_XOVR 0x80 /* Channel B output Crossover */
+#define AHAL_XOVR 0x100 /* Channel A output Crossover */
+
+/* Bit masks for PWMLSI Register */
+#define PWM_SR_LSI_A 0x1 /* PWM SR Low Side Invert Channel A */
+#define PWM_SR_LSI_B 0x2 /* PWM SR Low Side Invert Channel A */
+#define PWM_SR_LSI_C 0x4 /* PWM SR Low Side Invert Channel A */
+
+/* Bit masks for PWM_STAT2 Register */
+#define PWM_AL 0x1 /* pwm_al output signal for S/W observation */
+#define PWM_AH 0x2 /* pwm_ah output signal for S/W observation */
+#define PWM_BL 0x4 /* pwm_bl output signal for S/W observation */
+#define PWM_BH 0x8 /* pwm_bh output signal for S/W observation */
+#define PWM_CL 0x10 /* pwm_cl output signal for S/W observation */
+#define PWM_CH 0x20 /* pwm_ch output signal for S/W observation */
+
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif /* _DEF_BF51x_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** Copyright (C) 2009 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for register-access and bit-manipulation.
+**
+**/
+#ifndef _DEF_BF523_H
+#define _DEF_BF523_H
+
+/* Include all Core registers and bit definitions */
+#include <def_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF523 */
+
+/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
+#include <defBF52x_base.h>
+
+#endif /* _DEF_BF523_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** Copyright (C) 2009 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for register-access and bit-manipulation.
+**
+**/
+#ifndef _DEF_BF524_H
+#define _DEF_BF524_H
+
+/* Include all Core registers and bit definitions */
+#include <def_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF524 */
+
+/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
+#include <defBF52x_base.h>
+
+/* The following are the #defines needed by ADSP-BF524 that are not in the common header */
+
+/* USB Control Registers */
+
+#define USB_FADDR 0xffc03800 /* Function address register */
+#define USB_POWER 0xffc03804 /* Power management register */
+#define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */
+#define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */
+#define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */
+#define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */
+#define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */
+#define USB_FRAME 0xffc03820 /* USB frame number */
+#define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */
+#define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */
+#define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */
+
+/* USB Packet Control Registers */
+
+#define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */
+#define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */
+#define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */
+#define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
+
+/* USB Endpoint FIFO Registers */
+
+#define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */
+#define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */
+#define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */
+#define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */
+#define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */
+#define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */
+#define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */
+#define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */
+
+/* USB OTG Control Registers */
+
+#define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */
+#define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */
+#define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */
+
+/* USB Phy Control Registers */
+
+#define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */
+#define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */
+#define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */
+#define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */
+#define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */
+
+/* (APHY_CNTRL is for ADI usage only) */
+
+#define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */
+
+/* (APHY_CALIB is for ADI usage only) */
+
+#define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */
+
+#define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+
+/* (PHY_TEST is for ADI usage only) */
+
+#define USB_PHY_TEST 0xffc039ec /* Used for reducing simulation time and simplifies FIFO testability */
+
+#define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */
+#define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
+
+/* USB Endpoint 0 Control Registers */
+
+#define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */
+#define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */
+#define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */
+#define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */
+#define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
+
+/* USB Endpoint 1 Control Registers */
+
+#define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */
+#define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */
+#define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */
+#define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */
+#define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+
+/* USB Endpoint 2 Control Registers */
+
+#define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */
+#define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */
+#define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */
+#define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */
+#define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
+
+/* USB Endpoint 3 Control Registers */
+
+#define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */
+#define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */
+#define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */
+#define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */
+#define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+
+/* USB Endpoint 4 Control Registers */
+
+#define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */
+#define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */
+#define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */
+#define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */
+#define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
+
+/* USB Endpoint 5 Control Registers */
+
+#define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */
+#define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */
+#define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */
+#define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */
+#define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
+
+/* USB Endpoint 6 Control Registers */
+
+#define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */
+#define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */
+#define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */
+#define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */
+#define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
+
+/* USB Endpoint 7 Control Registers */
+
+#define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */
+#define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */
+#define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */
+#define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */
+#define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define USB_EP_NI7_RXINTERVAL 0xffc03bf0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define USB_EP_NI7_TXCOUNT 0xffc03bf8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
+
+#define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */
+
+/* USB Channel 0 Config Registers */
+
+#define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */
+#define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+
+/* USB Channel 1 Config Registers */
+
+#define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */
+#define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+
+/* USB Channel 2 Config Registers */
+
+#define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */
+#define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+
+/* USB Channel 3 Config Registers */
+
+#define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */
+#define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+
+/* USB Channel 4 Config Registers */
+
+#define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */
+#define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+
+/* USB Channel 5 Config Registers */
+
+#define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */
+#define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+
+/* USB Channel 6 Config Registers */
+
+#define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */
+#define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+
+/* USB Channel 7 Config Registers */
+
+#define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */
+#define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+
+/* Bit masks for USB_FADDR */
+
+#define FUNCTION_ADDRESS 0x7f /* Function address */
+
+/* Bit masks for USB_POWER */
+
+#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
+#define nENABLE_SUSPENDM 0x0
+#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
+#define nSUSPEND_MODE 0x0
+#define RESUME_MODE 0x4 /* DMA Mode */
+#define nRESUME_MODE 0x0
+#define RESET 0x8 /* Reset indicator */
+#define nRESET 0x0
+#define HS_MODE 0x10 /* High Speed mode indicator */
+#define nHS_MODE 0x0
+#define HS_ENABLE 0x20 /* high Speed Enable */
+#define nHS_ENABLE 0x0
+#define SOFT_CONN 0x40 /* Soft connect */
+#define nSOFT_CONN 0x0
+#define ISO_UPDATE 0x80 /* Isochronous update */
+#define nISO_UPDATE 0x0
+
+/* Bit masks for USB_INTRTX */
+
+#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
+#define nEP0_TX 0x0
+#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
+#define nEP1_TX 0x0
+#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
+#define nEP2_TX 0x0
+#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
+#define nEP3_TX 0x0
+#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
+#define nEP4_TX 0x0
+#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
+#define nEP5_TX 0x0
+#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
+#define nEP6_TX 0x0
+#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
+#define nEP7_TX 0x0
+
+/* Bit masks for USB_INTRRX */
+
+#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
+#define nEP1_RX 0x0
+#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
+#define nEP2_RX 0x0
+#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
+#define nEP3_RX 0x0
+#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
+#define nEP4_RX 0x0
+#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
+#define nEP5_RX 0x0
+#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
+#define nEP6_RX 0x0
+#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
+#define nEP7_RX 0x0
+
+/* Bit masks for USB_INTRTXE */
+
+#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
+#define nEP0_TX_E 0x0
+#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
+#define nEP1_TX_E 0x0
+#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
+#define nEP2_TX_E 0x0
+#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
+#define nEP3_TX_E 0x0
+#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
+#define nEP4_TX_E 0x0
+#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
+#define nEP5_TX_E 0x0
+#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
+#define nEP6_TX_E 0x0
+#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
+#define nEP7_TX_E 0x0
+
+/* Bit masks for USB_INTRRXE */
+
+#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
+#define nEP1_RX_E 0x0
+#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
+#define nEP2_RX_E 0x0
+#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
+#define nEP3_RX_E 0x0
+#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
+#define nEP4_RX_E 0x0
+#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
+#define nEP5_RX_E 0x0
+#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
+#define nEP6_RX_E 0x0
+#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
+#define nEP7_RX_E 0x0
+
+/* Bit masks for USB_INTRUSB */
+
+#define SUSPEND_B 0x1 /* Suspend indicator */
+#define nSUSPEND_B 0x0
+#define RESUME_B 0x2 /* Resume indicator */
+#define nRESUME_B 0x0
+#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
+#define nRESET_OR_BABLE_B 0x0
+#define SOF_B 0x8 /* Start of frame */
+#define nSOF_B 0x0
+#define CONN_B 0x10 /* Connection indicator */
+#define nCONN_B 0x0
+#define DISCON_B 0x20 /* Disconnect indicator */
+#define nDISCON_B 0x0
+#define SESSION_REQ_B 0x40 /* Session Request */
+#define nSESSION_REQ_B 0x0
+#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
+#define nVBUS_ERROR_B 0x0
+
+/* Bit masks for USB_INTRUSBE */
+
+#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
+#define nSUSPEND_BE 0x0
+#define RESUME_BE 0x2 /* Resume indicator int enable */
+#define nRESUME_BE 0x0
+#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
+#define nRESET_OR_BABLE_BE 0x0
+#define SOF_BE 0x8 /* Start of frame int enable */
+#define nSOF_BE 0x0
+#define CONN_BE 0x10 /* Connection indicator int enable */
+#define nCONN_BE 0x0
+#define DISCON_BE 0x20 /* Disconnect indicator int enable */
+#define nDISCON_BE 0x0
+#define SESSION_REQ_BE 0x40 /* Session Request int enable */
+#define nSESSION_REQ_BE 0x0
+#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
+#define nVBUS_ERROR_BE 0x0
+
+/* Bit masks for USB_FRAME */
+
+#define FRAME_NUMBER 0x7ff /* Frame number */
+
+/* Bit masks for USB_INDEX */
+
+#define SELECTED_ENDPOINT 0xf /* selected endpoint */
+
+/* Bit masks for USB_GLOBAL_CTL */
+
+#define GLOBAL_ENA 0x1 /* enables USB module */
+#define nGLOBAL_ENA 0x0
+#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
+#define nEP1_TX_ENA 0x0
+#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
+#define nEP2_TX_ENA 0x0
+#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
+#define nEP3_TX_ENA 0x0
+#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
+#define nEP4_TX_ENA 0x0
+#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
+#define nEP5_TX_ENA 0x0
+#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
+#define nEP6_TX_ENA 0x0
+#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
+#define nEP7_TX_ENA 0x0
+#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
+#define nEP1_RX_ENA 0x0
+#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
+#define nEP2_RX_ENA 0x0
+#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
+#define nEP3_RX_ENA 0x0
+#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
+#define nEP4_RX_ENA 0x0
+#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
+#define nEP5_RX_ENA 0x0
+#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
+#define nEP6_RX_ENA 0x0
+#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
+#define nEP7_RX_ENA 0x0
+
+/* Bit masks for USB_OTG_DEV_CTL */
+
+#define SESSION 0x1 /* session indicator */
+#define nSESSION 0x0
+#define HOST_REQ 0x2 /* Host negotiation request */
+#define nHOST_REQ 0x0
+#define HOST_MODE 0x4 /* indicates USBDRC is a host */
+#define nHOST_MODE 0x0
+#define VBUS0 0x8 /* Vbus level indicator[0] */
+#define nVBUS0 0x0
+#define VBUS1 0x10 /* Vbus level indicator[1] */
+#define nVBUS1 0x0
+#define LSDEV 0x20 /* Low-speed indicator */
+#define nLSDEV 0x0
+#define FSDEV 0x40 /* Full or High-speed indicator */
+#define nFSDEV 0x0
+#define B_DEVICE 0x80 /* A' or 'B' device indicator */
+#define nB_DEVICE 0x0
+
+/* Bit masks for USB_OTG_VBUS_IRQ */
+
+#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
+#define nDRIVE_VBUS_ON 0x0
+#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
+#define nDRIVE_VBUS_OFF 0x0
+#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
+#define nCHRG_VBUS_START 0x0
+#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
+#define nCHRG_VBUS_END 0x0
+#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
+#define nDISCHRG_VBUS_START 0x0
+#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
+#define nDISCHRG_VBUS_END 0x0
+
+/* Bit masks for USB_OTG_VBUS_MASK */
+
+#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
+#define nDRIVE_VBUS_ON_ENA 0x0
+#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
+#define nDRIVE_VBUS_OFF_ENA 0x0
+#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
+#define nCHRG_VBUS_START_ENA 0x0
+#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
+#define nCHRG_VBUS_END_ENA 0x0
+#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
+#define nDISCHRG_VBUS_START_ENA 0x0
+#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
+#define nDISCHRG_VBUS_END_ENA 0x0
+
+/* Bit masks for USB_CSR0 */
+
+#define RXPKTRDY 0x1 /* data packet receive indicator */
+#define nRXPKTRDY 0x0
+#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
+#define nTXPKTRDY 0x0
+#define STALL_SENT 0x4 /* STALL handshake sent */
+#define nSTALL_SENT 0x0
+#define DATAEND 0x8 /* Data end indicator */
+#define nDATAEND 0x0
+#define SETUPEND 0x10 /* Setup end */
+#define nSETUPEND 0x0
+#define SENDSTALL 0x20 /* Send STALL handshake */
+#define nSENDSTALL 0x0
+#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
+#define nSERVICED_RXPKTRDY 0x0
+#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
+#define nSERVICED_SETUPEND 0x0
+#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
+#define nFLUSHFIFO 0x0
+#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
+#define nSTALL_RECEIVED_H 0x0
+#define SETUPPKT_H 0x8 /* send Setup token host mode */
+#define nSETUPPKT_H 0x0
+#define ERROR_H 0x10 /* timeout error indicator host mode */
+#define nERROR_H 0x0
+#define REQPKT_H 0x20 /* Request an IN transaction host mode */
+#define nREQPKT_H 0x0
+#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
+#define nSTATUSPKT_H 0x0
+#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
+#define nNAK_TIMEOUT_H 0x0
+
+/* Bit masks for USB_COUNT0 */
+
+#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
+
+/* Bit masks for USB_NAKLIMIT0 */
+
+#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
+
+/* Bit masks for USB_TX_MAX_PACKET */
+
+#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
+
+/* Bit masks for USB_RX_MAX_PACKET */
+
+#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
+
+/* Bit masks for USB_TXCSR */
+
+#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
+#define nTXPKTRDY_T 0x0
+#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
+#define nFIFO_NOT_EMPTY_T 0x0
+#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
+#define nUNDERRUN_T 0x0
+#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
+#define nFLUSHFIFO_T 0x0
+#define STALL_SEND_T 0x10 /* issue a Stall handshake */
+#define nSTALL_SEND_T 0x0
+#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
+#define nSTALL_SENT_T 0x0
+#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
+#define nCLEAR_DATATOGGLE_T 0x0
+#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
+#define nINCOMPTX_T 0x0
+#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
+#define nDMAREQMODE_T 0x0
+#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
+#define nFORCE_DATATOGGLE_T 0x0
+#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
+#define nDMAREQ_ENA_T 0x0
+#define ISO_T 0x4000 /* enable Isochronous transfers */
+#define nISO_T 0x0
+#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
+#define nAUTOSET_T 0x0
+#define ERROR_TH 0x4 /* error condition host mode */
+#define nERROR_TH 0x0
+#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
+#define nSTALL_RECEIVED_TH 0x0
+#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
+#define nNAK_TIMEOUT_TH 0x0
+
+/* Bit masks for USB_TXCOUNT */
+
+#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
+
+/* Bit masks for USB_RXCSR */
+
+#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
+#define nRXPKTRDY_R 0x0
+#define FIFO_FULL_R 0x2 /* FIFO not empty */
+#define nFIFO_FULL_R 0x0
+#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
+#define nOVERRUN_R 0x0
+#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
+#define nDATAERROR_R 0x0
+#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
+#define nFLUSHFIFO_R 0x0
+#define STALL_SEND_R 0x20 /* issue a Stall handshake */
+#define nSTALL_SEND_R 0x0
+#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
+#define nSTALL_SENT_R 0x0
+#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
+#define nCLEAR_DATATOGGLE_R 0x0
+#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
+#define nINCOMPRX_R 0x0
+#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
+#define nDMAREQMODE_R 0x0
+#define DISNYET_R 0x1000 /* disable Nyet handshakes */
+#define nDISNYET_R 0x0
+#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
+#define nDMAREQ_ENA_R 0x0
+#define ISO_R 0x4000 /* enable Isochronous transfers */
+#define nISO_R 0x0
+#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
+#define nAUTOCLEAR_R 0x0
+#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
+#define nERROR_RH 0x0
+#define REQPKT_RH 0x20 /* request an IN transaction host mode */
+#define nREQPKT_RH 0x0
+#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
+#define nSTALL_RECEIVED_RH 0x0
+#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
+#define nINCOMPRX_RH 0x0
+#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
+#define nDMAREQMODE_RH 0x0
+#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
+#define nAUTOREQ_RH 0x0
+
+/* Bit masks for USB_RXCOUNT */
+
+#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
+
+/* Bit masks for USB_TXTYPE */
+
+#define TARGET_EP_NO_T 0xf /* EP number */
+#define PROTOCOL_T 0xc /* transfer type */
+
+/* Bit masks for USB_TXINTERVAL */
+
+#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
+
+/* Bit masks for USB_RXTYPE */
+
+#define TARGET_EP_NO_R 0xf /* EP number */
+#define PROTOCOL_R 0xc /* transfer type */
+
+/* Bit masks for USB_RXINTERVAL */
+
+#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
+
+/* Bit masks for USB_DMA_INTERRUPT */
+
+#define DMA0_INT 0x1 /* DMA0 pending interrupt */
+#define nDMA0_INT 0x0
+#define DMA1_INT 0x2 /* DMA1 pending interrupt */
+#define nDMA1_INT 0x0
+#define DMA2_INT 0x4 /* DMA2 pending interrupt */
+#define nDMA2_INT 0x0
+#define DMA3_INT 0x8 /* DMA3 pending interrupt */
+#define nDMA3_INT 0x0
+#define DMA4_INT 0x10 /* DMA4 pending interrupt */
+#define nDMA4_INT 0x0
+#define DMA5_INT 0x20 /* DMA5 pending interrupt */
+#define nDMA5_INT 0x0
+#define DMA6_INT 0x40 /* DMA6 pending interrupt */
+#define nDMA6_INT 0x0
+#define DMA7_INT 0x80 /* DMA7 pending interrupt */
+#define nDMA7_INT 0x0
+
+/* Bit masks for USB_DMAxCONTROL */
+
+#define DMA_ENA 0x1 /* DMA enable */
+#define nDMA_ENA 0x0
+#define DIRECTION 0x2 /* direction of DMA transfer */
+#define nDIRECTION 0x0
+#define MODE 0x4 /* DMA Bus error */
+#define nMODE 0x0
+#define INT_ENA 0x8 /* Interrupt enable */
+#define nINT_ENA 0x0
+#define EPNUM 0xf0 /* EP number */
+#define BUSERROR 0x100 /* DMA Bus error */
+#define nBUSERROR 0x0
+
+/* Bit masks for USB_DMAxADDRHIGH */
+
+#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
+
+/* Bit masks for USB_DMAxADDRLOW */
+
+#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
+
+/* Bit masks for USB_DMAxCOUNTHIGH */
+
+#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
+
+/* Bit masks for USB_DMAxCOUNTLOW */
+
+#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
+
+#endif /* _DEF_BF524_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** Copyright (C) 2009 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for register-access and bit-manipulation.
+**
+**/
+#ifndef _DEF_BF526_H
+#define _DEF_BF526_H
+
+/* Include all Core registers and bit definitions */
+#include <def_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF526 */
+
+/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
+#include <defBF52x_base.h>
+
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"some acros violate rule 19.4")
+#pragma diag(suppress:misra_rule_19_7:"Allow function-like macros")
+#endif /* _MISRA_RULES */
+
+/* The following are the #defines needed by ADSP-BF526 that are not in the common header */
+/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
+
+#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
+#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
+#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
+#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
+#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
+#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
+#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
+#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
+#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
+#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
+#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
+#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
+#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
+#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
+#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
+#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
+#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
+#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
+#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
+
+#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
+#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
+#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
+#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
+#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
+#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
+#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
+#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
+
+#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
+#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
+#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
+#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
+#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
+
+#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
+#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
+#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
+#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
+#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
+#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
+#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
+#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
+#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
+#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
+#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
+#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
+#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
+#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
+#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
+#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
+#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
+#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
+#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
+#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */
+#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
+#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
+#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
+#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
+
+#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
+#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
+#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
+#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
+#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
+#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
+#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
+#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
+#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
+#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
+#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
+#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
+#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
+#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
+#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
+#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
+#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
+#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */
+#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
+#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
+#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
+#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
+#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
+
+/* Listing for IEEE-Supported Count Registers */
+
+#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
+#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
+#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
+#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
+#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
+#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
+#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
+#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
+#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
+#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
+#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
+#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
+#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
+#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
+#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
+#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
+#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
+#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
+#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
+#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */
+#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
+#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
+#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
+#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
+
+#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
+#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
+#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
+#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
+#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
+#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
+#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
+#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
+#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
+#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
+#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
+#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
+#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
+#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
+#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
+#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
+#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
+#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */
+#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
+#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
+#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
+#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
+#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
+
+/***********************************************************************************
+** System MMR Register Bits And Macros
+**
+** Disclaimer: All macros are intended to make C and Assembly code more readable.
+** Use these macros carefully, as any that do left shifts for field
+** depositing will result in the lower order bits being destroyed. Any
+** macro that shifts left to properly position the bit-field should be
+** used as part of an OR to initialize a register and NOT as a dynamic
+** modifier UNLESS the lower order bits are saved and ORed back in when
+** the macro is used.
+*************************************************************************************/
+
+/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
+
+/* EMAC_OPMODE Masks */
+
+#define RE 0x00000001 /* Receiver Enable */
+#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
+#define HU 0x00000010 /* Hash Filter Unicast Address */
+#define HM 0x00000020 /* Hash Filter Multicast Address */
+#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
+#define PR 0x00000080 /* Promiscuous Mode Enable */
+#define IFE 0x00000100 /* Inverse Filtering Enable */
+#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
+#define PBF 0x00000400 /* Pass Bad Frames Enable */
+#define PSF 0x00000800 /* Pass Short Frames Enable */
+#define RAF 0x00001000 /* Receive-All Mode */
+#define TE 0x00010000 /* Transmitter Enable */
+#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
+#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
+#define DC 0x00080000 /* Deferral Check */
+#define BOLMT 0x00300000 /* Back-Off Limit */
+#define BOLMT_10 0x00000000 /* 10-bit range */
+#define BOLMT_8 0x00100000 /* 8-bit range */
+#define BOLMT_4 0x00200000 /* 4-bit range */
+#define BOLMT_1 0x00300000 /* 1-bit range */
+#define DRTY 0x00400000 /* Disable TX Retry On Collision */
+#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
+#define RMII 0x01000000 /* RMII/MII* Mode */
+#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
+#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
+#define LB 0x08000000 /* Internal Loopback Enable */
+#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
+
+/* EMAC_STAADD Masks */
+
+#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
+#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
+#define STADISPRE 0x00000004 /* Disable Preamble Generation */
+#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
+#define REGAD 0x000007C0 /* STA Register Address */
+#define PHYAD 0x0000F800 /* PHY Device Address */
+
+#ifdef _MISRA_RULES
+#define SET_REGAD(x) (((x)&0x1Fu)<< 6 ) /* Set STA Register Address */
+#define SET_PHYAD(x) (((x)&0x1Fu)<< 11 ) /* Set PHY Device Address */
+#else
+#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
+#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
+#endif /* _MISRA_RULES */
+
+/* EMAC_STADAT Mask */
+
+#define STADATA 0x0000FFFF /* Station Management Data */
+
+/* EMAC_FLC Masks */
+
+#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
+#define FLCE 0x00000002 /* Flow Control Enable */
+#define PCF 0x00000004 /* Pass Control Frames */
+#define BKPRSEN 0x00000008 /* Enable Backpressure */
+#define FLCPAUSE 0xFFFF0000 /* Pause Time */
+
+#ifdef _MISRA_RULES
+#define SET_FLCPAUSE(x) (((x)&0xFFFFu)<< 16) /* Set Pause Time */
+#else
+#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
+#endif /* _MISRA_RULES */
+
+/* EMAC_WKUP_CTL Masks */
+
+#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
+#define MPKE 0x00000002 /* Magic Packet Enable */
+#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
+#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
+#define MPKS 0x00000020 /* Magic Packet Received Status */
+#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
+
+/* EMAC_WKUP_FFCMD Masks */
+
+#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
+#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
+#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
+#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
+#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
+#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
+#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
+#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
+
+/* EMAC_WKUP_FFOFF Masks */
+
+#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
+#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
+#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
+#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
+
+#ifdef _MISRA_RULES
+#define SET_WF0_OFF(x) (((x)&0xFFu)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
+#define SET_WF1_OFF(x) (((x)&0xFFu)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
+#define SET_WF2_OFF(x) (((x)&0xFFu)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
+#define SET_WF3_OFF(x) (((x)&0xFFu)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
+#else
+#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
+#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
+#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
+#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
+#endif /* _MISRA_RULES */
+
+/* Set ALL Offsets */
+#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
+
+/* EMAC_WKUP_FFCRC0 Masks */
+
+#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
+#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
+
+#ifdef _MISRA_RULES
+#define SET_WF0_CRC(x) (((x)&0xFFFFu)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
+#define SET_WF1_CRC(x) (((x)&0xFFFFu)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
+#else
+#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
+#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
+#endif /* _MISRA_RULES */
+
+/* EMAC_WKUP_FFCRC1 Masks */
+
+#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
+#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
+
+#ifdef _MISRA_RULES
+#define SET_WF2_CRC(x) (((x)&0xFFFFu)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
+#define SET_WF3_CRC(x) (((x)&0xFFFFu)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
+#else
+#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
+#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
+#endif /* _MISRA_RULES */
+
+/* EMAC_SYSCTL Masks */
+
+#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
+#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
+#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
+#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
+
+#ifdef _MISRA_RULES
+#define SET_MDCDIV(x) (((x)&0x3Fu)<< 8) /* Set MDC Clock Divisor */
+#else
+#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
+#endif /* _MISRA_RULES */
+
+/* EMAC_SYSTAT Masks */
+
+#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
+#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
+#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
+#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
+#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
+#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
+#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
+#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
+
+/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
+
+#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
+#define RX_COMP 0x00001000 /* RX Frame Complete */
+#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
+#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
+#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
+#define RX_CRC 0x00010000 /* RX Frame CRC Error */
+#define RX_LEN 0x00020000 /* RX Frame Length Error */
+#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
+#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
+#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
+#define RX_PHY 0x00200000 /* RX Frame PHY Error */
+#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
+#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
+#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
+#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
+#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
+#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
+#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
+#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
+#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
+#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
+
+/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
+
+#define TX_COMP 0x00000001 /* TX Frame Complete */
+#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
+#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
+#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
+#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
+#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
+#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
+#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
+#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
+#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
+#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
+#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
+#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
+#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
+#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
+
+/* EMAC_MMC_CTL Masks */
+#define RSTC 0x00000001 /* Reset All Counters */
+#define CROLL 0x00000002 /* Counter Roll-Over Enable */
+#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
+#define MMCE 0x00000008 /* Enable MMC Counter Operation */
+
+/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
+#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
+#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
+#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
+#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
+#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
+#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
+#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
+#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
+#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
+#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
+#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
+#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
+#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
+#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
+#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
+#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
+#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
+#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
+#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
+#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
+#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
+#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
+#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
+#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
+
+/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
+
+#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
+#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
+#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
+#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
+#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
+#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
+#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
+#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
+#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
+#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
+#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
+#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
+#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
+#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
+#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
+#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
+#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
+#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
+#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
+#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
+#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
+#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
+#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
+
+/* USB Control Registers */
+
+#define USB_FADDR 0xffc03800 /* Function address register */
+#define USB_POWER 0xffc03804 /* Power management register */
+#define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */
+#define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */
+#define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */
+#define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */
+#define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */
+#define USB_FRAME 0xffc03820 /* USB frame number */
+#define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */
+#define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */
+#define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */
+
+/* USB Packet Control Registers */
+
+#define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */
+#define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */
+#define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */
+#define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
+
+/* USB Endpoint FIFO Registers */
+
+#define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */
+#define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */
+#define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */
+#define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */
+#define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */
+#define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */
+#define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */
+#define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */
+
+/* USB OTG Control Registers */
+
+#define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */
+#define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */
+#define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */
+
+/* USB Phy Control Registers */
+
+#define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */
+#define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */
+#define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */
+#define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */
+#define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */
+
+/* (APHY_CNTRL is for ADI usage only) */
+
+#define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */
+
+/* (APHY_CALIB is for ADI usage only) */
+
+#define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */
+
+#define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+
+/* (PHY_TEST is for ADI usage only) */
+
+#define USB_PHY_TEST 0xffc039ec /* Used for reducing simulation time and simplifies FIFO testability */
+
+#define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */
+#define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
+
+/* USB Endpoint 0 Control Registers */
+
+#define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */
+#define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */
+#define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */
+#define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */
+#define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
+
+/* USB Endpoint 1 Control Registers */
+
+#define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */
+#define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */
+#define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */
+#define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */
+#define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+
+/* USB Endpoint 2 Control Registers */
+
+#define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */
+#define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */
+#define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */
+#define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */
+#define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
+
+/* USB Endpoint 3 Control Registers */
+
+#define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */
+#define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */
+#define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */
+#define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */
+#define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+
+/* USB Endpoint 4 Control Registers */
+
+#define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */
+#define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */
+#define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */
+#define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */
+#define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
+
+/* USB Endpoint 5 Control Registers */
+
+#define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */
+#define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */
+#define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */
+#define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */
+#define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
+
+/* USB Endpoint 6 Control Registers */
+
+#define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */
+#define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */
+#define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */
+#define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */
+#define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
+
+/* USB Endpoint 7 Control Registers */
+
+#define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */
+#define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */
+#define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */
+#define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */
+#define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define USB_EP_NI7_RXINTERVAL 0xffc03bf0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define USB_EP_NI7_TXCOUNT 0xffc03bf8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
+
+#define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */
+
+/* USB Channel 0 Config Registers */
+
+#define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */
+#define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+
+/* USB Channel 1 Config Registers */
+
+#define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */
+#define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+
+/* USB Channel 2 Config Registers */
+
+#define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */
+#define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+
+/* USB Channel 3 Config Registers */
+
+#define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */
+#define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+
+/* USB Channel 4 Config Registers */
+
+#define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */
+#define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+
+/* USB Channel 5 Config Registers */
+
+#define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */
+#define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+
+/* USB Channel 6 Config Registers */
+
+#define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */
+#define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+
+/* USB Channel 7 Config Registers */
+
+#define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */
+#define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+
+/* Bit masks for USB_FADDR */
+
+#define FUNCTION_ADDRESS 0x7f /* Function address */
+
+/* Bit masks for USB_POWER */
+
+#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
+#define nENABLE_SUSPENDM 0x0
+#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
+#define nSUSPEND_MODE 0x0
+#define RESUME_MODE 0x4 /* DMA Mode */
+#define nRESUME_MODE 0x0
+#define RESET 0x8 /* Reset indicator */
+#define nRESET 0x0
+#define HS_MODE 0x10 /* High Speed mode indicator */
+#define nHS_MODE 0x0
+#define HS_ENABLE 0x20 /* high Speed Enable */
+#define nHS_ENABLE 0x0
+#define SOFT_CONN 0x40 /* Soft connect */
+#define nSOFT_CONN 0x0
+#define ISO_UPDATE 0x80 /* Isochronous update */
+#define nISO_UPDATE 0x0
+
+/* Bit masks for USB_INTRTX */
+
+#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
+#define nEP0_TX 0x0
+#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
+#define nEP1_TX 0x0
+#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
+#define nEP2_TX 0x0
+#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
+#define nEP3_TX 0x0
+#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
+#define nEP4_TX 0x0
+#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
+#define nEP5_TX 0x0
+#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
+#define nEP6_TX 0x0
+#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
+#define nEP7_TX 0x0
+
+/* Bit masks for USB_INTRRX */
+
+#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
+#define nEP1_RX 0x0
+#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
+#define nEP2_RX 0x0
+#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
+#define nEP3_RX 0x0
+#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
+#define nEP4_RX 0x0
+#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
+#define nEP5_RX 0x0
+#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
+#define nEP6_RX 0x0
+#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
+#define nEP7_RX 0x0
+
+/* Bit masks for USB_INTRTXE */
+
+#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
+#define nEP0_TX_E 0x0
+#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
+#define nEP1_TX_E 0x0
+#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
+#define nEP2_TX_E 0x0
+#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
+#define nEP3_TX_E 0x0
+#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
+#define nEP4_TX_E 0x0
+#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
+#define nEP5_TX_E 0x0
+#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
+#define nEP6_TX_E 0x0
+#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
+#define nEP7_TX_E 0x0
+
+/* Bit masks for USB_INTRRXE */
+
+#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
+#define nEP1_RX_E 0x0
+#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
+#define nEP2_RX_E 0x0
+#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
+#define nEP3_RX_E 0x0
+#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
+#define nEP4_RX_E 0x0
+#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
+#define nEP5_RX_E 0x0
+#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
+#define nEP6_RX_E 0x0
+#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
+#define nEP7_RX_E 0x0
+
+/* Bit masks for USB_INTRUSB */
+
+#define SUSPEND_B 0x1 /* Suspend indicator */
+#define nSUSPEND_B 0x0
+#define RESUME_B 0x2 /* Resume indicator */
+#define nRESUME_B 0x0
+#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
+#define nRESET_OR_BABLE_B 0x0
+#define SOF_B 0x8 /* Start of frame */
+#define nSOF_B 0x0
+#define CONN_B 0x10 /* Connection indicator */
+#define nCONN_B 0x0
+#define DISCON_B 0x20 /* Disconnect indicator */
+#define nDISCON_B 0x0
+#define SESSION_REQ_B 0x40 /* Session Request */
+#define nSESSION_REQ_B 0x0
+#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
+#define nVBUS_ERROR_B 0x0
+
+/* Bit masks for USB_INTRUSBE */
+
+#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
+#define nSUSPEND_BE 0x0
+#define RESUME_BE 0x2 /* Resume indicator int enable */
+#define nRESUME_BE 0x0
+#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
+#define nRESET_OR_BABLE_BE 0x0
+#define SOF_BE 0x8 /* Start of frame int enable */
+#define nSOF_BE 0x0
+#define CONN_BE 0x10 /* Connection indicator int enable */
+#define nCONN_BE 0x0
+#define DISCON_BE 0x20 /* Disconnect indicator int enable */
+#define nDISCON_BE 0x0
+#define SESSION_REQ_BE 0x40 /* Session Request int enable */
+#define nSESSION_REQ_BE 0x0
+#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
+#define nVBUS_ERROR_BE 0x0
+
+/* Bit masks for USB_FRAME */
+
+#define FRAME_NUMBER 0x7ff /* Frame number */
+
+/* Bit masks for USB_INDEX */
+
+#define SELECTED_ENDPOINT 0xf /* selected endpoint */
+
+/* Bit masks for USB_GLOBAL_CTL */
+
+#define GLOBAL_ENA 0x1 /* enables USB module */
+#define nGLOBAL_ENA 0x0
+#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
+#define nEP1_TX_ENA 0x0
+#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
+#define nEP2_TX_ENA 0x0
+#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
+#define nEP3_TX_ENA 0x0
+#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
+#define nEP4_TX_ENA 0x0
+#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
+#define nEP5_TX_ENA 0x0
+#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
+#define nEP6_TX_ENA 0x0
+#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
+#define nEP7_TX_ENA 0x0
+#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
+#define nEP1_RX_ENA 0x0
+#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
+#define nEP2_RX_ENA 0x0
+#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
+#define nEP3_RX_ENA 0x0
+#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
+#define nEP4_RX_ENA 0x0
+#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
+#define nEP5_RX_ENA 0x0
+#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
+#define nEP6_RX_ENA 0x0
+#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
+#define nEP7_RX_ENA 0x0
+
+/* Bit masks for USB_OTG_DEV_CTL */
+
+#define SESSION 0x1 /* session indicator */
+#define nSESSION 0x0
+#define HOST_REQ 0x2 /* Host negotiation request */
+#define nHOST_REQ 0x0
+#define HOST_MODE 0x4 /* indicates USBDRC is a host */
+#define nHOST_MODE 0x0
+#define VBUS0 0x8 /* Vbus level indicator[0] */
+#define nVBUS0 0x0
+#define VBUS1 0x10 /* Vbus level indicator[1] */
+#define nVBUS1 0x0
+#define LSDEV 0x20 /* Low-speed indicator */
+#define nLSDEV 0x0
+#define FSDEV 0x40 /* Full or High-speed indicator */
+#define nFSDEV 0x0
+#define B_DEVICE 0x80 /* A' or 'B' device indicator */
+#define nB_DEVICE 0x0
+
+/* Bit masks for USB_OTG_VBUS_IRQ */
+
+#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
+#define nDRIVE_VBUS_ON 0x0
+#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
+#define nDRIVE_VBUS_OFF 0x0
+#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
+#define nCHRG_VBUS_START 0x0
+#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
+#define nCHRG_VBUS_END 0x0
+#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
+#define nDISCHRG_VBUS_START 0x0
+#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
+#define nDISCHRG_VBUS_END 0x0
+
+/* Bit masks for USB_OTG_VBUS_MASK */
+
+#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
+#define nDRIVE_VBUS_ON_ENA 0x0
+#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
+#define nDRIVE_VBUS_OFF_ENA 0x0
+#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
+#define nCHRG_VBUS_START_ENA 0x0
+#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
+#define nCHRG_VBUS_END_ENA 0x0
+#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
+#define nDISCHRG_VBUS_START_ENA 0x0
+#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
+#define nDISCHRG_VBUS_END_ENA 0x0
+
+/* Bit masks for USB_CSR0 */
+
+#define RXPKTRDY 0x1 /* data packet receive indicator */
+#define nRXPKTRDY 0x0
+#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
+#define nTXPKTRDY 0x0
+#define STALL_SENT 0x4 /* STALL handshake sent */
+#define nSTALL_SENT 0x0
+#define DATAEND 0x8 /* Data end indicator */
+#define nDATAEND 0x0
+#define SETUPEND 0x10 /* Setup end */
+#define nSETUPEND 0x0
+#define SENDSTALL 0x20 /* Send STALL handshake */
+#define nSENDSTALL 0x0
+#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
+#define nSERVICED_RXPKTRDY 0x0
+#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
+#define nSERVICED_SETUPEND 0x0
+#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
+#define nFLUSHFIFO 0x0
+#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
+#define nSTALL_RECEIVED_H 0x0
+#define SETUPPKT_H 0x8 /* send Setup token host mode */
+#define nSETUPPKT_H 0x0
+#define ERROR_H 0x10 /* timeout error indicator host mode */
+#define nERROR_H 0x0
+#define REQPKT_H 0x20 /* Request an IN transaction host mode */
+#define nREQPKT_H 0x0
+#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
+#define nSTATUSPKT_H 0x0
+#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
+#define nNAK_TIMEOUT_H 0x0
+
+/* Bit masks for USB_COUNT0 */
+
+#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
+
+/* Bit masks for USB_NAKLIMIT0 */
+
+#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
+
+/* Bit masks for USB_TX_MAX_PACKET */
+
+#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
+
+/* Bit masks for USB_RX_MAX_PACKET */
+
+#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
+
+/* Bit masks for USB_TXCSR */
+
+#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
+#define nTXPKTRDY_T 0x0
+#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
+#define nFIFO_NOT_EMPTY_T 0x0
+#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
+#define nUNDERRUN_T 0x0
+#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
+#define nFLUSHFIFO_T 0x0
+#define STALL_SEND_T 0x10 /* issue a Stall handshake */
+#define nSTALL_SEND_T 0x0
+#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
+#define nSTALL_SENT_T 0x0
+#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
+#define nCLEAR_DATATOGGLE_T 0x0
+#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
+#define nINCOMPTX_T 0x0
+#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
+#define nDMAREQMODE_T 0x0
+#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
+#define nFORCE_DATATOGGLE_T 0x0
+#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
+#define nDMAREQ_ENA_T 0x0
+#define ISO_T 0x4000 /* enable Isochronous transfers */
+#define nISO_T 0x0
+#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
+#define nAUTOSET_T 0x0
+#define ERROR_TH 0x4 /* error condition host mode */
+#define nERROR_TH 0x0
+#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
+#define nSTALL_RECEIVED_TH 0x0
+#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
+#define nNAK_TIMEOUT_TH 0x0
+
+/* Bit masks for USB_TXCOUNT */
+
+#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
+
+/* Bit masks for USB_RXCSR */
+
+#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
+#define nRXPKTRDY_R 0x0
+#define FIFO_FULL_R 0x2 /* FIFO not empty */
+#define nFIFO_FULL_R 0x0
+#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
+#define nOVERRUN_R 0x0
+#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
+#define nDATAERROR_R 0x0
+#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
+#define nFLUSHFIFO_R 0x0
+#define STALL_SEND_R 0x20 /* issue a Stall handshake */
+#define nSTALL_SEND_R 0x0
+#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
+#define nSTALL_SENT_R 0x0
+#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
+#define nCLEAR_DATATOGGLE_R 0x0
+#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
+#define nINCOMPRX_R 0x0
+#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
+#define nDMAREQMODE_R 0x0
+#define DISNYET_R 0x1000 /* disable Nyet handshakes */
+#define nDISNYET_R 0x0
+#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
+#define nDMAREQ_ENA_R 0x0
+#define ISO_R 0x4000 /* enable Isochronous transfers */
+#define nISO_R 0x0
+#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
+#define nAUTOCLEAR_R 0x0
+#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
+#define nERROR_RH 0x0
+#define REQPKT_RH 0x20 /* request an IN transaction host mode */
+#define nREQPKT_RH 0x0
+#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
+#define nSTALL_RECEIVED_RH 0x0
+#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
+#define nINCOMPRX_RH 0x0
+#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
+#define nDMAREQMODE_RH 0x0
+#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
+#define nAUTOREQ_RH 0x0
+
+/* Bit masks for USB_RXCOUNT */
+
+#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
+
+/* Bit masks for USB_TXTYPE */
+
+#define TARGET_EP_NO_T 0xf /* EP number */
+#define PROTOCOL_T 0xc /* transfer type */
+
+/* Bit masks for USB_TXINTERVAL */
+
+#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
+
+/* Bit masks for USB_RXTYPE */
+
+#define TARGET_EP_NO_R 0xf /* EP number */
+#define PROTOCOL_R 0xc /* transfer type */
+
+/* Bit masks for USB_RXINTERVAL */
+
+#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
+
+/* Bit masks for USB_DMA_INTERRUPT */
+
+#define DMA0_INT 0x1 /* DMA0 pending interrupt */
+#define nDMA0_INT 0x0
+#define DMA1_INT 0x2 /* DMA1 pending interrupt */
+#define nDMA1_INT 0x0
+#define DMA2_INT 0x4 /* DMA2 pending interrupt */
+#define nDMA2_INT 0x0
+#define DMA3_INT 0x8 /* DMA3 pending interrupt */
+#define nDMA3_INT 0x0
+#define DMA4_INT 0x10 /* DMA4 pending interrupt */
+#define nDMA4_INT 0x0
+#define DMA5_INT 0x20 /* DMA5 pending interrupt */
+#define nDMA5_INT 0x0
+#define DMA6_INT 0x40 /* DMA6 pending interrupt */
+#define nDMA6_INT 0x0
+#define DMA7_INT 0x80 /* DMA7 pending interrupt */
+#define nDMA7_INT 0x0
+
+/* Bit masks for USB_DMAxCONTROL */
+
+#define DMA_ENA 0x1 /* DMA enable */
+#define nDMA_ENA 0x0
+#define DIRECTION 0x2 /* direction of DMA transfer */
+#define nDIRECTION 0x0
+#define MODE 0x4 /* DMA Bus error */
+#define nMODE 0x0
+#define INT_ENA 0x8 /* Interrupt enable */
+#define nINT_ENA 0x0
+#define EPNUM 0xf0 /* EP number */
+#define BUSERROR 0x100 /* DMA Bus error */
+#define nBUSERROR 0x0
+
+/* Bit masks for USB_DMAxADDRHIGH */
+
+#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
+
+/* Bit masks for USB_DMAxADDRLOW */
+
+#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
+
+/* Bit masks for USB_DMAxCOUNTHIGH */
+
+#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
+
+/* Bit masks for USB_DMAxCOUNTLOW */
+
+#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
+
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif /* _DEF_BF526_H */
*/
/*
-** Copyright (C) 2008 Analog Devices, Inc.
+** Copyright (C) 2008, 2009 Analog Devices, Inc.
**
************************************************************************************
**
/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
#include <defBF52x_base.h>
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"some macros violate rule 19.4")
+#pragma diag(suppress:misra_rule_19_7:"Allow function-like macros ")
+#endif /* _MISRA_RULES */
+
/* The following are the #defines needed by ADSP-BF527 that are not in the common header */
/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
#define REGAD 0x000007C0 /* STA Register Address */
#define PHYAD 0x0000F800 /* PHY Device Address */
+#ifdef _MISRA_RULES
+#define SET_REGAD(x) (((x)&0x1Fu)<< 6 ) /* Set STA Register Address */
+#define SET_PHYAD(x) (((x)&0x1Fu)<< 11 ) /* Set PHY Device Address */
+#else
#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
+#endif /* _MISRA_RULES */
/* EMAC_STADAT Mask */
#define BKPRSEN 0x00000008 /* Enable Backpressure */
#define FLCPAUSE 0xFFFF0000 /* Pause Time */
+#ifdef _MISRA_RULES
+#define SET_FLCPAUSE(x) (((x)&0xFFFFu)<< 16) /* Set Pause Time */
+#else
#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
+#endif /* _MISRA_RULES */
/* EMAC_WKUP_CTL Masks */
#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
+#ifdef _MISRA_RULES
+#define SET_WF0_OFF(x) (((x)&0xFFu)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
+#define SET_WF1_OFF(x) (((x)&0xFFu)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
+#define SET_WF2_OFF(x) (((x)&0xFFu)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
+#define SET_WF3_OFF(x) (((x)&0xFFu)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
+#else
#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
+#endif /* _MISRA_RULES */
+
/* Set ALL Offsets */
#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
+#ifdef _MISRA_RULES
+#define SET_WF0_CRC(x) (((x)&0xFFFFu)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
+#define SET_WF1_CRC(x) (((x)&0xFFFFu)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
+#else
#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
+#endif /* _MISRA_RULES */
/* EMAC_WKUP_FFCRC1 Masks */
#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
+#ifdef _MISRA_RULES
+#define SET_WF2_CRC(x) (((x)&0xFFFFu)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
+#define SET_WF3_CRC(x) (((x)&0xFFFFu)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
+#else
#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
+#endif /* _MISRA_RULES */
/* EMAC_SYSCTL Masks */
#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
+#ifdef _MISRA_RULES
+#define SET_MDCDIV(x) (((x)&0x3Fu)<< 8) /* Set MDC Clock Divisor */
+#else
#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
+#endif /* _MISRA_RULES */
/* EMAC_SYSTAT Masks */
#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
#endif /* _DEF_BF527_H */
/*
** defBF52x_base.h
**
-** Copyright (C) 2008 Analog Devices, Inc.
+** Copyright (C) 2008, 2009 Analog Devices, Inc.
**
************************************************************************************
**
/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
#define SWRST 0xFFC00100 /* Software Reset Register */
#define SYSCR 0xFFC00104 /* System Configuration Register */
-#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
/* legacy register name (below) provided for backwards code compatibility */
#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */
#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */
#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */
-#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
-#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
-#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */
#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */
#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */
#define NONGPIO_DRIVE 0xFFC03280 /* Drive strength control for non-GPIO pins */
-#define NONGPIO_SLEW 0xFFC03284 /* Slew control for non-GPIO pins */
#define NONGPIO_HYSTERESIS 0xFFC03288 /* Schmitt trigger control for non-GPIO pins */
/***********************************************************************************
#define BYPASS 0x0100 /* Bypass the PLL */
#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
+#ifdef _MISRA_RULES
+#define SET_MSEL(x) (((x)&0x3Fu) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
+#else
#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
+#endif /* _MISRA_RULES */
/* PLL_DIV Masks */
#define SSEL 0x000F /* System Select */
#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
/* PLL_DIV Macros */
+#ifdef _MISRA_RULES
+#define SET_SSEL(x) ((x)&0xFu) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
+#else
#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
+#endif /* _MISRA_RULES */
/* VR_CTL Masks */
#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */
#define FULL_ON 0x0002 /* Processor In Full On Mode */
#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
+#define VSTAT 0x0080 /* Voltage Regulator Status: Regulator at programmed voltage */
/* SWRST Masks */
#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
-/* SYSCR Masks */
-#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
-#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
+/* SYSCR Masks */
+
+#define BMODE_BYPASS 0x0000 /* Bypass boot ROM, execute from 16-bit external memory */
+#define BMODE_FLASH 0x0001 /* Use Boot ROM to load from 8-bit or 16-bit flash */
+#define BMODE_SPIMEM 0x0003 /* Boot from serial SPI memory */
+#define BMODE_SPIHOST 0x0004 /* Boot from SPI0 host (slave mode) */
+#define BMODE_TWIMEM 0x0005 /* Boot from serial TWI memory */
+#define BMODE_TWIHOST 0x0006 /* Boot from TWI0 host (slave mode) */
+#define BMODE_UART0HOST 0x0007 /* Boot from UART0 host */
+#define BMODE_UART1HOST 0x0008 /* Boot from UART1 host */
+#define BMODE_SDRAMMEM 0x000A /* Boot from SDRAM memory (warm boot) */
+#define BMODE_OTPMEM 0x000B /* Boot from OTP memory */
+#define BMODE_HOSTDMA_ACK 0x000E /* Boot from 16-bit host DMA (ACK mode) */
+#define BMODE_HOSTDMA_INT 0x000F /* Boot from 8-bit host DMA (INT mode) */
+#define BMODE 0x000F /* Boot Mode. Mirror of BMODE Mode Pins */
+
+#define BCODE 0x00F0
+#define BCODE_NORMAL 0x0000 /* normal boot, update PLL/VR, quickboot as by WURESET */
+#define BCODE_NOBOOT 0x0010 /* bypass boot, don't update PLL/VR */
+#define BCODE_QUICKBOOT 0x0020 /* quick boot, overrule WURESET, don't update PLL/VR */
+#define BCODE_ALLBOOT 0x0040 /* no quick boot, overrule WURESET, don't update PLL/VR */
+#define BCODE_FULLBOOT 0x0060 /* no quick boot, overrule WURESET, update PLL/VR */
+
+#define DCB1_PRIO 0x0100 /* DCB1 requests are urgent */
+#define DCB_ROT_PRIO 0x0200 /* enable rotating DCB priority */
+#define DEB1_PRIO 0x0400 /* DEB1 requests are urgent */
+#define DEB_ROT_PRIO 0x0800 /* enable rotating DEB priority */
+
+#define WURESET 0x1000 /* wakeup event since last hardware reset */
+#define DFRESET 0x2000 /* recent reset was due to a double fault event */
+#define WDRESET 0x4000 /* recent reset was due to a watchdog event */
+#define SWRESET 0x8000 /* recent reset was issued by software */
/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
/* Peripheral Masks For SIC_ISR0, SIC_IWR0, SIC_IMASK0 */
#define IRQ_USB_INT2 0x00400000 /* USB INT1 interrupt */
#define IRQ_USB_DMAINT 0x00800000 /* USB DMAINT interrupt */
+/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
+#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
+#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
+/* x = pos 0 to 31, for 32-63 use value-32 */
+#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
+#ifdef _MISRA_RULES
+#define IWR_DISABLE(x) (0xFFFFFFFFu^(1<<(x)))/* Wakeup Disable Peripheral #x */
+#else
+#define IWR_DISABLE(x) (0xFFFFFFFF^(1<<(x)))/* Wakeup Disable Peripheral #x */
+#endif /* _MISRA_RULES */
+
+
+#ifdef _MISRA_RULES
+#define _MF15 0xFu
+#define _MF7 7u
+#else
+#define _MF15 0xF
+#define _MF7 7
+#endif /* _MISRA_RULES */
/* SIC_IAR0 Macros */
-#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
-#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
-#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
-#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
-#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
-#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
-#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
-#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
+#define P0_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #0 assigned IVG #x */
+#define P1_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #1 assigned IVG #x */
+#define P2_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #2 assigned IVG #x */
+#define P3_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #3 assigned IVG #x */
+#define P4_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #4 assigned IVG #x */
+#define P5_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #5 assigned IVG #x */
+#define P6_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #6 assigned IVG #x */
+#define P7_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #7 assigned IVG #x */
/* SIC_IAR1 Macros */
-#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
-#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
-#define P10_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #10 assigned IVG #x */
-#define P11_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #11 assigned IVG #x */
-#define P12_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #12 assigned IVG #x */
-#define P13_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #13 assigned IVG #x */
+#define P8_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #8 assigned IVG #x */
+#define P9_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #9 assigned IVG #x */
+#define P10_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #10 assigned IVG #x */
+#define P11_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #11 assigned IVG #x */
+#define P12_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #12 assigned IVG #x */
+#define P13_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #13 assigned IVG #x */
/* SIC_IAR2 Macros */
-#define P14_IVG(x) (((x)&0xF)-7) /* Peripheral #14 assigned IVG #x */
-#define P15_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #15 assigned IVG #x */
-#define P16_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #16 assigned IVG #x */
-#define P17_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #17 assigned IVG #x */
-#define P18_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #18 assigned IVG #x */
-#define P19_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #19 assigned IVG #x */
-#define P20_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #20 assigned IVG #x */
-#define P21_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #21 assigned IVG #x */
+#define P14_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #14 assigned IVG #x */
+#define P15_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #15 assigned IVG #x */
+#define P16_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #16 assigned IVG #x */
+#define P17_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #17 assigned IVG #x */
+#define P18_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #18 assigned IVG #x */
+#define P19_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #19 assigned IVG #x */
+#define P20_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #20 assigned IVG #x */
+#define P21_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #21 assigned IVG #x */
/* SIC_IAR3 Macros */
-#define P22_IVG(x) (((x)&0xF)-7) /* Peripheral #22 assigned IVG #x */
-#define P23_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #23 assigned IVG #x */
-#define P24_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #24 assigned IVG #x */
-#define P25_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #25 assigned IVG #x */
-#define P26_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #26 assigned IVG #x */
-#define P27_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #27 assigned IVG #x */
-#define P28_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #28 assigned IVG #x */
-#define P29_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #29 assigned IVG #x */
+#define P22_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #22 assigned IVG #x */
+#define P23_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #23 assigned IVG #x */
+#define P24_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #24 assigned IVG #x */
+#define P25_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #25 assigned IVG #x */
+#define P26_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #26 assigned IVG #x */
+#define P27_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #27 assigned IVG #x */
+#define P28_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #28 assigned IVG #x */
+#define P29_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #29 assigned IVG #x */
/* SIC_IAR4 Macros */
-#define P30_IVG(x) (((x)&0xF)-7) /* Peripheral #30 assigned IVG #x */
-#define P31_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #31 assigned IVG #x */
-#define P32_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #32 assigned IVG #x */
-#define P33_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #33 assigned IVG #x */
-#define P34_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #34 assigned IVG #x */
-#define P35_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #35 assigned IVG #x */
-#define P36_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #36 assigned IVG #x */
-#define P37_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #37 assigned IVG #x */
+#define P30_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #30 assigned IVG #x */
+#define P31_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #31 assigned IVG #x */
+#define P32_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #32 assigned IVG #x */
+#define P33_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #33 assigned IVG #x */
+#define P34_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #34 assigned IVG #x */
+#define P35_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #35 assigned IVG #x */
+#define P36_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #36 assigned IVG #x */
+#define P37_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #37 assigned IVG #x */
/* SIC_IAR5 Macros */
-#define P38_IVG(x) (((x)&0xF)-7) /* Peripheral #38assigned IVG #x */
-#define P39_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #39assigned IVG #x */
-#define P40_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #40 assigned IVG #x */
-#define P41_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #41 assigned IVG #x */
-#define P42_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #42 assigned IVG #x */
-#define P43_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #43 assigned IVG #x */
-#define P44_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #44 assigned IVG #x */
-#define P45_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #45 assigned IVG #x */
+#define P38_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #38assigned IVG #x */
+#define P39_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #39assigned IVG #x */
+#define P40_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #40 assigned IVG #x */
+#define P41_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #41 assigned IVG #x */
+#define P42_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #42 assigned IVG #x */
+#define P43_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #43 assigned IVG #x */
+#define P44_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #44 assigned IVG #x */
+#define P45_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #45 assigned IVG #x */
/* SIC_IAR6 Macros */
-#define P46_IVG(x) (((x)&0xF)-7) /* Peripheral #46 assigned IVG #x */
-#define P47_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #47 assigned IVG #x */
-#define P48_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #48 assigned IVG #x */
-#define P49_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #49 assigned IVG #x */
-#define P50_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #50 assigned IVG #x */
-#define P51_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #51 assigned IVG #x */
-#define P52_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #52 assigned IVG #x */
-#define P53_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #53 assigned IVG #x */
+#define P46_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #46 assigned IVG #x */
+#define P47_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #47 assigned IVG #x */
+#define P48_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #48 assigned IVG #x */
+#define P49_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #49 assigned IVG #x */
+#define P50_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #50 assigned IVG #x */
+#define P51_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #51 assigned IVG #x */
+#define P52_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #52 assigned IVG #x */
+#define P53_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #53 assigned IVG #x */
/* SIC_IAR7 Macros */
-#define P54_IVG(x) (((x)&0xF)-7) /* Peripheral #54 assigned IVG #x */
-#define P55_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #55 assigned IVG #x */
-#define P56_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #56 assigned IVG #x */
-#define P57_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #57 assigned IVG #x */
-#define P58_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #58 assigned IVG #x */
-#define P59_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #59 assigned IVG #x */
-#define P60_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #60 assigned IVG #x */
-#define P61_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #61 assigned IVG #x */
+#define P54_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #54 assigned IVG #x */
+#define P55_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #55 assigned IVG #x */
+#define P56_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #56 assigned IVG #x */
+#define P57_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #57 assigned IVG #x */
+#define P58_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #58 assigned IVG #x */
+#define P59_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #59 assigned IVG #x */
+#define P60_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #60 assigned IVG #x */
+#define P61_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #61 assigned IVG #x */
/* SIC_IMASK0 Masks */
#define SIC_UNMASK0_ALL 0x00000000 /* Unmask all peripheral interrupts */
#define SIC_MASK0_ALL 0xFFFFF3FF /* Mask all peripheral interrupts */
+#ifdef _MISRA_RULES
+#define SIC_MASK0(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
+#define SIC_UNMASK0(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Unmask Peripheral #x interrupt */
+#else
#define SIC_MASK0(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK0(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
+#endif /* _MISRA_RULES */
/* SIC_IMASK1 Masks */
#define SIC_UNMASK1_ALL 0x00000000 /* Unmask all peripheral interrupts */
#define SIC_MASK1_ALL 0xFFFFFF /* Mask all peripheral interrupts */
+#ifdef _MISRA_RULES
+#define SIC_MASK1(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
+#define SIC_UNMASK1(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Unmask Peripheral #x interrupt */
+#else
#define SIC_MASK1(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK1(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
+#endif /* _MISRA_RULES */
/* SIC_IWR0 Masks */
#define IWR0_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
#define IWR0_ENABLE_ALL 0xFFFFF3FF /* Wakeup Enable all peripherals */
+#ifdef _MISRA_RULES
+#define IWR0_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
+#define IWR0_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Wakeup Disable Peripheral #x */
+#else
#define IWR0_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
#define IWR0_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
+#endif /* _MISRA_RULES */
/* SIC_IWR1 Masks */
#define IWR1_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
#define IWR1_ENABLE_ALL 0xFFFFFF /* Wakeup Enable all peripherals */
+#ifdef _MISRA_RULES
+#define IWR1_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
+#define IWR1_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Wakeup Disable Peripheral #x */
+#else
#define IWR1_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
#define IWR1_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
+#endif /* _MISRA_RULES */
/* ********* WATCHDOG TIMER MASKS ******************** */
/* Watchdog Timer WDOG_CTL Register Masks */
+#ifdef _MISRA_RULES
+#define WDEV(x) (((x)<<1) & 0x0006u) /* event generated on roll over */
+#else
#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
+#endif /* _MISRA_RULES */
#define WDEV_RESET 0x0000 /* generate reset event on roll over */
#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
#define RTC_DAY 0xFFFE0000 /* Real-Time Clock Days */
/* RTC_ALARM Macro z=day y=hr x=min w=sec */
+#ifdef _MISRA_RULES
+#define SET_ALARM(z,y,x,w) ((((z)&0x7FFFu)<<0x11)|(((y)&0x1Fu)<<0xC)|(((x)&0x3Fu)<<0x6)|((w)&0x3Fu))
+#else
#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
+#endif /* _MISRA_RULES */
/* RTC_ICTL and RTC_ISTAT Masks */
#define STOPWATCH 0x0001 /* Stopwatch Interrupt Enable */
/* ************** UART CONTROLLER MASKS *************************/
/* UARTx_LCR Masks */
+#ifdef _MISRA_RULES
+#define WLS(x) (((x)-5u) & 0x03u) /* Word Length Select */
+#else
#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
+#endif /* _MISRA_RULES */
#define STB 0x04 /* Stop Bits */
#define PEN 0x08 /* Parity Enable */
#define EPS 0x10 /* Even Parity Select */
#define FPE 0x10 /* Force Parity Error On Transmit */
#define FFE 0x20 /* Force Framing Error On Transmit */
+/* Bit masks for UART Divisor Latch Registers: UARTx_DLL & UARTx_DLH */
+#define UARTDLL 0x00FF /* Divisor Latch Low Byte */
+#define UARTDLH 0xFF00 /* Divisor Latch High Byte */
+
/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/
/* SPI_CTL Masks */
/* SPORTx_TCR1 Masks */
#define TSPEN 0x0001 /* Transmit Enable */
#define ITCLK 0x0002 /* Internal Transmit Clock Select */
-#define DTYPE_NORM 0x0004 /* Data Format Normal */
+#define DTYPE_NORM 0x0000 /* Data Format Normal */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define TLSBIT 0x0010 /* Transmit Bit Order */
#define TCKFE 0x4000 /* Clock Falling Edge Select */
/* SPORTx_TCR2 Masks and Macro */
+#ifdef _MISRA_RULES
+#define SLEN(x) ((x)&0x1Fu) /* SPORT TX Word Length (2 - 31) */
+#else
#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
+#endif /* _MISRA_RULES */
+
#define TXSE 0x0100 /* TX Secondary Enable */
#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
/* SPORTx_RCR1 Masks */
#define RSPEN 0x0001 /* Receive Enable */
#define IRCLK 0x0002 /* Internal Receive Clock Select */
-#define DTYPE_NORM 0x0004 /* Data Format Normal */
+#define DTYPE_NORM 0x0000 /* Data Format Normal */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define RLSBIT 0x0010 /* Receive Bit Order */
#define RCKFE 0x4000 /* Clock Falling Edge Select */
/* SPORTx_RCR2 Masks */
+#ifdef _MISRA_RULES
+#define SLEN(x) ((x)&0x1Fu) /* SPORT RX Word Length (2 - 31) */
+#else
#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
+#endif /* _MISRA_RULES */
#define RXSE 0x0100 /* RX Secondary Enable */
#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
#define RRFST 0x0400 /* Right-First Data Order */
#define TXHRE 0x0040 /* Transmit Hold Register Empty */
/* SPORTx_MCMC1 Macros */
-#define WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
+#ifdef _MISRA_RULES
+#define WOFF(x) ((x) & 0x3FFu) /* Multichannel Window Offset Field */
+/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
+#define WSIZE(x) (((((x)>>0x3)-1u)&0xFu) << 0xC) /* Multichannel Window Size = (x/8)-1 */
+#else
+#define WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
#define WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
+#endif /* _MISRA_RULES */
+
/* SPORTx_MCMC2 Masks */
#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
/* EBIU_AMGCTL Masks */
#define AMCKEN 0x0001 /* Enable CLKOUT */
+#define AMBEN 0x000e /* Async bank enable */
#define AMBEN_NONE 0x0000 /* All Banks Disabled */
#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
#define SCTLE 0x00000001 /* Enable SDRAM Signals */
#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
+/* EBIU_SDGCTL Masks */
+#define CL 0x0000000C /* SDRAM CAS latency */
#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
+#define PASR 0x00000030 /* SDRAM partial array self-refresh */
#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
+#define TRAS 0x000003C0 /* SDRAM tRAS in SCLK cycles */
#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
+#define TRP 0x00003800 /* SDRAM tRP in SCLK cycles */
#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
+#define TRCD 0x00030000 /* SDRAM tRCD in SCLK cycles */
#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
+#define TWR 0x00180000 /* SDRAM tWR in SCLK cycles */
#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
-#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
-#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
+#define EBSZ 0x0006 /* SDRAM external bank size */
#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
+#define EBCAW 0x0030 /* SDRAM external bank column address width */
/* EBIU_SDSTAT Masks */
#define SDCI 0x0001 /* SDRAM Controller Idle */
/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
+#ifdef _MISRA_RULES
+#define CLKLOW(x) ((x) & 0xFFu) /* Periods Clock Is Held Low */
+#define CLKHI(y) (((y)&0xFFu)<<0x8) /* Periods Before New Clock Low */
+#else
#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
+#endif /* _MISRA_RULES */
/* TWI_PRESCALE Masks */
#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
/* Omit CAN masks from defBF534.h */
/* ******************* PIN CONTROL REGISTER MASKS ************************/
-/* PORT_MUX Masks */
-#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
-#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
-#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
-
-#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
-#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
-#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
-#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
-
-#define PFDE 0x0008 /* Port F DMA Request Enable */
-#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
-#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
-
-#define PFTE 0x0010 /* Port F Timer Enable */
-#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
-#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
-
-#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
-#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
-#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
-
-#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
-#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
-#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
-
-#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
-#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
-#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
-
-#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
-#define PFFE_TIMER 0x0000 /* Enable TMR2 */
-#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
-
-#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
-#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
-#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
-
-#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
-#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
-#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
-
-#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
-#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
-#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
+/* PORT_MUX deleted in VisualDSP++ 5.0 Update 3 */
/* ****************** HANDSHAKE DMA (HMDMA) MASKS *********************/
#define DPRESCALE 0xf /* Load Counter Register */
-/* Bit masks for OTP_CONTROL */
-
-#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
-#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
-#define nFIEN 0x0
-#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
-#define nFTESTDEC 0x0
-#define FWRTEST 0x2000 /* OTP/Fuse Write Test */
-#define nFWRTEST 0x0
-#define FRDEN 0x4000 /* OTP/Fuse Read Enable */
-#define nFRDEN 0x0
-#define FWREN 0x8000 /* OTP/Fuse Write Enable */
-#define nFWREN 0x0
-
-/* Bit masks for OTP_BEN */
-
-#define FBEN 0xffff /* OTP/Fuse Byte Enable */
-
-/* Bit masks for OTP_STATUS */
-
-#define FCOMP 0x1 /* OTP/Fuse Access Complete */
-#define nFCOMP 0x0
-#define FERROR 0x2 /* OTP/Fuse Access Error */
-#define nFERROR 0x0
-#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
-#define nMMRGLOAD 0x0
-#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
-#define nMMRGLOCK 0x0
-#define FPGMEN 0x40 /* OTP/Fuse Program Enable */
-#define nFPGMEN 0x0
-
-/* Bit masks for OTP_TIMING */
-
-#define USECDIV 0xff /* Micro Second Divider */
-#define READACC 0x7f00 /* Read Access Time */
-#define CPUMPRL 0x38000 /* Charge Pump Release Time */
-#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */
-#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */
-#define PGMTIME 0xff000000 /* Program Time */
-
/* Bit masks for SECURE_SYSSWT */
#define EMUDABL 0x1 /* Emulation Disable. */
#define nEMUOVR 0x0
#define OTPSEN 0x8000 /* OTP Secrets Enable. */
#define nOTPSEN 0x0
-#define L2DABL 0x70000 /* L2 Memory Disable. */
/* Bit masks for SECURE_CONTROL */
*
* defBF532.h
*
- * Copyright (C) 2008 Analog Devices, Inc.
+ * Copyright (C) 2008, 2009 Analog Devices, Inc.
*
************************************************************************/
#ifdef _MISRA_RULES
#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4)
#pragma diag(suppress:misra_rule_19_7)
#endif /* _MISRA_RULES */
/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
#define SYSCR 0xFFC00104 /* System Configuration registe */
-#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
/* ********************* PLL AND RESET MASKS ************************ */
/*// PLL_CTL Masks */
+#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
+#define SPORT_HYS 0x8000 /* Add 250mV of Hysteresis to SPORT Inputs */
+
+/* PLL_STAT Masks */
+#define VSTAT 0x0080 /* Voltage Regulator Status: Regulator at programmed voltage */
+#define CORE_IDLE 0x0040 /* processor is in the IDLE operating mode */
+#define SLEEP 0x0010 /* processor is in the Sleep operating mode */
+#define DEEP_SLEEP 0x0008 /* processor is in the Deep Sleep operating mode */
+
#define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */
#define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */
#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
#define BYPASS 0x0100 /* Bypass the PLL */
/* PLL_CTL Macros */
+#ifdef _MISRA_RULES
+#define SET_MSEL(x) (((x)&0x3Fu) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
+#else
#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
+#endif /* _MISRA_RULES */
/* PLL_DIV Masks */
#define SSEL 0x000F /* System Select */
#define CCLK_DIV4 0x0020 /* CCLK = VCO / 4 */
#define CCLK_DIV8 0x0030 /* CCLK = VCO / 8 */
/* PLL_DIV Macros */
+#ifdef _MISRA_RULES
+#define SET_SSEL(x) ((x)&0xFu) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
+#else
#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
+#endif /* _MISRA_RULES */
/* PLL_STAT Masks */
#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
/* SYSCR Masks */
+#define BMODE_BYPASS 0x0000 /* Bypass boot ROM, execute from 16-bit external memory */
+#define BMODE_FLASH 0x0001 /* Use Boot ROM to load from 8-bit or 16-bit flash */
+#define BMODE_SPIHOST 0x0002 /* Boot from SPI0 host (slave mode) */
+#define BMODE_SPIMEM 0x0003 /* Boot from serial SPI memory */
#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
#define MDMA1_IRQ 0x00400000 /* MemDMA Stream 1 Interrupt Request */
#define WDOG_IRQ 0x00800000 /* Software Watchdog Timer Interrupt Request */
+#ifdef _MISRA_RULES
+#define _MF15 0xFu
+#define _MF7 7u
+#else
+#define _MF15 0xF
+#define _MF7 7
+#endif /* _MISRA_RULES */
/* SIC_IAR0 Macros */
-#define P0_IVG(x) (((x)-7)&0xF) /* Peripheral #0 assigned IVG #x */
-#define P1_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #1 assigned IVG #x */
-#define P2_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #2 assigned IVG #x */
-#define P3_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #3 assigned IVG #x */
-#define P4_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #4 assigned IVG #x */
-#define P5_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #5 assigned IVG #x */
-#define P6_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #6 assigned IVG #x */
-#define P7_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #7 assigned IVG #x */
+#define P0_IVG(x) (((x)-_MF7)&_MF15) /* Peripheral #0 assigned IVG #x */
+#define P1_IVG(x) (((x)-_MF7)&_MF15) << 0x4 /* Peripheral #1 assigned IVG #x */
+#define P2_IVG(x) (((x)-_MF7)&_MF15) << 0x8 /* Peripheral #2 assigned IVG #x */
+#define P3_IVG(x) (((x)-_MF7)&_MF15) << 0xC /* Peripheral #3 assigned IVG #x */
+#define P4_IVG(x) (((x)-_MF7)&_MF15) << 0x10 /* Peripheral #4 assigned IVG #x */
+#define P5_IVG(x) (((x)-_MF7)&_MF15) << 0x14 /* Peripheral #5 assigned IVG #x */
+#define P6_IVG(x) (((x)-_MF7)&_MF15) << 0x18 /* Peripheral #6 assigned IVG #x */
+#define P7_IVG(x) (((x)-_MF7)&_MF15) << 0x1C /* Peripheral #7 assigned IVG #x */
/* SIC_IAR1 Macros */
-#define P8_IVG(x) (((x)-7)&0xF) /* Peripheral #8 assigned IVG #x */
-#define P9_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #9 assigned IVG #x */
-#define P10_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #10 assigned IVG #x */
-#define P11_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #11 assigned IVG #x */
-#define P12_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #12 assigned IVG #x */
-#define P13_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #13 assigned IVG #x */
-#define P14_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #14 assigned IVG #x */
-#define P15_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #15 assigned IVG #x */
+#define P8_IVG(x) (((x)-_MF7)&_MF15) /* Peripheral #8 assigned IVG #x */
+#define P9_IVG(x) (((x)-_MF7)&_MF15) << 0x4 /* Peripheral #9 assigned IVG #x */
+#define P10_IVG(x) (((x)-_MF7)&_MF15) << 0x8 /* Peripheral #10 assigned IVG #x */
+#define P11_IVG(x) (((x)-_MF7)&_MF15) << 0xC /* Peripheral #11 assigned IVG #x */
+#define P12_IVG(x) (((x)-_MF7)&_MF15) << 0x10 /* Peripheral #12 assigned IVG #x */
+#define P13_IVG(x) (((x)-_MF7)&_MF15) << 0x14 /* Peripheral #13 assigned IVG #x */
+#define P14_IVG(x) (((x)-_MF7)&_MF15) << 0x18 /* Peripheral #14 assigned IVG #x */
+#define P15_IVG(x) (((x)-_MF7)&_MF15) << 0x1C /* Peripheral #15 assigned IVG #x */
/* SIC_IAR2 Macros */
-#define P16_IVG(x) (((x)-7)&0xF) /* Peripheral #16 assigned IVG #x */
-#define P17_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #17 assigned IVG #x */
-#define P18_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #18 assigned IVG #x */
-#define P19_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #19 assigned IVG #x */
-#define P20_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #20 assigned IVG #x */
-#define P21_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #21 assigned IVG #x */
-#define P22_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #22 assigned IVG #x */
-#define P23_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #23 assigned IVG #x */
+#define P16_IVG(x) (((x)-_MF7)&_MF15) /* Peripheral #16 assigned IVG #x */
+#define P17_IVG(x) (((x)-_MF7)&_MF15) << 0x4 /* Peripheral #17 assigned IVG #x */
+#define P18_IVG(x) (((x)-_MF7)&_MF15) << 0x8 /* Peripheral #18 assigned IVG #x */
+#define P19_IVG(x) (((x)-_MF7)&_MF15) << 0xC /* Peripheral #19 assigned IVG #x */
+#define P20_IVG(x) (((x)-_MF7)&_MF15) << 0x10 /* Peripheral #20 assigned IVG #x */
+#define P21_IVG(x) (((x)-_MF7)&_MF15) << 0x14 /* Peripheral #21 assigned IVG #x */
+#define P22_IVG(x) (((x)-_MF7)&_MF15) << 0x18 /* Peripheral #22 assigned IVG #x */
+#define P23_IVG(x) (((x)-_MF7)&_MF15) << 0x1C /* Peripheral #23 assigned IVG #x */
/* SIC_IARx Macros */
+#ifdef _MISRA_RULES
+#define PX_IVG_CLR(x) (0xFFFFFFFFu ^ (0xFu << (((x)%8)*4))) /* Clear IVG Select for Peripheral #x */
+/* Usage: *pSIC_IAR1 &= PX_IVG_CLR(11); // Clears IVG Level of Peripheral #11 */
+#define PX_IVG(x,y) ((((y)-7u)&0xFu) << (((x)%8)*4)) /* Set IVG Select to #y for Peripheral #x */
+/* Usage: *pSIC_IAR1 |= PX_IVG(11, 8); // Sets Peripheral #11 to IVG8 */
+#else
#define PX_IVG_CLR(x) (0xFFFFFFFF ^ (0xF << (((x)%8)*4))) /* Clear IVG Select for Peripheral #x */
/* Usage: *pSIC_IAR1 &= PX_IVG_CLR(11); // Clears IVG Level of Peripheral #11 */
#define PX_IVG(x,y) ((((y)-7)&0xF) << (((x)%8)*4)) /* Set IVG Select to #y for Peripheral #x */
/* Usage: *pSIC_IAR1 |= PX_IVG(11, 8); // Sets Peripheral #11 to IVG8 */
+#endif /* _MISRA_RULES */
/* SIC_IMASK Masks */
#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
+#ifdef _MISRA_RULES
+#define SIC_MASK(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
+#define SIC_UNMASK(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Unmask Peripheral #x interrupt */
+#else
#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
+#endif /* _MISRA_RULES */
/* SIC_IWR Masks */
#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
+#ifdef _MISRA_RULES
+#define IWR_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
+#define IWR_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Wakeup Disable Peripheral #x */
+#else
#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
-
+#endif /* _MISRA_RULES */
/* ********* WATCHDOG TIMER MASKS ******************** */
/* Watchdog Timer WDOG_CTL Register Masks */
+#ifdef _MISRA_RULES
+#define WDEV(x) (((x)<<1) & 0x0006u) /* event generated on roll over */
+#else
#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
+#endif /* _MISRA_RULES */
#define WDEV_RESET 0x0000 /* generate reset event on roll over */
#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
/* ** Must be set after power-up for proper operation of RTC */
/* RTC_ALARM Macro z=day y=hr x=min w=sec */
+#ifdef _MISRA_RULES
+#define SET_ALARM(z,y,x,w) ((((z)&0x7FFFu)<<0x11)|(((y)&0x1Fu)<<0xC)|(((x)&0x3Fu)<<0x6)|((w)&0x3Fu))
+#else
#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
+#endif /* _MISRA_RULES */
/* Deprecated RTC_STAT and RTC_ALARM Masks */
#define RTC_SEC RTSEC /* Real-Time Clock Seconds */
/* ***************************** UART CONTROLLER MASKS ********************** */
/* UART_LCR Register */
+#ifdef _MISRA_RULES
+#define WLS(x) (((x)-5u) & 0x03u) /* Word Length Select */
+#else
#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
+#endif /* _MISRA_RULES */
#define STB 0x04 /* Stop Bits */
#define PEN 0x08 /* Parity Enable */
#define EPS 0x10 /* Even Parity Select */
#define ERBFI_P 0x00
/* UART_IIR Register */
+#ifdef _MISRA_RULES
+#define STATUS(x) (((x) << 1) & 0x06u)
+#else
#define STATUS(x) (((x) << 1) & 0x06)
+#endif /* _MISRA_RULES */
#define NINT 0x01
#define STATUS_P1 0x02
#define STATUS_P0 0x01
defined(__ADSPBF533__)
# define SLEN 0x001F
#else
+#ifdef _MISRA_RULES
+# define SLEN(x) ((x)&0x1Fu) /* SPORT TX Word Length (2 - 31) */
+#else
# define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
+#endif /* _MISRA_RULES */
#endif
#define TXSE 0x0100 /*TX Secondary Enable */
#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
#define WSIZE 0x0000F000 /*Multichannel Window Size Field */
#define WOFF 0x000003FF /*Multichannel Window Offset Field */
/* SPORTx_MCMC1 Macros */
+#ifdef _MISRA_RULES
+#define SET_WOFF(x) ((x) & 0x3FFu) /* Multichannel Window Offset Field */
+/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
+#define SET_WSIZE(x) (((((x)>>0x3)-1u)&0xFu) << 0xC) /* Multichannel Window Size = (x/8)-1 */
+#else
#define SET_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
#define SET_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
+#endif /* _MISRA_RULES */
/*SPORTx_MCMC2 Masks */
#define MCCRM 0x0003 /*Multichannel Clock Recovery Mode */
#define DLEN_14 0x2800 /* Data Length = 14 Bits */
#define DLEN_15 0x3000 /* Data Length = 15 Bits */
#define DLEN_16 0x3800 /* Data Length = 16 Bits */
+#ifdef _MISRA_RULES
+#define DLEN(x) ((((x)-9u) & 0x07u) << 11) /* PPI Data Length (only works for x=10-->x=16) */
+#else
#define DLEN(x) ((((x)-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
+#endif /* _MISRA_RULES */
#define POL 0xC000 /* PPI Signal Polarities */
#define POLC 0x4000 /* PPI Clock Polarity */
#define POLS 0x8000 /* PPI Frame Sync Polarity */
#define CLK_SEL 0x0080
#define TOGGLE_HI 0x0100
#define EMU_RUN 0x0200
+#ifdef _MISRA_RULES
+#define ERR_TYP(x) (((x) & 0x03u) << 14)
+#else
#define ERR_TYP(x) (((x) & 0x03) << 14)
+#endif /* _MISRA_RULES */
#define TMODE_P0 0x00
#define TMODE_P1 0x01
/* ********************** SDRAM CONTROLLER MASKS *************************** */
/* EBIU_SDGCTL Masks */
+
+
#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
+#define CL 0x0000000C /* SDRAM CAS latency */
#define PFE 0x00000010 /* Enable SDRAM prefetch */
#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
+#define PASR 0x00000030 /* SDRAM partial array self-refresh */
#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
+#define TRAS 0x000003C0 /* SDRAM tRAS in SCLK cycles */
#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
+#define TRP 0x00003800 /* SDRAM tRP in SCLK cycles */
#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
+#define TRCD 0x00030000 /* SDRAM tRCD in SCLK cycles */
#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
+#define TWR 0x00180000 /* SDRAM tWR in SCLK cycles */
#define PUPSD 0x00200000 /*Power-up start delay */
#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
/* EBIU_SDBCTL Masks */
#define EBE 0x00000001 /* Enable SDRAM external bank */
-#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */
-#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */
-#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */
+#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */
+#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */
+#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */
#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */
-#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
+#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
+#define EBSZ 0x0006 /* SDRAM external bank size */
+#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
+#define EBCAW 0x0030 /* SDRAM external bank column address width */
/* EBIU_SDSTAT Masks */
#define SDCI 0x00000001 /* SDRAM controller is idle */
*/
/*
-** Copyright (C) 2008 Analog Devices, Inc.
+** Copyright (C) 2008, 2009 Analog Devices, Inc.
**
************************************************************************************
**
#ifdef _MISRA_RULES
#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_7)
+#pragma diag(suppress:misra_rule_19_4:"ADI header allows any substitution")
+#pragma diag(suppress:misra_rule_19_7:"ADI header allows function macros")
+
#endif /* _MISRA_RULES */
/************************************************************************************
/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
#define SWRST 0xFFC00100 /* Software Reset Register */
#define SYSCR 0xFFC00104 /* System Configuration Register */
-#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
-#define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */
#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */
-#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */
+#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Reload/Capture Register */
#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */
/* Mailbox Acceptance Masks */
#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
#define BYPASS 0x0100 /* Bypass the PLL */
#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
+#define SPORT_HYS 0x8000 /* Add 250mV of Hysteresis to SPORT Inputs */
/* PLL_CTL Macros */
+#ifdef _MISRA_RULES
+#define SET_MSEL(x) (((x)&0x3Fu) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
+#else
#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
+#endif /* _MISRA_RULES */
/* PLL_DIV Masks */
#define SSEL 0x000F /* System Select */
#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
/* PLL_DIV Macros */
+#ifdef _MISRA_RULES
+#define SET_SSEL(x) ((x)&0xFu) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
+#else
#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
+#endif /* _MISRA_RULES */
/* VR_CTL Masks */
#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
/* SYSCR Masks */
+/* SYSCR Masks */
+#define BMODE_BYPASS 0x0000 /* Bypass boot ROM, execute from 16-bit external memory */
+#define BMODE_FLASH 0x0001 /* Use Boot ROM to load from 8-bit or 16-bit flash */
+#define BMODE_SPIMEM 0x0003 /* Boot from serial SPI memory */
+#define BMODE_SPIHOST 0x0004 /* Boot from SPI0 host (slave mode) */
+#define BMODE_TWIMEM 0x0005 /* Boot from serial TWI memory */
+#define BMODE_TWIHOST 0x0006 /* Boot from TWI0 host (slave mode) */
+#define BMODE_UARTHOST 0x0007 /* Boot from UART0 host */
#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */
#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */
+#ifdef _MISRA_RULES
+#define _MF15 0xFu
+#define _MF7 7u
+#else
+#define _MF15 0xF
+#define _MF7 7
+#endif /* _MISRA_RULES */
+
/* SIC_IAR0 Macros */
-#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
-#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
-#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
-#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
-#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
-#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
-#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
-#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
+#define P0_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #0 assigned IVG #x */
+#define P1_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #1 assigned IVG #x */
+#define P2_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #2 assigned IVG #x */
+#define P3_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #3 assigned IVG #x */
+#define P4_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #4 assigned IVG #x */
+#define P5_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #5 assigned IVG #x */
+#define P6_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #6 assigned IVG #x */
+#define P7_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #7 assigned IVG #x */
/* SIC_IAR1 Macros */
-#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
-#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
-#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
-#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
-#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
-#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
-#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
-#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
+#define P8_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #8 assigned IVG #x */
+#define P9_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #9 assigned IVG #x */
+#define P10_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #10 assigned IVG #x */
+#define P11_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #11 assigned IVG #x */
+#define P12_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #12 assigned IVG #x */
+#define P13_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #13 assigned IVG #x */
+#define P14_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #14 assigned IVG #x */
+#define P15_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #15 assigned IVG #x */
/* SIC_IAR2 Macros */
-#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
-#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
-#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
-#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
-#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
-#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
-#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
-#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
+#define P16_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #16 assigned IVG #x */
+#define P17_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #17 assigned IVG #x */
+#define P18_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #18 assigned IVG #x */
+#define P19_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #19 assigned IVG #x */
+#define P20_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #20 assigned IVG #x */
+#define P21_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #21 assigned IVG #x */
+#define P22_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #22 assigned IVG #x */
+#define P23_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #23 assigned IVG #x */
/* SIC_IAR3 Macros */
-#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
-#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
-#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
-#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
-#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
-#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
-#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
-#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
+#define P24_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #24 assigned IVG #x */
+#define P25_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #25 assigned IVG #x */
+#define P26_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #26 assigned IVG #x */
+#define P27_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #27 assigned IVG #x */
+#define P28_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #28 assigned IVG #x */
+#define P29_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #29 assigned IVG #x */
+#define P30_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #30 assigned IVG #x */
+#define P31_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #31 assigned IVG #x */
/* SIC_IMASK Masks */
#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
+#ifdef _MISRA_RULES
+#define SIC_MASK(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
+#define SIC_UNMASK(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Unmask Peripheral #x interrupt */
+#else
#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
+#endif /* _MISRA_RULES */
/* SIC_IWR Masks */
#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
+#ifdef _MISRA_RULES
+#define IWR_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
+#define IWR_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Wakeup Disable Peripheral #x */
+#else
#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
+#endif /* _MISRA_RULES */
/* ********* WATCHDOG TIMER MASKS ******************** */
/* Watchdog Timer WDOG_CTL Register Masks */
+#ifdef _MISRA_RULES
+#define WDEV(x) (((x)<<1) & 0x0006u) /* event generated on roll over */
+#else
#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
+#endif /* _MISRA_RULES */
#define WDEV_RESET 0x0000 /* generate reset event on roll over */
#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
#define RTC_DAY 0xFFFE0000 /* Real-Time Clock Days */
/* RTC_ALARM Macro z=day y=hr x=min w=sec */
+#ifdef _MISRA_RULES
+#define SET_ALARM(z,y,x,w) ((((z)&0x7FFFu)<<0x11)|(((y)&0x1Fu)<<0xC)|(((x)&0x3Fu)<<0x6)|((w)&0x3Fu))
+#else
#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
+#endif /* _MISRA_RULES */
/* RTC_ICTL and RTC_ISTAT Masks */
#define STOPWATCH 0x0001 /* Stopwatch Interrupt Enable */
/* ************** UART CONTROLLER MASKS *************************/
/* UARTx_LCR Masks */
+#ifdef _MISRA_RULES
+#define WLS(x) (((x)-5u) & 0x03u) /* Word Length Select */
+#else
#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
+#endif /* _MISRA_RULES */
#define STB 0x04 /* Stop Bits */
#define PEN 0x08 /* Parity Enable */
#define EPS 0x10 /* Even Parity Select */
#define FPE 0x10 /* Force Parity Error On Transmit */
#define FFE 0x20 /* Force Framing Error On Transmit */
+/* Bit masks for UART Divisor Latch Registers: UARTx_DLL & UARTx_DLH */
+#define UARTDLL 0x00FF /* Divisor Latch Low Byte */
+#define UARTDLH 0xFF00 /* Divisor Latch High Byte */
+
/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/
/* SPI_CTL Masks */
/* SPORTx_TCR1 Masks */
#define TSPEN 0x0001 /* Transmit Enable */
#define ITCLK 0x0002 /* Internal Transmit Clock Select */
-#define DTYPE_NORM 0x0004 /* Data Format Normal */
+#define DTYPE_NORM 0x0000 /* Data Format Normal */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define TLSBIT 0x0010 /* Transmit Bit Order */
#define TCKFE 0x4000 /* Clock Falling Edge Select */
/* SPORTx_TCR2 Masks and Macro */
+#ifdef _MISRA_RULES
+#define SLEN(x) ((x)&0x1Fu) /* SPORT TX Word Length (2 - 31) */
+#else
#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
+#endif /* _MISRA_RULES */
#define TXSE 0x0100 /* TX Secondary Enable */
#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
/* SPORTx_RCR1 Masks */
#define RSPEN 0x0001 /* Receive Enable */
#define IRCLK 0x0002 /* Internal Receive Clock Select */
-#define DTYPE_NORM 0x0004 /* Data Format Normal */
+#define DTYPE_NORM 0x0000 /* Data Format Normal */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define RLSBIT 0x0010 /* Receive Bit Order */
#define RCKFE 0x4000 /* Clock Falling Edge Select */
/* SPORTx_RCR2 Masks */
+#ifdef _MISRA_RULES
+#define SLEN(x) ((x)&0x1Fu) /* SPORT RX Word Length (2 - 31) */
+#else
#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
+#endif /* _MISRA_RULES */
#define RXSE 0x0100 /* RX Secondary Enable */
#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
#define RRFST 0x0400 /* Right-First Data Order */
#define TXHRE 0x0040 /* Transmit Hold Register Empty */
/* SPORTx_MCMC1 Macros */
+#ifdef _MISRA_RULES
+#define WOFF(x) ((x) & 0x3FFu) /* Multichannel Window Offset Field */
+
+/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
+#define WSIZE(x) (((((x)>>0x3)-1u)&0xFu) << 0xC) /* Multichannel Window Size = (x/8)-1 */
+#else
#define WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
#define WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
+#endif /* _MISRA_RULES */
/* SPORTx_MCMC2 Masks */
#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
/* ********************** SDRAM CONTROLLER MASKS **********************************************/
/* EBIU_SDGCTL Masks */
+
#define SCTLE 0x00000001 /* Enable SDRAM Signals */
#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
+#define CL 0x0000000C /* SDRAM CAS latency */
#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
+#define PASR 0x00000030 /* SDRAM partial array self-refresh */
#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
+#define TRAS 0x000003C0 /* SDRAM tRAS in SCLK cycles */
#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
+#define TRP 0x00003800 /* SDRAM tRP in SCLK cycles */
#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
+#define TRCD 0x00030000 /* SDRAM tRCD in SCLK cycles */
#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
+#define TWR 0x00180000 /* SDRAM tWR in SCLK cycles */
#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
-#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
-#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
+#define EBSZ 0x0006 /* SDRAM external bank size */
+
#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
+#define EBCAW 0x0030 /* SDRAM external bank column address width */
/* EBIU_SDSTAT Masks */
#define SDCI 0x0001 /* SDRAM Controller Idle */
/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
+#ifdef _MISRA_RULES
+#define CLKLOW(x) ((x) & 0xFFu) /* Periods Clock Is Held Low */
+#define CLKHI(y) (((y)&0xFFu)<<0x8) /* Periods Before New Clock Low */
+#else
#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
+#endif /* _MISRA_RULES */
/* TWI_PRESCALE Masks */
#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
+#ifdef _MISRA_RULES
+#define PJCE(x) (((x)&0x3u)<<1) /* Port J CAN/SPI/SPORT Enable */
+#else
#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
+#endif /* _MISRA_RULES */
+
#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
*
* defBF535.h
*
- * Copyright (C) 2008 Analog Devices, Inc.
+ * Copyright (C) 2008, 2009 Analog Devices, Inc.
*
************************************************************************/
/* include all Core registers and bit definitions */
#include <defblackfin.h>
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
+#endif /* _MISRA_RULES */
/*********************************************************************************** */
/* Memory Map */
#define CHIPID 0xFFC048C0 /* Device ID Register */
/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
-#define SIC_RVECT 0xFFC00C00 /* Reset Vector Register */
#define SIC_IAR0 0xFFC00C04 /* Interrupt Assignment Register 0 */
#define SIC_IAR1 0xFFC00C08 /* Interrupt Assignment Register 1 */
#define SIC_IAR2 0xFFC00C0C /* Interrupt Assignment Register 2 */
#define B7WAT_14 0x0000E000 /* Bank 7 Write Access Time = 14 cycles */
#define B7WAT_15 0x0000F000 /* Bank 7 Write Access Time = 15 cycles */
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
#endif /* __DEF_BF535_H */
*/
/*
-** Copyright (C) 2008 Analog Devices, Inc.
+** Copyright (C) 2008, 2009 Analog Devices, Inc.
**
************************************************************************************
**
#pragma diag(push)
#pragma diag(suppress:misra_rule_19_4)
#pragma diag(suppress:misra_rule_19_7)
+#pragma diag(suppress:misra_rule_19_11)
#endif /* _MISRA_RULES */
#define REGAD 0x000007C0 /* STA Register Address */
#define PHYAD 0x0000F800 /* PHY Device Address */
+#ifdef _MISRA_RULES
+#define SET_REGAD(x) (((x)&0x1Fu)<< 6 ) /* Set STA Register Address */
+#define SET_PHYAD(x) (((x)&0x1Fu)<< 11 ) /* Set PHY Device Address */
+#else
#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
+#endif /* _MISRA_RULES */
/* EMAC_STADAT Mask */
#define STADATA 0x0000FFFF /* Station Management Data */
#define BKPRSEN 0x00000008 /* Enable Backpressure */
#define FLCPAUSE 0xFFFF0000 /* Pause Time */
+#ifdef _MISRA_RULES
+#define SET_FLCPAUSE(x) (((x)&0xFFFFu)<< 16) /* Set Pause Time */
+#else
#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
+#endif /* _MISRA_RULES */
/* EMAC_WKUP_CTL Masks */
#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
+#ifdef _MISRA_RULES
+#define SET_WF0_OFF(x) (((x)&0xFFu)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
+#define SET_WF1_OFF(x) (((x)&0xFFu)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
+#define SET_WF2_OFF(x) (((x)&0xFFu)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
+#define SET_WF3_OFF(x) (((x)&0xFFu)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
+#else
#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
+#endif /* _MISRA_RULES */
+
/* Set ALL Offsets */
#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
+#ifdef _MISRA_RULES
+#define SET_WF0_CRC(x) (((x)&0xFFFFu)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
+#define SET_WF1_CRC(x) (((x)&0xFFFFu)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
+#else
#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
+#endif /* _MISRA_RULES */
/* EMAC_WKUP_FFCRC1 Masks */
#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
+#ifdef _MISRA_RULES
+#define SET_WF2_CRC(x) (((x)&0xFFFFu)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
+#define SET_WF3_CRC(x) (((x)&0xFFFFu)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
+#else
#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
+#endif /* _MISRA_RULES */
/* EMAC_SYSCTL Masks */
#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
-
+#if !defined(__SILICON_REVISION__) || (__SILICON_REVISION__>0x2)
+/* In BF536/7 revs. 0.0, 0.1 and 0.2, this bit was reserved */
+#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment(Even/Odd*) */
+#endif
+#ifdef _MISRA_RULES
+#define SET_MDCDIV(x) (((x)&0x3Fu)<< 8) /* Set MDC Clock Divisor */
+#else
#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
+#endif /* _MISRA_RULES */
/* EMAC_SYSTAT Masks */
#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
**
** defBF538.h
**
-** Copyright (C) 2008 Analog Devices, Inc.
+** Copyright (C) 2008, 2009 Analog Devices, Inc.
**
*************************************************************************/
#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
-#define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */
#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */
-#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */
+#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Reload/Capture Register */
#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */
/* Mailbox Acceptance Masks */
/* ********************* PLL AND RESET MASKS ****************************************/
/* PLL_CTL Masks (IN_DELAY and OUT_DELAY bit field definitions differ from BF533/BF532/BF531) */
+#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
#define IN_DELAY 0x0014 /* EBIU Input Delay Select */
#define OUT_DELAY 0x00C0 /* EBIU Output Delay Select */
+#ifdef _MISRA_RULES
+#define SET_OUT_DELAY(x) (((x)&0x03u) << 0x6)
+#define SET_IN_DELAY(x) ((((x)&0x02u) << 0x3) | (((x)&0x01u) << 0x2))
+#else
#define SET_OUT_DELAY(x) (((x)&0x03) << 0x6)
#define SET_IN_DELAY(x) ((((x)&0x02) << 0x3) | (((x)&0x01) << 0x2))
+#endif /* _MISRA_RULES */
/* VR_CTL Masks (Additional WakeUp Events) */
#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
#define MDMA1_0_IRQ 0x00020000 /* MemDMA1 Stream 0 Interrupt Request */
#define MDMA1_1_IRQ 0x00040000 /* MemDMA1 Stream 1 Interrupt Request */
-
+#ifdef _MISRA_RULES
+#define _MF15 0xFu
+#define _MF7 7u
+#else
+#define _MF15 0xF
+#define _MF7 7
+#endif /* _MISRA_RULES */
/* SIC_IAR3 Macros */
-#define P24_IVG(x) (((x)-7)&0xF) /* Peripheral #24 assigned IVG #x */
-#define P25_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #25 assigned IVG #x */
-#define P26_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #26 assigned IVG #x */
-#define P27_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #27 assigned IVG #x */
-#define P28_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #28 assigned IVG #x */
-#define P29_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #29 assigned IVG #x */
-#define P30_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #30 assigned IVG #x */
-#define P31_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #31 assigned IVG #x */
+#define P24_IVG(x) (((x)-_MF7)&_MF15) /* Peripheral #24 assigned IVG #x */
+#define P25_IVG(x) (((x)-_MF7)&_MF15) << 0x4 /* Peripheral #25 assigned IVG #x */
+#define P26_IVG(x) (((x)-_MF7)&_MF15) << 0x8 /* Peripheral #26 assigned IVG #x */
+#define P27_IVG(x) (((x)-_MF7)&_MF15) << 0xC /* Peripheral #27 assigned IVG #x */
+#define P28_IVG(x) (((x)-_MF7)&_MF15) << 0x10 /* Peripheral #28 assigned IVG #x */
+#define P29_IVG(x) (((x)-_MF7)&_MF15) << 0x14 /* Peripheral #29 assigned IVG #x */
+#define P30_IVG(x) (((x)-_MF7)&_MF15) << 0x18 /* Peripheral #30 assigned IVG #x */
+#define P31_IVG(x) (((x)-_MF7)&_MF15) << 0x1C /* Peripheral #31 assigned IVG #x */
/* SIC_IAR4 Macros */
-#define P32_IVG(x) (((x)-7)&0xF) /* Peripheral #32 assigned IVG #x */
-#define P33_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #33 assigned IVG #x */
-#define P34_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #34 assigned IVG #x */
-#define P35_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #35 assigned IVG #x */
-#define P36_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #36 assigned IVG #x */
-#define P37_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #37 assigned IVG #x */
-#define P38_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #38 assigned IVG #x */
-#define P39_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #39 assigned IVG #x */
+#define P32_IVG(x) (((x)-_MF7)&_MF15) /* Peripheral #32 assigned IVG #x */
+#define P33_IVG(x) (((x)-_MF7)&_MF15) << 0x4 /* Peripheral #33 assigned IVG #x */
+#define P34_IVG(x) (((x)-_MF7)&_MF15) << 0x8 /* Peripheral #34 assigned IVG #x */
+#define P35_IVG(x) (((x)-_MF7)&_MF15) << 0xC /* Peripheral #35 assigned IVG #x */
+#define P36_IVG(x) (((x)-_MF7)&_MF15) << 0x10 /* Peripheral #36 assigned IVG #x */
+#define P37_IVG(x) (((x)-_MF7)&_MF15) << 0x14 /* Peripheral #37 assigned IVG #x */
+#define P38_IVG(x) (((x)-_MF7)&_MF15) << 0x18 /* Peripheral #38 assigned IVG #x */
+#define P39_IVG(x) (((x)-_MF7)&_MF15) << 0x1C /* Peripheral #39 assigned IVG #x */
/* SIC_IAR5 Macros */
-#define P40_IVG(x) (((x)-7)&0xF) /* Peripheral #40 assigned IVG #x */
-#define P41_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #41 assigned IVG #x */
-#define P42_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #42 assigned IVG #x */
-#define P43_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #43 assigned IVG #x */
-#define P44_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #44 assigned IVG #x */
-#define P45_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #45 assigned IVG #x */
-#define P46_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #46 assigned IVG #x */
-#define P47_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #47 assigned IVG #x */
+#define P40_IVG(x) (((x)-_MF7)&_MF15) /* Peripheral #40 assigned IVG #x */
+#define P41_IVG(x) (((x)-_MF7)&_MF15) << 0x4 /* Peripheral #41 assigned IVG #x */
+#define P42_IVG(x) (((x)-_MF7)&_MF15) << 0x8 /* Peripheral #42 assigned IVG #x */
+#define P43_IVG(x) (((x)-_MF7)&_MF15) << 0xC /* Peripheral #43 assigned IVG #x */
+#define P44_IVG(x) (((x)-_MF7)&_MF15) << 0x10 /* Peripheral #44 assigned IVG #x */
+#define P45_IVG(x) (((x)-_MF7)&_MF15) << 0x14 /* Peripheral #45 assigned IVG #x */
+#define P46_IVG(x) (((x)-_MF7)&_MF15) << 0x18 /* Peripheral #46 assigned IVG #x */
+#define P47_IVG(x) (((x)-_MF7)&_MF15) << 0x1C /* Peripheral #47 assigned IVG #x */
/* SIC_IAR6 Macros */
-#define P48_IVG(x) (((x)-7)&0xF) /* Peripheral #48 assigned IVG #x */
-#define P49_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #49 assigned IVG #x */
-#define P50_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #50 assigned IVG #x */
-#define P51_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #51 assigned IVG #x */
-#define P52_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #52 assigned IVG #x */
-#define P53_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #53 assigned IVG #x */
-#define P54_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #54 assigned IVG #x */
-#define P55_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #55 assigned IVG #x */
+#define P48_IVG(x) (((x)-_MF7)&_MF15) /* Peripheral #48 assigned IVG #x */
+#define P49_IVG(x) (((x)-_MF7)&_MF15) << 0x4 /* Peripheral #49 assigned IVG #x */
+#define P50_IVG(x) (((x)-_MF7)&_MF15) << 0x8 /* Peripheral #50 assigned IVG #x */
+#define P51_IVG(x) (((x)-_MF7)&_MF15) << 0xC /* Peripheral #51 assigned IVG #x */
+#define P52_IVG(x) (((x)-_MF7)&_MF15) << 0x10 /* Peripheral #52 assigned IVG #x */
+#define P53_IVG(x) (((x)-_MF7)&_MF15) << 0x14 /* Peripheral #53 assigned IVG #x */
+#define P54_IVG(x) (((x)-_MF7)&_MF15) << 0x18 /* Peripheral #54 assigned IVG #x */
+#define P55_IVG(x) (((x)-_MF7)&_MF15) << 0x1C /* Peripheral #55 assigned IVG #x */
/******************* GPIO MASKS *********************/
#define PMAP_UART2RX 0xA000 /* PMAP UART2 Receive DMA */
#define PMAP_UART2TX 0xB000 /* PMAP UART2 Transmit DMA */
+/* EBIU_SDBCTL Masks */
+#define EBSZ 0x0006 /* SDRAM external bank size */
+#define EBCAW 0x0030 /* SDRAM external bank column address width */
+
+/* EBIU_SDGCTL Masks */
+#define CL 0x0000000C /* SDRAM CAS latency */
+#define PASR 0x00000030 /* SDRAM partial array self-refresh */
+#define TRAS 0x000003C0 /* SDRAM tRAS in SCLK cycles */
+#define TRP 0x00003800 /* SDRAM tRP in SCLK cycles */
+#define TRCD 0x00030000 /* SDRAM tRCD in SCLK cycles */
+#define TWR 0x00180000 /* SDRAM tWR in SCLK cycles */
/* ******************** TWO-WIRE INTERFACE (TWIx) MASKS ***********************/
/* TWIx_CLKDIV Macros (Use: *pTWIx_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
+#ifdef _MISRA_RULES
+#define CLKLOW(x) ((x) & 0xFFu) /* Periods Clock Is Held Low */
+#define CLKHI(y) (((y)&0xFFu)<<0x8) /* Periods Before New Clock Low */
+#else
#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
+#endif /* _MISRA_RULES */
/* TWIx_PRESCALE Masks */
#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
*/
/*
-** Copyright (C) 2008 Analog Devices, Inc.
+** Copyright (C) 2008, 2009 Analog Devices, Inc.
**
************************************************************************************
**
/* Include all Core registers and bit definitions */
#include <def_LPBlackfin.h>
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"some macros violate rule 19.4")
+#pragma diag(suppress:misra_rule_19_7:"Allow function-like macros ")
+#endif /* _MISRA_RULES */
+
/*********************************************************************************** */
/* System MMR Register Map */
/*********************************************************************************** */
/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
#define SYSCR 0xFFC00104 /* System Configuration registe */
-#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
-#define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */
#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */
-#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */
+#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Reload/Capture Register */
#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */
/* Mailbox Acceptance Masks */
#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
/* PLL_CTL Macros */
+#ifdef _MISRA_RULES
+#define SET_MSEL(x) (((x)&0x3Fu) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
+#define SET_OUT_DELAY(x) (((x)&0x03u) << 0x6)
+#define SET_IN_DELAY(x) ((((x)&0x02u) << 0x3) | (((x)&0x01u) << 0x2))
+#else
#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
-
#define SET_OUT_DELAY(x) (((x)&0x03) << 0x6)
#define SET_IN_DELAY(x) ((((x)&0x02) << 0x3) | (((x)&0x01) << 0x2))
+#endif /* _MISRA_RULES */
/* PLL_DIV Masks */
#define SSEL 0x000F /* System Select */
#define CCLK_DIV8 0x0030 /* CCLK = VCO / 8 */
/* PLL_DIV Macros */
+#ifdef _MISRA_RULES
+#define SET_SSEL(x) ((x)&0xFu) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
+#else
#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
+#endif /* _MISRA_RULES */
/* PLL_STAT Masks */
#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
#define MDMA0_IRQ MDMA1_0_IRQ
#define MDMA1_IRQ MDMA1_1_IRQ
+#ifdef _MISRA_RULES
+#define _MF15 0xFu
+#define _MF7 7u
+#else
+#define _MF15 0xF
+#define _MF7 7
+#endif /* _MISRA_RULES */
+
/* SIC_IAR0 Macros */
-#define P0_IVG(x) (((x)-7)&0xF) /* Peripheral #0 assigned IVG #x */
-#define P1_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #1 assigned IVG #x */
-#define P2_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #2 assigned IVG #x */
-#define P3_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #3 assigned IVG #x */
-#define P4_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #4 assigned IVG #x */
-#define P5_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #5 assigned IVG #x */
-#define P6_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #6 assigned IVG #x */
-#define P7_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #7 assigned IVG #x */
+#define P0_IVG(x) (((x)-_MF7)&_MF15) /* Peripheral #0 assigned IVG #x */
+#define P1_IVG(x) (((x)-_MF7)&_MF15) << 0x4 /* Peripheral #1 assigned IVG #x */
+#define P2_IVG(x) (((x)-_MF7)&_MF15) << 0x8 /* Peripheral #2 assigned IVG #x */
+#define P3_IVG(x) (((x)-_MF7)&_MF15) << 0xC /* Peripheral #3 assigned IVG #x */
+#define P4_IVG(x) (((x)-_MF7)&_MF15) << 0x10 /* Peripheral #4 assigned IVG #x */
+#define P5_IVG(x) (((x)-_MF7)&_MF15) << 0x14 /* Peripheral #5 assigned IVG #x */
+#define P6_IVG(x) (((x)-_MF7)&_MF15) << 0x18 /* Peripheral #6 assigned IVG #x */
+#define P7_IVG(x) (((x)-_MF7)&_MF15) << 0x1C /* Peripheral #7 assigned IVG #x */
/* SIC_IAR1 Macros */
-#define P8_IVG(x) (((x)-7)&0xF) /* Peripheral #8 assigned IVG #x */
-#define P9_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #9 assigned IVG #x */
-#define P10_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #10 assigned IVG #x */
-#define P11_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #11 assigned IVG #x */
-#define P12_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #12 assigned IVG #x */
-#define P13_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #13 assigned IVG #x */
-#define P14_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #14 assigned IVG #x */
-#define P15_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #15 assigned IVG #x */
+#define P8_IVG(x) (((x)-_MF7)&_MF15) /* Peripheral #8 assigned IVG #x */
+#define P9_IVG(x) (((x)-_MF7)&_MF15) << 0x4 /* Peripheral #9 assigned IVG #x */
+#define P10_IVG(x) (((x)-_MF7)&_MF15) << 0x8 /* Peripheral #10 assigned IVG #x */
+#define P11_IVG(x) (((x)-_MF7)&_MF15) << 0xC /* Peripheral #11 assigned IVG #x */
+#define P12_IVG(x) (((x)-_MF7)&_MF15) << 0x10 /* Peripheral #12 assigned IVG #x */
+#define P13_IVG(x) (((x)-_MF7)&_MF15) << 0x14 /* Peripheral #13 assigned IVG #x */
+#define P14_IVG(x) (((x)-_MF7)&_MF15) << 0x18 /* Peripheral #14 assigned IVG #x */
+#define P15_IVG(x) (((x)-_MF7)&_MF15) << 0x1C /* Peripheral #15 assigned IVG #x */
/* SIC_IAR2 Macros */
-#define P16_IVG(x) (((x)-7)&0xF) /* Peripheral #16 assigned IVG #x */
-#define P17_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #17 assigned IVG #x */
-#define P18_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #18 assigned IVG #x */
-#define P19_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #19 assigned IVG #x */
-#define P20_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #20 assigned IVG #x */
-#define P21_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #21 assigned IVG #x */
-#define P22_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #22 assigned IVG #x */
-#define P23_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #23 assigned IVG #x */
+#define P16_IVG(x) (((x)-_MF7)&_MF15) /* Peripheral #16 assigned IVG #x */
+#define P17_IVG(x) (((x)-_MF7)&_MF15) << 0x4 /* Peripheral #17 assigned IVG #x */
+#define P18_IVG(x) (((x)-_MF7)&_MF15) << 0x8 /* Peripheral #18 assigned IVG #x */
+#define P19_IVG(x) (((x)-_MF7)&_MF15) << 0xC /* Peripheral #19 assigned IVG #x */
+#define P20_IVG(x) (((x)-_MF7)&_MF15) << 0x10 /* Peripheral #20 assigned IVG #x */
+#define P21_IVG(x) (((x)-_MF7)&_MF15) << 0x14 /* Peripheral #21 assigned IVG #x */
+#define P22_IVG(x) (((x)-_MF7)&_MF15) << 0x18 /* Peripheral #22 assigned IVG #x */
+#define P23_IVG(x) (((x)-_MF7)&_MF15) << 0x1C /* Peripheral #23 assigned IVG #x */
/* SIC_IAR3 Macros */
-#define P24_IVG(x) (((x)-7)&0xF) /* Peripheral #24 assigned IVG #x */
-#define P25_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #25 assigned IVG #x */
-#define P26_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #26 assigned IVG #x */
-#define P27_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #27 assigned IVG #x */
-#define P28_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #28 assigned IVG #x */
-#define P29_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #29 assigned IVG #x */
-#define P30_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #30 assigned IVG #x */
-#define P31_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #31 assigned IVG #x */
+#define P24_IVG(x) (((x)-_MF7)&_MF15) /* Peripheral #24 assigned IVG #x */
+#define P25_IVG(x) (((x)-_MF7)&_MF15) << 0x4 /* Peripheral #25 assigned IVG #x */
+#define P26_IVG(x) (((x)-_MF7)&_MF15) << 0x8 /* Peripheral #26 assigned IVG #x */
+#define P27_IVG(x) (((x)-_MF7)&_MF15) << 0xC /* Peripheral #27 assigned IVG #x */
+#define P28_IVG(x) (((x)-_MF7)&_MF15) << 0x10 /* Peripheral #28 assigned IVG #x */
+#define P29_IVG(x) (((x)-_MF7)&_MF15) << 0x14 /* Peripheral #29 assigned IVG #x */
+#define P30_IVG(x) (((x)-_MF7)&_MF15) << 0x18 /* Peripheral #30 assigned IVG #x */
+#define P31_IVG(x) (((x)-_MF7)&_MF15) << 0x1C /* Peripheral #31 assigned IVG #x */
/* SIC_IAR4 Macros */
-#define P32_IVG(x) (((x)-7)&0xF) /* Peripheral #32 assigned IVG #x */
-#define P33_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #33 assigned IVG #x */
-#define P34_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #34 assigned IVG #x */
-#define P35_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #35 assigned IVG #x */
-#define P36_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #36 assigned IVG #x */
-#define P37_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #37 assigned IVG #x */
-#define P38_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #38 assigned IVG #x */
-#define P39_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #39 assigned IVG #x */
+#define P32_IVG(x) (((x)-_MF7)&_MF15) /* Peripheral #32 assigned IVG #x */
+#define P33_IVG(x) (((x)-_MF7)&_MF15) << 0x4 /* Peripheral #33 assigned IVG #x */
+#define P34_IVG(x) (((x)-_MF7)&_MF15) << 0x8 /* Peripheral #34 assigned IVG #x */
+#define P35_IVG(x) (((x)-_MF7)&_MF15) << 0xC /* Peripheral #35 assigned IVG #x */
+#define P36_IVG(x) (((x)-_MF7)&_MF15) << 0x10 /* Peripheral #36 assigned IVG #x */
+#define P37_IVG(x) (((x)-_MF7)&_MF15) << 0x14 /* Peripheral #37 assigned IVG #x */
+#define P38_IVG(x) (((x)-_MF7)&_MF15) << 0x18 /* Peripheral #38 assigned IVG #x */
+#define P39_IVG(x) (((x)-_MF7)&_MF15) << 0x1C /* Peripheral #39 assigned IVG #x */
/* SIC_IAR5 Macros */
-#define P40_IVG(x) (((x)-7)&0xF) /* Peripheral #40 assigned IVG #x */
-#define P41_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #41 assigned IVG #x */
-#define P42_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #42 assigned IVG #x */
-#define P43_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #43 assigned IVG #x */
-#define P44_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #44 assigned IVG #x */
-#define P45_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #45 assigned IVG #x */
-#define P46_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #46 assigned IVG #x */
-#define P47_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #47 assigned IVG #x */
+#define P40_IVG(x) (((x)-_MF7)&_MF15) /* Peripheral #40 assigned IVG #x */
+#define P41_IVG(x) (((x)-_MF7)&_MF15) << 0x4 /* Peripheral #41 assigned IVG #x */
+#define P42_IVG(x) (((x)-_MF7)&_MF15) << 0x8 /* Peripheral #42 assigned IVG #x */
+#define P43_IVG(x) (((x)-_MF7)&_MF15) << 0xC /* Peripheral #43 assigned IVG #x */
+#define P44_IVG(x) (((x)-_MF7)&_MF15) << 0x10 /* Peripheral #44 assigned IVG #x */
+#define P45_IVG(x) (((x)-_MF7)&_MF15) << 0x14 /* Peripheral #45 assigned IVG #x */
+#define P46_IVG(x) (((x)-_MF7)&_MF15) << 0x18 /* Peripheral #46 assigned IVG #x */
+#define P47_IVG(x) (((x)-_MF7)&_MF15) << 0x1C /* Peripheral #47 assigned IVG #x */
/* SIC_IAR6 Macros */
-#define P48_IVG(x) (((x)-7)&0xF) /* Peripheral #48 assigned IVG #x */
-#define P49_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #49 assigned IVG #x */
-#define P50_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #50 assigned IVG #x */
-#define P51_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #51 assigned IVG #x */
-#define P52_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #52 assigned IVG #x */
-#define P53_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #53 assigned IVG #x */
-#define P54_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #54 assigned IVG #x */
-#define P55_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #55 assigned IVG #x */
+#define P48_IVG(x) (((x)-_MF7)&_MF15) /* Peripheral #48 assigned IVG #x */
+#define P49_IVG(x) (((x)-_MF7)&_MF15) << 0x4 /* Peripheral #49 assigned IVG #x */
+#define P50_IVG(x) (((x)-_MF7)&_MF15) << 0x8 /* Peripheral #50 assigned IVG #x */
+#define P51_IVG(x) (((x)-_MF7)&_MF15) << 0xC /* Peripheral #51 assigned IVG #x */
+#define P52_IVG(x) (((x)-_MF7)&_MF15) << 0x10 /* Peripheral #52 assigned IVG #x */
+#define P53_IVG(x) (((x)-_MF7)&_MF15) << 0x14 /* Peripheral #53 assigned IVG #x */
+#define P54_IVG(x) (((x)-_MF7)&_MF15) << 0x18 /* Peripheral #54 assigned IVG #x */
+#define P55_IVG(x) (((x)-_MF7)&_MF15) << 0x1C /* Peripheral #55 assigned IVG #x */
/* SIC_IARx Macros */
+#ifdef _MISRA_RULES
+#define PX_IVG_CLR(x) (0xFFFFFFFFu ^ (0xFu << (((x)%8)*4))) /* Clear IVG Select for Peripheral #x */
+/* Usage: *pSIC_IAR1 &= PX_IVG_CLR(11); // Clears IVG Level of Peripheral #11 */
+#define PX_IVG(x,y) ((((y)-7u)&0xFu) << (((x)%8)*4)) /* Set IVG Select to #y for Peripheral #x */
+/* Usage: *pSIC_IAR1 |= PX_IVG(11, 8); // Sets Peripheral #11 to IVG8 */
+#else
#define PX_IVG_CLR(x) (0xFFFFFFFF ^ (0xF << (((x)%8)*4))) /* Clear IVG Select for Peripheral #x */
/* Usage: *pSIC_IAR1 &= PX_IVG_CLR(11); // Clears IVG Level of Peripheral #11 */
-
#define PX_IVG(x,y) ((((y)-7)&0xF) << (((x)%8)*4)) /* Set IVG Select to #y for Peripheral #x */
/* Usage: *pSIC_IAR1 |= PX_IVG(11, 8); // Sets Peripheral #11 to IVG8 */
+#endif /* _MISRA_RULES */
/* SIC_IMASKx Masks */
#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
+#ifdef _MISRA_RULES
+#define SIC_MASK(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
+#define SIC_UNMASK(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Unmask Peripheral #x interrupt */
+#else
#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
+#endif /* _MISRA_RULES */
/* SIC_IWRx Masks */
#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
+#ifdef _MISRA_RULES
+#define IWR_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
+#define IWR_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Wakeup Disable Peripheral #x */
+#else
#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
+#endif /* _MISRA_RULES */
/* ********* WATCHDOG TIMER MASKS ******************** */
/* Watchdog Timer WDOG_CTL Register Masks */
+#ifdef _MISRA_RULES
+#define WDEV(x) (((x)<<1) & 0x0006u) /* event generated on roll over */
+#else
#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
+#endif /* _MISRA_RULES */
#define WDEV_RESET 0x0000 /* generate reset event on roll over */
#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
/* ** Must be set after power-up for proper operation of RTC */
/* RTC_ALARM Macro z=day y=hr x=min w=sec */
+#ifdef _MISRA_RULES
+#define SET_ALARM(z,y,x,w) ((((z)&0x7FFFu)<<0x11)|(((y)&0x1Fu)<<0xC)|(((x)&0x3Fu)<<0x6)|((w)&0x3Fu))
+#else
#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
+#endif /* _MISRA_RULES */
/* Deprecated RTC_STAT and RTC_ALARM Masks */
#define RTC_SEC RTSEC /* Real-Time Clock Seconds */
/* ***************************** UART CONTROLLER MASKS ********************** */
/* UARTx_LCR Register */
+#ifdef _MISRA_RULES
+#define WLS(x) (((x)-5u) & 0x03u) /* Word Length Select */
+#else
#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
+#endif /* _MISRA_RULES */
#define STB 0x04 /* Stop Bits */
#define PEN 0x08 /* Parity Enable */
#define EPS 0x10 /* Even Parity Select */
#define ERBFI_P 0x00
/* UARTx_IIR Register */
+#ifdef _MISRA_RULES
+#define STATUS(x) (((x) << 1) & 0x06u)
+#else
#define STATUS(x) (((x) << 1) & 0x06)
+#endif /* _MISRA_RULES */
#define NINT 0x01
#define STATUS_P1 0x02
#define STATUS_P0 0x01
#define TALAW DTYPE_ALAW /* Compand Using A-Law */
/* SPORTx_TCR2 Masks */
+#ifdef _MISRA_RULES
+#define SLEN(x) ((x)&0x1Fu) /* SPORT TX Word Length (2 - 31) */
+#else
#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
+#endif /* _MISRA_RULES */
#define TXSE 0x0100 /*TX Secondary Enable */
#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
#define TRFST 0x0400 /*TX Right-First Data Order */
#define RALAW DTYPE_ALAW /* Compand Using A-Law */
/* SPORTx_RCR2 Masks */
+#ifdef _MISRA_RULES
+#define SLEN(x) ((x)&0x1Fu) /* SPORT RX Word Length (2 - 31) */
+#else
#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
+#endif /* _MISRA_RULES */
#define RXSE 0x0100 /*RX Secondary Enable */
#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
#define RRFST 0x0400 /*Right-First Data Order */
#define WSIZE 0x0000F000 /*Multichannel Window Size Field */
#define WOFF 0x000003FF /*Multichannel Window Offset Field */
/* SPORTx_MCMC1 Macros */
+#ifdef _MISRA_RULES
+#define SET_WOFF(x) ((x) & 0x3FFu) /* Multichannel Window Offset Field */
+/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
+#define SET_WSIZE(x) (((((x)>>0x3)-1u)&0xFu) << 0xC) /* Multichannel Window Size = (x/8)-1 */
+#else
#define SET_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
#define SET_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
+#endif /* _MISRA_RULES */
+
/*SPORTx_MCMC2 Masks */
#define MCCRM 0x0003 /*Multichannel Clock Recovery Mode */
#define DLEN_14 0x2800 /* Data Length = 14 Bits */
#define DLEN_15 0x3000 /* Data Length = 15 Bits */
#define DLEN_16 0x3800 /* Data Length = 16 Bits */
+#ifdef _MISRA_RULES
+#define DLEN(x) ((((x)-9u) & 0x07u) << 11) /* PPI Data Length (only works for x=10-->x=16) */
+#else
#define DLEN(x) ((((x)-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
+#endif /* _MISRA_RULES */
#define POL 0xC000 /* PPI Signal Polarities */
#define POLC 0x4000 /* PPI Clock Polarity */
#define POLS 0x8000 /* PPI Frame Sync Polarity */
#define CLK_SEL 0x0080
#define TOGGLE_HI 0x0100
#define EMU_RUN 0x0200
+#ifdef _MISRA_RULES
+#define ERR_TYP(x) (((x) & 0x03u) << 14)
+#else
#define ERR_TYP(x) (((x) & 0x03) << 14)
+#endif /* _MISRA_RULES */
#define TMODE_P0 0x00
#define TMODE_P1 0x01
#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
/* EBIU_SDBCTL Masks */
-#define EBE 0x00000001 /* Enable SDRAM external bank */
-#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */
-#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */
-#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */
-#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */
-#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
-#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
-#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
+#define EBE 0x0001 /* Enable SDRAM external bank */
+#define EBSZ_16 0x0000 /* SDRAM external bank size = 16MB */
+#define EBSZ_32 0x0002 /* SDRAM external bank size = 32MB */
+#define EBSZ_64 0x0004 /* SDRAM external bank size = 64MB */
+#define EBSZ_128 0x0006 /* SDRAM external bank size = 128MB */
+#define EBSZ 0x0006 /* SDRAM external bank size */
+#define EBCAW_8 0x0000 /* SDRAM external bank column address width = 8 bits */
+#define EBCAW_9 0x0010 /* SDRAM external bank column address width = 9 bits */
+#define EBCAW_10 0x0020 /* SDRAM external bank column address width = 9 bits */
+#define EBCAW_11 0x0030 /* SDRAM external bank column address width = 9 bits */
/* EBIU_SDSTAT Masks */
#define SDCI 0x00000001 /* SDRAM controller is idle */
/* ******************** TWO-WIRE INTERFACE (TWIx) MASKS ***********************/
/* TWIx_CLKDIV Macros (Use: *pTWIx_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
+#ifdef _MISRA_RULES
+#define CLKLOW(x) ((x) & 0xFFu) /* Periods Clock Is Held Low */
+#define CLKHI(y) (((y)&0xFFu)<<0x8) /* Periods Before New Clock Low */
+#else
#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
+#endif /* _MISRA_RULES */
/* TWIx_PRESCALE Masks */
#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
#define WAKEUP 0x00004000lu
#define LMECH 0x00008000lu
+#ifdef _MISRA_RULES
+#define SET_MSB(x) (((x)&0xFu) << 0x9)
+#else
#define SET_MSB(x) (((x)&0xF) << 0x9)
+#endif /* _MISRA_RULES */
/* MXVR_PLL_CTL_0 Masks */
#define MPLLCNTEN 0x00008000lu
#define MPLLCNT 0xFFFF0000lu
+#ifdef _MISRA_RULES
+#define SET_MPLLCNT(x) (((x)&0xFFFFu) << 0x10)
+#else
#define SET_MPLLCNT(x) (((x)&0xFFFF) << 0x10)
+#endif /* _MISRA_RULES */
/* MXVR_PLL_CTL_2 Masks */
#define MSHAPERSEL 0x00000007lu
#define MCPSEL 0x000000E0lu
+#ifdef _MISRA_RULES
+#define SET_MSHAPERSEL(x) ( (x) & 0x0007u )
+#define SET_MCPSEL(x) ( ( (x) & 0x0007u ) << 0x5 )
+#else
#define SET_MSHAPERSEL(x) ( (x) & 0x0007 )
#define SET_MCPSEL(x) ( ( (x) & 0x0007 ) << 0x5 )
+#endif /* _MISRA_RULES */
/* MXVR_INT_STAT_0 Masks */
#define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
#endif /* _DEF_BF539_H */
/*
** defBF542.h
**
-** Copyright (C) 2008 Analog Devices, Inc.
+** Copyright (C) 2008, 2009 Analog Devices, Inc.
**
************************************************************************************
**
/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
#include <defBF54x_base.h>
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"some macros violate rule 19.4")
+#pragma diag(suppress:misra_rule_19_7:"Allow function-like macros ")
+#endif /* _MISRA_RULES */
+
/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
/* ATAPI Registers */
#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
#define KPAD_COLEN 0xe000 /* Column Enable Width */
+#ifdef _MISRA_RULES
+#define SET_KPAD_ROWEN(x) (((x)&0x7u)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
+#define SET_KPAD_COLEN(x) (((x)&0x7u)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
+#else
#define SET_KPAD_ROWEN(x) (((x)&0x7)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
#define SET_KPAD_COLEN(x) (((x)&0x7)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
+#endif /* _MISRA_RULES */
/* Bit masks for KPAD_PRESCALE */
#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
+#ifdef _MISRA_RULES
+#define SET_KPAD_PRESCALE(x) ((x)&0x3Fu) /* KPAD_PRESCALE_VAL (Key Prescale) Key Prescale Value (5:0) */
+#else
#define SET_KPAD_PRESCALE(x) ((x)&0x3F) /* KPAD_PRESCALE_VAL (Key Prescale) Key Prescale Value (5:0) */
+#endif /* _MISRA_RULES */
/* Bit masks for KPAD_MSEL */
#define KPAD_ROW 0xff /* Rows Pressed */
#define KPAD_COL 0xff00 /* Columns Pressed */
+#ifdef _MISRA_RULES
+#define SET_KPAD_DBON_SCALE(x) ((x)&0xFFu) /* DBON_SCALE (Debounce Scale) Debounce Delay Multiplier Select [7:0] */
+#define SET_KPAD_COLDRV_SCALE(x) (((x)&0xFFu)<<8) /* COLDRV_SCALE (Column Driver Scale) Column Driver Period Multiplier Select [15:8] */
+#else
#define SET_KPAD_DBON_SCALE(x) ((x)&0xFF) /* DBON_SCALE (Debounce Scale) Debounce Delay Multiplier Select [7:0] */
#define SET_KPAD_COLDRV_SCALE(x) (((x)&0xFF)<<8) /* COLDRV_SCALE (Column Driver Scale) Column Driver Period Multiplier Select [15:8] */
+#endif /* _MISRA_RULES */
/* Bit masks for KPAD_STAT */
/* MULTI BIT MACRO ENUMERATIONS */
/* ******************************************* */
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
#endif /* _DEF_BF542_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** defBF542M.h
+**
+** Copyright (C) 2009 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This file just maps directly onto the def file for BF542, unless
+** anything is required to change for the M derivative.
+**
+**/
+
+#include <defBF542.h>
/*
** defBF544.h
**
-** Copyright (C) 2008 Analog Devices, Inc.
+** Copyright (C) 2008, 2009 Analog Devices, Inc.
**
************************************************************************************
**
#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
-#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
+#define CAN1_UCRC 0xffc032c8 /* Universal Counter Reload/Capture Register */
#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
/* CAN Controller 1 Mailbox Acceptance Registers */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** defBF544M.h
+**
+** Copyright (C) 2009 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This file just maps directly onto the def file for BF544, unless
+** anything is required to change for the M derivative.
+**
+**/
+
+#include <defBF544.h>
/*
** defBF547.h
**
-** Copyright (C) 2008 Analog Devices, Inc.
+** Copyright (C) 2008, 2009 Analog Devices, Inc.
**
************************************************************************************
**
/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
#include <defBF54x_base.h>
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"some macros violate rule 19.4 ")
+#pragma diag(suppress:misra_rule_19_7:"Allow function-like macros ")
+#endif /* _MISRA_RULES */
+
/* The following are the #defines needed by ADSP-BF547 that are not in the common header */
/* Timer Registers */
#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
#define KPAD_COLEN 0xe000 /* Column Enable Width */
+#ifdef _MISRA_RULES
+#define SET_KPAD_ROWEN(x) (((x)&0x7u)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
+#define SET_KPAD_COLEN(x) (((x)&0x7u)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
+#else
#define SET_KPAD_ROWEN(x) (((x)&0x7)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
#define SET_KPAD_COLEN(x) (((x)&0x7)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
+#endif /* _MISRA_RULES */
/* Bit masks for KPAD_PRESCALE */
#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
+#ifdef _MISRA_RULES
+#define SET_KPAD_PRESCALE(x) ((x)&0x3Fu) /* KPAD_PRESCALE_VAL (Key Prescale). Key Prescale Value (5:0) */
+#else
#define SET_KPAD_PRESCALE(x) ((x)&0x3F) /* KPAD_PRESCALE_VAL (Key Prescale). Key Prescale Value (5:0) */
+#endif /* _MISRA_RULES */
/* Bit masks for KPAD_MSEL */
#define DBON_SCALE 0xff /* Debounce Scale Value */
#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
+#ifdef _MISRA_RULES
+#define SET_KPAD_DBON_SCALE(x) ((x)&0xFFu) /* DBON_SCALE (Debounce Scale). Debounce Delay Multiplier Select [7:0] */
+#define SET_KPAD_COLDRV_SCALE(x) (((x)&0xFFu)<<8) /* COLDRV_SCALE (Column Driver Scale). Column Driver Period Multiplier Select [15:8] */
+#else
#define SET_KPAD_DBON_SCALE(x) ((x)&0xFF) /* DBON_SCALE (Debounce Scale). Debounce Delay Multiplier Select [7:0] */
#define SET_KPAD_COLDRV_SCALE(x) (((x)&0xFF)<<8) /* COLDRV_SCALE (Column Driver Scale). Column Driver Period Multiplier Select [15:8] */
+#endif /* _MISRA_RULES */
/* Bit masks for KPAD_ROWCOL */
/* MULTI BIT MACRO ENUMERATIONS */
/* ******************************************* */
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
#endif /* _DEF_BF547_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** defBF547M.h
+**
+** Copyright (C) 2009 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This file just maps directly onto the def file for BF547, unless
+** anything is required to change for the M derivative.
+**
+**/
+
+#include <defBF547.h>
/*
** defBF548.h
**
-** Copyright (C) 2008 Analog Devices, Inc.
+** Copyright (C) 2008, 2009 Analog Devices, Inc.
**
************************************************************************************
**
/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
#include <defBF54x_base.h>
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"some macros violate rule 19.4")
+#pragma diag(suppress:misra_rule_19_7:"Allow function-like macros ")
+#endif /* _MISRA_RULES */
+
/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
/* Timer Registers */
#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
-#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
+#define CAN1_UCRC 0xffc032c8 /* Universal Counter Reload/Capture Register */
#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
/* CAN Controller 1 Mailbox Acceptance Registers */
#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
#define KPAD_COLEN 0xe000 /* Column Enable Width */
+#ifdef _MISRA_RULES
+#define SET_KPAD_ROWEN(x) (((x)&0x7u)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
+#define SET_KPAD_COLEN(x) (((x)&0x7u)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
+#else
#define SET_KPAD_ROWEN(x) (((x)&0x7)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
#define SET_KPAD_COLEN(x) (((x)&0x7)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
+#endif /* _MISRA_RULES */
/* Bit masks for KPAD_PRESCALE */
#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
+#ifdef _MISRA_RULES
+#define SET_KPAD_PRESCALE(x) ((x)&0x3Fu) /* KPAD_PRESCALE_VAL (Key Prescale). Key Prescale Value (5:0) */
+#else
#define SET_KPAD_PRESCALE(x) ((x)&0x3F) /* KPAD_PRESCALE_VAL (Key Prescale). Key Prescale Value (5:0) */
+#endif /* _MISRA_RULES */
/* Bit masks for KPAD_MSEL */
#define DBON_SCALE 0xff /* Debounce Scale Value */
#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
+#ifdef _MISRA_RULES
+#define SET_KPAD_DBON_SCALE(x) ((x)&0xFFu) /* DBON_SCALE (Debounce Scale). Debounce Delay Multiplier Select [7:0] */
+#define SET_KPAD_COLDRV_SCALE(x) (((x)&0xFFu)<<8) /* COLDRV_SCALE (Column Driver Scale). Column Driver Period Multiplier Select [15:8] */
+#else
#define SET_KPAD_DBON_SCALE(x) ((x)&0xFF) /* DBON_SCALE (Debounce Scale). Debounce Delay Multiplier Select [7:0] */
#define SET_KPAD_COLDRV_SCALE(x) (((x)&0xFF)<<8) /* COLDRV_SCALE (Column Driver Scale). Column Driver Period Multiplier Select [15:8] */
+#endif /* _MISRA_RULES */
/* Bit masks for KPAD_ROWCOL */
/* MULTI BIT MACRO ENUMERATIONS */
/* ******************************************* */
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
#endif /* _DEF_BF548_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** defBF548M.h
+**
+** Copyright (C) 2009 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This file just maps directly onto the def file for BF548, unless
+** anything is required to change for the M derivative.
+**
+**/
+
+#include <defBF548.h>
/*
** defBF549.h
**
-** Copyright (C) 2008 Analog Devices, Inc.
+** Copyright (C) 2008, 2009 Analog Devices, Inc.
**
************************************************************************************
**
#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
-#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
+#define CAN1_UCRC 0xffc032c8 /* Universal Counter Reload/Capture Register */
#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
/* CAN Controller 1 Mailbox Acceptance Registers */
#define KPAD_COLEN 0xe000 /* Column Enable Width */
+#ifdef _MISRA_RULES
+#define SET_KPAD_ROWEN(x) (((x)&0x7u)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
+#define SET_KPAD_COLEN(x) (((x)&0x7u)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
+#else
#define SET_KPAD_ROWEN(x) (((x)&0x7)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
#define SET_KPAD_COLEN(x) (((x)&0x7)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
+#endif /* _MISRA_RULES */
/* Bit masks for KPAD_PRESCALE */
#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
+#ifdef _MISRA_RULES
+#define SET_KPAD_PRESCALE(x) ((x)&0x3Fu) /* KPAD_PRESCALE_VAL (Key Prescale). Key Prescale Value (5:0) */
+#else
#define SET_KPAD_PRESCALE(x) ((x)&0x3F) /* KPAD_PRESCALE_VAL (Key Prescale). Key Prescale Value (5:0) */
+#endif /* MISRA_RULES */
/* Bit masks for KPAD_MSEL */
#define DBON_SCALE 0xff /* Debounce Scale Value */
#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
+#ifdef _MISRA_RULES
+#define SET_KPAD_DBON_SCALE(x) ((x)&0xFFu) /* DBON_SCALE (Debounce Scale). Debounce Delay Multiplier Select [7:0] */
+#define SET_KPAD_COLDRV_SCALE(x) (((x)&0xFFu)<<8) /* COLDRV_SCALE (Column Driver Scale). Column Driver Period Multiplier Select [15:8] */
+#else
#define SET_KPAD_DBON_SCALE(x) ((x)&0xFF) /* DBON_SCALE (Debounce Scale). Debounce Delay Multiplier Select [7:0] */
#define SET_KPAD_COLDRV_SCALE(x) (((x)&0xFF)<<8) /* COLDRV_SCALE (Column Driver Scale). Column Driver Period Multiplier Select [15:8] */
+#endif /* _MISRA_RULES */
/* Bit masks for KPAD_ROWCOL */
/* MXVR_CONFIG Macros */
+#ifdef _MISRA_RULES
+#define SET_MSB(x) ( ( (x) & 0xFu ) << 9)
+#else
#define SET_MSB(x) ( ( (x) & 0xF ) << 9)
+#endif /* _MISRA_RULES */
/* MXVR_INT_STAT_1 Macros */
/* MXVR_CDRPLL_CTL Macros */
+#ifdef _MISRA_RULES
+#define SET_CDRSHPSEL(x) ( ( (x) & 0x3Fu ) << 16)
+#else
#define SET_CDRSHPSEL(x) ( ( (x) & 0x3F ) << 16)
+#endif /* _MISRA_RULES */
/* MXVR_FMPLL_CTL Macros */
+#ifdef _MISRA_RULES
+#define SET_CDRCPSEL(x) ( ( (x) & 0xFFu ) << 24)
+#define SET_FMCPSEL(x) ( ( (x) & 0xFFu ) << 24)
+#else
#define SET_CDRCPSEL(x) ( ( (x) & 0xFF ) << 24)
#define SET_FMCPSEL(x) ( ( (x) & 0xFF ) << 24)
+#endif /* _MISRA_RULES */
#ifdef _MISRA_RULES
#pragma diag(pop)
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** defBF549M.h
+**
+** Copyright (C) 2009 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This file just maps directly onto the def file for BF549, unless
+** anything is required to change for the M derivative.
+**
+**/
+
+#include <defBF549.h>
/*
** defBF54x_base.h
**
-** Copyright (C) 2008 Analog Devices, Inc.
+** Copyright (C) 2008, 2009 Analog Devices, Inc.
**
************************************************************************************
**
#define CAN0_EWR 0xffc02ab0 /* CAN Controller 0 Programmable Warning Level Register */
#define CAN0_ESR 0xffc02ab4 /* CAN Controller 0 Error Status Register */
#define CAN0_UCCNT 0xffc02ac4 /* CAN Controller 0 Universal Counter Register */
-#define CAN0_UCRC 0xffc02ac8 /* CAN Controller 0 Universal Counter Force Reload Register */
+#define CAN0_UCRC 0xffc02ac8 /* Universal Counter Reload/Capture Register */
#define CAN0_UCCNF 0xffc02acc /* CAN Controller 0 Universal Counter Configuration Register */
/* CAN Controller 0 Acceptance Registers */
#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
+#define AMBEN_B0_B1_B2_B3 0x0008 /* Enable Async Memory Banks 0, 1, 2 and 3 */
+#define AMBEN_ALL 0x0008 /* Enable All Async Memory Banks */
/* Bit masks for EBIU_AMBCTL0 */
#define B1WAT 0xf0000000 /* Bank 1 write access time */
/* EBIU_AMBCTL0 Macros */
+#ifdef _MISRA_RULES
+#define SET_B1WAT(x) (((x)&0xFu) << 28) /* B1 Write Access Time = x cycles */
+#define SET_B1RAT(x) (((x)&0xFu) << 24) /* B1 Read Access Time = x cycles */
+#define SET_B1HT(x) (((x)&0x3u) << 22) /* B1 Hold Time (~Read/Write to ~AOE) = x cycles */
+#define SET_B1ST(x) (((x)&0x3u) << 20) /* B1 Setup Time (AOE to Read/Write) = x cycle */
+#define SET_B1TT(x) (((x)&0x3u) << 18) /* B1 Transition Time (Read to Write) = x cycles */
+
+#define SET_B0WAT(x) (((x)&0xFu) << 12) /* B0 Write Access Time = x cycles */
+#define SET_B0RAT(x) (((x)&0xFu) << 8) /* B0 Read Access Time = x cycles */
+#define SET_B0HT(x) (((x)&0x3u) << 6) /* B0 Hold Time (~Read/Write to ~AOE) = x cycles */
+#define SET_B0ST(x) (((x)&0x3u) << 4) /* B0 Setup Time (AOE to Read/Write) = x cycle */
+#define SET_B0TT(x) (((x)&0x3u) << 2) /* B0 Transition Time (Read to Write) = x cycles */
+#else
#define SET_B1WAT(x) (((x)&0xF) << 28) /* B1 Write Access Time = x cycles */
#define SET_B1RAT(x) (((x)&0xF) << 24) /* B1 Read Access Time = x cycles */
#define SET_B1HT(x) (((x)&0x3) << 22) /* B1 Hold Time (~Read/Write to ~AOE) = x cycles */
-#define SET_B1ST[x) (((x)&0x3) << 20) /* B1 Setup Time (AOE to Read/Write) = x cycle */
+#define SET_B1ST(x) (((x)&0x3) << 20) /* B1 Setup Time (AOE to Read/Write) = x cycle */
#define SET_B1TT(x) (((x)&0x3) << 18) /* B1 Transition Time (Read to Write) = x cycles */
#define SET_B0WAT(x) (((x)&0xF) << 12) /* B0 Write Access Time = x cycles */
#define SET_B0RAT(x) (((x)&0xF) << 8) /* B0 Read Access Time = x cycles */
#define SET_B0HT(x) (((x)&0x3) << 6) /* B0 Hold Time (~Read/Write to ~AOE) = x cycles */
-#define SET_B0ST[x) (((x)&0x3) << 4) /* B0 Setup Time (AOE to Read/Write) = x cycle */
+#define SET_B0ST(x) (((x)&0x3) << 4) /* B0 Setup Time (AOE to Read/Write) = x cycle */
#define SET_B0TT(x) (((x)&0x3) << 2) /* B0 Transition Time (Read to Write) = x cycles */
+#endif /* _MISRA_RULES */
+
/* Bit masks for EBIU_AMBCTL1 */
#define B3WAT 0xf0000000 /* Bank 3 write access time */
/* EBIU_AMBCTL1 Macros */
+#ifdef _MISRA_RULES
+#define SET_B3WAT(x) (((x)&0xFu) << 28) /* B3 Write Access Time = x cycles */
+#define SET_B3RAT(x) (((x)&0xFu) << 24) /* B3 Read Access Time = x cycles */
+#define SET_B3HT(x) (((x)&0x3u) << 22) /* B3 Hold Time (~Read/Write to ~AOE) = x cycles */
+#define SET_B3ST(x) (((x)&0x3u) << 20) /* B3 Setup Time (AOE to Read/Write) = x cycle */
+#define SET_B3TT(x) (((x)&0x3u) << 18) /* B3 Transition Time (Read to Write) = x cycles */
+
+#define SET_B2WAT(x) (((x)&0xFu) << 12) /* B2 Write Access Time = x cycles */
+#define SET_B2RAT(x) (((x)&0xFu) << 8) /* B2 Read Access Time = x cycles */
+#define SET_B2HT(x) (((x)&0x3u) << 6) /* B2 Hold Time (~Read/Write to ~AOE) = x cycles */
+#define SET_B2ST(x) (((x)&0x3u) << 4) /* B2 Setup Time (AOE to Read/Write) = x cycle */
+#define SET_B2TT(x) (((x)&0x3u) << 2) /* B2 Transition Time (Read to Write) = x cycles */
+#else
#define SET_B3WAT(x) (((x)&0xF) << 28) /* B3 Write Access Time = x cycles */
#define SET_B3RAT(x) (((x)&0xF) << 24) /* B3 Read Access Time = x cycles */
#define SET_B3HT(x) (((x)&0x3) << 22) /* B3 Hold Time (~Read/Write to ~AOE) = x cycles */
-#define SET_B3ST[x) (((x)&0x3) << 20) /* B3 Setup Time (AOE to Read/Write) = x cycle */
+#define SET_B3ST(x) (((x)&0x3) << 20) /* B3 Setup Time (AOE to Read/Write) = x cycle */
#define SET_B3TT(x) (((x)&0x3) << 18) /* B3 Transition Time (Read to Write) = x cycles */
#define SET_B2WAT(x) (((x)&0xF) << 12) /* B2 Write Access Time = x cycles */
#define SET_B2RAT(x) (((x)&0xF) << 8) /* B2 Read Access Time = x cycles */
#define SET_B2HT(x) (((x)&0x3) << 6) /* B2 Hold Time (~Read/Write to ~AOE) = x cycles */
-#define SET_B2ST[x) (((x)&0x3) << 4) /* B2 Setup Time (AOE to Read/Write) = x cycle */
+#define SET_B2ST(x) (((x)&0x3) << 4) /* B2 Setup Time (AOE to Read/Write) = x cycle */
#define SET_B2TT(x) (((x)&0x3) << 2) /* B2 Transition Time (Read to Write) = x cycles */
+#endif /* _MISRA_RULES */
/* Bit masks for EBIU_MBSCTL */
#define BCLK4 0x00000006 /* Burst clock frequency: 11 - SCLK/4 */
/* Macros for EBIU_FCTL */
+#ifdef _MISRA_RULES
+#define SET_PGWS(x) (((x)&0x7u) << 0x3) /* PGWS[5:3] Page Wait States - 000 to 100 - 0 to 4 cycles */
+#else
#define SET_PGWS(x) (((x)&0x7) << 0x3) /* PGWS[5:3] Page Wait States - 000 to 100 - 0 to 4 cycles */
+#endif /* _MISRA_RULES */
/* Burst clock frequency: 00 - Reserved */
/* Bit masks for EBIU_ARBSTAT */
#define TRC 0x3c000000 /* Active-to-active time */
/* Macros for EBIU_DDRCTL0 */
+#ifdef _MISRA_RULES
+#define SET_tRC(x) (((x)&0xFu) << 26) /* tRC (Active-to-Active)[29:26] - Number of clock cycles from an active command to next active command (Default: 0x2) */
+#define SET_tRAS(x) (((x)&0xFu) << 22) /* tRAS (Minimum Active-to-Precharge time) [3:0] - Number of clock cycles from an ACTIVE command until a PRE-CHARGE command is issued. To obtain this value, one should divide the minimum RAS to pre-charge delay of SDRAM by clock cycle time (Default: 0x6) */
+#define SET_tRP(x) (((x)&0xFu) << 18) /* tRP (Precharge-to-Active Command period)[3:0] - Number of clock cycles needed for DDR to recover from a precharge command and ready to accept next active command (Default: 0x3) */
+#define SET_tRFC(x) (((x)&0xFu) << 14) /* tRFC[3:0] AUTO-REFRESH Command Period[3:0] - Number of clock cycles needed for DDR to recover from a refresh to be ready for next active command (tRFC/Clock Period) (Default: 0xA) */
+#define SET_tREFI(x) ((x)&0x3FFFu) /* tREFI (Refresh Interval)[13:0] - Number of clock cycles from one refresh cycle to next refresh cycle. To obtain this value, divide the DDR refresh period (tREF) by total number of rows to be refreshed. Then divide the result by total time. (Default: 0x0411) */
+#else
#define SET_tRC(x) (((x)&0xF) << 26) /* tRC (Active-to-Active)[29:26] - Number of clock cycles from an active command to next active command (Default: 0x2) */
#define SET_tRAS(x) (((x)&0xF) << 22) /* tRAS (Minimum Active-to-Precharge time) [3:0] - Number of clock cycles from an ACTIVE command until a PRE-CHARGE command is issued. To obtain this value, one should divide the minimum RAS to pre-charge delay of SDRAM by clock cycle time (Default: 0x6) */
#define SET_tRP(x) (((x)&0xF) << 18) /* tRP (Precharge-to-Active Command period)[3:0] - Number of clock cycles needed for DDR to recover from a precharge command and ready to accept next active command (Default: 0x3) */
#define SET_tRFC(x) (((x)&0xF) << 14) /* tRFC[3:0] AUTO-REFRESH Command Period[3:0] - Number of clock cycles needed for DDR to recover from a refresh to be ready for next active command (tRFC/Clock Period) (Default: 0xA) */
#define SET_tREFI(x) ((x)&0x3FFF) /* tREFI (Refresh Interval)[13:0] - Number of clock cycles from one refresh cycle to next refresh cycle. To obtain this value, divide the DDR refresh period (tREF) by total number of rows to be refreshed. Then divide the result by total time. (Default: 0x0411) */
+#endif /* _MISRA_RULES */
/* Bit masks for EBIU_DDRCTL1 */
#define DDR_DEVSIZE_256 0x000C0000
/* Macros for EBIU_DDRCTL1 */
+#ifdef _MISRA_RULES
+#define SET_tWTR(x) (((x)&0xFu) << 28) /* tWTR (Write-to-Read Delay)[3:0] - The Write to read delay (last write data to the next read command) as specified by DDR Data sheet (Default: 0x0001) */
+#define SET_tWR(x) (((x)&0x3u) << 8) /* tWR Write Recovery Time[9:8] */
+#define SET_tMRD(x) (((x)&0xFu) << 4) /* tMRD Mode register set to active[7:4] */
+#define SET_tRCD(x) ((x)&0xFu) /* tRCD ACTIVE-to-READ/WRITE delay[3:0] */
+#else
#define SET_tWTR(x) (((x)&0xF) << 28) /* tWTR (Write-to-Read Delay)[3:0] - The Write to read delay (last write data to the next read command) as specified by DDR Data sheet (Default: 0x0001) */
#define SET_tWR(x) (((x)&0x3) << 8) /* tWR Write Recovery Time[9:8] */
#define SET_tMRD(x) (((x)&0xF) << 4) /* tMRD Mode register set to active[7:4] */
#define SET_tRCD(x) ((x)&0xF) /* tRCD ACTIVE-to-READ/WRITE delay[3:0] */
+#endif /* _MISRA_RULES */
/* Bit masks for EBIU_DDRCTL2 */
#define BURSTLENGTH 0x7 /* Burst length */
#define PASR 0x7 /* Partial array self-refresh */
/* Bit masks for EBIU_DDRQUE */
-#define DEB0_PFLEN 0x30 /* Pre fetch length for DEB0 accesses */
-#define DEB1_PFLEN 0x3 /* Pre fetch length for DEB1 accesses */
-#define DEB2_PFLEN 0xc /* Pre fetch length for DEB2 accesses */
+#define DEB0_PFLEN 0x3 /* Pre fetch length for DEB0 accesses */
+#define DEB1_PFLEN 0xc /* Pre fetch length for DEB1 accesses */
+#define DEB2_PFLEN 0x30 /* Pre fetch length for DEB2 accesses */
#define DEB_ARB_PRIORITY 0x700 /* Arbitration between DEB busses */
-#define DEB0_URGENT 0x4000 /* DEB0 Urgent */
+#define DEB0_URGENT 0x1000 /* DEB0 Urgent */
#define nDEB0_URGENT 0x0
-#define DEB1_URGENT 0x1000 /* DEB1 Urgent */
+#define DEB1_URGENT 0x2000 /* DEB1 Urgent */
#define nDEB1_URGENT 0x0
-#define DEB2_URGENT 0x2000 /* DEB2 Urgent */
+#define DEB2_URGENT 0x4000 /* DEB2 Urgent */
#define nDEB2_URGENT 0x0
/* Bit masks for EBIU_DDRQUE (DEB0_PFLEN) */
#define nSRREQ 0x0
#define SRACK 0x10 /* Self-refresh acknowledge */
#define nSRACK 0x0
-#define MDDRENABLE 0x20 /* Mobile DDR enable */
-#define nMDDRENABLE 0x0
/* Bit masks for EBIU_DDRBRC0 */
#define PREN 0x1 /* Prescaler Enable */
#define nPREN 0x0
-/* Bit masks for OTP_CONTROL */
-
-#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
-#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
-#define nFIEN 0x0
-#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
-#define nFTESTDEC 0x0
-#define FWRTEST 0x2000 /* OTP/Fuse Write Test */
-#define nFWRTEST 0x0
-#define FRDEN 0x4000 /* OTP/Fuse Read Enable */
-#define nFRDEN 0x0
-#define FWREN 0x8000 /* OTP/Fuse Write Enable */
-#define nFWREN 0x0
-
-/* Bit masks for OTP_BEN */
-
-#define FBEN 0xffff /* OTP/Fuse Byte Enable */
-
-/* Bit masks for OTP_STATUS */
-
-#define FCOMP 0x1 /* OTP/Fuse Access Complete */
-#define nFCOMP 0x0
-#define FERROR 0x2 /* OTP/Fuse Access Error */
-#define nFERROR 0x0
-#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
-#define nMMRGLOAD 0x0
-#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
-#define nMMRGLOCK 0x0
-#define FPGMEN 0x40 /* OTP/Fuse Program Enable */
-#define nFPGMEN 0x0
-
-/* Bit masks for OTP_TIMING */
-
-#define USECDIV 0xff /* Micro Second Divider */
-#define READACC 0x7f00 /* Read Access Time */
-#define CPUMPRL 0x38000 /* Charge Pump Release Time */
-#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */
-#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */
-#define PGMTIME 0xff000000 /* Program Time */
-
/* Bit masks for SECURE_SYSSWT */
#define EMUDABL 0x1 /* Emulation Disable. */
#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
/* PLL_DIV Macros */
+#ifdef _MISRA_RULES
+#define SET_SSEL(x) ((x)&0xFu) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
+#else
#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
+#endif /* _MISRA_RULES */
/* Bit masks for PLL_CTL */
#define nDF 0x0
/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
+#ifdef _MISRA_RULES
+#define SET_MSEL(x) (((x)&0x3Fu) << 9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
+#else
#define SET_MSEL(x) (((x)&0x3F) << 9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
+#endif /* _MISRA_RULES */
/* Bit masks for PLL_STAT */
#define MFD 0xf000 /* Multi channel Frame Delay */
#define FSDR 0x80 /* Frame Sync to Data Relationship */
#define nFSDR 0x0
-#define MCMEM 0x10 /* Multi channel Frame Mode Enable */
-#define nMCMEM 0x0
+#define MCMEN 0x10 /* Multi channel Frame Mode Enable */
+#define nMCMEN 0x0
#define MCDRXPE 0x8 /* Multi channel DMA Receive Packing */
#define nMCDRXPE 0x0
#define MCDTXPE 0x4 /* Multi channel DMA Transmit Packing */
#define nBDIE 0x0
#define MBDI 0x40 /* Mask Block Done Interrupt */
#define nMBDI 0x0
+#define SND 0x80 /* Source/Not Destination */
+#define nSND 0x0
#define DRQ 0x300 /* Handshake MDMA Request Type */
#define RBC 0x1000 /* Force Reload of BCOUNT */
#define nRBC 0x0
/* MULTI BIT MACRO ENUMERATIONS */
/* ******************************************* */
-/* BCODE bit field options (SYSCFG register) */
+/* SYSCR Masks */
+
+#define BMODE 0x000F /* Boot Mode. Mirror of BMODE Mode Pins */
+#define NOBOOT 0x0030 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
-#define BCODE_WAKEUP 0x0000 /* boot according to wake-up condition */
-#define BCODE_FULLBOOT 0x0010 /* always perform full boot */
-#define BCODE_QUICKBOOT 0x0020 /* always perform quick boot */
-#define BCODE_NOBOOT 0x0030 /* always perform full boot */
+
+#define BCODE 0x00F0
+#define BCODE_NORMAL 0x0000 /* normal boot, update PLL/VR, quickboot as by WURESET */
+#define BCODE_NOBOOT 0x0010 /* bypass boot, don't update PLL/VR */
+#define BCODE_QUICKBOOT 0x0020 /* quick boot, overrule WURESET, don't update PLL/VR */
+#define BCODE_ALLBOOT 0x0040 /* no quick boot, overrule WURESET, don't update PLL/VR */
+#define BCODE_FULLBOOT 0x0060 /* no quick boot, overrule WURESET, update PLL/VR */
+
+#define CDMAPRIO 0x0100 /* DMA1 gets higher priority than DMA0 to L1 memory */
+#define L2DMAPRIO 0x0200 /* DMA1 gets higher priority than DMA0 to L2 memory */
+
+#define WURESET 0x1000 /* wakeup event since last hardware reset */
+#define DFRESET 0x2000 /* recent reset was due to a double fault event */
+#define WDRESET 0x4000 /* recent reset was due to a watchdog event */
+#define SWRESET 0x8000 /* recent reset was issued by software */
/* CNT_COMMAND bit field options */
#define MUX15_2 0x80000000
#define MUX15_3 0xC0000000
+#ifdef _MISRA_RULES
+#define MUX(b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1,b0) \
+ ((((b15)&3u) << 30) | \
+ (((b14)&3u) << 28) | \
+ (((b13)&3u) << 26) | \
+ (((b12)&3u) << 24) | \
+ (((b11)&3u) << 22) | \
+ (((b10)&3u) << 20) | \
+ (((b9) &3u) << 18) | \
+ (((b8) &3u) << 16) | \
+ (((b7) &3u) << 14) | \
+ (((b6) &3u) << 12) | \
+ (((b5) &3u) << 10) | \
+ (((b4) &3u) << 8) | \
+ (((b3) &3u) << 6) | \
+ (((b2) &3u) << 4) | \
+ (((b1) &3u) << 2) | \
+ (((b0) &3u)))
+#else
#define MUX(b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1,b0) \
((((b15)&3) << 30) | \
(((b14)&3) << 28) | \
(((b2) &3) << 4) | \
(((b1) &3) << 2) | \
(((b0) &3)))
+#endif /* _MISRA_RULES */
/* Bit fields for PINT0_ASSIGN and PINT1_ASSIGN registers */
/* for legacy compatibility */
+#ifdef _MISRA_RULES
+#define WLS(x) (((x)-5u) & 0x03u) /* Word Length Select */
+#else
#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
+#endif /* _MISRA_RULES */
#define W1LMAX_MAX W1LMAX_MIN
#define EBIU_AMCBCTL0 EBIU_AMBCTL0
#define EBIU_AMCBCTL1 EBIU_AMBCTL1
#define PINT2_IRQ PINT2_REQUEST
#define PINT3_IRQ PINT3_REQUEST
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _DEF_BF54X_H */
-
/*********************************************************************************** */
/* System MMR Register Bits */
#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
-#define SET_NDSIZE(x) (((x)&0xF)<<8) /* NDSIZE[3:0] (Flex Descriptor Size)
+
+#ifdef _MISRA_RULES
+#define SET_NDSIZE(x) (((x)&0xFu)<<8)
+#else
+#define SET_NDSIZE(x) (((x)&0xF)<<8)
+#endif
+ /* NDSIZE[3:0] (Flex Descriptor Size)
Size of next descriptor
0000 - Required if in Stop or Autobuffer mode
0001 - 1001 - Descriptor size
#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
-/* SYSCR Masks */
-#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
-#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
-
/* ******************************************* */
/* MULTI BIT MACRO ENUMERATIONS */
#define nPJ15 0x0
+#ifdef _MISRA_RULES
+#define _MF15 0xFu
+#define _MF7 7u
+#else
+#define _MF15 0xF
+#define _MF7 7
+#endif /* _MISRA_RULES */
+
/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
+
/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
+/* SIC_IMASKx Masks */
+/* masks are 32 bit wide, so two writes reguired for "64 bit" wide registers */
+#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
+#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
+
+/* SIC_IMASKx Macros */
+#ifdef _MISRA_RULES
+#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
+#define SIC_UNMASK(x) (0xFFFFFFFFu ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
+#else
+#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
+#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
+#endif /* _MISRA_RULES */
+
+/* SIC_IWR Masks */
+#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
+#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
+
+/* SIC_IWR Macros */
+/* x = pos 0 to 31, for 32-63 use value-32 */
+#ifdef _MISRA_RULES
+#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
+#define IWR_DISABLE(x) (0xFFFFFFFFu ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
+#else
+#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
+#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
+#endif /* _MISRA_RULES */
+
+#define PIVG(PNr, IVGNr) ( (IVGNr) - 7) << ( ((PNr)%8) * 4) /* Peripheral #PNr assigned IVG #IVGNr */
+/* Rx.L = lo(PIVG(62,10)); */
+/* Rx.H = hi(PIVG(62,10)); */
+/* PNr = 0 to 95 */
+/* IVGNr = 7 to 15 */
+
/* SIC_IAR0 Macros */
-#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
-#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
-#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
-#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
-#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
-#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
-#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
-#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
+#define P0_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #0 assigned IVG #x */
+#define P1_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #1 assigned IVG #x */
+#define P2_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #2 assigned IVG #x */
+#define P3_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #3 assigned IVG #x */
+#define P4_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #4 assigned IVG #x */
+#define P5_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #5 assigned IVG #x */
+#define P6_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #6 assigned IVG #x */
+#define P7_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #7 assigned IVG #x */
/* SIC_IAR1 Macros */
-#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
-#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
-#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
-#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
-#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
-#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
-#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
-#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
+#define P8_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #8 assigned IVG #x */
+#define P9_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #9 assigned IVG #x */
+#define P10_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #10 assigned IVG #x */
+#define P11_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #11 assigned IVG #x */
+#define P12_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #12 assigned IVG #x */
+#define P13_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #13 assigned IVG #x */
+#define P14_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #14 assigned IVG #x */
+#define P15_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #15 assigned IVG #x */
/* SIC_IAR2 Macros */
-#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
-#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
-#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
-#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
-#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
-#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
-#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
-#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
+#define P16_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #16 assigned IVG #x */
+#define P17_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #17 assigned IVG #x */
+#define P18_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #18 assigned IVG #x */
+#define P19_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #19 assigned IVG #x */
+#define P20_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #20 assigned IVG #x */
+#define P21_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #21 assigned IVG #x */
+#define P22_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #22 assigned IVG #x */
+#define P23_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #23 assigned IVG #x */
/* SIC_IAR3 Macros */
-#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
-#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
-#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
-#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
-#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
-#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
-#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
-#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
+#define P24_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #24 assigned IVG #x */
+#define P25_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #25 assigned IVG #x */
+#define P26_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #26 assigned IVG #x */
+#define P27_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #27 assigned IVG #x */
+#define P28_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #28 assigned IVG #x */
+#define P29_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #29 assigned IVG #x */
+#define P30_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #30 assigned IVG #x */
+#define P31_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #31 assigned IVG #x */
/* SIC_IAR4 Macros */
-#define P32_IVG(x) (((x)&0xF)-7) /* Peripheral #32 assigned IVG #x */
-#define P33_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #33 assigned IVG #x */
-#define P34_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #34 assigned IVG #x */
-#define P35_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #35 assigned IVG #x */
-#define P36_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #36 assigned IVG #x */
-#define P37_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #37 assigned IVG #x */
-#define P38_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #38 assigned IVG #x */
-#define P39_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #39 assigned IVG #x */
+#define P32_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #32 assigned IVG #x */
+#define P33_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #33 assigned IVG #x */
+#define P34_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #34 assigned IVG #x */
+#define P35_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #35 assigned IVG #x */
+#define P36_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #36 assigned IVG #x */
+#define P37_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #37 assigned IVG #x */
+#define P38_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #38 assigned IVG #x */
+#define P39_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #39 assigned IVG #x */
/* SIC_IAR4 Macros */
-#define P40_IVG(x) (((x)&0xF)-7) /* Peripheral #40 assigned IVG #x */
-#define P41_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #41 assigned IVG #x */
-#define P42_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #42 assigned IVG #x */
-#define P43_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #43 assigned IVG #x */
-#define P44_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #44 assigned IVG #x */
-#define P45_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #45 assigned IVG #x */
-#define P46_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #46 assigned IVG #x */
-#define P47_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #47 assigned IVG #x */
+#define P40_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #40 assigned IVG #x */
+#define P41_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #41 assigned IVG #x */
+#define P42_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #42 assigned IVG #x */
+#define P43_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #43 assigned IVG #x */
+#define P44_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #44 assigned IVG #x */
+#define P45_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #45 assigned IVG #x */
+#define P46_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #46 assigned IVG #x */
+#define P47_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #47 assigned IVG #x */
/* SIC_IAR5 Macros */
-#define P48_IVG(x) (((x)&0xF)-7) /* Peripheral #48 assigned IVG #x */
-#define P49_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #49 assigned IVG #x */
-#define P50_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #50 assigned IVG #x */
-#define P51_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #51 assigned IVG #x */
-#define P52_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #52 assigned IVG #x */
-#define P53_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #53 assigned IVG #x */
-#define P54_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #54 assigned IVG #x */
-#define P55_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #55 assigned IVG #x */
+#define P48_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #48 assigned IVG #x */
+#define P49_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #49 assigned IVG #x */
+#define P50_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #50 assigned IVG #x */
+#define P51_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #51 assigned IVG #x */
+#define P52_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #52 assigned IVG #x */
+#define P53_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #53 assigned IVG #x */
+#define P54_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #54 assigned IVG #x */
+#define P55_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #55 assigned IVG #x */
/* SIC_IAR5 Macros */
-#define P56_IVG(x) (((x)&0xF)-7) /* Peripheral #56 assigned IVG #x */
-#define P57_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #57 assigned IVG #x */
-#define P58_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #58 assigned IVG #x */
-#define P59_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #59 assigned IVG #x */
-#define P60_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #60 assigned IVG #x */
-#define P61_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #61 assigned IVG #x */
-#define P62_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #62 assigned IVG #x */
-#define P63_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #63 assigned IVG #x */
+#define P56_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #56 assigned IVG #x */
+#define P57_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #57 assigned IVG #x */
+#define P58_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #58 assigned IVG #x */
+#define P59_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #59 assigned IVG #x */
+#define P60_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #60 assigned IVG #x */
+#define P61_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #61 assigned IVG #x */
+#define P62_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #62 assigned IVG #x */
+#define P63_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #63 assigned IVG #x */
/* SIC_IAR6 Macros */
-#define P64_IVG(x) (((x)&0xF)-7) /* Peripheral #64 assigned IVG #x */
-#define P65_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #65 assigned IVG #x */
-#define P66_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #66 assigned IVG #x */
-#define P67_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #67 assigned IVG #x */
-#define P68_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #68 assigned IVG #x */
-#define P69_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #69 assigned IVG #x */
-#define P70_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #70 assigned IVG #x */
-#define P71_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #71 assigned IVG #x */
-
-/* SIC_IAR7 Macros */
-#define P72_IVG(x) (((x)&0xF)-7) /* Peripheral #72 assigned IVG #x */
-#define P73_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #73 assigned IVG #x */
-#define P74_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #74 assigned IVG #x */
-#define P75_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #75 assigned IVG #x */
-#define P76_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #76 assigned IVG #x */
-#define P77_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #77 assigned IVG #x */
-#define P78_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #78 assigned IVG #x */
-#define P79_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #79 assigned IVG #x */
+#define P64_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #64 assigned IVG #x */
+#define P65_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #65 assigned IVG #x */
+#define P66_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #66 assigned IVG #x */
+#define P67_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #67 assigned IVG #x */
+#define P68_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #68 assigned IVG #x */
+#define P69_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #69 assigned IVG #x */
+#define P70_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #70 assigned IVG #x */
+#define P71_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #71 assigned IVG #x */
/* SIC_IAR7 Macros */
-#define P72_IVG(x) (((x)&0xF)-7) /* Peripheral #72 assigned IVG #x */
-#define P73_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #73 assigned IVG #x */
-#define P74_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #74 assigned IVG #x */
-#define P75_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #75 assigned IVG #x */
-#define P76_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #76 assigned IVG #x */
-#define P77_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #77 assigned IVG #x */
-#define P78_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #78 assigned IVG #x */
-#define P79_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #79 assigned IVG #x */
+#define P72_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #72 assigned IVG #x */
+#define P73_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #73 assigned IVG #x */
+#define P74_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #74 assigned IVG #x */
+#define P75_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #75 assigned IVG #x */
+#define P76_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #76 assigned IVG #x */
+#define P77_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #77 assigned IVG #x */
+#define P78_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #78 assigned IVG #x */
+#define P79_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #79 assigned IVG #x */
/* SIC_IAR8 Macros */
-#define P80_IVG(x) (((x)&0xF)-7) /* Peripheral #80 assigned IVG #x */
-#define P81_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #81 assigned IVG #x */
-#define P82_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #82 assigned IVG #x */
-#define P83_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #83 assigned IVG #x */
-#define P84_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #84 assigned IVG #x */
-#define P85_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #85 assigned IVG #x */
-#define P86_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #86 assigned IVG #x */
-#define P87_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #87 assigned IVG #x */
+#define P80_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #80 assigned IVG #x */
+#define P81_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #81 assigned IVG #x */
+#define P82_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #82 assigned IVG #x */
+#define P83_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #83 assigned IVG #x */
+#define P84_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #84 assigned IVG #x */
+#define P85_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #85 assigned IVG #x */
+#define P86_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #86 assigned IVG #x */
+#define P87_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #87 assigned IVG #x */
+
+/* SIC_IAR9 Macros */
+#define P88_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #88 assigned IVG #x */
+#define P89_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #89 assigned IVG #x */
+#define P90_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #90 assigned IVG #x */
+#define P91_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #91 assigned IVG #x */
+#define P92_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #92 assigned IVG #x */
+#define P93_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #93 assigned IVG #x */
+#define P94_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #94 assigned IVG #x */
+#define P95_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #95 assigned IVG #x */
+
+
+/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/
-/* SIC_IAR8 Macros */
-#define P88_IVG(x) (((x)&0xF)-7) /* Peripheral #88 assigned IVG #x */
-#define P89_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #89 assigned IVG #x */
-#define P90_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #90 assigned IVG #x */
-#define P91_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #91 assigned IVG #x */
-#define P92_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #92 assigned IVG #x */
-#define P93_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #93 assigned IVG #x */
-#define P94_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #94 assigned IVG #x */
-#define P95_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #95 assigned IVG #x */
+/* Bit masks for SPIx_CTL */
+#define RDBR_CORE 0x0 /* RDBR Read Initiates, IRQ when RDBR Full */
+#define TDBR_CORE 0x1 /* TDBR Write Initiates, IRQ when TDBR Empty */
+#define RDBR_DMA 0x2 /* DMA Read, DMA Until FIFO Empty */
+#define TDBR_DMA 0x3 /* DMA Write, DMA Until FIFO Full */
+
+
+/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
+/* Bit macros for TWIx_CONTROL */
+#define SET_TWI_PRESCALE(x) ( (x) & PRESCALE )
+#define SET_TWI_DCNT(x) ( ((x) << 0x6) & DCNT )
+
+/* Bit masks for TWIx_INT_MASK */
+#define SCLIM 0x8000 /* Serial Clock Interrupt */
+#define nSCLIM 0x0
+#define SDAIM 0x4000 /* Serial Data Interrupt */
+#define nSDAIM 0x0
+
+/* Bit masks for TWIx_INT_STAT */
+#define SCLI 0x8000 /* Serial Clock Interrupt */
+#define nSCLI 0x0
+#define SDAI 0x4000 /* Serial Data Interrupt */
+#define nSDAI 0x0
+
+/* Bit macros for TWIx_MASTER_ADDR */
+#define SET_TWI_ADDR(x) ( (x) & 0x7F )
/* ********* WATCHDOG TIMER MASKS ******************** */
/* Watchdog Timer WDOG_CTL Register Masks */
+#ifdef _MISRA_RULES
+#define SET_WDEV(x) (((x)<<1) & 0x0006u) /* event generated on roll over */
+#else
#define SET_WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
+#endif /* _MISRA_RULES */
#define WDEV_RESET 0x0000 /* generate reset event on roll over */
#define nWDEV_RESET 0x0
#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
#define ENABLE_PRESCALE PREN /* Enable prescaler so RTC runs at 1 Hz */
/* RTC_ALARM Macro: z=day, y=hr, x=min, w=sec */
+#ifdef _MISRA_RULES
+#define SET_ALARM(z,y,x,w) ((((z)&0x7FFFu)<<0x11)|(((y)&0x1Fu)<<0xC)|(((x)&0x3Fu)<<0x6)|((w)&0x3Fu))
+#else
#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
+#endif /* _MISRA_RULES */
+
+/* ************** UART CONTROLLER MASKS *************************/
+/* Bit masks for UART Divisor Latch Registers: UARTx_DLL & UARTx_DLH */
+#define UARTDLL 0x00FF /* Divisor Latch Low Byte */
+#define UARTDLH 0xFF00 /* Divisor Latch High Byte */
/* ******************************************* */
#define nW1ZMONCE 0x0
/* Bit macros for CNT_DEBOUNCE */
+#ifdef _MISRA_RULES
+#define SET_DPRESCALE(x) ((x)&0x7u) /* 0000: 1x -> 0111: 128x, 1xxx Reserved */
+#else
#define SET_DPRESCALE(x) ((x)&0x7) /* 0000: 1x -> 0111: 128x, 1xxx Reserved */
+#endif /* _MISRA_RULES */
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define MCMEM MCMEN
+#define nMCMEM 0x0
+
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif /* _DEF_BF54X_H */
+
*
* defBF561.h
*
- * Copyright (C) 2008 Analog Devices, Inc.
+ * Copyright (C) 2008, 2009 Analog Devices, Inc.
*
************************************************************************/
#define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */
#define PLL_OFF 0x0002 /* Shut off PLL clocks */
#define STOPCK_OFF 0x0008 /* Core clock off */
-#define ALT_TIMING 0x0010 /* Enable Alternate PPI Timing (0.5 Silicon And Beyond) */
+#define ALT_TIMING 0x0010 /* Enable Alternate PPI Timing */
#define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */
#define BYPASS 0x0100 /* Bypass the PLL */
+#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
+#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
+#define IN_DELAY 0x0040 /* Add 200ps Delay on EBIU Inputs */
+#define OUT_DELAY 0x0080 /* Add 200ps Delay on EBIU Outputs */
+#define SPORT_HYS 0x8000 /* Add 250mV Hysteresis to SPORT Inputs */
+
+/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
+#ifdef _MISRA_RULES
+#define SET_MSEL(x) (((x)&0x3Fu) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
+#else
+#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
+#endif /* _MISRA_RULES */
/* PLL_DIV Masks */
+#define SSEL 0x000F /* System Select */
+#define CSEL 0x0030 /* Core Select */
#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
+/* PLL_DIV Macros */
+#ifdef _MISRA_RULES
+#define SET_SSEL(x) ((x)&0xFu) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
+#else
+#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
+#endif /* _MISRA_RULES */
+
+/* PLL_STAT Macros */
+#define VSTAT 0x0080 /* Voltage Regulator Status: Regulator at programmed voltage */
+#define CORE_IDLE 0x0040 /* processor is in the IDLE operating mode */
+#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
+#define SLEEP 0x0010 /* processor is in the Sleep operating mode */
+#define DEEP_SLEEP 0x0008 /* processor is in the Deep Sleep operating mode */
+#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
+#define FULL_ON 0x0002 /* Processor In Full On Mode */
+#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
+
+
#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */
#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */
#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */
#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */
/* SWRST Mask */
-#define SYSTEM_RESET 0x00000007 /* Initiates a system software reset */
-#define SWRST_DBL_FAULT_B 0x00000800 /* SWRST Core B Double Fault */
-#define SWRST_DBL_FAULT_A 0x00001000 /* SWRST Core A Double Fault */
-#define SWRST_WDT_B 0x00002000 /* SWRST Watchdog B */
-#define SWRST_WDT_A 0x00004000 /* SWRST Watchdog A */
-#define SWRST_OCCURRED 0x00008000 /* SWRST Status */
+#define SYSTEM_RESET 0x0007 /* Initiates a system software reset */
+#define SWRST_DBL_FAULT_A 0x0800 /* SWRST Core A Double Fault */
+#define SWRST_DBL_FAULT_B 0x1000 /* SWRST Core B Double Fault */
+#define SWRST_WDT_B 0x2000 /* SWRST Watchdog B */
+#define SWRST_WDT_A 0x4000 /* SWRST Watchdog A */
+#define SWRST_OCCURRED 0x8000 /* SWRST Status */
/* VR_CTL Masks */
#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
+#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
+#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */
+
#define GAIN 0x000C /* Voltage Level Gain */
#define GAIN_5 0x0000 /* GAIN = 5 */
#define VLEV_125 0x00E0 /* VLEV = 1.25 V (See Datasheet for Regulator Tolerance) */
#define VLEV_130 0x00F0 /* VLEV = 1.30 V (See Datasheet for Regulator Tolerance) */
+/* SYSCR Masks */
+#define BMODE_BYPASS 0x0000 /* Bypass boot ROM, execute from 16-bit external memory */
+#define BMODE_FLASH 0x0001 /* Use Boot ROM to load from 8-bit or 16-bit flash */
+#define BMODE_SPIHOST 0x0002 /* Boot from SPI0 host (slave mode) */
+#define BMODE_SPIMEM 0x0003 /* Boot from serial SPI memory */
+
+
/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
+/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
+#define PLL_WAKEUP_IRQ 0x00000001 /* PLL Wakeup Interrupt Request */
+#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt Request */
+
/* ********* WATCHDOG TIMER MASKS ******************** */
/* Watchdog Timer WDOG_CTL Register Masks */
+#ifdef _MISRA_RULES
+#define WDEV(x) (((x)<<1) & 0x0006u) /* event generated on roll over */
+#else
#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
+#endif /* _MISRA_RULES */
#define WDEV_RESET 0x0000 /* generate reset event on roll over */
#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
#define EPS 0x10
#define PEN 0x08
#define STB 0x04
+#ifdef _MISRA_RULES
+#define WLS(x) (((x)-5u) & 0x03u) /* Word Length Select */
+#else
#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
+#endif /* _MISRA_RULES */
#define DLAB_P 0x07
#define SB_P 0x06
#define ERBFI_P 0x00
/* UART_IIR Register */
+#ifdef _MISRA_RULES
+#define STATUS(x) (((x) << 1) & 0x06u)
+#else
#define STATUS(x) (((x) << 1) & 0x06)
+#endif /* _MISRA_RULES */
#define NINT 0x01
#define STATUS_P1 0x02
#define STATUS_P0 0x01
#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */
#define DLENGTH 0x00003800 /* PPI Data Length */
#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */
+#ifdef _MISRA_RULES
+#define DLEN(x) ((((x)-9u) & 0x07u) << 11) /* PPI Data Length (only works for x=10-->x=16) */
+#else
#define DLEN(x) ((((x)-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
+#endif /* _MISRA_RULES */
#define POL 0x0000C000 /* PPI Signal Polarities */
#define CLK_SEL 0x0080
#define TOGGLE_HI 0x0100
#define EMU_RUN 0x0200
+#ifdef _MISRA_RULES
+#define ERR_TYP(x) (((x) & 0x03u) << 14)
+#else
#define ERR_TYP(x) (((x) & 0x03) << 14)
+#endif /* _MISRA_RULES */
#define TMODE_P0 0x00
#define TMODE_P1 0x01
#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
+#define CL 0x0000000C /* SDRAM CAS latency */
#define PFE 0x00000010 /* Enable SDRAM prefetch */
#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
+#define PASR 0x00000030 /* SDRAM partial array self-refresh */
#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
+#define TRAS 0x000003C0 /* SDRAM tRAS in SCLK cycles */
#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
+#define TRP 0x00003800 /* SDRAM tRP in SCLK cycles */
#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
+#define TRCD 0x00030000 /* SDRAM tRCD in SCLK cycles */
#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
+#define TWR 0x00180000 /* SDRAM tWR in SCLK cycles */
#define PUPSD 0x00200000 /*Power-up start delay */
#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
/* EBIU_SDBCTL Masks */
+#define EBSZ 0x000E /* SDRAM external bank size */
+#define EBCAW 0x0030 /* SDRAM external bank column address width */
#define EB0_E 0x00000001 /* Enable SDRAM external bank 0 */
#define EB0_SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
#define EB0_SZ_32 0x00000002 /* SDRAM external bank size = 32MB */
*
* def_LPBlackfin.h
*
- * Copyright (C) 2008 Analog Devices, Inc.
+ * Copyright (C) 2008, 2009 Analog Devices, Inc.
*
************************************************************************/
#warning def_LPBlackfin.h should only be included for 532 compatible chips.
#endif
/* ensure macro params bracketed to avoid unexpected evaluations. (GA), MISRA Rule 19.10 */
+#ifdef _MISRA_RULES
+#define MK_BMSK_( x ) (1ul<<(x)) /* Make a bit mask from a bit position */
+#else
#define MK_BMSK_( x ) (1<<(x)) /* Make a bit mask from a bit position */
+#endif /* _MISRA_RULES */
/*********************************************************************************** */
/* System Register Bits */
/* IMEM_CONTROL Register */
/* ** Bit Positions */
-#define ENIM_P 0x00 /* Enable L1 Code Memory */
-#define IMCTL_ENIM_P 0x00 /* "" (older define) */
#define ENICPLB_P 0x01 /* Enable ICPLB */
#define IMCTL_ENICPLB_P 0x01 /* "" (older define) */
#define IMC_P 0x02 /* Enable */
#define ILOC3_P 0x06 /* Lock Way 3 */
#define LRUPRIORST_P 0x0D /* Least Recently Used Replacement Priority */
/* ** Masks */
-#define ENIM 0x00000001 /* Enable L1 Code Memory */
#define ENICPLB 0x00000002 /* Enable ICPLB */
#define IMC 0x00000004 /* Configure L1 code memory as cache (0=SRAM) */
#define ILOC0 0x00000008 /* Lock Way 0 */
#define TAUTORLD_P 0x00000002 /* Timer auto reload */
#define TINT_P 0x00000003 /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */
-/* DCPLB_DATA and ICPLB_DATA Registers */
-/*** Bit Positions */
-#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */
-#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry locked */
-#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access allowed (user mode) */
-/*** Masks */
+/* DCPLB_DATA and ICPLB_DATA Registers - bit positions */
+#define CPLB_VALID_P 0 /* 0=invalid entry, 1=valid entry */
+#define CPLB_LOCK_P 1 /* 0=entry may be replaced, 1=entry locked */
+#define CPLB_USER_RD_P 2 /* 0=no read access, 1=read access allowed (user mode) */
+#define CPLB_PORTPRIO_P 9 /* 0=low priority port, 1= high priority port */
+/*** ICPLB_DATA only */
+#define CPLB_LRUPRIO_P 8 /* 0=can be replaced by any line, 1=priority for non-replacement */
+/*** DCPLB_DATA only */
+#define CPLB_USER_WR_P 3 /* 0=no write access, 0=write access allowed (user mode) */
+#define CPLB_SUPV_WR_P 4 /* 0=no write access, 0=write access allowed (supervisor mode) */
+#define CPLB_DIRTY_P 7 /* 1=dirty, 0=clean */
+#define CPLB_L1_CHBL_P 12 /* 0=non-cacheable in L1, 1=cacheable in L1 */
+#define CPLB_WT_P 14 /* 0=write-back, 1=write-through */
+#define CPLB_L1_AOW_P 15 /* 0=do not allocate cache lines on write-through writes, */
+ /* 1= allocate cache lines on write-through writes. */
+
+/* DCPLB_DATA and ICPLB_DATA Registers - Masks */
#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */
#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry locked */
#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access allowed (user mode) */
#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
-#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high priority port */
+#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high priority port */
#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable in L1 */
/*** ICPLB_DATA only */
-#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line, 1=priority for non-replacement */
+#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line, 1=priority for non-replacement */
/*** DCPLB_DATA only */
#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write access allowed (user mode) */
#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write access allowed (supervisor mode) */
#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */
-#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on write-through writes, */
- /* 1= allocate cache lines on write-through writes. */
+#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on write-through writes, */
+ /* 1= allocate cache lines on write-through writes. */
#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
#define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */
#define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */
/* ensure macro params bracketed to avoid unexpected evaluations. (GA) MISRA Rule 19.10 */
+#ifdef _MISRA_RULES
+#define TEST_SET(x) (((x) << 5) & 0x03E0u) /* Set Index 0->31 */
+#else
#define TEST_SET(x) (((x) << 5) & 0x03E0) /* Set Index 0->31 */
+#endif /* _MISRA_RULES */
#define TEST_WAY0 0x00000000 /* Access Way0 */
#define TEST_WAY1 0x04000000 /* Access Way1 */
/*** ITEST_COMMAND only */
*
* defblackfin.h
*
- * Copyright (C) 2008 Analog Devices, Inc.
+ * Copyright (C) 2008, 2009 Analog Devices, Inc.
*
************************************************************************/
#if defined(__ADSPLPBLACKFIN__)
#warning defblackfin.h should only be included for 535 compatible chips.
#endif
-/* Macro parameters should be enclosed in parantheses to avoid incorrect expression evaluation. MISRA Rule 19.10 */
+/* Macro parameters should be enclosed in parentheses to avoid incorrect expression evaluation. MISRA Rule 19.10 */
+#ifdef _MISRA_RULES
+#define MK_BMSK_( x ) (1ul<<(x)) /* Make a bit mask from a bit position */
+#else
#define MK_BMSK_( x ) (1<<(x)) /* Make a bit mask from a bit position */
+#endif /* _MISRA_RULES */
/*********************************************************************************** */
/* System Register Bits */
/* DCPLB_DATA and ICPLB_DATA Bit Positions */
-#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */
-#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry locked */
-#define CPLB_USER_RD_P 0x00000002 /* */
+#define CPLB_VALID_P 0 /* 0=invalid entry, 1=valid entry */
+#define CPLB_LOCK_P 1 /* 0=entry may be replaced, 1=entry locked */
+#define CPLB_USER_RD_P 2 /* 0=no read access, 1=read access allowed (user mode) */
+/*** DCPLB_DATA only */
+#define CPLB_USER_WR_P 3 /* 0=no write access, 0=write access allowed (user mode) */
+#define CPLB_SUPV_WR_P 4 /* 0=no write access, 0=write access allowed (supervisor mode) */
+#define CPLB_L1SRAM_P 5 /* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */
+#define CPLB_DA0ACC_P 6 /* 0=access allowed from either DAG, 1=access from DAG0 only */
+#define CPLB_DIRTY_P 7 /* 1=dirty, 0=clean */
+#define CPLB_L1_CHBL_P 12 /* 0=non-cacheable in L1, 1=cacheable in L1 */
+#define CPLB_WT_P 14 /* 0=write-back, 1=write-through */
+
/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
#if !defined(__ADSPLPBLACKFIN__)
#include <cdefAD6903.h>
#elif defined (__AD6904__)
#include <cdefAD6904.h>
+#elif defined (__AD6905__)
+#include <cdefAD6905.h>
+#elif defined (__MT6906__)
+#include <cdefMT6906.h>
+#elif defined (__ADSPBF504__)
+#include <cdefBF504.h>
+#elif defined (__ADSPBF505__)
+#include <cdefBF505.h>
+#elif defined (__ADSPBF506__)
+#include <cdefBF506.h>
+#elif defined (__ADSPBF512__)
+#include <cdefBF512.h>
+#elif defined (__ADSPBF514__)
+#include <cdefBF514.h>
+#elif defined (__ADSPBF516__)
+#include <cdefBF516.h>
+#elif defined (__ADSPBF518__)
+#include <cdefBF518.h>
#elif defined (__ADSPBF522__)
#include <cdefBF522.h>
+#elif defined (__ADSPBF523__)
+#include <cdefBF523.h>
+#elif defined (__ADSPBF524__)
+#include <cdefBF524.h>
#elif defined (__ADSPBF525__)
#include <cdefBF525.h>
+#elif defined (__ADSPBF526__)
+#include <cdefBF526.h>
#elif defined (__ADSPBF527__)
#include <cdefBF527.h>
#elif defined (__ADSPBF542__) || defined (__ADSPBF541__)
#include <cdefBF542.h>
+#elif defined (__ADSPBF542M__)
+#include <cdefBF542M.h>
#elif defined (__ADSPBF544__)
#include <cdefBF544.h>
+#elif defined (__ADSPBF544M__)
+#include <cdefBF544M.h>
#elif defined (__ADSPBF547__)
#include <cdefBF547.h>
+#elif defined (__ADSPBF547M__)
+#include <cdefBF547M.h>
#elif defined (__ADSPBF548__)
#include <cdefBF548.h>
+#elif defined (__ADSPBF548M__)
+#include <cdefBF548M.h>
#elif defined (__ADSPBF549__)
#include <cdefBF549.h>
+#elif defined (__ADSPBF549M__)
+#include <cdefBF549M.h>
#else
#error Processor Type Not Supported
#endif
#include <defAD6903.h>
#elif defined (__AD6904__)
#include <defAD6904.h>
+#elif defined (__AD6905__)
+#include <defAD6905.h>
+#elif defined (__MT6906__)
+#include <defMT6906.h>
+#elif defined (__ADSPBF504__)
+#include <defBF504.h>
+#elif defined (__ADSPBF505__)
+#include <defBF505.h>
+#elif defined (__ADSPBF506__)
+#include <defBF506.h>
+#elif defined (__ADSPBF512__)
+#include <defBF512.h>
+#elif defined (__ADSPBF514__)
+#include <defBF514.h>
+#elif defined (__ADSPBF516__)
+#include <defBF516.h>
+#elif defined (__ADSPBF518__)
+#include <defBF518.h>
#elif defined (__ADSPBF522__)
#include <defBF522.h>
+#elif defined (__ADSPBF523__)
+#include <defBF523.h>
+#elif defined (__ADSPBF524__)
+#include <defBF524.h>
#elif defined (__ADSPBF525__)
#include <defBF525.h>
+#elif defined (__ADSPBF526__)
+#include <defBF526.h>
#elif defined (__ADSPBF527__)
#include <defBF527.h>
#elif defined (__ADSPBF542__) || defined (__ADSPBF541__)
#include <defBF542.h>
+#elif defined (__ADSPBF542M__)
+#include <defBF542M.h>
#elif defined (__ADSPBF544__)
#include <defBF544.h>
+#elif defined (__ADSPBF544M__)
+#include <defBF544M.h>
#elif defined (__ADSPBF547__)
#include <defBF547.h>
+#elif defined (__ADSPBF547M__)
+#include <defBF547M.h>
#elif defined (__ADSPBF548__)
#include <defBF548.h>
+#elif defined (__ADSPBF548M__)
+#include <defBF548M.h>
#elif defined (__ADSPBF549__)
#include <defBF549.h>
+#elif defined (__ADSPBF549M__)
+#include <defBF549M.h>
#else
#error Processor Type Not Supported
*
* anomaly_macros_rtl.h : $Revision$
*
- * Copyright (C) 2008 Analog Devices, Inc.
+ * Copyright (C) 2008, 2009 Analog Devices, Inc.
*
* This file defines macros used within the run-time libraries to enable
* certain anomaly workarounds for the appropriate chips and silicon
************************************************************************/
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_2_4:"Assembly code in comment used to illustrate anomalous behaviour")
+#pragma diag(suppress:misra_rule_19_4:"The definition of WA_05000204_CHECK_AVOID_FOR_REV cannot be parenthasised as it would fail when used in assembly library code.")
+#endif /* _MISRA_RULES */
+
#if !defined(__SILICON_REVISION__)
#define __FORCE_LEGACY_WORKAROUNDS__
#endif
defined(__FORCE_LEGACY_WORKAROUNDS__)))
+/* 05-00-0127 - Signbits instruction not functional under certain conditions
+**
+** ADSP-BF561 - from rev 0.0 (not yet fixed)
+**
+** The SIGNBITS instruction requires a NOP before it if one of its operands
+** is defined in the preceding instruction.
+**
+*/
+#define WA_05000127 \
+ (defined(__SILICON_REVISION__) && defined(__ADSPBF561__))
+
+
/* 05-00-0137 - DMEM_CONTROL<12> is not set on Reset
**
** ADSP-BF531/2/3 - revs 0.0-0.2 (fixed 0.3)
defined(__FORCE_LEGACY_WORKAROUNDS__)))
+/* 05-00-0162 - DMEM_CONTROL<12> is not set on Reset
+**
+** ADSP-BF561 - revs 0.0-0.2 (fixed 0.3)
+**
+** Changes to start code.
+**
+*/
+#define WA_05000162 \
+ (defined(__ADSPBF561__) && \
+ ((defined(__SILICON_REVISION__) && \
+ (__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x2)) || \
+ defined(__FORCE_LEGACY_WORKAROUNDS__)))
+
+/* 05-00-0198 - System MMR accesses may fail when stalled by preceding memory
+** read.
+**
+** Impacted:
+** ADSP-BF531 - rev 0.1-0.4 (fixed 0.5)
+** ADSP-BF532 - rev 0.1-0.4 (fixed 0.5)
+** ADSP-BF533 - rev 0.1-0.4 (fixed 0.5)
+** ADSP-BF534 - rev 0.0 (fixed 0.1)
+** ADSP-BF536 - rev 0.0 (fixed 0.1)
+** ADSP-BF537 - rev 0.0 (fixed 0.1)
+** ADSP-BF561 - rev 0.2-0.3 (fixed 0.4)
+**
+*/
+#define WA_05000198 \
+ (((defined(__ADSPBF531__) || \
+ defined(__ADSPBF532__) || \
+ defined(__ADSPBF533__)) && \
+ (defined(__SILICON_REVISION__) && \
+ (__SILICON_REVISION__ <= 0x4 || __SILICON_REVISION__ == 0xffff))) || \
+ ((defined(__ADSPBF534__) || \
+ defined(__ADSPBF536__) || \
+ defined(__ADSPBF537__) || \
+ defined(__ADSPBF539__)) && \
+ (defined(__SILICON_REVISION__) && \
+ (__SILICON_REVISION__ == 0x0 || __SILICON_REVISION__ == 0xffff))) || \
+ (defined(__ADSPBF561__) && \
+ (defined(__SILICON_REVISION__) && \
+ (__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff))))
+
+
+/* 05-00-0199 - Current DMA Address Shows Wrong Value During Carry Fix
+**
+** Impacted:
+** ADSP-BF53[123] - rev 0.0-0.3 (fixed 0.4)
+** ADSP-BF53[89] - rev 0.0-0.3 (fixed 0.4)
+** ADSP-BF561 - rev 0.0-0.3 (fixed 0.4)
+**
+** Use by System Services/Device Drivers.
+*/
+#define WA_05000199 \
+ ((defined(__ADSPBF533_FAMILY__) && \
+ (defined(__SILICON_REVISION__) && \
+ (__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff))) || \
+ (defined(__ADSPBF538_FAMILY__) && \
+ (defined(__SILICON_REVISION__) && \
+ (__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff))) || \
+ (defined(__ADSPBF561__) && \
+ (defined(__SILICON_REVISION__) && \
+ (__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff))))
+
+
/* 05-00-0204 - "Incorrect data read with write-through cache and
** allocate cache lines on reads only mode.
**
/* do not check at RT for 0.4 revs when doing 204 workaround */
#endif
+
+/* 05-00-0209 - Speed Path in Computational Unit Affects Certain Instructions
+**
+** ADSP-BF531/2/3 - revs 0.0 - 0.3 (fixed in 0.4)
+** ADSP-BF534/6/7 - rev 0.0 (fixed in 0.1)
+** ADSP-BF538/9 - rev 0.0 (fixed in 0.1)
+** ADSP-BF561 - revs 0.0 - 0.3 (fixed in 0.4)
+**
+** SIGNBITS, EXTRACT, DEPOSIT, EXPADJ require a NOP before them if
+** one of their operands is defined in the preceding instruction.
+*/
+#define WA_05000209 \
+ (defined(__SILICON_REVISION__) && \
+ (((defined(__ADSPBF531__) || \
+ defined(__ADSPBF532__) || \
+ defined(__ADSPBF533__)) && \
+ (__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff)) || \
+ ((defined(__ADSPBF534__) || \
+ defined(__ADSPBF536__) || \
+ defined(__ADSPBF537__) || \
+ defined(__ADSPBF538__) || \
+ defined(__ADSPBF539__)) && \
+ (__SILICON_REVISION__ == 0x0 || __SILICON_REVISION__ == 0xffff)) || \
+ ((defined(__ADSPBF561__)) && \
+ (__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff))))
+
+
+/* 05-00-0212 - PORTx_FER, PORT_MUX Registers Do Not accept "writes" correctly
+**
+** Impacted:
+** ADSP-BF53[467] - rev 0.0 (fixed 0.1)
+**
+** Use by System Services/Device Drivers.
+*/
+#define WA_05000212 \
+ (defined(__ADSPBF537_FAMILY__) && \
+ (defined(__SILICON_REVISION__) && \
+ (__SILICON_REVISION__ == 0x0 || __SILICON_REVISION__ == 0xffff)))
+
+
/* 05-00-0258 - "Instruction Cache is corrupted when bit 9 and 12 of
* the ICPLB Data registers differ"
*
* BF531/2/3 - 0.0-0.4 (fixed 0.5)
* BF534/6/7/8/9 - 0.0-0.2 (fixed 0.3)
* BF561 - 0.0-0.4 (fixed 0.5)
+ * BF566 - 0.0-0.1 (fixed 0.2)
* BF535/AD6532/AD6900 - all revs
*/
-
#define WA_05000258 \
- defined(__SILICON_REVISION__) && \
- (__SILICON_REVISION__ == 0xffff || \
- !defined(__ADSPLPBLACKFIN__) || \
- ((defined(__ADSPBF531__) || \
- defined(__ADSPBF532__) || \
- defined(__ADSPBF533__)) && \
- (__SILICON_REVISION__ <= 0x4)) || \
- ((defined(__ADSPBF534__) || \
- defined(__ADSPBF536__) || \
- defined(__ADSPBF537__) || \
- defined(__ADSPBF538__) || \
- defined(__ADSPBF539__)) && \
- (__SILICON_REVISION__ <= 0x2)) || \
- ((defined(__ADSPBF561__)) && \
- (__SILICON_REVISION__ <= 0x4)) || \
- ((defined(__ADSPBF561__)) && \
- (__SILICON_REVISION__ < 0x1)))
+ (((defined(__ADSPBF531__) || \
+ defined(__ADSPBF532__) || \
+ defined(__ADSPBF533__)) && \
+ (defined(__SILICON_REVISION__) && \
+ (__SILICON_REVISION__ <= 0x4 || \
+ __SILICON_REVISION__ == 0xffff))) || \
+ ((defined(__ADSPBF534__) || \
+ defined(__ADSPBF536__) || \
+ defined(__ADSPBF537__) || \
+ defined(__ADSPBF538__) || \
+ defined(__ADSPBF539__)) && \
+ (defined(__SILICON_REVISION__) && \
+ (__SILICON_REVISION__ <= 0x2 || \
+ __SILICON_REVISION__ == 0xffff))) || \
+ (defined(__ADSPBF561__) && \
+ (defined(__SILICON_REVISION__) && \
+ (__SILICON_REVISION__ <= 0x4 || \
+ __SILICON_REVISION__ == 0xffff))) || \
+ (defined(__ADSPBF566__) && \
+ (defined(__SILICON_REVISION__) && \
+ (__SILICON_REVISION__ <= 0x1 || \
+ __SILICON_REVISION__ == 0xffff))) || \
+ (!defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__)))
+
/* 05-00-0259 - "Non-deterministic ICPLB descriptors delivered to
* hardware". Whenever ICPLBs are disabled via an MMR write, immediately
*/
#define WA_05000261 \
- defined(__SILICON_REVISION__) && \
- (__SILICON_REVISION__ == 0xffff || \
- ((defined(__ADSPBF531__) || \
- defined(__ADSPBF532__) || \
- defined(__ADSPBF533__)) && \
- (__SILICON_REVISION__ <= 0x4)) || \
- ((defined(__ADSPBF534__) || \
- defined(__ADSPBF536__) || \
- defined(__ADSPBF537__) || \
- defined(__ADSPBF538__) || \
- defined(__ADSPBF539__)) && \
- (__SILICON_REVISION__ <= 0x2)) || \
- ((defined(__ADSPBF561__)) && \
- (__SILICON_REVISION__ <= 0x4)) || \
- ((defined(__ADSPBF561__)) && \
- (__SILICON_REVISION__ < 0x1)))
+ (((defined(__ADSPBF531__) || \
+ defined(__ADSPBF532__) || \
+ defined(__ADSPBF533__)) && \
+ (defined(__SILICON_REVISION__) && \
+ (__SILICON_REVISION__ <= 0x4 || \
+ __SILICON_REVISION__ == 0xffff))) || \
+ ((defined(__ADSPBF534__) || \
+ defined(__ADSPBF536__) || \
+ defined(__ADSPBF537__) || \
+ defined(__ADSPBF538__) || \
+ defined(__ADSPBF539__)) && \
+ (defined(__SILICON_REVISION__) && \
+ (__SILICON_REVISION__ <= 0x2 || \
+ __SILICON_REVISION__ == 0xffff))) || \
+ (defined(__ADSPBF561__) && \
+ (defined(__SILICON_REVISION__) && \
+ (__SILICON_REVISION__ <= 0x4 || \
+ __SILICON_REVISION__ == 0xffff))))
/* 05-00-0229 - "SPI Slave Boot Mode Modifies Registers".
* When the SPI slave boot completes, the final DMA IRQ is cleared
* after a not predicted conditional jump.
*
* This problem impacts:
- * BF531/2/3 - all revs
- * BF534/6/7/8/9 - all revs
- * BF561/6 - all revs
+ * BF531/2/3 - < 0.6
+ * BF534/6/7 - < 0.3
+ * BF538/9 - < 0.4
+ * BF561/6 - < 0.5
+ *
+ * Since this impacts 538/9 0.3 but not 534 0.3 (the libraries that they use)
+ * we have to enable this workaround for the 534 0.3 libraries (see bottom
+ * two lines).
*/
#define WA_05000283 \
- defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__)
+ (defined (__SILICON_REVISION__) && \
+ (((defined(__ADSPBF531__) || \
+ defined(__ADSPBF532__) || \
+ defined(__ADSPBF533__)) && \
+ (__SILICON_REVISION__ == 0xffff || \
+ __SILICON_REVISION__ < 0x6)) || \
+ ((defined(__ADSPBF534__) || \
+ defined(__ADSPBF536__) || \
+ defined(__ADSPBF537__)) && \
+ (__SILICON_REVISION__ == 0xffff || \
+ __SILICON_REVISION__ < 0x3)) || \
+ ((defined(__ADSPBF538__) || \
+ defined(__ADSPBF539__)) && \
+ (__SILICON_REVISION__ == 0xffff || \
+ __SILICON_REVISION__ < 0x4)) || \
+ (defined(__ADSPBF561__)) || \
+ (defined(__ADSPBF534__) && __SILICON_REVISION__ == 0x3 && \
+ defined(__ADI_LIB_BUILD__))))
+
+
+/* 05-00-0311 - Erroneous Flag (GPIO) Pin Operations under Specific Sequences
+**
+** Impacted:
+** ADSP-BF53[123] - 0.0-0.5 (fixed in 0.6)
+**
+** Use by System Services/Device Drivers.
+*/
+#define WA_05000311 \
+ (defined(__ADSPBF533_FAMILY__) && \
+ (defined(__SILICON_REVISION__) && \
+ (__SILICON_REVISION__ <= 0x5 || __SILICON_REVISION__ == 0xffff)))
+
+
+/* 05-00-0323 - Erroneous Flag (GPIO) Pin Operations under Specific Sequences
+**
+** Impacted:
+** ADSP-BF561 - all supported revisions
+**
+** Use by System Services/Device Drivers.
+*/
+#define WA_05000323 \
+ (defined(__ADSPBF561__) && defined(__SILICON_REVISION__))
+
+
+/* 05-00-0365 - DMAs that Go Urgent during Tight Core Writes to External
+** Memory Are Blocked
+**
+** Impacted:
+** ADSP-BF54[24789] - all supported revisions
+** ADSP-BF54[24789]M - all supported revisions
+**
+** Use by System Services/Device Drivers.
+*/
+#define WA_05000365 \
+ ((defined(__ADSPBF548_FAMILY__) || defined(__ADSPBF548M_FAMILY__)) && \
+ defined(__SILICON_REVISION__))
+
+
+/* 05-00-0380 - Data Read From L3 Memory by USB DMA May be Corrupted
+**
+** Impacted:
+** ADSP-BF52[357] - rev 0.0-0.1 (fixed 0.2)
+**
+** Use by System Services/Device Drivers.
+*/
+#define WA_05000380 \
+ (defined(__ADSPBF527_FAMILY__) && \
+ (defined(__SILICON_REVISION__) && \
+ (__SILICON_REVISION__ <= 0x1 || __SILICON_REVISION__ == 0xffff)))
+
+
+/* 05-00-0412 - "TESTSET Instruction Causes Data Corruption with Writeback Data
+ * Cache Enabled"
+ *
+ * If you use the testset instruction to operate on L2 memory and you have data
+ * in external memory that is cached using WB mode, data in external memory
+ * and/or L2 memory can be corrupted.
+ *
+ * Workaround: Either do not use writeback cache or precede the TESTSET
+ * instruction with an SSYNC instruction. If preceding the TESTSET instruction
+ * by an SSYNC instruction, do the following:
+ *
+ * CLI R0
+ * R1 = [P0] // perform a dummy read to make sure CPLB is installed
+ * NOP
+ * NOP
+ * SSYNC
+ * TESTSET (P0)
+ * STI R0
+ *
+ * This problem impacts:
+ * BF561/6 - rev 0.0-0.5
+ *
+ */
+
+#define WA_05000412 \
+ (defined (__SILICON_REVISION__) && defined(__ADSPBF561__))
+
+
+/* 05-00-0428 - "Lost/Corrupted Write to L2 Memory Following Speculative Read
+ * by Core B from L2 Memory"
+ *
+ * This issue occurs only when the accesses are performed by core B of a BF561.
+ *
+ * When a write to internal L2 memory follows a speculative read from internal
+ * L2 memory, the L2 write may be lost or corrupted. For this anomaly to occur,
+ * the speculative read must be caused by a read in the shadow of a branch. The
+ * accesses do not have to be consecutive accesses. In other words, the problem
+ * can occur even if there are multiple instructions between the speculative
+ * read and the write, as shown in the following example:
+ *
+ * R1 = 1; R2 = 1;
+ * CC = R1 == R2;
+ * IF CC JUMP X; // Always true...
+ * R0 = [P0]; // If any of these three loads accesses L2 memory from Core
+ * R1 = [P1]; // B, speculative execution in the pipeline causes the
+ * R2 = [P2]; // anomaly trigger condition.
+ * X:
+ * ... // Any number of instructions...
+ * [P0] = R0; // This write can be corrupted or lost.
+ *
+ * The issue does not occur if the speculative read access is caused by an
+ * interrupt or exception.
+ *
+ * The workaround required depends upon the conditional branch instruction.
+ * If the evaluated condition is true and the branch is predicted, then the
+ * workaround is to ensure that the target instruction is not be a load
+ * instruction, for example:
+ *
+ * IF CC JUMP X (BP);
+ * ...
+ * X: <load that might be from L2 memory>
+ *
+ * If the evaluated condition is false and the branch is not predicted, then
+ * the workaround is to make sure that none of the three instructions that
+ * are executed after the conditional JUMP are load instructions, for example:
+ *
+ * IF CC JUMP ...;
+ * <load that might be from L2 memory>
+ * <load that might be from L2 memory>
+ * <load that might be from L2 memory>
+ *
+ * This problem impacts:
+ * BF561 - rev 0.4,0.5
+ *
+ */
+
+#define WA_05000428 \
+ (defined(__SILICON_REVISION__) && \
+ defined(__ADSPBF561__) && \
+ ((__SILICON_REVISION__ == 0xffff) || \
+ (__SILICON_REVISION__ == 0x4) || \
+ (__SILICON_REVISION__ == 0x5)))
+
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
*
* exception.h
*
- * Copyright (C) 2008 Analog Devices, Inc.
+ * Copyright (C) 2008, 2009 Analog Devices, Inc.
*
************************************************************************/
#ifdef _MISRA_RULES
#pragma diag(push)
+#pragma diag(suppress:misra_rule_5_6)
#pragma diag(suppress:misra_rule_5_7)
#pragma diag(suppress:misra_rule_6_3)
#pragma diag(suppress:misra_rule_19_4)
#define EX_HANDLER(KIND,NAME) \
_Pragma(#KIND) \
-void NAME ()
+void NAME (void)
#define EX_HANDLER_PROTO(KIND, NAME) EX_HANDLER(KIND, NAME)
* they apply.
*/
-/* This file must be used with compiler version 8.0.1.5 */
+/* This file must be used with compiler version 8.0.6.4 */
#ifdef __VERSIONNUM__
-#if __VERSIONNUM__ != 0x08000105
+#if __VERSIONNUM__ != 0x08000604
#error The compiler version does not match the version of the sysreg.h include
#endif
#endif
*
* sysreg.h
*
- * Copyright (C) 2008 Analog Devices, Inc.
+ * Copyright (C) 2008, 2009 Analog Devices, Inc.
*
***********************************************************************/
#pragma diag(push)
#pragma diag(suppress:misra_rule_2_4)
#pragma diag(suppress:misra_rule_6_3)
+#pragma diag(suppress:misra_rule_19_4)
+#pragma diag(suppress:misra_rule_19_7)
#pragma diag(suppress:misra_rule_19_10)
#endif /* _MISRA_RULES */
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