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disas/riscv Fix ctzw disassemble
author
Ivan Klokov
<ivan.klokov@syntacore.com>
Fri, 17 Feb 2023 15:14:59 +0000
(18:14 +0300)
committer
Palmer Dabbelt
<palmer@rivosinc.com>
Sun, 5 Mar 2023 20:43:38 +0000
(12:43 -0800)
Due to typo in opcode list, ctzw is disassembled as clzw instruction.
Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
Fixes:
02c1b569a15b
("disas/riscv: Add Zb[abcs] instructions")
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <
20230217151459
.54649-1-ivan.klokov@syntacore.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
disas/riscv.c
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diff --git
a/disas/riscv.c
b/disas/riscv.c
index
ddda687
..
54455aa
100644
(file)
--- a/
disas/riscv.c
+++ b/
disas/riscv.c
@@
-1645,7
+1645,7
@@
const rv_opcode_data opcode_data[] = {
{ "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "c
l
zw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "c
t
zw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "slli.uw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
{ "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },