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target/riscv: Allow specifying MMU stage
2020-02-27 Alistair Francistarget/riscv: Allow specifying MMU stage
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-02-27 Alistair Francistarget/riscv: Respect MPRV and SPRV for floating point ops
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-02-27 Alistair Francistarget/riscv: Mark both sstatus and msstatus_hs as...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-02-27 Alistair Francistarget/riscv: Disable guest FP support based on virtual...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-02-27 Alistair Francistarget/riscv: Only set TB flags with FP status if enabled
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-02-27 Alistair Francistarget/riscv: Remove the hret instruction
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-02-27 Alistair Francistarget/riscv: Add hfence instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-02-27 Alistair Francistarget/riscv: Add Hypervisor trap return support
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-02-27 Alistair Francistarget/riscv: Add hypvervisor trap support
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-02-27 Alistair Francistarget/riscv: Generate illegal instruction on WFI when V=1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-02-27 Alistair Francistarget/ricsv: Flush the TLB on virtulisation mode changes
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-02-27 Alistair Francistarget/riscv: Add support for virtual interrupt setting
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-02-27 Alistair Francistarget/riscv: Extend the SIP CSR to support virtulisation
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-02-27 Alistair Francistarget/riscv: Extend the MIE CSR to support virtulisation
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-02-27 Alistair Francistarget/riscv: Set VS bits in mideleg for Hyp extension
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-02-27 Alistair Francistarget/riscv: Add virtual register swapping function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-02-27 Alistair Francistarget/riscv: Add Hypervisor machine CSRs accesses
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-02-27 Alistair Francistarget/riscv: Add Hypervisor virtual CSRs accesses
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-02-27 Alistair Francistarget/riscv: Add Hypervisor CSR access functions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-02-27 Alistair Francistarget/riscv: Dump Hypervisor registers if enabled
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-02-27 Alistair Francistarget/riscv: Print priv and virt in disas log
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-02-27 Alistair Francistarget/riscv: Fix CSR perm checking for HS mode
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-02-27 Alistair Francistarget/riscv: Add the force HS exception mode
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-02-27 Alistair Francistarget/riscv: Add the virtulisation mode
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-02-27 Alistair Francistarget/riscv: Rename the H irqs to VS irqs
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-02-27 Alistair Francistarget/riscv: Add support for the new execption numbers
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-02-27 Alistair Francistarget/riscv: Add the Hypervisor CSRs to CPUState
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-02-27 Alistair Francistarget/riscv: Add the Hypervisor extension
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-02-27 Alistair Francistarget/riscv: Convert MIP CSR to target_ulong
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-01-17 Alistair Francishw/arm: Add the Netduino Plus 2
Signed-off-by: Alistair Francis <alistair@alistair23.me>
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2020-01-17 Alistair Francishw/arm: Add the STM32F4xx SoC
Signed-off-by: Alistair Francis <alistair@alistair23.me>
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2020-01-17 Alistair Francishw/misc: Add the STM32F4xx EXTI device
Signed-off-by: Alistair Francis <alistair@alistair23.me>
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2020-01-17 Alistair Francishw/misc: Add the STM32F4xx Sysconfig device
Signed-off-by: Alistair Francis <alistair@alistair23.me>
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2019-11-14 Alistair Francisriscv/virt: Increase flash size
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-11-14 Alistair Francisopensbi: Upgrade from v0.4 to v0.5
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-11-14 Alistair Francistarget/riscv: Remove atomic accesses to MIP CSR
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-10-28 Alistair Francisriscv/boot: Fix possible memory leak
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-10-28 Alistair Francisriscv/virt: Jump to pflash if specified
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-10-28 Alistair Francisriscv/virt: Add the PFlash CFI01 device
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-10-28 Alistair Francisriscv/virt: Manually define the machine
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-10-28 Alistair Francisriscv/sifive_u: Add the start-in-flash property
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-10-28 Alistair Francisriscv/sifive_u: Manually define the machine
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-10-28 Alistair Francisriscv/sifive_u: Add QSPI memory region
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-10-28 Alistair Francisriscv/sifive_u: Add L2-LIM cache memory
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-09-17 Alistair Francistarget/riscv: Use TB_FLAGS_MSTATUS_FS for floating...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-09-17 Alistair Francistarget/riscv: Fix mstatus dirty mask
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-09-17 Alistair Francistarget/riscv: Update the Hypervisor CSRs to v0.4
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-09-17 Alistair Francistarget/riscv: Create function to test if FP is enabled
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-09-17 Alistair Francisriscv: plic: Remove unused interrupt functions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-07-26 Alistair Francisriscv/boot: Fixup the RISC-V firmware warning
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-07-18 Alistair Francishw/riscv: Load OpenSBI as the default firmware
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-07-18 Alistair Francisroms: Add OpenSBI version 0.4
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-07-09 Alistair Francistcg/riscv: Fix RISC-VH host build failure
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-06-27 Alistair Francishw/riscv: Extend the kernel loading support
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-06-27 Alistair Francishw/riscv: Add support for loading a firmware
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-06-27 Alistair Francishw/riscv: Split out the boot functions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-06-25 Alistair Francistarget/riscv: Add support for disabling/enabling Counters
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-06-25 Alistair Francistarget/riscv: Remove user version information
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-06-25 Alistair Francistarget/riscv: Require either I or E base extension
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-06-25 Alistair Francisqemu-deprecated.texi: Deprecate the RISC-V privledge...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-06-25 Alistair Francistarget/riscv: Set privledge spec 1.11.0 as default
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-06-25 Alistair Francistarget/riscv: Add the mcountinhibit CSR
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-06-24 Alistair Francistarget/riscv: Add the privledge spec version 1.11.0
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-06-24 Alistair Francistarget/riscv: Restructure deprecatd CPUs
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-06-24 Alistair Francistarget/riscv: Allow setting ISA extensions via CPU...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-24 Alistair Francistarget/riscv: Add the HGATP register masks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-24 Alistair Francistarget/riscv: Add the HSTATUS register masks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-24 Alistair Francistarget/riscv: Add Hypervisor CSR macros
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-24 Alistair Francistarget/riscv: Allow setting mstatus virtulisation bits
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-24 Alistair Francistarget/riscv: Add the MPV and MTL mstatus bits
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-24 Alistair Francistarget/riscv: Improve the scause logic
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-24 Alistair Francistarget/riscv: Trigger interrupt on MIP update asynchronously
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-24 Alistair Francistarget/riscv: Mark privilege level 2 as reserved
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-24 Alistair Francisriscv: spike: Add a generic spike machine
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-24 Alistair Francistarget/riscv: Deprecate the generic no MMU CPUs
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-24 Alistair Francistarget/riscv: Add a base 32 and 64 bit CPU
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-24 Alistair Francistarget/riscv: Create settable CPU properties
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-24 Alistair Francisriscv: virt: Allow specifying a CPU via commandline
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-24 Alistair Francislinux-user/riscv: Add the CPU type as a comment
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-23 Alistair Francistarget/arm: Fix vector operation segfault
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-09 Alistair Francislinux-user/elfload: Fix GCC 9 build warnings
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-04-04 Alistair Francisriscv: plic: Log guest errors
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-04-04 Alistair Francisriscv: plic: Fix incorrect irq calculation
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-03-27 Alistair FrancisMAINTAINERS: Update the device tree maintainers
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-03-19 Alistair Francistarget/riscv: Remove unused struct
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-03-19 Alistair Francisriscv: sifive_u: Allow up to 4 CPUs to be created
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-03-19 Alistair Francisriscv: pmp: Log pmp access errors as guest errors
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-03-18 Alistair Francisriscv: plic: Set msi_nonbroken as true
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-02-11 Alistair Francisriscv: Ensure the kernel start address is correctly...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-02-11 Alistair FrancisRISC-V: Add priv_ver to DisasContext
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-01-10 Alistair Francisdefault-configs: Enable USB support for RISC-V machines
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2018-12-25 Alistair Francisconfigure: Add support for building RISC-V host
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2018-12-25 Alistair Francisdisas: Add RISC-V support
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2018-12-25 Alistair Francistcg: Add RISC-V cpu signal handler
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2018-12-25 Alistair Francistcg/riscv: Add the target init code
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2018-12-25 Alistair Francistcg/riscv: Add the prologue generation and register...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2018-12-25 Alistair Francistcg/riscv: Add the out op decoder
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2018-12-25 Alistair Francistcg/riscv: Add direct load and store instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2018-12-25 Alistair Francistcg/riscv: Add slowpath load and store instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2018-12-25 Alistair Francistcg/riscv: Add branch and jump instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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