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| 2023-11-22 | Román Cárdenas | riscv: Fix SiFive E CLINT clock frequency Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-22 | Clément Chigot | target/riscv: don't verify ISA compatibility for zicntr... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-22 | Daniel Henrique... | hw/riscv/virt.c: do create_fdt() earlier, add finalize_fdt() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-22 | Palmer Dabbelt | linux-user/riscv: Add Zicboz block size to hwprobe Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Rob Bradford | docs/about/deprecated: Document RISC-V "pmu-num" deprecation Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Rob Bradford | target/riscv: Add "pmu-mask" property to replace "pmu... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Rob Bradford | target/riscv: Use existing PMU counter mask in FDT... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Rob Bradford | target/riscv: Don't assume PMU counters are continuous Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Rob Bradford | target/riscv: Propagate error from PMU setup Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Alistair Francis | target/riscv: cpu: Set the OpenTitan priv to 1.12.0 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...ID: <20231102003424.2003428-3-alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Alistair Francis | hw/ssi: ibex_spi_host: Clear the interrupt even if... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...ID: <20231102003424.2003428-2-alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Max Chou | disas/riscv: Replace TABs with space Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Max Chou | disas/riscv: Add support for vector crypto extensions Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Max Chou | disas/riscv: Add rv_codec_vror_vi for vror.vi Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Max Chou | disas/riscv: Add rv_fmt_vd_vs2_uimm format Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Max Chou | target/riscv: Move vector crypto extensions to riscv_cpu_ext... Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Max Chou | target/riscv: Expose Zvks[c|g] extnesion properties Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Max Chou | target/riscv: Add cfg properties for Zvks[c|g] extensions Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Max Chou | target/riscv: Expose Zvkn[c|g] extnesion properties Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Max Chou | target/riscv: Add cfg properties for Zvkn[c|g] extensions Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Max Chou | target/riscv: Expose Zvkb extension property Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Max Chou | target/riscv: Replace Zvbb checking by Zvkb Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Max Chou | target/riscv: Add cfg property for Zvkb extension Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Max Chou | target/riscv: Expose Zvkt extension property Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Max Chou | target/riscv: Add cfg property for Zvkt extension Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Weiwei Li | MAINTAINERS: update mail address for Weiwei Li Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Heinrich Schuchardt | target/riscv: correct csr_ops[CSR_MSECCFG] Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Daniel Henrique... | target/riscv/kvm: add zicsr, zifencei, zba, zbs, svnapot Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Daniel Henrique... | target/riscv/kvm: add zihpm reg Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Daniel Henrique... | target/riscv: add zihpm extension flag for TCG Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Daniel Henrique... | target/riscv/kvm: add zicntr reg Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Daniel Henrique... | target/riscv: add zicntr extension flag for TCG Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Mayuresh Chitale | target/riscv: pmp: Ignore writes when RW=01 Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Mayuresh Chitale | target/riscv: pmp: Clear pmp/smepmp bits on reset Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Himanshu Chauhan | Add epmp to extensions list and rename it to smepmp Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Daniel Henrique... | target/riscv/riscv-qmp-cmds.c: check CPU accel in query... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Daniel Henrique... | target/riscv: add riscv_cpu_accelerator_compatible() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Daniel Henrique... | target/riscv: handle custom props in qmp_query_cpu_model_exp... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Daniel Henrique... | target/riscv/tcg: add tcg_cpu_finalize_features() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Daniel Henrique... | qapi,risc-v: add query-cpu-model-expansion Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Daniel Henrique... | target/riscv/kvm/kvm-cpu.c: add missing property getters() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Daniel Henrique... | docs/system/riscv: update 'virt' machine core limit Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Daniel Henrique... | linux-user/riscv: change default cpu to 'max' Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Rajnesh Kanwal | target/riscv: Add HS-mode virtual interrupt and IRQ... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Rajnesh Kanwal | target/riscv: Add M-mode virtual interrupt and IRQ... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Rajnesh Kanwal | target/riscv: Split interrupt logic from riscv_cpu_update_mip. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Rajnesh Kanwal | target/riscv: Set VS* bits to one in mideleg when H... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Rajnesh Kanwal | target/riscv: Check for async flag in case of RISCV_EXCP_SEM... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Rajnesh Kanwal | target/riscv: Without H-mode mask all HS mode inturrupts... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Daniel Henrique... | target/riscv: rename ext_icboz to ext_zicboz Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Daniel Henrique... | target/riscv: rename ext_icbom to ext_zicbom Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Daniel Henrique... | target/riscv: rename ext_icsr to ext_zicsr Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-11-07 | Daniel Henrique... | target/riscv: rename ext_ifencei to ext_zifencei Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Max Chou | target/riscv: Fix vfwmaccbf16.vf Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv: deprecate capital 'Z' CPU properties Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Richard W.M. Jones | target/riscv: Use env_archcpu for better performance Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv/tcg: remove RVG warning Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv/kvm: support KVM_GET_REG_LIST Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv/kvm: improve 'init_multiext_cfg' error msg Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Clément Chigot | gdbstub: replace exit calls with proper shutdown for... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Clément Chigot | hw/char: riscv_htif: replace exit calls with proper... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Clément Chigot | hw/misc/sifive_test.c: replace exit calls with proper... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Clément Chigot | softmmu: pass the main loop status to gdb "Wxx" packet Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Clément Chigot | softmmu: add means to pass an exit code when requesting... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv/tcg-cpu.c: add extension properties for... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv: add riscv_cpu_get_name() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv/cpu: move priv spec functions to tcg-cpu.c Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv/cpu.c: export isa_edata_arr[] Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv/tcg: move riscv_cpu_add_misa_properties... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv/cpu.c: make misa_ext_cfgs[] 'const' Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv/tcg: introduce tcg_cpu_instance_init() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv/cpu.c: export set_misa() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv/kvm: do not use riscv_cpu_add_misa_properties() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv: move KVM only files to kvm subdir Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv: introduce KVM AccelCPUClass Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv: remove kvm-stub.c Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv: make riscv_add_satp_mode_properties(... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv: move riscv_cpu_add_kvm_properties() to... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv/cpu.c: mark extensions arrays as 'const' Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv: move 'host' CPU declaration to kvm.c Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv/cpu.c: add .instance_post_init() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv: move riscv_tcg_ops to tcg-cpu.c Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv: move riscv_cpu_validate_set_extensions... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv: move riscv_cpu_realize_tcg() to TCG:... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv: introduce TCG AccelCPUClass Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Alvin Chang | disas/riscv: Fix the typo of inverted order of pmpaddr13... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | liguang.zhang | target/riscv: Clear CSR values at reset and sync MPSTATE... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv/cpu.c: consider user option with RVG Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_up... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv: use isa_ext_update_enabled() in init_max_cpu_e... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv: make CPUCFG() macro public Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv/cpu.c: use offset in isa_ext_is_enabled... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv: deprecate the 'any' CPU type Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | avocado, risc-v: add tuxboot tests for 'max' CPU Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv: add 'max' CPU type Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv/cpu.c: limit cfg->vext_spec log message Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-10-12 | Daniel Henrique... | target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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