2023-11-22 | Ivan Klokov | target/riscv/cpu_helper.c: Fix mxr bit behavior Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> |
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2023-11-22 | Ivan Klokov | target/riscv/cpu_helper.c: Invalid exception on MMU... Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> |
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2023-07-10 | Ivan Klokov | target/riscv: Add RVV registers to log Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> |
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2023-06-13 | Ivan Klokov | util/log: Add vector registers to log Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> |
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2023-05-05 | Ivan Klokov | hw/intc/riscv_aplic: Zero init APLIC internal state Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> |
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2023-03-14 | Ivan Klokov | disas/riscv: Fix slli_uw decoding Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> |
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2023-03-05 | Ivan Klokov | disas/riscv Fix ctzw disassemble Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> |
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