Documentation/devicetree/bindings/gpu/adreno.txt

   1 Qualcomm GPU
   2
   3 Qualcomm Adreno GPU
   4
   5 Required properties:
   6 - label:                A string used as a descriptive name for the device.
   7 - compatible:           Must be "qcom,kgsl-3d0" and "qcom,kgsl-3d"
   8 - reg:                  Specifies the register base address and size. The second interval
   9                         specifies the shader memory base address and size.
  10 - reg-names:            Resource names used for the physical address of device registers
  11                         and shader memory. "kgsl_3d0_reg_memory" gives the physical address
  12                         and length of device registers while "kgsl_3d0_shader_memory" gives
  13                         physical address and length of device shader memory.  If
  14                         specified, "qfprom_memory" gives the range for the efuse
  15                         registers used for various configuration options.
  16 - interrupts:           Interrupt mapping for GPU IRQ.
  17 - interrupt-names:      String property to describe the name of the interrupt.
  18 - qcom,id:              An integer used as an identification number for the device.
  19 - qcom,gpu-bimc-interface-clk-freq:
  20                         GPU-BIMC interface clock needs to be set to this value for
  21                         targets where B/W requirements does not meet GPU Turbo use cases.
  22 - clocks:               List of phandle and clock specifier pairs, one pair
  23                         for each clock input to the device.
  24 - clock-names:          List of clock input name strings sorted in the same
  25                         order as the clocks property.
  26                                 Current values of clock-names are:
  27                                 "src_clk", "core_clk", "iface_clk", "mem_clk", "mem_iface_clk",
  28                                 "alt_mem_iface_clk", "rbbmtimer_clk",  "alwayson_clk",
  29                                 "iref_clk"
  30                                 "core_clk" and "iface_clk" are required and others are optional
  31
  32 - qcom,base-leakage-coefficient: Dynamic leakage coefficient.
  33 - qcom,lm-limit:        Current limit for GPU limit management.
  34 - qcom,isense-clk-on-level: below or equal this power level isense clock is at XO rate,
  35                                 above this powerlevel isense clock is at working frequency.
  36
  37 Bus Scaling Data:
  38 - qcom,msm-bus,name: String property to describe the name of the 3D graphics processor.
  39 - qcom,msm-bus,num-cases: This is the the number of Bus Scaling use cases defined in the vectors property.
  40 - qcom,msm-bus,active-only: A boolean flag indicating if it is active only.
  41 - qcom,msm-bus,num-paths: This represents the number of paths in each Bus Scaling Usecase.
  42 - qcom,msm-bus,vectors-KBps: A series of 4 cell properties, format of which is:
  43                                                 <src dst ab ib>, <src dst ab ib>, // For Bus Scaling Usecase 1
  44                                                 <src dst ab ib>, <src dst ab ib>, // For Bus Scaling Usecase 2
  45                                                 <..  ..  .. ..>, <..  ..  .. ..>; // For Bus Scaling Usecase n
  46                                                 This property is a series of all vectors for all Bus Scaling Usecases.
  47                                                 Each set of vectors for each usecase describes bandwidth votes for a combination
  48                                                 of src/dst ports.  The driver will set the desired use case based on the selected
  49                                                 power level and the desired bandwidth vote will be registered for the port pairs.
  50                                         Current values of src are:
  51                                                 0 = MSM_BUS_MASTER_GRAPHICS_3D
  52                                                 1 = MSM_BUS_MASTER_GRAPHICS_3D_PORT1
  53                                                 2 = MSM_BUS_MASTER_V_OCMEM_GFX3D
  54                                         Current values of dst are:
  55                                                 0 = MSM_BUS_SLAVE_EBI_CH0
  56                                                 1 = MSM_BUS_SLAVE_OCMEM
  57                                         ab: Represents aggregated bandwidth. This value is 0 for Graphics.
  58                                         ib: Represents instantaneous bandwidth. This value has a range <0 8000 MB/s>
  59
  60 - qcom,ocmem-bus-client: Container for another set of bus scaling properties
  61                                                 qcom,msm-bus,name
  62                                                 qcom,msm-bus,num-cases
  63                                                 qcom,msm-bus,num-paths
  64                                                 qcom,msm-bus,vectors-KBps
  65                         to be used by ocmem msm bus scaling client.
  66
  67 GDSC Oxili Regulators:
  68 - regulator-names:              List of regulator name strings sorted in power-on order
  69 - vddcx-supply:                 Phandle for vddcx regulator device node.
  70 - vdd-supply:                   Phandle for vdd regulator device node.
  71
  72 IOMMU Data:
  73 - iommu:                        Phandle for the KGSL IOMMU device node
  74
  75 GPU Power levels:
  76 - qcom,gpu-pwrlevel-bins:       Container for sets of GPU power levels (see
  77                                 adreno-pwrlevels.txt)
  78
  79 DCVS Core info
  80 - qcom,dcvs-core-info           Container for the DCVS core info (see
  81                                 dcvs-core-info.txt)
  82
  83 Optional Properties:
  84 - qcom,initial-powerlevel: This value indicates which qcom,gpu-pwrlevel should be used at start time
  85                            and when coming back out of resume
  86 - qcom,bus-control:        Boolean. Enables an independent bus vote from the gpu frequency
  87 - qcom,bus-width:          Bus width in number of bytes. This enables dynamic AB bus voting based on
  88                            bus width and actual bus transactions.
  89 - qcom,gpubw-dev:          a phandle to a device representing bus bandwidth requirements
  90                            (see devdw.txt)
  91 - qcom,idle-timeout:       This property represents the time in milliseconds for idle timeout.
  92 - qcom,no-nap:             If it exists software clockgating will be disabled at boot time.
  93 - qcom,chipid:             If it exists this property is used to replace
  94                            the chip identification read from the GPU hardware.
  95                            This is used to override faulty hardware readings.
  96 - qcom,disable-wake-on-touch:   Boolean. Disables the GPU power up on a touch input event.
  97 - qcom,disable-busy-time-burst:
  98                                 Boolean. Disables the busy time burst to avoid switching
  99                                 of power level for large frames based on the busy time limit.
 100
 101 - qcom,pm-qos-active-latency:
 102                                 Right after GPU wakes up from sleep, driver votes for
 103                                 acceptable maximum latency to the pm-qos driver. This
 104                                 voting demands that the system can not go into any
 105                                 power save state *if* the latency to bring system back
 106                                 into active state is more than this value.
 107                                 Value is in microseconds.
 108 - qcom,pm-qos-wakeup-latency:
 109                                 Similar to the above. Driver votes against deep low
 110                                 power modes right before GPU wakes up from sleep.
 111 - qcom,l2pc-cpu-mask-latency:
 112                                 The CPU mask latency in microseconds to avoid L2PC
 113                                 on masked CPUs.
 114
 115 - qcom,gpu-cx-ipeak:
 116                                 To handle Cx peak current limit.
 117                                 <phandle bit>
 118                                 phandle - phandle of cx ipeak device node
 119                                 bit     - bit number of client in relevant register
 120 - qcom,gpu-cx-ipeak-clk:
 121                                 GPU clock threshold for Cx Ipeak voting. KGSL votes
 122                                 to Cx Ipeak driver when GPU clock crosses this threshold.
 123                                 Cx Ipeak can limit peak current based on voting from other clients.
 124
 125 - qcom,force-32bit:
 126                                 Force the GPU to use 32 bit data sizes even if
 127                                 it is capable of doing 64 bit.
 128
 129 - qcom,gpu-speed-bin:      GPU speed bin information in the format
 130                            <offset mask shift>
 131                                 offset - offset of the efuse register from the base.
 132                                 mask   - mask for the relevant bits in the efuse register.
 133                                 shift  - number of bits to right shift to get the speed bin
 134                                 value.
 135 - qcom,highest-bank-bit:
 136                                 Specify the bit of the highest DDR bank. This
 137                                 is programmed into protected registers and also
 138                                 passed to the user as a property.
 139
 140 - qcom,l2pc-cpu-mask:
 141                                 Disables L2PC on masked CPUs when any of Graphics
 142                                 rendering thread is running on masked CPUs.
 143                                 Bit 0 is for CPU-0, bit 1 is for CPU-1...
 144
 145 - qcom,l2pc-update-queue:
 146                                 Disables L2PC on masked CPUs at queue time when it's true.
 147
 148 - qcom,snapshot-size:
 149                                 Specify the size of snapshot in bytes. This will override
 150                                 snapshot size defined in the driver code.
 151
 152 - qcom,gpu-qdss-stm:
 153                                 <baseAddr size>
 154                                 baseAddr - base address of the gpu channels in the qdss stm memory region
 155                                 size     - size of the gpu stm region
 156
 157 - qcom,gpu-qtimer:
 158                                 <baseAddr size>
 159                                 baseAddr - base address of the qtimer memory region
 160                                 size     - size of the qtimer region
 161
 162 - qcom,tsens-name:
 163                                 Specify the name of GPU temperature sensor. This name will be used
 164                                 to get the temperature from the thermal driver API.
 165
 166 - qcom,enable-midframe-timer:
 167                                 Boolean. Enables the use of midframe sampling timer. This timer
 168                                 samples the GPU powerstats if the cmdbatch expiry takes longer than
 169                                 the threshold set by KGSL_GOVERNOR_CALL_INTERVAL. Enable only if
 170                                 target has NAP state enabled.
 171
 172 GPU Quirks:
 173 - qcom,gpu-quirk-two-pass-use-wfi:
 174                                 Signal the GPU to set Set TWOPASSUSEWFI bit in
 175                                 A5XX_PC_DBG_ECO_CNTL (5XX only)
 176 - qcom,gpu-quirk-critical-packets:
 177                                 Submit a set of critical PM4 packets when the GPU wakes up
 178 - qcom,gpu-quirk-fault-detect-mask:
 179                                 Mask out RB1-3 activity signals from HW hang
 180                                 detection logic
 181 - qcom,gpu-quirk-dp2clockgating-disable:
 182                                 Disable RB sampler data path clock gating optimization
 183 - qcom,gpu-quirk-lmloadkill-disable:
 184                                 Use register setting to disable local memory(LM) feature
 185                                 to avoid corner case error
 186
 187 KGSL Memory Pools:
 188 - qcom,gpu-mempools:            Container for sets of GPU mempools.Multiple sets
 189                                 (pools) can be defined within qcom,gpu-mempools.
 190                                 Each mempool defines a pool order, reserved pages,
 191                                 allocation allowed.
 192 Properties:
 193 - compatible:                   Must be qcom,gpu-mempools.
 194 - qcom,mempool-max-pages:       Max pages for all mempools, If not defined there is no limit.
 195 - qcom,gpu-mempool:             Defines a set of mempools.
 196
 197 Properties:
 198 - reg:                          Index of the pool (0 = lowest pool order).
 199 - qcom,mempool-page-size:       Size of page.
 200 - qcom,mempool-reserved:        Number of pages reserved at init time for a pool.
 201 - qcom,mempool-allocate:        Allocate memory from the system memory when the
 202                                 reserved pool exhausted.
 203
 204 The following properties are optional as collecting data via coresight might
 205 not be supported for every chipset. The documentation for coresight
 206 properties can be found in:
 207 Documentation/devicetree/bindings/coresight/coresight.txt
 208
 209 - coresight-id           Unique integer identifier for the bus.
 210 - coresight-name         Unique descriptive name of the bus.
 211 - coresight-nr-inports   Number of input ports on the bus.
 212 - coresight-outports     List of output port numbers on the bus.
 213 - coresight-child-list   List of phandles pointing to the children of this
 214                          component.
 215 - coresight-child-ports  List of input port numbers of the children.
 216 - coresight-atid         The unique ATID value of the coresight device
 217
 218 Example of A330 GPU in MSM8916:
 219
 220 &soc {
 221         msm_gpu: qcom,kgsl-3d0@01c00000 {
 222                 label = "kgsl-3d0";
 223                 compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
 224                 reg = <0x01c00000 0x10000
 225                        0x01c20000 0x20000>;
 226                 reg-names = "kgsl_3d0_reg_memory" , "kgsl_3d0_shader_memory";
 227                 interrupts = <0 33 0>;
 228                 interrupt-names = "kgsl_3d0_irq";
 229                 qcom,id = <0>;
 230
 231                 qcom,chipid = <0x03000600>;
 232
 233                 qcom,initial-pwrlevel = <1>;
 234
 235                 /* Idle Timeout = HZ/12 */
 236                 qcom,idle-timeout = <8>;
 237                 qcom,strtstp-sleepwake;
 238
 239                 clocks = <&clock_gcc clk_gcc_oxili_gfx3d_clk>,
 240                         <&clock_gcc clk_gcc_oxili_ahb_clk>,
 241                         <&clock_gcc clk_gcc_oxili_gmem_clk>,
 242                         <&clock_gcc clk_gcc_bimc_gfx_clk>,
 243                         <&clock_gcc clk_gcc_bimc_gpu_clk>;
 244                 clock-names = "core_clk", "iface_clk", "mem_clk",
 245                                 "mem_iface_clk", "alt_mem_iface_clk";
 246
 247                 /* Bus Scale Settings */
 248                 qcom,msm-bus,name = "grp3d";
 249                 qcom,msm-bus,num-cases = <4>;
 250                 qcom,msm-bus,num-paths = <1>;
 251                 qcom,msm-bus,vectors-KBps =
 252                         <26 512 0 0>,
 253                         <26 512 0 1600000>,
 254                         <26 512 0 3200000>,
 255                         <26 512 0 4264000>;
 256
 257                 /* GDSC oxili regulators */
 258                 vdd-supply = <&gdsc_oxili_gx>;
 259
 260                 /* IOMMU Data */
 261                 iommu = <&gfx_iommu>;
 262
 263                 /* Trace bus */
 264                 coresight-id = <67>;
 265                 coresight-name = "coresight-gfx";
 266                 coresight-nr-inports = <0>;
 267                 coresight-outports = <0>;
 268                 coresight-child-list = <&funnel_in0>;
 269                 coresight-child-ports = <5>;
 270
 271                 /* GPU Mempools */
 272                 qcom,gpu-mempools {
 273                         #address-cells= <1>;
 274                         #size-cells = <0>;
 275                         compatible = "qcom,gpu-mempools";
 276
 277                         /* 4K Page Pool configuration */
 278                         qcom,gpu-mempool@0 {
 279                                 reg = <0>;
 280                                 qcom,mempool-page-size = <4096>;
 281                                 qcom,mempool-reserved = <2048>;
 282                                 qcom,mempool-allocate;
 283                         };
 284                         /* 8K Page Pool configuration */
 285                         qcom,gpu-mempool@1 {
 286                                 reg = <1>;
 287                                 qcom,mempool-page-size  = <8192>;
 288                                 qcom,mempool-reserved = <1024>;
 289                                 qcom,mempool-allocate;
 290                         };
 291                         /* 64K Page Pool configuration */
 292                         qcom,gpu-mempool@2 {
 293                                 reg = <2>;
 294                                 qcom,mempool-page-size  = <65536>;
 295                                 qcom,mempool-reserved = <256>;
 296                         };
 297                         /* 1M Page Pool configuration */
 298                         qcom,gpu-mempool@3 {
 299                                 reg = <3>;
 300                                 qcom,mempool-page-size  = <1048576>;
 301                                 qcom,mempool-reserved = <32>;
 302                         };
 303                 };
 304
 305                 /* Power levels */
 306                 qcom,gpu-pwrlevels-bins {
 307                         #address-cells = <1>;
 308                         #size-cells = <0>;
 309
 310                         qcom,gpu-pwrlevels-0 {
 311                                 #address-cells = <1>;
 312                                 #size-cells = <0>;
 313
 314                                 qcom,speed-bin = <0>;
 315
 316                                 qcom,gpu-pwrlevel@0 {
 317                                         reg = <0>;
 318                                         qcom,gpu-freq = <400000000>;
 319                                         qcom,bus-freq = <3>;
 320                                         qcom,io-fraction = <33>;
 321                                 };
 322
 323                                 qcom,gpu-pwrlevel@1 {
 324                                         reg = <1>;
 325                                         qcom,gpu-freq = <310000000>;
 326                                         qcom,bus-freq = <2>;
 327                                         qcom,io-fraction = <66>;
 328                                 };
 329
 330                                 qcom,gpu-pwrlevel@2 {
 331                                         reg = <2>;
 332                                         qcom,gpu-freq = <200000000>;
 333                                         qcom,bus-freq = <1>;
 334                                         qcom,io-fraction = <100>;
 335                                 };
 336
 337                                 qcom,gpu-pwrlevel@3 {
 338                                         reg = <3>;
 339                                         qcom,gpu-freq = <27000000>;
 340                                         qcom,bus-freq = <0>;
 341                                         qcom,io-fraction = <0>;
 342                                 };
 343                         };
 344                 };
 345
 346         };
 347 };