arch/arc/boot/dts/axs10x_mb.dtsi

   1 /*
   2  * Support for peripherals on the AXS10x mainboard
   3  *
   4  * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 / {
  12         axs10x_mb {
  13                 compatible = "simple-bus";
  14                 #address-cells = <1>;
  15                 #size-cells = <1>;
  16                 ranges = <0x00000000 0xe0000000 0x10000000>;
  17                 interrupt-parent = <&mb_intc>;
  18
  19                 clocks {
  20                         i2cclk: i2cclk {
  21                                 compatible = "fixed-clock";
  22                                 clock-frequency = <50000000>;
  23                                 #clock-cells = <0>;
  24                         };
  25
  26                         apbclk: apbclk {
  27                                 compatible = "fixed-clock";
  28                                 clock-frequency = <50000000>;
  29                                 #clock-cells = <0>;
  30                         };
  31
  32                         mmcclk: mmcclk {
  33                                 compatible = "fixed-clock";
  34                                 clock-frequency = <50000000>;
  35                                 #clock-cells = <0>;
  36                         };
  37                 };
  38
  39                 ethernet@0x18000 {
  40                         #interrupt-cells = <1>;
  41                         compatible = "snps,dwmac";
  42                         reg = < 0x18000 0x2000 >;
  43                         interrupts = < 4 >;
  44                         interrupt-names = "macirq";
  45                         phy-mode = "rgmii";
  46                         snps,pbl = < 32 >;
  47                         snps,multicast-filter-bins = <256>;
  48                         clocks = <&apbclk>;
  49                         clock-names = "stmmaceth";
  50                         max-speed = <100>;
  51                 };
  52
  53                 ehci@0x40000 {
  54                         compatible = "generic-ehci";
  55                         reg = < 0x40000 0x100 >;
  56                         interrupts = < 8 >;
  57                 };
  58
  59                 ohci@0x60000 {
  60                         compatible = "generic-ohci";
  61                         reg = < 0x60000 0x100 >;
  62                         interrupts = < 8 >;
  63                 };
  64
  65                 /*
  66                  * According to DW Mobile Storage databook it is required
  67                  * to use  "Hold Register" if card is enumerated in SDR12 or
  68                  * SDR25 modes.
  69                  *
  70                  * Utilization of "Hold Register" is already implemented via
  71                  * dw_mci_pltfm_prepare_command() which in its turn gets
  72                  * used through dw_mci_drv_data->prepare_command call-back.
  73                  * This call-back is used in Altera Socfpga platform and so
  74                  * we may reuse it saying that we're compatible with their
  75                  * "altr,socfpga-dw-mshc".
  76                  *
  77                  * Most probably "Hold Register" utilization is platform-
  78                  * independent requirement which means that single unified
  79                  * "snps,dw-mshc" should be enough for all users of DW MMC once
  80                  * dw_mci_pltfm_prepare_command() is used in generic platform
  81                  * code.
  82                  */
  83                 mmc@0x15000 {
  84                         compatible = "altr,socfpga-dw-mshc";
  85                         reg = < 0x15000 0x400 >;
  86                         num-slots = < 1 >;
  87                         fifo-depth = < 16 >;
  88                         card-detect-delay = < 200 >;
  89                         clocks = <&apbclk>, <&mmcclk>;
  90                         clock-names = "biu", "ciu";
  91                         interrupts = < 7 >;
  92                         bus-width = < 4 >;
  93                 };
  94
  95                 uart@0x20000 {
  96                         compatible = "snps,dw-apb-uart";
  97                         reg = <0x20000 0x100>;
  98                         clock-frequency = <33333333>;
  99                         interrupts = <17>;
 100                         baud = <115200>;
 101                         reg-shift = <2>;
 102                         reg-io-width = <4>;
 103                 };
 104
 105                 uart@0x21000 {
 106                         compatible = "snps,dw-apb-uart";
 107                         reg = <0x21000 0x100>;
 108                         clock-frequency = <33333333>;
 109                         interrupts = <18>;
 110                         baud = <115200>;
 111                         reg-shift = <2>;
 112                         reg-io-width = <4>;
 113                 };
 114
 115                 /* UART muxed with USB data port (ttyS3) */
 116                 uart@0x22000 {
 117                         compatible = "snps,dw-apb-uart";
 118                         reg = <0x22000 0x100>;
 119                         clock-frequency = <33333333>;
 120                         interrupts = <19>;
 121                         baud = <115200>;
 122                         reg-shift = <2>;
 123                         reg-io-width = <4>;
 124                 };
 125
 126                 i2c@0x1d000 {
 127                         compatible = "snps,designware-i2c";
 128                         reg = <0x1d000 0x100>;
 129                         clock-frequency = <400000>;
 130                         clocks = <&i2cclk>;
 131                         interrupts = <14>;
 132                 };
 133
 134                 i2c@0x1e000 {
 135                         compatible = "snps,designware-i2c";
 136                         reg = <0x1e000 0x100>;
 137                         clock-frequency = <400000>;
 138                         clocks = <&i2cclk>;
 139                         interrupts = <15>;
 140                 };
 141
 142                 i2c@0x1f000 {
 143                         compatible = "snps,designware-i2c";
 144                         #address-cells = <1>;
 145                         #size-cells = <0>;
 146                         reg = <0x1f000 0x100>;
 147                         clock-frequency = <400000>;
 148                         clocks = <&i2cclk>;
 149                         interrupts = <16>;
 150
 151                         eeprom@0x54{
 152                                 compatible = "24c01";
 153                                 reg = <0x54>;
 154                                 pagesize = <0x8>;
 155                         };
 156
 157                         eeprom@0x57{
 158                                 compatible = "24c04";
 159                                 reg = <0x57>;
 160                                 pagesize = <0x8>;
 161                         };
 162                 };
 163
 164                 gpio0:gpio@13000 {
 165                         compatible = "snps,dw-apb-gpio";
 166                         reg = <0x13000 0x1000>;
 167                         #address-cells = <1>;
 168                         #size-cells = <0>;
 169
 170                         gpio0_banka: gpio-controller@0 {
 171                                 compatible = "snps,dw-apb-gpio-port";
 172                                 gpio-controller;
 173                                 #gpio-cells = <2>;
 174                                 snps,nr-gpios = <32>;
 175                                 reg = <0>;
 176                         };
 177
 178                         gpio0_bankb: gpio-controller@1 {
 179                                 compatible = "snps,dw-apb-gpio-port";
 180                                 gpio-controller;
 181                                 #gpio-cells = <2>;
 182                                 snps,nr-gpios = <8>;
 183                                 reg = <1>;
 184                         };
 185
 186                         gpio0_bankc: gpio-controller@2 {
 187                                 compatible = "snps,dw-apb-gpio-port";
 188                                 gpio-controller;
 189                                 #gpio-cells = <2>;
 190                                 snps,nr-gpios = <8>;
 191                                 reg = <2>;
 192                         };
 193                 };
 194
 195                 gpio1:gpio@14000 {
 196                         compatible = "snps,dw-apb-gpio";
 197                         reg = <0x14000 0x1000>;
 198                         #address-cells = <1>;
 199                         #size-cells = <0>;
 200
 201                         gpio1_banka: gpio-controller@0 {
 202                                 compatible = "snps,dw-apb-gpio-port";
 203                                 gpio-controller;
 204                                 #gpio-cells = <2>;
 205                                 snps,nr-gpios = <30>;
 206                                 reg = <0>;
 207                         };
 208
 209                         gpio1_bankb: gpio-controller@1 {
 210                                 compatible = "snps,dw-apb-gpio-port";
 211                                 gpio-controller;
 212                                 #gpio-cells = <2>;
 213                                 snps,nr-gpios = <10>;
 214                                 reg = <1>;
 215                         };
 216
 217                         gpio1_bankc: gpio-controller@2 {
 218                                 compatible = "snps,dw-apb-gpio-port";
 219                                 gpio-controller;
 220                                 #gpio-cells = <2>;
 221                                 snps,nr-gpios = <8>;
 222                                 reg = <2>;
 223                         };
 224                 };
 225         };
 226 };