4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_ELF_RANDOMIZE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_MIGHT_HAVE_PC_PARPORT
10 select ARCH_SUPPORTS_ATOMIC_RMW
11 select ARCH_USE_BUILTIN_BSWAP
12 select ARCH_USE_CMPXCHG_LOCKREF
13 select ARCH_WANT_IPC_PARSE_VERSION
14 select BUILDTIME_EXTABLE_SORT if MMU
15 select CLONE_BACKWARDS
16 select CPU_PM if (SUSPEND || CPU_IDLE)
17 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
19 select EDAC_ATOMIC_SCRUB
20 select GENERIC_ALLOCATOR
21 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
22 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
23 select GENERIC_IDLE_POLL_SETUP
24 select GENERIC_IRQ_PROBE
25 select GENERIC_IRQ_SHOW
26 select GENERIC_IRQ_SHOW_LEVEL
27 select GENERIC_PCI_IOMAP
28 select GENERIC_SCHED_CLOCK
29 select GENERIC_SMP_IDLE_THREAD
30 select GENERIC_STRNCPY_FROM_USER
31 select GENERIC_STRNLEN_USER
32 select HANDLE_DOMAIN_IRQ
33 select HARDIRQS_SW_RESEND
34 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
35 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
36 select HAVE_ARCH_HARDENED_USERCOPY
37 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32
38 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32
39 select HAVE_ARCH_MMAP_RND_BITS if MMU
40 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
41 select HAVE_ARCH_TRACEHOOK
42 select HAVE_ARM_SMCCC if CPU_V7
44 select HAVE_CC_STACKPROTECTOR
45 select HAVE_CONTEXT_TRACKING
46 select HAVE_C_RECORDMCOUNT
47 select HAVE_DEBUG_KMEMLEAK
48 select HAVE_DMA_API_DEBUG
50 select HAVE_DMA_CONTIGUOUS if MMU
51 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32
52 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
53 select HAVE_EXIT_THREAD
54 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
55 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
56 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
57 select HAVE_GENERIC_DMA_COHERENT
58 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
59 select HAVE_IDE if PCI || ISA || PCMCIA
60 select HAVE_IRQ_TIME_ACCOUNTING
61 select HAVE_KERNEL_GZIP
62 select HAVE_KERNEL_LZ4
63 select HAVE_KERNEL_LZMA
64 select HAVE_KERNEL_LZO
66 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
67 select HAVE_KRETPROBES if (HAVE_KPROBES)
69 select HAVE_MOD_ARCH_SPECIFIC
70 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
71 select HAVE_OPTPROBES if !THUMB2_KERNEL
72 select HAVE_PERF_EVENTS
74 select HAVE_PERF_USER_STACK_DUMP
75 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
76 select HAVE_REGS_AND_STACK_ACCESS_API
77 select HAVE_SYSCALL_TRACEPOINTS
79 select HAVE_VIRT_CPU_ACCOUNTING_GEN
80 select IRQ_FORCED_THREADING
81 select MODULES_USE_ELF_REL
83 select OF_EARLY_FLATTREE if OF
84 select OF_RESERVED_MEM if OF
86 select OLD_SIGSUSPEND3
87 select PERF_USE_VMALLOC
89 select SYS_SUPPORTS_APM_EMULATION
90 # Above selects are sorted alphabetically; please add new ones
91 # according to that. Thanks.
93 The ARM series is a line of low-power-consumption RISC chip designs
94 licensed by ARM Ltd and targeted at embedded applications and
95 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
96 manufactured, but legacy ARM-based PC hardware remains popular in
97 Europe. There is an ARM Linux project with a web page at
98 <http://www.arm.linux.org.uk/>.
100 config ARM_HAS_SG_CHAIN
101 select ARCH_HAS_SG_CHAIN
104 config NEED_SG_DMA_LENGTH
107 config ARM_DMA_USE_IOMMU
109 select ARM_HAS_SG_CHAIN
110 select NEED_SG_DMA_LENGTH
114 config ARM_DMA_IOMMU_ALIGNMENT
115 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
119 DMA mapping framework by default aligns all buffers to the smallest
120 PAGE_SIZE order which is greater than or equal to the requested buffer
121 size. This works well for buffers up to a few hundreds kilobytes, but
122 for larger buffers it just a waste of address space. Drivers which has
123 relatively small addressing window (like 64Mib) might run out of
124 virtual space with just a few allocations.
126 With this parameter you can specify the maximum PAGE_SIZE order for
127 DMA IOMMU buffers. Larger buffers will be aligned only to this
128 specified order. The order is expressed as a power of two multiplied
133 config MIGHT_HAVE_PCI
136 config SYS_SUPPORTS_APM_EMULATION
141 select GENERIC_ALLOCATOR
152 The Extended Industry Standard Architecture (EISA) bus was
153 developed as an open alternative to the IBM MicroChannel bus.
155 The EISA bus provided some of the features of the IBM MicroChannel
156 bus while maintaining backward compatibility with cards made for
157 the older ISA bus. The EISA bus saw limited use between 1988 and
158 1995 when it was made obsolete by the PCI bus.
160 Say Y here if you are building a kernel for an EISA-based machine.
167 config STACKTRACE_SUPPORT
171 config HAVE_LATENCYTOP_SUPPORT
176 config LOCKDEP_SUPPORT
180 config TRACE_IRQFLAGS_SUPPORT
184 config RWSEM_XCHGADD_ALGORITHM
188 config ARCH_HAS_ILOG2_U32
191 config ARCH_HAS_ILOG2_U64
194 config ARCH_HAS_BANDGAP
197 config FIX_EARLYCON_MEM
200 config GENERIC_HWEIGHT
204 config GENERIC_CALIBRATE_DELAY
208 config ARCH_MAY_HAVE_PC_FDC
214 config NEED_DMA_MAP_STATE
217 config ARCH_SUPPORTS_UPROBES
220 config ARCH_HAS_DMA_SET_COHERENT_MASK
223 config GENERIC_ISA_DMA
229 config NEED_RET_TO_USER
237 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
238 default DRAM_BASE if REMAP_VECTORS_TO_RAM
241 The base address of exception vectors. This must be two pages
244 config ARM_PATCH_PHYS_VIRT
245 bool "Patch physical to virtual translations at runtime" if EMBEDDED
247 depends on !XIP_KERNEL && MMU
248 depends on !ARCH_REALVIEW || !SPARSEMEM
250 Patch phys-to-virt and virt-to-phys translation functions at
251 boot and module load time according to the position of the
252 kernel in system memory.
254 This can only be used with non-XIP MMU kernels where the base
255 of physical memory is at a 16MB boundary.
257 Only disable this option if you know that you do not require
258 this feature (eg, building a kernel for a single machine) and
259 you need to shrink the kernel to the minimal size.
261 config NEED_MACH_IO_H
264 Select this when mach/io.h is required to provide special
265 definitions for this platform. The need for mach/io.h should
266 be avoided when possible.
268 config NEED_MACH_MEMORY_H
271 Select this when mach/memory.h is required to provide special
272 definitions for this platform. The need for mach/memory.h should
273 be avoided when possible.
276 hex "Physical address of main memory" if MMU
277 depends on !ARM_PATCH_PHYS_VIRT
278 default DRAM_BASE if !MMU
279 default 0x00000000 if ARCH_EBSA110 || \
284 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
285 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
286 default 0x20000000 if ARCH_S5PV210
287 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
288 default 0xc0000000 if ARCH_SA1100
290 Please provide the physical address corresponding to the
291 location of main memory in your system.
297 config PGTABLE_LEVELS
299 default 3 if ARM_LPAE
302 source "init/Kconfig"
304 source "kernel/Kconfig.freezer"
309 bool "MMU-based Paged Memory Management Support"
312 Select if you want MMU-based virtualised addressing space
313 support by paged memory management. If unsure, say 'Y'.
315 config ARCH_MMAP_RND_BITS_MIN
318 config ARCH_MMAP_RND_BITS_MAX
319 default 14 if PAGE_OFFSET=0x40000000
320 default 15 if PAGE_OFFSET=0x80000000
324 # The "ARM system type" choice list is ordered alphabetically by option
325 # text. Please add new entries in the option alphabetic order.
328 prompt "ARM system type"
329 default ARCH_VERSATILE if !MMU
330 default ARCH_MULTIPLATFORM if MMU
332 config ARCH_MULTIPLATFORM
333 bool "Allow multiple platforms to be selected"
335 select ARCH_WANT_OPTIONAL_GPIOLIB
336 select ARM_HAS_SG_CHAIN
337 select ARM_PATCH_PHYS_VIRT
341 select GENERIC_CLOCKEVENTS
342 select MIGHT_HAVE_PCI
343 select MULTI_IRQ_HANDLER
347 config ARM_SINGLE_ARMV7M
348 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
350 select ARCH_WANT_OPTIONAL_GPIOLIB
356 select GENERIC_CLOCKEVENTS
362 bool "ARM Ltd. RealView family"
363 select ARCH_WANT_OPTIONAL_GPIOLIB
365 select ARM_TIMER_SP804
367 select COMMON_CLK_VERSATILE
368 select GENERIC_CLOCKEVENTS
369 select GPIO_PL061 if GPIOLIB
371 select NEED_MACH_MEMORY_H
372 select PLAT_VERSATILE
373 select PLAT_VERSATILE_SCHED_CLOCK
375 This enables support for ARM Ltd RealView boards.
377 config ARCH_VERSATILE
378 bool "ARM Ltd. Versatile family"
379 select ARCH_WANT_OPTIONAL_GPIOLIB
381 select ARM_TIMER_SP804
384 select GENERIC_CLOCKEVENTS
385 select HAVE_MACH_CLKDEV
387 select PLAT_VERSATILE
388 select PLAT_VERSATILE_CLOCK
389 select PLAT_VERSATILE_SCHED_CLOCK
390 select VERSATILE_FPGA_IRQ
392 This enables support for ARM Ltd Versatile board.
395 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
396 select ARCH_REQUIRE_GPIOLIB
401 select GENERIC_CLOCKEVENTS
405 Support for Cirrus Logic 711x/721x/731x based boards.
408 bool "Cortina Systems Gemini"
409 select ARCH_REQUIRE_GPIOLIB
412 select GENERIC_CLOCKEVENTS
414 Support for the Cortina Systems Gemini family SoCs
418 select ARCH_USES_GETTIMEOFFSET
421 select NEED_MACH_IO_H
422 select NEED_MACH_MEMORY_H
425 This is an evaluation board for the StrongARM processor available
426 from Digital. It has limited hardware on-board, including an
427 Ethernet interface, two PCMCIA sockets, two serial ports and a
432 select ARCH_HAS_HOLES_MEMORYMODEL
433 select ARCH_REQUIRE_GPIOLIB
435 select ARM_PATCH_PHYS_VIRT
441 select GENERIC_CLOCKEVENTS
443 This enables support for the Cirrus EP93xx series of CPUs.
445 config ARCH_FOOTBRIDGE
449 select GENERIC_CLOCKEVENTS
451 select NEED_MACH_IO_H if !MMU
452 select NEED_MACH_MEMORY_H
454 Support for systems based on the DC21285 companion chip
455 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
458 bool "Hilscher NetX based"
462 select GENERIC_CLOCKEVENTS
464 This enables support for systems based on the Hilscher NetX Soc
470 select NEED_MACH_MEMORY_H
471 select NEED_RET_TO_USER
477 Support for Intel's IOP13XX (XScale) family of processors.
482 select ARCH_REQUIRE_GPIOLIB
485 select NEED_RET_TO_USER
489 Support for Intel's 80219 and IOP32X (XScale) family of
495 select ARCH_REQUIRE_GPIOLIB
498 select NEED_RET_TO_USER
502 Support for Intel's IOP33X (XScale) family of processors.
507 select ARCH_HAS_DMA_SET_COHERENT_MASK
508 select ARCH_REQUIRE_GPIOLIB
509 select ARCH_SUPPORTS_BIG_ENDIAN
512 select DMABOUNCE if PCI
513 select GENERIC_CLOCKEVENTS
514 select MIGHT_HAVE_PCI
515 select NEED_MACH_IO_H
516 select USB_EHCI_BIG_ENDIAN_DESC
517 select USB_EHCI_BIG_ENDIAN_MMIO
519 Support for Intel's IXP4XX (XScale) family of processors.
523 select ARCH_REQUIRE_GPIOLIB
525 select GENERIC_CLOCKEVENTS
526 select MIGHT_HAVE_PCI
530 select PLAT_ORION_LEGACY
532 Support for the Marvell Dove SoC 88AP510
535 bool "Marvell MV78xx0"
536 select ARCH_REQUIRE_GPIOLIB
538 select GENERIC_CLOCKEVENTS
541 select PLAT_ORION_LEGACY
543 Support for the following Marvell MV78xx0 series SoCs:
549 select ARCH_REQUIRE_GPIOLIB
551 select GENERIC_CLOCKEVENTS
554 select PLAT_ORION_LEGACY
555 select MULTI_IRQ_HANDLER
557 Support for the following Marvell Orion 5x series SoCs:
558 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
559 Orion-2 (5281), Orion-1-90 (6183).
562 bool "Marvell PXA168/910/MMP2"
564 select ARCH_REQUIRE_GPIOLIB
566 select GENERIC_ALLOCATOR
567 select GENERIC_CLOCKEVENTS
570 select MULTI_IRQ_HANDLER
575 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
578 bool "Micrel/Kendin KS8695"
579 select ARCH_REQUIRE_GPIOLIB
582 select GENERIC_CLOCKEVENTS
583 select NEED_MACH_MEMORY_H
585 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
586 System-on-Chip devices.
589 bool "Nuvoton W90X900 CPU"
590 select ARCH_REQUIRE_GPIOLIB
594 select GENERIC_CLOCKEVENTS
596 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
597 At present, the w90x900 has been renamed nuc900, regarding
598 the ARM series product line, you can login the following
599 link address to know more.
601 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
602 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
606 select ARCH_REQUIRE_GPIOLIB
611 select GENERIC_CLOCKEVENTS
615 Support for the NXP LPC32XX family of processors
618 bool "PXA2xx/PXA3xx-based"
621 select ARCH_REQUIRE_GPIOLIB
622 select ARM_CPU_SUSPEND if PM
628 select GENERIC_CLOCKEVENTS
632 select MULTI_IRQ_HANDLER
636 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
642 select ARCH_MAY_HAVE_PC_FDC
643 select ARCH_SPARSEMEM_ENABLE
644 select ARCH_USES_GETTIMEOFFSET
648 select HAVE_PATA_PLATFORM
650 select NEED_MACH_IO_H
651 select NEED_MACH_MEMORY_H
655 On the Acorn Risc-PC, Linux can support the internal IDE disk and
656 CD-ROM interface, serial and parallel port, and the floppy drive.
661 select ARCH_REQUIRE_GPIOLIB
662 select ARCH_SPARSEMEM_ENABLE
667 select GENERIC_CLOCKEVENTS
671 select MULTI_IRQ_HANDLER
672 select NEED_MACH_MEMORY_H
675 Support for StrongARM 11x0 based boards.
678 bool "Samsung S3C24XX SoCs"
679 select ARCH_REQUIRE_GPIOLIB
682 select CLKSRC_SAMSUNG_PWM
683 select GENERIC_CLOCKEVENTS
685 select HAVE_S3C2410_I2C if I2C
686 select HAVE_S3C2410_WATCHDOG if WATCHDOG
687 select HAVE_S3C_RTC if RTC_CLASS
688 select MULTI_IRQ_HANDLER
689 select NEED_MACH_IO_H
692 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
693 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
694 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
695 Samsung SMDK2410 development board (and derivatives).
698 bool "Samsung S3C64XX"
699 select ARCH_REQUIRE_GPIOLIB
704 select CLKSRC_SAMSUNG_PWM
705 select COMMON_CLK_SAMSUNG
707 select GENERIC_CLOCKEVENTS
709 select HAVE_S3C2410_I2C if I2C
710 select HAVE_S3C2410_WATCHDOG if WATCHDOG
714 select PM_GENERIC_DOMAINS if PM
716 select S3C_GPIO_TRACK
718 select SAMSUNG_WAKEMASK
719 select SAMSUNG_WDT_RESET
721 Samsung S3C64XX series based systems
725 select ARCH_HAS_HOLES_MEMORYMODEL
726 select ARCH_REQUIRE_GPIOLIB
728 select GENERIC_ALLOCATOR
729 select GENERIC_CLOCKEVENTS
730 select GENERIC_IRQ_CHIP
735 Support for TI's DaVinci platform.
740 select ARCH_HAS_HOLES_MEMORYMODEL
742 select ARCH_REQUIRE_GPIOLIB
745 select GENERIC_CLOCKEVENTS
746 select GENERIC_IRQ_CHIP
749 select MULTI_IRQ_HANDLER
750 select NEED_MACH_IO_H if PCCARD
751 select NEED_MACH_MEMORY_H
754 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
758 menu "Multiple platform selection"
759 depends on ARCH_MULTIPLATFORM
761 comment "CPU Core family selection"
764 bool "ARMv4 based platforms (FA526)"
765 depends on !ARCH_MULTI_V6_V7
766 select ARCH_MULTI_V4_V5
769 config ARCH_MULTI_V4T
770 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
771 depends on !ARCH_MULTI_V6_V7
772 select ARCH_MULTI_V4_V5
773 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
774 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
775 CPU_ARM925T || CPU_ARM940T)
778 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
779 depends on !ARCH_MULTI_V6_V7
780 select ARCH_MULTI_V4_V5
781 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
782 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
783 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
785 config ARCH_MULTI_V4_V5
789 bool "ARMv6 based platforms (ARM11)"
790 select ARCH_MULTI_V6_V7
794 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
796 select ARCH_MULTI_V6_V7
800 config ARCH_MULTI_V6_V7
802 select MIGHT_HAVE_CACHE_L2X0
804 config ARCH_MULTI_CPU_AUTO
805 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
811 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
816 select HAVE_ARM_ARCH_TIMER
819 # This is sorted alphabetically by mach-* pathname. However, plat-*
820 # Kconfigs may be included either alphabetically (according to the
821 # plat- suffix) or along side the corresponding mach-* source.
823 source "arch/arm/mach-mvebu/Kconfig"
825 source "arch/arm/mach-alpine/Kconfig"
827 source "arch/arm/mach-asm9260/Kconfig"
829 source "arch/arm/mach-at91/Kconfig"
831 source "arch/arm/mach-axxia/Kconfig"
833 source "arch/arm/mach-bcm/Kconfig"
835 source "arch/arm/mach-berlin/Kconfig"
837 source "arch/arm/mach-clps711x/Kconfig"
839 source "arch/arm/mach-cns3xxx/Kconfig"
841 source "arch/arm/mach-davinci/Kconfig"
843 source "arch/arm/mach-digicolor/Kconfig"
845 source "arch/arm/mach-dove/Kconfig"
847 source "arch/arm/mach-ep93xx/Kconfig"
849 source "arch/arm/mach-footbridge/Kconfig"
851 source "arch/arm/mach-gemini/Kconfig"
853 source "arch/arm/mach-highbank/Kconfig"
855 source "arch/arm/mach-hisi/Kconfig"
857 source "arch/arm/mach-integrator/Kconfig"
859 source "arch/arm/mach-iop32x/Kconfig"
861 source "arch/arm/mach-iop33x/Kconfig"
863 source "arch/arm/mach-iop13xx/Kconfig"
865 source "arch/arm/mach-ixp4xx/Kconfig"
867 source "arch/arm/mach-keystone/Kconfig"
869 source "arch/arm/mach-ks8695/Kconfig"
871 source "arch/arm/mach-meson/Kconfig"
873 source "arch/arm/mach-moxart/Kconfig"
875 source "arch/arm/mach-mv78xx0/Kconfig"
877 source "arch/arm/mach-imx/Kconfig"
879 source "arch/arm/mach-mediatek/Kconfig"
881 source "arch/arm/mach-mxs/Kconfig"
883 source "arch/arm/mach-netx/Kconfig"
885 source "arch/arm/mach-nomadik/Kconfig"
887 source "arch/arm/mach-nspire/Kconfig"
889 source "arch/arm/plat-omap/Kconfig"
891 source "arch/arm/mach-omap1/Kconfig"
893 source "arch/arm/mach-omap2/Kconfig"
895 source "arch/arm/mach-orion5x/Kconfig"
897 source "arch/arm/mach-picoxcell/Kconfig"
899 source "arch/arm/mach-pxa/Kconfig"
900 source "arch/arm/plat-pxa/Kconfig"
902 source "arch/arm/mach-mmp/Kconfig"
904 source "arch/arm/mach-qcom/Kconfig"
906 source "arch/arm/mach-realview/Kconfig"
908 source "arch/arm/mach-rockchip/Kconfig"
910 source "arch/arm/mach-sa1100/Kconfig"
912 source "arch/arm/mach-socfpga/Kconfig"
914 source "arch/arm/mach-spear/Kconfig"
916 source "arch/arm/mach-sti/Kconfig"
918 source "arch/arm/mach-s3c24xx/Kconfig"
920 source "arch/arm/mach-s3c64xx/Kconfig"
922 source "arch/arm/mach-s5pv210/Kconfig"
924 source "arch/arm/mach-exynos/Kconfig"
925 source "arch/arm/plat-samsung/Kconfig"
927 source "arch/arm/mach-shmobile/Kconfig"
929 source "arch/arm/mach-sunxi/Kconfig"
931 source "arch/arm/mach-prima2/Kconfig"
933 source "arch/arm/mach-tegra/Kconfig"
935 source "arch/arm/mach-u300/Kconfig"
937 source "arch/arm/mach-uniphier/Kconfig"
939 source "arch/arm/mach-ux500/Kconfig"
941 source "arch/arm/mach-versatile/Kconfig"
943 source "arch/arm/mach-vexpress/Kconfig"
944 source "arch/arm/plat-versatile/Kconfig"
946 source "arch/arm/mach-vt8500/Kconfig"
948 source "arch/arm/mach-w90x900/Kconfig"
950 source "arch/arm/mach-zx/Kconfig"
952 source "arch/arm/mach-zynq/Kconfig"
954 # ARMv7-M architecture
956 bool "Energy Micro efm32"
957 depends on ARM_SINGLE_ARMV7M
958 select ARCH_REQUIRE_GPIOLIB
960 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
964 bool "NXP LPC18xx/LPC43xx"
965 depends on ARM_SINGLE_ARMV7M
966 select ARCH_HAS_RESET_CONTROLLER
968 select CLKSRC_LPC32XX
971 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
972 high performance microcontrollers.
975 bool "STMicrolectronics STM32"
976 depends on ARM_SINGLE_ARMV7M
977 select ARCH_HAS_RESET_CONTROLLER
978 select ARMV7M_SYSTICK
980 select RESET_CONTROLLER
982 Support for STMicroelectronics STM32 processors.
984 # Definitions to make life easier
990 select GENERIC_CLOCKEVENTS
996 select GENERIC_IRQ_CHIP
999 config PLAT_ORION_LEGACY
1006 config PLAT_VERSATILE
1009 source "arch/arm/firmware/Kconfig"
1011 source arch/arm/mm/Kconfig
1014 bool "Enable iWMMXt support"
1015 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1016 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1018 Enable support for iWMMXt context switching at run time if
1019 running on a CPU that supports it.
1021 config MULTI_IRQ_HANDLER
1024 Allow each machine to specify it's own IRQ handler at run time.
1027 source "arch/arm/Kconfig-nommu"
1030 config PJ4B_ERRATA_4742
1031 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1032 depends on CPU_PJ4B && MACH_ARMADA_370
1035 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1036 Event (WFE) IDLE states, a specific timing sensitivity exists between
1037 the retiring WFI/WFE instructions and the newly issued subsequent
1038 instructions. This sensitivity can result in a CPU hang scenario.
1040 The software must insert either a Data Synchronization Barrier (DSB)
1041 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1044 config ARM_ERRATA_326103
1045 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1048 Executing a SWP instruction to read-only memory does not set bit 11
1049 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1050 treat the access as a read, preventing a COW from occurring and
1051 causing the faulting task to livelock.
1053 config ARM_ERRATA_411920
1054 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1055 depends on CPU_V6 || CPU_V6K
1057 Invalidation of the Instruction Cache operation can
1058 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1059 It does not affect the MPCore. This option enables the ARM Ltd.
1060 recommended workaround.
1062 config ARM_ERRATA_430973
1063 bool "ARM errata: Stale prediction on replaced interworking branch"
1066 This option enables the workaround for the 430973 Cortex-A8
1067 r1p* erratum. If a code sequence containing an ARM/Thumb
1068 interworking branch is replaced with another code sequence at the
1069 same virtual address, whether due to self-modifying code or virtual
1070 to physical address re-mapping, Cortex-A8 does not recover from the
1071 stale interworking branch prediction. This results in Cortex-A8
1072 executing the new code sequence in the incorrect ARM or Thumb state.
1073 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1074 and also flushes the branch target cache at every context switch.
1075 Note that setting specific bits in the ACTLR register may not be
1076 available in non-secure mode.
1078 config ARM_ERRATA_458693
1079 bool "ARM errata: Processor deadlock when a false hazard is created"
1081 depends on !ARCH_MULTIPLATFORM
1083 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1084 erratum. For very specific sequences of memory operations, it is
1085 possible for a hazard condition intended for a cache line to instead
1086 be incorrectly associated with a different cache line. This false
1087 hazard might then cause a processor deadlock. The workaround enables
1088 the L1 caching of the NEON accesses and disables the PLD instruction
1089 in the ACTLR register. Note that setting specific bits in the ACTLR
1090 register may not be available in non-secure mode.
1092 config ARM_ERRATA_460075
1093 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1095 depends on !ARCH_MULTIPLATFORM
1097 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1098 erratum. Any asynchronous access to the L2 cache may encounter a
1099 situation in which recent store transactions to the L2 cache are lost
1100 and overwritten with stale memory contents from external memory. The
1101 workaround disables the write-allocate mode for the L2 cache via the
1102 ACTLR register. Note that setting specific bits in the ACTLR register
1103 may not be available in non-secure mode.
1105 config ARM_ERRATA_742230
1106 bool "ARM errata: DMB operation may be faulty"
1107 depends on CPU_V7 && SMP
1108 depends on !ARCH_MULTIPLATFORM
1110 This option enables the workaround for the 742230 Cortex-A9
1111 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1112 between two write operations may not ensure the correct visibility
1113 ordering of the two writes. This workaround sets a specific bit in
1114 the diagnostic register of the Cortex-A9 which causes the DMB
1115 instruction to behave as a DSB, ensuring the correct behaviour of
1118 config ARM_ERRATA_742231
1119 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1120 depends on CPU_V7 && SMP
1121 depends on !ARCH_MULTIPLATFORM
1123 This option enables the workaround for the 742231 Cortex-A9
1124 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1125 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1126 accessing some data located in the same cache line, may get corrupted
1127 data due to bad handling of the address hazard when the line gets
1128 replaced from one of the CPUs at the same time as another CPU is
1129 accessing it. This workaround sets specific bits in the diagnostic
1130 register of the Cortex-A9 which reduces the linefill issuing
1131 capabilities of the processor.
1133 config ARM_ERRATA_643719
1134 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1135 depends on CPU_V7 && SMP
1138 This option enables the workaround for the 643719 Cortex-A9 (prior to
1139 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1140 register returns zero when it should return one. The workaround
1141 corrects this value, ensuring cache maintenance operations which use
1142 it behave as intended and avoiding data corruption.
1144 config ARM_ERRATA_720789
1145 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1148 This option enables the workaround for the 720789 Cortex-A9 (prior to
1149 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1150 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1151 As a consequence of this erratum, some TLB entries which should be
1152 invalidated are not, resulting in an incoherency in the system page
1153 tables. The workaround changes the TLB flushing routines to invalidate
1154 entries regardless of the ASID.
1156 config ARM_ERRATA_743622
1157 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1159 depends on !ARCH_MULTIPLATFORM
1161 This option enables the workaround for the 743622 Cortex-A9
1162 (r2p*) erratum. Under very rare conditions, a faulty
1163 optimisation in the Cortex-A9 Store Buffer may lead to data
1164 corruption. This workaround sets a specific bit in the diagnostic
1165 register of the Cortex-A9 which disables the Store Buffer
1166 optimisation, preventing the defect from occurring. This has no
1167 visible impact on the overall performance or power consumption of the
1170 config ARM_ERRATA_751472
1171 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1173 depends on !ARCH_MULTIPLATFORM
1175 This option enables the workaround for the 751472 Cortex-A9 (prior
1176 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1177 completion of a following broadcasted operation if the second
1178 operation is received by a CPU before the ICIALLUIS has completed,
1179 potentially leading to corrupted entries in the cache or TLB.
1181 config ARM_ERRATA_754322
1182 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1185 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1186 r3p*) erratum. A speculative memory access may cause a page table walk
1187 which starts prior to an ASID switch but completes afterwards. This
1188 can populate the micro-TLB with a stale entry which may be hit with
1189 the new ASID. This workaround places two dsb instructions in the mm
1190 switching code so that no page table walks can cross the ASID switch.
1192 config ARM_ERRATA_754327
1193 bool "ARM errata: no automatic Store Buffer drain"
1194 depends on CPU_V7 && SMP
1196 This option enables the workaround for the 754327 Cortex-A9 (prior to
1197 r2p0) erratum. The Store Buffer does not have any automatic draining
1198 mechanism and therefore a livelock may occur if an external agent
1199 continuously polls a memory location waiting to observe an update.
1200 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1201 written polling loops from denying visibility of updates to memory.
1203 config ARM_ERRATA_364296
1204 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1207 This options enables the workaround for the 364296 ARM1136
1208 r0p2 erratum (possible cache data corruption with
1209 hit-under-miss enabled). It sets the undocumented bit 31 in
1210 the auxiliary control register and the FI bit in the control
1211 register, thus disabling hit-under-miss without putting the
1212 processor into full low interrupt latency mode. ARM11MPCore
1215 config ARM_ERRATA_764369
1216 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1217 depends on CPU_V7 && SMP
1219 This option enables the workaround for erratum 764369
1220 affecting Cortex-A9 MPCore with two or more processors (all
1221 current revisions). Under certain timing circumstances, a data
1222 cache line maintenance operation by MVA targeting an Inner
1223 Shareable memory region may fail to proceed up to either the
1224 Point of Coherency or to the Point of Unification of the
1225 system. This workaround adds a DSB instruction before the
1226 relevant cache maintenance functions and sets a specific bit
1227 in the diagnostic control register of the SCU.
1229 config ARM_ERRATA_775420
1230 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1233 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1234 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1235 operation aborts with MMU exception, it might cause the processor
1236 to deadlock. This workaround puts DSB before executing ISB if
1237 an abort may occur on cache maintenance.
1239 config ARM_ERRATA_798181
1240 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1241 depends on CPU_V7 && SMP
1243 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1244 adequately shooting down all use of the old entries. This
1245 option enables the Linux kernel workaround for this erratum
1246 which sends an IPI to the CPUs that are running the same ASID
1247 as the one being invalidated.
1249 config ARM_ERRATA_773022
1250 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1253 This option enables the workaround for the 773022 Cortex-A15
1254 (up to r0p4) erratum. In certain rare sequences of code, the
1255 loop buffer may deliver incorrect instructions. This
1256 workaround disables the loop buffer to avoid the erratum.
1260 source "arch/arm/common/Kconfig"
1267 Find out whether you have ISA slots on your motherboard. ISA is the
1268 name of a bus system, i.e. the way the CPU talks to the other stuff
1269 inside your box. Other bus systems are PCI, EISA, MicroChannel
1270 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1271 newer boards don't support it. If you have ISA, say Y, otherwise N.
1273 # Select ISA DMA controller support
1278 # Select ISA DMA interface
1283 bool "PCI support" if MIGHT_HAVE_PCI
1285 Find out whether you have a PCI motherboard. PCI is the name of a
1286 bus system, i.e. the way the CPU talks to the other stuff inside
1287 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1288 VESA. If you have PCI, say Y, otherwise N.
1294 config PCI_DOMAINS_GENERIC
1295 def_bool PCI_DOMAINS
1297 config PCI_NANOENGINE
1298 bool "BSE nanoEngine PCI support"
1299 depends on SA1100_NANOENGINE
1301 Enable PCI on the BSE nanoEngine board.
1306 config PCI_HOST_ITE8152
1308 depends on PCI && MACH_ARMCORE
1312 source "drivers/pci/Kconfig"
1313 source "drivers/pci/pcie/Kconfig"
1315 source "drivers/pcmcia/Kconfig"
1319 menu "Kernel Features"
1324 This option should be selected by machines which have an SMP-
1327 The only effect of this option is to make the SMP-related
1328 options available to the user for configuration.
1331 bool "Symmetric Multi-Processing"
1332 depends on CPU_V6K || CPU_V7
1333 depends on GENERIC_CLOCKEVENTS
1335 depends on MMU || ARM_MPU
1338 This enables support for systems with more than one CPU. If you have
1339 a system with only one CPU, say N. If you have a system with more
1340 than one CPU, say Y.
1342 If you say N here, the kernel will run on uni- and multiprocessor
1343 machines, but will use only one CPU of a multiprocessor machine. If
1344 you say Y here, the kernel will run on many, but not all,
1345 uniprocessor machines. On a uniprocessor machine, the kernel
1346 will run faster if you say N here.
1348 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1349 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1350 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1352 If you don't know what to do here, say N.
1355 bool "Allow booting SMP kernel on uniprocessor systems"
1356 depends on SMP && !XIP_KERNEL && MMU
1359 SMP kernels contain instructions which fail on non-SMP processors.
1360 Enabling this option allows the kernel to modify itself to make
1361 these instructions safe. Disabling it allows about 1K of space
1364 If you don't know what to do here, say Y.
1366 config ARM_CPU_TOPOLOGY
1367 bool "Support cpu topology definition"
1368 depends on SMP && CPU_V7
1371 Support ARM cpu topology definition. The MPIDR register defines
1372 affinity between processors which is then used to describe the cpu
1373 topology of an ARM System.
1376 bool "Multi-core scheduler support"
1377 depends on ARM_CPU_TOPOLOGY
1379 Multi-core scheduler support improves the CPU scheduler's decision
1380 making when dealing with multi-core CPU chips at a cost of slightly
1381 increased overhead in some places. If unsure say N here.
1384 bool "SMT scheduler support"
1385 depends on ARM_CPU_TOPOLOGY
1387 Improves the CPU scheduler's decision making when dealing with
1388 MultiThreading at a cost of slightly increased overhead in some
1389 places. If unsure say N here.
1394 This option enables support for the ARM system coherency unit
1396 config HAVE_ARM_ARCH_TIMER
1397 bool "Architected timer support"
1399 select ARM_ARCH_TIMER
1400 select GENERIC_CLOCKEVENTS
1402 This option enables support for the ARM architected timer
1406 select CLKSRC_OF if OF
1408 This options enables support for the ARM timer and watchdog unit
1411 bool "Multi-Cluster Power Management"
1412 depends on CPU_V7 && SMP
1414 This option provides the common power management infrastructure
1415 for (multi-)cluster based systems, such as big.LITTLE based
1418 config MCPM_QUAD_CLUSTER
1422 To avoid wasting resources unnecessarily, MCPM only supports up
1423 to 2 clusters by default.
1424 Platforms with 3 or 4 clusters that use MCPM must select this
1425 option to allow the additional clusters to be managed.
1428 bool "big.LITTLE support (Experimental)"
1429 depends on CPU_V7 && SMP
1432 This option enables support selections for the big.LITTLE
1433 system architecture.
1436 bool "big.LITTLE switcher support"
1437 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1440 The big.LITTLE "switcher" provides the core functionality to
1441 transparently handle transition between a cluster of A15's
1442 and a cluster of A7's in a big.LITTLE system.
1444 config BL_SWITCHER_DUMMY_IF
1445 tristate "Simple big.LITTLE switcher user interface"
1446 depends on BL_SWITCHER && DEBUG_KERNEL
1448 This is a simple and dummy char dev interface to control
1449 the big.LITTLE switcher core code. It is meant for
1450 debugging purposes only.
1453 prompt "Memory split"
1457 Select the desired split between kernel and user memory.
1459 If you are not absolutely sure what you are doing, leave this
1463 bool "3G/1G user/kernel split"
1464 config VMSPLIT_3G_OPT
1465 bool "3G/1G user/kernel split (for full 1G low memory)"
1467 bool "2G/2G user/kernel split"
1469 bool "1G/3G user/kernel split"
1474 default PHYS_OFFSET if !MMU
1475 default 0x40000000 if VMSPLIT_1G
1476 default 0x80000000 if VMSPLIT_2G
1477 default 0xB0000000 if VMSPLIT_3G_OPT
1481 int "Maximum number of CPUs (2-32)"
1487 bool "Support for hot-pluggable CPUs"
1489 select GENERIC_IRQ_MIGRATION
1491 Say Y here to experiment with turning CPUs off and on. CPUs
1492 can be controlled through /sys/devices/system/cpu.
1495 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1496 depends on HAVE_ARM_SMCCC
1499 Say Y here if you want Linux to communicate with system firmware
1500 implementing the PSCI specification for CPU-centric power
1501 management operations described in ARM document number ARM DEN
1502 0022A ("Power State Coordination Interface System Software on
1505 # The GPIO number here must be sorted by descending number. In case of
1506 # a multiplatform kernel, we just want the highest value required by the
1507 # selected platforms.
1510 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1512 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1513 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1514 default 416 if ARCH_SUNXI
1515 default 392 if ARCH_U8500
1516 default 352 if ARCH_VT8500
1517 default 288 if ARCH_ROCKCHIP
1518 default 264 if MACH_H4700
1521 Maximum number of GPIOs in the system.
1523 If unsure, leave the default value.
1525 source kernel/Kconfig.preempt
1529 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1530 ARCH_S5PV210 || ARCH_EXYNOS4
1531 default 128 if SOC_AT91RM9200
1535 depends on HZ_FIXED = 0
1536 prompt "Timer frequency"
1560 default HZ_FIXED if HZ_FIXED != 0
1561 default 100 if HZ_100
1562 default 200 if HZ_200
1563 default 250 if HZ_250
1564 default 300 if HZ_300
1565 default 500 if HZ_500
1569 def_bool HIGH_RES_TIMERS
1571 config THUMB2_KERNEL
1572 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1573 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1574 default y if CPU_THUMBONLY
1576 select ARM_ASM_UNIFIED
1579 By enabling this option, the kernel will be compiled in
1580 Thumb-2 mode. A compiler/assembler that understand the unified
1581 ARM-Thumb syntax is needed.
1585 config THUMB2_AVOID_R_ARM_THM_JUMP11
1586 bool "Work around buggy Thumb-2 short branch relocations in gas"
1587 depends on THUMB2_KERNEL && MODULES
1590 Various binutils versions can resolve Thumb-2 branches to
1591 locally-defined, preemptible global symbols as short-range "b.n"
1592 branch instructions.
1594 This is a problem, because there's no guarantee the final
1595 destination of the symbol, or any candidate locations for a
1596 trampoline, are within range of the branch. For this reason, the
1597 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1598 relocation in modules at all, and it makes little sense to add
1601 The symptom is that the kernel fails with an "unsupported
1602 relocation" error when loading some modules.
1604 Until fixed tools are available, passing
1605 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1606 code which hits this problem, at the cost of a bit of extra runtime
1607 stack usage in some cases.
1609 The problem is described in more detail at:
1610 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1612 Only Thumb-2 kernels are affected.
1614 Unless you are sure your tools don't have this problem, say Y.
1616 config ARM_ASM_UNIFIED
1620 bool "Use the ARM EABI to compile the kernel"
1622 This option allows for the kernel to be compiled using the latest
1623 ARM ABI (aka EABI). This is only useful if you are using a user
1624 space environment that is also compiled with EABI.
1626 Since there are major incompatibilities between the legacy ABI and
1627 EABI, especially with regard to structure member alignment, this
1628 option also changes the kernel syscall calling convention to
1629 disambiguate both ABIs and allow for backward compatibility support
1630 (selected with CONFIG_OABI_COMPAT).
1632 To use this you need GCC version 4.0.0 or later.
1635 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1636 depends on AEABI && !THUMB2_KERNEL
1638 This option preserves the old syscall interface along with the
1639 new (ARM EABI) one. It also provides a compatibility layer to
1640 intercept syscalls that have structure arguments which layout
1641 in memory differs between the legacy ABI and the new ARM EABI
1642 (only for non "thumb" binaries). This option adds a tiny
1643 overhead to all syscalls and produces a slightly larger kernel.
1645 The seccomp filter system will not be available when this is
1646 selected, since there is no way yet to sensibly distinguish
1647 between calling conventions during filtering.
1649 If you know you'll be using only pure EABI user space then you
1650 can say N here. If this option is not selected and you attempt
1651 to execute a legacy ABI binary then the result will be
1652 UNPREDICTABLE (in fact it can be predicted that it won't work
1653 at all). If in doubt say N.
1655 config ARCH_HAS_HOLES_MEMORYMODEL
1658 config ARCH_SPARSEMEM_ENABLE
1661 config ARCH_SPARSEMEM_DEFAULT
1662 def_bool ARCH_SPARSEMEM_ENABLE
1664 config ARCH_SELECT_MEMORY_MODEL
1665 def_bool ARCH_SPARSEMEM_ENABLE
1667 config HAVE_ARCH_PFN_VALID
1668 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1670 config HAVE_GENERIC_RCU_GUP
1675 bool "High Memory Support"
1678 The address space of ARM processors is only 4 Gigabytes large
1679 and it has to accommodate user address space, kernel address
1680 space as well as some memory mapped IO. That means that, if you
1681 have a large amount of physical memory and/or IO, not all of the
1682 memory can be "permanently mapped" by the kernel. The physical
1683 memory that is not permanently mapped is called "high memory".
1685 Depending on the selected kernel/user memory split, minimum
1686 vmalloc space and actual amount of RAM, you may not need this
1687 option which should result in a slightly faster kernel.
1692 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1696 The VM uses one page of physical memory for each page table.
1697 For systems with a lot of processes, this can use a lot of
1698 precious low memory, eventually leading to low memory being
1699 consumed by page tables. Setting this option will allow
1700 user-space 2nd level page tables to reside in high memory.
1702 config CPU_SW_DOMAIN_PAN
1703 bool "Enable use of CPU domains to implement privileged no-access"
1704 depends on MMU && !ARM_LPAE
1707 Increase kernel security by ensuring that normal kernel accesses
1708 are unable to access userspace addresses. This can help prevent
1709 use-after-free bugs becoming an exploitable privilege escalation
1710 by ensuring that magic values (such as LIST_POISON) will always
1711 fault when dereferenced.
1713 CPUs with low-vector mappings use a best-efforts implementation.
1714 Their lower 1MB needs to remain accessible for the vectors, but
1715 the remainder of userspace will become appropriately inaccessible.
1717 config HW_PERF_EVENTS
1721 config SYS_SUPPORTS_HUGETLBFS
1725 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1729 config ARCH_WANT_GENERAL_HUGETLB
1732 config ARM_MODULE_PLTS
1733 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1736 Allocate PLTs when loading modules so that jumps and calls whose
1737 targets are too far away for their relative offsets to be encoded
1738 in the instructions themselves can be bounced via veneers in the
1739 module's PLT. This allows modules to be allocated in the generic
1740 vmalloc area after the dedicated module memory area has been
1741 exhausted. The modules will use slightly more memory, but after
1742 rounding up to page size, the actual memory footprint is usually
1745 Say y if you are getting out of memory errors while loading modules
1749 config FORCE_MAX_ZONEORDER
1750 int "Maximum zone order"
1751 default "12" if SOC_AM33XX
1752 default "9" if SA1111 || ARCH_EFM32
1755 The kernel memory allocator divides physically contiguous memory
1756 blocks into "zones", where each zone is a power of two number of
1757 pages. This option selects the largest power of two that the kernel
1758 keeps in the memory allocator. If you need to allocate very large
1759 blocks of physically contiguous memory, then you may need to
1760 increase this value.
1762 This config option is actually maximum order plus one. For example,
1763 a value of 11 means that the largest free memory block is 2^10 pages.
1765 config ALIGNMENT_TRAP
1767 depends on CPU_CP15_MMU
1768 default y if !ARCH_EBSA110
1769 select HAVE_PROC_CPU if PROC_FS
1771 ARM processors cannot fetch/store information which is not
1772 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1773 address divisible by 4. On 32-bit ARM processors, these non-aligned
1774 fetch/store instructions will be emulated in software if you say
1775 here, which has a severe performance impact. This is necessary for
1776 correct operation of some network protocols. With an IP-only
1777 configuration it is safe to say N, otherwise say Y.
1779 config UACCESS_WITH_MEMCPY
1780 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1782 default y if CPU_FEROCEON
1784 Implement faster copy_to_user and clear_user methods for CPU
1785 cores where a 8-word STM instruction give significantly higher
1786 memory write throughput than a sequence of individual 32bit stores.
1788 A possible side effect is a slight increase in scheduling latency
1789 between threads sharing the same address space if they invoke
1790 such copy operations with large buffers.
1792 However, if the CPU data cache is using a write-allocate mode,
1793 this option is unlikely to provide any performance gain.
1797 prompt "Enable seccomp to safely compute untrusted bytecode"
1799 This kernel feature is useful for number crunching applications
1800 that may need to compute untrusted bytecode during their
1801 execution. By using pipes or other transports made available to
1802 the process as file descriptors supporting the read/write
1803 syscalls, it's possible to isolate those applications in
1804 their own address space using seccomp. Once seccomp is
1805 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1806 and the task is only allowed to execute a few safe syscalls
1807 defined by each seccomp mode.
1820 bool "Xen guest support on ARM"
1821 depends on ARM && AEABI && OF
1822 depends on CPU_V7 && !CPU_V6
1823 depends on !GENERIC_ATOMIC64
1825 select ARCH_DMA_ADDR_T_64BIT
1829 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1831 config ARM_FLUSH_CONSOLE_ON_RESTART
1832 bool "Force flush the console on restart"
1834 If the console is locked while the system is rebooted, the messages
1835 in the temporary logbuffer would not have propogated to all the
1836 console drivers. This option forces the console lock to be
1837 released if it failed to be acquired, which will cause all the
1838 pending messages to be flushed.
1845 bool "Flattened Device Tree support"
1849 Include support for flattened device tree machine descriptions.
1852 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1855 This is the traditional way of passing data to the kernel at boot
1856 time. If you are solely relying on the flattened device tree (or
1857 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1858 to remove ATAGS support from your kernel binary. If unsure,
1861 config DEPRECATED_PARAM_STRUCT
1862 bool "Provide old way to pass kernel parameters"
1865 This was deprecated in 2001 and announced to live on for 5 years.
1866 Some old boot loaders still use this way.
1868 config BUILD_ARM_APPENDED_DTB_IMAGE
1869 bool "Build a concatenated zImage/dtb by default"
1872 Enabling this option will cause a concatenated zImage and list of
1873 DTBs to be built by default (instead of a standalone zImage.)
1874 The image will built in arch/arm/boot/zImage-dtb
1876 config BUILD_ARM_APPENDED_DTB_IMAGE_NAMES
1877 string "Default dtb names"
1878 depends on BUILD_ARM_APPENDED_DTB_IMAGE
1880 Space separated list of names of dtbs to append when
1881 building a concatenated zImage-dtb.
1883 # Compressed boot loader in ROM. Yes, we really want to ask about
1884 # TEXT and BSS so we preserve their values in the config files.
1885 config ZBOOT_ROM_TEXT
1886 hex "Compressed ROM boot loader base address"
1889 The physical address at which the ROM-able zImage is to be
1890 placed in the target. Platforms which normally make use of
1891 ROM-able zImage formats normally set this to a suitable
1892 value in their defconfig file.
1894 If ZBOOT_ROM is not enabled, this has no effect.
1896 config ZBOOT_ROM_BSS
1897 hex "Compressed ROM boot loader BSS address"
1900 The base address of an area of read/write memory in the target
1901 for the ROM-able zImage which must be available while the
1902 decompressor is running. It must be large enough to hold the
1903 entire decompressed kernel plus an additional 128 KiB.
1904 Platforms which normally make use of ROM-able zImage formats
1905 normally set this to a suitable value in their defconfig file.
1907 If ZBOOT_ROM is not enabled, this has no effect.
1910 bool "Compressed boot loader in ROM/flash"
1911 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1912 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1914 Say Y here if you intend to execute your compressed kernel image
1915 (zImage) directly from ROM or flash. If unsure, say N.
1917 config ARM_APPENDED_DTB
1918 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1921 With this option, the boot code will look for a device tree binary
1922 (DTB) appended to zImage
1923 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1925 This is meant as a backward compatibility convenience for those
1926 systems with a bootloader that can't be upgraded to accommodate
1927 the documented boot protocol using a device tree.
1929 Beware that there is very little in terms of protection against
1930 this option being confused by leftover garbage in memory that might
1931 look like a DTB header after a reboot if no actual DTB is appended
1932 to zImage. Do not leave this option active in a production kernel
1933 if you don't intend to always append a DTB. Proper passing of the
1934 location into r2 of a bootloader provided DTB is always preferable
1937 config ARM_ATAG_DTB_COMPAT
1938 bool "Supplement the appended DTB with traditional ATAG information"
1939 depends on ARM_APPENDED_DTB
1941 Some old bootloaders can't be updated to a DTB capable one, yet
1942 they provide ATAGs with memory configuration, the ramdisk address,
1943 the kernel cmdline string, etc. Such information is dynamically
1944 provided by the bootloader and can't always be stored in a static
1945 DTB. To allow a device tree enabled kernel to be used with such
1946 bootloaders, this option allows zImage to extract the information
1947 from the ATAG list and store it at run time into the appended DTB.
1950 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1951 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1953 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1954 bool "Use bootloader kernel arguments if available"
1956 Uses the command-line options passed by the boot loader instead of
1957 the device tree bootargs property. If the boot loader doesn't provide
1958 any, the device tree bootargs property will be used.
1960 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1961 bool "Extend with bootloader kernel arguments"
1963 The command-line arguments provided by the boot loader will be
1964 appended to the the device tree bootargs property.
1969 string "Default kernel command string"
1972 On some architectures (EBSA110 and CATS), there is currently no way
1973 for the boot loader to pass arguments to the kernel. For these
1974 architectures, you should supply some command-line options at build
1975 time by entering them here. As a minimum, you should specify the
1976 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1979 prompt "Kernel command line type" if CMDLINE != ""
1980 default CMDLINE_FROM_BOOTLOADER
1983 config CMDLINE_FROM_BOOTLOADER
1984 bool "Use bootloader kernel arguments if available"
1986 Uses the command-line options passed by the boot loader. If
1987 the boot loader doesn't provide any, the default kernel command
1988 string provided in CMDLINE will be used.
1990 config CMDLINE_EXTEND
1991 bool "Extend bootloader kernel arguments"
1993 The command-line arguments provided by the boot loader will be
1994 appended to the default kernel command string.
1996 config CMDLINE_FORCE
1997 bool "Always use the default kernel command string"
1999 Always use the default kernel command string, even if the boot
2000 loader passes other arguments to the kernel.
2001 This is useful if you cannot or don't want to change the
2002 command-line options your boot loader passes to the kernel.
2006 bool "Kernel Execute-In-Place from ROM"
2007 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2009 Execute-In-Place allows the kernel to run from non-volatile storage
2010 directly addressable by the CPU, such as NOR flash. This saves RAM
2011 space since the text section of the kernel is not loaded from flash
2012 to RAM. Read-write sections, such as the data section and stack,
2013 are still copied to RAM. The XIP kernel is not compressed since
2014 it has to run directly from flash, so it will take more space to
2015 store it. The flash address used to link the kernel object files,
2016 and for storing it, is configuration dependent. Therefore, if you
2017 say Y here, you must know the proper physical address where to
2018 store the kernel image depending on your own flash memory usage.
2020 Also note that the make target becomes "make xipImage" rather than
2021 "make zImage" or "make Image". The final kernel binary to put in
2022 ROM memory will be arch/arm/boot/xipImage.
2026 config XIP_PHYS_ADDR
2027 hex "XIP Kernel Physical Location"
2028 depends on XIP_KERNEL
2029 default "0x00080000"
2031 This is the physical address in your flash memory the kernel will
2032 be linked for and stored to. This address is dependent on your
2036 bool "Kexec system call (EXPERIMENTAL)"
2037 depends on (!SMP || PM_SLEEP_SMP)
2041 kexec is a system call that implements the ability to shutdown your
2042 current kernel, and to start another kernel. It is like a reboot
2043 but it is independent of the system firmware. And like a reboot
2044 you can start any kernel with it, not just Linux.
2046 It is an ongoing process to be certain the hardware in a machine
2047 is properly shutdown, so do not be surprised if this code does not
2048 initially work for you.
2051 bool "Export atags in procfs"
2052 depends on ATAGS && KEXEC
2055 Should the atags used to boot the kernel be exported in an "atags"
2056 file in procfs. Useful with kexec.
2059 bool "Build kdump crash kernel (EXPERIMENTAL)"
2061 Generate crash dump after being started by kexec. This should
2062 be normally only set in special crash dump kernels which are
2063 loaded in the main kernel with kexec-tools into a specially
2064 reserved region and then later executed after a crash by
2065 kdump/kexec. The crash dump kernel must be compiled to a
2066 memory address not used by the main kernel
2068 For more details see Documentation/kdump/kdump.txt
2070 config AUTO_ZRELADDR
2071 bool "Auto calculation of the decompressed kernel image address"
2073 ZRELADDR is the physical address where the decompressed kernel
2074 image will be placed. If AUTO_ZRELADDR is selected, the address
2075 will be determined at run-time by masking the current IP with
2076 0xf8000000. This assumes the zImage being placed in the first 128MB
2077 from start of memory.
2081 menu "CPU Power Management"
2083 source "drivers/cpufreq/Kconfig"
2085 source "drivers/cpuidle/Kconfig"
2089 menu "Floating point emulation"
2091 comment "At least one emulation must be selected"
2094 bool "NWFPE math emulation"
2095 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2097 Say Y to include the NWFPE floating point emulator in the kernel.
2098 This is necessary to run most binaries. Linux does not currently
2099 support floating point hardware so you need to say Y here even if
2100 your machine has an FPA or floating point co-processor podule.
2102 You may say N here if you are going to load the Acorn FPEmulator
2103 early in the bootup.
2106 bool "Support extended precision"
2107 depends on FPE_NWFPE
2109 Say Y to include 80-bit support in the kernel floating-point
2110 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2111 Note that gcc does not generate 80-bit operations by default,
2112 so in most cases this option only enlarges the size of the
2113 floating point emulator without any good reason.
2115 You almost surely want to say N here.
2118 bool "FastFPE math emulation (EXPERIMENTAL)"
2119 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2121 Say Y here to include the FAST floating point emulator in the kernel.
2122 This is an experimental much faster emulator which now also has full
2123 precision for the mantissa. It does not support any exceptions.
2124 It is very simple, and approximately 3-6 times faster than NWFPE.
2126 It should be sufficient for most programs. It may be not suitable
2127 for scientific calculations, but you have to check this for yourself.
2128 If you do not feel you need a faster FP emulation you should better
2132 bool "VFP-format floating point maths"
2133 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2135 Say Y to include VFP support code in the kernel. This is needed
2136 if your hardware includes a VFP unit.
2138 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2139 release notes and additional status information.
2141 Say N if your target does not have VFP hardware.
2149 bool "Advanced SIMD (NEON) Extension support"
2150 depends on VFPv3 && CPU_V7
2152 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2155 config KERNEL_MODE_NEON
2156 bool "Support for NEON in kernel mode"
2157 depends on NEON && AEABI
2159 Say Y to include support for NEON in kernel mode.
2163 menu "Userspace binary formats"
2165 source "fs/Kconfig.binfmt"
2169 menu "Power management options"
2171 source "kernel/power/Kconfig"
2173 config ARCH_SUSPEND_POSSIBLE
2174 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2175 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2178 config ARM_CPU_SUSPEND
2179 def_bool PM_SLEEP || BL_SWITCHER
2180 depends on ARCH_SUSPEND_POSSIBLE
2182 config ARCH_HIBERNATION_POSSIBLE
2185 default y if ARCH_SUSPEND_POSSIBLE
2189 source "net/Kconfig"
2191 source "drivers/Kconfig"
2193 source "drivers/firmware/Kconfig"
2197 source "arch/arm/Kconfig.debug"
2199 source "security/Kconfig"
2201 source "crypto/Kconfig"
2203 source "arch/arm/crypto/Kconfig"
2206 source "lib/Kconfig"
2208 source "arch/arm/kvm/Kconfig"