arch/arm/boot/dts/dra7.dtsi

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/dra.h>
  12
  13 #include "skeleton.dtsi"
  14
  15 #define MAX_SOURCES 400
  16 #define DIRECT_IRQ(irq) (MAX_SOURCES + irq)
  17
  18 / {
  19         #address-cells = <1>;
  20         #size-cells = <1>;
  21
  22         compatible = "ti,dra7xx";
  23         interrupt-parent = <&gic>;
  24
  25         aliases {
  26                 i2c0 = &i2c1;
  27                 i2c1 = &i2c2;
  28                 i2c2 = &i2c3;
  29                 i2c3 = &i2c4;
  30                 i2c4 = &i2c5;
  31                 serial0 = &uart1;
  32                 serial1 = &uart2;
  33                 serial2 = &uart3;
  34                 serial3 = &uart4;
  35                 serial4 = &uart5;
  36                 serial5 = &uart6;
  37                 serial6 = &uart7;
  38                 serial7 = &uart8;
  39                 serial8 = &uart9;
  40                 serial9 = &uart10;
  41                 ethernet0 = &cpsw_emac0;
  42                 ethernet1 = &cpsw_emac1;
  43         };
  44
  45         timer {
  46                 compatible = "arm,armv7-timer";
  47                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  48                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  49                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  50                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  51         };
  52
  53         gic: interrupt-controller@48211000 {
  54                 compatible = "arm,cortex-a15-gic";
  55                 interrupt-controller;
  56                 #interrupt-cells = <3>;
  57                 arm,routable-irqs = <192>;
  58                 reg = <0x48211000 0x1000>,
  59                       <0x48212000 0x1000>,
  60                       <0x48214000 0x2000>,
  61                       <0x48216000 0x2000>;
  62                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  63         };
  64
  65         /*
  66          * The soc node represents the soc top level view. It is used for IPs
  67          * that are not memory mapped in the MPU view or for the MPU itself.
  68          */
  69         soc {
  70                 compatible = "ti,omap-infra";
  71                 mpu {
  72                         compatible = "ti,omap5-mpu";
  73                         ti,hwmods = "mpu";
  74                 };
  75         };
  76
  77         /*
  78          * XXX: Use a flat representation of the SOC interconnect.
  79          * The real OMAP interconnect network is quite complex.
  80          * Since it will not bring real advantage to represent that in DT for
  81          * the moment, just use a fake OCP bus entry to represent the whole bus
  82          * hierarchy.
  83          */
  84         ocp {
  85                 compatible = "ti,dra7-l3-noc", "simple-bus";
  86                 #address-cells = <1>;
  87                 #size-cells = <1>;
  88                 ranges;
  89                 ti,hwmods = "l3_main_1", "l3_main_2";
  90                 reg = <0x44000000 0x1000000>,
  91                       <0x45000000 0x1000>;
  92                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
  93                              <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
  94
  95                 prm: prm@4ae06000 {
  96                         compatible = "ti,dra7-prm";
  97                         reg = <0x4ae06000 0x3000>;
  98                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  99
 100                         prm_clocks: clocks {
 101                                 #address-cells = <1>;
 102                                 #size-cells = <0>;
 103                         };
 104
 105                         prm_clockdomains: clockdomains {
 106                         };
 107                 };
 108
 109                 axi@0 {
 110                         compatible = "simple-bus";
 111                         #size-cells = <1>;
 112                         #address-cells = <1>;
 113                         ranges = <0x51000000 0x51000000 0x3000
 114                                   0x0        0x20000000 0x10000000>;
 115                         pcie@51000000 {
 116                                 compatible = "ti,dra7-pcie";
 117                                 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
 118                                 reg-names = "rc_dbics", "ti_conf", "config";
 119                                 interrupts = <0 232 0x4>, <0 233 0x4>;
 120                                 #address-cells = <3>;
 121                                 #size-cells = <2>;
 122                                 device_type = "pci";
 123                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 124                                           0x82000000 0 0x20013000 0x13000 0 0xffed000>;
 125                                 #interrupt-cells = <1>;
 126                                 num-lanes = <1>;
 127                                 ti,hwmods = "pcie1";
 128                                 phys = <&pcie1_phy>;
 129                                 phy-names = "pcie-phy0";
 130                                 interrupt-map-mask = <0 0 0 7>;
 131                                 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
 132                                                 <0 0 0 2 &pcie1_intc 2>,
 133                                                 <0 0 0 3 &pcie1_intc 3>,
 134                                                 <0 0 0 4 &pcie1_intc 4>;
 135                                 pcie1_intc: interrupt-controller {
 136                                         interrupt-controller;
 137                                         #address-cells = <0>;
 138                                         #interrupt-cells = <1>;
 139                                 };
 140                         };
 141                 };
 142
 143                 axi@1 {
 144                         compatible = "simple-bus";
 145                         #size-cells = <1>;
 146                         #address-cells = <1>;
 147                         ranges = <0x51800000 0x51800000 0x3000
 148                                   0x0        0x30000000 0x10000000>;
 149                         status = "disabled";
 150                         pcie@51000000 {
 151                                 compatible = "ti,dra7-pcie";
 152                                 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
 153                                 reg-names = "rc_dbics", "ti_conf", "config";
 154                                 interrupts = <0 355 0x4>, <0 356 0x4>;
 155                                 #address-cells = <3>;
 156                                 #size-cells = <2>;
 157                                 device_type = "pci";
 158                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 159                                           0x82000000 0 0x30013000 0x13000 0 0xffed000>;
 160                                 #interrupt-cells = <1>;
 161                                 num-lanes = <1>;
 162                                 ti,hwmods = "pcie2";
 163                                 phys = <&pcie2_phy>;
 164                                 phy-names = "pcie-phy0";
 165                                 interrupt-map-mask = <0 0 0 7>;
 166                                 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
 167                                                 <0 0 0 2 &pcie2_intc 2>,
 168                                                 <0 0 0 3 &pcie2_intc 3>,
 169                                                 <0 0 0 4 &pcie2_intc 4>;
 170                                 pcie2_intc: interrupt-controller {
 171                                         interrupt-controller;
 172                                         #address-cells = <0>;
 173                                         #interrupt-cells = <1>;
 174                                 };
 175                         };
 176                 };
 177
 178                 cm_core_aon: cm_core_aon@4a005000 {
 179                         compatible = "ti,dra7-cm-core-aon";
 180                         reg = <0x4a005000 0x2000>;
 181
 182                         cm_core_aon_clocks: clocks {
 183                                 #address-cells = <1>;
 184                                 #size-cells = <0>;
 185                         };
 186
 187                         cm_core_aon_clockdomains: clockdomains {
 188                         };
 189                 };
 190
 191                 cm_core: cm_core@4a008000 {
 192                         compatible = "ti,dra7-cm-core";
 193                         reg = <0x4a008000 0x3000>;
 194
 195                         cm_core_clocks: clocks {
 196                                 #address-cells = <1>;
 197                                 #size-cells = <0>;
 198                         };
 199
 200                         cm_core_clockdomains: clockdomains {
 201                         };
 202                 };
 203
 204                 counter32k: counter@4ae04000 {
 205                         compatible = "ti,omap-counter32k";
 206                         reg = <0x4ae04000 0x40>;
 207                         ti,hwmods = "counter_32k";
 208                 };
 209
 210                 dra7_ctrl_core: ctrl_core@4a002000 {
 211                         compatible = "syscon";
 212                         reg = <0x4a002000 0x6d0>;
 213                 };
 214
 215                 dra7_ctrl_general: tisyscon@4a002e00 {
 216                         compatible = "syscon";
 217                         reg = <0x4a002e00 0x7c>;
 218                 };
 219
 220                 pbias_regulator: pbias_regulator {
 221                         compatible = "ti,pbias-omap";
 222                         reg = <0 0x4>;
 223                         syscon = <&dra7_ctrl_general>;
 224                         pbias_mmc_reg: pbias_mmc_omap5 {
 225                                 regulator-name = "pbias_mmc_omap5";
 226                                 regulator-min-microvolt = <1800000>;
 227                                 regulator-max-microvolt = <3000000>;
 228                         };
 229                 };
 230
 231                 dra7_pmx_core: pinmux@4a003400 {
 232                         compatible = "ti,dra7-padconf", "pinctrl-single";
 233                         reg = <0x4a003400 0x0464>;
 234                         #address-cells = <1>;
 235                         #size-cells = <0>;
 236                         #interrupt-cells = <1>;
 237                         interrupt-controller;
 238                         pinctrl-single,register-width = <32>;
 239                         pinctrl-single,function-mask = <0x3fffffff>;
 240                 };
 241
 242                 sdma: dma-controller@4a056000 {
 243                         compatible = "ti,omap4430-sdma";
 244                         reg = <0x4a056000 0x1000>;
 245                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 246                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 247                                      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 248                                      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 249                         #dma-cells = <1>;
 250                         #dma-channels = <32>;
 251                         #dma-requests = <127>;
 252                 };
 253
 254                 gpio1: gpio@4ae10000 {
 255                         compatible = "ti,omap4-gpio";
 256                         reg = <0x4ae10000 0x200>;
 257                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 258                         ti,hwmods = "gpio1";
 259                         gpio-controller;
 260                         #gpio-cells = <2>;
 261                         interrupt-controller;
 262                         #interrupt-cells = <2>;
 263                 };
 264
 265                 gpio2: gpio@48055000 {
 266                         compatible = "ti,omap4-gpio";
 267                         reg = <0x48055000 0x200>;
 268                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 269                         ti,hwmods = "gpio2";
 270                         gpio-controller;
 271                         #gpio-cells = <2>;
 272                         interrupt-controller;
 273                         #interrupt-cells = <2>;
 274                 };
 275
 276                 gpio3: gpio@48057000 {
 277                         compatible = "ti,omap4-gpio";
 278                         reg = <0x48057000 0x200>;
 279                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 280                         ti,hwmods = "gpio3";
 281                         gpio-controller;
 282                         #gpio-cells = <2>;
 283                         interrupt-controller;
 284                         #interrupt-cells = <2>;
 285                 };
 286
 287                 gpio4: gpio@48059000 {
 288                         compatible = "ti,omap4-gpio";
 289                         reg = <0x48059000 0x200>;
 290                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 291                         ti,hwmods = "gpio4";
 292                         gpio-controller;
 293                         #gpio-cells = <2>;
 294                         interrupt-controller;
 295                         #interrupt-cells = <2>;
 296                 };
 297
 298                 gpio5: gpio@4805b000 {
 299                         compatible = "ti,omap4-gpio";
 300                         reg = <0x4805b000 0x200>;
 301                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 302                         ti,hwmods = "gpio5";
 303                         gpio-controller;
 304                         #gpio-cells = <2>;
 305                         interrupt-controller;
 306                         #interrupt-cells = <2>;
 307                 };
 308
 309                 gpio6: gpio@4805d000 {
 310                         compatible = "ti,omap4-gpio";
 311                         reg = <0x4805d000 0x200>;
 312                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 313                         ti,hwmods = "gpio6";
 314                         gpio-controller;
 315                         #gpio-cells = <2>;
 316                         interrupt-controller;
 317                         #interrupt-cells = <2>;
 318                 };
 319
 320                 gpio7: gpio@48051000 {
 321                         compatible = "ti,omap4-gpio";
 322                         reg = <0x48051000 0x200>;
 323                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 324                         ti,hwmods = "gpio7";
 325                         gpio-controller;
 326                         #gpio-cells = <2>;
 327                         interrupt-controller;
 328                         #interrupt-cells = <2>;
 329                 };
 330
 331                 gpio8: gpio@48053000 {
 332                         compatible = "ti,omap4-gpio";
 333                         reg = <0x48053000 0x200>;
 334                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 335                         ti,hwmods = "gpio8";
 336                         gpio-controller;
 337                         #gpio-cells = <2>;
 338                         interrupt-controller;
 339                         #interrupt-cells = <2>;
 340                 };
 341
 342                 uart1: serial@4806a000 {
 343                         compatible = "ti,omap4-uart";
 344                         reg = <0x4806a000 0x100>;
 345                         interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 346                         ti,hwmods = "uart1";
 347                         clock-frequency = <48000000>;
 348                         status = "disabled";
 349                         dmas = <&sdma 49>, <&sdma 50>;
 350                         dma-names = "tx", "rx";
 351                 };
 352
 353                 uart2: serial@4806c000 {
 354                         compatible = "ti,omap4-uart";
 355                         reg = <0x4806c000 0x100>;
 356                         interrupts-extended = <&gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 357                         ti,hwmods = "uart2";
 358                         clock-frequency = <48000000>;
 359                         status = "disabled";
 360                         dmas = <&sdma 51>, <&sdma 52>;
 361                         dma-names = "tx", "rx";
 362                 };
 363
 364                 uart3: serial@48020000 {
 365                         compatible = "ti,omap4-uart";
 366                         reg = <0x48020000 0x100>;
 367                         interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 368                         ti,hwmods = "uart3";
 369                         clock-frequency = <48000000>;
 370                         status = "disabled";
 371                         dmas = <&sdma 53>, <&sdma 54>;
 372                         dma-names = "tx", "rx";
 373                 };
 374
 375                 uart4: serial@4806e000 {
 376                         compatible = "ti,omap4-uart";
 377                         reg = <0x4806e000 0x100>;
 378                         interrupts-extended = <&gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 379                         ti,hwmods = "uart4";
 380                         clock-frequency = <48000000>;
 381                         status = "disabled";
 382                         dmas = <&sdma 55>, <&sdma 56>;
 383                         dma-names = "tx", "rx";
 384                 };
 385
 386                 uart5: serial@48066000 {
 387                         compatible = "ti,omap4-uart";
 388                         reg = <0x48066000 0x100>;
 389                         interrupts-extended = <&gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 390                         ti,hwmods = "uart5";
 391                         clock-frequency = <48000000>;
 392                         status = "disabled";
 393                         dmas = <&sdma 63>, <&sdma 64>;
 394                         dma-names = "tx", "rx";
 395                 };
 396
 397                 uart6: serial@48068000 {
 398                         compatible = "ti,omap4-uart";
 399                         reg = <0x48068000 0x100>;
 400                         interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 401                         ti,hwmods = "uart6";
 402                         clock-frequency = <48000000>;
 403                         status = "disabled";
 404                         dmas = <&sdma 79>, <&sdma 80>;
 405                         dma-names = "tx", "rx";
 406                 };
 407
 408                 uart7: serial@48420000 {
 409                         compatible = "ti,omap4-uart";
 410                         reg = <0x48420000 0x100>;
 411                         interrupts-extended = <&gic GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
 412                         ti,hwmods = "uart7";
 413                         clock-frequency = <48000000>;
 414                         status = "disabled";
 415                 };
 416
 417                 uart8: serial@48422000 {
 418                         compatible = "ti,omap4-uart";
 419                         reg = <0x48422000 0x100>;
 420                         interrupts-extended = <&gic GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
 421                         ti,hwmods = "uart8";
 422                         clock-frequency = <48000000>;
 423                         status = "disabled";
 424                 };
 425
 426                 uart9: serial@48424000 {
 427                         compatible = "ti,omap4-uart";
 428                         reg = <0x48424000 0x100>;
 429                         interrupts-extended = <&gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 430                         ti,hwmods = "uart9";
 431                         clock-frequency = <48000000>;
 432                         status = "disabled";
 433                 };
 434
 435                 uart10: serial@4ae2b000 {
 436                         compatible = "ti,omap4-uart";
 437                         reg = <0x4ae2b000 0x100>;
 438                         interrupts-extended = <&gic GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 439                         ti,hwmods = "uart10";
 440                         clock-frequency = <48000000>;
 441                         status = "disabled";
 442                 };
 443
 444                 mailbox1: mailbox@4a0f4000 {
 445                         compatible = "ti,omap4-mailbox";
 446                         reg = <0x4a0f4000 0x200>;
 447                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 448                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 449                                      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 450                         ti,hwmods = "mailbox1";
 451                         #mbox-cells = <1>;
 452                         ti,mbox-num-users = <3>;
 453                         ti,mbox-num-fifos = <8>;
 454                         status = "disabled";
 455                 };
 456
 457                 mailbox2: mailbox@4883a000 {
 458                         compatible = "ti,omap4-mailbox";
 459                         reg = <0x4883a000 0x200>;
 460                         interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
 461                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
 462                                      <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
 463                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 464                         ti,hwmods = "mailbox2";
 465                         #mbox-cells = <1>;
 466                         ti,mbox-num-users = <4>;
 467                         ti,mbox-num-fifos = <12>;
 468                         status = "disabled";
 469                 };
 470
 471                 mailbox3: mailbox@4883c000 {
 472                         compatible = "ti,omap4-mailbox";
 473                         reg = <0x4883c000 0x200>;
 474                         interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
 475                                      <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
 476                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
 477                                      <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
 478                         ti,hwmods = "mailbox3";
 479                         #mbox-cells = <1>;
 480                         ti,mbox-num-users = <4>;
 481                         ti,mbox-num-fifos = <12>;
 482                         status = "disabled";
 483                 };
 484
 485                 mailbox4: mailbox@4883e000 {
 486                         compatible = "ti,omap4-mailbox";
 487                         reg = <0x4883e000 0x200>;
 488                         interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 489                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 490                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 491                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
 492                         ti,hwmods = "mailbox4";
 493                         #mbox-cells = <1>;
 494                         ti,mbox-num-users = <4>;
 495                         ti,mbox-num-fifos = <12>;
 496                         status = "disabled";
 497                 };
 498
 499                 mailbox5: mailbox@48840000 {
 500                         compatible = "ti,omap4-mailbox";
 501                         reg = <0x48840000 0x200>;
 502                         interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 503                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 504                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 505                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
 506                         ti,hwmods = "mailbox5";
 507                         #mbox-cells = <1>;
 508                         ti,mbox-num-users = <4>;
 509                         ti,mbox-num-fifos = <12>;
 510                         status = "disabled";
 511                 };
 512
 513                 mailbox6: mailbox@48842000 {
 514                         compatible = "ti,omap4-mailbox";
 515                         reg = <0x48842000 0x200>;
 516                         interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 517                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 518                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 519                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
 520                         ti,hwmods = "mailbox6";
 521                         #mbox-cells = <1>;
 522                         ti,mbox-num-users = <4>;
 523                         ti,mbox-num-fifos = <12>;
 524                         status = "disabled";
 525                 };
 526
 527                 mailbox7: mailbox@48844000 {
 528                         compatible = "ti,omap4-mailbox";
 529                         reg = <0x48844000 0x200>;
 530                         interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
 531                                      <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
 532                                      <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
 533                                      <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
 534                         ti,hwmods = "mailbox7";
 535                         #mbox-cells = <1>;
 536                         ti,mbox-num-users = <4>;
 537                         ti,mbox-num-fifos = <12>;
 538                         status = "disabled";
 539                 };
 540
 541                 mailbox8: mailbox@48846000 {
 542                         compatible = "ti,omap4-mailbox";
 543                         reg = <0x48846000 0x200>;
 544                         interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 545                                      <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
 546                                      <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
 547                                      <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
 548                         ti,hwmods = "mailbox8";
 549                         #mbox-cells = <1>;
 550                         ti,mbox-num-users = <4>;
 551                         ti,mbox-num-fifos = <12>;
 552                         status = "disabled";
 553                 };
 554
 555                 mailbox9: mailbox@4885e000 {
 556                         compatible = "ti,omap4-mailbox";
 557                         reg = <0x4885e000 0x200>;
 558                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
 559                                      <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
 560                                      <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
 561                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 562                         ti,hwmods = "mailbox9";
 563                         #mbox-cells = <1>;
 564                         ti,mbox-num-users = <4>;
 565                         ti,mbox-num-fifos = <12>;
 566                         status = "disabled";
 567                 };
 568
 569                 mailbox10: mailbox@48860000 {
 570                         compatible = "ti,omap4-mailbox";
 571                         reg = <0x48860000 0x200>;
 572                         interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
 573                                      <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
 574                                      <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
 575                                      <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 576                         ti,hwmods = "mailbox10";
 577                         #mbox-cells = <1>;
 578                         ti,mbox-num-users = <4>;
 579                         ti,mbox-num-fifos = <12>;
 580                         status = "disabled";
 581                 };
 582
 583                 mailbox11: mailbox@48862000 {
 584                         compatible = "ti,omap4-mailbox";
 585                         reg = <0x48862000 0x200>;
 586                         interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
 587                                      <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
 588                                      <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
 589                                      <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
 590                         ti,hwmods = "mailbox11";
 591                         #mbox-cells = <1>;
 592                         ti,mbox-num-users = <4>;
 593                         ti,mbox-num-fifos = <12>;
 594                         status = "disabled";
 595                 };
 596
 597                 mailbox12: mailbox@48864000 {
 598                         compatible = "ti,omap4-mailbox";
 599                         reg = <0x48864000 0x200>;
 600                         interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
 601                                      <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
 602                                      <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
 603                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
 604                         ti,hwmods = "mailbox12";
 605                         #mbox-cells = <1>;
 606                         ti,mbox-num-users = <4>;
 607                         ti,mbox-num-fifos = <12>;
 608                         status = "disabled";
 609                 };
 610
 611                 mailbox13: mailbox@48802000 {
 612                         compatible = "ti,omap4-mailbox";
 613                         reg = <0x48802000 0x200>;
 614                         interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
 615                                      <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
 616                                      <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
 617                                      <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
 618                         ti,hwmods = "mailbox13";
 619                         #mbox-cells = <1>;
 620                         ti,mbox-num-users = <4>;
 621                         ti,mbox-num-fifos = <12>;
 622                         status = "disabled";
 623                 };
 624
 625                 timer1: timer@4ae18000 {
 626                         compatible = "ti,omap5430-timer";
 627                         reg = <0x4ae18000 0x80>;
 628                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 629                         ti,hwmods = "timer1";
 630                         ti,timer-alwon;
 631                 };
 632
 633                 timer2: timer@48032000 {
 634                         compatible = "ti,omap5430-timer";
 635                         reg = <0x48032000 0x80>;
 636                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 637                         ti,hwmods = "timer2";
 638                 };
 639
 640                 timer3: timer@48034000 {
 641                         compatible = "ti,omap5430-timer";
 642                         reg = <0x48034000 0x80>;
 643                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 644                         ti,hwmods = "timer3";
 645                 };
 646
 647                 timer4: timer@48036000 {
 648                         compatible = "ti,omap5430-timer";
 649                         reg = <0x48036000 0x80>;
 650                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 651                         ti,hwmods = "timer4";
 652                 };
 653
 654                 timer5: timer@48820000 {
 655                         compatible = "ti,omap5430-timer";
 656                         reg = <0x48820000 0x80>;
 657                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 658                         ti,hwmods = "timer5";
 659                         ti,timer-dsp;
 660                 };
 661
 662                 timer6: timer@48822000 {
 663                         compatible = "ti,omap5430-timer";
 664                         reg = <0x48822000 0x80>;
 665                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 666                         ti,hwmods = "timer6";
 667                         ti,timer-dsp;
 668                         ti,timer-pwm;
 669                 };
 670
 671                 timer7: timer@48824000 {
 672                         compatible = "ti,omap5430-timer";
 673                         reg = <0x48824000 0x80>;
 674                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 675                         ti,hwmods = "timer7";
 676                         ti,timer-dsp;
 677                 };
 678
 679                 timer8: timer@48826000 {
 680                         compatible = "ti,omap5430-timer";
 681                         reg = <0x48826000 0x80>;
 682                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 683                         ti,hwmods = "timer8";
 684                         ti,timer-dsp;
 685                         ti,timer-pwm;
 686                 };
 687
 688                 timer9: timer@4803e000 {
 689                         compatible = "ti,omap5430-timer";
 690                         reg = <0x4803e000 0x80>;
 691                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 692                         ti,hwmods = "timer9";
 693                 };
 694
 695                 timer10: timer@48086000 {
 696                         compatible = "ti,omap5430-timer";
 697                         reg = <0x48086000 0x80>;
 698                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 699                         ti,hwmods = "timer10";
 700                 };
 701
 702                 timer11: timer@48088000 {
 703                         compatible = "ti,omap5430-timer";
 704                         reg = <0x48088000 0x80>;
 705                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 706                         ti,hwmods = "timer11";
 707                         ti,timer-pwm;
 708                 };
 709
 710                 timer13: timer@48828000 {
 711                         compatible = "ti,omap5430-timer";
 712                         reg = <0x48828000 0x80>;
 713                         interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
 714                         ti,hwmods = "timer13";
 715                         status = "disabled";
 716                 };
 717
 718                 timer14: timer@4882a000 {
 719                         compatible = "ti,omap5430-timer";
 720                         reg = <0x4882a000 0x80>;
 721                         interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
 722                         ti,hwmods = "timer14";
 723                         status = "disabled";
 724                 };
 725
 726                 timer15: timer@4882c000 {
 727                         compatible = "ti,omap5430-timer";
 728                         reg = <0x4882c000 0x80>;
 729                         interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
 730                         ti,hwmods = "timer15";
 731                         status = "disabled";
 732                 };
 733
 734                 timer16: timer@4882e000 {
 735                         compatible = "ti,omap5430-timer";
 736                         reg = <0x4882e000 0x80>;
 737                         interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
 738                         ti,hwmods = "timer16";
 739                         status = "disabled";
 740                 };
 741
 742                 wdt2: wdt@4ae14000 {
 743                         compatible = "ti,omap4-wdt";
 744                         reg = <0x4ae14000 0x80>;
 745                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 746                         ti,hwmods = "wd_timer2";
 747                 };
 748
 749                 hwspinlock: spinlock@4a0f6000 {
 750                         compatible = "ti,omap4-hwspinlock";
 751                         reg = <0x4a0f6000 0x1000>;
 752                         ti,hwmods = "spinlock";
 753                         #hwlock-cells = <1>;
 754                 };
 755
 756                 dmm@4e000000 {
 757                         compatible = "ti,omap5-dmm";
 758                         reg = <0x4e000000 0x800>;
 759                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 760                         ti,hwmods = "dmm";
 761                 };
 762
 763                 i2c1: i2c@48070000 {
 764                         compatible = "ti,omap4-i2c";
 765                         reg = <0x48070000 0x100>;
 766                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 767                         #address-cells = <1>;
 768                         #size-cells = <0>;
 769                         ti,hwmods = "i2c1";
 770                         status = "disabled";
 771                 };
 772
 773                 i2c2: i2c@48072000 {
 774                         compatible = "ti,omap4-i2c";
 775                         reg = <0x48072000 0x100>;
 776                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 777                         #address-cells = <1>;
 778                         #size-cells = <0>;
 779                         ti,hwmods = "i2c2";
 780                         status = "disabled";
 781                 };
 782
 783                 i2c3: i2c@48060000 {
 784                         compatible = "ti,omap4-i2c";
 785                         reg = <0x48060000 0x100>;
 786                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 787                         #address-cells = <1>;
 788                         #size-cells = <0>;
 789                         ti,hwmods = "i2c3";
 790                         status = "disabled";
 791                 };
 792
 793                 i2c4: i2c@4807a000 {
 794                         compatible = "ti,omap4-i2c";
 795                         reg = <0x4807a000 0x100>;
 796                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 797                         #address-cells = <1>;
 798                         #size-cells = <0>;
 799                         ti,hwmods = "i2c4";
 800                         status = "disabled";
 801                 };
 802
 803                 i2c5: i2c@4807c000 {
 804                         compatible = "ti,omap4-i2c";
 805                         reg = <0x4807c000 0x100>;
 806                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 807                         #address-cells = <1>;
 808                         #size-cells = <0>;
 809                         ti,hwmods = "i2c5";
 810                         status = "disabled";
 811                 };
 812
 813                 mmc1: mmc@4809c000 {
 814                         compatible = "ti,omap4-hsmmc";
 815                         reg = <0x4809c000 0x400>;
 816                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 817                         ti,hwmods = "mmc1";
 818                         ti,dual-volt;
 819                         ti,needs-special-reset;
 820                         dmas = <&sdma 61>, <&sdma 62>;
 821                         dma-names = "tx", "rx";
 822                         status = "disabled";
 823                         pbias-supply = <&pbias_mmc_reg>;
 824                 };
 825
 826                 mmc2: mmc@480b4000 {
 827                         compatible = "ti,omap4-hsmmc";
 828                         reg = <0x480b4000 0x400>;
 829                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 830                         ti,hwmods = "mmc2";
 831                         ti,needs-special-reset;
 832                         dmas = <&sdma 47>, <&sdma 48>;
 833                         dma-names = "tx", "rx";
 834                         status = "disabled";
 835                 };
 836
 837                 mmc3: mmc@480ad000 {
 838                         compatible = "ti,omap4-hsmmc";
 839                         reg = <0x480ad000 0x400>;
 840                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 841                         ti,hwmods = "mmc3";
 842                         ti,needs-special-reset;
 843                         dmas = <&sdma 77>, <&sdma 78>;
 844                         dma-names = "tx", "rx";
 845                         status = "disabled";
 846                 };
 847
 848                 mmc4: mmc@480d1000 {
 849                         compatible = "ti,omap4-hsmmc";
 850                         reg = <0x480d1000 0x400>;
 851                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 852                         ti,hwmods = "mmc4";
 853                         ti,needs-special-reset;
 854                         dmas = <&sdma 57>, <&sdma 58>;
 855                         dma-names = "tx", "rx";
 856                         status = "disabled";
 857                 };
 858
 859                 abb_mpu: regulator-abb-mpu {
 860                         compatible = "ti,abb-v3";
 861                         regulator-name = "abb_mpu";
 862                         #address-cells = <0>;
 863                         #size-cells = <0>;
 864                         clocks = <&sys_clkin1>;
 865                         ti,settling-time = <50>;
 866                         ti,clock-cycles = <16>;
 867
 868                         reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
 869                               <0x4ae06014 0x4>, <0x4a003b20 0x8>,
 870                               <0x4ae0c158 0x4>;
 871                         reg-names = "setup-address", "control-address",
 872                                     "int-address", "efuse-address",
 873                                     "ldo-address";
 874                         ti,tranxdone-status-mask = <0x80>;
 875                         /* LDOVBBMPU_FBB_MUX_CTRL */
 876                         ti,ldovbb-override-mask = <0x400>;
 877                         /* LDOVBBMPU_FBB_VSET_OUT */
 878                         ti,ldovbb-vset-mask = <0x1F>;
 879
 880                         /*
 881                          * NOTE: only FBB mode used but actual vset will
 882                          * determine final biasing
 883                          */
 884                         ti,abb_info = <
 885                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 886                         1060000         0       0x0     0 0x02000000 0x01F00000
 887                         1160000         0       0x4     0 0x02000000 0x01F00000
 888                         1210000         0       0x8     0 0x02000000 0x01F00000
 889                         >;
 890                 };
 891
 892                 abb_ivahd: regulator-abb-ivahd {
 893                         compatible = "ti,abb-v3";
 894                         regulator-name = "abb_ivahd";
 895                         #address-cells = <0>;
 896                         #size-cells = <0>;
 897                         clocks = <&sys_clkin1>;
 898                         ti,settling-time = <50>;
 899                         ti,clock-cycles = <16>;
 900
 901                         reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
 902                               <0x4ae06010 0x4>, <0x4a0025cc 0x8>,
 903                               <0x4a002470 0x4>;
 904                         reg-names = "setup-address", "control-address",
 905                                     "int-address", "efuse-address",
 906                                     "ldo-address";
 907                         ti,tranxdone-status-mask = <0x40000000>;
 908                         /* LDOVBBIVA_FBB_MUX_CTRL */
 909                         ti,ldovbb-override-mask = <0x400>;
 910                         /* LDOVBBIVA_FBB_VSET_OUT */
 911                         ti,ldovbb-vset-mask = <0x1F>;
 912
 913                         /*
 914                          * NOTE: only FBB mode used but actual vset will
 915                          * determine final biasing
 916                          */
 917                         ti,abb_info = <
 918                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 919                         1055000         0       0x0     0 0x02000000 0x01F00000
 920                         1150000         0       0x4     0 0x02000000 0x01F00000
 921                         1250000         0       0x8     0 0x02000000 0x01F00000
 922                         >;
 923                 };
 924
 925                 abb_dspeve: regulator-abb-dspeve {
 926                         compatible = "ti,abb-v3";
 927                         regulator-name = "abb_dspeve";
 928                         #address-cells = <0>;
 929                         #size-cells = <0>;
 930                         clocks = <&sys_clkin1>;
 931                         ti,settling-time = <50>;
 932                         ti,clock-cycles = <16>;
 933
 934                         reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
 935                               <0x4ae06010 0x4>, <0x4a0025e0 0x8>,
 936                               <0x4a00246c 0x4>;
 937                         reg-names = "setup-address", "control-address",
 938                                     "int-address", "efuse-address",
 939                                     "ldo-address";
 940                         ti,tranxdone-status-mask = <0x20000000>;
 941                         /* LDOVBBDSPEVE_FBB_MUX_CTRL */
 942                         ti,ldovbb-override-mask = <0x400>;
 943                         /* LDOVBBDSPEVE_FBB_VSET_OUT */
 944                         ti,ldovbb-vset-mask = <0x1F>;
 945
 946                         /*
 947                          * NOTE: only FBB mode used but actual vset will
 948                          * determine final biasing
 949                          */
 950                         ti,abb_info = <
 951                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 952                         1055000         0       0x0     0 0x02000000 0x01F00000
 953                         1150000         0       0x4     0 0x02000000 0x01F00000
 954                         1250000         0       0x8     0 0x02000000 0x01F00000
 955                         >;
 956                 };
 957
 958                 abb_gpu: regulator-abb-gpu {
 959                         compatible = "ti,abb-v3";
 960                         regulator-name = "abb_gpu";
 961                         #address-cells = <0>;
 962                         #size-cells = <0>;
 963                         clocks = <&sys_clkin1>;
 964                         ti,settling-time = <50>;
 965                         ti,clock-cycles = <16>;
 966
 967                         reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
 968                               <0x4ae06010 0x4>, <0x4a003b08 0x8>,
 969                               <0x4ae0c154 0x4>;
 970                         reg-names = "setup-address", "control-address",
 971                                     "int-address", "efuse-address",
 972                                     "ldo-address";
 973                         ti,tranxdone-status-mask = <0x10000000>;
 974                         /* LDOVBBGPU_FBB_MUX_CTRL */
 975                         ti,ldovbb-override-mask = <0x400>;
 976                         /* LDOVBBGPU_FBB_VSET_OUT */
 977                         ti,ldovbb-vset-mask = <0x1F>;
 978
 979                         /*
 980                          * NOTE: only FBB mode used but actual vset will
 981                          * determine final biasing
 982                          */
 983                         ti,abb_info = <
 984                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 985                         1090000         0       0x0     0 0x02000000 0x01F00000
 986                         1210000         0       0x4     0 0x02000000 0x01F00000
 987                         1280000         0       0x8     0 0x02000000 0x01F00000
 988                         >;
 989                 };
 990
 991                 mcspi1: spi@48098000 {
 992                         compatible = "ti,omap4-mcspi";
 993                         reg = <0x48098000 0x200>;
 994                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 995                         #address-cells = <1>;
 996                         #size-cells = <0>;
 997                         ti,hwmods = "mcspi1";
 998                         ti,spi-num-cs = <4>;
 999                         dmas = <&sdma 35>,
1000                                <&sdma 36>,
1001                                <&sdma 37>,
1002                                <&sdma 38>,
1003                                <&sdma 39>,
1004                                <&sdma 40>,
1005                                <&sdma 41>,
1006                                <&sdma 42>;
1007                         dma-names = "tx0", "rx0", "tx1", "rx1",
1008                                     "tx2", "rx2", "tx3", "rx3";
1009                         status = "disabled";
1010                 };
1011
1012                 mcspi2: spi@4809a000 {
1013                         compatible = "ti,omap4-mcspi";
1014                         reg = <0x4809a000 0x200>;
1015                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1016                         #address-cells = <1>;
1017                         #size-cells = <0>;
1018                         ti,hwmods = "mcspi2";
1019                         ti,spi-num-cs = <2>;
1020                         dmas = <&sdma 43>,
1021                                <&sdma 44>,
1022                                <&sdma 45>,
1023                                <&sdma 46>;
1024                         dma-names = "tx0", "rx0", "tx1", "rx1";
1025                         status = "disabled";
1026                 };
1027
1028                 mcspi3: spi@480b8000 {
1029                         compatible = "ti,omap4-mcspi";
1030                         reg = <0x480b8000 0x200>;
1031                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1032                         #address-cells = <1>;
1033                         #size-cells = <0>;
1034                         ti,hwmods = "mcspi3";
1035                         ti,spi-num-cs = <2>;
1036                         dmas = <&sdma 15>, <&sdma 16>;
1037                         dma-names = "tx0", "rx0";
1038                         status = "disabled";
1039                 };
1040
1041                 mcspi4: spi@480ba000 {
1042                         compatible = "ti,omap4-mcspi";
1043                         reg = <0x480ba000 0x200>;
1044                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1045                         #address-cells = <1>;
1046                         #size-cells = <0>;
1047                         ti,hwmods = "mcspi4";
1048                         ti,spi-num-cs = <1>;
1049                         dmas = <&sdma 70>, <&sdma 71>;
1050                         dma-names = "tx0", "rx0";
1051                         status = "disabled";
1052                 };
1053
1054                 qspi: qspi@4b300000 {
1055                         compatible = "ti,dra7xxx-qspi";
1056                         reg = <0x4b300000 0x100>;
1057                         reg-names = "qspi_base";
1058                         #address-cells = <1>;
1059                         #size-cells = <0>;
1060                         ti,hwmods = "qspi";
1061                         clocks = <&qspi_gfclk_div>;
1062                         clock-names = "fck";
1063                         num-cs = <4>;
1064                         interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1065                         status = "disabled";
1066                 };
1067
1068                 omap_control_sata: control-phy@4a002374 {
1069                         compatible = "ti,control-phy-pipe3";
1070                         reg = <0x4a002374 0x4>;
1071                         reg-names = "power";
1072                         clocks = <&sys_clkin1>;
1073                         clock-names = "sysclk";
1074                 };
1075
1076                 /* OCP2SCP3 */
1077                 ocp2scp@4a090000 {
1078                         compatible = "ti,omap-ocp2scp";
1079                         #address-cells = <1>;
1080                         #size-cells = <1>;
1081                         ranges;
1082                         reg = <0x4a090000 0x20>;
1083                         ti,hwmods = "ocp2scp3";
1084                         sata_phy: phy@4A096000 {
1085                                 compatible = "ti,phy-pipe3-sata";
1086                                 reg = <0x4A096000 0x80>, /* phy_rx */
1087                                       <0x4A096400 0x64>, /* phy_tx */
1088                                       <0x4A096800 0x40>; /* pll_ctrl */
1089                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1090                                 ctrl-module = <&omap_control_sata>;
1091                                 clocks = <&sys_clkin1>;
1092                                 clock-names = "sysclk";
1093                                 #phy-cells = <0>;
1094                         };
1095
1096                         pcie1_phy: pciephy@4a094000 {
1097                                 compatible = "ti,phy-pipe3-pcie";
1098                                 reg = <0x4a094000 0x80>, /* phy_rx */
1099                                       <0x4a094400 0x64>; /* phy_tx */
1100                                 reg-names = "phy_rx", "phy_tx";
1101                                 ctrl-module = <&omap_control_pcie1phy>;
1102                                 clocks = <&dpll_pcie_ref_ck>,
1103                                          <&dpll_pcie_ref_m2ldo_ck>,
1104                                          <&optfclk_pciephy1_32khz>,
1105                                          <&optfclk_pciephy1_clk>,
1106                                          <&optfclk_pciephy1_div_clk>,
1107                                          <&optfclk_pciephy_div>;
1108                                 clock-names = "dpll_ref", "dpll_ref_m2",
1109                                               "wkupclk", "refclk",
1110                                               "div-clk", "phy-div";
1111                                 #phy-cells = <0>;
1112                                 id = <1>;
1113                                 ti,hwmods = "pcie1-phy";
1114                         };
1115
1116                         pcie2_phy: pciephy@4a095000 {
1117                                 compatible = "ti,phy-pipe3-pcie";
1118                                 reg = <0x4a095000 0x80>, /* phy_rx */
1119                                       <0x4a095400 0x64>; /* phy_tx */
1120                                 reg-names = "phy_rx", "phy_tx";
1121                                 ctrl-module = <&omap_control_pcie2phy>;
1122                                 clocks = <&dpll_pcie_ref_ck>,
1123                                          <&dpll_pcie_ref_m2ldo_ck>,
1124                                          <&optfclk_pciephy2_32khz>,
1125                                          <&optfclk_pciephy2_clk>,
1126                                          <&optfclk_pciephy2_div_clk>,
1127                                          <&optfclk_pciephy_div>;
1128                                 clock-names = "dpll_ref", "dpll_ref_m2",
1129                                               "wkupclk", "refclk",
1130                                               "div-clk", "phy-div";
1131                                 #phy-cells = <0>;
1132                                 ti,hwmods = "pcie2-phy";
1133                                 id = <2>;
1134                                 status = "disabled";
1135                         };
1136                 };
1137
1138                 sata: sata@4a141100 {
1139                         compatible = "snps,dwc-ahci";
1140                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1141                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1142                         phys = <&sata_phy>;
1143                         phy-names = "sata-phy";
1144                         clocks = <&sata_ref_clk>;
1145                         ti,hwmods = "sata";
1146                 };
1147
1148                 omap_control_pcie1phy: control-phy@0x4a003c40 {
1149                         compatible = "ti,control-phy-pcie";
1150                         reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1151                         reg-names = "power", "control_sma", "pcie_pcs";
1152                         clocks = <&sys_clkin1>;
1153                         clock-names = "sysclk";
1154                 };
1155
1156                 omap_control_pcie2phy: control-pcie@0x4a003c44 {
1157                         compatible = "ti,control-phy-pcie";
1158                         reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1159                         reg-names = "power", "control_sma", "pcie_pcs";
1160                         clocks = <&sys_clkin1>;
1161                         clock-names = "sysclk";
1162                         status = "disabled";
1163                 };
1164
1165                 rtc@48838000 {
1166                         compatible = "ti,am3352-rtc";
1167                         reg = <0x48838000 0x100>;
1168                         interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1169                                      <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1170                         ti,hwmods = "rtcss";
1171                         clocks = <&sys_32k_ck>;
1172                 };
1173
1174                 omap_control_usb2phy1: control-phy@4a002300 {
1175                         compatible = "ti,control-phy-usb2";
1176                         reg = <0x4a002300 0x4>;
1177                         reg-names = "power";
1178                 };
1179
1180                 omap_control_usb3phy1: control-phy@4a002370 {
1181                         compatible = "ti,control-phy-pipe3";
1182                         reg = <0x4a002370 0x4>;
1183                         reg-names = "power";
1184                 };
1185
1186                 omap_control_usb2phy2: control-phy@0x4a002e74 {
1187                         compatible = "ti,control-phy-usb2-dra7";
1188                         reg = <0x4a002e74 0x4>;
1189                         reg-names = "power";
1190                 };
1191
1192                 /* OCP2SCP1 */
1193                 ocp2scp@4a080000 {
1194                         compatible = "ti,omap-ocp2scp";
1195                         #address-cells = <1>;
1196                         #size-cells = <1>;
1197                         ranges;
1198                         reg = <0x4a080000 0x20>;
1199                         ti,hwmods = "ocp2scp1";
1200
1201                         usb2_phy1: phy@4a084000 {
1202                                 compatible = "ti,omap-usb2";
1203                                 reg = <0x4a084000 0x400>;
1204                                 ctrl-module = <&omap_control_usb2phy1>;
1205                                 clocks = <&usb_phy1_always_on_clk32k>,
1206                                          <&usb_otg_ss1_refclk960m>;
1207                                 clock-names =   "wkupclk",
1208                                                 "refclk";
1209                                 #phy-cells = <0>;
1210                         };
1211
1212                         usb2_phy2: phy@4a085000 {
1213                                 compatible = "ti,omap-usb2";
1214                                 reg = <0x4a085000 0x400>;
1215                                 ctrl-module = <&omap_control_usb2phy2>;
1216                                 clocks = <&usb_phy2_always_on_clk32k>,
1217                                          <&usb_otg_ss2_refclk960m>;
1218                                 clock-names =   "wkupclk",
1219                                                 "refclk";
1220                                 #phy-cells = <0>;
1221                         };
1222
1223                         usb3_phy1: phy@4a084400 {
1224                                 compatible = "ti,omap-usb3";
1225                                 reg = <0x4a084400 0x80>,
1226                                       <0x4a084800 0x64>,
1227                                       <0x4a084c00 0x40>;
1228                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1229                                 ctrl-module = <&omap_control_usb3phy1>;
1230                                 clocks = <&usb_phy3_always_on_clk32k>,
1231                                          <&sys_clkin1>,
1232                                          <&usb_otg_ss1_refclk960m>;
1233                                 clock-names =   "wkupclk",
1234                                                 "sysclk",
1235                                                 "refclk";
1236                                 #phy-cells = <0>;
1237                         };
1238                 };
1239
1240                 omap_dwc3_1: omap_dwc3_1@48880000 {
1241                         compatible = "ti,dwc3";
1242                         ti,hwmods = "usb_otg_ss1";
1243                         reg = <0x48880000 0x10000>;
1244                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1245                         #address-cells = <1>;
1246                         #size-cells = <1>;
1247                         utmi-mode = <2>;
1248                         ranges;
1249                         usb1: usb@48890000 {
1250                                 compatible = "snps,dwc3";
1251                                 reg = <0x48890000 0x17000>;
1252                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1253                                 phys = <&usb2_phy1>, <&usb3_phy1>;
1254                                 phy-names = "usb2-phy", "usb3-phy";
1255                                 tx-fifo-resize;
1256                                 maximum-speed = "super-speed";
1257                                 dr_mode = "otg";
1258                         };
1259                 };
1260
1261                 omap_dwc3_2: omap_dwc3_2@488c0000 {
1262                         compatible = "ti,dwc3";
1263                         ti,hwmods = "usb_otg_ss2";
1264                         reg = <0x488c0000 0x10000>;
1265                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1266                         #address-cells = <1>;
1267                         #size-cells = <1>;
1268                         utmi-mode = <2>;
1269                         ranges;
1270                         usb2: usb@488d0000 {
1271                                 compatible = "snps,dwc3";
1272                                 reg = <0x488d0000 0x17000>;
1273                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1274                                 phys = <&usb2_phy2>;
1275                                 phy-names = "usb2-phy";
1276                                 tx-fifo-resize;
1277                                 maximum-speed = "high-speed";
1278                                 dr_mode = "otg";
1279                         };
1280                 };
1281
1282                 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1283                 omap_dwc3_3: omap_dwc3_3@48900000 {
1284                         compatible = "ti,dwc3";
1285                         ti,hwmods = "usb_otg_ss3";
1286                         reg = <0x48900000 0x10000>;
1287                         interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1288                         #address-cells = <1>;
1289                         #size-cells = <1>;
1290                         utmi-mode = <2>;
1291                         ranges;
1292                         status = "disabled";
1293                         usb3: usb@48910000 {
1294                                 compatible = "snps,dwc3";
1295                                 reg = <0x48910000 0x17000>;
1296                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1297                                 tx-fifo-resize;
1298                                 maximum-speed = "high-speed";
1299                                 dr_mode = "otg";
1300                         };
1301                 };
1302
1303                 elm: elm@48078000 {
1304                         compatible = "ti,am3352-elm";
1305                         reg = <0x48078000 0xfc0>;      /* device IO registers */
1306                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1307                         ti,hwmods = "elm";
1308                         status = "disabled";
1309                 };
1310
1311                 gpmc: gpmc@50000000 {
1312                         compatible = "ti,am3352-gpmc";
1313                         ti,hwmods = "gpmc";
1314                         reg = <0x50000000 0x37c>;      /* device IO registers */
1315                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1316                         gpmc,num-cs = <8>;
1317                         gpmc,num-waitpins = <2>;
1318                         #address-cells = <2>;
1319                         #size-cells = <1>;
1320                         status = "disabled";
1321                 };
1322
1323                 atl: atl@4843c000 {
1324                         compatible = "ti,dra7-atl";
1325                         reg = <0x4843c000 0x3ff>;
1326                         ti,hwmods = "atl";
1327                         ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1328                                              <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1329                         clocks = <&atl_gfclk_mux>;
1330                         clock-names = "fck";
1331                         status = "disabled";
1332                 };
1333
1334                 crossbar_mpu: crossbar@4a020000 {
1335                         compatible = "ti,irq-crossbar";
1336                         reg = <0x4a002a48 0x130>;
1337                         ti,max-irqs = <160>;
1338                         ti,max-crossbar-sources = <MAX_SOURCES>;
1339                         ti,reg-size = <2>;
1340                         ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1341                         ti,irqs-skip = <10 133 139 140>;
1342                         ti,irqs-safe-map = <0>;
1343                 };
1344
1345                 mac: ethernet@4a100000 {
1346                         compatible = "ti,cpsw";
1347                         ti,hwmods = "gmac";
1348                         clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
1349                         clock-names = "fck", "cpts";
1350                         cpdma_channels = <8>;
1351                         ale_entries = <1024>;
1352                         bd_ram_size = <0x2000>;
1353                         no_bd_ram = <0>;
1354                         rx_descs = <64>;
1355                         mac_control = <0x20>;
1356                         slaves = <2>;
1357                         active_slave = <0>;
1358                         cpts_clock_mult = <0x80000000>;
1359                         cpts_clock_shift = <29>;
1360                         reg = <0x48484000 0x1000
1361                                0x48485200 0x2E00>;
1362                         #address-cells = <1>;
1363                         #size-cells = <1>;
1364                         /*
1365                          * rx_thresh_pend
1366                          * rx_pend
1367                          * tx_pend
1368                          * misc_pend
1369                          */
1370                         interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1371                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1372                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1373                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1374                         ranges;
1375                         status = "disabled";
1376
1377                         davinci_mdio: mdio@48485000 {
1378                                 compatible = "ti,davinci_mdio";
1379                                 #address-cells = <1>;
1380                                 #size-cells = <0>;
1381                                 ti,hwmods = "davinci_mdio";
1382                                 bus_freq = <1000000>;
1383                                 reg = <0x48485000 0x100>;
1384                         };
1385
1386                         cpsw_emac0: slave@48480200 {
1387                                 /* Filled in by U-Boot */
1388                                 mac-address = [ 00 00 00 00 00 00 ];
1389                         };
1390
1391                         cpsw_emac1: slave@48480300 {
1392                                 /* Filled in by U-Boot */
1393                                 mac-address = [ 00 00 00 00 00 00 ];
1394                         };
1395
1396                         phy_sel: cpsw-phy-sel@4a002554 {
1397                                 compatible = "ti,dra7xx-cpsw-phy-sel";
1398                                 reg= <0x4a002554 0x4>;
1399                                 reg-names = "gmii-sel";
1400                         };
1401                 };
1402
1403         };
1404 };
1405
1406 /include/ "dra7xx-clocks.dtsi"