arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Dor Laor <dor.laor@qumranet.com>
  12  *   Gregory Haskins <ghaskins@novell.com>
  13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  14  *
  15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  */
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/kvm.h>
  23 #include <linux/mm.h>
  24 #include <linux/highmem.h>
  25 #include <linux/smp.h>
  26 #include <linux/hrtimer.h>
  27 #include <linux/io.h>
  28 #include <linux/module.h>
  29 #include <linux/math64.h>
  30 #include <linux/slab.h>
  31 #include <asm/processor.h>
  32 #include <asm/msr.h>
  33 #include <asm/page.h>
  34 #include <asm/current.h>
  35 #include <asm/apicdef.h>
  36 #include <asm/delay.h>
  37 #include <linux/atomic.h>
  38 #include <linux/jump_label.h>
  39 #include "kvm_cache_regs.h"
  40 #include "irq.h"
  41 #include "trace.h"
  42 #include "x86.h"
  43 #include "cpuid.h"
  44
  45 #ifndef CONFIG_X86_64
  46 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  47 #else
  48 #define mod_64(x, y) ((x) % (y))
  49 #endif
  50
  51 #define PRId64 "d"
  52 #define PRIx64 "llx"
  53 #define PRIu64 "u"
  54 #define PRIo64 "o"
  55
  56 #define APIC_BUS_CYCLE_NS 1
  57
  58 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  59 #define apic_debug(fmt, arg...) do {} while (0)
  60
  61 #define APIC_LVT_NUM                    6
  62 /* 14 is the version for Xeon and Pentium 8.4.8*/
  63 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  64 #define LAPIC_MMIO_LENGTH               (1 << 12)
  65 /* followed define is not in apicdef.h */
  66 #define APIC_SHORT_MASK                 0xc0000
  67 #define APIC_DEST_NOSHORT               0x0
  68 #define APIC_DEST_MASK                  0x800
  69 #define MAX_APIC_VECTOR                 256
  70 #define APIC_VECTORS_PER_REG            32
  71
  72 #define APIC_BROADCAST                  0xFF
  73 #define X2APIC_BROADCAST                0xFFFFFFFFul
  74
  75 #define VEC_POS(v) ((v) & (32 - 1))
  76 #define REG_POS(v) (((v) >> 5) << 4)
  77
  78 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  79 {
  80         *((u32 *) (apic->regs + reg_off)) = val;
  81 }
  82
  83 static inline int apic_test_vector(int vec, void *bitmap)
  84 {
  85         return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  86 }
  87
  88 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
  89 {
  90         struct kvm_lapic *apic = vcpu->arch.apic;
  91
  92         return apic_test_vector(vector, apic->regs + APIC_ISR) ||
  93                 apic_test_vector(vector, apic->regs + APIC_IRR);
  94 }
  95
  96 static inline void apic_set_vector(int vec, void *bitmap)
  97 {
  98         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  99 }
 100
 101 static inline void apic_clear_vector(int vec, void *bitmap)
 102 {
 103         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 104 }
 105
 106 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
 107 {
 108         return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 109 }
 110
 111 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
 112 {
 113         return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 114 }
 115
 116 struct static_key_deferred apic_hw_disabled __read_mostly;
 117 struct static_key_deferred apic_sw_disabled __read_mostly;
 118
 119 static inline int apic_enabled(struct kvm_lapic *apic)
 120 {
 121         return kvm_apic_sw_enabled(apic) &&     kvm_apic_hw_enabled(apic);
 122 }
 123
 124 #define LVT_MASK        \
 125         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 126
 127 #define LINT_MASK       \
 128         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 129          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 130
 131 static inline int kvm_apic_id(struct kvm_lapic *apic)
 132 {
 133         return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 134 }
 135
 136 /* The logical map is definitely wrong if we have multiple
 137  * modes at the same time.  (Physical map is always right.)
 138  */
 139 static inline bool kvm_apic_logical_map_valid(struct kvm_apic_map *map)
 140 {
 141         return !(map->mode & (map->mode - 1));
 142 }
 143
 144 static inline void
 145 apic_logical_id(struct kvm_apic_map *map, u32 dest_id, u16 *cid, u16 *lid)
 146 {
 147         unsigned lid_bits;
 148
 149         BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_CLUSTER !=  4);
 150         BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_FLAT    !=  8);
 151         BUILD_BUG_ON(KVM_APIC_MODE_X2APIC        != 16);
 152         lid_bits = map->mode;
 153
 154         *cid = dest_id >> lid_bits;
 155         *lid = dest_id & ((1 << lid_bits) - 1);
 156 }
 157
 158 static void recalculate_apic_map(struct kvm *kvm)
 159 {
 160         struct kvm_apic_map *new, *old = NULL;
 161         struct kvm_vcpu *vcpu;
 162         int i;
 163
 164         new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
 165
 166         mutex_lock(&kvm->arch.apic_map_lock);
 167
 168         if (!new)
 169                 goto out;
 170
 171         kvm_for_each_vcpu(i, vcpu, kvm) {
 172                 struct kvm_lapic *apic = vcpu->arch.apic;
 173                 u16 cid, lid;
 174                 u32 ldr, aid;
 175
 176                 if (!kvm_apic_present(vcpu))
 177                         continue;
 178
 179                 aid = kvm_apic_id(apic);
 180                 ldr = kvm_apic_get_reg(apic, APIC_LDR);
 181
 182                 if (aid < ARRAY_SIZE(new->phys_map))
 183                         new->phys_map[aid] = apic;
 184
 185                 if (apic_x2apic_mode(apic)) {
 186                         new->mode |= KVM_APIC_MODE_X2APIC;
 187                 } else if (ldr) {
 188                         ldr = GET_APIC_LOGICAL_ID(ldr);
 189                         if (kvm_apic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
 190                                 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
 191                         else
 192                                 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
 193                 }
 194
 195                 if (!kvm_apic_logical_map_valid(new))
 196                         continue;
 197
 198                 apic_logical_id(new, ldr, &cid, &lid);
 199
 200                 if (lid && cid < ARRAY_SIZE(new->logical_map))
 201                         new->logical_map[cid][ffs(lid) - 1] = apic;
 202         }
 203 out:
 204         old = rcu_dereference_protected(kvm->arch.apic_map,
 205                         lockdep_is_held(&kvm->arch.apic_map_lock));
 206         rcu_assign_pointer(kvm->arch.apic_map, new);
 207         mutex_unlock(&kvm->arch.apic_map_lock);
 208
 209         if (old)
 210                 kfree_rcu(old, rcu);
 211
 212         kvm_make_scan_ioapic_request(kvm);
 213 }
 214
 215 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
 216 {
 217         bool enabled = val & APIC_SPIV_APIC_ENABLED;
 218
 219         apic_set_reg(apic, APIC_SPIV, val);
 220
 221         if (enabled != apic->sw_enabled) {
 222                 apic->sw_enabled = enabled;
 223                 if (enabled) {
 224                         static_key_slow_dec_deferred(&apic_sw_disabled);
 225                         recalculate_apic_map(apic->vcpu->kvm);
 226                 } else
 227                         static_key_slow_inc(&apic_sw_disabled.key);
 228         }
 229 }
 230
 231 static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
 232 {
 233         apic_set_reg(apic, APIC_ID, id << 24);
 234         recalculate_apic_map(apic->vcpu->kvm);
 235 }
 236
 237 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
 238 {
 239         apic_set_reg(apic, APIC_LDR, id);
 240         recalculate_apic_map(apic->vcpu->kvm);
 241 }
 242
 243 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u8 id)
 244 {
 245         u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
 246
 247         apic_set_reg(apic, APIC_ID, id << 24);
 248         apic_set_reg(apic, APIC_LDR, ldr);
 249         recalculate_apic_map(apic->vcpu->kvm);
 250 }
 251
 252 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 253 {
 254         return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 255 }
 256
 257 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 258 {
 259         return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 260 }
 261
 262 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
 263 {
 264         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
 265 }
 266
 267 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 268 {
 269         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
 270 }
 271
 272 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
 273 {
 274         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
 275 }
 276
 277 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 278 {
 279         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 280 }
 281
 282 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 283 {
 284         struct kvm_lapic *apic = vcpu->arch.apic;
 285         struct kvm_cpuid_entry2 *feat;
 286         u32 v = APIC_VERSION;
 287
 288         if (!kvm_vcpu_has_lapic(vcpu))
 289                 return;
 290
 291         /*
 292          * KVM emulates 82093AA datasheet (with in-kernel IOAPIC implementation)
 293          * which doesn't have EOI register; Some buggy OSes (e.g. Windows with
 294          * Hyper-V role) disable EOI broadcast in lapic not checking for IOAPIC
 295          * version first and level-triggered interrupts never get EOIed in
 296          * IOAPIC.
 297          */
 298         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
 299         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))) &&
 300             !ioapic_in_kernel(vcpu->kvm))
 301                 v |= APIC_LVR_DIRECTED_EOI;
 302         apic_set_reg(apic, APIC_LVR, v);
 303 }
 304
 305 static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 306         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
 307         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 308         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 309         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 310         LVT_MASK                /* LVTERR */
 311 };
 312
 313 static int find_highest_vector(void *bitmap)
 314 {
 315         int vec;
 316         u32 *reg;
 317
 318         for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
 319              vec >= 0; vec -= APIC_VECTORS_PER_REG) {
 320                 reg = bitmap + REG_POS(vec);
 321                 if (*reg)
 322                         return fls(*reg) - 1 + vec;
 323         }
 324
 325         return -1;
 326 }
 327
 328 static u8 count_vectors(void *bitmap)
 329 {
 330         int vec;
 331         u32 *reg;
 332         u8 count = 0;
 333
 334         for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
 335                 reg = bitmap + REG_POS(vec);
 336                 count += hweight32(*reg);
 337         }
 338
 339         return count;
 340 }
 341
 342 void __kvm_apic_update_irr(u32 *pir, void *regs)
 343 {
 344         u32 i, pir_val;
 345
 346         for (i = 0; i <= 7; i++) {
 347                 pir_val = xchg(&pir[i], 0);
 348                 if (pir_val)
 349                         *((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val;
 350         }
 351 }
 352 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
 353
 354 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
 355 {
 356         struct kvm_lapic *apic = vcpu->arch.apic;
 357
 358         __kvm_apic_update_irr(pir, apic->regs);
 359
 360         kvm_make_request(KVM_REQ_EVENT, vcpu);
 361 }
 362 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
 363
 364 static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
 365 {
 366         apic_set_vector(vec, apic->regs + APIC_IRR);
 367         /*
 368          * irr_pending must be true if any interrupt is pending; set it after
 369          * APIC_IRR to avoid race with apic_clear_irr
 370          */
 371         apic->irr_pending = true;
 372 }
 373
 374 static inline int apic_search_irr(struct kvm_lapic *apic)
 375 {
 376         return find_highest_vector(apic->regs + APIC_IRR);
 377 }
 378
 379 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 380 {
 381         int result;
 382
 383         /*
 384          * Note that irr_pending is just a hint. It will be always
 385          * true with virtual interrupt delivery enabled.
 386          */
 387         if (!apic->irr_pending)
 388                 return -1;
 389
 390         kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
 391         result = apic_search_irr(apic);
 392         ASSERT(result == -1 || result >= 16);
 393
 394         return result;
 395 }
 396
 397 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 398 {
 399         struct kvm_vcpu *vcpu;
 400
 401         vcpu = apic->vcpu;
 402
 403         if (unlikely(kvm_vcpu_apic_vid_enabled(vcpu))) {
 404                 /* try to update RVI */
 405                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 406                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 407         } else {
 408                 apic->irr_pending = false;
 409                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 410                 if (apic_search_irr(apic) != -1)
 411                         apic->irr_pending = true;
 412         }
 413 }
 414
 415 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
 416 {
 417         struct kvm_vcpu *vcpu;
 418
 419         if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
 420                 return;
 421
 422         vcpu = apic->vcpu;
 423
 424         /*
 425          * With APIC virtualization enabled, all caching is disabled
 426          * because the processor can modify ISR under the hood.  Instead
 427          * just set SVI.
 428          */
 429         if (unlikely(kvm_x86_ops->hwapic_isr_update))
 430                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
 431         else {
 432                 ++apic->isr_count;
 433                 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
 434                 /*
 435                  * ISR (in service register) bit is set when injecting an interrupt.
 436                  * The highest vector is injected. Thus the latest bit set matches
 437                  * the highest bit in ISR.
 438                  */
 439                 apic->highest_isr_cache = vec;
 440         }
 441 }
 442
 443 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 444 {
 445         int result;
 446
 447         /*
 448          * Note that isr_count is always 1, and highest_isr_cache
 449          * is always -1, with APIC virtualization enabled.
 450          */
 451         if (!apic->isr_count)
 452                 return -1;
 453         if (likely(apic->highest_isr_cache != -1))
 454                 return apic->highest_isr_cache;
 455
 456         result = find_highest_vector(apic->regs + APIC_ISR);
 457         ASSERT(result == -1 || result >= 16);
 458
 459         return result;
 460 }
 461
 462 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
 463 {
 464         struct kvm_vcpu *vcpu;
 465         if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
 466                 return;
 467
 468         vcpu = apic->vcpu;
 469
 470         /*
 471          * We do get here for APIC virtualization enabled if the guest
 472          * uses the Hyper-V APIC enlightenment.  In this case we may need
 473          * to trigger a new interrupt delivery by writing the SVI field;
 474          * on the other hand isr_count and highest_isr_cache are unused
 475          * and must be left alone.
 476          */
 477         if (unlikely(kvm_x86_ops->hwapic_isr_update))
 478                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
 479                                                apic_find_highest_isr(apic));
 480         else {
 481                 --apic->isr_count;
 482                 BUG_ON(apic->isr_count < 0);
 483                 apic->highest_isr_cache = -1;
 484         }
 485 }
 486
 487 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 488 {
 489         int highest_irr;
 490
 491         /* This may race with setting of irr in __apic_accept_irq() and
 492          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 493          * will cause vmexit immediately and the value will be recalculated
 494          * on the next vmentry.
 495          */
 496         if (!kvm_vcpu_has_lapic(vcpu))
 497                 return 0;
 498         highest_irr = apic_find_highest_irr(vcpu->arch.apic);
 499
 500         return highest_irr;
 501 }
 502
 503 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 504                              int vector, int level, int trig_mode,
 505                              unsigned long *dest_map);
 506
 507 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
 508                 unsigned long *dest_map)
 509 {
 510         struct kvm_lapic *apic = vcpu->arch.apic;
 511
 512         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 513                         irq->level, irq->trig_mode, dest_map);
 514 }
 515
 516 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
 517 {
 518
 519         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
 520                                       sizeof(val));
 521 }
 522
 523 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
 524 {
 525
 526         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
 527                                       sizeof(*val));
 528 }
 529
 530 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
 531 {
 532         return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
 533 }
 534
 535 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
 536 {
 537         u8 val;
 538         if (pv_eoi_get_user(vcpu, &val) < 0)
 539                 apic_debug("Can't read EOI MSR value: 0x%llx\n",
 540                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 541         return val & 0x1;
 542 }
 543
 544 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
 545 {
 546         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
 547                 apic_debug("Can't set EOI MSR value: 0x%llx\n",
 548                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 549                 return;
 550         }
 551         __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 552 }
 553
 554 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
 555 {
 556         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
 557                 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
 558                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 559                 return;
 560         }
 561         __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 562 }
 563
 564 static void apic_update_ppr(struct kvm_lapic *apic)
 565 {
 566         u32 tpr, isrv, ppr, old_ppr;
 567         int isr;
 568
 569         old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
 570         tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
 571         isr = apic_find_highest_isr(apic);
 572         isrv = (isr != -1) ? isr : 0;
 573
 574         if ((tpr & 0xf0) >= (isrv & 0xf0))
 575                 ppr = tpr & 0xff;
 576         else
 577                 ppr = isrv & 0xf0;
 578
 579         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 580                    apic, ppr, isr, isrv);
 581
 582         if (old_ppr != ppr) {
 583                 apic_set_reg(apic, APIC_PROCPRI, ppr);
 584                 if (ppr < old_ppr)
 585                         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 586         }
 587 }
 588
 589 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 590 {
 591         apic_set_reg(apic, APIC_TASKPRI, tpr);
 592         apic_update_ppr(apic);
 593 }
 594
 595 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
 596 {
 597         if (apic_x2apic_mode(apic))
 598                 return mda == X2APIC_BROADCAST;
 599
 600         return GET_APIC_DEST_FIELD(mda) == APIC_BROADCAST;
 601 }
 602
 603 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
 604 {
 605         if (kvm_apic_broadcast(apic, mda))
 606                 return true;
 607
 608         if (apic_x2apic_mode(apic))
 609                 return mda == kvm_apic_id(apic);
 610
 611         return mda == SET_APIC_DEST_FIELD(kvm_apic_id(apic));
 612 }
 613
 614 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
 615 {
 616         u32 logical_id;
 617
 618         if (kvm_apic_broadcast(apic, mda))
 619                 return true;
 620
 621         logical_id = kvm_apic_get_reg(apic, APIC_LDR);
 622
 623         if (apic_x2apic_mode(apic))
 624                 return ((logical_id >> 16) == (mda >> 16))
 625                        && (logical_id & mda & 0xffff) != 0;
 626
 627         logical_id = GET_APIC_LOGICAL_ID(logical_id);
 628         mda = GET_APIC_DEST_FIELD(mda);
 629
 630         switch (kvm_apic_get_reg(apic, APIC_DFR)) {
 631         case APIC_DFR_FLAT:
 632                 return (logical_id & mda) != 0;
 633         case APIC_DFR_CLUSTER:
 634                 return ((logical_id >> 4) == (mda >> 4))
 635                        && (logical_id & mda & 0xf) != 0;
 636         default:
 637                 apic_debug("Bad DFR vcpu %d: %08x\n",
 638                            apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
 639                 return false;
 640         }
 641 }
 642
 643 /* KVM APIC implementation has two quirks
 644  *  - dest always begins at 0 while xAPIC MDA has offset 24,
 645  *  - IOxAPIC messages have to be delivered (directly) to x2APIC.
 646  */
 647 static u32 kvm_apic_mda(unsigned int dest_id, struct kvm_lapic *source,
 648                                               struct kvm_lapic *target)
 649 {
 650         bool ipi = source != NULL;
 651         bool x2apic_mda = apic_x2apic_mode(ipi ? source : target);
 652
 653         if (!ipi && dest_id == APIC_BROADCAST && x2apic_mda)
 654                 return X2APIC_BROADCAST;
 655
 656         return x2apic_mda ? dest_id : SET_APIC_DEST_FIELD(dest_id);
 657 }
 658
 659 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 660                            int short_hand, unsigned int dest, int dest_mode)
 661 {
 662         struct kvm_lapic *target = vcpu->arch.apic;
 663         u32 mda = kvm_apic_mda(dest, source, target);
 664
 665         apic_debug("target %p, source %p, dest 0x%x, "
 666                    "dest_mode 0x%x, short_hand 0x%x\n",
 667                    target, source, dest, dest_mode, short_hand);
 668
 669         ASSERT(target);
 670         switch (short_hand) {
 671         case APIC_DEST_NOSHORT:
 672                 if (dest_mode == APIC_DEST_PHYSICAL)
 673                         return kvm_apic_match_physical_addr(target, mda);
 674                 else
 675                         return kvm_apic_match_logical_addr(target, mda);
 676         case APIC_DEST_SELF:
 677                 return target == source;
 678         case APIC_DEST_ALLINC:
 679                 return true;
 680         case APIC_DEST_ALLBUT:
 681                 return target != source;
 682         default:
 683                 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
 684                            short_hand);
 685                 return false;
 686         }
 687 }
 688
 689 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
 690                 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
 691 {
 692         struct kvm_apic_map *map;
 693         unsigned long bitmap = 1;
 694         struct kvm_lapic **dst;
 695         int i;
 696         bool ret, x2apic_ipi;
 697
 698         *r = -1;
 699
 700         if (irq->shorthand == APIC_DEST_SELF) {
 701                 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
 702                 return true;
 703         }
 704
 705         if (irq->shorthand)
 706                 return false;
 707
 708         x2apic_ipi = src && apic_x2apic_mode(src);
 709         if (irq->dest_id == (x2apic_ipi ? X2APIC_BROADCAST : APIC_BROADCAST))
 710                 return false;
 711
 712         ret = true;
 713         rcu_read_lock();
 714         map = rcu_dereference(kvm->arch.apic_map);
 715
 716         if (!map) {
 717                 ret = false;
 718                 goto out;
 719         }
 720
 721         if (irq->dest_mode == APIC_DEST_PHYSICAL) {
 722                 if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
 723                         goto out;
 724
 725                 dst = &map->phys_map[irq->dest_id];
 726         } else {
 727                 u16 cid;
 728
 729                 if (!kvm_apic_logical_map_valid(map)) {
 730                         ret = false;
 731                         goto out;
 732                 }
 733
 734                 apic_logical_id(map, irq->dest_id, &cid, (u16 *)&bitmap);
 735
 736                 if (cid >= ARRAY_SIZE(map->logical_map))
 737                         goto out;
 738
 739                 dst = map->logical_map[cid];
 740
 741                 if (kvm_lowest_prio_delivery(irq)) {
 742                         int l = -1;
 743                         for_each_set_bit(i, &bitmap, 16) {
 744                                 if (!dst[i])
 745                                         continue;
 746                                 if (l < 0)
 747                                         l = i;
 748                                 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
 749                                         l = i;
 750                         }
 751
 752                         bitmap = (l >= 0) ? 1 << l : 0;
 753                 }
 754         }
 755
 756         for_each_set_bit(i, &bitmap, 16) {
 757                 if (!dst[i])
 758                         continue;
 759                 if (*r < 0)
 760                         *r = 0;
 761                 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
 762         }
 763 out:
 764         rcu_read_unlock();
 765         return ret;
 766 }
 767
 768 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
 769                         struct kvm_vcpu **dest_vcpu)
 770 {
 771         struct kvm_apic_map *map;
 772         bool ret = false;
 773         struct kvm_lapic *dst = NULL;
 774
 775         if (irq->shorthand)
 776                 return false;
 777
 778         rcu_read_lock();
 779         map = rcu_dereference(kvm->arch.apic_map);
 780
 781         if (!map)
 782                 goto out;
 783
 784         if (irq->dest_mode == APIC_DEST_PHYSICAL) {
 785                 if (irq->dest_id == 0xFF)
 786                         goto out;
 787
 788                 if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
 789                         goto out;
 790
 791                 dst = map->phys_map[irq->dest_id];
 792                 if (dst && kvm_apic_present(dst->vcpu))
 793                         *dest_vcpu = dst->vcpu;
 794                 else
 795                         goto out;
 796         } else {
 797                 u16 cid;
 798                 unsigned long bitmap = 1;
 799                 int i, r = 0;
 800
 801                 if (!kvm_apic_logical_map_valid(map))
 802                         goto out;
 803
 804                 apic_logical_id(map, irq->dest_id, &cid, (u16 *)&bitmap);
 805
 806                 if (cid >= ARRAY_SIZE(map->logical_map))
 807                         goto out;
 808
 809                 for_each_set_bit(i, &bitmap, 16) {
 810                         dst = map->logical_map[cid][i];
 811                         if (++r == 2)
 812                                 goto out;
 813                 }
 814
 815                 if (dst && kvm_apic_present(dst->vcpu))
 816                         *dest_vcpu = dst->vcpu;
 817                 else
 818                         goto out;
 819         }
 820
 821         ret = true;
 822 out:
 823         rcu_read_unlock();
 824         return ret;
 825 }
 826
 827 /*
 828  * Add a pending IRQ into lapic.
 829  * Return 1 if successfully added and 0 if discarded.
 830  */
 831 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 832                              int vector, int level, int trig_mode,
 833                              unsigned long *dest_map)
 834 {
 835         int result = 0;
 836         struct kvm_vcpu *vcpu = apic->vcpu;
 837
 838         trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
 839                                   trig_mode, vector);
 840         switch (delivery_mode) {
 841         case APIC_DM_LOWEST:
 842                 vcpu->arch.apic_arb_prio++;
 843         case APIC_DM_FIXED:
 844                 if (unlikely(trig_mode && !level))
 845                         break;
 846
 847                 /* FIXME add logic for vcpu on reset */
 848                 if (unlikely(!apic_enabled(apic)))
 849                         break;
 850
 851                 result = 1;
 852
 853                 if (dest_map)
 854                         __set_bit(vcpu->vcpu_id, dest_map);
 855
 856                 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
 857                         if (trig_mode)
 858                                 apic_set_vector(vector, apic->regs + APIC_TMR);
 859                         else
 860                                 apic_clear_vector(vector, apic->regs + APIC_TMR);
 861                 }
 862
 863                 if (kvm_x86_ops->deliver_posted_interrupt)
 864                         kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
 865                 else {
 866                         apic_set_irr(vector, apic);
 867
 868                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 869                         kvm_vcpu_kick(vcpu);
 870                 }
 871                 break;
 872
 873         case APIC_DM_REMRD:
 874                 result = 1;
 875                 vcpu->arch.pv.pv_unhalted = 1;
 876                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 877                 kvm_vcpu_kick(vcpu);
 878                 break;
 879
 880         case APIC_DM_SMI:
 881                 result = 1;
 882                 kvm_make_request(KVM_REQ_SMI, vcpu);
 883                 kvm_vcpu_kick(vcpu);
 884                 break;
 885
 886         case APIC_DM_NMI:
 887                 result = 1;
 888                 kvm_inject_nmi(vcpu);
 889                 kvm_vcpu_kick(vcpu);
 890                 break;
 891
 892         case APIC_DM_INIT:
 893                 if (!trig_mode || level) {
 894                         result = 1;
 895                         /* assumes that there are only KVM_APIC_INIT/SIPI */
 896                         apic->pending_events = (1UL << KVM_APIC_INIT);
 897                         /* make sure pending_events is visible before sending
 898                          * the request */
 899                         smp_wmb();
 900                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 901                         kvm_vcpu_kick(vcpu);
 902                 } else {
 903                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
 904                                    vcpu->vcpu_id);
 905                 }
 906                 break;
 907
 908         case APIC_DM_STARTUP:
 909                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
 910                            vcpu->vcpu_id, vector);
 911                 result = 1;
 912                 apic->sipi_vector = vector;
 913                 /* make sure sipi_vector is visible for the receiver */
 914                 smp_wmb();
 915                 set_bit(KVM_APIC_SIPI, &apic->pending_events);
 916                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 917                 kvm_vcpu_kick(vcpu);
 918                 break;
 919
 920         case APIC_DM_EXTINT:
 921                 /*
 922                  * Should only be called by kvm_apic_local_deliver() with LVT0,
 923                  * before NMI watchdog was enabled. Already handled by
 924                  * kvm_apic_accept_pic_intr().
 925                  */
 926                 break;
 927
 928         default:
 929                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 930                        delivery_mode);
 931                 break;
 932         }
 933         return result;
 934 }
 935
 936 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
 937 {
 938         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
 939 }
 940
 941 static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
 942 {
 943         return test_bit(vector, (ulong *)apic->vcpu->arch.eoi_exit_bitmap);
 944 }
 945
 946 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
 947 {
 948         int trigger_mode;
 949
 950         /* Eoi the ioapic only if the ioapic doesn't own the vector. */
 951         if (!kvm_ioapic_handles_vector(apic, vector))
 952                 return;
 953
 954         /* Request a KVM exit to inform the userspace IOAPIC. */
 955         if (irqchip_split(apic->vcpu->kvm)) {
 956                 apic->vcpu->arch.pending_ioapic_eoi = vector;
 957                 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
 958                 return;
 959         }
 960
 961         if (apic_test_vector(vector, apic->regs + APIC_TMR))
 962                 trigger_mode = IOAPIC_LEVEL_TRIG;
 963         else
 964                 trigger_mode = IOAPIC_EDGE_TRIG;
 965
 966         kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
 967 }
 968
 969 static int apic_set_eoi(struct kvm_lapic *apic)
 970 {
 971         int vector = apic_find_highest_isr(apic);
 972
 973         trace_kvm_eoi(apic, vector);
 974
 975         /*
 976          * Not every write EOI will has corresponding ISR,
 977          * one example is when Kernel check timer on setup_IO_APIC
 978          */
 979         if (vector == -1)
 980                 return vector;
 981
 982         apic_clear_isr(vector, apic);
 983         apic_update_ppr(apic);
 984
 985         kvm_ioapic_send_eoi(apic, vector);
 986         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 987         return vector;
 988 }
 989
 990 /*
 991  * this interface assumes a trap-like exit, which has already finished
 992  * desired side effect including vISR and vPPR update.
 993  */
 994 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
 995 {
 996         struct kvm_lapic *apic = vcpu->arch.apic;
 997
 998         trace_kvm_eoi(apic, vector);
 999
1000         kvm_ioapic_send_eoi(apic, vector);
1001         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1002 }
1003 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
1004
1005 static void apic_send_ipi(struct kvm_lapic *apic)
1006 {
1007         u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
1008         u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
1009         struct kvm_lapic_irq irq;
1010
1011         irq.vector = icr_low & APIC_VECTOR_MASK;
1012         irq.delivery_mode = icr_low & APIC_MODE_MASK;
1013         irq.dest_mode = icr_low & APIC_DEST_MASK;
1014         irq.level = (icr_low & APIC_INT_ASSERT) != 0;
1015         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
1016         irq.shorthand = icr_low & APIC_SHORT_MASK;
1017         irq.msi_redir_hint = false;
1018         if (apic_x2apic_mode(apic))
1019                 irq.dest_id = icr_high;
1020         else
1021                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
1022
1023         trace_kvm_apic_ipi(icr_low, irq.dest_id);
1024
1025         apic_debug("icr_high 0x%x, icr_low 0x%x, "
1026                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
1027                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
1028                    "msi_redir_hint 0x%x\n",
1029                    icr_high, icr_low, irq.shorthand, irq.dest_id,
1030                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
1031                    irq.vector, irq.msi_redir_hint);
1032
1033         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
1034 }
1035
1036 static u32 apic_get_tmcct(struct kvm_lapic *apic)
1037 {
1038         ktime_t remaining;
1039         s64 ns;
1040         u32 tmcct;
1041
1042         ASSERT(apic != NULL);
1043
1044         /* if initial count is 0, current count should also be 0 */
1045         if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
1046                 apic->lapic_timer.period == 0)
1047                 return 0;
1048
1049         remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
1050         if (ktime_to_ns(remaining) < 0)
1051                 remaining = ktime_set(0, 0);
1052
1053         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1054         tmcct = div64_u64(ns,
1055                          (APIC_BUS_CYCLE_NS * apic->divide_count));
1056
1057         return tmcct;
1058 }
1059
1060 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1061 {
1062         struct kvm_vcpu *vcpu = apic->vcpu;
1063         struct kvm_run *run = vcpu->run;
1064
1065         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
1066         run->tpr_access.rip = kvm_rip_read(vcpu);
1067         run->tpr_access.is_write = write;
1068 }
1069
1070 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1071 {
1072         if (apic->vcpu->arch.tpr_access_reporting)
1073                 __report_tpr_access(apic, write);
1074 }
1075
1076 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1077 {
1078         u32 val = 0;
1079
1080         if (offset >= LAPIC_MMIO_LENGTH)
1081                 return 0;
1082
1083         switch (offset) {
1084         case APIC_ID:
1085                 if (apic_x2apic_mode(apic))
1086                         val = kvm_apic_id(apic);
1087                 else
1088                         val = kvm_apic_id(apic) << 24;
1089                 break;
1090         case APIC_ARBPRI:
1091                 apic_debug("Access APIC ARBPRI register which is for P6\n");
1092                 break;
1093
1094         case APIC_TMCCT:        /* Timer CCR */
1095                 if (apic_lvtt_tscdeadline(apic))
1096                         return 0;
1097
1098                 val = apic_get_tmcct(apic);
1099                 break;
1100         case APIC_PROCPRI:
1101                 apic_update_ppr(apic);
1102                 val = kvm_apic_get_reg(apic, offset);
1103                 break;
1104         case APIC_TASKPRI:
1105                 report_tpr_access(apic, false);
1106                 /* fall thru */
1107         default:
1108                 val = kvm_apic_get_reg(apic, offset);
1109                 break;
1110         }
1111
1112         return val;
1113 }
1114
1115 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1116 {
1117         return container_of(dev, struct kvm_lapic, dev);
1118 }
1119
1120 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1121                 void *data)
1122 {
1123         unsigned char alignment = offset & 0xf;
1124         u32 result;
1125         /* this bitmask has a bit cleared for each reserved register */
1126         static const u64 rmask = 0x43ff01ffffffe70cULL;
1127
1128         if ((alignment + len) > 4) {
1129                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1130                            offset, len);
1131                 return 1;
1132         }
1133
1134         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1135                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1136                            offset);
1137                 return 1;
1138         }
1139
1140         result = __apic_read(apic, offset & ~0xf);
1141
1142         trace_kvm_apic_read(offset, result);
1143
1144         switch (len) {
1145         case 1:
1146         case 2:
1147         case 4:
1148                 memcpy(data, (char *)&result + alignment, len);
1149                 break;
1150         default:
1151                 printk(KERN_ERR "Local APIC read with len = %x, "
1152                        "should be 1,2, or 4 instead\n", len);
1153                 break;
1154         }
1155         return 0;
1156 }
1157
1158 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1159 {
1160         return kvm_apic_hw_enabled(apic) &&
1161             addr >= apic->base_address &&
1162             addr < apic->base_address + LAPIC_MMIO_LENGTH;
1163 }
1164
1165 static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1166                            gpa_t address, int len, void *data)
1167 {
1168         struct kvm_lapic *apic = to_lapic(this);
1169         u32 offset = address - apic->base_address;
1170
1171         if (!apic_mmio_in_range(apic, address))
1172                 return -EOPNOTSUPP;
1173
1174         apic_reg_read(apic, offset, len, data);
1175
1176         return 0;
1177 }
1178
1179 static void update_divide_count(struct kvm_lapic *apic)
1180 {
1181         u32 tmp1, tmp2, tdcr;
1182
1183         tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
1184         tmp1 = tdcr & 0xf;
1185         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1186         apic->divide_count = 0x1 << (tmp2 & 0x7);
1187
1188         apic_debug("timer divide count is 0x%x\n",
1189                                    apic->divide_count);
1190 }
1191
1192 static void apic_update_lvtt(struct kvm_lapic *apic)
1193 {
1194         u32 timer_mode = kvm_apic_get_reg(apic, APIC_LVTT) &
1195                         apic->lapic_timer.timer_mode_mask;
1196
1197         if (apic->lapic_timer.timer_mode != timer_mode) {
1198                 apic->lapic_timer.timer_mode = timer_mode;
1199                 hrtimer_cancel(&apic->lapic_timer.timer);
1200         }
1201 }
1202
1203 static void apic_timer_expired(struct kvm_lapic *apic)
1204 {
1205         struct kvm_vcpu *vcpu = apic->vcpu;
1206         wait_queue_head_t *q = &vcpu->wq;
1207         struct kvm_timer *ktimer = &apic->lapic_timer;
1208
1209         if (atomic_read(&apic->lapic_timer.pending))
1210                 return;
1211
1212         atomic_inc(&apic->lapic_timer.pending);
1213         kvm_set_pending_timer(vcpu);
1214
1215         if (waitqueue_active(q))
1216                 wake_up_interruptible(q);
1217
1218         if (apic_lvtt_tscdeadline(apic))
1219                 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1220 }
1221
1222 /*
1223  * On APICv, this test will cause a busy wait
1224  * during a higher-priority task.
1225  */
1226
1227 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1228 {
1229         struct kvm_lapic *apic = vcpu->arch.apic;
1230         u32 reg = kvm_apic_get_reg(apic, APIC_LVTT);
1231
1232         if (kvm_apic_hw_enabled(apic)) {
1233                 int vec = reg & APIC_VECTOR_MASK;
1234                 void *bitmap = apic->regs + APIC_ISR;
1235
1236                 if (kvm_x86_ops->deliver_posted_interrupt)
1237                         bitmap = apic->regs + APIC_IRR;
1238
1239                 if (apic_test_vector(vec, bitmap))
1240                         return true;
1241         }
1242         return false;
1243 }
1244
1245 void wait_lapic_expire(struct kvm_vcpu *vcpu)
1246 {
1247         struct kvm_lapic *apic = vcpu->arch.apic;
1248         u64 guest_tsc, tsc_deadline;
1249
1250         if (!kvm_vcpu_has_lapic(vcpu))
1251                 return;
1252
1253         if (apic->lapic_timer.expired_tscdeadline == 0)
1254                 return;
1255
1256         if (!lapic_timer_int_injected(vcpu))
1257                 return;
1258
1259         tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1260         apic->lapic_timer.expired_tscdeadline = 0;
1261         guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1262         trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
1263
1264         /* __delay is delay_tsc whenever the hardware has TSC, thus always.  */
1265         if (guest_tsc < tsc_deadline)
1266                 __delay(tsc_deadline - guest_tsc);
1267 }
1268
1269 static void start_apic_timer(struct kvm_lapic *apic)
1270 {
1271         ktime_t now;
1272
1273         atomic_set(&apic->lapic_timer.pending, 0);
1274
1275         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1276                 /* lapic timer in oneshot or periodic mode */
1277                 now = apic->lapic_timer.timer.base->get_time();
1278                 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
1279                             * APIC_BUS_CYCLE_NS * apic->divide_count;
1280
1281                 if (!apic->lapic_timer.period)
1282                         return;
1283                 /*
1284                  * Do not allow the guest to program periodic timers with small
1285                  * interval, since the hrtimers are not throttled by the host
1286                  * scheduler.
1287                  */
1288                 if (apic_lvtt_period(apic)) {
1289                         s64 min_period = min_timer_period_us * 1000LL;
1290
1291                         if (apic->lapic_timer.period < min_period) {
1292                                 pr_info_ratelimited(
1293                                     "kvm: vcpu %i: requested %lld ns "
1294                                     "lapic timer period limited to %lld ns\n",
1295                                     apic->vcpu->vcpu_id,
1296                                     apic->lapic_timer.period, min_period);
1297                                 apic->lapic_timer.period = min_period;
1298                         }
1299                 }
1300
1301                 hrtimer_start(&apic->lapic_timer.timer,
1302                               ktime_add_ns(now, apic->lapic_timer.period),
1303                               HRTIMER_MODE_ABS);
1304
1305                 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1306                            PRIx64 ", "
1307                            "timer initial count 0x%x, period %lldns, "
1308                            "expire @ 0x%016" PRIx64 ".\n", __func__,
1309                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1310                            kvm_apic_get_reg(apic, APIC_TMICT),
1311                            apic->lapic_timer.period,
1312                            ktime_to_ns(ktime_add_ns(now,
1313                                         apic->lapic_timer.period)));
1314         } else if (apic_lvtt_tscdeadline(apic)) {
1315                 /* lapic timer in tsc deadline mode */
1316                 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1317                 u64 ns = 0;
1318                 ktime_t expire;
1319                 struct kvm_vcpu *vcpu = apic->vcpu;
1320                 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1321                 unsigned long flags;
1322
1323                 if (unlikely(!tscdeadline || !this_tsc_khz))
1324                         return;
1325
1326                 local_irq_save(flags);
1327
1328                 now = apic->lapic_timer.timer.base->get_time();
1329                 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1330                 if (likely(tscdeadline > guest_tsc)) {
1331                         ns = (tscdeadline - guest_tsc) * 1000000ULL;
1332                         do_div(ns, this_tsc_khz);
1333                         expire = ktime_add_ns(now, ns);
1334                         expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1335                         hrtimer_start(&apic->lapic_timer.timer,
1336                                       expire, HRTIMER_MODE_ABS);
1337                 } else
1338                         apic_timer_expired(apic);
1339
1340                 local_irq_restore(flags);
1341         }
1342 }
1343
1344 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1345 {
1346         bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
1347
1348         if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1349                 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1350                 if (lvt0_in_nmi_mode) {
1351                         apic_debug("Receive NMI setting on APIC_LVT0 "
1352                                    "for cpu %d\n", apic->vcpu->vcpu_id);
1353                         atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1354                 } else
1355                         atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1356         }
1357 }
1358
1359 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1360 {
1361         int ret = 0;
1362
1363         trace_kvm_apic_write(reg, val);
1364
1365         switch (reg) {
1366         case APIC_ID:           /* Local APIC ID */
1367                 if (!apic_x2apic_mode(apic))
1368                         kvm_apic_set_id(apic, val >> 24);
1369                 else
1370                         ret = 1;
1371                 break;
1372
1373         case APIC_TASKPRI:
1374                 report_tpr_access(apic, true);
1375                 apic_set_tpr(apic, val & 0xff);
1376                 break;
1377
1378         case APIC_EOI:
1379                 apic_set_eoi(apic);
1380                 break;
1381
1382         case APIC_LDR:
1383                 if (!apic_x2apic_mode(apic))
1384                         kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1385                 else
1386                         ret = 1;
1387                 break;
1388
1389         case APIC_DFR:
1390                 if (!apic_x2apic_mode(apic)) {
1391                         apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1392                         recalculate_apic_map(apic->vcpu->kvm);
1393                 } else
1394                         ret = 1;
1395                 break;
1396
1397         case APIC_SPIV: {
1398                 u32 mask = 0x3ff;
1399                 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1400                         mask |= APIC_SPIV_DIRECTED_EOI;
1401                 apic_set_spiv(apic, val & mask);
1402                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1403                         int i;
1404                         u32 lvt_val;
1405
1406                         for (i = 0; i < APIC_LVT_NUM; i++) {
1407                                 lvt_val = kvm_apic_get_reg(apic,
1408                                                        APIC_LVTT + 0x10 * i);
1409                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1410                                              lvt_val | APIC_LVT_MASKED);
1411                         }
1412                         apic_update_lvtt(apic);
1413                         atomic_set(&apic->lapic_timer.pending, 0);
1414
1415                 }
1416                 break;
1417         }
1418         case APIC_ICR:
1419                 /* No delay here, so we always clear the pending bit */
1420                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1421                 apic_send_ipi(apic);
1422                 break;
1423
1424         case APIC_ICR2:
1425                 if (!apic_x2apic_mode(apic))
1426                         val &= 0xff000000;
1427                 apic_set_reg(apic, APIC_ICR2, val);
1428                 break;
1429
1430         case APIC_LVT0:
1431                 apic_manage_nmi_watchdog(apic, val);
1432         case APIC_LVTTHMR:
1433         case APIC_LVTPC:
1434         case APIC_LVT1:
1435         case APIC_LVTERR:
1436                 /* TODO: Check vector */
1437                 if (!kvm_apic_sw_enabled(apic))
1438                         val |= APIC_LVT_MASKED;
1439
1440                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1441                 apic_set_reg(apic, reg, val);
1442
1443                 break;
1444
1445         case APIC_LVTT:
1446                 if (!kvm_apic_sw_enabled(apic))
1447                         val |= APIC_LVT_MASKED;
1448                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1449                 apic_set_reg(apic, APIC_LVTT, val);
1450                 apic_update_lvtt(apic);
1451                 break;
1452
1453         case APIC_TMICT:
1454                 if (apic_lvtt_tscdeadline(apic))
1455                         break;
1456
1457                 hrtimer_cancel(&apic->lapic_timer.timer);
1458                 apic_set_reg(apic, APIC_TMICT, val);
1459                 start_apic_timer(apic);
1460                 break;
1461
1462         case APIC_TDCR:
1463                 if (val & 4)
1464                         apic_debug("KVM_WRITE:TDCR %x\n", val);
1465                 apic_set_reg(apic, APIC_TDCR, val);
1466                 update_divide_count(apic);
1467                 break;
1468
1469         case APIC_ESR:
1470                 if (apic_x2apic_mode(apic) && val != 0) {
1471                         apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1472                         ret = 1;
1473                 }
1474                 break;
1475
1476         case APIC_SELF_IPI:
1477                 if (apic_x2apic_mode(apic)) {
1478                         apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1479                 } else
1480                         ret = 1;
1481                 break;
1482         default:
1483                 ret = 1;
1484                 break;
1485         }
1486         if (ret)
1487                 apic_debug("Local APIC Write to read-only register %x\n", reg);
1488         return ret;
1489 }
1490
1491 static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1492                             gpa_t address, int len, const void *data)
1493 {
1494         struct kvm_lapic *apic = to_lapic(this);
1495         unsigned int offset = address - apic->base_address;
1496         u32 val;
1497
1498         if (!apic_mmio_in_range(apic, address))
1499                 return -EOPNOTSUPP;
1500
1501         /*
1502          * APIC register must be aligned on 128-bits boundary.
1503          * 32/64/128 bits registers must be accessed thru 32 bits.
1504          * Refer SDM 8.4.1
1505          */
1506         if (len != 4 || (offset & 0xf)) {
1507                 /* Don't shout loud, $infamous_os would cause only noise. */
1508                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1509                 return 0;
1510         }
1511
1512         val = *(u32*)data;
1513
1514         /* too common printing */
1515         if (offset != APIC_EOI)
1516                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1517                            "0x%x\n", __func__, offset, len, val);
1518
1519         apic_reg_write(apic, offset & 0xff0, val);
1520
1521         return 0;
1522 }
1523
1524 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1525 {
1526         if (kvm_vcpu_has_lapic(vcpu))
1527                 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1528 }
1529 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1530
1531 /* emulate APIC access in a trap manner */
1532 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1533 {
1534         u32 val = 0;
1535
1536         /* hw has done the conditional check and inst decode */
1537         offset &= 0xff0;
1538
1539         apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1540
1541         /* TODO: optimize to just emulate side effect w/o one more write */
1542         apic_reg_write(vcpu->arch.apic, offset, val);
1543 }
1544 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1545
1546 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1547 {
1548         struct kvm_lapic *apic = vcpu->arch.apic;
1549
1550         if (!vcpu->arch.apic)
1551                 return;
1552
1553         hrtimer_cancel(&apic->lapic_timer.timer);
1554
1555         if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1556                 static_key_slow_dec_deferred(&apic_hw_disabled);
1557
1558         if (!apic->sw_enabled)
1559                 static_key_slow_dec_deferred(&apic_sw_disabled);
1560
1561         if (apic->regs)
1562                 free_page((unsigned long)apic->regs);
1563
1564         kfree(apic);
1565 }
1566
1567 /*
1568  *----------------------------------------------------------------------
1569  * LAPIC interface
1570  *----------------------------------------------------------------------
1571  */
1572
1573 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1574 {
1575         struct kvm_lapic *apic = vcpu->arch.apic;
1576
1577         if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1578                         apic_lvtt_period(apic))
1579                 return 0;
1580
1581         return apic->lapic_timer.tscdeadline;
1582 }
1583
1584 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1585 {
1586         struct kvm_lapic *apic = vcpu->arch.apic;
1587
1588         if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1589                         apic_lvtt_period(apic))
1590                 return;
1591
1592         hrtimer_cancel(&apic->lapic_timer.timer);
1593         apic->lapic_timer.tscdeadline = data;
1594         start_apic_timer(apic);
1595 }
1596
1597 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1598 {
1599         struct kvm_lapic *apic = vcpu->arch.apic;
1600
1601         if (!kvm_vcpu_has_lapic(vcpu))
1602                 return;
1603
1604         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1605                      | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
1606 }
1607
1608 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1609 {
1610         u64 tpr;
1611
1612         if (!kvm_vcpu_has_lapic(vcpu))
1613                 return 0;
1614
1615         tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1616
1617         return (tpr & 0xf0) >> 4;
1618 }
1619
1620 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1621 {
1622         u64 old_value = vcpu->arch.apic_base;
1623         struct kvm_lapic *apic = vcpu->arch.apic;
1624
1625         if (!apic) {
1626                 value |= MSR_IA32_APICBASE_BSP;
1627                 vcpu->arch.apic_base = value;
1628                 return;
1629         }
1630
1631         vcpu->arch.apic_base = value;
1632
1633         /* update jump label if enable bit changes */
1634         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1635                 if (value & MSR_IA32_APICBASE_ENABLE)
1636                         static_key_slow_dec_deferred(&apic_hw_disabled);
1637                 else
1638                         static_key_slow_inc(&apic_hw_disabled.key);
1639                 recalculate_apic_map(vcpu->kvm);
1640         }
1641
1642         if ((old_value ^ value) & X2APIC_ENABLE) {
1643                 if (value & X2APIC_ENABLE) {
1644                         kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
1645                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1646                 } else
1647                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1648         }
1649
1650         apic->base_address = apic->vcpu->arch.apic_base &
1651                              MSR_IA32_APICBASE_BASE;
1652
1653         if ((value & MSR_IA32_APICBASE_ENABLE) &&
1654              apic->base_address != APIC_DEFAULT_PHYS_BASE)
1655                 pr_warn_once("APIC base relocation is unsupported by KVM");
1656
1657         /* with FSB delivery interrupt, we can restart APIC functionality */
1658         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1659                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1660
1661 }
1662
1663 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
1664 {
1665         struct kvm_lapic *apic;
1666         int i;
1667
1668         apic_debug("%s\n", __func__);
1669
1670         ASSERT(vcpu);
1671         apic = vcpu->arch.apic;
1672         ASSERT(apic != NULL);
1673
1674         /* Stop the timer in case it's a reset to an active apic */
1675         hrtimer_cancel(&apic->lapic_timer.timer);
1676
1677         if (!init_event)
1678                 kvm_apic_set_id(apic, vcpu->vcpu_id);
1679         kvm_apic_set_version(apic->vcpu);
1680
1681         for (i = 0; i < APIC_LVT_NUM; i++)
1682                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1683         apic_update_lvtt(apic);
1684         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
1685                 apic_set_reg(apic, APIC_LVT0,
1686                              SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1687         apic_manage_nmi_watchdog(apic, kvm_apic_get_reg(apic, APIC_LVT0));
1688
1689         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1690         apic_set_spiv(apic, 0xff);
1691         apic_set_reg(apic, APIC_TASKPRI, 0);
1692         if (!apic_x2apic_mode(apic))
1693                 kvm_apic_set_ldr(apic, 0);
1694         apic_set_reg(apic, APIC_ESR, 0);
1695         apic_set_reg(apic, APIC_ICR, 0);
1696         apic_set_reg(apic, APIC_ICR2, 0);
1697         apic_set_reg(apic, APIC_TDCR, 0);
1698         apic_set_reg(apic, APIC_TMICT, 0);
1699         for (i = 0; i < 8; i++) {
1700                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1701                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1702                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1703         }
1704         apic->irr_pending = kvm_vcpu_apic_vid_enabled(vcpu);
1705         apic->isr_count = kvm_x86_ops->hwapic_isr_update ? 1 : 0;
1706         apic->highest_isr_cache = -1;
1707         update_divide_count(apic);
1708         atomic_set(&apic->lapic_timer.pending, 0);
1709         if (kvm_vcpu_is_bsp(vcpu))
1710                 kvm_lapic_set_base(vcpu,
1711                                 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1712         vcpu->arch.pv_eoi.msr_val = 0;
1713         apic_update_ppr(apic);
1714
1715         vcpu->arch.apic_arb_prio = 0;
1716         vcpu->arch.apic_attention = 0;
1717
1718         apic_debug("%s: vcpu=%p, id=%d, base_msr="
1719                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1720                    vcpu, kvm_apic_id(apic),
1721                    vcpu->arch.apic_base, apic->base_address);
1722 }
1723
1724 /*
1725  *----------------------------------------------------------------------
1726  * timer interface
1727  *----------------------------------------------------------------------
1728  */
1729
1730 static bool lapic_is_periodic(struct kvm_lapic *apic)
1731 {
1732         return apic_lvtt_period(apic);
1733 }
1734
1735 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1736 {
1737         struct kvm_lapic *apic = vcpu->arch.apic;
1738
1739         if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
1740                         apic_lvt_enabled(apic, APIC_LVTT))
1741                 return atomic_read(&apic->lapic_timer.pending);
1742
1743         return 0;
1744 }
1745
1746 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1747 {
1748         u32 reg = kvm_apic_get_reg(apic, lvt_type);
1749         int vector, mode, trig_mode;
1750
1751         if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1752                 vector = reg & APIC_VECTOR_MASK;
1753                 mode = reg & APIC_MODE_MASK;
1754                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1755                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1756                                         NULL);
1757         }
1758         return 0;
1759 }
1760
1761 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1762 {
1763         struct kvm_lapic *apic = vcpu->arch.apic;
1764
1765         if (apic)
1766                 kvm_apic_local_deliver(apic, APIC_LVT0);
1767 }
1768
1769 static const struct kvm_io_device_ops apic_mmio_ops = {
1770         .read     = apic_mmio_read,
1771         .write    = apic_mmio_write,
1772 };
1773
1774 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1775 {
1776         struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1777         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1778
1779         apic_timer_expired(apic);
1780
1781         if (lapic_is_periodic(apic)) {
1782                 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1783                 return HRTIMER_RESTART;
1784         } else
1785                 return HRTIMER_NORESTART;
1786 }
1787
1788 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1789 {
1790         struct kvm_lapic *apic;
1791
1792         ASSERT(vcpu != NULL);
1793         apic_debug("apic_init %d\n", vcpu->vcpu_id);
1794
1795         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1796         if (!apic)
1797                 goto nomem;
1798
1799         vcpu->arch.apic = apic;
1800
1801         apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1802         if (!apic->regs) {
1803                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1804                        vcpu->vcpu_id);
1805                 goto nomem_free_apic;
1806         }
1807         apic->vcpu = vcpu;
1808
1809         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1810                      HRTIMER_MODE_ABS);
1811         apic->lapic_timer.timer.function = apic_timer_fn;
1812
1813         /*
1814          * APIC is created enabled. This will prevent kvm_lapic_set_base from
1815          * thinking that APIC satet has changed.
1816          */
1817         vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1818         kvm_lapic_set_base(vcpu,
1819                         APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1820
1821         static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1822         kvm_lapic_reset(vcpu, false);
1823         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1824
1825         return 0;
1826 nomem_free_apic:
1827         kfree(apic);
1828 nomem:
1829         return -ENOMEM;
1830 }
1831
1832 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1833 {
1834         struct kvm_lapic *apic = vcpu->arch.apic;
1835         int highest_irr;
1836
1837         if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
1838                 return -1;
1839
1840         apic_update_ppr(apic);
1841         highest_irr = apic_find_highest_irr(apic);
1842         if ((highest_irr == -1) ||
1843             ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
1844                 return -1;
1845         return highest_irr;
1846 }
1847
1848 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1849 {
1850         u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1851         int r = 0;
1852
1853         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1854                 r = 1;
1855         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1856             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1857                 r = 1;
1858         return r;
1859 }
1860
1861 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1862 {
1863         struct kvm_lapic *apic = vcpu->arch.apic;
1864
1865         if (!kvm_vcpu_has_lapic(vcpu))
1866                 return;
1867
1868         if (atomic_read(&apic->lapic_timer.pending) > 0) {
1869                 kvm_apic_local_deliver(apic, APIC_LVTT);
1870                 if (apic_lvtt_tscdeadline(apic))
1871                         apic->lapic_timer.tscdeadline = 0;
1872                 atomic_set(&apic->lapic_timer.pending, 0);
1873         }
1874 }
1875
1876 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1877 {
1878         int vector = kvm_apic_has_interrupt(vcpu);
1879         struct kvm_lapic *apic = vcpu->arch.apic;
1880
1881         if (vector == -1)
1882                 return -1;
1883
1884         /*
1885          * We get here even with APIC virtualization enabled, if doing
1886          * nested virtualization and L1 runs with the "acknowledge interrupt
1887          * on exit" mode.  Then we cannot inject the interrupt via RVI,
1888          * because the process would deliver it through the IDT.
1889          */
1890
1891         apic_set_isr(vector, apic);
1892         apic_update_ppr(apic);
1893         apic_clear_irr(vector, apic);
1894         return vector;
1895 }
1896
1897 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1898                 struct kvm_lapic_state *s)
1899 {
1900         struct kvm_lapic *apic = vcpu->arch.apic;
1901
1902         kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1903         /* set SPIV separately to get count of SW disabled APICs right */
1904         apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1905         memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1906         /* call kvm_apic_set_id() to put apic into apic_map */
1907         kvm_apic_set_id(apic, kvm_apic_id(apic));
1908         kvm_apic_set_version(vcpu);
1909
1910         apic_update_ppr(apic);
1911         hrtimer_cancel(&apic->lapic_timer.timer);
1912         apic_update_lvtt(apic);
1913         apic_manage_nmi_watchdog(apic, kvm_apic_get_reg(apic, APIC_LVT0));
1914         update_divide_count(apic);
1915         start_apic_timer(apic);
1916         apic->irr_pending = true;
1917         apic->isr_count = kvm_x86_ops->hwapic_isr_update ?
1918                                 1 : count_vectors(apic->regs + APIC_ISR);
1919         apic->highest_isr_cache = -1;
1920         if (kvm_x86_ops->hwapic_irr_update)
1921                 kvm_x86_ops->hwapic_irr_update(vcpu,
1922                                 apic_find_highest_irr(apic));
1923         if (unlikely(kvm_x86_ops->hwapic_isr_update))
1924                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
1925                                 apic_find_highest_isr(apic));
1926         kvm_make_request(KVM_REQ_EVENT, vcpu);
1927         if (ioapic_in_kernel(vcpu->kvm))
1928                 kvm_rtc_eoi_tracking_restore_one(vcpu);
1929
1930         vcpu->arch.apic_arb_prio = 0;
1931 }
1932
1933 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1934 {
1935         struct hrtimer *timer;
1936
1937         if (!kvm_vcpu_has_lapic(vcpu))
1938                 return;
1939
1940         timer = &vcpu->arch.apic->lapic_timer.timer;
1941         if (hrtimer_cancel(timer))
1942                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1943 }
1944
1945 /*
1946  * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1947  *
1948  * Detect whether guest triggered PV EOI since the
1949  * last entry. If yes, set EOI on guests's behalf.
1950  * Clear PV EOI in guest memory in any case.
1951  */
1952 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1953                                         struct kvm_lapic *apic)
1954 {
1955         bool pending;
1956         int vector;
1957         /*
1958          * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1959          * and KVM_PV_EOI_ENABLED in guest memory as follows:
1960          *
1961          * KVM_APIC_PV_EOI_PENDING is unset:
1962          *      -> host disabled PV EOI.
1963          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1964          *      -> host enabled PV EOI, guest did not execute EOI yet.
1965          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1966          *      -> host enabled PV EOI, guest executed EOI.
1967          */
1968         BUG_ON(!pv_eoi_enabled(vcpu));
1969         pending = pv_eoi_get_pending(vcpu);
1970         /*
1971          * Clear pending bit in any case: it will be set again on vmentry.
1972          * While this might not be ideal from performance point of view,
1973          * this makes sure pv eoi is only enabled when we know it's safe.
1974          */
1975         pv_eoi_clr_pending(vcpu);
1976         if (pending)
1977                 return;
1978         vector = apic_set_eoi(apic);
1979         trace_kvm_pv_eoi(apic, vector);
1980 }
1981
1982 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1983 {
1984         u32 data;
1985
1986         if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1987                 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1988
1989         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1990                 return;
1991
1992         if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1993                                   sizeof(u32)))
1994                 return;
1995
1996         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1997 }
1998
1999 /*
2000  * apic_sync_pv_eoi_to_guest - called before vmentry
2001  *
2002  * Detect whether it's safe to enable PV EOI and
2003  * if yes do so.
2004  */
2005 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
2006                                         struct kvm_lapic *apic)
2007 {
2008         if (!pv_eoi_enabled(vcpu) ||
2009             /* IRR set or many bits in ISR: could be nested. */
2010             apic->irr_pending ||
2011             /* Cache not set: could be safe but we don't bother. */
2012             apic->highest_isr_cache == -1 ||
2013             /* Need EOI to update ioapic. */
2014             kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
2015                 /*
2016                  * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2017                  * so we need not do anything here.
2018                  */
2019                 return;
2020         }
2021
2022         pv_eoi_set_pending(apic->vcpu);
2023 }
2024
2025 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
2026 {
2027         u32 data, tpr;
2028         int max_irr, max_isr;
2029         struct kvm_lapic *apic = vcpu->arch.apic;
2030
2031         apic_sync_pv_eoi_to_guest(vcpu, apic);
2032
2033         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2034                 return;
2035
2036         tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
2037         max_irr = apic_find_highest_irr(apic);
2038         if (max_irr < 0)
2039                 max_irr = 0;
2040         max_isr = apic_find_highest_isr(apic);
2041         if (max_isr < 0)
2042                 max_isr = 0;
2043         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
2044
2045         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2046                                 sizeof(u32));
2047 }
2048
2049 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
2050 {
2051         if (vapic_addr) {
2052                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2053                                         &vcpu->arch.apic->vapic_cache,
2054                                         vapic_addr, sizeof(u32)))
2055                         return -EINVAL;
2056                 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2057         } else {
2058                 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2059         }
2060
2061         vcpu->arch.apic->vapic_addr = vapic_addr;
2062         return 0;
2063 }
2064
2065 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2066 {
2067         struct kvm_lapic *apic = vcpu->arch.apic;
2068         u32 reg = (msr - APIC_BASE_MSR) << 4;
2069
2070         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2071                 return 1;
2072
2073         if (reg == APIC_ICR2)
2074                 return 1;
2075
2076         /* if this is ICR write vector before command */
2077         if (reg == APIC_ICR)
2078                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2079         return apic_reg_write(apic, reg, (u32)data);
2080 }
2081
2082 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2083 {
2084         struct kvm_lapic *apic = vcpu->arch.apic;
2085         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2086
2087         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2088                 return 1;
2089
2090         if (reg == APIC_DFR || reg == APIC_ICR2) {
2091                 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
2092                            reg);
2093                 return 1;
2094         }
2095
2096         if (apic_reg_read(apic, reg, 4, &low))
2097                 return 1;
2098         if (reg == APIC_ICR)
2099                 apic_reg_read(apic, APIC_ICR2, 4, &high);
2100
2101         *data = (((u64)high) << 32) | low;
2102
2103         return 0;
2104 }
2105
2106 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2107 {
2108         struct kvm_lapic *apic = vcpu->arch.apic;
2109
2110         if (!kvm_vcpu_has_lapic(vcpu))
2111                 return 1;
2112
2113         /* if this is ICR write vector before command */
2114         if (reg == APIC_ICR)
2115                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2116         return apic_reg_write(apic, reg, (u32)data);
2117 }
2118
2119 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2120 {
2121         struct kvm_lapic *apic = vcpu->arch.apic;
2122         u32 low, high = 0;
2123
2124         if (!kvm_vcpu_has_lapic(vcpu))
2125                 return 1;
2126
2127         if (apic_reg_read(apic, reg, 4, &low))
2128                 return 1;
2129         if (reg == APIC_ICR)
2130                 apic_reg_read(apic, APIC_ICR2, 4, &high);
2131
2132         *data = (((u64)high) << 32) | low;
2133
2134         return 0;
2135 }
2136
2137 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
2138 {
2139         u64 addr = data & ~KVM_MSR_ENABLED;
2140         if (!IS_ALIGNED(addr, 4))
2141                 return 1;
2142
2143         vcpu->arch.pv_eoi.msr_val = data;
2144         if (!pv_eoi_enabled(vcpu))
2145                 return 0;
2146         return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
2147                                          addr, sizeof(u8));
2148 }
2149
2150 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2151 {
2152         struct kvm_lapic *apic = vcpu->arch.apic;
2153         u8 sipi_vector;
2154         unsigned long pe;
2155
2156         if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
2157                 return;
2158
2159         /*
2160          * INITs are latched while in SMM.  Because an SMM CPU cannot
2161          * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
2162          * and delay processing of INIT until the next RSM.
2163          */
2164         if (is_smm(vcpu)) {
2165                 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2166                 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2167                         clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2168                 return;
2169         }
2170
2171         pe = xchg(&apic->pending_events, 0);
2172         if (test_bit(KVM_APIC_INIT, &pe)) {
2173                 kvm_lapic_reset(vcpu, true);
2174                 kvm_vcpu_reset(vcpu, true);
2175                 if (kvm_vcpu_is_bsp(apic->vcpu))
2176                         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2177                 else
2178                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2179         }
2180         if (test_bit(KVM_APIC_SIPI, &pe) &&
2181             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2182                 /* evaluate pending_events before reading the vector */
2183                 smp_rmb();
2184                 sipi_vector = apic->sipi_vector;
2185                 apic_debug("vcpu %d received sipi with vector # %x\n",
2186                          vcpu->vcpu_id, sipi_vector);
2187                 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2188                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2189         }
2190 }
2191
2192 void kvm_lapic_init(void)
2193 {
2194         /* do not patch jump label more than once per second */
2195         jump_label_rate_limit(&apic_hw_disabled, HZ);
2196         jump_label_rate_limit(&apic_sw_disabled, HZ);
2197 }
2198
2199 void kvm_lapic_exit(void)
2200 {
2201         static_key_deferred_flush(&apic_hw_disabled);
2202         static_key_deferred_flush(&apic_sw_disabled);
2203 }