2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
27 #include <linux/kvm_host.h>
28 #include <linux/types.h>
29 #include <linux/string.h>
31 #include <linux/highmem.h>
32 #include <linux/module.h>
33 #include <linux/swap.h>
34 #include <linux/hugetlb.h>
35 #include <linux/compiler.h>
36 #include <linux/srcu.h>
37 #include <linux/slab.h>
38 #include <linux/uaccess.h>
41 #include <asm/cmpxchg.h>
46 * When setting this variable to true it enables Two-Dimensional-Paging
47 * where the hardware walks 2 page tables:
48 * 1. the guest-virtual to guest-physical
49 * 2. while doing 1. it walks guest-physical to host-physical
50 * If the hardware supports that we don't need to do shadow paging.
52 bool tdp_enabled = false;
56 AUDIT_POST_PAGE_FAULT,
63 char *audit_point_name[] = {
76 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
77 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
81 #define pgprintk(x...) do { } while (0)
82 #define rmap_printk(x...) do { } while (0)
88 module_param(dbg, bool, 0644);
91 static int oos_shadow = 1;
92 module_param(oos_shadow, bool, 0644);
95 #define ASSERT(x) do { } while (0)
99 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
100 __FILE__, __LINE__, #x); \
104 #define PTE_PREFETCH_NUM 8
106 #define PT_FIRST_AVAIL_BITS_SHIFT 9
107 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
109 #define PT64_LEVEL_BITS 9
111 #define PT64_LEVEL_SHIFT(level) \
112 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
114 #define PT64_INDEX(address, level)\
115 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
118 #define PT32_LEVEL_BITS 10
120 #define PT32_LEVEL_SHIFT(level) \
121 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
123 #define PT32_LVL_OFFSET_MASK(level) \
124 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
125 * PT32_LEVEL_BITS))) - 1))
127 #define PT32_INDEX(address, level)\
128 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
131 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
132 #define PT64_DIR_BASE_ADDR_MASK \
133 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
134 #define PT64_LVL_ADDR_MASK(level) \
135 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
136 * PT64_LEVEL_BITS))) - 1))
137 #define PT64_LVL_OFFSET_MASK(level) \
138 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
139 * PT64_LEVEL_BITS))) - 1))
141 #define PT32_BASE_ADDR_MASK PAGE_MASK
142 #define PT32_DIR_BASE_ADDR_MASK \
143 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
144 #define PT32_LVL_ADDR_MASK(level) \
145 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
146 * PT32_LEVEL_BITS))) - 1))
148 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
151 #define PTE_LIST_EXT 4
153 #define ACC_EXEC_MASK 1
154 #define ACC_WRITE_MASK PT_WRITABLE_MASK
155 #define ACC_USER_MASK PT_USER_MASK
156 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
158 #include <trace/events/kvm.h>
160 #define CREATE_TRACE_POINTS
161 #include "mmutrace.h"
163 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
165 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
167 struct pte_list_desc {
168 u64 *sptes[PTE_LIST_EXT];
169 struct pte_list_desc *more;
172 struct kvm_shadow_walk_iterator {
180 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
181 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
182 shadow_walk_okay(&(_walker)); \
183 shadow_walk_next(&(_walker)))
185 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
186 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
187 shadow_walk_okay(&(_walker)) && \
188 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
189 __shadow_walk_next(&(_walker), spte))
191 static struct kmem_cache *pte_list_desc_cache;
192 static struct kmem_cache *mmu_page_header_cache;
193 static struct percpu_counter kvm_total_used_mmu_pages;
195 static u64 __read_mostly shadow_nx_mask;
196 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
197 static u64 __read_mostly shadow_user_mask;
198 static u64 __read_mostly shadow_accessed_mask;
199 static u64 __read_mostly shadow_dirty_mask;
201 static inline u64 rsvd_bits(int s, int e)
203 return ((1ULL << (e - s + 1)) - 1) << s;
206 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
207 u64 dirty_mask, u64 nx_mask, u64 x_mask)
209 shadow_user_mask = user_mask;
210 shadow_accessed_mask = accessed_mask;
211 shadow_dirty_mask = dirty_mask;
212 shadow_nx_mask = nx_mask;
213 shadow_x_mask = x_mask;
215 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
217 static int is_cpuid_PSE36(void)
222 static int is_nx(struct kvm_vcpu *vcpu)
224 return vcpu->arch.efer & EFER_NX;
227 static int is_shadow_present_pte(u64 pte)
229 return pte & PT_PRESENT_MASK;
232 static int is_large_pte(u64 pte)
234 return pte & PT_PAGE_SIZE_MASK;
237 static int is_dirty_gpte(unsigned long pte)
239 return pte & PT_DIRTY_MASK;
242 static int is_rmap_spte(u64 pte)
244 return is_shadow_present_pte(pte);
247 static int is_last_spte(u64 pte, int level)
249 if (level == PT_PAGE_TABLE_LEVEL)
251 if (is_large_pte(pte))
256 static pfn_t spte_to_pfn(u64 pte)
258 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
261 static gfn_t pse36_gfn_delta(u32 gpte)
263 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
265 return (gpte & PT32_DIR_PSE36_MASK) << shift;
269 static void __set_spte(u64 *sptep, u64 spte)
274 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
279 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
281 return xchg(sptep, spte);
284 static u64 __get_spte_lockless(u64 *sptep)
286 return ACCESS_ONCE(*sptep);
297 static void count_spte_clear(u64 *sptep, u64 spte)
299 struct kvm_mmu_page *sp = page_header(__pa(sptep));
301 if (is_shadow_present_pte(spte))
304 /* Ensure the spte is completely set before we increase the count */
306 sp->clear_spte_count++;
309 static void __set_spte(u64 *sptep, u64 spte)
311 union split_spte *ssptep, sspte;
313 ssptep = (union split_spte *)sptep;
314 sspte = (union split_spte)spte;
316 ssptep->spte_high = sspte.spte_high;
319 * If we map the spte from nonpresent to present, We should store
320 * the high bits firstly, then set present bit, so cpu can not
321 * fetch this spte while we are setting the spte.
325 ssptep->spte_low = sspte.spte_low;
328 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
330 union split_spte *ssptep, sspte;
332 ssptep = (union split_spte *)sptep;
333 sspte = (union split_spte)spte;
335 ssptep->spte_low = sspte.spte_low;
338 * If we map the spte from present to nonpresent, we should clear
339 * present bit firstly to avoid vcpu fetch the old high bits.
343 ssptep->spte_high = sspte.spte_high;
344 count_spte_clear(sptep, spte);
347 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
349 union split_spte *ssptep, sspte, orig;
351 ssptep = (union split_spte *)sptep;
352 sspte = (union split_spte)spte;
354 /* xchg acts as a barrier before the setting of the high bits */
355 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
356 orig.spte_high = ssptep->spte_high = sspte.spte_high;
357 count_spte_clear(sptep, spte);
363 * The idea using the light way get the spte on x86_32 guest is from
364 * gup_get_pte(arch/x86/mm/gup.c).
365 * The difference is we can not catch the spte tlb flush if we leave
366 * guest mode, so we emulate it by increase clear_spte_count when spte
369 static u64 __get_spte_lockless(u64 *sptep)
371 struct kvm_mmu_page *sp = page_header(__pa(sptep));
372 union split_spte spte, *orig = (union split_spte *)sptep;
376 count = sp->clear_spte_count;
379 spte.spte_low = orig->spte_low;
382 spte.spte_high = orig->spte_high;
385 if (unlikely(spte.spte_low != orig->spte_low ||
386 count != sp->clear_spte_count))
393 static bool spte_has_volatile_bits(u64 spte)
395 if (!shadow_accessed_mask)
398 if (!is_shadow_present_pte(spte))
401 if ((spte & shadow_accessed_mask) &&
402 (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
408 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
410 return (old_spte & bit_mask) && !(new_spte & bit_mask);
413 /* Rules for using mmu_spte_set:
414 * Set the sptep from nonpresent to present.
415 * Note: the sptep being assigned *must* be either not present
416 * or in a state where the hardware will not attempt to update
419 static void mmu_spte_set(u64 *sptep, u64 new_spte)
421 WARN_ON(is_shadow_present_pte(*sptep));
422 __set_spte(sptep, new_spte);
425 /* Rules for using mmu_spte_update:
426 * Update the state bits, it means the mapped pfn is not changged.
428 static void mmu_spte_update(u64 *sptep, u64 new_spte)
430 u64 mask, old_spte = *sptep;
432 WARN_ON(!is_rmap_spte(new_spte));
434 if (!is_shadow_present_pte(old_spte))
435 return mmu_spte_set(sptep, new_spte);
437 new_spte |= old_spte & shadow_dirty_mask;
439 mask = shadow_accessed_mask;
440 if (is_writable_pte(old_spte))
441 mask |= shadow_dirty_mask;
443 if (!spte_has_volatile_bits(old_spte) || (new_spte & mask) == mask)
444 __update_clear_spte_fast(sptep, new_spte);
446 old_spte = __update_clear_spte_slow(sptep, new_spte);
448 if (!shadow_accessed_mask)
451 if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
452 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
453 if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
454 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
458 * Rules for using mmu_spte_clear_track_bits:
459 * It sets the sptep from present to nonpresent, and track the
460 * state bits, it is used to clear the last level sptep.
462 static int mmu_spte_clear_track_bits(u64 *sptep)
465 u64 old_spte = *sptep;
467 if (!spte_has_volatile_bits(old_spte))
468 __update_clear_spte_fast(sptep, 0ull);
470 old_spte = __update_clear_spte_slow(sptep, 0ull);
472 if (!is_rmap_spte(old_spte))
475 pfn = spte_to_pfn(old_spte);
476 if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
477 kvm_set_pfn_accessed(pfn);
478 if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
479 kvm_set_pfn_dirty(pfn);
484 * Rules for using mmu_spte_clear_no_track:
485 * Directly clear spte without caring the state bits of sptep,
486 * it is used to set the upper level spte.
488 static void mmu_spte_clear_no_track(u64 *sptep)
490 __update_clear_spte_fast(sptep, 0ull);
493 static u64 mmu_spte_get_lockless(u64 *sptep)
495 return __get_spte_lockless(sptep);
498 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
501 atomic_inc(&vcpu->kvm->arch.reader_counter);
503 /* Increase the counter before walking shadow page table */
504 smp_mb__after_atomic_inc();
507 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
509 /* Decrease the counter after walking shadow page table finished */
510 smp_mb__before_atomic_dec();
511 atomic_dec(&vcpu->kvm->arch.reader_counter);
515 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
516 struct kmem_cache *base_cache, int min)
520 if (cache->nobjs >= min)
522 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
523 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
526 cache->objects[cache->nobjs++] = obj;
531 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
532 struct kmem_cache *cache)
535 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
538 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
543 if (cache->nobjs >= min)
545 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
546 page = (void *)__get_free_page(GFP_KERNEL);
549 cache->objects[cache->nobjs++] = page;
554 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
557 free_page((unsigned long)mc->objects[--mc->nobjs]);
560 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
564 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
565 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
568 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
571 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
572 mmu_page_header_cache, 4);
577 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
579 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
580 pte_list_desc_cache);
581 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
582 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
583 mmu_page_header_cache);
586 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
592 p = mc->objects[--mc->nobjs];
596 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
598 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache,
599 sizeof(struct pte_list_desc));
602 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
604 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
607 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
609 if (!sp->role.direct)
610 return sp->gfns[index];
612 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
615 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
618 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
620 sp->gfns[index] = gfn;
624 * Return the pointer to the large page information for a given gfn,
625 * handling slots that are not large page aligned.
627 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
628 struct kvm_memory_slot *slot,
633 idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
634 (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
635 return &slot->lpage_info[level - 2][idx];
638 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
640 struct kvm_memory_slot *slot;
641 struct kvm_lpage_info *linfo;
644 slot = gfn_to_memslot(kvm, gfn);
645 for (i = PT_DIRECTORY_LEVEL;
646 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
647 linfo = lpage_info_slot(gfn, slot, i);
648 linfo->write_count += 1;
650 kvm->arch.indirect_shadow_pages++;
653 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
655 struct kvm_memory_slot *slot;
656 struct kvm_lpage_info *linfo;
659 slot = gfn_to_memslot(kvm, gfn);
660 for (i = PT_DIRECTORY_LEVEL;
661 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
662 linfo = lpage_info_slot(gfn, slot, i);
663 linfo->write_count -= 1;
664 WARN_ON(linfo->write_count < 0);
666 kvm->arch.indirect_shadow_pages--;
669 static int has_wrprotected_page(struct kvm *kvm,
673 struct kvm_memory_slot *slot;
674 struct kvm_lpage_info *linfo;
676 slot = gfn_to_memslot(kvm, gfn);
678 linfo = lpage_info_slot(gfn, slot, level);
679 return linfo->write_count;
685 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
687 unsigned long page_size;
690 page_size = kvm_host_page_size(kvm, gfn);
692 for (i = PT_PAGE_TABLE_LEVEL;
693 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
694 if (page_size >= KVM_HPAGE_SIZE(i))
703 static struct kvm_memory_slot *
704 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
707 struct kvm_memory_slot *slot;
709 slot = gfn_to_memslot(vcpu->kvm, gfn);
710 if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
711 (no_dirty_log && slot->dirty_bitmap))
717 static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn)
719 return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true);
722 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
724 int host_level, level, max_level;
726 host_level = host_mapping_level(vcpu->kvm, large_gfn);
728 if (host_level == PT_PAGE_TABLE_LEVEL)
731 max_level = kvm_x86_ops->get_lpage_level() < host_level ?
732 kvm_x86_ops->get_lpage_level() : host_level;
734 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
735 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
742 * Pte mapping structures:
744 * If pte_list bit zero is zero, then pte_list point to the spte.
746 * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
747 * pte_list_desc containing more mappings.
749 * Returns the number of pte entries before the spte was added or zero if
750 * the spte was not added.
753 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
754 unsigned long *pte_list)
756 struct pte_list_desc *desc;
760 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
761 *pte_list = (unsigned long)spte;
762 } else if (!(*pte_list & 1)) {
763 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
764 desc = mmu_alloc_pte_list_desc(vcpu);
765 desc->sptes[0] = (u64 *)*pte_list;
766 desc->sptes[1] = spte;
767 *pte_list = (unsigned long)desc | 1;
770 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
771 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
772 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
774 count += PTE_LIST_EXT;
776 if (desc->sptes[PTE_LIST_EXT-1]) {
777 desc->more = mmu_alloc_pte_list_desc(vcpu);
780 for (i = 0; desc->sptes[i]; ++i)
782 desc->sptes[i] = spte;
787 static u64 *pte_list_next(unsigned long *pte_list, u64 *spte)
789 struct pte_list_desc *desc;
795 else if (!(*pte_list & 1)) {
797 return (u64 *)*pte_list;
800 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
803 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
804 if (prev_spte == spte)
805 return desc->sptes[i];
806 prev_spte = desc->sptes[i];
814 pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc,
815 int i, struct pte_list_desc *prev_desc)
819 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
821 desc->sptes[i] = desc->sptes[j];
822 desc->sptes[j] = NULL;
825 if (!prev_desc && !desc->more)
826 *pte_list = (unsigned long)desc->sptes[0];
829 prev_desc->more = desc->more;
831 *pte_list = (unsigned long)desc->more | 1;
832 mmu_free_pte_list_desc(desc);
835 static void pte_list_remove(u64 *spte, unsigned long *pte_list)
837 struct pte_list_desc *desc;
838 struct pte_list_desc *prev_desc;
842 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
844 } else if (!(*pte_list & 1)) {
845 rmap_printk("pte_list_remove: %p 1->0\n", spte);
846 if ((u64 *)*pte_list != spte) {
847 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
852 rmap_printk("pte_list_remove: %p many->many\n", spte);
853 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
856 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
857 if (desc->sptes[i] == spte) {
858 pte_list_desc_remove_entry(pte_list,
866 pr_err("pte_list_remove: %p many->many\n", spte);
871 typedef void (*pte_list_walk_fn) (u64 *spte);
872 static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
874 struct pte_list_desc *desc;
880 if (!(*pte_list & 1))
881 return fn((u64 *)*pte_list);
883 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
885 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
892 * Take gfn and return the reverse mapping to it.
894 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
896 struct kvm_memory_slot *slot;
897 struct kvm_lpage_info *linfo;
899 slot = gfn_to_memslot(kvm, gfn);
900 if (likely(level == PT_PAGE_TABLE_LEVEL))
901 return &slot->rmap[gfn - slot->base_gfn];
903 linfo = lpage_info_slot(gfn, slot, level);
905 return &linfo->rmap_pde;
908 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
910 struct kvm_mmu_page *sp;
911 unsigned long *rmapp;
913 sp = page_header(__pa(spte));
914 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
915 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
916 return pte_list_add(vcpu, spte, rmapp);
919 static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
921 return pte_list_next(rmapp, spte);
924 static void rmap_remove(struct kvm *kvm, u64 *spte)
926 struct kvm_mmu_page *sp;
928 unsigned long *rmapp;
930 sp = page_header(__pa(spte));
931 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
932 rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
933 pte_list_remove(spte, rmapp);
936 static void drop_spte(struct kvm *kvm, u64 *sptep)
938 if (mmu_spte_clear_track_bits(sptep))
939 rmap_remove(kvm, sptep);
942 static int rmap_write_protect(struct kvm *kvm, u64 gfn)
944 unsigned long *rmapp;
946 int i, write_protected = 0;
948 rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
950 spte = rmap_next(kvm, rmapp, NULL);
953 BUG_ON(!(*spte & PT_PRESENT_MASK));
954 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
955 if (is_writable_pte(*spte)) {
956 mmu_spte_update(spte, *spte & ~PT_WRITABLE_MASK);
959 spte = rmap_next(kvm, rmapp, spte);
962 /* check for huge page mappings */
963 for (i = PT_DIRECTORY_LEVEL;
964 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
965 rmapp = gfn_to_rmap(kvm, gfn, i);
966 spte = rmap_next(kvm, rmapp, NULL);
969 BUG_ON(!(*spte & PT_PRESENT_MASK));
970 BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
971 pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
972 if (is_writable_pte(*spte)) {
973 drop_spte(kvm, spte);
978 spte = rmap_next(kvm, rmapp, spte);
982 return write_protected;
985 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
989 int need_tlb_flush = 0;
991 while ((spte = rmap_next(kvm, rmapp, NULL))) {
992 BUG_ON(!(*spte & PT_PRESENT_MASK));
993 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
994 drop_spte(kvm, spte);
997 return need_tlb_flush;
1000 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
1004 u64 *spte, new_spte;
1005 pte_t *ptep = (pte_t *)data;
1008 WARN_ON(pte_huge(*ptep));
1009 new_pfn = pte_pfn(*ptep);
1010 spte = rmap_next(kvm, rmapp, NULL);
1012 BUG_ON(!is_shadow_present_pte(*spte));
1013 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
1015 if (pte_write(*ptep)) {
1016 drop_spte(kvm, spte);
1017 spte = rmap_next(kvm, rmapp, NULL);
1019 new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
1020 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1022 new_spte &= ~PT_WRITABLE_MASK;
1023 new_spte &= ~SPTE_HOST_WRITEABLE;
1024 new_spte &= ~shadow_accessed_mask;
1025 mmu_spte_clear_track_bits(spte);
1026 mmu_spte_set(spte, new_spte);
1027 spte = rmap_next(kvm, rmapp, spte);
1031 kvm_flush_remote_tlbs(kvm);
1036 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1038 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
1039 unsigned long data))
1044 struct kvm_memslots *slots;
1046 slots = kvm_memslots(kvm);
1048 for (i = 0; i < slots->nmemslots; i++) {
1049 struct kvm_memory_slot *memslot = &slots->memslots[i];
1050 unsigned long start = memslot->userspace_addr;
1053 end = start + (memslot->npages << PAGE_SHIFT);
1054 if (hva >= start && hva < end) {
1055 gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
1056 gfn_t gfn = memslot->base_gfn + gfn_offset;
1058 ret = handler(kvm, &memslot->rmap[gfn_offset], data);
1060 for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
1061 struct kvm_lpage_info *linfo;
1063 linfo = lpage_info_slot(gfn, memslot,
1064 PT_DIRECTORY_LEVEL + j);
1065 ret |= handler(kvm, &linfo->rmap_pde, data);
1067 trace_kvm_age_page(hva, memslot, ret);
1075 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1077 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1080 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1082 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1085 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1092 * Emulate the accessed bit for EPT, by checking if this page has
1093 * an EPT mapping, and clearing it if it does. On the next access,
1094 * a new EPT mapping will be established.
1095 * This has some overhead, but not as much as the cost of swapping
1096 * out actively used pages or breaking up actively used hugepages.
1098 if (!shadow_accessed_mask)
1099 return kvm_unmap_rmapp(kvm, rmapp, data);
1101 spte = rmap_next(kvm, rmapp, NULL);
1105 BUG_ON(!(_spte & PT_PRESENT_MASK));
1106 _young = _spte & PT_ACCESSED_MASK;
1109 clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
1111 spte = rmap_next(kvm, rmapp, spte);
1116 static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1123 * If there's no access bit in the secondary pte set by the
1124 * hardware it's up to gup-fast/gup to set the access bit in
1125 * the primary pte or in the page structure.
1127 if (!shadow_accessed_mask)
1130 spte = rmap_next(kvm, rmapp, NULL);
1133 BUG_ON(!(_spte & PT_PRESENT_MASK));
1134 young = _spte & PT_ACCESSED_MASK;
1139 spte = rmap_next(kvm, rmapp, spte);
1145 #define RMAP_RECYCLE_THRESHOLD 1000
1147 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1149 unsigned long *rmapp;
1150 struct kvm_mmu_page *sp;
1152 sp = page_header(__pa(spte));
1154 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1156 kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
1157 kvm_flush_remote_tlbs(vcpu->kvm);
1160 int kvm_age_hva(struct kvm *kvm, unsigned long hva)
1162 return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
1165 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1167 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1171 static int is_empty_shadow_page(u64 *spt)
1176 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1177 if (is_shadow_present_pte(*pos)) {
1178 printk(KERN_ERR "%s: %p %llx\n", __func__,
1187 * This value is the sum of all of the kvm instances's
1188 * kvm->arch.n_used_mmu_pages values. We need a global,
1189 * aggregate version in order to make the slab shrinker
1192 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1194 kvm->arch.n_used_mmu_pages += nr;
1195 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1199 * Remove the sp from shadow page cache, after call it,
1200 * we can not find this sp from the cache, and the shadow
1201 * page table is still valid.
1202 * It should be under the protection of mmu lock.
1204 static void kvm_mmu_isolate_page(struct kvm_mmu_page *sp)
1206 ASSERT(is_empty_shadow_page(sp->spt));
1207 hlist_del(&sp->hash_link);
1208 if (!sp->role.direct)
1209 free_page((unsigned long)sp->gfns);
1213 * Free the shadow page table and the sp, we can do it
1214 * out of the protection of mmu lock.
1216 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1218 list_del(&sp->link);
1219 free_page((unsigned long)sp->spt);
1220 kmem_cache_free(mmu_page_header_cache, sp);
1223 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1225 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1228 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1229 struct kvm_mmu_page *sp, u64 *parent_pte)
1234 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1237 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1240 pte_list_remove(parent_pte, &sp->parent_ptes);
1243 static void drop_parent_pte(struct kvm_mmu_page *sp,
1246 mmu_page_remove_parent_pte(sp, parent_pte);
1247 mmu_spte_clear_no_track(parent_pte);
1250 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1251 u64 *parent_pte, int direct)
1253 struct kvm_mmu_page *sp;
1254 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache,
1256 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
1258 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache,
1260 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1261 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1262 bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
1263 sp->parent_ptes = 0;
1264 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1265 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1269 static void mark_unsync(u64 *spte);
1270 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1272 pte_list_walk(&sp->parent_ptes, mark_unsync);
1275 static void mark_unsync(u64 *spte)
1277 struct kvm_mmu_page *sp;
1280 sp = page_header(__pa(spte));
1281 index = spte - sp->spt;
1282 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1284 if (sp->unsync_children++)
1286 kvm_mmu_mark_parents_unsync(sp);
1289 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1290 struct kvm_mmu_page *sp)
1295 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1299 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1300 struct kvm_mmu_page *sp, u64 *spte,
1306 #define KVM_PAGE_ARRAY_NR 16
1308 struct kvm_mmu_pages {
1309 struct mmu_page_and_offset {
1310 struct kvm_mmu_page *sp;
1312 } page[KVM_PAGE_ARRAY_NR];
1316 #define for_each_unsync_children(bitmap, idx) \
1317 for (idx = find_first_bit(bitmap, 512); \
1319 idx = find_next_bit(bitmap, 512, idx+1))
1321 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1327 for (i=0; i < pvec->nr; i++)
1328 if (pvec->page[i].sp == sp)
1331 pvec->page[pvec->nr].sp = sp;
1332 pvec->page[pvec->nr].idx = idx;
1334 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1337 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1338 struct kvm_mmu_pages *pvec)
1340 int i, ret, nr_unsync_leaf = 0;
1342 for_each_unsync_children(sp->unsync_child_bitmap, i) {
1343 struct kvm_mmu_page *child;
1344 u64 ent = sp->spt[i];
1346 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1347 goto clear_child_bitmap;
1349 child = page_header(ent & PT64_BASE_ADDR_MASK);
1351 if (child->unsync_children) {
1352 if (mmu_pages_add(pvec, child, i))
1355 ret = __mmu_unsync_walk(child, pvec);
1357 goto clear_child_bitmap;
1359 nr_unsync_leaf += ret;
1362 } else if (child->unsync) {
1364 if (mmu_pages_add(pvec, child, i))
1367 goto clear_child_bitmap;
1372 __clear_bit(i, sp->unsync_child_bitmap);
1373 sp->unsync_children--;
1374 WARN_ON((int)sp->unsync_children < 0);
1378 return nr_unsync_leaf;
1381 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1382 struct kvm_mmu_pages *pvec)
1384 if (!sp->unsync_children)
1387 mmu_pages_add(pvec, sp, 0);
1388 return __mmu_unsync_walk(sp, pvec);
1391 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1393 WARN_ON(!sp->unsync);
1394 trace_kvm_mmu_sync_page(sp);
1396 --kvm->stat.mmu_unsync;
1399 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1400 struct list_head *invalid_list);
1401 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1402 struct list_head *invalid_list);
1404 #define for_each_gfn_sp(kvm, sp, gfn, pos) \
1405 hlist_for_each_entry(sp, pos, \
1406 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1407 if ((sp)->gfn != (gfn)) {} else
1409 #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \
1410 hlist_for_each_entry(sp, pos, \
1411 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1412 if ((sp)->gfn != (gfn) || (sp)->role.direct || \
1413 (sp)->role.invalid) {} else
1415 /* @sp->gfn should be write-protected at the call site */
1416 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1417 struct list_head *invalid_list, bool clear_unsync)
1419 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1420 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1425 kvm_unlink_unsync_page(vcpu->kvm, sp);
1427 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1428 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1432 kvm_mmu_flush_tlb(vcpu);
1436 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1437 struct kvm_mmu_page *sp)
1439 LIST_HEAD(invalid_list);
1442 ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1444 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1449 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1450 struct list_head *invalid_list)
1452 return __kvm_sync_page(vcpu, sp, invalid_list, true);
1455 /* @gfn should be write-protected at the call site */
1456 static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1458 struct kvm_mmu_page *s;
1459 struct hlist_node *node;
1460 LIST_HEAD(invalid_list);
1463 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
1467 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1468 kvm_unlink_unsync_page(vcpu->kvm, s);
1469 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1470 (vcpu->arch.mmu.sync_page(vcpu, s))) {
1471 kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1477 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1479 kvm_mmu_flush_tlb(vcpu);
1482 struct mmu_page_path {
1483 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1484 unsigned int idx[PT64_ROOT_LEVEL-1];
1487 #define for_each_sp(pvec, sp, parents, i) \
1488 for (i = mmu_pages_next(&pvec, &parents, -1), \
1489 sp = pvec.page[i].sp; \
1490 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1491 i = mmu_pages_next(&pvec, &parents, i))
1493 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1494 struct mmu_page_path *parents,
1499 for (n = i+1; n < pvec->nr; n++) {
1500 struct kvm_mmu_page *sp = pvec->page[n].sp;
1502 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1503 parents->idx[0] = pvec->page[n].idx;
1507 parents->parent[sp->role.level-2] = sp;
1508 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1514 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1516 struct kvm_mmu_page *sp;
1517 unsigned int level = 0;
1520 unsigned int idx = parents->idx[level];
1522 sp = parents->parent[level];
1526 --sp->unsync_children;
1527 WARN_ON((int)sp->unsync_children < 0);
1528 __clear_bit(idx, sp->unsync_child_bitmap);
1530 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1533 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1534 struct mmu_page_path *parents,
1535 struct kvm_mmu_pages *pvec)
1537 parents->parent[parent->role.level-1] = NULL;
1541 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1542 struct kvm_mmu_page *parent)
1545 struct kvm_mmu_page *sp;
1546 struct mmu_page_path parents;
1547 struct kvm_mmu_pages pages;
1548 LIST_HEAD(invalid_list);
1550 kvm_mmu_pages_init(parent, &parents, &pages);
1551 while (mmu_unsync_walk(parent, &pages)) {
1554 for_each_sp(pages, sp, parents, i)
1555 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1558 kvm_flush_remote_tlbs(vcpu->kvm);
1560 for_each_sp(pages, sp, parents, i) {
1561 kvm_sync_page(vcpu, sp, &invalid_list);
1562 mmu_pages_clear_parents(&parents);
1564 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1565 cond_resched_lock(&vcpu->kvm->mmu_lock);
1566 kvm_mmu_pages_init(parent, &parents, &pages);
1570 static void init_shadow_page_table(struct kvm_mmu_page *sp)
1574 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1578 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1586 union kvm_mmu_page_role role;
1588 struct kvm_mmu_page *sp;
1589 struct hlist_node *node;
1590 bool need_sync = false;
1592 role = vcpu->arch.mmu.base_role;
1594 role.direct = direct;
1597 role.access = access;
1598 if (!vcpu->arch.mmu.direct_map
1599 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1600 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1601 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1602 role.quadrant = quadrant;
1604 for_each_gfn_sp(vcpu->kvm, sp, gfn, node) {
1605 if (!need_sync && sp->unsync)
1608 if (sp->role.word != role.word)
1611 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1614 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1615 if (sp->unsync_children) {
1616 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1617 kvm_mmu_mark_parents_unsync(sp);
1618 } else if (sp->unsync)
1619 kvm_mmu_mark_parents_unsync(sp);
1621 trace_kvm_mmu_get_page(sp, false);
1624 ++vcpu->kvm->stat.mmu_cache_miss;
1625 sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
1630 hlist_add_head(&sp->hash_link,
1631 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
1633 if (rmap_write_protect(vcpu->kvm, gfn))
1634 kvm_flush_remote_tlbs(vcpu->kvm);
1635 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1636 kvm_sync_pages(vcpu, gfn);
1638 account_shadowed(vcpu->kvm, gfn);
1640 init_shadow_page_table(sp);
1641 trace_kvm_mmu_get_page(sp, true);
1645 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1646 struct kvm_vcpu *vcpu, u64 addr)
1648 iterator->addr = addr;
1649 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1650 iterator->level = vcpu->arch.mmu.shadow_root_level;
1652 if (iterator->level == PT64_ROOT_LEVEL &&
1653 vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
1654 !vcpu->arch.mmu.direct_map)
1657 if (iterator->level == PT32E_ROOT_LEVEL) {
1658 iterator->shadow_addr
1659 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1660 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1662 if (!iterator->shadow_addr)
1663 iterator->level = 0;
1667 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1669 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1672 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1673 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1677 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
1680 if (is_last_spte(spte, iterator->level)) {
1681 iterator->level = 0;
1685 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
1689 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1691 return __shadow_walk_next(iterator, *iterator->sptep);
1694 static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp)
1698 spte = __pa(sp->spt)
1699 | PT_PRESENT_MASK | PT_ACCESSED_MASK
1700 | PT_WRITABLE_MASK | PT_USER_MASK;
1701 mmu_spte_set(sptep, spte);
1704 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1706 if (is_large_pte(*sptep)) {
1707 drop_spte(vcpu->kvm, sptep);
1708 kvm_flush_remote_tlbs(vcpu->kvm);
1712 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1713 unsigned direct_access)
1715 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
1716 struct kvm_mmu_page *child;
1719 * For the direct sp, if the guest pte's dirty bit
1720 * changed form clean to dirty, it will corrupt the
1721 * sp's access: allow writable in the read-only sp,
1722 * so we should update the spte at this point to get
1723 * a new sp with the correct access.
1725 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
1726 if (child->role.access == direct_access)
1729 drop_parent_pte(child, sptep);
1730 kvm_flush_remote_tlbs(vcpu->kvm);
1734 static void mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
1738 struct kvm_mmu_page *child;
1741 if (is_shadow_present_pte(pte)) {
1742 if (is_last_spte(pte, sp->role.level))
1743 drop_spte(kvm, spte);
1745 child = page_header(pte & PT64_BASE_ADDR_MASK);
1746 drop_parent_pte(child, spte);
1750 if (is_large_pte(pte))
1754 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
1755 struct kvm_mmu_page *sp)
1759 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1760 mmu_page_zap_pte(kvm, sp, sp->spt + i);
1763 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
1765 mmu_page_remove_parent_pte(sp, parent_pte);
1768 static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
1771 struct kvm_vcpu *vcpu;
1773 kvm_for_each_vcpu(i, vcpu, kvm)
1774 vcpu->arch.last_pte_updated = NULL;
1777 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
1781 while ((parent_pte = pte_list_next(&sp->parent_ptes, NULL)))
1782 drop_parent_pte(sp, parent_pte);
1785 static int mmu_zap_unsync_children(struct kvm *kvm,
1786 struct kvm_mmu_page *parent,
1787 struct list_head *invalid_list)
1790 struct mmu_page_path parents;
1791 struct kvm_mmu_pages pages;
1793 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
1796 kvm_mmu_pages_init(parent, &parents, &pages);
1797 while (mmu_unsync_walk(parent, &pages)) {
1798 struct kvm_mmu_page *sp;
1800 for_each_sp(pages, sp, parents, i) {
1801 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
1802 mmu_pages_clear_parents(&parents);
1805 kvm_mmu_pages_init(parent, &parents, &pages);
1811 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1812 struct list_head *invalid_list)
1816 trace_kvm_mmu_prepare_zap_page(sp);
1817 ++kvm->stat.mmu_shadow_zapped;
1818 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
1819 kvm_mmu_page_unlink_children(kvm, sp);
1820 kvm_mmu_unlink_parents(kvm, sp);
1821 if (!sp->role.invalid && !sp->role.direct)
1822 unaccount_shadowed(kvm, sp->gfn);
1824 kvm_unlink_unsync_page(kvm, sp);
1825 if (!sp->root_count) {
1828 list_move(&sp->link, invalid_list);
1829 kvm_mod_used_mmu_pages(kvm, -1);
1831 list_move(&sp->link, &kvm->arch.active_mmu_pages);
1832 kvm_reload_remote_mmus(kvm);
1835 sp->role.invalid = 1;
1836 kvm_mmu_reset_last_pte_updated(kvm);
1840 static void kvm_mmu_isolate_pages(struct list_head *invalid_list)
1842 struct kvm_mmu_page *sp;
1844 list_for_each_entry(sp, invalid_list, link)
1845 kvm_mmu_isolate_page(sp);
1848 static void free_pages_rcu(struct rcu_head *head)
1850 struct kvm_mmu_page *next, *sp;
1852 sp = container_of(head, struct kvm_mmu_page, rcu);
1854 if (!list_empty(&sp->link))
1855 next = list_first_entry(&sp->link,
1856 struct kvm_mmu_page, link);
1859 kvm_mmu_free_page(sp);
1864 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1865 struct list_head *invalid_list)
1867 struct kvm_mmu_page *sp;
1869 if (list_empty(invalid_list))
1872 kvm_flush_remote_tlbs(kvm);
1874 if (atomic_read(&kvm->arch.reader_counter)) {
1875 kvm_mmu_isolate_pages(invalid_list);
1876 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
1877 list_del_init(invalid_list);
1878 call_rcu(&sp->rcu, free_pages_rcu);
1883 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
1884 WARN_ON(!sp->role.invalid || sp->root_count);
1885 kvm_mmu_isolate_page(sp);
1886 kvm_mmu_free_page(sp);
1887 } while (!list_empty(invalid_list));
1892 * Changing the number of mmu pages allocated to the vm
1893 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
1895 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
1897 LIST_HEAD(invalid_list);
1899 * If we set the number of mmu pages to be smaller be than the
1900 * number of actived pages , we must to free some mmu pages before we
1904 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
1905 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages &&
1906 !list_empty(&kvm->arch.active_mmu_pages)) {
1907 struct kvm_mmu_page *page;
1909 page = container_of(kvm->arch.active_mmu_pages.prev,
1910 struct kvm_mmu_page, link);
1911 kvm_mmu_prepare_zap_page(kvm, page, &invalid_list);
1913 kvm_mmu_commit_zap_page(kvm, &invalid_list);
1914 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
1917 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
1920 static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
1922 struct kvm_mmu_page *sp;
1923 struct hlist_node *node;
1924 LIST_HEAD(invalid_list);
1927 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
1930 for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
1931 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
1934 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
1936 kvm_mmu_commit_zap_page(kvm, &invalid_list);
1940 static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
1942 struct kvm_mmu_page *sp;
1943 struct hlist_node *node;
1944 LIST_HEAD(invalid_list);
1946 for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
1947 pgprintk("%s: zap %llx %x\n",
1948 __func__, gfn, sp->role.word);
1949 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
1951 kvm_mmu_commit_zap_page(kvm, &invalid_list);
1954 static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
1956 int slot = memslot_id(kvm, gfn);
1957 struct kvm_mmu_page *sp = page_header(__pa(pte));
1959 __set_bit(slot, sp->slot_bitmap);
1963 * The function is based on mtrr_type_lookup() in
1964 * arch/x86/kernel/cpu/mtrr/generic.c
1966 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
1971 u8 prev_match, curr_match;
1972 int num_var_ranges = KVM_NR_VAR_MTRR;
1974 if (!mtrr_state->enabled)
1977 /* Make end inclusive end, instead of exclusive */
1980 /* Look in fixed ranges. Just return the type as per start */
1981 if (mtrr_state->have_fixed && (start < 0x100000)) {
1984 if (start < 0x80000) {
1986 idx += (start >> 16);
1987 return mtrr_state->fixed_ranges[idx];
1988 } else if (start < 0xC0000) {
1990 idx += ((start - 0x80000) >> 14);
1991 return mtrr_state->fixed_ranges[idx];
1992 } else if (start < 0x1000000) {
1994 idx += ((start - 0xC0000) >> 12);
1995 return mtrr_state->fixed_ranges[idx];
2000 * Look in variable ranges
2001 * Look of multiple ranges matching this address and pick type
2002 * as per MTRR precedence
2004 if (!(mtrr_state->enabled & 2))
2005 return mtrr_state->def_type;
2008 for (i = 0; i < num_var_ranges; ++i) {
2009 unsigned short start_state, end_state;
2011 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
2014 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
2015 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
2016 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
2017 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
2019 start_state = ((start & mask) == (base & mask));
2020 end_state = ((end & mask) == (base & mask));
2021 if (start_state != end_state)
2024 if ((start & mask) != (base & mask))
2027 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
2028 if (prev_match == 0xFF) {
2029 prev_match = curr_match;
2033 if (prev_match == MTRR_TYPE_UNCACHABLE ||
2034 curr_match == MTRR_TYPE_UNCACHABLE)
2035 return MTRR_TYPE_UNCACHABLE;
2037 if ((prev_match == MTRR_TYPE_WRBACK &&
2038 curr_match == MTRR_TYPE_WRTHROUGH) ||
2039 (prev_match == MTRR_TYPE_WRTHROUGH &&
2040 curr_match == MTRR_TYPE_WRBACK)) {
2041 prev_match = MTRR_TYPE_WRTHROUGH;
2042 curr_match = MTRR_TYPE_WRTHROUGH;
2045 if (prev_match != curr_match)
2046 return MTRR_TYPE_UNCACHABLE;
2049 if (prev_match != 0xFF)
2052 return mtrr_state->def_type;
2055 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
2059 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
2060 (gfn << PAGE_SHIFT) + PAGE_SIZE);
2061 if (mtrr == 0xfe || mtrr == 0xff)
2062 mtrr = MTRR_TYPE_WRBACK;
2065 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
2067 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2069 trace_kvm_mmu_unsync_page(sp);
2070 ++vcpu->kvm->stat.mmu_unsync;
2073 kvm_mmu_mark_parents_unsync(sp);
2076 static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
2078 struct kvm_mmu_page *s;
2079 struct hlist_node *node;
2081 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2084 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2085 __kvm_unsync_page(vcpu, s);
2089 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2092 struct kvm_mmu_page *s;
2093 struct hlist_node *node;
2094 bool need_unsync = false;
2096 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2100 if (s->role.level != PT_PAGE_TABLE_LEVEL)
2103 if (!need_unsync && !s->unsync) {
2110 kvm_unsync_pages(vcpu, gfn);
2114 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2115 unsigned pte_access, int user_fault,
2116 int write_fault, int level,
2117 gfn_t gfn, pfn_t pfn, bool speculative,
2118 bool can_unsync, bool host_writable)
2120 u64 spte, entry = *sptep;
2124 * We don't set the accessed bit, since we sometimes want to see
2125 * whether the guest actually used the pte (in order to detect
2128 spte = PT_PRESENT_MASK;
2130 spte |= shadow_accessed_mask;
2132 if (pte_access & ACC_EXEC_MASK)
2133 spte |= shadow_x_mask;
2135 spte |= shadow_nx_mask;
2136 if (pte_access & ACC_USER_MASK)
2137 spte |= shadow_user_mask;
2138 if (level > PT_PAGE_TABLE_LEVEL)
2139 spte |= PT_PAGE_SIZE_MASK;
2141 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2142 kvm_is_mmio_pfn(pfn));
2145 spte |= SPTE_HOST_WRITEABLE;
2147 pte_access &= ~ACC_WRITE_MASK;
2149 spte |= (u64)pfn << PAGE_SHIFT;
2151 if ((pte_access & ACC_WRITE_MASK)
2152 || (!vcpu->arch.mmu.direct_map && write_fault
2153 && !is_write_protection(vcpu) && !user_fault)) {
2155 if (level > PT_PAGE_TABLE_LEVEL &&
2156 has_wrprotected_page(vcpu->kvm, gfn, level)) {
2158 drop_spte(vcpu->kvm, sptep);
2162 spte |= PT_WRITABLE_MASK;
2164 if (!vcpu->arch.mmu.direct_map
2165 && !(pte_access & ACC_WRITE_MASK)) {
2166 spte &= ~PT_USER_MASK;
2168 * If we converted a user page to a kernel page,
2169 * so that the kernel can write to it when cr0.wp=0,
2170 * then we should prevent the kernel from executing it
2171 * if SMEP is enabled.
2173 if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
2174 spte |= PT64_NX_MASK;
2178 * Optimization: for pte sync, if spte was writable the hash
2179 * lookup is unnecessary (and expensive). Write protection
2180 * is responsibility of mmu_get_page / kvm_sync_page.
2181 * Same reasoning can be applied to dirty page accounting.
2183 if (!can_unsync && is_writable_pte(*sptep))
2186 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2187 pgprintk("%s: found shadow page for %llx, marking ro\n",
2190 pte_access &= ~ACC_WRITE_MASK;
2191 if (is_writable_pte(spte))
2192 spte &= ~PT_WRITABLE_MASK;
2196 if (pte_access & ACC_WRITE_MASK)
2197 mark_page_dirty(vcpu->kvm, gfn);
2200 mmu_spte_update(sptep, spte);
2202 * If we overwrite a writable spte with a read-only one we
2203 * should flush remote TLBs. Otherwise rmap_write_protect
2204 * will find a read-only spte, even though the writable spte
2205 * might be cached on a CPU's TLB.
2207 if (is_writable_pte(entry) && !is_writable_pte(*sptep))
2208 kvm_flush_remote_tlbs(vcpu->kvm);
2213 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2214 unsigned pt_access, unsigned pte_access,
2215 int user_fault, int write_fault,
2216 int *emulate, int level, gfn_t gfn,
2217 pfn_t pfn, bool speculative,
2220 int was_rmapped = 0;
2223 pgprintk("%s: spte %llx access %x write_fault %d"
2224 " user_fault %d gfn %llx\n",
2225 __func__, *sptep, pt_access,
2226 write_fault, user_fault, gfn);
2228 if (is_rmap_spte(*sptep)) {
2230 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2231 * the parent of the now unreachable PTE.
2233 if (level > PT_PAGE_TABLE_LEVEL &&
2234 !is_large_pte(*sptep)) {
2235 struct kvm_mmu_page *child;
2238 child = page_header(pte & PT64_BASE_ADDR_MASK);
2239 drop_parent_pte(child, sptep);
2240 kvm_flush_remote_tlbs(vcpu->kvm);
2241 } else if (pfn != spte_to_pfn(*sptep)) {
2242 pgprintk("hfn old %llx new %llx\n",
2243 spte_to_pfn(*sptep), pfn);
2244 drop_spte(vcpu->kvm, sptep);
2245 kvm_flush_remote_tlbs(vcpu->kvm);
2250 if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
2251 level, gfn, pfn, speculative, true,
2255 kvm_mmu_flush_tlb(vcpu);
2258 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2259 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2260 is_large_pte(*sptep)? "2MB" : "4kB",
2261 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2263 if (!was_rmapped && is_large_pte(*sptep))
2264 ++vcpu->kvm->stat.lpages;
2266 if (is_shadow_present_pte(*sptep)) {
2267 page_header_update_slot(vcpu->kvm, sptep, gfn);
2269 rmap_count = rmap_add(vcpu, sptep, gfn);
2270 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2271 rmap_recycle(vcpu, sptep, gfn);
2274 kvm_release_pfn_clean(pfn);
2276 vcpu->arch.last_pte_updated = sptep;
2277 vcpu->arch.last_pte_gfn = gfn;
2281 static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
2285 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2288 struct kvm_memory_slot *slot;
2291 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2293 get_page(fault_page);
2294 return page_to_pfn(fault_page);
2297 hva = gfn_to_hva_memslot(slot, gfn);
2299 return hva_to_pfn_atomic(vcpu->kvm, hva);
2302 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2303 struct kvm_mmu_page *sp,
2304 u64 *start, u64 *end)
2306 struct page *pages[PTE_PREFETCH_NUM];
2307 unsigned access = sp->role.access;
2311 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2312 if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK))
2315 ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2319 for (i = 0; i < ret; i++, gfn++, start++)
2320 mmu_set_spte(vcpu, start, ACC_ALL,
2322 sp->role.level, gfn,
2323 page_to_pfn(pages[i]), true, true);
2328 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2329 struct kvm_mmu_page *sp, u64 *sptep)
2331 u64 *spte, *start = NULL;
2334 WARN_ON(!sp->role.direct);
2336 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2339 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2340 if (is_shadow_present_pte(*spte) || spte == sptep) {
2343 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2351 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2353 struct kvm_mmu_page *sp;
2356 * Since it's no accessed bit on EPT, it's no way to
2357 * distinguish between actually accessed translations
2358 * and prefetched, so disable pte prefetch if EPT is
2361 if (!shadow_accessed_mask)
2364 sp = page_header(__pa(sptep));
2365 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2368 __direct_pte_prefetch(vcpu, sp, sptep);
2371 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2372 int map_writable, int level, gfn_t gfn, pfn_t pfn,
2375 struct kvm_shadow_walk_iterator iterator;
2376 struct kvm_mmu_page *sp;
2380 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2381 if (iterator.level == level) {
2382 unsigned pte_access = ACC_ALL;
2384 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, pte_access,
2386 level, gfn, pfn, prefault, map_writable);
2387 direct_pte_prefetch(vcpu, iterator.sptep);
2388 ++vcpu->stat.pf_fixed;
2392 if (!is_shadow_present_pte(*iterator.sptep)) {
2393 u64 base_addr = iterator.addr;
2395 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2396 pseudo_gfn = base_addr >> PAGE_SHIFT;
2397 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2399 1, ACC_ALL, iterator.sptep);
2401 pgprintk("nonpaging_map: ENOMEM\n");
2402 kvm_release_pfn_clean(pfn);
2406 mmu_spte_set(iterator.sptep,
2408 | PT_PRESENT_MASK | PT_WRITABLE_MASK
2409 | shadow_user_mask | shadow_x_mask
2410 | shadow_accessed_mask);
2416 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2420 info.si_signo = SIGBUS;
2422 info.si_code = BUS_MCEERR_AR;
2423 info.si_addr = (void __user *)address;
2424 info.si_addr_lsb = PAGE_SHIFT;
2426 send_sig_info(SIGBUS, &info, tsk);
2429 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn)
2431 kvm_release_pfn_clean(pfn);
2432 if (is_hwpoison_pfn(pfn)) {
2433 kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current);
2440 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2441 gfn_t *gfnp, pfn_t *pfnp, int *levelp)
2445 int level = *levelp;
2448 * Check if it's a transparent hugepage. If this would be an
2449 * hugetlbfs page, level wouldn't be set to
2450 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2453 if (!is_error_pfn(pfn) && !kvm_is_mmio_pfn(pfn) &&
2454 level == PT_PAGE_TABLE_LEVEL &&
2455 PageTransCompound(pfn_to_page(pfn)) &&
2456 !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) {
2459 * mmu_notifier_retry was successful and we hold the
2460 * mmu_lock here, so the pmd can't become splitting
2461 * from under us, and in turn
2462 * __split_huge_page_refcount() can't run from under
2463 * us and we can safely transfer the refcount from
2464 * PG_tail to PG_head as we switch the pfn to tail to
2467 *levelp = level = PT_DIRECTORY_LEVEL;
2468 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2469 VM_BUG_ON((gfn & mask) != (pfn & mask));
2473 kvm_release_pfn_clean(pfn);
2475 if (!get_page_unless_zero(pfn_to_page(pfn)))
2482 static bool mmu_invalid_pfn(pfn_t pfn)
2484 return unlikely(is_invalid_pfn(pfn) || is_noslot_pfn(pfn));
2487 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2488 pfn_t pfn, unsigned access, int *ret_val)
2492 /* The pfn is invalid, report the error! */
2493 if (unlikely(is_invalid_pfn(pfn))) {
2494 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2498 if (unlikely(is_noslot_pfn(pfn))) {
2499 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2509 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2510 gva_t gva, pfn_t *pfn, bool write, bool *writable);
2512 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn,
2519 unsigned long mmu_seq;
2522 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2523 if (likely(!force_pt_level)) {
2524 level = mapping_level(vcpu, gfn);
2526 * This path builds a PAE pagetable - so we can map
2527 * 2mb pages at maximum. Therefore check if the level
2528 * is larger than that.
2530 if (level > PT_DIRECTORY_LEVEL)
2531 level = PT_DIRECTORY_LEVEL;
2533 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2535 level = PT_PAGE_TABLE_LEVEL;
2537 mmu_seq = vcpu->kvm->mmu_notifier_seq;
2540 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
2543 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
2546 spin_lock(&vcpu->kvm->mmu_lock);
2547 if (mmu_notifier_retry(vcpu, mmu_seq))
2549 kvm_mmu_free_some_pages(vcpu);
2550 if (likely(!force_pt_level))
2551 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
2552 r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
2554 spin_unlock(&vcpu->kvm->mmu_lock);
2560 spin_unlock(&vcpu->kvm->mmu_lock);
2561 kvm_release_pfn_clean(pfn);
2566 static void mmu_free_roots(struct kvm_vcpu *vcpu)
2569 struct kvm_mmu_page *sp;
2570 LIST_HEAD(invalid_list);
2572 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2574 spin_lock(&vcpu->kvm->mmu_lock);
2575 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
2576 (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
2577 vcpu->arch.mmu.direct_map)) {
2578 hpa_t root = vcpu->arch.mmu.root_hpa;
2580 sp = page_header(root);
2582 if (!sp->root_count && sp->role.invalid) {
2583 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2584 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2586 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2587 spin_unlock(&vcpu->kvm->mmu_lock);
2590 for (i = 0; i < 4; ++i) {
2591 hpa_t root = vcpu->arch.mmu.pae_root[i];
2594 root &= PT64_BASE_ADDR_MASK;
2595 sp = page_header(root);
2597 if (!sp->root_count && sp->role.invalid)
2598 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2601 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2603 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2604 spin_unlock(&vcpu->kvm->mmu_lock);
2605 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2608 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2612 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2613 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2620 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
2622 struct kvm_mmu_page *sp;
2625 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2626 spin_lock(&vcpu->kvm->mmu_lock);
2627 kvm_mmu_free_some_pages(vcpu);
2628 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
2631 spin_unlock(&vcpu->kvm->mmu_lock);
2632 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
2633 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
2634 for (i = 0; i < 4; ++i) {
2635 hpa_t root = vcpu->arch.mmu.pae_root[i];
2637 ASSERT(!VALID_PAGE(root));
2638 spin_lock(&vcpu->kvm->mmu_lock);
2639 kvm_mmu_free_some_pages(vcpu);
2640 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
2642 PT32_ROOT_LEVEL, 1, ACC_ALL,
2644 root = __pa(sp->spt);
2646 spin_unlock(&vcpu->kvm->mmu_lock);
2647 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
2649 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2656 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
2658 struct kvm_mmu_page *sp;
2663 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
2665 if (mmu_check_root(vcpu, root_gfn))
2669 * Do we shadow a long mode page table? If so we need to
2670 * write-protect the guests page table root.
2672 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2673 hpa_t root = vcpu->arch.mmu.root_hpa;
2675 ASSERT(!VALID_PAGE(root));
2677 spin_lock(&vcpu->kvm->mmu_lock);
2678 kvm_mmu_free_some_pages(vcpu);
2679 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
2681 root = __pa(sp->spt);
2683 spin_unlock(&vcpu->kvm->mmu_lock);
2684 vcpu->arch.mmu.root_hpa = root;
2689 * We shadow a 32 bit page table. This may be a legacy 2-level
2690 * or a PAE 3-level page table. In either case we need to be aware that
2691 * the shadow page table may be a PAE or a long mode page table.
2693 pm_mask = PT_PRESENT_MASK;
2694 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
2695 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
2697 for (i = 0; i < 4; ++i) {
2698 hpa_t root = vcpu->arch.mmu.pae_root[i];
2700 ASSERT(!VALID_PAGE(root));
2701 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
2702 pdptr = kvm_pdptr_read_mmu(vcpu, &vcpu->arch.mmu, i);
2703 if (!is_present_gpte(pdptr)) {
2704 vcpu->arch.mmu.pae_root[i] = 0;
2707 root_gfn = pdptr >> PAGE_SHIFT;
2708 if (mmu_check_root(vcpu, root_gfn))
2711 spin_lock(&vcpu->kvm->mmu_lock);
2712 kvm_mmu_free_some_pages(vcpu);
2713 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
2716 root = __pa(sp->spt);
2718 spin_unlock(&vcpu->kvm->mmu_lock);
2720 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
2722 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2725 * If we shadow a 32 bit page table with a long mode page
2726 * table we enter this path.
2728 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2729 if (vcpu->arch.mmu.lm_root == NULL) {
2731 * The additional page necessary for this is only
2732 * allocated on demand.
2737 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
2738 if (lm_root == NULL)
2741 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
2743 vcpu->arch.mmu.lm_root = lm_root;
2746 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
2752 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
2754 if (vcpu->arch.mmu.direct_map)
2755 return mmu_alloc_direct_roots(vcpu);
2757 return mmu_alloc_shadow_roots(vcpu);
2760 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2763 struct kvm_mmu_page *sp;
2765 if (vcpu->arch.mmu.direct_map)
2768 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2771 vcpu_clear_mmio_info(vcpu, ~0ul);
2772 trace_kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
2773 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2774 hpa_t root = vcpu->arch.mmu.root_hpa;
2775 sp = page_header(root);
2776 mmu_sync_children(vcpu, sp);
2777 trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
2780 for (i = 0; i < 4; ++i) {
2781 hpa_t root = vcpu->arch.mmu.pae_root[i];
2783 if (root && VALID_PAGE(root)) {
2784 root &= PT64_BASE_ADDR_MASK;
2785 sp = page_header(root);
2786 mmu_sync_children(vcpu, sp);
2789 trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
2792 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2794 spin_lock(&vcpu->kvm->mmu_lock);
2795 mmu_sync_roots(vcpu);
2796 spin_unlock(&vcpu->kvm->mmu_lock);
2799 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
2800 u32 access, struct x86_exception *exception)
2803 exception->error_code = 0;
2807 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
2809 struct x86_exception *exception)
2812 exception->error_code = 0;
2813 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access);
2816 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
2817 u32 error_code, bool prefault)
2822 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
2823 r = mmu_topup_memory_caches(vcpu);
2828 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2830 gfn = gva >> PAGE_SHIFT;
2832 return nonpaging_map(vcpu, gva & PAGE_MASK,
2833 error_code & PFERR_WRITE_MASK, gfn, prefault);
2836 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
2838 struct kvm_arch_async_pf arch;
2840 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
2842 arch.direct_map = vcpu->arch.mmu.direct_map;
2843 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
2845 return kvm_setup_async_pf(vcpu, gva, gfn, &arch);
2848 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
2850 if (unlikely(!irqchip_in_kernel(vcpu->kvm) ||
2851 kvm_event_needs_reinjection(vcpu)))
2854 return kvm_x86_ops->interrupt_allowed(vcpu);
2857 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2858 gva_t gva, pfn_t *pfn, bool write, bool *writable)
2862 *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable);
2865 return false; /* *pfn has correct page already */
2867 put_page(pfn_to_page(*pfn));
2869 if (!prefault && can_do_async_pf(vcpu)) {
2870 trace_kvm_try_async_get_page(gva, gfn);
2871 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
2872 trace_kvm_async_pf_doublefault(gva, gfn);
2873 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
2875 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
2879 *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable);
2884 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
2891 gfn_t gfn = gpa >> PAGE_SHIFT;
2892 unsigned long mmu_seq;
2893 int write = error_code & PFERR_WRITE_MASK;
2897 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2899 r = mmu_topup_memory_caches(vcpu);
2903 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2904 if (likely(!force_pt_level)) {
2905 level = mapping_level(vcpu, gfn);
2906 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2908 level = PT_PAGE_TABLE_LEVEL;
2910 mmu_seq = vcpu->kvm->mmu_notifier_seq;
2913 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
2916 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
2919 spin_lock(&vcpu->kvm->mmu_lock);
2920 if (mmu_notifier_retry(vcpu, mmu_seq))
2922 kvm_mmu_free_some_pages(vcpu);
2923 if (likely(!force_pt_level))
2924 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
2925 r = __direct_map(vcpu, gpa, write, map_writable,
2926 level, gfn, pfn, prefault);
2927 spin_unlock(&vcpu->kvm->mmu_lock);
2932 spin_unlock(&vcpu->kvm->mmu_lock);
2933 kvm_release_pfn_clean(pfn);
2937 static void nonpaging_free(struct kvm_vcpu *vcpu)
2939 mmu_free_roots(vcpu);
2942 static int nonpaging_init_context(struct kvm_vcpu *vcpu,
2943 struct kvm_mmu *context)
2945 context->new_cr3 = nonpaging_new_cr3;
2946 context->page_fault = nonpaging_page_fault;
2947 context->gva_to_gpa = nonpaging_gva_to_gpa;
2948 context->free = nonpaging_free;
2949 context->sync_page = nonpaging_sync_page;
2950 context->invlpg = nonpaging_invlpg;
2951 context->update_pte = nonpaging_update_pte;
2952 context->root_level = 0;
2953 context->shadow_root_level = PT32E_ROOT_LEVEL;
2954 context->root_hpa = INVALID_PAGE;
2955 context->direct_map = true;
2956 context->nx = false;
2960 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
2962 ++vcpu->stat.tlb_flush;
2963 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2966 static void paging_new_cr3(struct kvm_vcpu *vcpu)
2968 pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu));
2969 mmu_free_roots(vcpu);
2972 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
2974 return kvm_read_cr3(vcpu);
2977 static void inject_page_fault(struct kvm_vcpu *vcpu,
2978 struct x86_exception *fault)
2980 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
2983 static void paging_free(struct kvm_vcpu *vcpu)
2985 nonpaging_free(vcpu);
2988 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
2992 bit7 = (gpte >> 7) & 1;
2993 return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0;
2997 #include "paging_tmpl.h"
3001 #include "paging_tmpl.h"
3004 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3005 struct kvm_mmu *context,
3008 int maxphyaddr = cpuid_maxphyaddr(vcpu);
3009 u64 exb_bit_rsvd = 0;
3012 exb_bit_rsvd = rsvd_bits(63, 63);
3014 case PT32_ROOT_LEVEL:
3015 /* no rsvd bits for 2 level 4K page table entries */
3016 context->rsvd_bits_mask[0][1] = 0;
3017 context->rsvd_bits_mask[0][0] = 0;
3018 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3020 if (!is_pse(vcpu)) {
3021 context->rsvd_bits_mask[1][1] = 0;
3025 if (is_cpuid_PSE36())
3026 /* 36bits PSE 4MB page */
3027 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3029 /* 32 bits PSE 4MB page */
3030 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3032 case PT32E_ROOT_LEVEL:
3033 context->rsvd_bits_mask[0][2] =
3034 rsvd_bits(maxphyaddr, 63) |
3035 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
3036 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3037 rsvd_bits(maxphyaddr, 62); /* PDE */
3038 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3039 rsvd_bits(maxphyaddr, 62); /* PTE */
3040 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3041 rsvd_bits(maxphyaddr, 62) |
3042 rsvd_bits(13, 20); /* large page */
3043 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3045 case PT64_ROOT_LEVEL:
3046 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3047 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3048 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3049 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3050 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3051 rsvd_bits(maxphyaddr, 51);
3052 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3053 rsvd_bits(maxphyaddr, 51);
3054 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3055 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3056 rsvd_bits(maxphyaddr, 51) |
3058 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3059 rsvd_bits(maxphyaddr, 51) |
3060 rsvd_bits(13, 20); /* large page */
3061 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3066 static int paging64_init_context_common(struct kvm_vcpu *vcpu,
3067 struct kvm_mmu *context,
3070 context->nx = is_nx(vcpu);
3072 reset_rsvds_bits_mask(vcpu, context, level);
3074 ASSERT(is_pae(vcpu));
3075 context->new_cr3 = paging_new_cr3;
3076 context->page_fault = paging64_page_fault;
3077 context->gva_to_gpa = paging64_gva_to_gpa;
3078 context->sync_page = paging64_sync_page;
3079 context->invlpg = paging64_invlpg;
3080 context->update_pte = paging64_update_pte;
3081 context->free = paging_free;
3082 context->root_level = level;
3083 context->shadow_root_level = level;
3084 context->root_hpa = INVALID_PAGE;
3085 context->direct_map = false;
3089 static int paging64_init_context(struct kvm_vcpu *vcpu,
3090 struct kvm_mmu *context)
3092 return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
3095 static int paging32_init_context(struct kvm_vcpu *vcpu,
3096 struct kvm_mmu *context)
3098 context->nx = false;
3100 reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
3102 context->new_cr3 = paging_new_cr3;
3103 context->page_fault = paging32_page_fault;
3104 context->gva_to_gpa = paging32_gva_to_gpa;
3105 context->free = paging_free;
3106 context->sync_page = paging32_sync_page;
3107 context->invlpg = paging32_invlpg;
3108 context->update_pte = paging32_update_pte;
3109 context->root_level = PT32_ROOT_LEVEL;
3110 context->shadow_root_level = PT32E_ROOT_LEVEL;
3111 context->root_hpa = INVALID_PAGE;
3112 context->direct_map = false;
3116 static int paging32E_init_context(struct kvm_vcpu *vcpu,
3117 struct kvm_mmu *context)
3119 return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
3122 static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
3124 struct kvm_mmu *context = vcpu->arch.walk_mmu;
3126 context->base_role.word = 0;
3127 context->new_cr3 = nonpaging_new_cr3;
3128 context->page_fault = tdp_page_fault;
3129 context->free = nonpaging_free;
3130 context->sync_page = nonpaging_sync_page;
3131 context->invlpg = nonpaging_invlpg;
3132 context->update_pte = nonpaging_update_pte;
3133 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3134 context->root_hpa = INVALID_PAGE;
3135 context->direct_map = true;
3136 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
3137 context->get_cr3 = get_cr3;
3138 context->inject_page_fault = kvm_inject_page_fault;
3139 context->nx = is_nx(vcpu);
3141 if (!is_paging(vcpu)) {
3142 context->nx = false;
3143 context->gva_to_gpa = nonpaging_gva_to_gpa;
3144 context->root_level = 0;
3145 } else if (is_long_mode(vcpu)) {
3146 context->nx = is_nx(vcpu);
3147 reset_rsvds_bits_mask(vcpu, context, PT64_ROOT_LEVEL);
3148 context->gva_to_gpa = paging64_gva_to_gpa;
3149 context->root_level = PT64_ROOT_LEVEL;
3150 } else if (is_pae(vcpu)) {
3151 context->nx = is_nx(vcpu);
3152 reset_rsvds_bits_mask(vcpu, context, PT32E_ROOT_LEVEL);
3153 context->gva_to_gpa = paging64_gva_to_gpa;
3154 context->root_level = PT32E_ROOT_LEVEL;
3156 context->nx = false;
3157 reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
3158 context->gva_to_gpa = paging32_gva_to_gpa;
3159 context->root_level = PT32_ROOT_LEVEL;
3165 int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3168 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3170 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3172 if (!is_paging(vcpu))
3173 r = nonpaging_init_context(vcpu, context);
3174 else if (is_long_mode(vcpu))
3175 r = paging64_init_context(vcpu, context);
3176 else if (is_pae(vcpu))
3177 r = paging32E_init_context(vcpu, context);
3179 r = paging32_init_context(vcpu, context);
3181 vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3182 vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu);
3183 vcpu->arch.mmu.base_role.smep_andnot_wp
3184 = smep && !is_write_protection(vcpu);
3188 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
3190 static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
3192 int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu);
3194 vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3;
3195 vcpu->arch.walk_mmu->get_cr3 = get_cr3;
3196 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
3201 static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
3203 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
3205 g_context->get_cr3 = get_cr3;
3206 g_context->inject_page_fault = kvm_inject_page_fault;
3209 * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3210 * translation of l2_gpa to l1_gpa addresses is done using the
3211 * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3212 * functions between mmu and nested_mmu are swapped.
3214 if (!is_paging(vcpu)) {
3215 g_context->nx = false;
3216 g_context->root_level = 0;
3217 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
3218 } else if (is_long_mode(vcpu)) {
3219 g_context->nx = is_nx(vcpu);
3220 reset_rsvds_bits_mask(vcpu, g_context, PT64_ROOT_LEVEL);
3221 g_context->root_level = PT64_ROOT_LEVEL;
3222 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3223 } else if (is_pae(vcpu)) {
3224 g_context->nx = is_nx(vcpu);
3225 reset_rsvds_bits_mask(vcpu, g_context, PT32E_ROOT_LEVEL);
3226 g_context->root_level = PT32E_ROOT_LEVEL;
3227 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3229 g_context->nx = false;
3230 reset_rsvds_bits_mask(vcpu, g_context, PT32_ROOT_LEVEL);
3231 g_context->root_level = PT32_ROOT_LEVEL;
3232 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
3238 static int init_kvm_mmu(struct kvm_vcpu *vcpu)
3240 if (mmu_is_nested(vcpu))
3241 return init_kvm_nested_mmu(vcpu);
3242 else if (tdp_enabled)
3243 return init_kvm_tdp_mmu(vcpu);
3245 return init_kvm_softmmu(vcpu);
3248 static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
3251 if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
3252 /* mmu.free() should set root_hpa = INVALID_PAGE */
3253 vcpu->arch.mmu.free(vcpu);
3256 int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
3258 destroy_kvm_mmu(vcpu);
3259 return init_kvm_mmu(vcpu);
3261 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
3263 int kvm_mmu_load(struct kvm_vcpu *vcpu)
3267 r = mmu_topup_memory_caches(vcpu);
3270 r = mmu_alloc_roots(vcpu);
3271 spin_lock(&vcpu->kvm->mmu_lock);
3272 mmu_sync_roots(vcpu);
3273 spin_unlock(&vcpu->kvm->mmu_lock);
3276 /* set_cr3() should ensure TLB has been flushed */
3277 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
3281 EXPORT_SYMBOL_GPL(kvm_mmu_load);
3283 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
3285 mmu_free_roots(vcpu);
3287 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
3289 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
3290 struct kvm_mmu_page *sp, u64 *spte,
3293 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
3294 ++vcpu->kvm->stat.mmu_pde_zapped;
3298 ++vcpu->kvm->stat.mmu_pte_updated;
3299 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
3302 static bool need_remote_flush(u64 old, u64 new)
3304 if (!is_shadow_present_pte(old))
3306 if (!is_shadow_present_pte(new))
3308 if ((old ^ new) & PT64_BASE_ADDR_MASK)
3310 old ^= PT64_NX_MASK;
3311 new ^= PT64_NX_MASK;
3312 return (old & ~new & PT64_PERM_MASK) != 0;
3315 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
3316 bool remote_flush, bool local_flush)
3322 kvm_flush_remote_tlbs(vcpu->kvm);
3323 else if (local_flush)
3324 kvm_mmu_flush_tlb(vcpu);
3327 static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
3329 u64 *spte = vcpu->arch.last_pte_updated;
3331 return !!(spte && (*spte & shadow_accessed_mask));
3334 static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn)
3336 u64 *spte = vcpu->arch.last_pte_updated;
3339 && vcpu->arch.last_pte_gfn == gfn
3340 && shadow_accessed_mask
3341 && !(*spte & shadow_accessed_mask)
3342 && is_shadow_present_pte(*spte))
3343 set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
3346 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
3347 const u8 *new, int bytes,
3348 bool guest_initiated)
3350 gfn_t gfn = gpa >> PAGE_SHIFT;
3351 union kvm_mmu_page_role mask = { .word = 0 };
3352 struct kvm_mmu_page *sp;
3353 struct hlist_node *node;
3354 LIST_HEAD(invalid_list);
3355 u64 entry, gentry, *spte;
3356 unsigned pte_size, page_offset, misaligned, quadrant, offset;
3357 int level, npte, invlpg_counter, r, flooded = 0;
3358 bool remote_flush, local_flush, zap_page;
3361 * If we don't have indirect shadow pages, it means no page is
3362 * write-protected, so we can exit simply.
3364 if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
3367 zap_page = remote_flush = local_flush = false;
3368 offset = offset_in_page(gpa);
3370 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
3372 invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter);
3375 * Assume that the pte write on a page table of the same type
3376 * as the current vcpu paging mode since we update the sptes only
3377 * when they have the same mode.
3379 if ((is_pae(vcpu) && bytes == 4) || !new) {
3380 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3385 r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8));
3388 new = (const u8 *)&gentry;
3393 gentry = *(const u32 *)new;
3396 gentry = *(const u64 *)new;
3403 spin_lock(&vcpu->kvm->mmu_lock);
3404 if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter)
3406 kvm_mmu_free_some_pages(vcpu);
3407 ++vcpu->kvm->stat.mmu_pte_write;
3408 trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
3409 if (guest_initiated) {
3410 kvm_mmu_access_page(vcpu, gfn);
3411 if (gfn == vcpu->arch.last_pt_write_gfn
3412 && !last_updated_pte_accessed(vcpu)) {
3413 ++vcpu->arch.last_pt_write_count;
3414 if (vcpu->arch.last_pt_write_count >= 3)
3417 vcpu->arch.last_pt_write_gfn = gfn;
3418 vcpu->arch.last_pt_write_count = 1;
3419 vcpu->arch.last_pte_updated = NULL;
3423 mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
3424 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) {
3425 pte_size = sp->role.cr4_pae ? 8 : 4;
3426 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
3427 misaligned |= bytes < 4;
3428 if (misaligned || flooded) {
3430 * Misaligned accesses are too much trouble to fix
3431 * up; also, they usually indicate a page is not used
3434 * If we're seeing too many writes to a page,
3435 * it may no longer be a page table, or we may be
3436 * forking, in which case it is better to unmap the
3439 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3440 gpa, bytes, sp->role.word);
3441 zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3443 ++vcpu->kvm->stat.mmu_flooded;
3446 page_offset = offset;
3447 level = sp->role.level;
3449 if (!sp->role.cr4_pae) {
3450 page_offset <<= 1; /* 32->64 */
3452 * A 32-bit pde maps 4MB while the shadow pdes map
3453 * only 2MB. So we need to double the offset again
3454 * and zap two pdes instead of one.
3456 if (level == PT32_ROOT_LEVEL) {
3457 page_offset &= ~7; /* kill rounding error */
3461 quadrant = page_offset >> PAGE_SHIFT;
3462 page_offset &= ~PAGE_MASK;
3463 if (quadrant != sp->role.quadrant)
3467 spte = &sp->spt[page_offset / sizeof(*spte)];
3470 mmu_page_zap_pte(vcpu->kvm, sp, spte);
3472 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
3474 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
3475 if (!remote_flush && need_remote_flush(entry, *spte))
3476 remote_flush = true;
3480 mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
3481 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3482 trace_kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
3483 spin_unlock(&vcpu->kvm->mmu_lock);
3486 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
3491 if (vcpu->arch.mmu.direct_map)
3494 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
3496 spin_lock(&vcpu->kvm->mmu_lock);
3497 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
3498 spin_unlock(&vcpu->kvm->mmu_lock);
3501 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
3503 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
3505 LIST_HEAD(invalid_list);
3507 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES &&
3508 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
3509 struct kvm_mmu_page *sp;
3511 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
3512 struct kvm_mmu_page, link);
3513 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
3514 ++vcpu->kvm->stat.mmu_recycled;
3516 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3519 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
3520 void *insn, int insn_len)
3523 enum emulation_result er;
3525 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
3534 r = mmu_topup_memory_caches(vcpu);
3538 er = x86_emulate_instruction(vcpu, cr2, 0, insn, insn_len);
3543 case EMULATE_DO_MMIO:
3544 ++vcpu->stat.mmio_exits;
3554 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
3556 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
3558 vcpu->arch.mmu.invlpg(vcpu, gva);
3559 kvm_mmu_flush_tlb(vcpu);
3560 ++vcpu->stat.invlpg;
3562 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
3564 void kvm_enable_tdp(void)
3568 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
3570 void kvm_disable_tdp(void)
3572 tdp_enabled = false;
3574 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
3576 static void free_mmu_pages(struct kvm_vcpu *vcpu)
3578 free_page((unsigned long)vcpu->arch.mmu.pae_root);
3579 if (vcpu->arch.mmu.lm_root != NULL)
3580 free_page((unsigned long)vcpu->arch.mmu.lm_root);
3583 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
3591 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
3592 * Therefore we need to allocate shadow page tables in the first
3593 * 4GB of memory, which happens to fit the DMA32 zone.
3595 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
3599 vcpu->arch.mmu.pae_root = page_address(page);
3600 for (i = 0; i < 4; ++i)
3601 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
3606 int kvm_mmu_create(struct kvm_vcpu *vcpu)
3609 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3611 return alloc_mmu_pages(vcpu);
3614 int kvm_mmu_setup(struct kvm_vcpu *vcpu)
3617 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3619 return init_kvm_mmu(vcpu);
3622 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
3624 struct kvm_mmu_page *sp;
3626 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
3630 if (!test_bit(slot, sp->slot_bitmap))
3634 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3635 if (!is_shadow_present_pte(pt[i]) ||
3636 !is_last_spte(pt[i], sp->role.level))
3639 if (is_large_pte(pt[i])) {
3640 drop_spte(kvm, &pt[i]);
3646 if (is_writable_pte(pt[i]))
3647 mmu_spte_update(&pt[i],
3648 pt[i] & ~PT_WRITABLE_MASK);
3651 kvm_flush_remote_tlbs(kvm);
3654 void kvm_mmu_zap_all(struct kvm *kvm)
3656 struct kvm_mmu_page *sp, *node;
3657 LIST_HEAD(invalid_list);
3659 spin_lock(&kvm->mmu_lock);
3661 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
3662 if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
3665 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3666 spin_unlock(&kvm->mmu_lock);
3669 static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm,
3670 struct list_head *invalid_list)
3672 struct kvm_mmu_page *page;
3674 page = container_of(kvm->arch.active_mmu_pages.prev,
3675 struct kvm_mmu_page, link);
3676 return kvm_mmu_prepare_zap_page(kvm, page, invalid_list);
3679 static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
3682 struct kvm *kvm_freed = NULL;
3683 int nr_to_scan = sc->nr_to_scan;
3685 if (nr_to_scan == 0)
3688 raw_spin_lock(&kvm_lock);
3690 list_for_each_entry(kvm, &vm_list, vm_list) {
3691 int idx, freed_pages;
3692 LIST_HEAD(invalid_list);
3694 idx = srcu_read_lock(&kvm->srcu);
3695 spin_lock(&kvm->mmu_lock);
3696 if (!kvm_freed && nr_to_scan > 0 &&
3697 kvm->arch.n_used_mmu_pages > 0) {
3698 freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm,
3704 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3705 spin_unlock(&kvm->mmu_lock);
3706 srcu_read_unlock(&kvm->srcu, idx);
3709 list_move_tail(&kvm_freed->vm_list, &vm_list);
3711 raw_spin_unlock(&kvm_lock);
3714 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
3717 static struct shrinker mmu_shrinker = {
3718 .shrink = mmu_shrink,
3719 .seeks = DEFAULT_SEEKS * 10,
3722 static void mmu_destroy_caches(void)
3724 if (pte_list_desc_cache)
3725 kmem_cache_destroy(pte_list_desc_cache);
3726 if (mmu_page_header_cache)
3727 kmem_cache_destroy(mmu_page_header_cache);
3730 int kvm_mmu_module_init(void)
3732 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
3733 sizeof(struct pte_list_desc),
3735 if (!pte_list_desc_cache)
3738 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
3739 sizeof(struct kvm_mmu_page),
3741 if (!mmu_page_header_cache)
3744 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0))
3747 register_shrinker(&mmu_shrinker);
3752 mmu_destroy_caches();
3757 * Caculate mmu pages needed for kvm.
3759 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
3762 unsigned int nr_mmu_pages;
3763 unsigned int nr_pages = 0;
3764 struct kvm_memslots *slots;
3766 slots = kvm_memslots(kvm);
3768 for (i = 0; i < slots->nmemslots; i++)
3769 nr_pages += slots->memslots[i].npages;
3771 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
3772 nr_mmu_pages = max(nr_mmu_pages,
3773 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
3775 return nr_mmu_pages;
3778 static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3781 if (len > buffer->len)
3786 static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3791 ret = pv_mmu_peek_buffer(buffer, len);
3796 buffer->processed += len;
3800 static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
3801 gpa_t addr, gpa_t value)
3806 if (!is_long_mode(vcpu) && !is_pae(vcpu))
3809 r = mmu_topup_memory_caches(vcpu);
3813 if (!emulator_write_phys(vcpu, addr, &value, bytes))
3819 static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3821 (void)kvm_set_cr3(vcpu, kvm_read_cr3(vcpu));
3825 static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
3827 spin_lock(&vcpu->kvm->mmu_lock);
3828 mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
3829 spin_unlock(&vcpu->kvm->mmu_lock);
3833 static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
3834 struct kvm_pv_mmu_op_buffer *buffer)
3836 struct kvm_mmu_op_header *header;
3838 header = pv_mmu_peek_buffer(buffer, sizeof *header);
3841 switch (header->op) {
3842 case KVM_MMU_OP_WRITE_PTE: {
3843 struct kvm_mmu_op_write_pte *wpte;
3845 wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
3848 return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
3851 case KVM_MMU_OP_FLUSH_TLB: {
3852 struct kvm_mmu_op_flush_tlb *ftlb;
3854 ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
3857 return kvm_pv_mmu_flush_tlb(vcpu);
3859 case KVM_MMU_OP_RELEASE_PT: {
3860 struct kvm_mmu_op_release_pt *rpt;
3862 rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
3865 return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
3871 int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
3872 gpa_t addr, unsigned long *ret)
3875 struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
3877 buffer->ptr = buffer->buf;
3878 buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
3879 buffer->processed = 0;
3881 r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
3885 while (buffer->len) {
3886 r = kvm_pv_mmu_op_one(vcpu, buffer);
3895 *ret = buffer->processed;
3899 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
3901 struct kvm_shadow_walk_iterator iterator;
3905 walk_shadow_page_lockless_begin(vcpu);
3906 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
3907 sptes[iterator.level-1] = spte;
3909 if (!is_shadow_present_pte(spte))
3912 walk_shadow_page_lockless_end(vcpu);
3916 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
3918 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
3922 destroy_kvm_mmu(vcpu);
3923 free_mmu_pages(vcpu);
3924 mmu_free_memory_caches(vcpu);
3927 #ifdef CONFIG_KVM_MMU_AUDIT
3928 #include "mmu_audit.c"
3930 static void mmu_audit_disable(void) { }
3933 void kvm_mmu_module_exit(void)
3935 mmu_destroy_caches();
3936 percpu_counter_destroy(&kvm_total_used_mmu_pages);
3937 unregister_shrinker(&mmu_shrinker);
3938 mmu_audit_disable();